Revision 172:7d866c31b3c5, committed 2017-08-31

Comitter:

AnnaBridge

Date:

Thu Aug 31 17:27:04 2017 +0100

Parent:

171:89b338f31ef1

Child:

173:e131a1973e81

Commit message:

This updates the lib to the mbed lib v 150

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,94 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    .text
+    .global __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+__v7_all_cache:
+        .arm
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    .END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,97 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    SECTION `.text`:CODE:NOROOT(2)
+    arm 
+    PUBLIC __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+
+__v7_all_cache:
+
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+ 

--- a/hal/flash_api.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/hal/flash_api.h	Thu Aug 31 17:27:04 2017 +0100
@@ -98,7 +98,6 @@
 /** Get page size
  *
  * @param obj The flash object
- * @param address The page starting address
  * @return The size of a page
  */
 uint32_t flash_get_page_size(const flash_t *obj);

--- a/hal/i2c_api.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/hal/i2c_api.h	Thu Aug 31 17:27:04 2017 +0100
@@ -156,6 +156,7 @@
 
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive
  *  @return non-zero if a value is available
  */
 void i2c_slave_mode(i2c_t *obj, int enable_slave);
@@ -169,12 +170,16 @@
 
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
  *  @return non-zero if a value is available
  */
 int  i2c_slave_read(i2c_t *obj, char *data, int length);
 
 /** Configure I2C as slave or master.
  *  @param obj The I2C object
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to write
  *  @return non-zero if a value is available
  */
 int  i2c_slave_write(i2c_t *obj, const char *data, int length);
@@ -208,6 +213,7 @@
  *  @param address   The address to be set - 7bit or 9bit
  *  @param stop      If true, stop will be generated after the transfer is done
  *  @param handler   The I2C IRQ handler to be set
+ *  @param event     Event mask for the transfer. See \ref hal_I2CEvents
  *  @param hint      DMA hint usage
  */
 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);

--- a/mbed.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/mbed.h	Thu Aug 31 17:27:04 2017 +0100
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 149
+#define MBED_LIBRARY_VERSION 150
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
 #define MBED_MINOR_VERSION 5
-#define MBED_PATCH_VERSION 5
+#define MBED_PATCH_VERSION 6
 
 #else
 // mbed 2

--- a/platform/mbed_critical.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/platform/mbed_critical.c	Thu Aug 31 17:27:04 2017 +0100
@@ -23,12 +23,6 @@
 #include "platform/mbed_assert.h"
 #include "platform/mbed_toolchain.h"
 
-#if !defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS)
-#define EXCLUSIVE_ACCESS 1
-#else
-#define EXCLUSIVE_ACCESS 0
-#endif
-
 static volatile uint32_t interrupt_enable_counter = 0;
 static volatile bool critical_interrupts_disabled = false;
 
@@ -107,7 +101,7 @@
     }
 }
 
-#if EXCLUSIVE_ACCESS
+#if __EXCLUSIVE_ACCESS
 
 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
 #if defined (__CC_ARM) 

--- a/platform/mbed_retarget.cpp	Wed Aug 16 18:27:13 2017 +0100
+++ b/platform/mbed_retarget.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -228,10 +228,10 @@
 
     FileHandle *res = NULL;
 
-    /* FILENAME: ":0x12345678" describes a FileHandle* */
+    /* FILENAME: ":(pointer)" describes a FileHandle* */
     if (name[0] == ':') {
         void *p;
-        std::sscanf(name, ":%p", &p);
+        memcpy(&p, name + 1, sizeof(p));
         res = (FileHandle*)p;
 
     /* FILENAME: "/file_system/file_name" */
@@ -682,11 +682,11 @@
 extern "C" int errno;
 
 // Dynamic memory allocation related syscall.
-#if defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NUMAKER_PFM_M453)
+#if defined(TARGET_NUVOTON)
 // Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
 // __wrap__sbrk() is implemented in:
-// TARGET_NUMAKER_PFM_NUC472    hal/targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/retarget.c
-// TARGET_NUMAKER_PFM_M453      hal/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
+// TARGET_NUMAKER_PFM_NUC472    targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c
+// TARGET_NUMAKER_PFM_M453      targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/m451_retarget.c
 extern "C" void *__wrap__sbrk(int incr);
 extern "C" caddr_t _sbrk(int incr) {
     return (caddr_t) __wrap__sbrk(incr);
@@ -826,8 +826,12 @@
  */
 std::FILE *mbed_fdopen(FileHandle *fh, const char *mode)
 {
-    char buf[12]; /* :0x12345678 + null byte */
-    std::sprintf(buf, ":%p", fh);
+    // This is to avoid scanf(buf, ":%.4s", fh) and the bloat it brings.
+    char buf[1 + sizeof(fh)]; /* :(pointer) */
+    MBED_STATIC_ASSERT(sizeof(buf) == 5, "Pointers should be 4 bytes.");
+    buf[0] = ':';
+    memcpy(buf + 1, &fh, sizeof(fh));
+
     std::FILE *stream = std::fopen(buf, mode);
     /* newlib-nano doesn't appear to ever call _isatty itself, so
      * happily fully buffers an interactive stream. Deal with that here.
@@ -978,72 +982,3 @@
         free(ptr);
     }
 }
-
-#if defined(MBED_CONF_RTOS_PRESENT) && defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
-
-static const char* error_msg(int32_t status)
-{
-    switch (status) {
-    case osError:
-        return "Unspecified RTOS error";
-    case osErrorTimeout:
-        return "Operation not completed within the timeout period";
-    case osErrorResource:
-        return "Resource not available";
-    case osErrorParameter:
-        return "Parameter error";
-    case osErrorNoMemory:
-        return "System is out of memory";
-    case osErrorISR:
-        return "Not allowed in ISR context";
-    default:
-        return "Unknown";
-    }
-}
-
-extern "C" void EvrRtxKernelError (int32_t status)
-{
-    error("Kernel error %i: %s\r\n", status, error_msg(status));
-}
-
-extern "C" void EvrRtxThreadError (osThreadId_t thread_id, int32_t status)
-{
-    error("Thread %p error %i: %s\r\n", thread_id, status, error_msg(status));
-}
-
-extern "C" void EvrRtxTimerError (osTimerId_t timer_id, int32_t status)
-{
-    error("Timer %p error %i: %s\r\n", timer_id, status, error_msg(status));
-}
-
-extern "C" void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status)
-{
-    error("Event %p error %i: %s\r\n", ef_id, status, error_msg(status));
-}
-
-extern "C" void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status)
-{
-    error("Mutex %p error %i: %s\r\n", mutex_id, status, error_msg(status));
-}
-
-extern "C" void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status)
-{
-    // Ignore semaphore overflow, the count will saturate with a returned error
-    if (status == osRtxErrorSemaphoreCountLimit) {
-        return;
-    }
-
-    error("Semaphore %p error %i\r\n", semaphore_id, status);
-}
-
-extern "C" void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status)
-{
-    error("Memory Pool %p error %i\r\n", mp_id, status);
-}
-
-extern "C" void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status)
-{
-    error("Message Queue %p error %i\r\n", mq_id, status);
-}
-
-#endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -131,13 +131,17 @@
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
-    for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
-        char in = spi_master_write(obj, out);
-        if (i < rx_length) {
-            rx_buffer[i] = in;
-        }
-    }
+    // Default write is done in each and every call, in future can create HAL API instead
+    DSPI_SetDummyData(spi_address[obj->spi.instance], write_fill);
+
+    DSPI_MasterTransferBlocking(spi_address[obj->spi.instance], &(dspi_transfer_t){
+          .txData = (uint8_t *)tx_buffer,
+          .rxData = (uint8_t *)rx_buffer,
+          .dataSize = total,
+          .configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
+    });
+
+    DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
 
     return total;
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/analogout_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/analogout_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -40,6 +40,8 @@
     DAC_Init(dac_bases[obj->dac], &dac_config);
 
     DAC_SetBufferValue(dac_bases[obj->dac], 0, 0);
+
+    DAC_Enable(dac_bases[obj->dac], true);
 }
 
 void analogout_free(dac_t *obj)

--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -115,7 +115,7 @@
     LED1 = PD_2,
     LED2 = PD_3,
     LED3 = PD_7,
-    LED4 = D0,  // No real LED. Just for passing ATS.
+    LED4 = LED1,    // No real LED. Just for passing ATS.
     LED_RED = LED2,
     LED_GREEN = LED3,
     LED_BLUE = LED1,

--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c	Thu Aug 31 17:27:04 2017 +0100
@@ -16,14 +16,6 @@
 
 #include "analogin_api.h"
 
-// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
-#if defined(__CC_ARM) || defined(__GNUC__)
-void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
-#elif defined(__ICCARM__)
-    // FIXME: How to achieve it in IAR?
-#endif
-
-
 void mbed_sdk_init(void)
 {
     // NOTE: Support singleton semantics to be called from other init functions
@@ -75,8 +67,3 @@
     /* Lock protected registers */
     SYS_LockReg();
 }
-
-void mbed_sdk_init_forced(void)
-{
-    mbed_sdk_init();
-}

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -9,7 +9,7 @@
 define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
 define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM_end__   = 0x20008000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20008000 - 1;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x800;
 define symbol __ICFEDIT_size_heap__   = 0x4000;

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c	Thu Aug 31 17:27:04 2017 +0100
@@ -61,12 +61,11 @@
 extern uint32_t __bss_end__;
 
 extern void uvisor_init(void);
-//#if defined(TOOLCHAIN_GCC_ARM)
-//extern void _start(void);
-//#endif
-extern void software_init_hook(void) __attribute__((weak));
-extern void __libc_init_array(void);
-extern int main(void);
+#if defined(TOOLCHAIN_GCC_ARM)
+extern void _start(void);
+#else
+#error("For GCC toolchain, only support GNU ARM Embedded")
+#endif
 #endif
 
 /* Default empty handler */
@@ -271,14 +270,15 @@
     /* HXT Crystal Type Select: INV */
     CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
     
-    /* Enable register write-protection function */
-    SYS_LockReg();
-    
     /**
-     * Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
+     * NOTE 1: Unlock is required for perhaps some register access in SystemInit().
+     * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
      */
     SystemInit();
     
+    /* Enable register write-protection function */
+    SYS_LockReg();
+
 #if defined(__CC_ARM)
     __main();
     
@@ -306,19 +306,8 @@
         }
     }
     
-    //uvisor_init();
+    _start();
     
-    if (software_init_hook) {
-        /**
-         * Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
-         * Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
-         */
-        software_init_hook();
-    }
-    else {
-        __libc_init_array();
-        main();
-    }
 #endif
 
     /* Infinite loop */

--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -52,23 +52,23 @@
 
 #define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
 
-#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
-#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0
 #endif
 
-#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
-#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
 #endif
 static PinName gpio_irq_debounce_arr[] = {
-    MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+    MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
 };
 
-#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
 #endif
 
-#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
 #endif
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
@@ -88,15 +88,16 @@
     obj->irq_id = id;
 
     GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
     //gpio_set(pin);
     
     {
-#if MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
+#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
         // Suppress compiler warning
         (void) gpio_irq_debounce_arr;
 
         // Configure de-bounce clock source and sampling cycle time
-        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
         GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
 #else
         // Enable de-bounce if the pin is in the de-bounce enable list
@@ -113,7 +114,7 @@
             if (pin_index == pin_index_debunce &&
                 port_index == port_index_debounce) {
                 // Configure de-bounce clock source and sampling cycle time
-                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
                 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 break;
             }

--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c	Thu Aug 31 17:27:04 2017 +0100
@@ -138,7 +138,7 @@
         while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
 
         // Add power-down compensation
-        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
     }
     while (0);
 }

--- a/targets/TARGET_NUVOTON/TARGET_M451/mbed_lib.json	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-{
-    "name": "M451",
-    "config": {
-        "gpio-irq-debounce-enable": {
-            "help": "Enable GPIO IRQ debounce",
-            "value": 0
-        },
-        "gpio-irq-debounce-enable-list": {
-            "help": "Comma separated pin list to enable GPIO IRQ debounce",
-            "value": "NC"
-        },
-        "gpio-irq-debounce-clock-source": {
-            "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
-            "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
-        },
-
-        "gpio-irq-debounce-sample-rate": {
-            "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
-            "value": "GPIO_DBCTL_DBCLKSEL_16"
-        }
-    }
-}

--- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -26,31 +26,33 @@
 
 #define YEAR0       1900
 //#define EPOCH_YR    1970
-static int rtc_inited = 0;
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
 void rtc_init(void)
 {
-    if (rtc_inited) {
+    if (rtc_isenabled()) {
         return;
     }
-    rtc_inited = 1;
-    
-    // Enable IP clock
-    CLK_EnableModuleClock(rtc_modinit.clkidx);
     
     RTC_Open(NULL);
 }
 
 void rtc_free(void)
 {
-    // FIXME
+    // N/A
 }
 
 int rtc_isenabled(void)
 {
-    return rtc_inited;
+    // NOTE: To access (RTC) registers, clock must be enabled first.
+    if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
+        // Enable IP clock
+        CLK_EnableModuleClock(rtc_modinit.clkidx);
+    }
+    
+    // NOTE: Check RTC Init Active flag to support crossing reset cycle.
+    return  !! (RTC->INIT & RTC_INIT_ACTIVE_Msk);
 }
 
 /*
@@ -68,7 +70,9 @@
 
 time_t rtc_read(void)
 {
-    if (! rtc_inited) {
+    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+    if (! rtc_isenabled()) {
         rtc_init();
     }
     
@@ -94,7 +98,7 @@
 
 void rtc_write(time_t t)
 {
-    if (! rtc_inited) {
+    if (! rtc_isenabled()) {
         rtc_init();
     }
     

--- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -269,7 +269,11 @@
     // Flush Tx FIFO. Otherwise, output data may get lost on this change.
     while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
     
-    // TODO: Assert for not supported parity and data bits
+    // Sanity check arguments    
+    MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+    
     obj->serial.databits = data_bits;
     obj->serial.parity = parity;
     obj->serial.stopbits = stop_bits;

--- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -573,7 +573,7 @@
     // Receive Time-Out
     if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
         spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
-        //event |= SPI_EVENT_ERROR;
+        // Not using this IF. Just clear it.
     }
     // Transmit FIFO Under-Run
     if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,140 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name 
+//       which encodes module base address and module index/subindex.
+#define NU_MODSUBINDEX_Pos              0
+#define NU_MODSUBINDEX_Msk              (0x1Ful << NU_MODSUBINDEX_Pos)
+#define NU_MODINDEX_Pos                 20
+#define NU_MODINDEX_Msk                 (0xFul << NU_MODINDEX_Pos)
+
+#define NU_MODNAME(MODBASE, INDEX, SUBINDEX)    ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
+#define NU_MODBASE(MODNAME)                     ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
+#define NU_MODINDEX(MODNAME)                    (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
+#define NU_MODSUBINDEX(MODNAME)                 (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
+
+#if 0
+typedef enum {
+    GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
+    GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
+    GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
+    GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
+    GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
+    GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0),
+    GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0),
+    GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0)
+} GPIOName;
+#endif
+
+typedef enum {
+    ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0),
+    ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1),
+    ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2),
+    ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3),
+    ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4),
+    ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5),
+    ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6),
+    ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7),
+    ADC_0_8 = (int) NU_MODNAME(EADC_BASE, 0, 8),
+    ADC_0_9 = (int) NU_MODNAME(EADC_BASE, 0, 9),
+    ADC_0_10 = (int) NU_MODNAME(EADC_BASE, 0, 10),
+    ADC_0_11 = (int) NU_MODNAME(EADC_BASE, 0, 11),
+    ADC_0_12 = (int) NU_MODNAME(EADC_BASE, 0, 12),
+    ADC_0_13 = (int) NU_MODNAME(EADC_BASE, 0, 13),
+    ADC_0_14 = (int) NU_MODNAME(EADC_BASE, 0, 14),
+    ADC_0_15 = (int) NU_MODNAME(EADC_BASE, 0, 15)
+} ADCName;
+
+typedef enum {
+    UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
+    UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
+    UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
+    UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
+    UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
+    UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
+    // NOTE: board-specific
+    STDIO_UART  = UART_0
+} UARTName;
+
+typedef enum {
+    SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
+    SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
+    SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
+    SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0),
+    SPI_4 = (int) NU_MODNAME(SPI4_BASE, 4, 0)
+} SPIName;
+
+typedef enum {
+    I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
+    I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0),
+    I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0)
+} I2CName;
+
+typedef enum {
+    PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE, 0, 0),
+    PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE, 0, 1),
+    PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE, 0, 2),
+    PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE, 0, 3),
+    PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE, 0, 4),
+    PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE, 0, 5),
+    
+    PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE, 1, 0),
+    PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE, 1, 1),
+    PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE, 1, 2),
+    PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE, 1, 3),
+    PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE, 1, 4),
+    PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE, 1, 5)
+} PWMName;
+
+typedef enum {
+    TIMER_0  = (int) NU_MODNAME(TIMER0_BASE, 0, 0),
+    TIMER_1  = (int) NU_MODNAME(TIMER1_BASE, 1, 0),
+    TIMER_2  = (int) NU_MODNAME(TIMER2_BASE, 2, 0),
+    TIMER_3  = (int) NU_MODNAME(TIMER3_BASE, 3, 0),
+} TIMERName;
+
+typedef enum {
+    RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
+} RTCName;
+
+typedef enum {
+    DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0)
+} DMAName;
+
+typedef enum {
+    SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0),
+    SD_1 = (int) NU_MODNAME(SDH1_BASE, 1, 0)
+} SDName;
+
+typedef enum {
+    CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0),
+    CAN_1 = (int) NU_MODNAME(CAN1_BASE, 1, 0)
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,586 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0},
+    {PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1},
+    {PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2},
+    {PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3},
+    {PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4},
+    {PB_5, ADC_0_5, SYS_GPB_MFPL_PB5MFP_EADC0_CH5},
+    {PB_6, ADC_0_6, SYS_GPB_MFPL_PB6MFP_EADC0_CH6},
+    {PB_7, ADC_0_7, SYS_GPB_MFPL_PB7MFP_EADC0_CH7},
+    {PB_8, ADC_0_8, SYS_GPB_MFPH_PB8MFP_EADC0_CH8},
+    {PB_9, ADC_0_9, SYS_GPB_MFPH_PB9MFP_EADC0_CH9},
+    {PB_10, ADC_0_10, SYS_GPB_MFPH_PB10MFP_EADC0_CH10},
+    {PB_11, ADC_0_11, SYS_GPB_MFPH_PB11MFP_EADC0_CH11},
+    {PB_12, ADC_0_12, SYS_GPB_MFPH_PB12MFP_EADC0_CH12},
+    {PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13},
+    {PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14},
+    {PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15},
+
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PA_0, I2C_2, SYS_GPA_MFPL_PA0MFP_I2C2_SDA},
+    {PA_2, I2C_1, SYS_GPA_MFPL_PA2MFP_I2C1_SDA},
+    {PA_4, I2C_0, SYS_GPA_MFPL_PA4MFP_I2C0_SDA},
+    {PA_6, I2C_1, SYS_GPA_MFPL_PA6MFP_I2C1_SDA},
+    {PA_10, I2C_2, SYS_GPA_MFPH_PA10MFP_I2C2_SDA},
+    {PA_13, I2C_1, SYS_GPA_MFPH_PA13MFP_I2C1_SDA},
+    {PA_15, I2C_2, SYS_GPA_MFPH_PA15MFP_I2C2_SDA},
+    {PB_0, I2C_1, SYS_GPB_MFPL_PB0MFP_I2C1_SDA},
+    {PB_4, I2C_0, SYS_GPB_MFPL_PB4MFP_I2C0_SDA},
+    {PB_10, I2C_1, SYS_GPB_MFPH_PB10MFP_I2C1_SDA},
+    {PB_12, I2C_2, SYS_GPB_MFPH_PB12MFP_I2C2_SDA},
+    {PC_0, I2C_0, SYS_GPC_MFPL_PC0MFP_I2C0_SDA},
+    {PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SDA},
+    {PC_8, I2C_0, SYS_GPC_MFPH_PC8MFP_I2C0_SDA},
+    {PC_11, I2C_0, SYS_GPC_MFPH_PC11MFP_I2C0_SDA},
+    {PD_0, I2C_2, SYS_GPD_MFPL_PD0MFP_I2C2_SDA},
+    {PD_4, I2C_1, SYS_GPD_MFPL_PD4MFP_I2C1_SDA},
+    {PD_6, I2C_0, SYS_GPD_MFPL_PD6MFP_I2C0_SDA},
+    {PD_8, I2C_2, SYS_GPD_MFPH_PD8MFP_I2C2_SDA},
+    {PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
+    {PF_1, I2C_1, SYS_GPF_MFPL_PF1MFP_I2C1_SDA},
+    {PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA},
+    {PG_1, I2C_0, SYS_GPG_MFPL_PG1MFP_I2C0_SDA},
+    {PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA},
+    {PH_3, I2C_0, SYS_GPH_MFPL_PH3MFP_I2C0_SDA},
+    {PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_1, I2C_2, SYS_GPA_MFPL_PA1MFP_I2C2_SCL},
+    {PA_3, I2C_1, SYS_GPA_MFPL_PA3MFP_I2C1_SCL},
+    {PA_5, I2C_0, SYS_GPA_MFPL_PA5MFP_I2C0_SCL},
+    {PA_7, I2C_1, (int) SYS_GPA_MFPL_PA7MFP_I2C1_SCL},
+    {PA_11, I2C_2, SYS_GPA_MFPH_PA11MFP_I2C2_SCL},
+    {PA_12, I2C_1, SYS_GPA_MFPH_PA12MFP_I2C1_SCL},
+    {PA_14, I2C_2, SYS_GPA_MFPH_PA14MFP_I2C2_SCL},
+    {PB_1, I2C_1, SYS_GPB_MFPL_PB1MFP_I2C1_SCL},
+    {PB_5, I2C_0, SYS_GPB_MFPL_PB5MFP_I2C0_SCL},
+    {PB_11, I2C_1, SYS_GPB_MFPH_PB11MFP_I2C1_SCL},
+    {PB_13, I2C_2, SYS_GPB_MFPH_PB13MFP_I2C2_SCL},
+    {PC_1, I2C_0, SYS_GPC_MFPL_PC1MFP_I2C0_SCL},
+    {PC_5, I2C_1, SYS_GPC_MFPL_PC5MFP_I2C1_SCL},
+    {PC_12, I2C_0, SYS_GPC_MFPH_PC12MFP_I2C0_SCL},
+    {PD_1, I2C_2, SYS_GPD_MFPL_PD1MFP_I2C2_SCL},
+    {PD_5, I2C_1, SYS_GPD_MFPL_PD5MFP_I2C1_SCL},
+    {PD_7, I2C_0, SYS_GPD_MFPL_PD7MFP_I2C0_SCL},
+    {PD_9, I2C_2, SYS_GPD_MFPH_PD9MFP_I2C2_SCL},
+    {PE_1, I2C_1, SYS_GPE_MFPL_PE1MFP_I2C1_SCL},
+    {PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SCL},
+    {PF_0, I2C_1, SYS_GPF_MFPL_PF0MFP_I2C1_SCL},
+    {PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL},
+    {PG_0, I2C_0, SYS_GPG_MFPL_PG0MFP_I2C0_SCL},
+    {PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL},
+    {PH_2, I2C_0, SYS_GPH_MFPL_PH2MFP_I2C0_SCL},
+    {PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL},
+   
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PA_0, PWM_0_5, SYS_GPA_MFPL_PA0MFP_EPWM0_CH5},
+    {PA_1, PWM_0_4, SYS_GPA_MFPL_PA1MFP_EPWM0_CH4},
+    {PA_2, PWM_0_3, SYS_GPA_MFPL_PA2MFP_EPWM0_CH3},
+    {PA_3, PWM_0_2, SYS_GPA_MFPL_PA3MFP_EPWM0_CH2},
+    {PA_4, PWM_0_1, SYS_GPA_MFPL_PA4MFP_EPWM0_CH1},
+    {PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_EPWM0_CH0},
+    {PA_6, PWM_1_5, SYS_GPA_MFPL_PA6MFP_EPWM1_CH5},
+    {PA_7, PWM_1_4, (int) SYS_GPA_MFPL_PA7MFP_EPWM1_CH4},
+    
+    {PB_0, PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
+    {NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5},
+    {PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
+    {NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5},
+    
+    {PB_1, PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
+    {NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4},
+    {PB_1, PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
+    {NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4},
+    
+    {PB_2, PWM_0_3, SYS_GPB_MFPL_PB2MFP_EPWM0_CH3},
+    {PB_3, PWM_0_2, SYS_GPB_MFPL_PB3MFP_EPWM0_CH2},
+    {PB_4, PWM_0_1, SYS_GPB_MFPL_PB4MFP_EPWM0_CH1},
+    {PB_5, PWM_0_0, SYS_GPB_MFPL_PB5MFP_EPWM0_CH0},
+    {PB_6, PWM_1_5, SYS_GPB_MFPL_PB6MFP_EPWM1_CH5},
+    {PB_7, PWM_1_4, (int) SYS_GPB_MFPL_PB7MFP_EPWM1_CH4},
+    {PB_12, PWM_1_3, SYS_GPB_MFPH_PB12MFP_EPWM1_CH3},
+    {PB_13, PWM_1_2, SYS_GPB_MFPH_PB13MFP_EPWM1_CH2},
+    {PB_14, PWM_1_1, SYS_GPB_MFPH_PB14MFP_EPWM1_CH1},
+    {PB_15, PWM_1_0, (int) SYS_GPB_MFPH_PB15MFP_EPWM1_CH0},
+    {PC_0, PWM_1_5, SYS_GPC_MFPL_PC0MFP_EPWM1_CH5},
+    {PC_1, PWM_1_4, SYS_GPC_MFPL_PC1MFP_EPWM1_CH4},
+    {PC_2, PWM_1_3, SYS_GPC_MFPL_PC2MFP_EPWM1_CH3},
+    {PC_3, PWM_1_2, SYS_GPC_MFPL_PC3MFP_EPWM1_CH2},
+    {PC_4, PWM_1_1, SYS_GPC_MFPL_PC4MFP_EPWM1_CH1},
+    {PC_5, PWM_1_0, SYS_GPC_MFPL_PC5MFP_EPWM1_CH0},
+    {PC_6, PWM_1_3, SYS_GPC_MFPL_PC6MFP_EPWM1_CH3},
+    {PC_7, PWM_1_2, (int) SYS_GPC_MFPL_PC7MFP_EPWM1_CH2},
+    {PC_8, PWM_1_1, SYS_GPC_MFPH_PC8MFP_EPWM1_CH1},
+    {PC_9, PWM_1_3, SYS_GPC_MFPH_PC9MFP_EPWM1_CH3},
+    {PC_10, PWM_1_2, SYS_GPC_MFPH_PC10MFP_EPWM1_CH2},
+    {PC_11, PWM_1_1, SYS_GPC_MFPH_PC11MFP_EPWM1_CH1},
+    {PC_12, PWM_1_0, SYS_GPC_MFPH_PC12MFP_EPWM1_CH0},
+    {PD_14, PWM_0_4, SYS_GPD_MFPH_PD14MFP_EPWM0_CH4},
+    {PE_2, PWM_0_5, SYS_GPE_MFPL_PE2MFP_EPWM0_CH5},
+    {PE_3, PWM_0_4, SYS_GPE_MFPL_PE3MFP_EPWM0_CH4},
+    {PE_4, PWM_0_3, SYS_GPE_MFPL_PE4MFP_EPWM0_CH3},
+    {PE_5, PWM_0_2, SYS_GPE_MFPL_PE5MFP_EPWM0_CH2},
+    {PE_6, PWM_0_1, SYS_GPE_MFPL_PE6MFP_EPWM0_CH1},
+    {PE_7, PWM_0_0, (int) SYS_GPE_MFPL_PE7MFP_EPWM0_CH0},
+    {PE_8, PWM_0_0, SYS_GPE_MFPH_PE8MFP_EPWM0_CH0},
+    {PE_9, PWM_0_1, SYS_GPE_MFPH_PE9MFP_EPWM0_CH1},
+    {PE_10, PWM_0_2, SYS_GPE_MFPH_PE10MFP_EPWM0_CH2},
+    {PE_11, PWM_0_3, SYS_GPE_MFPH_PE11MFP_EPWM0_CH3},
+    {PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_EPWM0_CH4},
+    
+    {PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
+    {NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5},
+    {PE_13, PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
+    {NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0},
+    
+    {PG_5, PWM_0_3, SYS_GPG_MFPL_PG5MFP_EPWM0_CH3},
+    {PG_6, PWM_0_2, SYS_GPG_MFPL_PG6MFP_EPWM0_CH2},
+    {PG_7, PWM_0_1, (int) SYS_GPG_MFPL_PG7MFP_EPWM0_CH1},
+    {PG_8, PWM_0_0, SYS_GPG_MFPH_PG8MFP_EPWM0_CH0},
+    {PH_11, PWM_0_5, SYS_GPH_MFPH_PH11MFP_EPWM0_CH5},
+
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_1, UART_0, SYS_GPA_MFPL_PA1MFP_UART0_TXD},
+    
+    {PA_3, UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
+    {NU_PINNAME_BIND(PA_3, UART_1), UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD},
+    {PA_3, UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
+    {NU_PINNAME_BIND(PA_3, UART_4), UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD},
+    
+    {PA_5, UART_5, SYS_GPA_MFPL_PA5MFP_UART5_TXD},
+    {PA_7, UART_0, SYS_GPA_MFPL_PA7MFP_UART0_TXD},
+    {PA_9, UART_1, SYS_GPA_MFPH_PA9MFP_UART1_TXD},
+    {PA_12, UART_4, SYS_GPA_MFPH_PA12MFP_UART4_TXD},
+    {PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD},
+    {PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
+    {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
+    {PB_5, UART_5, SYS_GPB_MFPL_PB5MFP_UART5_TXD},
+    {PB_7, UART_1, SYS_GPB_MFPL_PB7MFP_UART1_TXD},
+    {PB_9, UART_0, SYS_GPB_MFPH_PB9MFP_UART0_TXD},
+    {PB_11, UART_4, SYS_GPB_MFPH_PB11MFP_UART4_TXD},
+    {PB_13, UART_0, SYS_GPB_MFPH_PB13MFP_UART0_TXD},
+    {PB_15, UART_3, SYS_GPB_MFPH_PB15MFP_UART3_TXD},
+    {PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_TXD},
+    {PC_3, UART_3, SYS_GPC_MFPL_PC3MFP_UART3_TXD},
+    
+    {PC_5, UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
+    {NU_PINNAME_BIND(PC_5, UART_2), UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD},
+    {PC_5, UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
+    {NU_PINNAME_BIND(PC_5, UART_4), UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
+    
+    {PC_7, UART_4, SYS_GPC_MFPL_PC7MFP_UART4_TXD},
+    {PC_10, UART_3, SYS_GPC_MFPH_PC10MFP_UART3_TXD},
+    {PC_12, UART_0, SYS_GPC_MFPH_PC12MFP_UART0_TXD},
+    {PC_13, UART_2, SYS_GPC_MFPH_PC13MFP_UART2_TXD},
+    {PD_1, UART_3, SYS_GPD_MFPL_PD1MFP_UART3_TXD},
+    {PD_3, UART_0, SYS_GPD_MFPL_PD3MFP_UART0_TXD},
+    {PD_7, UART_1, SYS_GPD_MFPL_PD7MFP_UART1_TXD},
+    {PD_11, UART_1, SYS_GPD_MFPH_PD11MFP_UART1_TXD},
+    {PE_1, UART_3, SYS_GPE_MFPL_PE1MFP_UART3_TXD},
+    {PE_7, UART_5, (int) SYS_GPE_MFPL_PE7MFP_UART5_TXD},
+    {PE_8, UART_2, SYS_GPE_MFPH_PE8MFP_UART2_TXD},
+    {PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
+    {PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_TXD},
+    {PE_14, UART_2, SYS_GPE_MFPH_PE14MFP_UART2_TXD},
+    {PF_0, UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD},
+    {PF_3, UART_0, SYS_GPF_MFPL_PF3MFP_UART0_TXD},
+    {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_TXD},
+    {PF_7, UART_4, SYS_GPF_MFPL_PF7MFP_UART4_TXD},
+    {PG_0, UART_1, SYS_GPG_MFPL_PG0MFP_UART1_TXD},
+    {PG_1, UART_2, SYS_GPG_MFPL_PG1MFP_UART2_TXD},
+    {PH_0, UART_5, SYS_GPH_MFPL_PH0MFP_UART5_TXD},
+    {PH_2, UART_4, SYS_GPH_MFPL_PH2MFP_UART4_TXD},
+    {PH_8, UART_1, SYS_GPH_MFPH_PH8MFP_UART1_TXD},
+    
+    {PH_10, UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
+    {NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
+    {PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
+    {NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
+    
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_0, UART_0, SYS_GPA_MFPL_PA0MFP_UART0_RXD},
+    
+    {PA_2, UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
+    {NU_PINNAME_BIND(PA_2, UART_1), UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD},
+    {PA_2, UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
+    {NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
+    
+    {PA_4, UART_5, SYS_GPA_MFPL_PA4MFP_UART5_RXD},
+    {PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD},
+    {PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD},
+    {PA_13, UART_4, SYS_GPA_MFPH_PA13MFP_UART4_RXD},
+    {PA_15, UART_0, SYS_GPA_MFPH_PA15MFP_UART0_RXD},
+    {PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
+    {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
+    {PB_4, UART_5, SYS_GPB_MFPL_PB4MFP_UART5_RXD},
+    {PB_6, UART_1, SYS_GPB_MFPL_PB6MFP_UART1_RXD},
+    {PB_8, UART_0, SYS_GPB_MFPH_PB8MFP_UART0_RXD},
+    {PB_10, UART_4, SYS_GPB_MFPH_PB10MFP_UART4_RXD},
+    {PB_12, UART_0, SYS_GPB_MFPH_PB12MFP_UART0_RXD},
+    {PB_14, UART_3, SYS_GPB_MFPH_PB14MFP_UART3_RXD},
+    {PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_RXD},
+    {PC_2, UART_3, SYS_GPC_MFPL_PC2MFP_UART3_RXD},
+    
+    {PC_4, UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
+    {NU_PINNAME_BIND(PC_4, UART_2), UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD},
+    {PC_4, UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
+    {NU_PINNAME_BIND(PC_4, UART_4), UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD},
+    
+    {PC_6, UART_4, SYS_GPC_MFPL_PC6MFP_UART4_RXD},
+    {PC_8, UART_1, SYS_GPC_MFPH_PC8MFP_UART1_RXD},
+    {PC_9, UART_3, SYS_GPC_MFPH_PC9MFP_UART3_RXD},
+    {PC_11, UART_0, SYS_GPC_MFPH_PC11MFP_UART0_RXD},
+    {PD_0, UART_3, SYS_GPD_MFPL_PD0MFP_UART3_RXD},
+    {PD_2, UART_0, SYS_GPD_MFPL_PD2MFP_UART0_RXD},
+    {PD_6, UART_1, SYS_GPD_MFPL_PD6MFP_UART1_RXD},
+    {PD_10, UART_1, SYS_GPD_MFPH_PD10MFP_UART1_RXD},
+    {PD_12, UART_2, SYS_GPD_MFPH_PD12MFP_UART2_RXD},
+    {PE_0, UART_3, SYS_GPE_MFPL_PE0MFP_UART3_RXD},
+    {PE_6, UART_5, SYS_GPE_MFPL_PE6MFP_UART5_RXD},
+    {PE_9, UART_2, SYS_GPE_MFPH_PE9MFP_UART2_RXD},
+    {PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
+    {PE_15, UART_2, SYS_GPE_MFPH_PE15MFP_UART2_RXD},
+    {PF_1, UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD},
+    {PF_2, UART_0, SYS_GPF_MFPL_PF2MFP_UART0_RXD},
+    {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_RXD},
+    {PF_6, UART_4, SYS_GPF_MFPL_PF6MFP_UART4_RXD},
+    {PG_0, UART_2, SYS_GPG_MFPL_PG0MFP_UART2_RXD},
+    {PG_1, UART_1, SYS_GPG_MFPL_PG1MFP_UART1_RXD},
+    {PH_1, UART_5, SYS_GPH_MFPL_PH1MFP_UART5_RXD},
+    {PH_3, UART_4, SYS_GPH_MFPL_PH3MFP_UART4_RXD},
+    {PH_9, UART_1, SYS_GPH_MFPH_PH9MFP_UART1_RXD},
+    
+    {PH_11, UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
+    {NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
+    {PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
+    {NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
+    
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nRTS},
+    {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_nRTS},
+    {PB_3, UART_5, SYS_GPB_MFPL_PB3MFP_UART5_nRTS},
+    {PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
+    {PB_10, UART_0, SYS_GPB_MFPH_PB10MFP_UART0_nRTS},
+    {PB_13, UART_3, SYS_GPB_MFPH_PB13MFP_UART3_nRTS},
+    {PB_14, UART_0, SYS_GPB_MFPH_PB14MFP_UART0_nRTS},
+    {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_nRTS},
+    {PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_nRTS},
+    {PD_3, UART_3, SYS_GPD_MFPL_PD3MFP_UART3_nRTS},
+    {PD_8, UART_2, SYS_GPD_MFPH_PD8MFP_UART2_nRTS},
+    {PE_0, UART_4, SYS_GPE_MFPL_PE0MFP_UART4_nRTS},
+    {PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_nRTS},
+    {PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS},
+    {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS},
+    {PH_2, UART_5, SYS_GPH_MFPL_PH2MFP_UART5_nRTS},
+    {PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS},
+
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nCTS},
+    {PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_nCTS},
+    {PB_2, UART_5, SYS_GPB_MFPL_PB2MFP_UART5_nCTS},
+    {PB_9, UART_1, SYS_GPB_MFPH_PB9MFP_UART1_nCTS},
+    {PB_11, UART_0, SYS_GPB_MFPH_PB11MFP_UART0_nCTS},
+    {PB_12, UART_3, SYS_GPB_MFPH_PB12MFP_UART3_nCTS},
+    {PB_15, UART_0, SYS_GPB_MFPH_PB15MFP_UART0_nCTS},
+    {PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_nCTS},
+    {PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_nCTS},
+    {PC_8, UART_4, SYS_GPC_MFPH_PC8MFP_UART4_nCTS},
+    {PD_2, UART_3, SYS_GPD_MFPL_PD2MFP_UART3_nCTS},
+    {PD_9, UART_2, SYS_GPD_MFPH_PD9MFP_UART2_nCTS},
+    {PE_1, UART_4, SYS_GPE_MFPL_PE1MFP_UART4_nCTS},
+    {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS},
+    {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS},
+    {PH_3, UART_5, SYS_GPH_MFPL_PH3MFP_UART5_nCTS},
+    {PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS},
+
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI0},
+    {NU_PINNAME_BIND(PA_0, SPI_0), SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI0},
+    {PA_0, SPI_1, SYS_GPA_MFPL_PA0MFP_SPI1_MOSI},
+    {NU_PINNAME_BIND(PA_0, SPI_1), SPI_1, SYS_GPA_MFPL_PA0MFP_SPI1_MOSI},
+    
+    {PA_8, SPI_3, SYS_GPA_MFPH_PA8MFP_SPI3_MOSI},
+    {PA_15, SPI_3, SYS_GPA_MFPH_PA15MFP_SPI3_MOSI},
+    {PB_4, SPI_2, SYS_GPB_MFPL_PB4MFP_SPI2_MOSI},
+    {PB_8, SPI_4, SYS_GPB_MFPH_PB8MFP_SPI4_MOSI},
+    {PB_12, SPI_1, SYS_GPB_MFPH_PB12MFP_SPI1_MOSI},
+    {PC_0, SPI_0, SYS_GPC_MFPL_PC0MFP_SPI0_MOSI0},
+    {PC_2, SPI_2, SYS_GPC_MFPL_PC2MFP_SPI2_MOSI},
+    {PC_6, SPI_2, SYS_GPC_MFPL_PC6MFP_SPI2_MOSI},
+    {PC_11, SPI_4, SYS_GPC_MFPH_PC11MFP_SPI4_MOSI},
+    {PD_0, SPI_1, SYS_GPD_MFPL_PD0MFP_SPI1_MOSI},
+    {PD_6, SPI_2, SYS_GPD_MFPL_PD6MFP_SPI2_MOSI},
+    
+    {PE_0, SPI_0, SYS_GPE_MFPL_PE0MFP_SPI0_MOSI0},
+    {NU_PINNAME_BIND(PE_0, SPI_0), SPI_0, SYS_GPE_MFPL_PE0MFP_SPI0_MOSI0},
+    {PE_0, SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_MOSI},
+    {NU_PINNAME_BIND(PE_0, SPI_2), SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_MOSI},
+    
+    {PE_2, SPI_4, SYS_GPE_MFPL_PE2MFP_SPI4_MOSI},
+    {PE_10, SPI_3, SYS_GPE_MFPH_PE10MFP_SPI3_MOSI},
+    {PF_6, SPI_1, SYS_GPF_MFPL_PF6MFP_SPI1_MOSI},
+    {PF_11, SPI_3, SYS_GPF_MFPH_PF11MFP_SPI3_MOSI},
+    {PG_8, SPI_4, SYS_GPG_MFPH_PG8MFP_SPI4_MOSI},
+    {PH_5, SPI_2, SYS_GPH_MFPL_PH5MFP_SPI2_MOSI},
+    
+    {NC,    NC,    0}
+};
+    
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO0},
+    {NU_PINNAME_BIND(PA_1, SPI_0), SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO0},
+    {PA_1, SPI_1, SYS_GPA_MFPL_PA1MFP_SPI1_MISO},
+    {NU_PINNAME_BIND(PA_1, SPI_1), SPI_1, SYS_GPA_MFPL_PA1MFP_SPI1_MISO},
+    
+    {PA_9, SPI_3, SYS_GPA_MFPH_PA9MFP_SPI3_MISO},
+    {PA_14, SPI_3, SYS_GPA_MFPH_PA14MFP_SPI3_MISO},
+    {PB_5, SPI_2, SYS_GPB_MFPL_PB5MFP_SPI2_MISO},
+    {PB_9, SPI_4, SYS_GPB_MFPH_PB9MFP_SPI4_MISO},
+    {PB_13, SPI_1, SYS_GPB_MFPH_PB13MFP_SPI1_MISO},
+    {PC_1, SPI_0, SYS_GPC_MFPL_PC1MFP_SPI0_MISO0},
+    {PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MISO},
+    {PC_7, SPI_2, SYS_GPC_MFPL_PC7MFP_SPI2_MISO},
+    {PC_12, SPI_4, SYS_GPC_MFPH_PC12MFP_SPI4_MISO},
+    {PD_1, SPI_1, SYS_GPD_MFPL_PD1MFP_SPI1_MISO},
+    {PD_7, SPI_2, SYS_GPD_MFPL_PD7MFP_SPI2_MISO},
+    
+    {PE_1, SPI_0, SYS_GPE_MFPL_PE1MFP_SPI0_MISO0},
+    {NU_PINNAME_BIND(PE_1, SPI_0), SPI_0, SYS_GPE_MFPL_PE1MFP_SPI0_MISO0},
+    {PE_1, SPI_2, SYS_GPE_MFPL_PE1MFP_SPI2_MISO},
+    {NU_PINNAME_BIND(PE_1, SPI_2), SPI_2, SYS_GPE_MFPL_PE1MFP_SPI2_MISO},
+    
+    {PE_3, SPI_4, SYS_GPE_MFPL_PE3MFP_SPI4_MISO},
+    {PE_9, SPI_3, SYS_GPE_MFPH_PE9MFP_SPI3_MISO},
+    {PF_7, SPI_1, SYS_GPF_MFPL_PF7MFP_SPI1_MISO},
+    {PG_4, SPI_3, SYS_GPG_MFPL_PG4MFP_SPI3_MISO},
+    {PG_7, SPI_4, SYS_GPG_MFPL_PG7MFP_SPI4_MISO},
+    {PH_4, SPI_2, SYS_GPH_MFPL_PH4MFP_SPI2_MISO},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
+    {NU_PINNAME_BIND(PA_2, SPI_0), SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
+    {PA_2, SPI_1, SYS_GPA_MFPL_PA2MFP_SPI1_CLK},
+    {NU_PINNAME_BIND(PA_2, SPI_1), SPI_1, SYS_GPA_MFPL_PA2MFP_SPI1_CLK},
+    
+    {PA_7, SPI_2, SYS_GPA_MFPL_PA7MFP_SPI2_CLK},
+    {PA_10, SPI_3, SYS_GPA_MFPH_PA10MFP_SPI3_CLK},
+    {PA_13, SPI_3, SYS_GPA_MFPH_PA13MFP_SPI3_CLK},
+    {PB_3, SPI_2, SYS_GPB_MFPL_PB3MFP_SPI2_CLK},
+    {PB_11, SPI_4, SYS_GPB_MFPH_PB11MFP_SPI4_CLK},
+    {PB_14, SPI_1, SYS_GPB_MFPH_PB14MFP_SPI1_CLK},
+    {PC_1, SPI_2, SYS_GPC_MFPL_PC1MFP_SPI2_CLK},
+    {PC_2, SPI_0, SYS_GPC_MFPL_PC2MFP_SPI0_CLK},
+    {PC_10, SPI_4, SYS_GPC_MFPH_PC10MFP_SPI4_CLK},
+    {PC_14, SPI_0, SYS_GPC_MFPH_PC14MFP_SPI0_CLK},
+    {PD_2, SPI_1, SYS_GPD_MFPL_PD2MFP_SPI1_CLK},
+    {PD_5, SPI_2, SYS_GPD_MFPL_PD5MFP_SPI2_CLK},
+    {PE_4, SPI_4, SYS_GPE_MFPL_PE4MFP_SPI4_CLK},
+    {PE_8, SPI_3, SYS_GPE_MFPH_PE8MFP_SPI3_CLK},
+    {PF_2, SPI_0, SYS_GPF_MFPL_PF2MFP_SPI0_CLK},
+    {PF_8, SPI_1, SYS_GPF_MFPH_PF8MFP_SPI1_CLK},
+    {PG_3, SPI_3, SYS_GPG_MFPL_PG3MFP_SPI3_CLK},
+    {PG_6, SPI_4, SYS_GPG_MFPL_PG6MFP_SPI4_CLK},
+    {PH_6, SPI_2, SYS_GPH_MFPL_PH6MFP_SPI2_CLK},
+    
+    {PH_8, SPI_0, SYS_GPH_MFPH_PH8MFP_SPI0_CLK},
+    {NU_PINNAME_BIND(PH_8, SPI_0), SPI_0, SYS_GPH_MFPH_PH8MFP_SPI0_CLK},
+    {PH_8, SPI_2, SYS_GPH_MFPH_PH8MFP_SPI2_CLK},
+    {NU_PINNAME_BIND(PH_8, SPI_2), SPI_2, SYS_GPH_MFPH_PH8MFP_SPI2_CLK},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
+    {NU_PINNAME_BIND(PA_3, SPI_0), SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
+    {PA_3, SPI_1, SYS_GPA_MFPL_PA3MFP_SPI1_SS},
+    {NU_PINNAME_BIND(PA_3, SPI_1), SPI_1, SYS_GPA_MFPL_PA3MFP_SPI1_SS},
+    
+    {PA_6, SPI_2, SYS_GPA_MFPL_PA6MFP_SPI2_SS},
+    {PA_11, SPI_3, SYS_GPA_MFPH_PA11MFP_SPI3_SS},
+    {PA_12, SPI_3, SYS_GPA_MFPH_PA12MFP_SPI3_SS},
+    {PB_2, SPI_2, SYS_GPB_MFPL_PB2MFP_SPI2_SS},
+    {PB_10, SPI_4, SYS_GPB_MFPH_PB10MFP_SPI4_SS},
+    {PB_15, SPI_1, SYS_GPB_MFPH_PB15MFP_SPI1_SS},
+    {PC_0, SPI_2, SYS_GPC_MFPL_PC0MFP_SPI2_SS},
+    {PC_3, SPI_0, SYS_GPC_MFPL_PC3MFP_SPI0_SS},
+    {PC_9, SPI_4, SYS_GPC_MFPH_PC9MFP_SPI4_SS},
+    {PD_3, SPI_1, SYS_GPD_MFPL_PD3MFP_SPI1_SS},
+    {PD_4, SPI_2, SYS_GPD_MFPL_PD4MFP_SPI2_SS},
+    {PE_5, SPI_4, SYS_GPE_MFPL_PE5MFP_SPI4_SS},
+    {PE_11, SPI_3, SYS_GPE_MFPH_PE11MFP_SPI3_SS},
+    {PF_9, SPI_1, SYS_GPF_MFPH_PF9MFP_SPI1_SS},
+    {PG_2, SPI_3, SYS_GPG_MFPL_PG2MFP_SPI3_SS},
+    {PG_5, SPI_4, SYS_GPG_MFPL_PG5MFP_SPI4_SS},
+    {PH_7, SPI_2, SYS_GPH_MFPL_PH7MFP_SPI2_SS},
+    
+    {PH_9, SPI_0, SYS_GPH_MFPH_PH9MFP_SPI0_SS},
+    {NU_PINNAME_BIND(PH_9, SPI_0), SPI_0, SYS_GPH_MFPH_PH9MFP_SPI0_SS},
+    {PH_9, SPI_2, SYS_GPH_MFPH_PH9MFP_SPI2_SS},
+    {NU_PINNAME_BIND(PH_9, SPI_2), SPI_2, SYS_GPH_MFPH_PH9MFP_SPI2_SS},
+    
+    {NC,    NC,    0}
+};
+
+//*** SD ***
+
+const PinMap PinMap_SD_DAT0[] = {
+    {PA_0, SD_1, SYS_GPA_MFPL_PA0MFP_SD1_DAT0},
+    {PA_8, SD_1, SYS_GPA_MFPH_PA8MFP_SD1_DAT0},
+    {PB_2, SD_0, SYS_GPB_MFPL_PB2MFP_SD0_DAT0},
+    {PE_2, SD_0, SYS_GPE_MFPL_PE2MFP_SD0_DAT0},
+    {PG_12, SD_1, SYS_GPG_MFPH_PG12MFP_SD1_DAT0},
+
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT1[] = {
+    {PA_1, SD_1, SYS_GPA_MFPL_PA1MFP_SD1_DAT1},
+    {PA_9, SD_1, SYS_GPA_MFPH_PA9MFP_SD1_DAT1},
+    {PB_3, SD_0, SYS_GPB_MFPL_PB3MFP_SD0_DAT1},
+    {PE_3, SD_0, SYS_GPE_MFPL_PE3MFP_SD0_DAT1},
+    {PG_11, SD_1, SYS_GPG_MFPH_PG11MFP_SD1_DAT1},
+
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT2[] = {
+    {PA_2, SD_1, SYS_GPA_MFPL_PA2MFP_SD1_DAT2},
+    {PA_10, SD_1, SYS_GPA_MFPH_PA10MFP_SD1_DAT2},
+    {PB_4, SD_0, SYS_GPB_MFPL_PB4MFP_SD0_DAT2},
+    {PE_4, SD_0, SYS_GPE_MFPL_PE4MFP_SD0_DAT2},
+    {PG_10, SD_1, SYS_GPG_MFPH_PG10MFP_SD1_DAT2},
+
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT3[] = {
+    {PA_3, SD_1, SYS_GPA_MFPL_PA3MFP_SD1_DAT3},
+    {PA_11, SD_1, SYS_GPA_MFPH_PA11MFP_SD1_DAT3},
+    {PB_5, SD_0, SYS_GPB_MFPL_PB5MFP_SD0_DAT3},
+    {PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_DAT3},
+    {PG_9, SD_1, SYS_GPG_MFPH_PG9MFP_SD1_DAT3},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_CMD[] = {
+    {PA_5, SD_1, SYS_GPA_MFPL_PA5MFP_SD1_CMD},
+    {PB_0, SD_0, SYS_GPB_MFPL_PB0MFP_SD0_CMD},
+    {PB_7, SD_1, SYS_GPB_MFPL_PB7MFP_SD1_CMD},
+    {PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CMD},
+    {PG_13, SD_1, SYS_GPG_MFPH_PG13MFP_SD1_CMD},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_CLK[] = {
+    {PA_4, SD_1, SYS_GPA_MFPL_PA4MFP_SD1_CLK},
+    {PB_1, SD_0, SYS_GPB_MFPL_PB1MFP_SD0_CLK},
+    {PB_6, SD_1, SYS_GPB_MFPL_PB6MFP_SD1_CLK},
+    {PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CLK},
+    {PG_14, SD_1, SYS_GPG_MFPH_PG14MFP_SD1_CLK},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_CD[] = {
+    {PA_6, SD_1, SYS_GPA_MFPL_PA6MFP_SD1_nCD},
+    {PB_12, SD_0, SYS_GPB_MFPH_PB12MFP_SD0_nCD},
+    {PD_13, SD_0, SYS_GPD_MFPH_PD13MFP_SD0_nCD},
+    {PE_14, SD_1, SYS_GPE_MFPH_PE14MFP_SD1_nCD},
+    {PG_15, SD_1, SYS_GPG_MFPH_PG15MFP_SD1_nCD},
+    
+    {NC,    NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_5, CAN_0, SYS_GPA_MFPL_PA5MFP_CAN0_TXD},
+    {PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
+    {PB_7, CAN_1, SYS_GPB_MFPL_PB7MFP_CAN1_TXD},
+    {PB_11, CAN_0, SYS_GPB_MFPH_PB11MFP_CAN0_TXD},
+    {PC_3, CAN_1, SYS_GPC_MFPL_PC3MFP_CAN1_TXD},
+    {PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD},
+    {PC_10, CAN_1, SYS_GPC_MFPH_PC10MFP_CAN1_TXD},
+    {PC_13, CAN_1, SYS_GPC_MFPH_PC13MFP_CAN1_TXD},
+    {PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD},
+    {PE_7, CAN_1, (int) SYS_GPE_MFPL_PE7MFP_CAN1_TXD},
+    {PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD},
+    {PG_0, CAN_1, SYS_GPG_MFPL_PG0MFP_CAN1_TXD},
+
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_CAN_RD[] = { 
+    {PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD},
+    {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
+    {PB_6, CAN_1, SYS_GPB_MFPL_PB6MFP_CAN1_RXD},
+    {PB_10, CAN_0, SYS_GPB_MFPH_PB10MFP_CAN0_RXD},
+    {PC_2, CAN_1, SYS_GPC_MFPL_PC2MFP_CAN1_RXD},
+    {PC_4, CAN_0, SYS_GPC_MFPL_PC4MFP_CAN0_RXD},
+    {PC_9, CAN_1, SYS_GPC_MFPH_PC9MFP_CAN1_RXD},
+    {PD_10, CAN_0, SYS_GPD_MFPH_PD10MFP_CAN0_RXD},
+    {PD_12, CAN_1, SYS_GPD_MFPH_PD12MFP_CAN1_RXD},
+    {PE_6, CAN_1, SYS_GPE_MFPL_PE6MFP_CAN1_RXD},
+    {PE_15, CAN_0, SYS_GPE_MFPH_PE15MFP_CAN0_RXD},
+    {PG_1, CAN_1, SYS_GPG_MFPL_PG1MFP_CAN1_RXD},
+
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//*** GPIO ***
+
+extern const PinMap PinMap_GPIO[];
+
+//*** ADC ***
+
+extern const PinMap PinMap_ADC[];
+
+//*** I2C ***
+
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+//*** PWM ***
+
+extern const PinMap PinMap_PWM[];
+
+//*** SERIAL ***
+
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_RTS[];
+extern const PinMap PinMap_UART_CTS[];
+
+//*** SPI ***
+
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+//*** SD ***
+
+extern const PinMap PinMap_SD_CD[];
+extern const PinMap PinMap_SD_CMD[];
+extern const PinMap PinMap_SD_CLK[];
+extern const PinMap PinMap_SD_DAT0[];
+extern const PinMap PinMap_SD_DAT1[];
+extern const PinMap PinMap_SD_DAT2[];
+extern const PinMap PinMap_SD_DAT3[];
+
+//*** CAN ***
+
+extern PinMap const PinMap_CAN_TD[];
+extern PinMap const PinMap_CAN_RD[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,132 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NU_PININDEX_Pos                             0
+#define NU_PININDEX_Msk                             (0xFFul << NU_PININDEX_Pos)
+#define NU_PINPORT_Pos                              8
+#define NU_PINPORT_Msk                              (0xFul << NU_PINPORT_Pos)
+#define NU_PIN_MODINDEX_Pos                         12
+#define NU_PIN_MODINDEX_Msk                         (0xFul << NU_PIN_MODINDEX_Pos)
+#define NU_PIN_BIND_Pos                             16
+#define NU_PIN_BIND_Msk                             (0x1ul << NU_PIN_BIND_Pos)
+
+#define NU_PININDEX(PINNAME)                        (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
+#define NU_PINPORT(PINNAME)                         (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
+#define NU_PIN_BIND(PINNAME)                        (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
+#define NU_PIN_MODINDEX(PINNAME)                    (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
+#define NU_PINNAME(PORT, PIN)                       ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
+#define NU_PINNAME_BIND(PINNAME, modname)           ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname))
+#define NU_PINNAME_BIND_(PORT, PIN, modname)        ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
+
+#define NU_PORT_BASE(PORT)                          ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * PORT))
+#define NU_MFP_POS(PIN)                             ((PIN % 8) * 4)
+#define NU_MFP_MSK(PIN)                             (0xful << NU_MFP_POS(PIN))
+
+// LEGACY
+#define NU_PINNAME_TO_PIN(PINNAME)                  NU_PININDEX(PINNAME)
+#define NU_PINNAME_TO_PORT(PINNAME)                 NU_PINPORT(PINNAME)
+#define NU_PINNAME_TO_MODSUBINDEX(PINNAME)          NU_PIN_MODINDEX(PINNAME)
+#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN)         NU_PINNAME((PORT), (PIN))
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PullNone = 0,
+    PullDown,
+    PullUp,
+    
+    PushPull,
+    OpenDrain,
+    Quasi,
+    
+    PullDefault = PullUp,
+} PinMode;
+
+typedef enum {
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+    
+    // Generic naming
+    PA_0    = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
+    PB_0    = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
+    PC_0    = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14,
+    PD_0    = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14,
+    PE_0    = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15,
+    PF_0    = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11,
+    PG_0    = NU_PORT_N_PIN_TO_PINNAME(6, 0), PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PG_8, PG_9, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15,
+    PH_0    = NU_PORT_N_PIN_TO_PINNAME(7, 0), PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11,
+    
+    // Arduino UNO naming
+    A0 = PB_6,
+    A1 = PB_7,
+    A2 = PB_8,
+    A3 = PB_3,
+    A4 = PB_4,
+    A5 = PB_5,
+
+    D0 = PH_9,
+    D1 = PH_8,
+    D2 = PB_9,
+    D3 = PF_11,
+    D4 = PG_4,
+    D5 = PC_11,
+    D6 = PC_12,
+    D7 = PC_13,
+    D8 = PA_5,
+    D9 = PA_4,
+    D10 = PA_3,
+    D11 = PA_0,
+    D12 = PA_1,
+    D13 = PA_2,
+    D14 = PG_3,
+    D15 = PG_2,
+
+    // Note: board-specific
+    // UART naming
+    USBTX = PD_3,
+    USBRX = PD_2,
+    STDIO_UART_TX   = USBTX,
+    STDIO_UART_RX   = USBRX,
+    // LED naming
+    LED_RED = PH_0,
+    LED_YELLOW = PH_1,
+    LED_GREEN = PH_2,
+    LED1 = LED_RED,
+    LED2 = LED_YELLOW,
+    LED3 = LED_GREEN,
+    LED4 = LED1,    // No real LED. Just for passing ATS.
+    // Button naming
+    SW2 = PC_10,
+    SW3 = PC_9,
+    
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_PINNAMES_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PortNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5,
+    PortG = 6,
+    PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/device.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbed_overrides.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,72 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "analogin_api.h"
+
+void mbed_sdk_init(void)
+{
+    // NOTE: Support singleton semantics to be called from other init functions
+    static int inited = 0;
+    if (inited) {
+        return;
+    }
+    inited = 1;
+    
+    /*---------------------------------------------------------------------------------------------------------*/
+    /* Init System Clock                                                                                       */
+    /*---------------------------------------------------------------------------------------------------------*/
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+
+    /* Enable HIRC clock (Internal RC 22.1184MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
+    /* Enable HXT clock (external XTAL 12MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+    /* Enable LIRC for lp_ticker */
+    CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
+    /* Enable LXT for RTC */
+    CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+
+    /* Wait for HIRC clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    /* Wait for HXT clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+    /* Wait for LIRC clock ready */
+    CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+    /* Wait for LXT clock ready */
+    CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+
+    /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
+    
+    /* Set core clock as 192000000 from PLL */
+    CLK_SetCoreClock(192000000);
+    
+    /* Set PCLK0/PCLK1 to HCLK/2 */
+    CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); // PCLK divider set 2
+    
+#if DEVICE_ANALOGIN
+    /* Vref connect to internal */
+    SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V;
+#endif
+    
+    /* Update System Core Clock */
+    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+    SystemCoreClockUpdate();
+
+    /* Lock protected registers */
+    SYS_LockReg();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "dma_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    //IRQn_Type irq_n;
+    //uint32_t irq_index;
+    //uint32_t event;
+    
+    PinName     pin;
+    uint32_t    irq_handler;
+    uint32_t    irq_id;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+};
+
+struct analogin_s {
+    ADCName adc;
+    //PinName pin;
+};
+
+struct serial_s {
+    UARTName uart;
+    PinName pin_tx;
+    PinName pin_rx;
+    
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t parity;
+    uint32_t stopbits;
+    
+    void        (*vec)(void);
+    uint32_t    irq_handler;
+    uint32_t    irq_id;
+    uint32_t    irq_en;
+    uint32_t    inten_msk;
+    
+    // Async transfer related fields
+    DMAUsage    dma_usage_tx;
+    DMAUsage    dma_usage_rx;
+    int         dma_chn_id_tx;
+    int         dma_chn_id_rx;
+    uint32_t    event;
+    void        (*irq_handler_tx_async)(void);
+    void        (*irq_handler_rx_async)(void);
+};
+
+struct spi_s {
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+    
+    //void        (*vec)(void);
+    
+    // Async transfer related fields
+    DMAUsage    dma_usage;
+    int         dma_chn_id_tx;
+    int         dma_chn_id_rx;
+    uint32_t    event;
+    //void        (*irq_handler_tx_async)(void);
+    //void        (*irq_handler_rx_async)(void);
+};
+
+struct i2c_s {
+    I2CName     i2c;
+    //void        (*vec)(void);
+    int         slaveaddr_state;
+    
+    uint32_t    tran_ctrl;
+    char *      tran_beg;
+    char *      tran_pos;
+    char *      tran_end;
+    int         inten;
+    
+    
+    // Async transfer related fields
+    DMAUsage    dma_usage;
+    uint32_t    event;
+    int         stop;
+    uint32_t    address;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    //PinName pin;
+    uint32_t period_us;
+    uint32_t pulsewidth_us;
+};
+
+struct sleep_s {
+    int powerdown;
+};
+
+struct trng_s {
+    uint8_t dummy;
+};
+
+struct can_s {
+    CANName can;
+    int index; 
+};
+#ifdef __cplusplus
+}
+#endif
+
+#include "gpio_object.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+
+static uint32_t eadc_modinit_mask = 0;
+
+static const struct nu_modinit_s adc_modinit_tab[] = {
+    {ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+    {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC0_IRQn, NULL},
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName) NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->adc);
+
+    EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
+
+    // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
+    if (! eadc_modinit_mask) {
+        // Reset this module if no channel enabled
+        SYS_ResetModule(modinit->rsetidx);
+
+        // Select clock source of paired channels
+        CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+        // Enable clock of paired channels
+        CLK_EnableModuleClock(modinit->clkidx);
+
+        // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
+        EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
+    }
+
+    uint32_t chn =  NU_MODSUBINDEX(obj->adc);
+
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_ADC);
+
+    // Configure the sample module Nmod for analog input channel Nch and software trigger source
+    EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn);
+
+    eadc_modinit_mask |= 1 << chn;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
+    uint32_t chn =  NU_MODSUBINDEX(obj->adc);
+
+    EADC_START_CONV(eadc_base, 1 << chn);
+    while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn)));
+    uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
+    // Just 12 bits are effective. Convert to 16 bits.
+    // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
+    // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
+    uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
+
+    return conv_res_16;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float) value * (1.0f / (float) 0xFFFF);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/can_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,355 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "can_api.h"
+#include "m480_gpio.h"
+#include "m480_can.h"
+
+#if DEVICE_CAN
+#include <string.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+#include "mbed_critical.h"
+
+#define NU_CAN_DEBUG    0
+#define CAN_NUM         2
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler can0_irq_handler;
+static can_irq_handler can1_irq_handler;
+
+extern uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+extern void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+extern void CAN_LeaveInitMode(CAN_T *tCAN);
+extern void CAN_LeaveTestMode(CAN_T *tCAN);
+extern void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+
+static const struct nu_modinit_s can_modinit_tab[] = {
+    {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
+    {CAN_1, CAN1_MODULE, 0, 0, CAN1_RST, CAN1_IRQn, NULL},
+
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
+{
+    uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    obj->can = (CANName)pinmap_merge(can_td, can_rd);
+    MBED_ASSERT((int)obj->can != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->can);
+
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+
+    NVIC_DisableIRQ(CAN0_IRQn);
+    NVIC_DisableIRQ(CAN1_IRQn);
+
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    if(obj->can == CAN_1) {
+        obj->index = 1;
+    } else
+        obj->index = 0;
+
+    pinmap_pinout(td, PinMap_CAN_TD);
+    pinmap_pinout(rd, PinMap_CAN_RD);
+#if 0
+    /* TBD: For M487 mbed Board Transmitter Setting (RS Pin) */
+    GPIO_SetMode(PA, BIT2| BIT3, GPIO_MODE_OUTPUT);
+    PA2 = 0x00;
+    PA3 = 0x00;
+#endif
+    CAN_Open((CAN_T *)NU_MODBASE(obj->can), hz, CAN_NORMAL_MODE);
+
+    can_filter(obj, 0, 0, CANStandard, 0);
+}
+
+void can_init(can_t *obj, PinName rd, PinName td)
+{
+    can_init_freq(obj, rd, td, 500000);
+}
+
+void can_free(can_t *obj)
+{
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->can);
+
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+
+    CLK_DisableModuleClock(modinit->clkidx);
+}
+
+int can_frequency(can_t *obj, int hz)
+{
+    CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz);
+
+    return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can));
+}
+
+static void can_irq(CANName name, int id)
+{
+
+    CAN_T *can = (CAN_T *)NU_MODBASE(name);
+    uint32_t u8IIDRstatus;
+
+    u8IIDRstatus = can->IIDR;
+
+    if(u8IIDRstatus == 0x00008000) {      /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+        /**************************/
+        /* Status Change interrupt*/
+        /**************************/
+        if(can->STATUS & CAN_STATUS_RXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_RXOK_Msk;   /* Clear Rx Ok status*/
+            if(id)
+                can1_irq_handler(can_irq_ids[id], IRQ_RX);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_RX);
+        }
+
+        if(can->STATUS & CAN_STATUS_TXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_TXOK_Msk;    /* Clear Tx Ok status*/
+            if(id)
+                can1_irq_handler(can_irq_ids[id], IRQ_TX);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_TX);
+
+        }
+
+        /**************************/
+        /* Error Status interrupt */
+        /**************************/
+        if(can->STATUS & CAN_STATUS_EWARN_Msk) {
+            if(id)
+                can1_irq_handler(can_irq_ids[id], IRQ_ERROR);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
+        }
+
+        if(can->STATUS & CAN_STATUS_BOFF_Msk) {
+            if(id)
+                can1_irq_handler(can_irq_ids[id], IRQ_BUS);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_BUS);
+        }
+    } else if (u8IIDRstatus!=0) {
+
+        if(id)
+            can1_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
+        else
+            can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
+
+        CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1));      /* Clear Interrupt Pending */
+
+    } else if(can->WU_STATUS == 1) {
+
+        can->WU_STATUS = 0;                       /* Write '0' to clear */
+        if(id)
+            can1_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
+        else
+            can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
+    }
+}
+
+void CAN0_IRQHandler(void)
+{
+    can_irq(CAN_0, 0);
+}
+
+void CAN1_IRQHandler(void)
+{
+    can_irq(CAN_1, 1);
+}
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
+{
+    if(obj->index)
+        can1_irq_handler = handler;
+    else
+        can0_irq_handler = handler;
+    can_irq_ids[obj->index] = id;
+
+}
+
+void can_irq_free(can_t *obj)
+{
+    CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
+
+    can_irq_ids[obj->index] = 0;
+
+    if(!obj->index)
+        NVIC_DisableIRQ(CAN0_IRQn);
+    else
+        NVIC_DisableIRQ(CAN1_IRQn);
+
+
+}
+
+void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
+{
+    uint8_t u8Mask;
+
+    u8Mask = ((enable != 0 )? CAN_CON_IE_Msk :0);
+
+    switch (irq) {
+    case IRQ_ERROR:
+    case IRQ_BUS:
+    case IRQ_PASSIVE:
+        u8Mask = u8Mask | CAN_CON_EIE_Msk | CAN_CON_SIE_Msk;
+        break;
+
+    case IRQ_RX:
+    case IRQ_TX:
+    case IRQ_OVERRUN:
+    case IRQ_WAKEUP:
+        u8Mask = u8Mask | CAN_CON_SIE_Msk;
+        break;
+
+    default:
+        break;
+
+    }
+    CAN_EnterInitMode((CAN_T*)NU_MODBASE(obj->can), u8Mask);
+
+    CAN_LeaveInitMode((CAN_T*)NU_MODBASE(obj->can));
+
+    if(!obj->index) {
+        NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
+        NVIC_EnableIRQ(CAN0_IRQn);
+    } else {
+        NVIC_SetVector(CAN1_IRQn, (uint32_t)&CAN1_IRQHandler);
+        NVIC_EnableIRQ(CAN1_IRQn);
+    }
+
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc)
+{
+    STR_CANMSG_T CMsg;
+
+    CMsg.IdType = (uint32_t)msg.format;
+    CMsg.FrameType = (uint32_t)!msg.type;
+    CMsg.Id = msg.id;
+    CMsg.DLC = msg.len;
+    memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
+
+    return CAN_Transmit((CAN_T *)(NU_MODBASE(obj->can)), cc, &CMsg);
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle)
+{
+    STR_CANMSG_T CMsg;
+
+    if(!CAN_Receive((CAN_T *)(NU_MODBASE(obj->can)), handle, &CMsg))
+        return 0;
+
+    msg->format = (CANFormat)CMsg.IdType;
+    msg->type = (CANType)!CMsg.FrameType;
+    msg->id = CMsg.Id;
+    msg->len = CMsg.DLC;
+    memcpy(&msg->data[0], &CMsg.Data[0], 8);
+
+    return 1;
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+    int success = 0;
+    switch (mode) {
+    case MODE_RESET:
+        CAN_LeaveTestMode((CAN_T*)NU_MODBASE(obj->can));
+        success = 1;
+        break;
+
+    case MODE_NORMAL:
+        CAN_EnterTestMode((CAN_T*)NU_MODBASE(obj->can), CAN_TEST_BASIC_Msk);
+        success = 1;
+        break;
+
+    case MODE_SILENT:
+        CAN_EnterTestMode((CAN_T*)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk);
+        success = 1;
+        break;
+
+    case MODE_TEST_LOCAL:
+    case MODE_TEST_GLOBAL:
+        CAN_EnterTestMode((CAN_T*)NU_MODBASE(obj->can), CAN_TEST_LBACK_Msk);
+        success = 1;
+        break;
+
+    case MODE_TEST_SILENT:
+        CAN_EnterTestMode((CAN_T*)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+        success = 1;
+        break;
+
+    default:
+        success = 0;
+        break;
+
+    }
+
+
+    return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
+{
+    return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle, (uint32_t)format, id);
+}
+
+
+void can_reset(can_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->can);
+
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+
+}
+
+unsigned char can_rderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
+    return ((can->ERR>>8)&0xFF);
+}
+
+unsigned char can_tderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)NU_MODBASE(obj->can);
+    return ((can->ERR)&0xFF);
+}
+
+void can_monitor(can_t *obj, int silent)
+{
+    CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk);
+}
+
+#endif // DEVICE_CAN

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,36016 @@
+/**************************************************************************//**
+ * @file     M480.h
+ * @version  V1.00
+ * @brief    M480 peripheral access layer header file.
+ *           This file contains all the peripheral register's definitions,
+ *           bits definitions and memory mapping for NuMicro TC8226 MCU.
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+/**
+   \mainpage NuMicro M480 Driver Reference Guide
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the usage of M480 Series MCU device driver
+   *
+   * <b>Disclaimer</b>
+   *
+   * The Software is furnished "AS IS", without warranty as to performance or results, and
+   * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+   * warranties, express, implied or otherwise, with regard to the Software, its use, or
+   * operation, including without limitation any and all warranties of merchantability, fitness
+   * for a particular purpose, and non-infringement of intellectual property rights.
+   *
+   * <b>Important Notice</b>
+   *
+   * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+   * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+   * property damage. Such applications are deemed, "Insecure Usage".
+   *
+   * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+   * atomic energy control instruments, airplane or spaceship instruments, the control or
+   * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+   * instruments, all types of safety devices, and other applications intended to support or
+   * sustain life.
+   *
+   * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+   * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+   * the damages and liabilities thus incurred by Nuvoton.
+   *
+   * Please note that all data and specifications are subject to change without notice. All the
+   * trademarks of products and companies mentioned in this datasheet belong to their respective
+   * owners.
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+   */
+#ifndef __M480_H__
+#define __M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup M480_CMSIS M480 Device CMSIS Definitions
+  Configuration of the Cortex-M4 Processor and Core Peripherals
+  @{
+*/
+
+/**
+ * @details  Interrupt Number Definition.
+ */
+typedef enum IRQn {
+    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+    MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+    BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+    UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+    SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+    DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+    PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+    SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+    /******  M480 Specific Interrupt Numbers ********************************************************/
+
+    BOD_IRQn                      = 0,        /*!< Brown Out detection Interrupt                    */
+    IRC_IRQn                      = 1,        /*!< Internal RC Interrupt                            */
+    PWRWU_IRQn                    = 2,        /*!< Power Down Wake Up Interrupt                     */
+    RAMPE_IRQn                    = 3,        /*!< SRAM parity check failed Interrupt               */
+    CKFAIL_IRQn                   = 4,        /*!< Clock failed Interrupt                           */
+    RTC_IRQn                      = 6,        /*!< Real Time Clock Interrupt                        */
+    TAMPER_IRQn                   = 7,        /*!< Tamper detection Interrupt                       */
+    WDT_IRQn                      = 8,        /*!< Watchdog timer Interrupt                         */
+    WWDT_IRQn                     = 9,        /*!< Window Watchdog timer Interrupt                  */
+    EINT0_IRQn                    = 10,       /*!< External Input 0 Interrupt                       */
+    EINT1_IRQn                    = 11,       /*!< External Input 1 Interrupt                       */
+    EINT2_IRQn                    = 12,       /*!< External Input 2 Interrupt                       */
+    EINT3_IRQn                    = 13,       /*!< External Input 3 Interrupt                       */
+    EINT4_IRQn                    = 14,       /*!< External Input 4 Interrupt                       */
+    EINT5_IRQn                    = 15,       /*!< External Input 5 Interrupt                       */
+    GPA_IRQn                      = 16,       /*!< GPIO Port A Interrupt                            */
+    GPB_IRQn                      = 17,       /*!< GPIO Port B Interrupt                            */
+    GPC_IRQn                      = 18,       /*!< GPIO Port C Interrupt                            */
+    GPD_IRQn                      = 19,       /*!< GPIO Port D Interrupt                            */
+    GPE_IRQn                      = 20,       /*!< GPIO Port E Interrupt                            */
+    GPF_IRQn                      = 21,       /*!< GPIO Port F Interrupt                            */
+    SPI0_IRQn                     = 22,       /*!< SPI0 Interrupt                                   */
+    SPI1_IRQn                     = 23,       /*!< SPI1 Interrupt                                   */
+    BRAKE0_IRQn                   = 24,       /*!< BRAKE0 Interrupt                                 */
+    EPWM0P0_IRQn                  = 25,       /*!< EPWM0P0 Interrupt                                */
+    EPWM0P1_IRQn                  = 26,       /*!< EPWM0P1 Interrupt                                */
+    EPWM0P2_IRQn                  = 27,       /*!< EPWM0P2 Interrupt                                */
+    BRAKE1_IRQn                   = 28,       /*!< BRAKE1 Interrupt                                 */
+    EPWM1P0_IRQn                  = 29,       /*!< EPWM1P0 Interrupt                                */
+    EPWM1P1_IRQn                  = 30,       /*!< EPWM1P1 Interrupt                                */
+    EPWM1P2_IRQn                  = 31,       /*!< EPWM1P2 Interrupt                                */
+    TMR0_IRQn                     = 32,       /*!< Timer 0 Interrupt                                */
+    TMR1_IRQn                     = 33,       /*!< Timer 1 Interrupt                                */
+    TMR2_IRQn                     = 34,       /*!< Timer 2 Interrupt                                */
+    TMR3_IRQn                     = 35,       /*!< Timer 3 Interrupt                                */
+    UART0_IRQn                    = 36,       /*!< UART 0 Interrupt                                 */
+    UART1_IRQn                    = 37,       /*!< UART 1 Interrupt                                 */
+    I2C0_IRQn                     = 38,       /*!< I2C 0 Interrupt                                  */
+    I2C1_IRQn                     = 39,       /*!< I2C 1 Interrupt                                  */
+    PDMA_IRQn                     = 40,       /*!< Peripheral DMA Interrupt                         */
+    DAC_IRQn                      = 41,       /*!< DAC Interrupt                                    */
+    ADC0_IRQn                     = 42,       /*!< ADC0 Interrupt                                   */
+    ADC1_IRQn                     = 43,       /*!< ADC1 Interrupt                                   */
+    ACMP01_IRQn                   = 44,       /*!< Analog Comparator 0 and 1 Interrupt              */
+    ADC2_IRQn                     = 46,       /*!< ADC2 Interrupt                                   */
+    ADC3_IRQn                     = 47,       /*!< ADC3 Interrupt                                   */
+    UART2_IRQn                    = 48,       /*!< UART2 Interrupt                                  */
+    UART3_IRQn                    = 49,       /*!< UART3 Interrupt                                  */
+    SPI2_IRQn                     = 51,       /*!< SPI2 Interrupt                                   */
+    SPI3_IRQn                     = 52,       /*!< SPI3 Interrupt                                   */
+    USBD_IRQn                     = 53,       /*!< USB device Interrupt                             */
+    USBH_IRQn                     = 54,       /*!< USB host Interrupt                               */
+    USBOTG_IRQn                   = 55,       /*!< USB OTG Interrupt                                */
+    CAN0_IRQn                     = 56,       /*!< CAN0 Interrupt                                   */
+    CAN1_IRQn                     = 57,       /*!< CAN1 Interrupt                                   */
+    SC0_IRQn                      = 58,       /*!< Smart Card 0 Interrupt                           */
+    SC1_IRQn                      = 59,       /*!< Smart Card 1 Interrupt                           */
+    SC2_IRQn                      = 60,       /*!< Smart Card 2 Interrupt                           */
+    SPI4_IRQn                     = 62,       /*!< SPI4 Interrupt                                   */
+    EMAC_TX_IRQn                  = 66,       /*!< Ethernet MAC TX Interrupt                        */
+    EMAC_RX_IRQn                  = 67,       /*!< Ethernet MAC RX Interrupt                        */
+    SDH0_IRQn                     = 64,       /*!< Secure Digital Host Controller 0 Interrupt       */
+    USBD20_IRQn                   = 65,       /*!< High Speed USB device Interrupt                  */
+    I2S0_IRQn                     = 68,       /*!< I2S0 Interrupt                                   */
+    OPA_IRQn                      = 70,       /*!< OPA Interrupt                                    */
+    CRPT_IRQn                     = 71,       /*!< CRPT Interrupt                                   */
+    GPG_IRQn                      = 72,       /*!< GPIO Port G Interrupt                            */
+    EINT6_IRQn                    = 73,       /*!< External Input 6 Interrupt                       */
+    UART4_IRQn                    = 74,       /*!< UART4 Interrupt                                  */
+    UART5_IRQn                    = 75,       /*!< UART5 Interrupt                                  */
+    USCI0_IRQn                    = 76,       /*!< USCI0 Interrupt                                  */
+    USCI1_IRQn                    = 77,       /*!< USCI1 Interrupt                                  */
+    BPWM0_IRQn                    = 78,       /*!< BPWM0 Interrupt                                  */
+    BPWM1_IRQn                    = 79,       /*!< BPWM1 Interrupt                                  */
+    SPIM_IRQn                     = 80,       /*!< SPIM Interrupt                                   */
+    I2C2_IRQn                     = 82,       /*!< I2C2 Interrupt                                   */
+    QEI0_IRQn                     = 84,       /*!< QEI0 Interrupt                                   */
+    QEI1_IRQn                     = 85,       /*!< QEI1 Interrupt                                   */
+    ECAP0_IRQn                    = 86,       /*!< ECAP0 Interrupt                                  */
+    ECAP1_IRQn                    = 87,       /*!< ECAP1 Interrupt                                  */
+    GPH_IRQn                      = 88,       /*!< GPIO Port H Interrupt                            */
+    EINT7_IRQn                    = 89,       /*!< External Input 7 Interrupt                       */
+    SDH1_IRQn                     = 90,       /*!< Secure Digital Host Controller 1 Interrupt       */
+    HSUSBH_IRQn                   = 92,       /*!< High speed USB host Interrupt                    */
+    USBOTG20_IRQn                 = 93,       /*!< High speed USB OTG Interrupt                     */
+}
+IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+#define __CM4_REV                 0x0201      /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          4           /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0           /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             1           /*!< MPU present or not                               */
+#define __FPU_PRESENT             1           /*!< FPU present or not                               */
+
+/*@}*/ /* end of group M480_CMSIS */
+
+
+#include "core_cm4.h"               /* Cortex-M4 processor and core peripherals           */
+#include "system_M480.h"            /* TC8226 System include file                         */
+#include <stdint.h>
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup M480_Peripherals M480 Control Register
+  M480 Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+
+/*---------------------- System Manger Controller -------------------------*/
+/**
+    @addtogroup SYS System Manger Controller(SYS)
+    Memory Mapped Structure for SYS Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var SYS_T::PDID
+     * Offset: 0x00  Part Device Identification Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PDID      |Part Device Identification Number (Read Only)
+     * |        |          |This register reflects device part number code
+     * |        |          |Software can read this register to identify which device is used.
+     * @var SYS_T::RSTSTS
+     * Offset: 0x04  System Reset Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PORF      |POR Reset Flag
+     * |        |          |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+     * |        |          |0 = No reset from POR or CHIPRST.
+     * |        |          |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |PINRF     |NRESET Pin Reset Flag
+     * |        |          |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+     * |        |          |0 = No reset from nRESET pin.
+     * |        |          |1 = Pin nRESET had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[2]     |WDTRF     |WDT Reset Flag
+     * |        |          |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+     * |        |          |0 = No reset from watchdog timer or window watchdog timer.
+     * |        |          |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset
+     * |        |          |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+     * |[3]     |LVRF      |LVR Reset Flag
+     * |        |          |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
+     * |        |          |0 = No reset from LVR.
+     * |        |          |1 = LVR controller had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |BODRF     |BOD Reset Flag
+     * |        |          |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source.
+     * |        |          |0 = No reset from BOD.
+     * |        |          |1 = The BOD had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |SYSRF     |System Reset Flag
+     * |        |          |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
+     * |        |          |0 = No reset from Cortex-M4.
+     * |        |          |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[7]     |CPURF     |CPU Reset Flag
+     * |        |          |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
+     * |        |          |0 = No reset from CPU.
+     * |        |          |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
+     * |        |          |Note: Write to clear this bit to 0.
+     * |[8]     |CPULKRF   |CPU Lock-up Reset Flag
+     * |        |          |0 = No reset from CPU lock-up happened.
+     * |        |          |1 = The Cortex-M4 lock-up happened and chip is reset.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |        |          |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset.
+     * @var SYS_T::IPRST0
+     * Offset: 0x08  Peripheral  Reset Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CHIPRST   |Chip One-shot Reset (Write Protect)
+     * |        |          |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+     * |        |          |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+     * |        |          |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
+     * |        |          |0 = Chip normal operation.
+     * |        |          |1 = Chip one-shot reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |CPURST    |Processor Core One-shot Reset (Write Protect)
+     * |        |          |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+     * |        |          |0 = Processor core normal operation.
+     * |        |          |1 = Processor core one-shot reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |PDMARST   |PDMA Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the PDMA
+     * |        |          |User needs to set this bit to 0 to release from reset state.
+     * |        |          |0 = PDMA controller normal operation.
+     * |        |          |1 = PDMA controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |EBIRST    |EBI Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the EBI
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = EBI controller normal operation.
+     * |        |          |1 = EBI controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |EMACRST   |EMAC Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the EMAC controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = EMAC controller normal operation.
+     * |        |          |1 = EMAC controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |SDH0RST   |SDHOST0 Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = SDHOST0 controller normal operation.
+     * |        |          |1 = SDHOST0 controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |CRCRST    |CRC Calculation Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the CRC calculation controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = CRC calculation controller normal operation.
+     * |        |          |1 = CRC calculation controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10]    |HSUSBDRST |HSUSBD Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the HSUSBD controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = HSUSBD controller normal operation.
+     * |        |          |1 = HSUSBD controller reset.
+     * |[12]    |CRPTRST   |CRYPTO Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the CRYPTO controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = CRYPTO controller normal operation.
+     * |        |          |1 = CRYPTO controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[14]    |SPIMRST   |SPIM Controller Reset
+     * |        |          |Setting this bit to 1 will generate a reset signal to the SPIM controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = SPIM controller normal operation.
+     * |        |          |1 = SPIM controller reset.
+     * |[16]    |USBHRST   |USBH Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the USBH controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = USBH controller normal operation.
+     * |        |          |1 = USBH controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17]    |SDH1RST   |SDHOST1 Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = SDHOST1 controller normal operation.
+     * |        |          |1 = SDHOST1 controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::IPRST1
+     * Offset: 0x0C  Peripheral Reset Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |GPIORST   |GPIO Controller Reset
+     * |        |          |0 = GPIO controller normal operation.
+     * |        |          |1 = GPIO controller reset.
+     * |[2]     |TMR0RST   |Timer0 Controller Reset
+     * |        |          |0 = Timer0 controller normal operation.
+     * |        |          |1 = Timer0 controller reset.
+     * |[3]     |TMR1RST   |Timer1 Controller Reset
+     * |        |          |0 = Timer1 controller normal operation.
+     * |        |          |1 = Timer1 controller reset.
+     * |[4]     |TMR2RST   |Timer2 Controller Reset
+     * |        |          |0 = Timer2 controller normal operation.
+     * |        |          |1 = Timer2 controller reset.
+     * |[5]     |TMR3RST   |Timer3 Controller Reset
+     * |        |          |0 = Timer3 controller normal operation.
+     * |        |          |1 = Timer3 controller reset.
+     * |[7]     |ACMP01RST |Analog Comparator 0/1 Controller Reset
+     * |        |          |0 = Analog Comparator 0/1 controller normal operation.
+     * |        |          |1 = Analog Comparator 0/1 controller reset.
+     * |[8]     |I2C0RST   |I2C0 Controller Reset
+     * |        |          |0 = I2C0 controller normal operation.
+     * |        |          |1 = I2C0 controller reset.
+     * |[9]     |I2C1RST   |I2C1 Controller Reset
+     * |        |          |0 = I2C1 controller normal operation.
+     * |        |          |1 = I2C1 controller reset.
+     * |[10]    |I2C2RST   |I2C2 Controller Reset
+     * |        |          |0 = I2C2 controller normal operation.
+     * |        |          |1 = I2C2 controller reset.
+     * |[12]    |SPI0RST   |SPI0 Controller Reset
+     * |        |          |0 = SPI0 controller normal operation.
+     * |        |          |1 = SPI0 controller reset.
+     * |[13]    |SPI1RST   |SPI1 Controller Reset
+     * |        |          |0 = SPI1 controller normal operation.
+     * |        |          |1 = SPI1 controller reset.
+     * |[14]    |SPI2RST   |SPI2 Controller Reset
+     * |        |          |0 = SPI2 controller normal operation.
+     * |        |          |1 = SPI2 controller reset.
+     * |[15]    |SPI3RST   |SPI3 Controller Reset
+     * |        |          |0 = SPI3 controller normal operation.
+     * |        |          |1 = SPI3 controller reset.
+     * |[16]    |UART0RST  |UART0 Controller Reset
+     * |        |          |0 = UART0 controller normal operation.
+     * |        |          |1 = UART0 controller reset.
+     * |[17]    |UART1RST  |UART1 Controller Reset
+     * |        |          |0 = UART1 controller normal operation.
+     * |        |          |1 = UART1 controller reset.
+     * |[18]    |UART2RST  |UART2 Controller Reset
+     * |        |          |0 = UART2 controller normal operation.
+     * |        |          |1 = UART2 controller reset.
+     * |[19]    |UART3RST  |UART3 Controller Reset
+     * |        |          |0 = UART3 controller normal operation.
+     * |        |          |1 = UART3 controller reset.
+     * |[20]    |UART4RST  |UART4 Controller Reset
+     * |        |          |0 = UART4 controller normal operation.
+     * |        |          |1 = UART4 controller reset.
+     * |[21]    |UART5RST  |UART5 Controller Reset
+     * |        |          |0 = UART5 controller normal operation.
+     * |        |          |1 = UART5 controller reset.
+     * |[24]    |CAN0RST   |CAN0 Controller Reset
+     * |        |          |0 = CAN0 controller normal operation.
+     * |        |          |1 = CAN0 controller reset.
+     * |[25]    |CAN1RST   |CAN1 Controller Reset
+     * |        |          |0 = CAN1 controller normal operation.
+     * |        |          |1 = CAN1 controller reset.
+     * |[27]    |USBDRST   |USBD Controller Reset
+     * |        |          |0 = USBD controller normal operation.
+     * |        |          |1 = USBD controller reset.
+     * |[28]    |EADCRST   |EADC Controller Reset
+     * |        |          |0 = EADC controller normal operation.
+     * |        |          |1 = EADC controller reset.
+     * |[29]    |I2S0RST   |I2S0 Controller Reset
+     * |        |          |0 = I2S0 controller normal operation.
+     * |        |          |1 = I2S0 controller reset.
+     * @var SYS_T::IPRST2
+     * Offset: 0x10  Peripheral Reset Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SC0RST    |SC0 Controller Reset
+     * |        |          |0 = SC0 controller normal operation.
+     * |        |          |1 = SC0 controller reset.
+     * |[1]     |SC1RST    |SC1 Controller Reset
+     * |        |          |0 = SC1 controller normal operation.
+     * |        |          |1 = SC1 controller reset.
+     * |[2]     |SC2RST    |SC2 Controller Reset
+     * |        |          |0 = SC2 controller normal operation.
+     * |        |          |1 = SC2 controller reset.
+     * |[6]     |SPI4RST   |SPI4 Controller Reset
+     * |        |          |0 = SPI4 controller normal operation.
+     * |        |          |1 = SPI4 controller reset.
+     * |[8]     |USCI0RST  |USCI0 Controller Reset
+     * |        |          |0 = USCI0 controller normal operation.
+     * |        |          |1 = USCI0 controller reset.
+     * |[9]     |USCI1RST  |USCI1 Controller Reset
+     * |        |          |0 = USCI1 controller normal operation.
+     * |        |          |1 = USCI1 controller reset.
+     * |[12]    |DACRST    |DAC Controller Reset
+     * |        |          |0 = DAC controller normal operation.
+     * |        |          |1 = DAC controller reset.
+     * |[16]    |EPWM0RST   |EPWM0 Controller Reset
+     * |        |          |0 = EPWM0 controller normal operation.
+     * |        |          |1 = EPWM0 controller reset.
+     * |[17]    |EPWM1RST   |EPWM1 Controller Reset
+     * |        |          |0 = EPWM1 controller normal operation.
+     * |        |          |1 = EPWM1 controller reset.
+     * |[18]    |BPWM0RST  |BPWM0 Controller Reset
+     * |        |          |0 = BPWM0 controller normal operation.
+     * |        |          |1 = BPWM0 controller reset.
+     * |[19]    |BPWM1RST  |BPWM1 Controller Reset
+     * |        |          |0 = BPWM1 controller normal operation.
+     * |        |          |1 = BPWM1 controller reset.
+     * |[22]    |QEI0RST   |QEI0 Controller Reset
+     * |        |          |0 = QEI0 controller normal operation.
+     * |        |          |1 = QEI0 controller reset.
+     * |[23]    |QEI1RST   |QEI1 Controller Reset
+     * |        |          |0 = QEI1 controller normal operation.
+     * |        |          |1 = QEI1 controller reset.
+     * |[26]    |ECAP0RST  |ECAP0 Controller Reset
+     * |        |          |0 = ECAP0 controller normal operation.
+     * |        |          |1 = ECAP0 controller reset.
+     * |[27]    |ECAP1RST  |ECAP1 Controller Reset
+     * |        |          |0 = ECAP1 controller normal operation.
+     * |        |          |1 = ECAP1 controller reset.
+     * |[30]    |OPARST    |OP Amplifier (OPA) Controller Reset
+     * |        |          |0 = OPA controller normal operation.
+     * |        |          |1 = OPA controller reset.
+     * @var SYS_T::BODCTL
+     * Offset: 0x18  Brown-Out Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BODEN     |Brown-out Detector Enable Bit (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]).
+     * |        |          |0 = Brown-out Detector function Disabled.
+     * |        |          |1 = Brown-out Detector function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |BODRSTEN  |Brown-out Reset Enable Bit (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+     * |        |          |0 = Brown-out INTERRUPT function Enabled.
+     * |        |          |1 = Brown-out RESET function Enabled.
+     * |        |          |Note1:
+     * |        |          |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+     * |        |          |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high
+     * |        |          |BOD interrupt will keep till to the BODEN set to 0
+     * |        |          |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |BODIF     |Brown-out Detector Interrupt Flag
+     * |        |          |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+     * |        |          |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |BODLPM    |Brown-out Detector Low Power Mode (Write Protect)
+     * |        |          |0 = BOD operate in normal mode (default).
+     * |        |          |1 = BOD Low Power mode Enabled.
+     * |        |          |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |BODOUT    |Brown-out Detector Output Status
+     * |        |          |0 = Brown-out Detector output status is 0.
+     * |        |          |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+     * |        |          |1 = Brown-out Detector output status is 1.
+     * |        |          |It means the detected voltage is lower than BODVL setting
+     * |        |          |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
+     * |[7]     |LVREN     |Low Voltage Reset Enable Bit (Write Protect)
+     * |        |          |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting
+     * |        |          |LVR function is enabled by default.
+     * |        |          |0 = Low Voltage Reset function Disabled.
+     * |        |          |1 = Low Voltage Reset function Enabled.
+     * |        |          |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10:8]  |BODDGSEL  |Brown-out Detector Output De-glitch Time Select (Write Protect)
+     * |        |          |000 = BOD output is sampled by RC10K clock.
+     * |        |          |001 = 4 system clock (HCLK).
+     * |        |          |010 = 8 system clock (HCLK).
+     * |        |          |011 = 16 system clock (HCLK).
+     * |        |          |100 = 32 system clock (HCLK).
+     * |        |          |101 = 64 system clock (HCLK).
+     * |        |          |110 = 128 system clock (HCLK).
+     * |        |          |111 = 256 system clock (HCLK).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[14:12] |LVRDGSEL  |LVR Output De-glitch Time Select (Write Protect)
+     * |        |          |000 = Without de-glitch function.
+     * |        |          |001 = 4 system clock (HCLK).
+     * |        |          |010 = 8 system clock (HCLK).
+     * |        |          |011 = 16 system clock (HCLK).
+     * |        |          |100 = 32 system clock (HCLK).
+     * |        |          |101 = 64 system clock (HCLK).
+     * |        |          |110 = 128 system clock (HCLK).
+     * |        |          |111 = 256 system clock (HCLK).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[18:16] |BODVL     |Brown-out Detector Threshold Voltage Selection (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).
+     * |        |          |000 = Brown-Out Detector threshold voltage is 1.6V.
+     * |        |          |001 = Brown-Out Detector threshold voltage is 1.8V.
+     * |        |          |010 = Brown-Out Detector threshold voltage is 2.0V.
+     * |        |          |011 = Brown-Out Detector threshold voltage is 2.2V.
+     * |        |          |100 = Brown-Out Detector threshold voltage is 2.4V.
+     * |        |          |101 = Brown-Out Detector threshold voltage is 2.6V.
+     * |        |          |110 = Brown-Out Detector threshold voltage is 2.8V.
+     * |        |          |111 = Brown-Out Detector threshold voltage is 3.0V.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::IVSCTL
+     * Offset: 0x1C  Internal Voltage Source Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VTEMPEN   |Temperature Sensor Enable Bit
+     * |        |          |This bit is used to enable/disable temperature sensor function.
+     * |        |          |0 = Temperature sensor function Disabled (default).
+     * |        |          |1 = Temperature sensor function Enabled.
+     * |        |          |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
+     * |[1]     |VBATUGEN  |VBAT Unity Gain Buffer Enable Bit
+     * |        |          |This bit is used to enable/disable VBAT unity gain buffer function.
+     * |        |          |0 = VBAT unity gain buffer function Disabled (default).
+     * |        |          |1 = VBAT unity gain buffer function Enabled.
+     * |        |          |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
+     * @var SYS_T::PORCTL
+     * Offset: 0x24  Power-On-Reset Controller Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |POROFF    |Power-on Reset Enable Bit (Write Protect)
+     * |        |          |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again
+     * |        |          |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+     * |        |          |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+     * |        |          |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::VREFCTL
+     * Offset: 0x28  VREF Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |VREFCTL   |VREF Control Bits (Write Protect)
+     * |        |          |00000 = VREF is from external pin.
+     * |        |          |00011 = VREF is internal 1.6V.
+     * |        |          |00111 = VREF is internal 2.0V.
+     * |        |          |01011 = VREF is internal 2.5V.
+     * |        |          |01111 = VREF is internal 3.0V.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7:6]   |PRELOAD_SEL|Pre-load Timing Selection.
+     * |        |          |00 = pre-load time is 60us for 0.1uF Capacitor.
+     * |        |          |01 = pre-load time is 310us for 1uF Capacitor.
+     * |        |          |10 = pre-load time is 1270us for 4.7uF Capacitor.
+     * |        |          |11 = pre-load time is 2650us for 10uF Capacitor.
+     * @var SYS_T::USBPHY
+     * Offset: 0x2C  USB PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |USBROLE   |USB Role Option (Write Protect)
+     * |        |          |These two bits are used to select the role of USB.
+     * |        |          |00 = Standard USB Device mode.
+     * |        |          |01 = Standard USB Host mode.
+     * |        |          |10 = ID dependent mode.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |SBO       |Note: This bit must always be kept 1. If set to 0, the result is unpredictable
+     * |[8]     |USBEN     |USB PHY Enable (Write Protect)
+     * |        |          |This bit is used to enable/disable USB PHY.
+     * |        |          |0 = USB PHY Disabled.
+     * |        |          |1 = USB PHY Enabled.
+     * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect)
+     * |        |          |These two bits are used to select the role of HSUSB
+     * |        |          |00 = Standard HSUSB Device mode.
+     * |        |          |01 = Standard HSUSB Host mode.
+     * |        |          |10 = ID dependent mode.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[24]    |HSUSBEN   |HSUSB PHY Enable (Write Protect)
+     * |        |          |This bit is used to enable/disable HSUSB PHY.
+     * |        |          |0 = HSUSB PHY Disabled.
+     * |        |          |1 = HSUSB PHY Enabled.
+     * |[25]    |HSUSBACT  |HSUSB PHY Active Control
+     * |        |          |This bit is used to control HSUSB PHY at reset state or active state.
+     * |        |          |0 = HSUSB PHY at reset state.
+     * |        |          |1 = HSUSB PHY at active state.
+     * |        |          |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
+     * @var SYS_T::GPA_MFPL
+     * Offset: 0x30  GPIOA Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PA0MFP    |PA.0 Multi-function Pin Selection
+     * |[7:4]   |PA1MFP    |PA.1 Multi-function Pin Selection
+     * |[11:8]  |PA2MFP    |PA.2 Multi-function Pin Selection
+     * |[15:12] |PA3MFP    |PA.3 Multi-function Pin Selection
+     * |[19:16] |PA4MFP    |PA.4 Multi-function Pin Selection
+     * |[23:20] |PA5MFP    |PA.5 Multi-function Pin Selection
+     * |[27:24] |PA6MFP    |PA.6 Multi-function Pin Selection
+     * |[31:28] |PA7MFP    |PA.7 Multi-function Pin Selection
+     * @var SYS_T::GPA_MFPH
+     * Offset: 0x34  GPIOA High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PA8MFP    |PA.8 Multi-function Pin Selection
+     * |[7:4]   |PA9MFP    |PA.9 Multi-function Pin Selection
+     * |[11:8]  |PA10MFP   |PA.10 Multi-function Pin Selection
+     * |[15:12] |PA11MFP   |PA.11 Multi-function Pin Selection
+     * |[19:16] |PA12MFP   |PA.12 Multi-function Pin Selection
+     * |[23:20] |PA13MFP   |PA.13 Multi-function Pin Selection
+     * |[27:24] |PA14MFP   |PA.14 Multi-function Pin Selection
+     * |[31:28] |PA15MFP   |PA.15 Multi-function Pin Selection
+     * @var SYS_T::GPB_MFPL
+     * Offset: 0x38  GPIOB Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PB0MFP    |PB.0 Multi-function Pin Selection
+     * |[7:4]   |PB1MFP    |PB.1 Multi-function Pin Selection
+     * |[11:8]  |PB2MFP    |PB.2 Multi-function Pin Selection
+     * |[15:12] |PB3MFP    |PB.3 Multi-function Pin Selection
+     * |[19:16] |PB4MFP    |PB.4 Multi-function Pin Selection
+     * |[23:20] |PB5MFP    |PB.5 Multi-function Pin Selection
+     * |[27:24] |PB6MFP    |PB.6 Multi-function Pin Selection
+     * |[31:28] |PB7MFP    |PB.7 Multi-function Pin Selection
+     * @var SYS_T::GPB_MFPH
+     * Offset: 0x3C  GPIOB High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PB8MFP    |PB.8 Multi-function Pin Selection
+     * |[7:4]   |PB9MFP    |PB.9 Multi-function Pin Selection
+     * |[11:8]  |PB10MFP   |PB.10 Multi-function Pin Selection
+     * |[15:12] |PB11MFP   |PB.11 Multi-function Pin Selection
+     * |[19:16] |PB12MFP   |PB.12 Multi-function Pin Selection
+     * |[23:20] |PB13MFP   |PB.13 Multi-function Pin Selection
+     * |[27:24] |PB14MFP   |PB.14 Multi-function Pin Selection
+     * |[31:28] |PB15MFP   |PB.15 Multi-function Pin Selection
+     * @var SYS_T::GPC_MFPL
+     * Offset: 0x40  GPIOC Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PC0MFP    |PC.0 Multi-function Pin Selection
+     * |[7:4]   |PC1MFP    |PC.1 Multi-function Pin Selection
+     * |[11:8]  |PC2MFP    |PC.2 Multi-function Pin Selection
+     * |[15:12] |PC3MFP    |PC.3 Multi-function Pin Selection
+     * |[19:16] |PC4MFP    |PC.4 Multi-function Pin Selection
+     * |[23:20] |PC5MFP    |PC.5 Multi-function Pin Selection
+     * |[27:24] |PC6MFP    |PC.6 Multi-function Pin Selection
+     * |[31:28] |PC7MFP    |PC.7 Multi-function Pin Selection
+     * @var SYS_T::GPC_MFPH
+     * Offset: 0x44  GPIOC High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PC8MFP    |PC.8 Multi-function Pin Selection
+     * |[7:4]   |PC9MFP    |PC.9 Multi-function Pin Selection
+     * |[11:8]  |PC10MFP   |PC.10 Multi-function Pin Selection
+     * |[15:12] |PC11MFP   |PC.11 Multi-function Pin Selection
+     * |[19:16] |PC12MFP   |PC.12 Multi-function Pin Selection
+     * |[23:20] |PC13MFP   |PC.13 Multi-function Pin Selection
+     * |[27:24] |PC14MFP   |PC.14 Multi-function Pin Selection
+     * |[31:28] |PC15MFP   |PC.15 Multi-function Pin Selection
+     * @var SYS_T::GPD_MFPL
+     * Offset: 0x48  GPIOD Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PD0MFP    |PD.0 Multi-function Pin Selection
+     * |[7:4]   |PD1MFP    |PD.1 Multi-function Pin Selection
+     * |[11:8]  |PD2MFP    |PD.2 Multi-function Pin Selection
+     * |[15:12] |PD3MFP    |PD.3 Multi-function Pin Selection
+     * |[19:16] |PD4MFP    |PD.4 Multi-function Pin Selection
+     * |[23:20] |PD5MFP    |PD.5 Multi-function Pin Selection
+     * |[27:24] |PD6MFP    |PD.6 Multi-function Pin Selection
+     * |[31:28] |PD7MFP    |PD.7 Multi-function Pin Selection
+     * @var SYS_T::GPD_MFPH
+     * Offset: 0x4C  GPIOD High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PD8MFP    |PD.8 Multi-function Pin Selection
+     * |[7:4]   |PD9MFP    |PD.9 Multi-function Pin Selection
+     * |[11:8]  |PD10MFP   |PD.10 Multi-function Pin Selection
+     * |[15:12] |PD11MFP   |PD.11 Multi-function Pin Selection
+     * |[19:16] |PD12MFP   |PD.12 Multi-function Pin Selection
+     * |[23:20] |PD13MFP   |PD.13 Multi-function Pin Selection
+     * |[27:24] |PD14MFP   |PD.14 Multi-function Pin Selection
+     * |[31:28] |PD15MFP   |PD.15 Multi-function Pin Selection
+     * @var SYS_T::GPE_MFPL
+     * Offset: 0x50  GPIOE Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PE0MFP    |PE.0 Multi-function Pin Selection
+     * |[7:4]   |PE1MFP    |PE.1 Multi-function Pin Selection
+     * |[11:8]  |PE2MFP    |PE.2 Multi-function Pin Selection
+     * |[15:12] |PE3MFP    |PE.3 Multi-function Pin Selection
+     * |[19:16] |PE4MFP    |PE.4 Multi-function Pin Selection
+     * |[23:20] |PE5MFP    |PE.5 Multi-function Pin Selection
+     * |[27:24] |PE6MFP    |PE.6 Multi-function Pin Selection
+     * |[31:28] |PE7MFP    |PE.7 Multi-function Pin Selection
+     * @var SYS_T::GPE_MFPH
+     * Offset: 0x54  GPIOE High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PE8MFP    |PE.8 Multi-function Pin Selection
+     * |[7:4]   |PE9MFP    |PE.9 Multi-function Pin Selection
+     * |[11:8]  |PE10MFP   |PE.10 Multi-function Pin Selection
+     * |[15:12] |PE11MFP   |PE.11 Multi-function Pin Selection
+     * |[19:16] |PE12MFP   |PE.12 Multi-function Pin Selection
+     * |[23:20] |PE13MFP   |PE.13 Multi-function Pin Selection
+     * |[27:24] |PE14MFP   |PE.14 Multi-function Pin Selection
+     * |[31:28] |PE15MFP   |PE.15 Multi-function Pin Selection
+     * @var SYS_T::GPF_MFPL
+     * Offset: 0x58  GPIOF Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PF0MFP    |PF.0 Multi-function Pin Selection
+     * |[7:4]   |PF1MFP    |PF.1 Multi-function Pin Selection
+     * |[11:8]  |PF2MFP    |PF.2 Multi-function Pin Selection
+     * |[15:12] |PF3MFP    |PF.3 Multi-function Pin Selection
+     * |[19:16] |PF4MFP    |PF.4 Multi-function Pin Selection
+     * |[23:20] |PF5MFP    |PF.5 Multi-function Pin Selection
+     * |[27:24] |PF6MFP    |PF.6 Multi-function Pin Selection
+     * |[31:28] |PF7MFP    |PF.7 Multi-function Pin Selection
+     * @var SYS_T::GPF_MFPH
+     * Offset: 0x5C  GPIOF High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PF8MFP    |PF.8 Multi-function Pin Selection
+     * |[7:4]   |PF9MFP    |PF.9 Multi-function Pin Selection
+     * |[11:8]  |PF10MFP   |PF.10 Multi-function Pin Selection
+     * |[15:12] |PF11MFP   |PF.11 Multi-function Pin Selection
+     * |[19:16] |PF12MFP   |PF.12 Multi-function Pin Selection
+     * |[23:20] |PF13MFP   |PF.13 Multi-function Pin Selection
+     * |[27:24] |PF14MFP   |PF.14 Multi-function Pin Selection
+     * |[31:28] |PF15MFP   |PF.15 Multi-function Pin Selection
+     * @var SYS_T::GPG_MFPL
+     * Offset: 0x60  GPIOG Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PG0MFP    |PG.0 Multi-function Pin Selection
+     * |[7:4]   |PG1MFP    |PG.1 Multi-function Pin Selection
+     * |[11:8]  |PG2MFP    |PG.2 Multi-function Pin Selection
+     * |[15:12] |PG3MFP    |PG.3 Multi-function Pin Selection
+     * |[19:16] |PG4MFP    |PG.4 Multi-function Pin Selection
+     * |[23:20] |PG5MFP    |PG.5 Multi-function Pin Selection
+     * |[27:24] |PG6MFP    |PG.6 Multi-function Pin Selection
+     * |[31:28] |PG7MFP    |PG.7 Multi-function Pin Selection
+     * @var SYS_T::GPG_MFPH
+     * Offset: 0x64  GPIOG High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PG8MFP    |PG.8 Multi-function Pin Selection
+     * |[7:4]   |PG9MFP    |PG.9 Multi-function Pin Selection
+     * |[11:8]  |PG10MFP   |PG.10 Multi-function Pin Selection
+     * |[15:12] |PG11MFP   |PG.11 Multi-function Pin Selection
+     * |[19:16] |PG12MFP   |PG.12 Multi-function Pin Selection
+     * |[23:20] |PG13MFP   |PG.13 Multi-function Pin Selection
+     * |[27:24] |PG14MFP   |PG.14 Multi-function Pin Selection
+     * |[31:28] |PG15MFP   |PG.15 Multi-function Pin Selection
+     * @var SYS_T::GPH_MFPL
+     * Offset: 0x68  GPIOH Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PH0MFP    |PH.0 Multi-function Pin Selection
+     * |[7:4]   |PH1MFP    |PH.1 Multi-function Pin Selection
+     * |[11:8]  |PH2MFP    |PH.2 Multi-function Pin Selection
+     * |[15:12] |PH3MFP    |PH.3 Multi-function Pin Selection
+     * |[19:16] |PH4MFP    |PH.4 Multi-function Pin Selection
+     * |[23:20] |PH5MFP    |PH.5 Multi-function Pin Selection
+     * |[27:24] |PH6MFP    |PH.6 Multi-function Pin Selection
+     * |[31:28] |PH7MFP    |PH.7 Multi-function Pin Selection
+     * @var SYS_T::GPH_MFPH
+     * Offset: 0x6C  GPIOH High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PH8MFP    |PH.8 Multi-function Pin Selection
+     * |[7:4]   |PH9MFP    |PH.9 Multi-function Pin Selection
+     * |[11:8]  |PH10MFP   |PH.10 Multi-function Pin Selection
+     * |[15:12] |PH11MFP   |PH.11 Multi-function Pin Selection
+     * |[19:16] |PH12MFP   |PH.12 Multi-function Pin Selection
+     * |[23:20] |PH13MFP   |PH.13 Multi-function Pin Selection
+     * |[27:24] |PH14MFP   |PH.14 Multi-function Pin Selection
+     * |[31:28] |PH15MFP   |PH.15 Multi-function Pin Selection
+     * @var SYS_T::GPA_MFOS
+     * Offset: 0x80  GPIOA Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPB_MFOS
+     * Offset: 0x84  GPIOB Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPC_MFOS
+     * Offset: 0x88  GPIOC Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPD_MFOS
+     * Offset: 0x8C  GPIOD Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPE_MFOS
+     * Offset: 0x90  GPIOE Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPF_MFOS
+     * Offset: 0x94  GPIOF Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPG_MFOS
+     * Offset: 0x98  GPIOG Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::GPH_MFOS
+     * Offset: 0x9C  GPIOH Multiple Function Output Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MFOS0     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[1]     |MFOS1     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[2]     |MFOS2     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[3]     |MFOS3     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[4]     |MFOS4     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[5]     |MFOS5     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[6]     |MFOS6     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[7]     |MFOS7     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[8]     |MFOS8     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[9]     |MFOS9     |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[10]    |MFOS10    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[11]    |MFOS11    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[12]    |MFOS12    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[13]    |MFOS13    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[14]    |MFOS14    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[15]    |MFOS15    |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+     * |        |          |This bit used to select multiple function pin output mode type for Px.n pin
+     * |        |          |0 = Multiple function pin output mode type is Push-pull mode.
+     * |        |          |1 = Multiple function pin output mode type is Open-drain mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var SYS_T::SRAM_INTCTL
+     * Offset: 0xC0  System SRAM Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PERRIEN   |SRAM Parity Check Error Interrupt Enable Bit
+     * |        |          |0 = SRAM parity check error interrupt Disabled.
+     * |        |          |1 = SRAM parity check error interrupt Enabled.
+     * @var SYS_T::SRAM_STATUS
+     * Offset: 0xC4  System SRAM Parity Error Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PERRIF    |SRAM Parity Check Error Flag
+     * |        |          |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
+     * |        |          |0 = No System SRAM parity error.
+     * |        |          |1 = System SRAM parity error occur.
+     * @var SYS_T::SRAM_ERRADDR
+     * Offset: 0xC8  System SRAM Parity Check Error Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ERRADDR   |System SRAM Parity Error Address
+     * |        |          |This register shows system SRAM parity error byte address.
+     * @var SYS_T::SRAM_BISTCTL
+     * Offset: 0xD0  System SRAM BIST Test Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SRBIST0   |SRAM Bank0 BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for SRAM bank0.
+     * |        |          |0 = system SRAM bank0 BIST Disabled.
+     * |        |          |1 = system SRAM bank0 BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |SRBIST1   |SRAM Bank1 BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for SRAM bank1.
+     * |        |          |0 = system SRAM bank1 BIST Disabled.
+     * |        |          |1 = system SRAM bank1 BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |CRBIST    |CACHE BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for CACHE RAM
+     * |        |          |0 = system CACHE BIST Disabled.
+     * |        |          |1 = system CACHE BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |CANBIST   |CAN BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for CAN RAM
+     * |        |          |0 = system CAN BIST Disabled.
+     * |        |          |1 = system CAN BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |USBBIST   |USB BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for USB RAM
+     * |        |          |0 = system USB BIST Disabled.
+     * |        |          |1 = system USB BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |SPIMBIST  |SPIM BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for SPIM RAM
+     * |        |          |0 = system SPIM BIST Disabled.
+     * |        |          |1 = system SPIM BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |EMCBIST   |EMC BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for EMC RAM
+     * |        |          |0 = system EMC BIST Disabled.
+     * |        |          |1 = system EMC BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |PDMABIST  |PDMA BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for PDMA RAM
+     * |        |          |0 = system PDMA BIST Disabled.
+     * |        |          |1 = system PDMA BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for HSUSBD RAM
+     * |        |          |0 = system HSUSBD BIST Disabled.
+     * |        |          |1 = system HSUSBD BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[9]     |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect)
+     * |        |          |This bit enables BIST test for HSUSBH RAM
+     * |        |          |0 = system HSUSBH BIST Disabled.
+     * |        |          |1 = system HSUSBH BIST Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |SRB0S0    |SRAM Bank0 Section 0 BIST Select (Write Protect)
+     * |        |          |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank0 section 0 is deselected when doing bist test.
+     * |        |          |1 = SRAM bank0 section 0 is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+     * |[17]    |SRB0S1    |SRAM Bank0 Section 1 BIST Select (Write Protect)
+     * |        |          |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank0 section 1 is deselected when doing bist test.
+     * |        |          |1 = SRAM bank0 section 1 is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+     * |[18]    |SRB1S0    |SRAM Bank1 Section 0 BIST Select (Write Protect)
+     * |        |          |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 first 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 first 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * |[19]    |SRB1S1    |SRAM Bank1 Section 1 BIST Select (Write Protect)
+     * |        |          |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 second 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 second 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * |[20]    |SRB1S2    |SRAM Bank1 Section 0 BIST Select (Write Protect)
+     * |        |          |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 third 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 third 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * |[21]    |SRB1S3    |SRAM Bank1 Section 1 BIST Select (Write Protect)
+     * |        |          |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 fourth 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * |[22]    |SRB1S4    |SRAM Bank1 Section 0 BIST Select (Write Protect)
+     * |        |          |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 fifth 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * |[23]    |SRB1S5    |SRAM Bank1 Section 1 BIST Select (Write Protect)
+     * |        |          |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test.
+     * |        |          |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test.
+     * |        |          |1 = SRAM bank1 sixth 16KB section is selected when doing bist test.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+     * @var SYS_T::SRAM_BISTSTS
+     * Offset: 0xD4  System SRAM BIST Test Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SRBISTEF0 |1st System SRAM BIST Fail Flag
+     * |        |          |0 = 1st system SRAM BIST test pass.
+     * |        |          |1 = 1st system SRAM BIST test fail.
+     * |[1]     |SRBISTEF1 |2nd System SRAM BIST Fail Flag
+     * |        |          |0 = 2nd system SRAM BIST test pass.
+     * |        |          |1 = 2nd system SRAM BIST test fail.
+     * |[2]     |CRBISTEF  |CACHE SRAM BIST Fail Flag
+     * |        |          |0 = System CACHE RAM BIST test pass.
+     * |        |          |1 = System CACHE RAM BIST test fail.
+     * |[3]     |CANBEF    |CAN SRAM BIST Fail Flag
+     * |        |          |0 = CAN SRAM BIST test pass.
+     * |        |          |1 = CAN SRAM BIST test fail.
+     * |[4]     |USBBEF    |USB SRAM BIST Fail Flag
+     * |        |          |0 = USB SRAM BIST test pass.
+     * |        |          |1 = USB SRAM BIST test fail.
+     * |[16]    |SRBEND0   |1st SRAM BIST Test Finish
+     * |        |          |0 = 1st system SRAM BIST active.
+     * |        |          |1 =1st system SRAM BIST finish.
+     * |[17]    |SRBEND1   |2nd SRAM BIST Test Finish
+     * |        |          |0 = 2nd system SRAM BIST is active.
+     * |        |          |1 = 2nd system SRAM BIST finish.
+     * |[18]    |CRBEND    |CACHE SRAM BIST Test Finish
+     * |        |          |0 = System CACHE RAM BIST is active.
+     * |        |          |1 = System CACHE RAM BIST test finish.
+     * |[19]    |CANBEND   |CAN SRAM BIST Test Finish
+     * |        |          |0 = CAN SRAM BIST is active.
+     * |        |          |1 = CAN SRAM BIST test finish.
+     * |[20]    |USBBEND   |USB SRAM BIST Test Finish
+     * |        |          |0 = USB SRAM BIST is active.
+     * |        |          |1 = USB SRAM BIST test finish.
+     * @var SYS_T::IRCTCTL
+     * Offset: 0xF0  HIRC Trim Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |FREQSEL   |Trim Frequency Selection
+     * |        |          |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.
+     * |        |          |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+     * |        |          |00 = Disable HIRC auto trim function.
+     * |        |          |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
+     * |        |          |10 = Reserved..
+     * |        |          |11 = Reserved.
+     * |[5:4]   |LOOPSEL   |Trim Calculation Loop Selection
+     * |        |          |This field defines that trim value calculation is based on how many reference clocks.
+     * |        |          |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+     * |        |          |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+     * |        |          |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+     * |        |          |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+     * |        |          |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+     * |[7:6]   |RETRYCNT  |Trim Value Update Limitation Count
+     * |        |          |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+     * |        |          |Once the HIRC locked, the internal trim value update counter will be reset.
+     * |        |          |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+     * |        |          |00 = Trim retry count limitation is 64 loops.
+     * |        |          |01 = Trim retry count limitation is 128 loops.
+     * |        |          |10 = Trim retry count limitation is 256 loops.
+     * |        |          |11 = Trim retry count limitation is 512 loops.
+     * |[8]     |CESTOPEN  |Clock Error Stop Enable Bit
+     * |        |          |0 = The trim operation is keep going if clock is inaccuracy.
+     * |        |          |1 = The trim operation is stopped if clock is inaccuracy.
+     * |[10]    |REFCKSEL  |Reference Clock Selection
+     * |        |          |0 = HIRC trim reference clock is from LXT (32.768 kHz).
+     * |        |          |1 = HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet.
+     * |        |          |Note: HIRC trim reference clock is 20Khz in test mode.
+     * @var SYS_T::IRCTIEN
+     * Offset: 0xF4  HIRC Trim Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TFAILIEN  |Trim Failure Interrupt Enable Bit
+     * |        |          |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
+     * |        |          |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+     * |        |          |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+     * |[2]     |CLKEIEN   |Clock Error Interrupt Enable Bit
+     * |        |          |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+     * |        |          |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+     * @var SYS_T::IRCTISTS
+     * Offset: 0xF8  HIRC Trim Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FREQLOCK  |HIRC Frequency Lock Status
+     * |        |          |This bit indicates the HIRC frequency is locked.
+     * |        |          |This is a status bit and doesn't trigger any interrupt
+     * |        |          |Write 1 to clear this to 0
+     * |        |          |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+     * |        |          |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.
+     * |        |          |1 = The internal high-speed oscillator frequency locked at 12 MHz.
+     * |[1]     |TFAILIF   |Trim Failure Interrupt Status
+     * |        |          |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked
+     * |        |          |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+     * |        |          |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Trim value update limitation count does not reach.
+     * |        |          |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+     * |[2]     |CLKERRIF  |Clock Error Interrupt Status
+     * |        |          |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy.
+     * |        |          |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
+     * |        |          |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Clock frequency is accuracy.
+     * |        |          |1 = Clock frequency is inaccuracy.
+     * @var SYS_T::REGLCTL
+     * Offset: 0x100  Register Lock Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |REGLCTL   |Register Lock Control Code (Write Only)
+     * |        |          |Some registers have write-protection function
+     * |        |          |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
+     * |        |          |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+     * |        |          |Register Lock Control Code (Read Only)
+     * |        |          |0 = Write-protection Enabled for writing protected registers
+     * |        |          |Any write to the protected register is ignored.
+     * |        |          |1 = Write-protection Disabled for writing protected registers.
+     * @var SYS_T::PLCTL
+     * Offset: 0x1F8  Power Level Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |PLSEL     |Power Level Select(Write Protect)
+     * |        |          |00 = Set core voltage to 1.26V.
+     * |        |          |01 = Set core voltage to 1.2V.
+     * |        |          |10 = Set core voltage to 0.9V.
+     * |        |          |11 = Reserved.
+     * |[21:16] |LVSSTEP   |LDO Voltage Scaling Step(Write Protect)
+     * |        |          |The LVSSTEP value is LDO voltage rising step.
+     * |        |          |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
+     * |[31:24] |LVSPRD    |LDO Voltage Scaling Period(Write Protect)
+     * |        |          |The LVSPRD value is the period of each LDO voltage rising step.
+     * |        |          |LDO voltage scaling period = (LVSPRD + 1) * 1us.
+     * @var SYS_T::PLSTS
+     * Offset: 0x1FC  Power Level Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PLCBUSY   |Power Level Change Busy Bit (Read Only)
+     * |        |          |This bit is set by hardware when core voltage is changing
+     * |        |          |After core voltage change is completed, this bit will be cleared automatically by hardware.
+     * |        |          |0 = Core voltage change is completed.
+     * |        |          |1 = Core voltage change is ongoing.
+     * |[9:8]   |PLSTATUS  |Power Level Status (Read Only)
+     * |        |          |00 = Power level is PL0.
+     * |        |          |01 = Power level is PL1.
+     * |        |          |Others = Reserved.
+     * @var SYS_T::AHBMCTL
+     * Offset: 0x400  AHB Bus Matrix Priority Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INTACTEN  |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect)
+     * |        |          |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix
+     * |        |          |0 = Run robin mode.
+     * |        |          |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     */
+    __I  uint32_t PDID;                  /*!< [0x0000] Part Device Identification Number Register                       */
+    __IO uint32_t RSTSTS;                /*!< [0x0004] System Reset Status Register                                     */
+    __IO uint32_t IPRST0;                /*!< [0x0008] Peripheral  Reset Control Register 0                             */
+    __IO uint32_t IPRST1;                /*!< [0x000c] Peripheral Reset Control Register 1                              */
+    __IO uint32_t IPRST2;                /*!< [0x0010] Peripheral Reset Control Register 2                              */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[1];
+    /** @endcond */
+    __IO uint32_t BODCTL;                /*!< [0x0018] Brown-Out Detector Control Register                              */
+    __IO uint32_t IVSCTL;                /*!< [0x001c] Internal Voltage Source Control Register                         */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE1[1];
+    /** @endcond */
+    __IO uint32_t PORCTL;                /*!< [0x0024] Power-On-Reset Controller Register                               */
+    __IO uint32_t VREFCTL;               /*!< [0x0028] VREF Control Register                                            */
+    __IO uint32_t USBPHY;                /*!< [0x002c] USB PHY Control Register                                         */
+    __IO uint32_t GPA_MFPL;              /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPA_MFPH;              /*!< [0x0034] GPIOA High Byte Multiple Function Control Register               */
+    __IO uint32_t GPB_MFPL;              /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPB_MFPH;              /*!< [0x003c] GPIOB High Byte Multiple Function Control Register               */
+    __IO uint32_t GPC_MFPL;              /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPC_MFPH;              /*!< [0x0044] GPIOC High Byte Multiple Function Control Register               */
+    __IO uint32_t GPD_MFPL;              /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPD_MFPH;              /*!< [0x004c] GPIOD High Byte Multiple Function Control Register               */
+    __IO uint32_t GPE_MFPL;              /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPE_MFPH;              /*!< [0x0054] GPIOE High Byte Multiple Function Control Register               */
+    __IO uint32_t GPF_MFPL;              /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPF_MFPH;              /*!< [0x005c] GPIOF High Byte Multiple Function Control Register               */
+    __IO uint32_t GPG_MFPL;              /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPG_MFPH;              /*!< [0x0064] GPIOG High Byte Multiple Function Control Register               */
+    __IO uint32_t GPH_MFPL;              /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPH_MFPH;              /*!< [0x006c] GPIOH High Byte Multiple Function Control Register               */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE2[4];
+    /** @endcond */
+    __IO uint32_t GPA_MFOS;              /*!< [0x0080] GPIOA Multiple Function Output Select Register                   */
+    __IO uint32_t GPB_MFOS;              /*!< [0x0084] GPIOB Multiple Function Output Select Register                   */
+    __IO uint32_t GPC_MFOS;              /*!< [0x0088] GPIOC Multiple Function Output Select Register                   */
+    __IO uint32_t GPD_MFOS;              /*!< [0x008c] GPIOD Multiple Function Output Select Register                   */
+    __IO uint32_t GPE_MFOS;              /*!< [0x0090] GPIOE Multiple Function Output Select Register                   */
+    __IO uint32_t GPF_MFOS;              /*!< [0x0094] GPIOF Multiple Function Output Select Register                   */
+    __IO uint32_t GPG_MFOS;              /*!< [0x0098] GPIOG Multiple Function Output Select Register                   */
+    __IO uint32_t GPH_MFOS;              /*!< [0x009c] GPIOH Multiple Function Output Select Register                   */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE3[8];
+    /** @endcond */
+    __IO uint32_t SRAM_INTCTL;           /*!< [0x00c0] System SRAM Interrupt Enable Control Register                    */
+    __IO uint32_t SRAM_STATUS;           /*!< [0x00c4] System SRAM Parity Error Status Register                         */
+    __I  uint32_t SRAM_ERRADDR;          /*!< [0x00c8] System SRAM Parity Check Error Address Register                  */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE4[1];
+    /** @endcond */
+    __IO uint32_t SRAM_BISTCTL;          /*!< [0x00d0] System SRAM BIST Test Control Register                           */
+    __I  uint32_t SRAM_BISTSTS;          /*!< [0x00d4] System SRAM BIST Test Status Register                            */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE5[6];
+    /** @endcond */
+    __IO uint32_t IRCTCTL;               /*!< [0x00f0] HIRC Trim Control Register                                       */
+    __IO uint32_t IRCTIEN;               /*!< [0x00f4] HIRC Trim Interrupt Enable Register                              */
+    __IO uint32_t IRCTISTS;              /*!< [0x00f8] HIRC Trim Interrupt Status Register                              */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE6[1];
+    /** @endcond */
+    __IO uint32_t REGLCTL;               /*!< [0x0100] Register Lock Control Register                                   */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE7[61];
+    /** @endcond */
+    __IO uint32_t PLCTL;                 /*!< [0x01f8] Power Level Control Register                                     */
+    __I  uint32_t PLSTS;                 /*!< [0x01fc] Power Level Status Register                                      */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE8[128];
+    /** @endcond */
+    __IO uint32_t AHBMCTL;               /*!< [0x0400] AHB Bus Matrix Priority Control Register                         */
+
+} SYS_T;
+
+/**
+    @addtogroup SYS_CONST SYS Bit Field Definition
+    Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos                (0)                                               /*!< SYS_T::PDID: PDID Position             */
+#define SYS_PDID_PDID_Msk                (0xfffffffful << SYS_PDID_PDID_Pos)               /*!< SYS_T::PDID: PDID Mask                 */
+
+#define SYS_RSTSTS_PORF_Pos              (0)                                               /*!< SYS_T::RSTSTS: PORF Position           */
+#define SYS_RSTSTS_PORF_Msk              (0x1ul << SYS_RSTSTS_PORF_Pos)                    /*!< SYS_T::RSTSTS: PORF Mask               */
+
+#define SYS_RSTSTS_PINRF_Pos             (1)                                               /*!< SYS_T::RSTSTS: PINRF Position          */
+#define SYS_RSTSTS_PINRF_Msk             (0x1ul << SYS_RSTSTS_PINRF_Pos)                   /*!< SYS_T::RSTSTS: PINRF Mask              */
+
+#define SYS_RSTSTS_WDTRF_Pos             (2)                                               /*!< SYS_T::RSTSTS: WDTRF Position          */
+#define SYS_RSTSTS_WDTRF_Msk             (0x1ul << SYS_RSTSTS_WDTRF_Pos)                   /*!< SYS_T::RSTSTS: WDTRF Mask              */
+
+#define SYS_RSTSTS_LVRF_Pos              (3)                                               /*!< SYS_T::RSTSTS: LVRF Position           */
+#define SYS_RSTSTS_LVRF_Msk              (0x1ul << SYS_RSTSTS_LVRF_Pos)                    /*!< SYS_T::RSTSTS: LVRF Mask               */
+
+#define SYS_RSTSTS_BODRF_Pos             (4)                                               /*!< SYS_T::RSTSTS: BODRF Position          */
+#define SYS_RSTSTS_BODRF_Msk             (0x1ul << SYS_RSTSTS_BODRF_Pos)                   /*!< SYS_T::RSTSTS: BODRF Mask              */
+
+#define SYS_RSTSTS_SYSRF_Pos             (5)                                               /*!< SYS_T::RSTSTS: SYSRF Position          */
+#define SYS_RSTSTS_SYSRF_Msk             (0x1ul << SYS_RSTSTS_SYSRF_Pos)                   /*!< SYS_T::RSTSTS: SYSRF Mask              */
+
+#define SYS_RSTSTS_CPURF_Pos             (7)                                               /*!< SYS_T::RSTSTS: CPURF Position          */
+#define SYS_RSTSTS_CPURF_Msk             (0x1ul << SYS_RSTSTS_CPURF_Pos)                   /*!< SYS_T::RSTSTS: CPURF Mask              */
+
+#define SYS_RSTSTS_CPULKRF_Pos           (8)                                               /*!< SYS_T::RSTSTS: CPULKRF Position        */
+#define SYS_RSTSTS_CPULKRF_Msk           (0x1ul << SYS_RSTSTS_CPULKRF_Pos)                 /*!< SYS_T::RSTSTS: CPULKRF Mask            */
+
+#define SYS_IPRST0_CHIPRST_Pos           (0)                                               /*!< SYS_T::IPRST0: CHIPRST Position        */
+#define SYS_IPRST0_CHIPRST_Msk           (0x1ul << SYS_IPRST0_CHIPRST_Pos)                 /*!< SYS_T::IPRST0: CHIPRST Mask            */
+
+#define SYS_IPRST0_CPURST_Pos            (1)                                               /*!< SYS_T::IPRST0: CPURST Position         */
+#define SYS_IPRST0_CPURST_Msk            (0x1ul << SYS_IPRST0_CPURST_Pos)                  /*!< SYS_T::IPRST0: CPURST Mask             */
+
+#define SYS_IPRST0_PDMARST_Pos           (2)                                               /*!< SYS_T::IPRST0: PDMARST Position        */
+#define SYS_IPRST0_PDMARST_Msk           (0x1ul << SYS_IPRST0_PDMARST_Pos)                 /*!< SYS_T::IPRST0: PDMARST Mask            */
+
+#define SYS_IPRST0_EBIRST_Pos            (3)                                               /*!< SYS_T::IPRST0: EBIRST Position         */
+#define SYS_IPRST0_EBIRST_Msk            (0x1ul << SYS_IPRST0_EBIRST_Pos)                  /*!< SYS_T::IPRST0: EBIRST Mask             */
+
+#define SYS_IPRST0_EMACRST_Pos           (5)                                               /*!< SYS_T::IPRST0: EMACRST Position        */
+#define SYS_IPRST0_EMACRST_Msk           (0x1ul << SYS_IPRST0_EMACRST_Pos)                 /*!< SYS_T::IPRST0: EMACRST Mask            */
+
+#define SYS_IPRST0_SDH0RST_Pos           (6)                                               /*!< SYS_T::IPRST0: SDH0RST Position        */
+#define SYS_IPRST0_SDH0RST_Msk           (0x1ul << SYS_IPRST0_SDH0RST_Pos)                 /*!< SYS_T::IPRST0: SDH0RST Mask            */
+
+#define SYS_IPRST0_CRCRST_Pos            (7)                                               /*!< SYS_T::IPRST0: CRCRST Position         */
+#define SYS_IPRST0_CRCRST_Msk            (0x1ul << SYS_IPRST0_CRCRST_Pos)                  /*!< SYS_T::IPRST0: CRCRST Mask             */
+
+#define SYS_IPRST0_HSUSBDRST_Pos         (10)                                              /*!< SYS_T::IPRST0: HSUSBDRST Position      */
+#define SYS_IPRST0_HSUSBDRST_Msk         (0x1ul << SYS_IPRST0_HSUSBDRST_Pos)               /*!< SYS_T::IPRST0: HSUSBDRST Mask          */
+
+#define SYS_IPRST0_CRPTRST_Pos           (12)                                              /*!< SYS_T::IPRST0: CRPTRST Position        */
+#define SYS_IPRST0_CRPTRST_Msk           (0x1ul << SYS_IPRST0_CRPTRST_Pos)                 /*!< SYS_T::IPRST0: CRPTRST Mask            */
+
+#define SYS_IPRST0_SPIMRST_Pos           (14)                                              /*!< SYS_T::IPRST0: SPIMRST Position        */
+#define SYS_IPRST0_SPIMRST_Msk           (0x1ul << SYS_IPRST0_SPIMRST_Pos)                 /*!< SYS_T::IPRST0: SPIMRST Mask            */
+
+#define SYS_IPRST0_USBHRST_Pos           (16)                                              /*!< SYS_T::IPRST0: USBHRST Position        */
+#define SYS_IPRST0_USBHRST_Msk           (0x1ul << SYS_IPRST0_USBHRST_Pos)                 /*!< SYS_T::IPRST0: USBHRST Mask            */
+
+#define SYS_IPRST0_SDH1RST_Pos           (17)                                              /*!< SYS_T::IPRST0: SDH1RST Position        */
+#define SYS_IPRST0_SDH1RST_Msk           (0x1ul << SYS_IPRST0_SDH1RST_Pos)                 /*!< SYS_T::IPRST0: SDH1RST Mask            */
+
+#define SYS_IPRST1_GPIORST_Pos           (1)                                               /*!< SYS_T::IPRST1: GPIORST Position        */
+#define SYS_IPRST1_GPIORST_Msk           (0x1ul << SYS_IPRST1_GPIORST_Pos)                 /*!< SYS_T::IPRST1: GPIORST Mask            */
+
+#define SYS_IPRST1_TMR0RST_Pos           (2)                                               /*!< SYS_T::IPRST1: TMR0RST Position        */
+#define SYS_IPRST1_TMR0RST_Msk           (0x1ul << SYS_IPRST1_TMR0RST_Pos)                 /*!< SYS_T::IPRST1: TMR0RST Mask            */
+
+#define SYS_IPRST1_TMR1RST_Pos           (3)                                               /*!< SYS_T::IPRST1: TMR1RST Position        */
+#define SYS_IPRST1_TMR1RST_Msk           (0x1ul << SYS_IPRST1_TMR1RST_Pos)                 /*!< SYS_T::IPRST1: TMR1RST Mask            */
+
+#define SYS_IPRST1_TMR2RST_Pos           (4)                                               /*!< SYS_T::IPRST1: TMR2RST Position        */
+#define SYS_IPRST1_TMR2RST_Msk           (0x1ul << SYS_IPRST1_TMR2RST_Pos)                 /*!< SYS_T::IPRST1: TMR2RST Mask            */
+
+#define SYS_IPRST1_TMR3RST_Pos           (5)                                               /*!< SYS_T::IPRST1: TMR3RST Position        */
+#define SYS_IPRST1_TMR3RST_Msk           (0x1ul << SYS_IPRST1_TMR3RST_Pos)                 /*!< SYS_T::IPRST1: TMR3RST Mask            */
+
+#define SYS_IPRST1_ACMP01RST_Pos         (7)                                               /*!< SYS_T::IPRST1: ACMP01RST Position      */
+#define SYS_IPRST1_ACMP01RST_Msk         (0x1ul << SYS_IPRST1_ACMP01RST_Pos)               /*!< SYS_T::IPRST1: ACMP01RST Mask          */
+
+#define SYS_IPRST1_I2C0RST_Pos           (8)                                               /*!< SYS_T::IPRST1: I2C0RST Position        */
+#define SYS_IPRST1_I2C0RST_Msk           (0x1ul << SYS_IPRST1_I2C0RST_Pos)                 /*!< SYS_T::IPRST1: I2C0RST Mask            */
+
+#define SYS_IPRST1_I2C1RST_Pos           (9)                                               /*!< SYS_T::IPRST1: I2C1RST Position        */
+#define SYS_IPRST1_I2C1RST_Msk           (0x1ul << SYS_IPRST1_I2C1RST_Pos)                 /*!< SYS_T::IPRST1: I2C1RST Mask            */
+
+#define SYS_IPRST1_I2C2RST_Pos           (10)                                              /*!< SYS_T::IPRST1: I2C2RST Position        */
+#define SYS_IPRST1_I2C2RST_Msk           (0x1ul << SYS_IPRST1_I2C2RST_Pos)                 /*!< SYS_T::IPRST1: I2C2RST Mask            */
+
+#define SYS_IPRST1_SPI0RST_Pos           (12)                                              /*!< SYS_T::IPRST1: SPI0RST Position        */
+#define SYS_IPRST1_SPI0RST_Msk           (0x1ul << SYS_IPRST1_SPI0RST_Pos)                 /*!< SYS_T::IPRST1: SPI0RST Mask            */
+
+#define SYS_IPRST1_SPI1RST_Pos           (13)                                              /*!< SYS_T::IPRST1: SPI1RST Position        */
+#define SYS_IPRST1_SPI1RST_Msk           (0x1ul << SYS_IPRST1_SPI1RST_Pos)                 /*!< SYS_T::IPRST1: SPI1RST Mask            */
+
+#define SYS_IPRST1_SPI2RST_Pos           (14)                                              /*!< SYS_T::IPRST1: SPI2RST Position        */
+#define SYS_IPRST1_SPI2RST_Msk           (0x1ul << SYS_IPRST1_SPI2RST_Pos)                 /*!< SYS_T::IPRST1: SPI2RST Mask            */
+
+#define SYS_IPRST1_SPI3RST_Pos           (15)                                              /*!< SYS_T::IPRST1: SPI3RST Position        */
+#define SYS_IPRST1_SPI3RST_Msk           (0x1ul << SYS_IPRST1_SPI3RST_Pos)                 /*!< SYS_T::IPRST1: SPI3RST Mask            */
+
+#define SYS_IPRST1_UART0RST_Pos          (16)                                              /*!< SYS_T::IPRST1: UART0RST Position       */
+#define SYS_IPRST1_UART0RST_Msk          (0x1ul << SYS_IPRST1_UART0RST_Pos)                /*!< SYS_T::IPRST1: UART0RST Mask           */
+
+#define SYS_IPRST1_UART1RST_Pos          (17)                                              /*!< SYS_T::IPRST1: UART1RST Position       */
+#define SYS_IPRST1_UART1RST_Msk          (0x1ul << SYS_IPRST1_UART1RST_Pos)                /*!< SYS_T::IPRST1: UART1RST Mask           */
+
+#define SYS_IPRST1_UART2RST_Pos          (18)                                              /*!< SYS_T::IPRST1: UART2RST Position       */
+#define SYS_IPRST1_UART2RST_Msk          (0x1ul << SYS_IPRST1_UART2RST_Pos)                /*!< SYS_T::IPRST1: UART2RST Mask           */
+
+#define SYS_IPRST1_UART3RST_Pos          (19)                                              /*!< SYS_T::IPRST1: UART3RST Position       */
+#define SYS_IPRST1_UART3RST_Msk          (0x1ul << SYS_IPRST1_UART3RST_Pos)                /*!< SYS_T::IPRST1: UART3RST Mask           */
+
+#define SYS_IPRST1_UART4RST_Pos          (20)                                              /*!< SYS_T::IPRST1: UART4RST Position       */
+#define SYS_IPRST1_UART4RST_Msk          (0x1ul << SYS_IPRST1_UART4RST_Pos)                /*!< SYS_T::IPRST1: UART4RST Mask           */
+
+#define SYS_IPRST1_UART5RST_Pos          (21)                                              /*!< SYS_T::IPRST1: UART5RST Position       */
+#define SYS_IPRST1_UART5RST_Msk          (0x1ul << SYS_IPRST1_UART5RST_Pos)                /*!< SYS_T::IPRST1: UART5RST Mask           */
+
+#define SYS_IPRST1_CAN0RST_Pos           (24)                                              /*!< SYS_T::IPRST1: CAN0RST Position        */
+#define SYS_IPRST1_CAN0RST_Msk           (0x1ul << SYS_IPRST1_CAN0RST_Pos)                 /*!< SYS_T::IPRST1: CAN0RST Mask            */
+
+#define SYS_IPRST1_CAN1RST_Pos           (25)                                              /*!< SYS_T::IPRST1: CAN1RST Position        */
+#define SYS_IPRST1_CAN1RST_Msk           (0x1ul << SYS_IPRST1_CAN1RST_Pos)                 /*!< SYS_T::IPRST1: CAN1RST Mask            */
+
+#define SYS_IPRST1_USBDRST_Pos           (27)                                              /*!< SYS_T::IPRST1: USBDRST Position        */
+#define SYS_IPRST1_USBDRST_Msk           (0x1ul << SYS_IPRST1_USBDRST_Pos)                 /*!< SYS_T::IPRST1: USBDRST Mask            */
+
+#define SYS_IPRST1_EADCRST_Pos           (28)                                              /*!< SYS_T::IPRST1: EADCRST Position        */
+#define SYS_IPRST1_EADCRST_Msk           (0x1ul << SYS_IPRST1_EADCRST_Pos)                 /*!< SYS_T::IPRST1: EADCRST Mask            */
+
+#define SYS_IPRST1_I2S0RST_Pos           (29)                                              /*!< SYS_T::IPRST1: I2S0RST Position        */
+#define SYS_IPRST1_I2S0RST_Msk           (0x1ul << SYS_IPRST1_I2S0RST_Pos)                 /*!< SYS_T::IPRST1: I2S0RST Mask            */
+
+#define SYS_IPRST2_SC0RST_Pos            (0)                                               /*!< SYS_T::IPRST2: SC0RST Position         */
+#define SYS_IPRST2_SC0RST_Msk            (0x1ul << SYS_IPRST2_SC0RST_Pos)                  /*!< SYS_T::IPRST2: SC0RST Mask             */
+
+#define SYS_IPRST2_SC1RST_Pos            (1)                                               /*!< SYS_T::IPRST2: SC1RST Position         */
+#define SYS_IPRST2_SC1RST_Msk            (0x1ul << SYS_IPRST2_SC1RST_Pos)                  /*!< SYS_T::IPRST2: SC1RST Mask             */
+
+#define SYS_IPRST2_SC2RST_Pos            (2)                                               /*!< SYS_T::IPRST2: SC2RST Position         */
+#define SYS_IPRST2_SC2RST_Msk            (0x1ul << SYS_IPRST2_SC2RST_Pos)                  /*!< SYS_T::IPRST2: SC2RST Mask             */
+
+#define SYS_IPRST2_SPI4RST_Pos           (6)                                               /*!< SYS_T::IPRST2: SPI4RST Position        */
+#define SYS_IPRST2_SPI4RST_Msk           (0x1ul << SYS_IPRST2_SPI4RST_Pos)                 /*!< SYS_T::IPRST2: SPI4RST Mask            */
+
+#define SYS_IPRST2_USCI0RST_Pos          (8)                                               /*!< SYS_T::IPRST2: USCI0RST Position       */
+#define SYS_IPRST2_USCI0RST_Msk          (0x1ul << SYS_IPRST2_USCI0RST_Pos)                /*!< SYS_T::IPRST2: USCI0RST Mask           */
+
+#define SYS_IPRST2_USCI1RST_Pos          (9)                                               /*!< SYS_T::IPRST2: USCI1RST Position       */
+#define SYS_IPRST2_USCI1RST_Msk          (0x1ul << SYS_IPRST2_USCI1RST_Pos)                /*!< SYS_T::IPRST2: USCI1RST Mask           */
+
+#define SYS_IPRST2_DACRST_Pos            (12)                                              /*!< SYS_T::IPRST2: DACRST Position         */
+#define SYS_IPRST2_DACRST_Msk            (0x1ul << SYS_IPRST2_DACRST_Pos)                  /*!< SYS_T::IPRST2: DACRST Mask             */
+
+#define SYS_IPRST2_EPWM0RST_Pos          (16)                                              /*!< SYS_T::IPRST2: EPWM0RST Position       */
+#define SYS_IPRST2_EPWM0RST_Msk          (0x1ul << SYS_IPRST2_EPWM0RST_Pos)                /*!< SYS_T::IPRST2: EPWM0RST Mask           */
+
+#define SYS_IPRST2_EPWM1RST_Pos          (17)                                              /*!< SYS_T::IPRST2: EPWM1RST Position       */
+#define SYS_IPRST2_EPWM1RST_Msk          (0x1ul << SYS_IPRST2_EPWM1RST_Pos)                /*!< SYS_T::IPRST2: EPWM1RST Mask           */
+
+#define SYS_IPRST2_BPWM0RST_Pos          (18)                                              /*!< SYS_T::IPRST2: BPWM0RST Position       */
+#define SYS_IPRST2_BPWM0RST_Msk          (0x1ul << SYS_IPRST2_BPWM0RST_Pos)                /*!< SYS_T::IPRST2: BPWM0RST Mask           */
+
+#define SYS_IPRST2_BPWM1RST_Pos          (19)                                              /*!< SYS_T::IPRST2: BPWM1RST Position       */
+#define SYS_IPRST2_BPWM1RST_Msk          (0x1ul << SYS_IPRST2_BPWM1RST_Pos)                /*!< SYS_T::IPRST2: BPWM1RST Mask           */
+
+#define SYS_IPRST2_QEI0RST_Pos           (22)                                              /*!< SYS_T::IPRST2: QEI0RST Position        */
+#define SYS_IPRST2_QEI0RST_Msk           (0x1ul << SYS_IPRST2_QEI0RST_Pos)                 /*!< SYS_T::IPRST2: QEI0RST Mask            */
+
+#define SYS_IPRST2_QEI1RST_Pos           (23)                                              /*!< SYS_T::IPRST2: QEI1RST Position        */
+#define SYS_IPRST2_QEI1RST_Msk           (0x1ul << SYS_IPRST2_QEI1RST_Pos)                 /*!< SYS_T::IPRST2: QEI1RST Mask            */
+
+#define SYS_IPRST2_ECAP0RST_Pos          (26)                                              /*!< SYS_T::IPRST2: ECAP0RST Position       */
+#define SYS_IPRST2_ECAP0RST_Msk          (0x1ul << SYS_IPRST2_ECAP0RST_Pos)                /*!< SYS_T::IPRST2: ECAP0RST Mask           */
+
+#define SYS_IPRST2_ECAP1RST_Pos          (27)                                              /*!< SYS_T::IPRST2: ECAP1RST Position       */
+#define SYS_IPRST2_ECAP1RST_Msk          (0x1ul << SYS_IPRST2_ECAP1RST_Pos)                /*!< SYS_T::IPRST2: ECAP1RST Mask           */
+
+#define SYS_IPRST2_OPARST_Pos            (30)                                              /*!< SYS_T::IPRST2: OPARST Position         */
+#define SYS_IPRST2_OPARST_Msk            (0x1ul << SYS_IPRST2_OPARST_Pos)                  /*!< SYS_T::IPRST2: OPARST Mask             */
+
+#define SYS_BODCTL_BODEN_Pos             (0)                                               /*!< SYS_T::BODCTL: BODEN Position          */
+#define SYS_BODCTL_BODEN_Msk             (0x1ul << SYS_BODCTL_BODEN_Pos)                   /*!< SYS_T::BODCTL: BODEN Mask              */
+
+#define SYS_BODCTL_BODRSTEN_Pos          (3)                                               /*!< SYS_T::BODCTL: BODRSTEN Position       */
+#define SYS_BODCTL_BODRSTEN_Msk          (0x1ul << SYS_BODCTL_BODRSTEN_Pos)                /*!< SYS_T::BODCTL: BODRSTEN Mask           */
+
+#define SYS_BODCTL_BODIF_Pos             (4)                                               /*!< SYS_T::BODCTL: BODIF Position          */
+#define SYS_BODCTL_BODIF_Msk             (0x1ul << SYS_BODCTL_BODIF_Pos)                   /*!< SYS_T::BODCTL: BODIF Mask              */
+
+#define SYS_BODCTL_BODLPM_Pos            (5)                                               /*!< SYS_T::BODCTL: BODLPM Position         */
+#define SYS_BODCTL_BODLPM_Msk            (0x1ul << SYS_BODCTL_BODLPM_Pos)                  /*!< SYS_T::BODCTL: BODLPM Mask             */
+
+#define SYS_BODCTL_BODOUT_Pos            (6)                                               /*!< SYS_T::BODCTL: BODOUT Position         */
+#define SYS_BODCTL_BODOUT_Msk            (0x1ul << SYS_BODCTL_BODOUT_Pos)                  /*!< SYS_T::BODCTL: BODOUT Mask             */
+
+#define SYS_BODCTL_LVREN_Pos             (7)                                               /*!< SYS_T::BODCTL: LVREN Position          */
+#define SYS_BODCTL_LVREN_Msk             (0x1ul << SYS_BODCTL_LVREN_Pos)                   /*!< SYS_T::BODCTL: LVREN Mask              */
+
+#define SYS_BODCTL_BODDGSEL_Pos          (8)                                               /*!< SYS_T::BODCTL: BODDGSEL Position       */
+#define SYS_BODCTL_BODDGSEL_Msk          (0x7ul << SYS_BODCTL_BODDGSEL_Pos)                /*!< SYS_T::BODCTL: BODDGSEL Mask           */
+
+#define SYS_BODCTL_LVRDGSEL_Pos          (12)                                              /*!< SYS_T::BODCTL: LVRDGSEL Position       */
+#define SYS_BODCTL_LVRDGSEL_Msk          (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)                /*!< SYS_T::BODCTL: LVRDGSEL Mask           */
+
+#define SYS_BODCTL_BODVL_Pos             (16)                                              /*!< SYS_T::BODCTL: BODVL Position          */
+#define SYS_BODCTL_BODVL_Msk             (0x7ul << SYS_BODCTL_BODVL_Pos)                   /*!< SYS_T::BODCTL: BODVL Mask              */
+
+#define SYS_IVSCTL_VTEMPEN_Pos           (0)                                               /*!< SYS_T::IVSCTL: VTEMPEN Position        */
+#define SYS_IVSCTL_VTEMPEN_Msk           (0x1ul << SYS_IVSCTL_VTEMPEN_Pos)                 /*!< SYS_T::IVSCTL: VTEMPEN Mask            */
+
+#define SYS_IVSCTL_VBATUGEN_Pos          (1)                                               /*!< SYS_T::IVSCTL: VBATUGEN Position       */
+#define SYS_IVSCTL_VBATUGEN_Msk          (0x1ul << SYS_IVSCTL_VBATUGEN_Pos)                /*!< SYS_T::IVSCTL: VBATUGEN Mask           */
+
+#define SYS_PORCTL_POROFF_Pos            (0)                                               /*!< SYS_T::PORCTL: POROFF Position         */
+#define SYS_PORCTL_POROFF_Msk            (0xfffful << SYS_PORCTL_POROFF_Pos)               /*!< SYS_T::PORCTL: POROFF Mask             */
+
+#define SYS_VREFCTL_VREFCTL_Pos          (0)                                               /*!< SYS_T::VREFCTL: VREFCTL Position       */
+#define SYS_VREFCTL_VREFCTL_Msk          (0x1ful << SYS_VREFCTL_VREFCTL_Pos)               /*!< SYS_T::VREFCTL: VREFCTL Mask           */
+
+#define SYS_VREFCTL_PRELOAD_SEL_Pos      (6)                                               /*!< SYS_T::VREFCTL: PRELOAD_SEL Position   */
+#define SYS_VREFCTL_PRELOAD_SEL_Msk      (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos)            /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask       */
+
+#define SYS_USBPHY_USBROLE_Pos           (0)                                               /*!< SYS_T::USBPHY: USBROLE Position        */
+#define SYS_USBPHY_USBROLE_Msk           (0x3ul << SYS_USBPHY_USBROLE_Pos)                 /*!< SYS_T::USBPHY: USBROLE Mask            */
+
+#define SYS_USBPHY_SBO_Pos               (2)                                               /*!< SYS_T::USBPHY: SBO Position            */
+#define SYS_USBPHY_SBO_Msk               (0x1ul << SYS_USBPHY_SBO_Pos)                     /*!< SYS_T::USBPHY: SBO Mask                */
+
+#define SYS_USBPHY_USBEN_Pos             (8)                                               /*!< SYS_T::USBPHY: USBEN Position          */
+#define SYS_USBPHY_USBEN_Msk             (0x1ul << SYS_USBPHY_USBEN_Pos)                   /*!< SYS_T::USBPHY: USBEN Mask              */
+
+#define SYS_USBPHY_HSUSBROLE_Pos         (16)                                              /*!< SYS_T::USBPHY: HSUSBROLE Position      */
+#define SYS_USBPHY_HSUSBROLE_Msk         (0x3ul << SYS_USBPHY_HSUSBROLE_Pos)               /*!< SYS_T::USBPHY: HSUSBROLE Mask          */
+
+#define SYS_USBPHY_HSUSBEN_Pos           (24)                                              /*!< SYS_T::USBPHY: HSUSBEN Position        */
+#define SYS_USBPHY_HSUSBEN_Msk           (0x1ul << SYS_USBPHY_HSUSBEN_Pos)                 /*!< SYS_T::USBPHY: HSUSBEN Mask            */
+
+#define SYS_USBPHY_HSUSBACT_Pos          (25)                                              /*!< SYS_T::USBPHY: HSUSBACT Position       */
+#define SYS_USBPHY_HSUSBACT_Msk          (0x1ul << SYS_USBPHY_HSUSBACT_Pos)                /*!< SYS_T::USBPHY: HSUSBACT Mask           */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPL: PA0MFP Position       */
+#define SYS_GPA_MFPL_PA0MFP_Msk          (0xful << SYS_GPA_MFPL_PA0MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA0MFP Mask           */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPL: PA1MFP Position       */
+#define SYS_GPA_MFPL_PA1MFP_Msk          (0xful << SYS_GPA_MFPL_PA1MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA1MFP Mask           */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos          (8)                                               /*!< SYS_T::GPA_MFPL: PA2MFP Position       */
+#define SYS_GPA_MFPL_PA2MFP_Msk          (0xful << SYS_GPA_MFPL_PA2MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA2MFP Mask           */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos          (12)                                              /*!< SYS_T::GPA_MFPL: PA3MFP Position       */
+#define SYS_GPA_MFPL_PA3MFP_Msk          (0xful << SYS_GPA_MFPL_PA3MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA3MFP Mask           */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos          (16)                                              /*!< SYS_T::GPA_MFPL: PA4MFP Position       */
+#define SYS_GPA_MFPL_PA4MFP_Msk          (0xful << SYS_GPA_MFPL_PA4MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA4MFP Mask           */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos          (20)                                              /*!< SYS_T::GPA_MFPL: PA5MFP Position       */
+#define SYS_GPA_MFPL_PA5MFP_Msk          (0xful << SYS_GPA_MFPL_PA5MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA5MFP Mask           */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos          (24)                                              /*!< SYS_T::GPA_MFPL: PA6MFP Position       */
+#define SYS_GPA_MFPL_PA6MFP_Msk          (0xful << SYS_GPA_MFPL_PA6MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA6MFP Mask           */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos          (28)                                              /*!< SYS_T::GPA_MFPL: PA7MFP Position       */
+#define SYS_GPA_MFPL_PA7MFP_Msk          (0xful << SYS_GPA_MFPL_PA7MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA7MFP Mask           */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPH: PA8MFP Position       */
+#define SYS_GPA_MFPH_PA8MFP_Msk          (0xful << SYS_GPA_MFPH_PA8MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA8MFP Mask           */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPH: PA9MFP Position       */
+#define SYS_GPA_MFPH_PA9MFP_Msk          (0xful << SYS_GPA_MFPH_PA9MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA9MFP Mask           */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos         (8)                                               /*!< SYS_T::GPA_MFPH: PA10MFP Position      */
+#define SYS_GPA_MFPH_PA10MFP_Msk         (0xful << SYS_GPA_MFPH_PA10MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA10MFP Mask          */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos         (12)                                              /*!< SYS_T::GPA_MFPH: PA11MFP Position      */
+#define SYS_GPA_MFPH_PA11MFP_Msk         (0xful << SYS_GPA_MFPH_PA11MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA11MFP Mask          */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos         (16)                                              /*!< SYS_T::GPA_MFPH: PA12MFP Position      */
+#define SYS_GPA_MFPH_PA12MFP_Msk         (0xful << SYS_GPA_MFPH_PA12MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA12MFP Mask          */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos         (20)                                              /*!< SYS_T::GPA_MFPH: PA13MFP Position      */
+#define SYS_GPA_MFPH_PA13MFP_Msk         (0xful << SYS_GPA_MFPH_PA13MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA13MFP Mask          */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos         (24)                                              /*!< SYS_T::GPA_MFPH: PA14MFP Position      */
+#define SYS_GPA_MFPH_PA14MFP_Msk         (0xful << SYS_GPA_MFPH_PA14MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA14MFP Mask          */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos         (28)                                              /*!< SYS_T::GPA_MFPH: PA15MFP Position      */
+#define SYS_GPA_MFPH_PA15MFP_Msk         (0xful << SYS_GPA_MFPH_PA15MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA15MFP Mask          */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPL: PB0MFP Position       */
+#define SYS_GPB_MFPL_PB0MFP_Msk          (0xful << SYS_GPB_MFPL_PB0MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB0MFP Mask           */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPL: PB1MFP Position       */
+#define SYS_GPB_MFPL_PB1MFP_Msk          (0xful << SYS_GPB_MFPL_PB1MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB1MFP Mask           */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos          (8)                                               /*!< SYS_T::GPB_MFPL: PB2MFP Position       */
+#define SYS_GPB_MFPL_PB2MFP_Msk          (0xful << SYS_GPB_MFPL_PB2MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB2MFP Mask           */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos          (12)                                              /*!< SYS_T::GPB_MFPL: PB3MFP Position       */
+#define SYS_GPB_MFPL_PB3MFP_Msk          (0xful << SYS_GPB_MFPL_PB3MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB3MFP Mask           */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos          (16)                                              /*!< SYS_T::GPB_MFPL: PB4MFP Position       */
+#define SYS_GPB_MFPL_PB4MFP_Msk          (0xful << SYS_GPB_MFPL_PB4MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB4MFP Mask           */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos          (20)                                              /*!< SYS_T::GPB_MFPL: PB5MFP Position       */
+#define SYS_GPB_MFPL_PB5MFP_Msk          (0xful << SYS_GPB_MFPL_PB5MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB5MFP Mask           */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos          (24)                                              /*!< SYS_T::GPB_MFPL: PB6MFP Position       */
+#define SYS_GPB_MFPL_PB6MFP_Msk          (0xful << SYS_GPB_MFPL_PB6MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB6MFP Mask           */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos          (28)                                              /*!< SYS_T::GPB_MFPL: PB7MFP Position       */
+#define SYS_GPB_MFPL_PB7MFP_Msk          (0xful << SYS_GPB_MFPL_PB7MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB7MFP Mask           */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPH: PB8MFP Position       */
+#define SYS_GPB_MFPH_PB8MFP_Msk          (0xful << SYS_GPB_MFPH_PB8MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB8MFP Mask           */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPH: PB9MFP Position       */
+#define SYS_GPB_MFPH_PB9MFP_Msk          (0xful << SYS_GPB_MFPH_PB9MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB9MFP Mask           */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos         (8)                                               /*!< SYS_T::GPB_MFPH: PB10MFP Position      */
+#define SYS_GPB_MFPH_PB10MFP_Msk         (0xful << SYS_GPB_MFPH_PB10MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB10MFP Mask          */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos         (12)                                              /*!< SYS_T::GPB_MFPH: PB11MFP Position      */
+#define SYS_GPB_MFPH_PB11MFP_Msk         (0xful << SYS_GPB_MFPH_PB11MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB11MFP Mask          */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos         (16)                                              /*!< SYS_T::GPB_MFPH: PB12MFP Position      */
+#define SYS_GPB_MFPH_PB12MFP_Msk         (0xful << SYS_GPB_MFPH_PB12MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB12MFP Mask          */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos         (20)                                              /*!< SYS_T::GPB_MFPH: PB13MFP Position      */
+#define SYS_GPB_MFPH_PB13MFP_Msk         (0xful << SYS_GPB_MFPH_PB13MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB13MFP Mask          */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos         (24)                                              /*!< SYS_T::GPB_MFPH: PB14MFP Position      */
+#define SYS_GPB_MFPH_PB14MFP_Msk         (0xful << SYS_GPB_MFPH_PB14MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB14MFP Mask          */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos         (28)                                              /*!< SYS_T::GPB_MFPH: PB15MFP Position      */
+#define SYS_GPB_MFPH_PB15MFP_Msk         (0xful << SYS_GPB_MFPH_PB15MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB15MFP Mask          */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPL: PC0MFP Position       */
+#define SYS_GPC_MFPL_PC0MFP_Msk          (0xful << SYS_GPC_MFPL_PC0MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC0MFP Mask           */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPL: PC1MFP Position       */
+#define SYS_GPC_MFPL_PC1MFP_Msk          (0xful << SYS_GPC_MFPL_PC1MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC1MFP Mask           */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos          (8)                                               /*!< SYS_T::GPC_MFPL: PC2MFP Position       */
+#define SYS_GPC_MFPL_PC2MFP_Msk          (0xful << SYS_GPC_MFPL_PC2MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC2MFP Mask           */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos          (12)                                              /*!< SYS_T::GPC_MFPL: PC3MFP Position       */
+#define SYS_GPC_MFPL_PC3MFP_Msk          (0xful << SYS_GPC_MFPL_PC3MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC3MFP Mask           */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos          (16)                                              /*!< SYS_T::GPC_MFPL: PC4MFP Position       */
+#define SYS_GPC_MFPL_PC4MFP_Msk          (0xful << SYS_GPC_MFPL_PC4MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC4MFP Mask           */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos          (20)                                              /*!< SYS_T::GPC_MFPL: PC5MFP Position       */
+#define SYS_GPC_MFPL_PC5MFP_Msk          (0xful << SYS_GPC_MFPL_PC5MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC5MFP Mask           */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos          (24)                                              /*!< SYS_T::GPC_MFPL: PC6MFP Position       */
+#define SYS_GPC_MFPL_PC6MFP_Msk          (0xful << SYS_GPC_MFPL_PC6MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC6MFP Mask           */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos          (28)                                              /*!< SYS_T::GPC_MFPL: PC7MFP Position       */
+#define SYS_GPC_MFPL_PC7MFP_Msk          (0xful << SYS_GPC_MFPL_PC7MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC7MFP Mask           */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPH: PC8MFP Position       */
+#define SYS_GPC_MFPH_PC8MFP_Msk          (0xful << SYS_GPC_MFPH_PC8MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC8MFP Mask           */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPH: PC9MFP Position       */
+#define SYS_GPC_MFPH_PC9MFP_Msk          (0xful << SYS_GPC_MFPH_PC9MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC9MFP Mask           */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos         (8)                                               /*!< SYS_T::GPC_MFPH: PC10MFP Position      */
+#define SYS_GPC_MFPH_PC10MFP_Msk         (0xful << SYS_GPC_MFPH_PC10MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC10MFP Mask          */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos         (12)                                              /*!< SYS_T::GPC_MFPH: PC11MFP Position      */
+#define SYS_GPC_MFPH_PC11MFP_Msk         (0xful << SYS_GPC_MFPH_PC11MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC11MFP Mask          */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos         (16)                                              /*!< SYS_T::GPC_MFPH: PC12MFP Position      */
+#define SYS_GPC_MFPH_PC12MFP_Msk         (0xful << SYS_GPC_MFPH_PC12MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC12MFP Mask          */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos         (20)                                              /*!< SYS_T::GPC_MFPH: PC13MFP Position      */
+#define SYS_GPC_MFPH_PC13MFP_Msk         (0xful << SYS_GPC_MFPH_PC13MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC13MFP Mask          */
+
+#define SYS_GPC_MFPH_PC14MFP_Pos         (24)                                              /*!< SYS_T::GPC_MFPH: PC14MFP Position      */
+#define SYS_GPC_MFPH_PC14MFP_Msk         (0xful << SYS_GPC_MFPH_PC14MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC14MFP Mask          */
+
+#define SYS_GPC_MFPH_PC15MFP_Pos         (28)                                              /*!< SYS_T::GPC_MFPH: PC15MFP Position      */
+#define SYS_GPC_MFPH_PC15MFP_Msk         (0xful << SYS_GPC_MFPH_PC15MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC15MFP Mask          */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPL: PD0MFP Position       */
+#define SYS_GPD_MFPL_PD0MFP_Msk          (0xful << SYS_GPD_MFPL_PD0MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD0MFP Mask           */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPL: PD1MFP Position       */
+#define SYS_GPD_MFPL_PD1MFP_Msk          (0xful << SYS_GPD_MFPL_PD1MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD1MFP Mask           */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos          (8)                                               /*!< SYS_T::GPD_MFPL: PD2MFP Position       */
+#define SYS_GPD_MFPL_PD2MFP_Msk          (0xful << SYS_GPD_MFPL_PD2MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD2MFP Mask           */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos          (12)                                              /*!< SYS_T::GPD_MFPL: PD3MFP Position       */
+#define SYS_GPD_MFPL_PD3MFP_Msk          (0xful << SYS_GPD_MFPL_PD3MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD3MFP Mask           */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos          (16)                                              /*!< SYS_T::GPD_MFPL: PD4MFP Position       */
+#define SYS_GPD_MFPL_PD4MFP_Msk          (0xful << SYS_GPD_MFPL_PD4MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD4MFP Mask           */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos          (20)                                              /*!< SYS_T::GPD_MFPL: PD5MFP Position       */
+#define SYS_GPD_MFPL_PD5MFP_Msk          (0xful << SYS_GPD_MFPL_PD5MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD5MFP Mask           */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos          (24)                                              /*!< SYS_T::GPD_MFPL: PD6MFP Position       */
+#define SYS_GPD_MFPL_PD6MFP_Msk          (0xful << SYS_GPD_MFPL_PD6MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD6MFP Mask           */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos          (28)                                              /*!< SYS_T::GPD_MFPL: PD7MFP Position       */
+#define SYS_GPD_MFPL_PD7MFP_Msk          (0xful << SYS_GPD_MFPL_PD7MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD7MFP Mask           */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPH: PD8MFP Position       */
+#define SYS_GPD_MFPH_PD8MFP_Msk          (0xful << SYS_GPD_MFPH_PD8MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD8MFP Mask           */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPH: PD9MFP Position       */
+#define SYS_GPD_MFPH_PD9MFP_Msk          (0xful << SYS_GPD_MFPH_PD9MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD9MFP Mask           */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos         (8)                                               /*!< SYS_T::GPD_MFPH: PD10MFP Position      */
+#define SYS_GPD_MFPH_PD10MFP_Msk         (0xful << SYS_GPD_MFPH_PD10MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD10MFP Mask          */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos         (12)                                              /*!< SYS_T::GPD_MFPH: PD11MFP Position      */
+#define SYS_GPD_MFPH_PD11MFP_Msk         (0xful << SYS_GPD_MFPH_PD11MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD11MFP Mask          */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos         (16)                                              /*!< SYS_T::GPD_MFPH: PD12MFP Position      */
+#define SYS_GPD_MFPH_PD12MFP_Msk         (0xful << SYS_GPD_MFPH_PD12MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD12MFP Mask          */
+
+#define SYS_GPD_MFPH_PD13MFP_Pos         (20)                                              /*!< SYS_T::GPD_MFPH: PD13MFP Position      */
+#define SYS_GPD_MFPH_PD13MFP_Msk         (0xful << SYS_GPD_MFPH_PD13MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD13MFP Mask          */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos         (24)                                              /*!< SYS_T::GPD_MFPH: PD14MFP Position      */
+#define SYS_GPD_MFPH_PD14MFP_Msk         (0xful << SYS_GPD_MFPH_PD14MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD14MFP Mask          */
+
+#define SYS_GPD_MFPH_PD15MFP_Pos         (28)                                              /*!< SYS_T::GPD_MFPH: PD15MFP Position      */
+#define SYS_GPD_MFPH_PD15MFP_Msk         (0xful << SYS_GPD_MFPH_PD15MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD15MFP Mask          */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPL: PE0MFP Position       */
+#define SYS_GPE_MFPL_PE0MFP_Msk          (0xful << SYS_GPE_MFPL_PE0MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE0MFP Mask           */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPL: PE1MFP Position       */
+#define SYS_GPE_MFPL_PE1MFP_Msk          (0xful << SYS_GPE_MFPL_PE1MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE1MFP Mask           */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos          (8)                                               /*!< SYS_T::GPE_MFPL: PE2MFP Position       */
+#define SYS_GPE_MFPL_PE2MFP_Msk          (0xful << SYS_GPE_MFPL_PE2MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE2MFP Mask           */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos          (12)                                              /*!< SYS_T::GPE_MFPL: PE3MFP Position       */
+#define SYS_GPE_MFPL_PE3MFP_Msk          (0xful << SYS_GPE_MFPL_PE3MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE3MFP Mask           */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos          (16)                                              /*!< SYS_T::GPE_MFPL: PE4MFP Position       */
+#define SYS_GPE_MFPL_PE4MFP_Msk          (0xful << SYS_GPE_MFPL_PE4MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE4MFP Mask           */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos          (20)                                              /*!< SYS_T::GPE_MFPL: PE5MFP Position       */
+#define SYS_GPE_MFPL_PE5MFP_Msk          (0xful << SYS_GPE_MFPL_PE5MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE5MFP Mask           */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos          (24)                                              /*!< SYS_T::GPE_MFPL: PE6MFP Position       */
+#define SYS_GPE_MFPL_PE6MFP_Msk          (0xful << SYS_GPE_MFPL_PE6MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE6MFP Mask           */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos          (28)                                              /*!< SYS_T::GPE_MFPL: PE7MFP Position       */
+#define SYS_GPE_MFPL_PE7MFP_Msk          (0xful << SYS_GPE_MFPL_PE7MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE7MFP Mask           */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPH: PE8MFP Position       */
+#define SYS_GPE_MFPH_PE8MFP_Msk          (0xful << SYS_GPE_MFPH_PE8MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE8MFP Mask           */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPH: PE9MFP Position       */
+#define SYS_GPE_MFPH_PE9MFP_Msk          (0xful << SYS_GPE_MFPH_PE9MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE9MFP Mask           */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos         (8)                                               /*!< SYS_T::GPE_MFPH: PE10MFP Position      */
+#define SYS_GPE_MFPH_PE10MFP_Msk         (0xful << SYS_GPE_MFPH_PE10MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE10MFP Mask          */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos         (12)                                              /*!< SYS_T::GPE_MFPH: PE11MFP Position      */
+#define SYS_GPE_MFPH_PE11MFP_Msk         (0xful << SYS_GPE_MFPH_PE11MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE11MFP Mask          */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos         (16)                                              /*!< SYS_T::GPE_MFPH: PE12MFP Position      */
+#define SYS_GPE_MFPH_PE12MFP_Msk         (0xful << SYS_GPE_MFPH_PE12MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE12MFP Mask          */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos         (20)                                              /*!< SYS_T::GPE_MFPH: PE13MFP Position      */
+#define SYS_GPE_MFPH_PE13MFP_Msk         (0xful << SYS_GPE_MFPH_PE13MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE13MFP Mask          */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos         (24)                                              /*!< SYS_T::GPE_MFPH: PE14MFP Position      */
+#define SYS_GPE_MFPH_PE14MFP_Msk         (0xful << SYS_GPE_MFPH_PE14MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE14MFP Mask          */
+
+#define SYS_GPE_MFPH_PE15MFP_Pos         (28)                                              /*!< SYS_T::GPE_MFPH: PE15MFP Position      */
+#define SYS_GPE_MFPH_PE15MFP_Msk         (0xful << SYS_GPE_MFPH_PE15MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE15MFP Mask          */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos          (0)                                               /*!< SYS_T::GPF_MFPL: PF0MFP Position       */
+#define SYS_GPF_MFPL_PF0MFP_Msk          (0xful << SYS_GPF_MFPL_PF0MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF0MFP Mask           */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos          (4)                                               /*!< SYS_T::GPF_MFPL: PF1MFP Position       */
+#define SYS_GPF_MFPL_PF1MFP_Msk          (0xful << SYS_GPF_MFPL_PF1MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF1MFP Mask           */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos          (8)                                               /*!< SYS_T::GPF_MFPL: PF2MFP Position       */
+#define SYS_GPF_MFPL_PF2MFP_Msk          (0xful << SYS_GPF_MFPL_PF2MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF2MFP Mask           */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos          (12)                                              /*!< SYS_T::GPF_MFPL: PF3MFP Position       */
+#define SYS_GPF_MFPL_PF3MFP_Msk          (0xful << SYS_GPF_MFPL_PF3MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF3MFP Mask           */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos          (16)                                              /*!< SYS_T::GPF_MFPL: PF4MFP Position       */
+#define SYS_GPF_MFPL_PF4MFP_Msk          (0xful << SYS_GPF_MFPL_PF4MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF4MFP Mask           */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos          (20)                                              /*!< SYS_T::GPF_MFPL: PF5MFP Position       */
+#define SYS_GPF_MFPL_PF5MFP_Msk          (0xful << SYS_GPF_MFPL_PF5MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF5MFP Mask           */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos          (24)                                              /*!< SYS_T::GPF_MFPL: PF6MFP Position       */
+#define SYS_GPF_MFPL_PF6MFP_Msk          (0xful << SYS_GPF_MFPL_PF6MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF6MFP Mask           */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos          (28)                                              /*!< SYS_T::GPF_MFPL: PF7MFP Position       */
+#define SYS_GPF_MFPL_PF7MFP_Msk          (0xful << SYS_GPF_MFPL_PF7MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF7MFP Mask           */
+
+#define SYS_GPF_MFPH_PF8MFP_Pos          (0)                                               /*!< SYS_T::GPF_MFPH: PF8MFP Position       */
+#define SYS_GPF_MFPH_PF8MFP_Msk          (0xful << SYS_GPF_MFPH_PF8MFP_Pos)                /*!< SYS_T::GPF_MFPH: PF8MFP Mask           */
+
+#define SYS_GPF_MFPH_PF9MFP_Pos          (4)                                               /*!< SYS_T::GPF_MFPH: PF9MFP Position       */
+#define SYS_GPF_MFPH_PF9MFP_Msk          (0xful << SYS_GPF_MFPH_PF9MFP_Pos)                /*!< SYS_T::GPF_MFPH: PF9MFP Mask           */
+
+#define SYS_GPF_MFPH_PF10MFP_Pos         (8)                                               /*!< SYS_T::GPF_MFPH: PF10MFP Position      */
+#define SYS_GPF_MFPH_PF10MFP_Msk         (0xful << SYS_GPF_MFPH_PF10MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF10MFP Mask          */
+
+#define SYS_GPF_MFPH_PF11MFP_Pos         (12)                                              /*!< SYS_T::GPF_MFPH: PF11MFP Position      */
+#define SYS_GPF_MFPH_PF11MFP_Msk         (0xful << SYS_GPF_MFPH_PF11MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF11MFP Mask          */
+
+#define SYS_GPF_MFPH_PF12MFP_Pos         (16)                                              /*!< SYS_T::GPF_MFPH: PF12MFP Position      */
+#define SYS_GPF_MFPH_PF12MFP_Msk         (0xful << SYS_GPF_MFPH_PF12MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF12MFP Mask          */
+
+#define SYS_GPF_MFPH_PF13MFP_Pos         (20)                                              /*!< SYS_T::GPF_MFPH: PF13MFP Position      */
+#define SYS_GPF_MFPH_PF13MFP_Msk         (0xful << SYS_GPF_MFPH_PF13MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF13MFP Mask          */
+
+#define SYS_GPF_MFPH_PF14MFP_Pos         (24)                                              /*!< SYS_T::GPF_MFPH: PF14MFP Position      */
+#define SYS_GPF_MFPH_PF14MFP_Msk         (0xful << SYS_GPF_MFPH_PF14MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF14MFP Mask          */
+
+#define SYS_GPF_MFPH_PF15MFP_Pos         (28)                                              /*!< SYS_T::GPF_MFPH: PF15MFP Position      */
+#define SYS_GPF_MFPH_PF15MFP_Msk         (0xful << SYS_GPF_MFPH_PF15MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF15MFP Mask          */
+
+#define SYS_GPG_MFPL_PG0MFP_Pos          (0)                                               /*!< SYS_T::GPG_MFPL: PG0MFP Position       */
+#define SYS_GPG_MFPL_PG0MFP_Msk          (0xful << SYS_GPG_MFPL_PG0MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG0MFP Mask           */
+
+#define SYS_GPG_MFPL_PG1MFP_Pos          (4)                                               /*!< SYS_T::GPG_MFPL: PG1MFP Position       */
+#define SYS_GPG_MFPL_PG1MFP_Msk          (0xful << SYS_GPG_MFPL_PG1MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG1MFP Mask           */
+
+#define SYS_GPG_MFPL_PG2MFP_Pos          (8)                                               /*!< SYS_T::GPG_MFPL: PG2MFP Position       */
+#define SYS_GPG_MFPL_PG2MFP_Msk          (0xful << SYS_GPG_MFPL_PG2MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG2MFP Mask           */
+
+#define SYS_GPG_MFPL_PG3MFP_Pos          (12)                                              /*!< SYS_T::GPG_MFPL: PG3MFP Position       */
+#define SYS_GPG_MFPL_PG3MFP_Msk          (0xful << SYS_GPG_MFPL_PG3MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG3MFP Mask           */
+
+#define SYS_GPG_MFPL_PG4MFP_Pos          (16)                                              /*!< SYS_T::GPG_MFPL: PG4MFP Position       */
+#define SYS_GPG_MFPL_PG4MFP_Msk          (0xful << SYS_GPG_MFPL_PG4MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG4MFP Mask           */
+
+#define SYS_GPG_MFPL_PG5MFP_Pos          (20)                                              /*!< SYS_T::GPG_MFPL: PG5MFP Position       */
+#define SYS_GPG_MFPL_PG5MFP_Msk          (0xful << SYS_GPG_MFPL_PG5MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG5MFP Mask           */
+
+#define SYS_GPG_MFPL_PG6MFP_Pos          (24)                                              /*!< SYS_T::GPG_MFPL: PG6MFP Position       */
+#define SYS_GPG_MFPL_PG6MFP_Msk          (0xful << SYS_GPG_MFPL_PG6MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG6MFP Mask           */
+
+#define SYS_GPG_MFPL_PG7MFP_Pos          (28)                                              /*!< SYS_T::GPG_MFPL: PG7MFP Position       */
+#define SYS_GPG_MFPL_PG7MFP_Msk          (0xful << SYS_GPG_MFPL_PG7MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG7MFP Mask           */
+
+#define SYS_GPG_MFPH_PG8MFP_Pos          (0)                                               /*!< SYS_T::GPG_MFPH: PG8MFP Position       */
+#define SYS_GPG_MFPH_PG8MFP_Msk          (0xful << SYS_GPG_MFPH_PG8MFP_Pos)                /*!< SYS_T::GPG_MFPH: PG8MFP Mask           */
+
+#define SYS_GPG_MFPH_PG9MFP_Pos          (4)                                               /*!< SYS_T::GPG_MFPH: PG9MFP Position       */
+#define SYS_GPG_MFPH_PG9MFP_Msk          (0xful << SYS_GPG_MFPH_PG9MFP_Pos)                /*!< SYS_T::GPG_MFPH: PG9MFP Mask           */
+
+#define SYS_GPG_MFPH_PG10MFP_Pos         (8)                                               /*!< SYS_T::GPG_MFPH: PG10MFP Position      */
+#define SYS_GPG_MFPH_PG10MFP_Msk         (0xful << SYS_GPG_MFPH_PG10MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG10MFP Mask          */
+
+#define SYS_GPG_MFPH_PG11MFP_Pos         (12)                                              /*!< SYS_T::GPG_MFPH: PG11MFP Position      */
+#define SYS_GPG_MFPH_PG11MFP_Msk         (0xful << SYS_GPG_MFPH_PG11MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG11MFP Mask          */
+
+#define SYS_GPG_MFPH_PG12MFP_Pos         (16)                                              /*!< SYS_T::GPG_MFPH: PG12MFP Position      */
+#define SYS_GPG_MFPH_PG12MFP_Msk         (0xful << SYS_GPG_MFPH_PG12MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG12MFP Mask          */
+
+#define SYS_GPG_MFPH_PG13MFP_Pos         (20)                                              /*!< SYS_T::GPG_MFPH: PG13MFP Position      */
+#define SYS_GPG_MFPH_PG13MFP_Msk         (0xful << SYS_GPG_MFPH_PG13MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG13MFP Mask          */
+
+#define SYS_GPG_MFPH_PG14MFP_Pos         (24)                                              /*!< SYS_T::GPG_MFPH: PG14MFP Position      */
+#define SYS_GPG_MFPH_PG14MFP_Msk         (0xful << SYS_GPG_MFPH_PG14MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG14MFP Mask          */
+
+#define SYS_GPG_MFPH_PG15MFP_Pos         (28)                                              /*!< SYS_T::GPG_MFPH: PG15MFP Position      */
+#define SYS_GPG_MFPH_PG15MFP_Msk         (0xful << SYS_GPG_MFPH_PG15MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG15MFP Mask          */
+
+#define SYS_GPH_MFPL_PH0MFP_Pos          (0)                                               /*!< SYS_T::GPH_MFPL: PH0MFP Position       */
+#define SYS_GPH_MFPL_PH0MFP_Msk          (0xful << SYS_GPH_MFPL_PH0MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH0MFP Mask           */
+
+#define SYS_GPH_MFPL_PH1MFP_Pos          (4)                                               /*!< SYS_T::GPH_MFPL: PH1MFP Position       */
+#define SYS_GPH_MFPL_PH1MFP_Msk          (0xful << SYS_GPH_MFPL_PH1MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH1MFP Mask           */
+
+#define SYS_GPH_MFPL_PH2MFP_Pos          (8)                                               /*!< SYS_T::GPH_MFPL: PH2MFP Position       */
+#define SYS_GPH_MFPL_PH2MFP_Msk          (0xful << SYS_GPH_MFPL_PH2MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH2MFP Mask           */
+
+#define SYS_GPH_MFPL_PH3MFP_Pos          (12)                                              /*!< SYS_T::GPH_MFPL: PH3MFP Position       */
+#define SYS_GPH_MFPL_PH3MFP_Msk          (0xful << SYS_GPH_MFPL_PH3MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH3MFP Mask           */
+
+#define SYS_GPH_MFPL_PH4MFP_Pos          (16)                                              /*!< SYS_T::GPH_MFPL: PH4MFP Position       */
+#define SYS_GPH_MFPL_PH4MFP_Msk          (0xful << SYS_GPH_MFPL_PH4MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH4MFP Mask           */
+
+#define SYS_GPH_MFPL_PH5MFP_Pos          (20)                                              /*!< SYS_T::GPH_MFPL: PH5MFP Position       */
+#define SYS_GPH_MFPL_PH5MFP_Msk          (0xful << SYS_GPH_MFPL_PH5MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH5MFP Mask           */
+
+#define SYS_GPH_MFPL_PH6MFP_Pos          (24)                                              /*!< SYS_T::GPH_MFPL: PH6MFP Position       */
+#define SYS_GPH_MFPL_PH6MFP_Msk          (0xful << SYS_GPH_MFPL_PH6MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH6MFP Mask           */
+
+#define SYS_GPH_MFPL_PH7MFP_Pos          (28)                                              /*!< SYS_T::GPH_MFPL: PH7MFP Position       */
+#define SYS_GPH_MFPL_PH7MFP_Msk          (0xful << SYS_GPH_MFPL_PH7MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH7MFP Mask           */
+
+#define SYS_GPH_MFPH_PH8MFP_Pos          (0)                                               /*!< SYS_T::GPH_MFPH: PH8MFP Position       */
+#define SYS_GPH_MFPH_PH8MFP_Msk          (0xful << SYS_GPH_MFPH_PH8MFP_Pos)                /*!< SYS_T::GPH_MFPH: PH8MFP Mask           */
+
+#define SYS_GPH_MFPH_PH9MFP_Pos          (4)                                               /*!< SYS_T::GPH_MFPH: PH9MFP Position       */
+#define SYS_GPH_MFPH_PH9MFP_Msk          (0xful << SYS_GPH_MFPH_PH9MFP_Pos)                /*!< SYS_T::GPH_MFPH: PH9MFP Mask           */
+
+#define SYS_GPH_MFPH_PH10MFP_Pos         (8)                                               /*!< SYS_T::GPH_MFPH: PH10MFP Position      */
+#define SYS_GPH_MFPH_PH10MFP_Msk         (0xful << SYS_GPH_MFPH_PH10MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH10MFP Mask          */
+
+#define SYS_GPH_MFPH_PH11MFP_Pos         (12)                                              /*!< SYS_T::GPH_MFPH: PH11MFP Position      */
+#define SYS_GPH_MFPH_PH11MFP_Msk         (0xful << SYS_GPH_MFPH_PH11MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH11MFP Mask          */
+
+#define SYS_GPH_MFPH_PH12MFP_Pos         (16)                                              /*!< SYS_T::GPH_MFPH: PH12MFP Position      */
+#define SYS_GPH_MFPH_PH12MFP_Msk         (0xful << SYS_GPH_MFPH_PH12MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH12MFP Mask          */
+
+#define SYS_GPH_MFPH_PH13MFP_Pos         (20)                                              /*!< SYS_T::GPH_MFPH: PH13MFP Position      */
+#define SYS_GPH_MFPH_PH13MFP_Msk         (0xful << SYS_GPH_MFPH_PH13MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH13MFP Mask          */
+
+#define SYS_GPH_MFPH_PH14MFP_Pos         (24)                                              /*!< SYS_T::GPH_MFPH: PH14MFP Position      */
+#define SYS_GPH_MFPH_PH14MFP_Msk         (0xful << SYS_GPH_MFPH_PH14MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH14MFP Mask          */
+
+#define SYS_GPH_MFPH_PH15MFP_Pos         (28)                                              /*!< SYS_T::GPH_MFPH: PH15MFP Position      */
+#define SYS_GPH_MFPH_PH15MFP_Msk         (0xful << SYS_GPH_MFPH_PH15MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH15MFP Mask          */
+
+#define SYS_GPA_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPA_MFOS: MFOS0 Position        */
+#define SYS_GPA_MFOS_MFOS0_Msk           (0x1ul << SYS_GPA_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS0 Mask            */
+
+#define SYS_GPA_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPA_MFOS: MFOS1 Position        */
+#define SYS_GPA_MFOS_MFOS1_Msk           (0x1ul << SYS_GPA_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS1 Mask            */
+
+#define SYS_GPA_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPA_MFOS: MFOS2 Position        */
+#define SYS_GPA_MFOS_MFOS2_Msk           (0x1ul << SYS_GPA_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS2 Mask            */
+
+#define SYS_GPA_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPA_MFOS: MFOS3 Position        */
+#define SYS_GPA_MFOS_MFOS3_Msk           (0x1ul << SYS_GPA_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS3 Mask            */
+
+#define SYS_GPA_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPA_MFOS: MFOS4 Position        */
+#define SYS_GPA_MFOS_MFOS4_Msk           (0x1ul << SYS_GPA_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS4 Mask            */
+
+#define SYS_GPA_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPA_MFOS: MFOS5 Position        */
+#define SYS_GPA_MFOS_MFOS5_Msk           (0x1ul << SYS_GPA_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS5 Mask            */
+
+#define SYS_GPA_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPA_MFOS: MFOS6 Position        */
+#define SYS_GPA_MFOS_MFOS6_Msk           (0x1ul << SYS_GPA_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS6 Mask            */
+
+#define SYS_GPA_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPA_MFOS: MFOS7 Position        */
+#define SYS_GPA_MFOS_MFOS7_Msk           (0x1ul << SYS_GPA_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS7 Mask            */
+
+#define SYS_GPA_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPA_MFOS: MFOS8 Position        */
+#define SYS_GPA_MFOS_MFOS8_Msk           (0x1ul << SYS_GPA_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS8 Mask            */
+
+#define SYS_GPA_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPA_MFOS: MFOS9 Position        */
+#define SYS_GPA_MFOS_MFOS9_Msk           (0x1ul << SYS_GPA_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS9 Mask            */
+
+#define SYS_GPA_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPA_MFOS: MFOS10 Position       */
+#define SYS_GPA_MFOS_MFOS10_Msk          (0x1ul << SYS_GPA_MFOS_MFOS10_Pos)                /*!< SYS_T::GPA_MFOS: MFOS10 Mask           */
+
+#define SYS_GPA_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPA_MFOS: MFOS11 Position       */
+#define SYS_GPA_MFOS_MFOS11_Msk          (0x1ul << SYS_GPA_MFOS_MFOS11_Pos)                /*!< SYS_T::GPA_MFOS: MFOS11 Mask           */
+
+#define SYS_GPA_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPA_MFOS: MFOS12 Position       */
+#define SYS_GPA_MFOS_MFOS12_Msk          (0x1ul << SYS_GPA_MFOS_MFOS12_Pos)                /*!< SYS_T::GPA_MFOS: MFOS12 Mask           */
+
+#define SYS_GPA_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPA_MFOS: MFOS13 Position       */
+#define SYS_GPA_MFOS_MFOS13_Msk          (0x1ul << SYS_GPA_MFOS_MFOS13_Pos)                /*!< SYS_T::GPA_MFOS: MFOS13 Mask           */
+
+#define SYS_GPA_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPA_MFOS: MFOS14 Position       */
+#define SYS_GPA_MFOS_MFOS14_Msk          (0x1ul << SYS_GPA_MFOS_MFOS14_Pos)                /*!< SYS_T::GPA_MFOS: MFOS14 Mask           */
+
+#define SYS_GPA_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPA_MFOS: MFOS15 Position       */
+#define SYS_GPA_MFOS_MFOS15_Msk          (0x1ul << SYS_GPA_MFOS_MFOS15_Pos)                /*!< SYS_T::GPA_MFOS: MFOS15 Mask           */
+
+#define SYS_GPB_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPB_MFOS: MFOS0 Position        */
+#define SYS_GPB_MFOS_MFOS0_Msk           (0x1ul << SYS_GPB_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS0 Mask            */
+
+#define SYS_GPB_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPB_MFOS: MFOS1 Position        */
+#define SYS_GPB_MFOS_MFOS1_Msk           (0x1ul << SYS_GPB_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS1 Mask            */
+
+#define SYS_GPB_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPB_MFOS: MFOS2 Position        */
+#define SYS_GPB_MFOS_MFOS2_Msk           (0x1ul << SYS_GPB_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS2 Mask            */
+
+#define SYS_GPB_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPB_MFOS: MFOS3 Position        */
+#define SYS_GPB_MFOS_MFOS3_Msk           (0x1ul << SYS_GPB_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS3 Mask            */
+
+#define SYS_GPB_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPB_MFOS: MFOS4 Position        */
+#define SYS_GPB_MFOS_MFOS4_Msk           (0x1ul << SYS_GPB_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS4 Mask            */
+
+#define SYS_GPB_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPB_MFOS: MFOS5 Position        */
+#define SYS_GPB_MFOS_MFOS5_Msk           (0x1ul << SYS_GPB_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS5 Mask            */
+
+#define SYS_GPB_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPB_MFOS: MFOS6 Position        */
+#define SYS_GPB_MFOS_MFOS6_Msk           (0x1ul << SYS_GPB_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS6 Mask            */
+
+#define SYS_GPB_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPB_MFOS: MFOS7 Position        */
+#define SYS_GPB_MFOS_MFOS7_Msk           (0x1ul << SYS_GPB_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS7 Mask            */
+
+#define SYS_GPB_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPB_MFOS: MFOS8 Position        */
+#define SYS_GPB_MFOS_MFOS8_Msk           (0x1ul << SYS_GPB_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS8 Mask            */
+
+#define SYS_GPB_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPB_MFOS: MFOS9 Position        */
+#define SYS_GPB_MFOS_MFOS9_Msk           (0x1ul << SYS_GPB_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS9 Mask            */
+
+#define SYS_GPB_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPB_MFOS: MFOS10 Position       */
+#define SYS_GPB_MFOS_MFOS10_Msk          (0x1ul << SYS_GPB_MFOS_MFOS10_Pos)                /*!< SYS_T::GPB_MFOS: MFOS10 Mask           */
+
+#define SYS_GPB_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPB_MFOS: MFOS11 Position       */
+#define SYS_GPB_MFOS_MFOS11_Msk          (0x1ul << SYS_GPB_MFOS_MFOS11_Pos)                /*!< SYS_T::GPB_MFOS: MFOS11 Mask           */
+
+#define SYS_GPB_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPB_MFOS: MFOS12 Position       */
+#define SYS_GPB_MFOS_MFOS12_Msk          (0x1ul << SYS_GPB_MFOS_MFOS12_Pos)                /*!< SYS_T::GPB_MFOS: MFOS12 Mask           */
+
+#define SYS_GPB_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPB_MFOS: MFOS13 Position       */
+#define SYS_GPB_MFOS_MFOS13_Msk          (0x1ul << SYS_GPB_MFOS_MFOS13_Pos)                /*!< SYS_T::GPB_MFOS: MFOS13 Mask           */
+
+#define SYS_GPB_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPB_MFOS: MFOS14 Position       */
+#define SYS_GPB_MFOS_MFOS14_Msk          (0x1ul << SYS_GPB_MFOS_MFOS14_Pos)                /*!< SYS_T::GPB_MFOS: MFOS14 Mask           */
+
+#define SYS_GPB_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPB_MFOS: MFOS15 Position       */
+#define SYS_GPB_MFOS_MFOS15_Msk          (0x1ul << SYS_GPB_MFOS_MFOS15_Pos)                /*!< SYS_T::GPB_MFOS: MFOS15 Mask           */
+
+#define SYS_GPC_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPC_MFOS: MFOS0 Position        */
+#define SYS_GPC_MFOS_MFOS0_Msk           (0x1ul << SYS_GPC_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS0 Mask            */
+
+#define SYS_GPC_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPC_MFOS: MFOS1 Position        */
+#define SYS_GPC_MFOS_MFOS1_Msk           (0x1ul << SYS_GPC_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS1 Mask            */
+
+#define SYS_GPC_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPC_MFOS: MFOS2 Position        */
+#define SYS_GPC_MFOS_MFOS2_Msk           (0x1ul << SYS_GPC_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS2 Mask            */
+
+#define SYS_GPC_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPC_MFOS: MFOS3 Position        */
+#define SYS_GPC_MFOS_MFOS3_Msk           (0x1ul << SYS_GPC_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS3 Mask            */
+
+#define SYS_GPC_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPC_MFOS: MFOS4 Position        */
+#define SYS_GPC_MFOS_MFOS4_Msk           (0x1ul << SYS_GPC_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS4 Mask            */
+
+#define SYS_GPC_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPC_MFOS: MFOS5 Position        */
+#define SYS_GPC_MFOS_MFOS5_Msk           (0x1ul << SYS_GPC_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS5 Mask            */
+
+#define SYS_GPC_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPC_MFOS: MFOS6 Position        */
+#define SYS_GPC_MFOS_MFOS6_Msk           (0x1ul << SYS_GPC_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS6 Mask            */
+
+#define SYS_GPC_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPC_MFOS: MFOS7 Position        */
+#define SYS_GPC_MFOS_MFOS7_Msk           (0x1ul << SYS_GPC_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS7 Mask            */
+
+#define SYS_GPC_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPC_MFOS: MFOS8 Position        */
+#define SYS_GPC_MFOS_MFOS8_Msk           (0x1ul << SYS_GPC_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS8 Mask            */
+
+#define SYS_GPC_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPC_MFOS: MFOS9 Position        */
+#define SYS_GPC_MFOS_MFOS9_Msk           (0x1ul << SYS_GPC_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS9 Mask            */
+
+#define SYS_GPC_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPC_MFOS: MFOS10 Position       */
+#define SYS_GPC_MFOS_MFOS10_Msk          (0x1ul << SYS_GPC_MFOS_MFOS10_Pos)                /*!< SYS_T::GPC_MFOS: MFOS10 Mask           */
+
+#define SYS_GPC_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPC_MFOS: MFOS11 Position       */
+#define SYS_GPC_MFOS_MFOS11_Msk          (0x1ul << SYS_GPC_MFOS_MFOS11_Pos)                /*!< SYS_T::GPC_MFOS: MFOS11 Mask           */
+
+#define SYS_GPC_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPC_MFOS: MFOS12 Position       */
+#define SYS_GPC_MFOS_MFOS12_Msk          (0x1ul << SYS_GPC_MFOS_MFOS12_Pos)                /*!< SYS_T::GPC_MFOS: MFOS12 Mask           */
+
+#define SYS_GPC_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPC_MFOS: MFOS13 Position       */
+#define SYS_GPC_MFOS_MFOS13_Msk          (0x1ul << SYS_GPC_MFOS_MFOS13_Pos)                /*!< SYS_T::GPC_MFOS: MFOS13 Mask           */
+
+#define SYS_GPC_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPC_MFOS: MFOS14 Position       */
+#define SYS_GPC_MFOS_MFOS14_Msk          (0x1ul << SYS_GPC_MFOS_MFOS14_Pos)                /*!< SYS_T::GPC_MFOS: MFOS14 Mask           */
+
+#define SYS_GPC_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPC_MFOS: MFOS15 Position       */
+#define SYS_GPC_MFOS_MFOS15_Msk          (0x1ul << SYS_GPC_MFOS_MFOS15_Pos)                /*!< SYS_T::GPC_MFOS: MFOS15 Mask           */
+
+#define SYS_GPD_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPD_MFOS: MFOS0 Position        */
+#define SYS_GPD_MFOS_MFOS0_Msk           (0x1ul << SYS_GPD_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS0 Mask            */
+
+#define SYS_GPD_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPD_MFOS: MFOS1 Position        */
+#define SYS_GPD_MFOS_MFOS1_Msk           (0x1ul << SYS_GPD_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS1 Mask            */
+
+#define SYS_GPD_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPD_MFOS: MFOS2 Position        */
+#define SYS_GPD_MFOS_MFOS2_Msk           (0x1ul << SYS_GPD_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS2 Mask            */
+
+#define SYS_GPD_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPD_MFOS: MFOS3 Position        */
+#define SYS_GPD_MFOS_MFOS3_Msk           (0x1ul << SYS_GPD_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS3 Mask            */
+
+#define SYS_GPD_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPD_MFOS: MFOS4 Position        */
+#define SYS_GPD_MFOS_MFOS4_Msk           (0x1ul << SYS_GPD_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS4 Mask            */
+
+#define SYS_GPD_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPD_MFOS: MFOS5 Position        */
+#define SYS_GPD_MFOS_MFOS5_Msk           (0x1ul << SYS_GPD_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS5 Mask            */
+
+#define SYS_GPD_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPD_MFOS: MFOS6 Position        */
+#define SYS_GPD_MFOS_MFOS6_Msk           (0x1ul << SYS_GPD_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS6 Mask            */
+
+#define SYS_GPD_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPD_MFOS: MFOS7 Position        */
+#define SYS_GPD_MFOS_MFOS7_Msk           (0x1ul << SYS_GPD_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS7 Mask            */
+
+#define SYS_GPD_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPD_MFOS: MFOS8 Position        */
+#define SYS_GPD_MFOS_MFOS8_Msk           (0x1ul << SYS_GPD_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS8 Mask            */
+
+#define SYS_GPD_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPD_MFOS: MFOS9 Position        */
+#define SYS_GPD_MFOS_MFOS9_Msk           (0x1ul << SYS_GPD_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS9 Mask            */
+
+#define SYS_GPD_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPD_MFOS: MFOS10 Position       */
+#define SYS_GPD_MFOS_MFOS10_Msk          (0x1ul << SYS_GPD_MFOS_MFOS10_Pos)                /*!< SYS_T::GPD_MFOS: MFOS10 Mask           */
+
+#define SYS_GPD_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPD_MFOS: MFOS11 Position       */
+#define SYS_GPD_MFOS_MFOS11_Msk          (0x1ul << SYS_GPD_MFOS_MFOS11_Pos)                /*!< SYS_T::GPD_MFOS: MFOS11 Mask           */
+
+#define SYS_GPD_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPD_MFOS: MFOS12 Position       */
+#define SYS_GPD_MFOS_MFOS12_Msk          (0x1ul << SYS_GPD_MFOS_MFOS12_Pos)                /*!< SYS_T::GPD_MFOS: MFOS12 Mask           */
+
+#define SYS_GPD_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPD_MFOS: MFOS13 Position       */
+#define SYS_GPD_MFOS_MFOS13_Msk          (0x1ul << SYS_GPD_MFOS_MFOS13_Pos)                /*!< SYS_T::GPD_MFOS: MFOS13 Mask           */
+
+#define SYS_GPD_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPD_MFOS: MFOS14 Position       */
+#define SYS_GPD_MFOS_MFOS14_Msk          (0x1ul << SYS_GPD_MFOS_MFOS14_Pos)                /*!< SYS_T::GPD_MFOS: MFOS14 Mask           */
+
+#define SYS_GPD_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPD_MFOS: MFOS15 Position       */
+#define SYS_GPD_MFOS_MFOS15_Msk          (0x1ul << SYS_GPD_MFOS_MFOS15_Pos)                /*!< SYS_T::GPD_MFOS: MFOS15 Mask           */
+
+#define SYS_GPE_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPE_MFOS: MFOS0 Position        */
+#define SYS_GPE_MFOS_MFOS0_Msk           (0x1ul << SYS_GPE_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS0 Mask            */
+
+#define SYS_GPE_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPE_MFOS: MFOS1 Position        */
+#define SYS_GPE_MFOS_MFOS1_Msk           (0x1ul << SYS_GPE_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS1 Mask            */
+
+#define SYS_GPE_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPE_MFOS: MFOS2 Position        */
+#define SYS_GPE_MFOS_MFOS2_Msk           (0x1ul << SYS_GPE_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS2 Mask            */
+
+#define SYS_GPE_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPE_MFOS: MFOS3 Position        */
+#define SYS_GPE_MFOS_MFOS3_Msk           (0x1ul << SYS_GPE_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS3 Mask            */
+
+#define SYS_GPE_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPE_MFOS: MFOS4 Position        */
+#define SYS_GPE_MFOS_MFOS4_Msk           (0x1ul << SYS_GPE_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS4 Mask            */
+
+#define SYS_GPE_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPE_MFOS: MFOS5 Position        */
+#define SYS_GPE_MFOS_MFOS5_Msk           (0x1ul << SYS_GPE_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS5 Mask            */
+
+#define SYS_GPE_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPE_MFOS: MFOS6 Position        */
+#define SYS_GPE_MFOS_MFOS6_Msk           (0x1ul << SYS_GPE_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS6 Mask            */
+
+#define SYS_GPE_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPE_MFOS: MFOS7 Position        */
+#define SYS_GPE_MFOS_MFOS7_Msk           (0x1ul << SYS_GPE_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS7 Mask            */
+
+#define SYS_GPE_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPE_MFOS: MFOS8 Position        */
+#define SYS_GPE_MFOS_MFOS8_Msk           (0x1ul << SYS_GPE_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS8 Mask            */
+
+#define SYS_GPE_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPE_MFOS: MFOS9 Position        */
+#define SYS_GPE_MFOS_MFOS9_Msk           (0x1ul << SYS_GPE_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS9 Mask            */
+
+#define SYS_GPE_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPE_MFOS: MFOS10 Position       */
+#define SYS_GPE_MFOS_MFOS10_Msk          (0x1ul << SYS_GPE_MFOS_MFOS10_Pos)                /*!< SYS_T::GPE_MFOS: MFOS10 Mask           */
+
+#define SYS_GPE_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPE_MFOS: MFOS11 Position       */
+#define SYS_GPE_MFOS_MFOS11_Msk          (0x1ul << SYS_GPE_MFOS_MFOS11_Pos)                /*!< SYS_T::GPE_MFOS: MFOS11 Mask           */
+
+#define SYS_GPE_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPE_MFOS: MFOS12 Position       */
+#define SYS_GPE_MFOS_MFOS12_Msk          (0x1ul << SYS_GPE_MFOS_MFOS12_Pos)                /*!< SYS_T::GPE_MFOS: MFOS12 Mask           */
+
+#define SYS_GPE_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPE_MFOS: MFOS13 Position       */
+#define SYS_GPE_MFOS_MFOS13_Msk          (0x1ul << SYS_GPE_MFOS_MFOS13_Pos)                /*!< SYS_T::GPE_MFOS: MFOS13 Mask           */
+
+#define SYS_GPE_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPE_MFOS: MFOS14 Position       */
+#define SYS_GPE_MFOS_MFOS14_Msk          (0x1ul << SYS_GPE_MFOS_MFOS14_Pos)                /*!< SYS_T::GPE_MFOS: MFOS14 Mask           */
+
+#define SYS_GPE_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPE_MFOS: MFOS15 Position       */
+#define SYS_GPE_MFOS_MFOS15_Msk          (0x1ul << SYS_GPE_MFOS_MFOS15_Pos)                /*!< SYS_T::GPE_MFOS: MFOS15 Mask           */
+
+#define SYS_GPF_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPF_MFOS: MFOS0 Position        */
+#define SYS_GPF_MFOS_MFOS0_Msk           (0x1ul << SYS_GPF_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS0 Mask            */
+
+#define SYS_GPF_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPF_MFOS: MFOS1 Position        */
+#define SYS_GPF_MFOS_MFOS1_Msk           (0x1ul << SYS_GPF_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS1 Mask            */
+
+#define SYS_GPF_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPF_MFOS: MFOS2 Position        */
+#define SYS_GPF_MFOS_MFOS2_Msk           (0x1ul << SYS_GPF_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS2 Mask            */
+
+#define SYS_GPF_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPF_MFOS: MFOS3 Position        */
+#define SYS_GPF_MFOS_MFOS3_Msk           (0x1ul << SYS_GPF_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS3 Mask            */
+
+#define SYS_GPF_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPF_MFOS: MFOS4 Position        */
+#define SYS_GPF_MFOS_MFOS4_Msk           (0x1ul << SYS_GPF_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS4 Mask            */
+
+#define SYS_GPF_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPF_MFOS: MFOS5 Position        */
+#define SYS_GPF_MFOS_MFOS5_Msk           (0x1ul << SYS_GPF_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS5 Mask            */
+
+#define SYS_GPF_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPF_MFOS: MFOS6 Position        */
+#define SYS_GPF_MFOS_MFOS6_Msk           (0x1ul << SYS_GPF_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS6 Mask            */
+
+#define SYS_GPF_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPF_MFOS: MFOS7 Position        */
+#define SYS_GPF_MFOS_MFOS7_Msk           (0x1ul << SYS_GPF_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS7 Mask            */
+
+#define SYS_GPF_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPF_MFOS: MFOS8 Position        */
+#define SYS_GPF_MFOS_MFOS8_Msk           (0x1ul << SYS_GPF_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS8 Mask            */
+
+#define SYS_GPF_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPF_MFOS: MFOS9 Position        */
+#define SYS_GPF_MFOS_MFOS9_Msk           (0x1ul << SYS_GPF_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS9 Mask            */
+
+#define SYS_GPF_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPF_MFOS: MFOS10 Position       */
+#define SYS_GPF_MFOS_MFOS10_Msk          (0x1ul << SYS_GPF_MFOS_MFOS10_Pos)                /*!< SYS_T::GPF_MFOS: MFOS10 Mask           */
+
+#define SYS_GPF_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPF_MFOS: MFOS11 Position       */
+#define SYS_GPF_MFOS_MFOS11_Msk          (0x1ul << SYS_GPF_MFOS_MFOS11_Pos)                /*!< SYS_T::GPF_MFOS: MFOS11 Mask           */
+
+#define SYS_GPF_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPF_MFOS: MFOS12 Position       */
+#define SYS_GPF_MFOS_MFOS12_Msk          (0x1ul << SYS_GPF_MFOS_MFOS12_Pos)                /*!< SYS_T::GPF_MFOS: MFOS12 Mask           */
+
+#define SYS_GPF_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPF_MFOS: MFOS13 Position       */
+#define SYS_GPF_MFOS_MFOS13_Msk          (0x1ul << SYS_GPF_MFOS_MFOS13_Pos)                /*!< SYS_T::GPF_MFOS: MFOS13 Mask           */
+
+#define SYS_GPF_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPF_MFOS: MFOS14 Position       */
+#define SYS_GPF_MFOS_MFOS14_Msk          (0x1ul << SYS_GPF_MFOS_MFOS14_Pos)                /*!< SYS_T::GPF_MFOS: MFOS14 Mask           */
+
+#define SYS_GPF_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPF_MFOS: MFOS15 Position       */
+#define SYS_GPF_MFOS_MFOS15_Msk          (0x1ul << SYS_GPF_MFOS_MFOS15_Pos)                /*!< SYS_T::GPF_MFOS: MFOS15 Mask           */
+
+#define SYS_GPG_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPG_MFOS: MFOS0 Position        */
+#define SYS_GPG_MFOS_MFOS0_Msk           (0x1ul << SYS_GPG_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS0 Mask            */
+
+#define SYS_GPG_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPG_MFOS: MFOS1 Position        */
+#define SYS_GPG_MFOS_MFOS1_Msk           (0x1ul << SYS_GPG_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS1 Mask            */
+
+#define SYS_GPG_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPG_MFOS: MFOS2 Position        */
+#define SYS_GPG_MFOS_MFOS2_Msk           (0x1ul << SYS_GPG_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS2 Mask            */
+
+#define SYS_GPG_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPG_MFOS: MFOS3 Position        */
+#define SYS_GPG_MFOS_MFOS3_Msk           (0x1ul << SYS_GPG_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS3 Mask            */
+
+#define SYS_GPG_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPG_MFOS: MFOS4 Position        */
+#define SYS_GPG_MFOS_MFOS4_Msk           (0x1ul << SYS_GPG_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS4 Mask            */
+
+#define SYS_GPG_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPG_MFOS: MFOS5 Position        */
+#define SYS_GPG_MFOS_MFOS5_Msk           (0x1ul << SYS_GPG_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS5 Mask            */
+
+#define SYS_GPG_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPG_MFOS: MFOS6 Position        */
+#define SYS_GPG_MFOS_MFOS6_Msk           (0x1ul << SYS_GPG_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS6 Mask            */
+
+#define SYS_GPG_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPG_MFOS: MFOS7 Position        */
+#define SYS_GPG_MFOS_MFOS7_Msk           (0x1ul << SYS_GPG_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS7 Mask            */
+
+#define SYS_GPG_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPG_MFOS: MFOS8 Position        */
+#define SYS_GPG_MFOS_MFOS8_Msk           (0x1ul << SYS_GPG_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS8 Mask            */
+
+#define SYS_GPG_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPG_MFOS: MFOS9 Position        */
+#define SYS_GPG_MFOS_MFOS9_Msk           (0x1ul << SYS_GPG_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS9 Mask            */
+
+#define SYS_GPG_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPG_MFOS: MFOS10 Position       */
+#define SYS_GPG_MFOS_MFOS10_Msk          (0x1ul << SYS_GPG_MFOS_MFOS10_Pos)                /*!< SYS_T::GPG_MFOS: MFOS10 Mask           */
+
+#define SYS_GPG_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPG_MFOS: MFOS11 Position       */
+#define SYS_GPG_MFOS_MFOS11_Msk          (0x1ul << SYS_GPG_MFOS_MFOS11_Pos)                /*!< SYS_T::GPG_MFOS: MFOS11 Mask           */
+
+#define SYS_GPG_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPG_MFOS: MFOS12 Position       */
+#define SYS_GPG_MFOS_MFOS12_Msk          (0x1ul << SYS_GPG_MFOS_MFOS12_Pos)                /*!< SYS_T::GPG_MFOS: MFOS12 Mask           */
+
+#define SYS_GPG_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPG_MFOS: MFOS13 Position       */
+#define SYS_GPG_MFOS_MFOS13_Msk          (0x1ul << SYS_GPG_MFOS_MFOS13_Pos)                /*!< SYS_T::GPG_MFOS: MFOS13 Mask           */
+
+#define SYS_GPG_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPG_MFOS: MFOS14 Position       */
+#define SYS_GPG_MFOS_MFOS14_Msk          (0x1ul << SYS_GPG_MFOS_MFOS14_Pos)                /*!< SYS_T::GPG_MFOS: MFOS14 Mask           */
+
+#define SYS_GPG_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPG_MFOS: MFOS15 Position       */
+#define SYS_GPG_MFOS_MFOS15_Msk          (0x1ul << SYS_GPG_MFOS_MFOS15_Pos)                /*!< SYS_T::GPG_MFOS: MFOS15 Mask           */
+
+#define SYS_GPH_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPH_MFOS: MFOS0 Position        */
+#define SYS_GPH_MFOS_MFOS0_Msk           (0x1ul << SYS_GPH_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS0 Mask            */
+
+#define SYS_GPH_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPH_MFOS: MFOS1 Position        */
+#define SYS_GPH_MFOS_MFOS1_Msk           (0x1ul << SYS_GPH_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS1 Mask            */
+
+#define SYS_GPH_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPH_MFOS: MFOS2 Position        */
+#define SYS_GPH_MFOS_MFOS2_Msk           (0x1ul << SYS_GPH_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS2 Mask            */
+
+#define SYS_GPH_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPH_MFOS: MFOS3 Position        */
+#define SYS_GPH_MFOS_MFOS3_Msk           (0x1ul << SYS_GPH_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS3 Mask            */
+
+#define SYS_GPH_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPH_MFOS: MFOS4 Position        */
+#define SYS_GPH_MFOS_MFOS4_Msk           (0x1ul << SYS_GPH_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS4 Mask            */
+
+#define SYS_GPH_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPH_MFOS: MFOS5 Position        */
+#define SYS_GPH_MFOS_MFOS5_Msk           (0x1ul << SYS_GPH_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS5 Mask            */
+
+#define SYS_GPH_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPH_MFOS: MFOS6 Position        */
+#define SYS_GPH_MFOS_MFOS6_Msk           (0x1ul << SYS_GPH_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS6 Mask            */
+
+#define SYS_GPH_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPH_MFOS: MFOS7 Position        */
+#define SYS_GPH_MFOS_MFOS7_Msk           (0x1ul << SYS_GPH_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS7 Mask            */
+
+#define SYS_GPH_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPH_MFOS: MFOS8 Position        */
+#define SYS_GPH_MFOS_MFOS8_Msk           (0x1ul << SYS_GPH_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS8 Mask            */
+
+#define SYS_GPH_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPH_MFOS: MFOS9 Position        */
+#define SYS_GPH_MFOS_MFOS9_Msk           (0x1ul << SYS_GPH_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS9 Mask            */
+
+#define SYS_GPH_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPH_MFOS: MFOS10 Position       */
+#define SYS_GPH_MFOS_MFOS10_Msk          (0x1ul << SYS_GPH_MFOS_MFOS10_Pos)                /*!< SYS_T::GPH_MFOS: MFOS10 Mask           */
+
+#define SYS_GPH_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPH_MFOS: MFOS11 Position       */
+#define SYS_GPH_MFOS_MFOS11_Msk          (0x1ul << SYS_GPH_MFOS_MFOS11_Pos)                /*!< SYS_T::GPH_MFOS: MFOS11 Mask           */
+
+#define SYS_GPH_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPH_MFOS: MFOS12 Position       */
+#define SYS_GPH_MFOS_MFOS12_Msk          (0x1ul << SYS_GPH_MFOS_MFOS12_Pos)                /*!< SYS_T::GPH_MFOS: MFOS12 Mask           */
+
+#define SYS_GPH_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPH_MFOS: MFOS13 Position       */
+#define SYS_GPH_MFOS_MFOS13_Msk          (0x1ul << SYS_GPH_MFOS_MFOS13_Pos)                /*!< SYS_T::GPH_MFOS: MFOS13 Mask           */
+
+#define SYS_GPH_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPH_MFOS: MFOS14 Position       */
+#define SYS_GPH_MFOS_MFOS14_Msk          (0x1ul << SYS_GPH_MFOS_MFOS14_Pos)                /*!< SYS_T::GPH_MFOS: MFOS14 Mask           */
+
+#define SYS_GPH_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPH_MFOS: MFOS15 Position       */
+#define SYS_GPH_MFOS_MFOS15_Msk          (0x1ul << SYS_GPH_MFOS_MFOS15_Pos)                /*!< SYS_T::GPH_MFOS: MFOS15 Mask           */
+
+#define SYS_SRAM_INTCTL_PERRIEN_Pos      (0)                                               /*!< SYS_T::SRAM_INTCTL: PERRIEN Position   */
+#define SYS_SRAM_INTCTL_PERRIEN_Msk      (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos)            /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask       */
+
+#define SYS_SRAM_STATUS_PERRIF_Pos       (0)                                               /*!< SYS_T::SRAM_STATUS: PERRIF Position    */
+#define SYS_SRAM_STATUS_PERRIF_Msk       (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos)             /*!< SYS_T::SRAM_STATUS: PERRIF Mask        */
+
+#define SYS_SRAM_ERRADDR_ERRADDR_Pos     (0)                                               /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position  */
+#define SYS_SRAM_ERRADDR_ERRADDR_Msk     (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos)    /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask      */
+
+#define SYS_SRAM_BISTCTL_SRBIST0_Pos     (0)                                               /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position  */
+#define SYS_SRAM_BISTCTL_SRBIST0_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos)           /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask      */
+
+#define SYS_SRAM_BISTCTL_SRBIST1_Pos     (1)                                               /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position  */
+#define SYS_SRAM_BISTCTL_SRBIST1_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos)           /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask      */
+
+#define SYS_SRAM_BISTCTL_CRBIST_Pos      (2)                                               /*!< SYS_T::SRAM_BISTCTL: CRBIST Position   */
+#define SYS_SRAM_BISTCTL_CRBIST_Msk      (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos)            /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask       */
+
+#define SYS_SRAM_BISTCTL_CANBIST_Pos     (3)                                               /*!< SYS_T::SRAM_BISTCTL: CANBIST Position  */
+#define SYS_SRAM_BISTCTL_CANBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos)           /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask      */
+
+#define SYS_SRAM_BISTCTL_USBBIST_Pos     (4)                                               /*!< SYS_T::SRAM_BISTCTL: USBBIST Position  */
+#define SYS_SRAM_BISTCTL_USBBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos)           /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask      */
+
+#define SYS_SRAM_BISTCTL_SPIMBIST_Pos    (5)                                               /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */
+#define SYS_SRAM_BISTCTL_SPIMBIST_Msk    (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos)          /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask     */
+
+#define SYS_SRAM_BISTCTL_EMCBIST_Pos     (6)                                               /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position  */
+#define SYS_SRAM_BISTCTL_EMCBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos)           /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask      */
+
+#define SYS_SRAM_BISTCTL_PDMABIST_Pos    (7)                                               /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */
+#define SYS_SRAM_BISTCTL_PDMABIST_Msk    (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos)          /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask     */
+
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos  (8)                                               /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk  (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos)        /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask   */
+
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos  (9)                                               /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk  (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos)        /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask   */
+
+#define SYS_SRAM_BISTCTL_SRB0S0_Pos      (16)                                              /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position   */
+#define SYS_SRAM_BISTCTL_SRB0S0_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB0S1_Pos      (17)                                              /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position   */
+#define SYS_SRAM_BISTCTL_SRB0S1_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S0_Pos      (18)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S0_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S1_Pos      (19)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S1_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S2_Pos      (20)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S2_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S3_Pos      (21)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S3_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S4_Pos      (22)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S4_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask       */
+
+#define SYS_SRAM_BISTCTL_SRB1S5_Pos      (23)                                              /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position   */
+#define SYS_SRAM_BISTCTL_SRB1S5_Msk      (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos)            /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask       */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos   (0)                                               /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos)         /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask    */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos   (1)                                               /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos)         /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask    */
+
+#define SYS_SRAM_BISTSTS_CRBISTEF_Pos    (2)                                               /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
+#define SYS_SRAM_BISTSTS_CRBISTEF_Msk    (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos)          /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask     */
+
+#define SYS_SRAM_BISTSTS_CANBEF_Pos      (3)                                               /*!< SYS_T::SRAM_BISTSTS: CANBEF Position   */
+#define SYS_SRAM_BISTSTS_CANBEF_Msk      (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos)            /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask       */
+
+#define SYS_SRAM_BISTSTS_USBBEF_Pos      (4)                                               /*!< SYS_T::SRAM_BISTSTS: USBBEF Position   */
+#define SYS_SRAM_BISTSTS_USBBEF_Msk      (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos)            /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask       */
+
+#define SYS_SRAM_BISTSTS_SRBEND0_Pos     (16)                                              /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position  */
+#define SYS_SRAM_BISTSTS_SRBEND0_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos)           /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask      */
+
+#define SYS_SRAM_BISTSTS_SRBEND1_Pos     (17)                                              /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position  */
+#define SYS_SRAM_BISTSTS_SRBEND1_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos)           /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask      */
+
+#define SYS_SRAM_BISTSTS_CRBEND_Pos      (18)                                              /*!< SYS_T::SRAM_BISTSTS: CRBEND Position   */
+#define SYS_SRAM_BISTSTS_CRBEND_Msk      (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos)            /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask       */
+
+#define SYS_SRAM_BISTSTS_CANBEND_Pos     (19)                                              /*!< SYS_T::SRAM_BISTSTS: CANBEND Position  */
+#define SYS_SRAM_BISTSTS_CANBEND_Msk     (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos)           /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask      */
+
+#define SYS_SRAM_BISTSTS_USBBEND_Pos     (20)                                              /*!< SYS_T::SRAM_BISTSTS: USBBEND Position  */
+#define SYS_SRAM_BISTSTS_USBBEND_Msk     (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos)           /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask      */
+
+#define SYS_IRCTCTL_FREQSEL_Pos          (0)                                               /*!< SYS_T::IRCTCTL: FREQSEL Position       */
+#define SYS_IRCTCTL_FREQSEL_Msk          (0x3ul << SYS_IRCTCTL_FREQSEL_Pos)                /*!< SYS_T::IRCTCTL: FREQSEL Mask           */
+
+#define SYS_IRCTCTL_LOOPSEL_Pos          (4)                                               /*!< SYS_T::IRCTCTL: LOOPSEL Position       */
+#define SYS_IRCTCTL_LOOPSEL_Msk          (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)                /*!< SYS_T::IRCTCTL: LOOPSEL Mask           */
+
+#define SYS_IRCTCTL_RETRYCNT_Pos         (6)                                               /*!< SYS_T::IRCTCTL: RETRYCNT Position      */
+#define SYS_IRCTCTL_RETRYCNT_Msk         (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos)               /*!< SYS_T::IRCTCTL: RETRYCNT Mask          */
+
+#define SYS_IRCTCTL_CESTOPEN_Pos         (8)                                               /*!< SYS_T::IRCTCTL: CESTOPEN Position      */
+#define SYS_IRCTCTL_CESTOPEN_Msk         (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos)               /*!< SYS_T::IRCTCTL: CESTOPEN Mask          */
+
+#define SYS_IRCTCTL_REFCKSEL_Pos         (10)                                              /*!< SYS_T::IRCTCTL: REFCKSEL Position      */
+#define SYS_IRCTCTL_REFCKSEL_Msk         (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos)               /*!< SYS_T::IRCTCTL: REFCKSEL Mask          */
+
+#define SYS_IRCTIEN_TFAILIEN_Pos         (1)                                               /*!< SYS_T::IRCTIEN: TFAILIEN Position      */
+#define SYS_IRCTIEN_TFAILIEN_Msk         (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)               /*!< SYS_T::IRCTIEN: TFAILIEN Mask          */
+
+#define SYS_IRCTIEN_CLKEIEN_Pos          (2)                                               /*!< SYS_T::IRCTIEN: CLKEIEN Position       */
+#define SYS_IRCTIEN_CLKEIEN_Msk          (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)                /*!< SYS_T::IRCTIEN: CLKEIEN Mask           */
+
+#define SYS_IRCTISTS_FREQLOCK_Pos        (0)                                               /*!< SYS_T::IRCTISTS: FREQLOCK Position     */
+#define SYS_IRCTISTS_FREQLOCK_Msk        (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)              /*!< SYS_T::IRCTISTS: FREQLOCK Mask         */
+
+#define SYS_IRCTISTS_TFAILIF_Pos         (1)                                               /*!< SYS_T::IRCTISTS: TFAILIF Position      */
+#define SYS_IRCTISTS_TFAILIF_Msk         (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)               /*!< SYS_T::IRCTISTS: TFAILIF Mask          */
+
+#define SYS_IRCTISTS_CLKERRIF_Pos        (2)                                               /*!< SYS_T::IRCTISTS: CLKERRIF Position     */
+#define SYS_IRCTISTS_CLKERRIF_Msk        (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)              /*!< SYS_T::IRCTISTS: CLKERRIF Mask         */
+
+#define SYS_REGLCTL_REGLCTL_Pos          (0)                                               /*!< SYS_T::REGLCTL: REGLCTL Position       */
+#define SYS_REGLCTL_REGLCTL_Msk          (0x1ul << SYS_REGLCTL_REGLCTL_Pos)                /*!< SYS_T::REGLCTL: REGLCTL Mask           */
+
+#define SYS_PLCTL_PLSEL_Pos              (0)                                               /*!< SYS_T::PLCTL: PLSEL Position           */
+#define SYS_PLCTL_PLSEL_Msk              (0x3ul << SYS_PLCTL_PLSEL_Pos)                    /*!< SYS_T::PLCTL: PLSEL Mask               */
+
+#define SYS_PLCTL_LVSSTEP_Pos            (16)                                              /*!< SYS_T::PLCTL: LVSSTEP Position         */
+#define SYS_PLCTL_LVSSTEP_Msk            (0x3ful << SYS_PLCTL_LVSSTEP_Pos)                 /*!< SYS_T::PLCTL: LVSSTEP Mask             */
+
+#define SYS_PLCTL_LVSPRD_Pos             (24)                                              /*!< SYS_T::PLCTL: LVSPRD Position          */
+#define SYS_PLCTL_LVSPRD_Msk             (0xfful << SYS_PLCTL_LVSPRD_Pos)                  /*!< SYS_T::PLCTL: LVSPRD Mask              */
+
+#define SYS_PLSTS_PLCBUSY_Pos            (0)                                               /*!< SYS_T::PLSTS: PLCBUSY Position         */
+#define SYS_PLSTS_PLCBUSY_Msk            (0x1ul << SYS_PLSTS_PLCBUSY_Pos)                  /*!< SYS_T::PLSTS: PLCBUSY Mask             */
+
+#define SYS_PLSTS_PLSTATUS_Pos           (8)                                               /*!< SYS_T::PLSTS: PLSTATUS Position        */
+#define SYS_PLSTS_PLSTATUS_Msk           (0x3ul << SYS_PLSTS_PLSTATUS_Pos)                 /*!< SYS_T::PLSTS: PLSTATUS Mask            */
+
+#define SYS_AHBMCTL_INTACTEN_Pos         (0)                                               /*!< SYS_T::AHBMCTL: INTACTEN Position      */
+#define SYS_AHBMCTL_INTACTEN_Msk         (0x1ul << SYS_AHBMCTL_INTACTEN_Pos)               /*!< SYS_T::AHBMCTL: INTACTEN Mask          */
+
+/**@}*/ /* SYS_CONST */
+/**@}*/ /* end of SYS register group */
+
+
+
+/*---------------------- System Clock Controller -------------------------*/
+/**
+    @addtogroup CLK System Clock Controller(CLK)
+    Memory Mapped Structure for CLK Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var CLK_T::PWRCTL
+     * Offset: 0x00  System Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTEN     |HXT Enable Bit (Write Protect)
+     * |        |          |The bit default value is set by flash controller user configuration register CONFIG0 [26]
+     * |        |          |When the default clock source is from HXT, this bit is set to 1 automatically.
+     * |        |          |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |LXTEN     |LXT Enable Bit (Write Protect)
+     * |        |          |0 = 32.768 kHz external low speed crystal (LXT) Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal (LXT) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |HIRCEN    |HIRC Enable Bit (Write Protect)
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |LIRCEN    |LIRC Enable Bit (Write Protect)
+     * |        |          |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
+     * |        |          |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |PDWKDLY   |Enable the Wake-up Delay Counter (Write Protect)
+     * |        |          |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+     * |        |          |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |0 = Clock cycles delay Disabled.
+     * |        |          |1 = Clock cycles delay Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |PDWKIEN   |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
+     * |        |          |0 = Power-down mode wake-up interrupt Disabled.
+     * |        |          |1 = Power-down mode wake-up interrupt Enabled.
+     * |        |          |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |PDWKIF    |Power-down Mode Wake-up Interrupt Status
+     * |        |          |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
+     * |        |          |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+     * |[7]     |PDEN      |System Power-down Enable (Write Protect)
+     * |        |          |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+     * |        |          |When chip wakes up from Power-down mode, this bit is auto cleared
+     * |        |          |Users need to set this bit again for next Power-down.
+     * |        |          |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
+     * |        |          |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection
+     * |        |          |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
+     * |        |          |0 = Chip will not enter Power-down mode after CPU sleep command WFI.
+     * |        |          |1 = Chip enters Power-down mode after CPU sleep command WFI.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:10] |HXTGAIN   |HXT Gain Control Bit (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |Gain control is used to enlarge the gain of crystal to make sure crystal work normally
+     * |        |          |If gain control is enabled, crystal will consume more power than gain control off.
+     * |        |          |00 = HXT frequency is lower than from 8 MHz.
+     * |        |          |01 = HXT frequency is from 8 MHz to 12 MHz.
+     * |        |          |10 = HXT frequency is from 12 MHz to 16 MHz.
+     * |        |          |11 = HXT frequency is higher than 16 MHz.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[12]    |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = Select INV type.
+     * |        |          |1 = Select GM type.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13]    |HXTTBEN   |HXT Crystal TURBO Mode (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = HXT Crystal TURBO mode disabled.
+     * |        |          |1 = HXT Crystal TURBO mode enabled.
+     * |[17:16] |HIRCSTBS  |HIRC Stable Count Select (Write Protect)
+     * |        |          |00 = HIRC stable count is 64 clocks.
+     * |        |          |01 = HIRC stable count is 24 clocks.
+     * |        |          |others = Reserved.
+     * @var CLK_T::AHBCLK
+     * Offset: 0x04  AHB Devices Clock Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |PDMACKEN  |PDMA Controller Clock Enable Bit
+     * |        |          |0 = PDMA peripheral clock Disabled.
+     * |        |          |1 = PDMA peripheral clock Enabled.
+     * |[2]     |ISPCKEN   |Flash ISP Controller Clock Enable Bit
+     * |        |          |0 = Flash ISP peripheral clock Disabled.
+     * |        |          |1 = Flash ISP peripheral clock Enabled.
+     * |[3]     |EBICKEN   |EBI Controller Clock Enable Bit
+     * |        |          |0 = EBI peripheral clock Disabled.
+     * |        |          |1 = EBI peripheral clock Enabled.
+     * |[5]     |EMACCKEN  |Ethernet Controller Clock Enable Bit
+     * |        |          |0 = Ethernet Controller engine clock Disabled.
+     * |        |          |1 = Ethernet Controller engine clock Enabled.
+     * |[6]     |SDH0CKEN  |SD0 Controller Clock Enable Bit
+     * |        |          |0 = SD0 engine clock Disabled.
+     * |        |          |1 = SD0 engine clock Enabled.
+     * |[7]     |CRCCKEN   |CRC Generator Controller Clock Enable Bit
+     * |        |          |0 = CRC peripheral clock Disabled.
+     * |        |          |1 = CRC peripheral clock Enabled.
+     * |[10]    |HSUSBDCKEN|HSUSB Device Clock Enable Bit
+     * |        |          |0 = HSUSB device controller's clock Disabled.
+     * |        |          |1 = HSUSB device controller's clock Enabled.
+     * |[12]    |CRPTCKEN  |Cryptographic Accelerator Clock Enable Bit
+     * |        |          |0 = Cryptographic Accelerator clock Disabled.
+     * |        |          |1 = Cryptographic Accelerator clock Enabled.
+     * |[14]    |SPIMCKEN  |SPIM Controller Clock Enable Bit
+     * |        |          |0 = SPIM controller clock Disabled.
+     * |        |          |1 = SPIM controller clock Enabled.
+     * |[15]    |FMCIDLE   |Flash Memory Controller Clock Enable Bit in IDLE Mode
+     * |        |          |0 = FMC clock Disabled when chip is under IDLE mode.
+     * |        |          |1 = FMC clock Enabled when chip is under IDLE mode.
+     * |[16]    |USBHCKEN  |USB HOST Controller Clock Enable Bit
+     * |        |          |0 = USB HOST peripheral clock Disabled.
+     * |        |          |1 = USB HOST peripheral clock Enabled.
+     * |[17]    |SDH1CKEN  |SD1 Controller Clock Enable Bit
+     * |        |          |0 = SD1 engine clock Disabled.
+     * |        |          |1 = SD1 engine clock Enabled.
+     * @var CLK_T::APBCLK0
+     * Offset: 0x08  APB Devices Clock Enable Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WDTCKEN   |Watchdog Timer Clock Enable Bit (Write Protect)
+     * |        |          |0 = Watchdog timer clock Disabled.
+     * |        |          |1 = Watchdog timer clock Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |RTCCKEN   |Real-time-clock APB Interface Clock Enable Bit
+     * |        |          |This bit is used to control the RTC APB clock only
+     * |        |          |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
+     * |        |          |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = RTC clock Disabled.
+     * |        |          |1 = RTC clock Enabled.
+     * |[2]     |TMR0CKEN  |Timer0 Clock Enable Bit
+     * |        |          |0 = Timer0 clock Disabled.
+     * |        |          |1 = Timer0 clock Enabled.
+     * |[3]     |TMR1CKEN  |Timer1 Clock Enable Bit
+     * |        |          |0 = Timer1 clock Disabled.
+     * |        |          |1 = Timer1 clock Enabled.
+     * |[4]     |TMR2CKEN  |Timer2 Clock Enable Bit
+     * |        |          |0 = Timer2 clock Disabled.
+     * |        |          |1 = Timer2 clock Enabled.
+     * |[5]     |TMR3CKEN  |Timer3 Clock Enable Bit
+     * |        |          |0 = Timer3 clock Disabled.
+     * |        |          |1 = Timer3 clock Enabled.
+     * |[6]     |CLKOCKEN  |CLKO Clock Enable Bit
+     * |        |          |0 = CLKO clock Disabled.
+     * |        |          |1 = CLKO clock Enabled.
+     * |[7]     |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+     * |        |          |0 = Analog comparator 0/1 clock Disabled.
+     * |        |          |1 = Analog comparator 0/1 clock Enabled.
+     * |[8]     |I2C0CKEN  |I2C0 Clock Enable Bit
+     * |        |          |0 = I2C0 clock Disabled.
+     * |        |          |1 = I2C0 clock Enabled.
+     * |[9]     |I2C1CKEN  |I2C1 Clock Enable Bit
+     * |        |          |0 = I2C1 clock Disabled.
+     * |        |          |1 = I2C1 clock Enabled.
+     * |[10]    |I2C2CKEN  |I2C2 Clock Enable Bit
+     * |        |          |0 = I2C2 clock Disabled.
+     * |        |          |1 = I2C2 clock Enabled.
+     * |[12]    |SPI0CKEN  |SPI0 Clock Enable Bit
+     * |        |          |0 = SPI0 clock Disabled.
+     * |        |          |1 = SPI0 clock Enabled.
+     * |[13]    |SPI1CKEN  |SPI1 Clock Enable Bit
+     * |        |          |0 = SPI1 clock Disabled.
+     * |        |          |1 = SPI1 clock Enabled.
+     * |[14]    |SPI2CKEN  |SPI2 Clock Enable Bit
+     * |        |          |0 = SPI2 clock Disabled.
+     * |        |          |1 = SPI2 clock Enabled.
+     * |[15]    |SPI3CKEN  |SPI3 Clock Enable Bit
+     * |        |          |0 = SPI3 clock Disabled.
+     * |        |          |1 = SPI3 clock Enabled.
+     * |[16]    |UART0CKEN |UART0 Clock Enable Bit
+     * |        |          |0 = UART0 clock Disabled.
+     * |        |          |1 = UART0 clock Enabled.
+     * |[17]    |UART1CKEN |UART1 Clock Enable Bit
+     * |        |          |0 = UART1 clock Disabled.
+     * |        |          |1 = UART1 clock Enabled.
+     * |[18]    |UART2CKEN |UART2 Clock Enable Bit
+     * |        |          |0 = UART2 clock Disabled.
+     * |        |          |1 = UART2 clock Enabled.
+     * |[19]    |UART3CKEN |UART3 Clock Enable Bit
+     * |        |          |0 = UART3 clock Disabled.
+     * |        |          |1 = UART3 clock Enabled.
+     * |[20]    |UART4CKEN |UART4 Clock Enable Bit
+     * |        |          |0 = UART4 clock Disabled.
+     * |        |          |1 = UART4 clock Enabled.
+     * |[21]    |UART5CKEN |UART5 Clock Enable Bit
+     * |        |          |0 = UART5 clock Disabled.
+     * |        |          |1 = UART5 clock Enabled.
+     * |[24]    |CAN0CKEN  |CAN0 Clock Enable Bit
+     * |        |          |0 = CAN0 clock Disabled.
+     * |        |          |1 = CAN0 clock Enabled.
+     * |[25]    |CAN1CKEN  |CAN1 Clock Enable Bit
+     * |        |          |0 = CAN1 clock Disabled.
+     * |        |          |1 = CAN1 clock Enabled.
+     * |[26]    |OTGCKEN   |USB OTG Clock Enable Bit
+     * |        |          |0 = USB OTG clock Disabled.
+     * |        |          |1 = USB OTG clock Enabled.
+     * |[27]    |USBDCKEN  |USB Device Clock Enable Bit
+     * |        |          |0 = USB Device clock Disabled.
+     * |        |          |1 = USB Device clock Enabled.
+     * |[28]    |EADCCKEN  |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
+     * |        |          |0 = EADC clock Disabled.
+     * |        |          |1 = EADC clock Enabled.
+     * |[29]    |I2S0CKEN  |I2S0 Clock Enable Bit
+     * |        |          |0 = I2S0 Clock Disabled.
+     * |        |          |1 = I2S0 Clock Enabled.
+     * |[30]    |HSOTGCKEN |HSUSB OTG Clock Enable Bit
+     * |        |          |0 = HSUSB OTG clock Disabled.
+     * |        |          |1 = HSUSB OTG clock Enabled.
+     * @var CLK_T::APBCLK1
+     * Offset: 0x0C  APB Devices Clock Enable Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SC0CKEN   |SC0 Clock Enable Bit
+     * |        |          |0 = SC0 clock Disabled.
+     * |        |          |1 = SC0 clock Enabled.
+     * |[1]     |SC1CKEN   |SC1 Clock Enable Bit
+     * |        |          |0 = SC1 clock Disabled.
+     * |        |          |1 = SC1 clock Enabled.
+     * |[2]     |SC2CKEN   |SC2 Clock Enable Bit
+     * |        |          |0 = SC2 clock Disabled.
+     * |        |          |1 = SC2 clock Enabled.
+     * |[6]     |SPI4CKEN  |SPI4 Clock Enable Bit
+     * |        |          |0 = SPI4 clock Disabled.
+     * |        |          |1 = SPI4 clock Enabled.
+     * |[8]     |USCI0CKEN |USCI0 Clock Enable Bit
+     * |        |          |0 = USCI0 clock Disabled.
+     * |        |          |1 = USCI0 clock Enabled.
+     * |[9]     |USCI1CKEN |USCI1 Clock Enable Bit
+     * |        |          |0 = USCI1 clock Disabled.
+     * |        |          |1 = USCI1 clock Enabled.
+     * |[12]    |DACCKEN   |DAC Clock Enable Bit
+     * |        |          |0 = DAC clock Disabled.
+     * |        |          |1 = DAC clock Enabled.
+     * |[16]    |EPWM0CKEN |EPWM0 Clock Enable Bit
+     * |        |          |0 = EPWM0 clock Disabled.
+     * |        |          |1 = EPWM0 clock Enabled.
+     * |[17]    |EPWM1CKEN |EPWM1 Clock Enable Bit
+     * |        |          |0 = EPWM1 clock Disabled.
+     * |        |          |1 = EPWM1 clock Enabled.
+     * |[18]    |BPWM0CKEN |BPWM0 Clock Enable Bit
+     * |        |          |0 = BPWM0 clock Disabled.
+     * |        |          |1 = BPWM0 clock Enabled.
+     * |[19]    |BPWM1CKEN |BPWM1 Clock Enable Bit
+     * |        |          |0 = BPWM1 clock Disabled.
+     * |        |          |1 = BPWM1 clock Enabled.
+     * |[22]    |QEI0CKEN  |QEI0 Clock Enable Bit
+     * |        |          |0 = QEI0 clock Disabled.
+     * |        |          |1 = QEI0 clock Enabled.
+     * |[23]    |QEI1CKEN  |QEI1 Clock Enable Bit
+     * |        |          |0 = QEI1 clock Disabled.
+     * |        |          |1 = QEI1 clock Enabled.
+     * |[26]    |ECAP0CKEN |ECAP0 Clock Enable Bit
+     * |        |          |0 = ECAP0 clock Disabled.
+     * |        |          |1 = ECAP0 clock Enabled.
+     * |[27]    |ECAP1CKEN |ECAP1 Clock Enable Bit
+     * |        |          |0 = ECAP1 clock Disabled.
+     * |        |          |1 = ECAP1 clock Enabled.
+     * |[30]    |OPACKEN   |OP Amplifier (OPA) Clock Enable Bit
+     * |        |          |0 = OPA clock Disabled.
+     * |        |          |1 = OPA clock Enabled.
+     * @var CLK_T::CLKSEL0
+     * Offset: 0x10  Clock Source Select Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |HCLKSEL   |HCLK Clock Source Selection (Write Protect)
+     * |        |          |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+     * |        |          |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset
+     * |        |          |Therefore the default value is either 000b or 111b.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from PLL.
+     * |        |          |011 = Clock source from LIRC.
+     * |        |          |111 = Clock source from HIRC.
+     * |        |          |Other = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5:3]   |STCLKSEL  |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+     * |        |          |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from HXT/2.
+     * |        |          |011 = Clock source from HCLK/2.
+     * |        |          |111 = Clock source from HIRC/2.
+     * |        |          |Note: if SysTick clock source is not from HCLK (i.e
+     * |        |          |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[21:20] |SDH0SEL   |SD0 Engine Clock Source Selection (Write Protect)
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |[23:22] |SDH1SEL   |SD1 Engine Clock Source Selection (Write Protect)
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * @var CLK_T::CLKSEL1
+     * Offset: 0x14  Clock Source Select Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |WDTSEL    |Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |00 = Reserved.
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10:8]  |TMR0SEL   |TIMER0 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM0 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[14:12] |TMR1SEL   |TIMER1 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM1 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[18:16] |TMR2SEL   |TIMER2 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM2 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[22:20] |TMR3SEL   |TIMER3 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM3 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[25:24] |UART0SEL  |UART0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[27:26] |UART1SEL  |UART1 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[29:28] |CLKOSEL   |Clock Divider Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[31:30] |WWDTSEL   |Window Watchdog Timer Clock Source Selection
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Others = Reserved.
+     * @var CLK_T::CLKSEL2
+     * Offset: 0x18  Clock Source Select Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EPWM0SEL  |EPWM0 Clock Source Selection
+     * |        |          |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[1]     |EPWM1SEL  |EPWM1 Clock Source Selection
+     * |        |          |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[3:2]   |SPI0SEL   |SPI0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SPI1SEL   |SPI1 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[7:6]   |SPI2SEL   |SPI2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[8]     |BPWM0SEL  |BPWM0 Clock Source Selection
+     * |        |          |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[9]     |BPWM1SEL  |BPWM1 Clock Source Selection
+     * |        |          |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[11:10] |SPI3SEL   |SPI3 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[13:12] |SPI4SEL   |SPI4 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * @var CLK_T::CLKSEL3
+     * Offset: 0x1C  Clock Source Select Control Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SC0SEL    |SC0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[3:2]   |SC1SEL    |SC0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SC2SEL    |SC2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[8]     |RTCSEL    |RTC Clock Source Selection
+     * |        |          |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |[17:16] |I2S0SEL   |I2S0 Clock Source Selection
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from PCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |[25:24] |UART2SEL  |UART2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[27:26] |UART3SEL  |UART3 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[29:28] |UART4SEL  |UART4 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[31:30] |UART5SEL  |UART5 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * @var CLK_T::CLKDIV0
+     * Offset: 0x20  Clock Divider Number Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |HCLKDIV   |HCLK Clock Divide Number From HCLK Clock Source
+     * |        |          |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+     * |[7:4]   |USBDIV    |USB Clock Divide Number From PLL Clock
+     * |        |          |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+     * |[11:8]  |UART0DIV  |UART0 Clock Divide Number From UART0 Clock Source
+     * |        |          |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
+     * |[15:12] |UART1DIV  |UART1 Clock Divide Number From UART1 Clock Source
+     * |        |          |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
+     * |[23:16] |EADCDIV   |EADC Clock Divide Number From EADC Clock Source
+     * |        |          |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+     * |[31:24] |SDH0DIV   |SD0 Clock Divide Number From SD0 Clock Source
+     * |        |          |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1).
+     * @var CLK_T::CLKDIV1
+     * Offset: 0x24  Clock Divider Number Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SC0DIV    |SC0 Clock Divide Number From SC0 Clock Source
+     * |        |          |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+     * |[15:8]  |SC1DIV    |SC1 Clock Divide Number From SC1 Clock Source
+     * |        |          |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
+     * |[23:16] |SC2DIV    |SC2 Clock Divide Number From SC2 Clock Source
+     * |        |          |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
+     * @var CLK_T::CLKDIV3
+     * Offset: 0x2C  Clock Divider Number Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |EMACDIV   |Ethernet Clock Divide Number Form HCLK
+     * |        |          |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
+     * |[31:24] |SDH1DIV   |SD1 Clock Divide Number From SD1 Clock Source
+     * |        |          |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1).
+     * @var CLK_T::CLKDIV4
+     * Offset: 0x30  Clock Divider Number Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |UART2DIV  |UART2 Clock Divide Number From UART2 Clock Source
+     * |        |          |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
+     * |[7:4]   |UART3DIV  |UART3 Clock Divide Number From UART3 Clock Source
+     * |        |          |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
+     * |[11:8]  |UART4DIV  |UART4 Clock Divide Number From UART4 Clock Source
+     * |        |          |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
+     * |[15:12] |UART5DIV  |UART5 Clock Divide Number From UART5 Clock Source
+     * |        |          |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
+     * @var CLK_T::PCLKDIV
+     * Offset: 0x34  APB Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |APB0DIV   |APB0 Clock Divider
+     * |        |          |APB0 clock can be divided from HCLK
+     * |        |          |000: PCLK0 = HCLK.
+     * |        |          |001: PCLK0 = 1/2 HCLK.
+     * |        |          |010: PCLK0 = 1/4 HCLK.
+     * |        |          |011: PCLK0 = 1/8 HCLK.
+     * |        |          |100: PCLK0 = 1/16 HCLK.
+     * |        |          |Others: Reserved.
+     * |[6:4]   |APB1DIV   |APB1 Clock Divider
+     * |        |          |APB1 clock can be divided from HCLK
+     * |        |          |000: PCLK1 = HCLK.
+     * |        |          |001: PCLK1 = 1/2 HCLK.
+     * |        |          |010: PCLK1 = 1/4 HCLK.
+     * |        |          |011: PCLK1 = 1/8 HCLK.
+     * |        |          |100: PCLK1 = 1/16 HCLK.
+     * |        |          |Others: Reserved.
+     * @var CLK_T::PLLCTL
+     * Offset: 0x40  PLL Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |FBDIV     |PLL Feedback Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13:9]  |INDIV     |PLL Input Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[15:14] |OUTDIV    |PLL Output Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |PD        |Power-down Mode (Write Protect)
+     * |        |          |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+     * |        |          |0 = PLL is in normal mode.
+     * |        |          |1 = PLL is in Power-down mode (default).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17]    |BP        |PLL Bypass Control (Write Protect)
+     * |        |          |0 = PLL is in normal mode (default).
+     * |        |          |1 = PLL clock output is same as PLL input clock FIN.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |OE        |PLL OE (FOUT Enable) Pin Control (Write Protect)
+     * |        |          |0 = PLL FOUT Enabled.
+     * |        |          |1 = PLL FOUT is fixed low.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[19]    |PLLSRC    |PLL Source Clock Selection (Write Protect)
+     * |        |          |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
+     * |        |          |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |STBSEL    |PLL Stable Counter Selection (Write Protect)
+     * |        |          |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
+     * |        |          |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[28]    |BANDSEL   |PLL Stable Counter Selection (Write Protect)
+     * |        |          |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ)
+     * |        |          |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ)
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::STATUS
+     * Offset: 0x50  Clock Status Monitor Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTSTB    |HXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
+     * |[1]     |LXTSTB    |LXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
+     * |[2]     |PLLSTB    |Internal PLL Clock Source Stable Flag (Read Only)
+     * |        |          |0 = Internal PLL clock is not stable or disabled.
+     * |        |          |1 = Internal PLL clock is stable and enabled.
+     * |[3]     |LIRCSTB   |LIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
+     * |        |          |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
+     * |[4]     |HIRCSTB   |HIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+     * |        |          |Note: This bit is read only.
+     * |[7]     |CLKSFAIL  |Clock Switching Fail Flag (Read Only)
+     * |        |          |This bit is updated when software switches system clock source
+     * |        |          |If switch target clock is stable, this bit will be set to 0
+     * |        |          |If switch target clock is not stable, this bit will be set to 1.
+     * |        |          |0 = Clock switching success.
+     * |        |          |1 = Clock switching failure.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * @var CLK_T::CLKOCTL
+     * Offset: 0x60  Clock Output Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |FREQSEL   |Clock Output Frequency Selection
+     * |        |          |The formula of output frequency is
+     * |        |          |Fout = Fin/2(N+1).
+     * |        |          |Fin is the input clock frequency.
+     * |        |          |Fout is the frequency of divider output clock.
+     * |        |          |N is the 4-bit value of FREQSEL[3:0].
+     * |[4]     |CLKOEN    |Clock Output Enable Bit
+     * |        |          |0 = Clock Output function Disabled.
+     * |        |          |1 = Clock Output function Enabled.
+     * |[5]     |DIV1EN    |Clock Output Divide One Enable Bit
+     * |        |          |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+     * |        |          |1 = Clock Output will output clock with source frequency.
+     * |[6]     |CLK1HZEN  |Clock Output 1Hz Enable Bit
+     * |        |          |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
+     * |        |          |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
+     * @var CLK_T::CLKDCTL
+     * Offset: 0x70  Clock Fail Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4]     |HXTFDEN   |HXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
+     * |[5]     |HXTFIEN   |HXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
+     * |[12]    |LXTFDEN   |LXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
+     * |[13]    |LXTFIEN   |LXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
+     * |[16]    |HXTFQDEN  |HXT Clock Frequency Range Detector Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled.
+     * |[17]    |HXTFQIEN  |HXT Clock Frequency Range Detector Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
+     * @var CLK_T::CLKDSTS
+     * Offset: 0x74  Clock Fail Detector Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTFIF    |HXT Clock Fail Interrupt Flag
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * |[1]     |LXTFIF    |LXT Clock Fail Interrupt Flag
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * |[8]     |HXTFQIF   |HXT Clock Frequency Range Detector Interrupt Flag
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * @var CLK_T::CDUPB
+     * Offset: 0x78  Clock Frequency Range Detector Upper Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |UPERBD    |HXT Clock Frequency Range Detector Upper Boundary Value
+     * |        |          |The bits define the maximum value of frequency range detector window.
+     * |        |          |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+     * @var CLK_T::CDLOWB
+     * Offset: 0x7C  Clock Frequency Range Detector Lower Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |LOWERBD   |HXT Clock Frequency Range Detector Lower Boundary Value
+     * |        |          |The bits define the minimum value of frequency range detector window.
+     * |        |          |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+     * @var CLK_T::PMUCTL
+     * Offset: 0x90  Power Manager Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |PDMSEL    |Power-down Mode Selection (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
+     * |        |          |000 = Power-down mode is selected. (PD)
+     * |        |          |001 = Low leakage Power-down mode is selected (LLPD).
+     * |        |          |010 =Fast wake-up Power-down mode is selected (FWPD).
+     * |        |          |011 = Reserved.
+     * |        |          |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention).
+     * |        |          |101 = Standby Power-down mode 1 is selected (SPD1).
+     * |        |          |110 = Deep Power-down mode is selected (DPD).
+     * |        |          |111 = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |WKTMREN   |Wake-up Timer Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = Wake-up timer disable at DPD/SPD mode.
+     * |        |          |1 = Wake-up timer enabled at DPD/SPD mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:9]  |WKTMRIS   |Wake-up Timer Time-out Interval Select (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
+     * |        |          |000 = Time-out interval is 128 OSC10K clocks (12.8 ms).
+     * |        |          |001 = Time-out interval is 256 OSC10K clocks (25.6 ms).
+     * |        |          |010 = Time-out interval is 512 OSC10K clocks (51.2 ms).
+     * |        |          |011 = Time-out interval is 1024 OSC10K clocks (102.4ms).
+     * |        |          |100 = Time-out interval is 4096 OSC10K clocks (409.6ms).
+     * |        |          |101 = Time-out interval is 8192 OSC10K clocks (819.2ms).
+     * |        |          |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms).
+     * |        |          |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17:16] |WKPINEN   |Wake-up Pin Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |00 = Wake-up pin disable at Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge enabled at Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge enabled at Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge enabled at Deep Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |ACMPSPWK  |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = ACMP wake-up disable at Standby Power-down mode.
+     * |        |          |1 = ACMP wake-up enabled at Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |RTCWKEN   |RTC Wake-up Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode.
+     * |        |          |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::PMUSTS
+     * Offset: 0x94  Power Manager Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINWK     |Pin Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0)
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[1]     |TMRWK     |Timer Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[2]     |RTCWK     |RTC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[8]     |GPAWK     |GPA Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[9]     |GPBWK     |GPB Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[10]    |GPCWK     |GPC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[11]    |GPDWK     |GPD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[12]    |LVRWK     |LVR Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[13]    |BODWK     |BOD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[14]    |ACMPWK    |ACMP Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[31]    |CLRWK     |Clear Wake-up Flag
+     * |        |          |0 = No clear.
+     * |        |          |1= Clear all wake-up flag.
+     * @var CLK_T::SWKDBCTL
+     * Offset: 0x9C  Standby Power-down Wake-up De-bounce Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
+     * |        |          |0000 = Sample wake-up input once per 1 clocks.
+     * |        |          |0001 = Sample wake-up input once per 2 clocks.
+     * |        |          |0010 = Sample wake-up input once per 4 clocks.
+     * |        |          |0011 = Sample wake-up input once per 8 clocks.
+     * |        |          |0100 = Sample wake-up input once per 16 clocks.
+     * |        |          |0101 = Sample wake-up input once per 32 clocks.
+     * |        |          |0110 = Sample wake-up input once per 64 clocks.
+     * |        |          |0111 = Sample wake-up input once per 128 clocks.
+     * |        |          |1000 = Sample wake-up input once per 256 clocks.
+     * |        |          |1001 = Sample wake-up input once per 2*256 clocks.
+     * |        |          |1010 = Sample wake-up input once per 4*256 clocks.
+     * |        |          |1011 = Sample wake-up input once per 8*256 clocks.
+     * |        |          |1100 = Sample wake-up input once per 16*256 clocks.
+     * |        |          |1101 = Sample wake-up input once per 32*256 clocks.
+     * |        |          |1110 = Sample wake-up input once per 64*256 clocks.
+     * |        |          |1111 = Sample wake-up input once per 128*256 clocks.
+     * |        |          |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+     * @var CLK_T::PASWKCTL
+     * Offset: 0xA0  GPA Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPA group pin wake-up function disabled.
+     * |        |          |1 = GPA group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPA group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPA group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPA Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPA.0 wake-up function enabled.
+     * |        |          |0001 = GPA.1 wake-up function enabled.
+     * |        |          |0010 = GPA.2 wake-up function enabled.
+     * |        |          |0011 = GPA.3 wake-up function enabled.
+     * |        |          |0100 = GPA.4 wake-up function enabled.
+     * |        |          |0101 = GPA.5 wake-up function enabled.
+     * |        |          |0110 = GPA.6 wake-up function enabled.
+     * |        |          |0111 = GPA.7 wake-up function enabled.
+     * |        |          |1000 = GPA.8 wake-up function enabled.
+     * |        |          |1001 = GPA.9 wake-up function enabled.
+     * |        |          |1010 = GPA.10 wake-up function enabled.
+     * |        |          |1011 = GPA.11 wake-up function enabled.
+     * |        |          |1100 = GPA.12 wake-up function enabled.
+     * |        |          |1101 = GPA.13 wake-up function enabled.
+     * |        |          |1110 = GPA.14 wake-up function enabled.
+     * |        |          |1111 = GPA.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPA Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PBSWKCTL
+     * Offset: 0xA4  GPB Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPB group pin wake-up function disabled.
+     * |        |          |1 = GPB group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPB group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPB group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPB Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPB.0 wake-up function enabled.
+     * |        |          |0001 = GPB.1 wake-up function enabled.
+     * |        |          |0010 = GPB.2 wake-up function enabled.
+     * |        |          |0011 = GPB.3 wake-up function enabled.
+     * |        |          |0100 = GPB.4 wake-up function enabled.
+     * |        |          |0101 = GPB.5 wake-up function enabled.
+     * |        |          |0110 = GPB.6 wake-up function enabled.
+     * |        |          |0111 = GPB.7 wake-up function enabled.
+     * |        |          |1000 = GPB.8 wake-up function enabled.
+     * |        |          |1001 = GPB.9 wake-up function enabled.
+     * |        |          |1010 = GPB.10 wake-up function enabled.
+     * |        |          |1011 = GPB.11 wake-up function enabled.
+     * |        |          |1100 = GPB.12 wake-up function enabled.
+     * |        |          |1101 = GPB.13 wake-up function enabled.
+     * |        |          |1110 = GPB.14 wake-up function enabled.
+     * |        |          |1111 = GPB.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPB Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PCSWKCTL
+     * Offset: 0xA8  GPC Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPC group pin wake-up function disabled.
+     * |        |          |1 = GPC group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPC group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPC group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPC Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPC.0 wake-up function enabled.
+     * |        |          |0001 = GPC.1 wake-up function enabled.
+     * |        |          |0010 = GPC.2 wake-up function enabled.
+     * |        |          |0011 = GPC.3 wake-up function enabled.
+     * |        |          |0100 = GPC.4 wake-up function enabled.
+     * |        |          |0101 = GPC.5 wake-up function enabled.
+     * |        |          |0110 = GPC.6 wake-up function enabled.
+     * |        |          |0111 = GPC.7 wake-up function enabled.
+     * |        |          |1000 = GPC.8 wake-up function enabled.
+     * |        |          |1001 = GPC.9 wake-up function enabled.
+     * |        |          |1010 = GPC.10 wake-up function enabled.
+     * |        |          |1011 = GPC.11 wake-up function enabled.
+     * |        |          |1100 = GPC.12 wake-up function enabled.
+     * |        |          |1101 = GPC.13 wake-up function enabled.
+     * |        |          |1110 = GPC.14 wake-up function enabled.
+     * |        |          |1111 = GPC.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPC Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PDSWKCTL
+     * Offset: 0xAC  GPD Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPD group pin wake-up function disabled.
+     * |        |          |1 = GPD group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPD group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPD group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPD Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPD.0 wake-up function enabled.
+     * |        |          |0001 = GPD.1 wake-up function enabled.
+     * |        |          |0010 = GPD.2 wake-up function enabled.
+     * |        |          |0011 = GPD.3 wake-up function enabled.
+     * |        |          |0100 = GPD.4 wake-up function enabled.
+     * |        |          |0101 = GPD.5 wake-up function enabled.
+     * |        |          |0110 = GPD.6 wake-up function enabled.
+     * |        |          |0111 = GPD.7 wake-up function enabled.
+     * |        |          |1000 = GPD.8 wake-up function enabled.
+     * |        |          |1001 = GPD.9 wake-up function enabled.
+     * |        |          |1010 = GPD.10 wake-up function enabled.
+     * |        |          |1011 = GPD.11 wake-up function enabled.
+     * |        |          |1100 = GPD.12 wake-up function enabled.
+     * |        |          |1101 = GPD.13 wake-up function enabled.
+     * |        |          |1110 = GPD.14 wake-up function enabled.
+     * |        |          |1111 = GPD.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPD Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::IOPDCTL
+     * Offset: 0xB0  GPIO Standby Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IOHR      |GPIO Hold Release
+     * |        |          |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status
+     * |        |          |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
+     * |        |          |This bit is auto cleared by hardware.
+     */
+    __IO uint32_t PWRCTL;                /*!< [0x0000] System Power-down Control Register                               */
+    __IO uint32_t AHBCLK;                /*!< [0x0004] AHB Devices Clock Enable Control Register                        */
+    __IO uint32_t APBCLK0;               /*!< [0x0008] APB Devices Clock Enable Control Register 0                      */
+    __IO uint32_t APBCLK1;               /*!< [0x000c] APB Devices Clock Enable Control Register 1                      */
+    __IO uint32_t CLKSEL0;               /*!< [0x0010] Clock Source Select Control Register 0                           */
+    __IO uint32_t CLKSEL1;               /*!< [0x0014] Clock Source Select Control Register 1                           */
+    __IO uint32_t CLKSEL2;               /*!< [0x0018] Clock Source Select Control Register 2                           */
+    __IO uint32_t CLKSEL3;               /*!< [0x001c] Clock Source Select Control Register 3                           */
+    __IO uint32_t CLKDIV0;               /*!< [0x0020] Clock Divider Number Register 0                                  */
+    __IO uint32_t CLKDIV1;               /*!< [0x0024] Clock Divider Number Register 1                                  */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[1];
+    /** @endcond */
+    __IO uint32_t CLKDIV3;               /*!< [0x002c] Clock Divider Number Register 3                                  */
+    __IO uint32_t CLKDIV4;               /*!< [0x0030] Clock Divider Number Register 4                                  */
+    __IO uint32_t PCLKDIV;               /*!< [0x0034] APB Clock Divider Register                                       */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE1[2];
+    /** @endcond */
+    __IO uint32_t PLLCTL;                /*!< [0x0040] PLL Control Register                                             */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE2[3];
+    /** @endcond */
+    __I  uint32_t STATUS;                /*!< [0x0050] Clock Status Monitor Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE3[3];
+    /** @endcond */
+    __IO uint32_t CLKOCTL;               /*!< [0x0060] Clock Output Control Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE4[3];
+    /** @endcond */
+    __IO uint32_t CLKDCTL;               /*!< [0x0070] Clock Fail Detector Control Register                             */
+    __IO uint32_t CLKDSTS;               /*!< [0x0074] Clock Fail Detector Status Register                              */
+    __IO uint32_t CDUPB;                 /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register           */
+    __IO uint32_t CDLOWB;                /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register           */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE5[4];
+    /** @endcond */
+    __IO uint32_t PMUCTL;                /*!< [0x0090] Power Manager Control Register                                   */
+    __IO uint32_t PMUSTS;                /*!< [0x0094] Power Manager Status Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE6[1];
+    /** @endcond */
+    __IO uint32_t SWKDBCTL;              /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register            */
+    __IO uint32_t PASWKCTL;              /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PBSWKCTL;              /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PCSWKCTL;              /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PDSWKCTL;              /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t IOPDCTL;               /*!< [0x00b0] GPIO Standby Power-down Control Register                         */
+
+} CLK_T;
+
+/**
+    @addtogroup CLK_CONST CLK Bit Field Definition
+    Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos             (0)                                               /*!< CLK_T::PWRCTL: HXTEN Position          */
+#define CLK_PWRCTL_HXTEN_Msk             (0x1ul << CLK_PWRCTL_HXTEN_Pos)                   /*!< CLK_T::PWRCTL: HXTEN Mask              */
+
+#define CLK_PWRCTL_LXTEN_Pos             (1)                                               /*!< CLK_T::PWRCTL: LXTEN Position          */
+#define CLK_PWRCTL_LXTEN_Msk             (0x1ul << CLK_PWRCTL_LXTEN_Pos)                   /*!< CLK_T::PWRCTL: LXTEN Mask              */
+
+#define CLK_PWRCTL_HIRCEN_Pos            (2)                                               /*!< CLK_T::PWRCTL: HIRCEN Position         */
+#define CLK_PWRCTL_HIRCEN_Msk            (0x1ul << CLK_PWRCTL_HIRCEN_Pos)                  /*!< CLK_T::PWRCTL: HIRCEN Mask             */
+
+#define CLK_PWRCTL_LIRCEN_Pos            (3)                                               /*!< CLK_T::PWRCTL: LIRCEN Position         */
+#define CLK_PWRCTL_LIRCEN_Msk            (0x1ul << CLK_PWRCTL_LIRCEN_Pos)                  /*!< CLK_T::PWRCTL: LIRCEN Mask             */
+
+#define CLK_PWRCTL_PDWKDLY_Pos           (4)                                               /*!< CLK_T::PWRCTL: PDWKDLY Position        */
+#define CLK_PWRCTL_PDWKDLY_Msk           (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)                 /*!< CLK_T::PWRCTL: PDWKDLY Mask            */
+
+#define CLK_PWRCTL_PDWKIEN_Pos           (5)                                               /*!< CLK_T::PWRCTL: PDWKIEN Position        */
+#define CLK_PWRCTL_PDWKIEN_Msk           (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)                 /*!< CLK_T::PWRCTL: PDWKIEN Mask            */
+
+#define CLK_PWRCTL_PDWKIF_Pos            (6)                                               /*!< CLK_T::PWRCTL: PDWKIF Position         */
+#define CLK_PWRCTL_PDWKIF_Msk            (0x1ul << CLK_PWRCTL_PDWKIF_Pos)                  /*!< CLK_T::PWRCTL: PDWKIF Mask             */
+
+#define CLK_PWRCTL_PDEN_Pos              (7)                                               /*!< CLK_T::PWRCTL: PDEN Position           */
+#define CLK_PWRCTL_PDEN_Msk              (0x1ul << CLK_PWRCTL_PDEN_Pos)                    /*!< CLK_T::PWRCTL: PDEN Mask               */
+
+#define CLK_PWRCTL_HXTGAIN_Pos           (10)                                              /*!< CLK_T::PWRCTL: HXTGAIN Position        */
+#define CLK_PWRCTL_HXTGAIN_Msk           (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)                 /*!< CLK_T::PWRCTL: HXTGAIN Mask            */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos         (12)                                              /*!< CLK_T::PWRCTL: HXTSELTYP Position      */
+#define CLK_PWRCTL_HXTSELTYP_Msk         (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)               /*!< CLK_T::PWRCTL: HXTSELTYP Mask          */
+
+#define CLK_PWRCTL_HXTTBEN_Pos           (13)                                              /*!< CLK_T::PWRCTL: HXTTBEN Position        */
+#define CLK_PWRCTL_HXTTBEN_Msk           (0x1ul << CLK_PWRCTL_HXTTBEN_Pos)                 /*!< CLK_T::PWRCTL: HXTTBEN Mask            */
+
+#define CLK_PWRCTL_HIRCSTBS_Pos          (16)                                              /*!< CLK_T::PWRCTL: HIRCSTBS Position       */
+#define CLK_PWRCTL_HIRCSTBS_Msk          (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos)                /*!< CLK_T::PWRCTL: HIRCSTBS Mask           */
+
+#define CLK_AHBCLK_PDMACKEN_Pos          (1)                                               /*!< CLK_T::AHBCLK: PDMACKEN Position       */
+#define CLK_AHBCLK_PDMACKEN_Msk          (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)                /*!< CLK_T::AHBCLK: PDMACKEN Mask           */
+
+#define CLK_AHBCLK_ISPCKEN_Pos           (2)                                               /*!< CLK_T::AHBCLK: ISPCKEN Position        */
+#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)                 /*!< CLK_T::AHBCLK: ISPCKEN Mask            */
+
+#define CLK_AHBCLK_EBICKEN_Pos           (3)                                               /*!< CLK_T::AHBCLK: EBICKEN Position        */
+#define CLK_AHBCLK_EBICKEN_Msk           (0x1ul << CLK_AHBCLK_EBICKEN_Pos)                 /*!< CLK_T::AHBCLK: EBICKEN Mask            */
+
+#define CLK_AHBCLK_EMACCKEN_Pos          (5)                                               /*!< CLK_T::AHBCLK: EMACCKEN Position       */
+#define CLK_AHBCLK_EMACCKEN_Msk          (0x1ul << CLK_AHBCLK_EMACCKEN_Pos)                /*!< CLK_T::AHBCLK: EMACCKEN Mask           */
+
+#define CLK_AHBCLK_SDH0CKEN_Pos          (6)                                               /*!< CLK_T::AHBCLK: SDH0CKEN Position       */
+#define CLK_AHBCLK_SDH0CKEN_Msk          (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos)                /*!< CLK_T::AHBCLK: SDH0CKEN Mask           */
+
+#define CLK_AHBCLK_CRCCKEN_Pos           (7)                                               /*!< CLK_T::AHBCLK: CRCCKEN Position        */
+#define CLK_AHBCLK_CRCCKEN_Msk           (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)                 /*!< CLK_T::AHBCLK: CRCCKEN Mask            */
+
+#define CLK_AHBCLK_HSUSBDCKEN_Pos        (10)                                              /*!< CLK_T::AHBCLK: HSUSBDCKEN Position     */
+#define CLK_AHBCLK_HSUSBDCKEN_Msk        (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos)              /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask         */
+
+#define CLK_AHBCLK_CRPTCKEN_Pos          (12)                                              /*!< CLK_T::AHBCLK: CRPTCKEN Position       */
+#define CLK_AHBCLK_CRPTCKEN_Msk          (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)                /*!< CLK_T::AHBCLK: CRPTCKEN Mask           */
+
+#define CLK_AHBCLK_SPIMCKEN_Pos          (14)                                              /*!< CLK_T::AHBCLK: SPIMCKEN Position       */
+#define CLK_AHBCLK_SPIMCKEN_Msk          (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos)                /*!< CLK_T::AHBCLK: SPIMCKEN Mask           */
+
+#define CLK_AHBCLK_FMCIDLE_Pos           (15)                                              /*!< CLK_T::AHBCLK: FMCIDLE Position        */
+#define CLK_AHBCLK_FMCIDLE_Msk           (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)                 /*!< CLK_T::AHBCLK: FMCIDLE Mask            */
+
+#define CLK_AHBCLK_USBHCKEN_Pos          (16)                                              /*!< CLK_T::AHBCLK: USBHCKEN Position       */
+#define CLK_AHBCLK_USBHCKEN_Msk          (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)                /*!< CLK_T::AHBCLK: USBHCKEN Mask           */
+
+#define CLK_AHBCLK_SDH1CKEN_Pos          (17)                                              /*!< CLK_T::AHBCLK: SDH1CKEN Position       */
+#define CLK_AHBCLK_SDH1CKEN_Msk          (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos)                /*!< CLK_T::AHBCLK: SDH1CKEN Mask           */
+
+#define CLK_APBCLK0_WDTCKEN_Pos          (0)                                               /*!< CLK_T::APBCLK0: WDTCKEN Position       */
+#define CLK_APBCLK0_WDTCKEN_Msk          (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)                /*!< CLK_T::APBCLK0: WDTCKEN Mask           */
+
+#define CLK_APBCLK0_RTCCKEN_Pos          (1)                                               /*!< CLK_T::APBCLK0: RTCCKEN Position       */
+#define CLK_APBCLK0_RTCCKEN_Msk          (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)                /*!< CLK_T::APBCLK0: RTCCKEN Mask           */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos         (2)                                               /*!< CLK_T::APBCLK0: TMR0CKEN Position      */
+#define CLK_APBCLK0_TMR0CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR0CKEN Mask          */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos         (3)                                               /*!< CLK_T::APBCLK0: TMR1CKEN Position      */
+#define CLK_APBCLK0_TMR1CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR1CKEN Mask          */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos         (4)                                               /*!< CLK_T::APBCLK0: TMR2CKEN Position      */
+#define CLK_APBCLK0_TMR2CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR2CKEN Mask          */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos         (5)                                               /*!< CLK_T::APBCLK0: TMR3CKEN Position      */
+#define CLK_APBCLK0_TMR3CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR3CKEN Mask          */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos         (6)                                               /*!< CLK_T::APBCLK0: CLKOCKEN Position      */
+#define CLK_APBCLK0_CLKOCKEN_Msk         (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)               /*!< CLK_T::APBCLK0: CLKOCKEN Mask          */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos       (7)                                               /*!< CLK_T::APBCLK0: ACMP01CKEN Position    */
+#define CLK_APBCLK0_ACMP01CKEN_Msk       (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)             /*!< CLK_T::APBCLK0: ACMP01CKEN Mask        */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos         (8)                                               /*!< CLK_T::APBCLK0: I2C0CKEN Position      */
+#define CLK_APBCLK0_I2C0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C0CKEN Mask          */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos         (9)                                               /*!< CLK_T::APBCLK0: I2C1CKEN Position      */
+#define CLK_APBCLK0_I2C1CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C1CKEN Mask          */
+
+#define CLK_APBCLK0_I2C2CKEN_Pos         (10)                                              /*!< CLK_T::APBCLK0: I2C2CKEN Position      */
+#define CLK_APBCLK0_I2C2CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C2CKEN Mask          */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos         (12)                                              /*!< CLK_T::APBCLK0: SPI0CKEN Position      */
+#define CLK_APBCLK0_SPI0CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI0CKEN Mask          */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos         (13)                                              /*!< CLK_T::APBCLK0: SPI1CKEN Position      */
+#define CLK_APBCLK0_SPI1CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI1CKEN Mask          */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos         (14)                                              /*!< CLK_T::APBCLK0: SPI2CKEN Position      */
+#define CLK_APBCLK0_SPI2CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI2CKEN Mask          */
+
+#define CLK_APBCLK0_SPI3CKEN_Pos         (15)                                              /*!< CLK_T::APBCLK0: SPI3CKEN Position      */
+#define CLK_APBCLK0_SPI3CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI3CKEN Mask          */
+
+#define CLK_APBCLK0_UART0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK0: UART0CKEN Position     */
+#define CLK_APBCLK0_UART0CKEN_Msk        (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)              /*!< CLK_T::APBCLK0: UART0CKEN Mask         */
+
+#define CLK_APBCLK0_UART1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK0: UART1CKEN Position     */
+#define CLK_APBCLK0_UART1CKEN_Msk        (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)              /*!< CLK_T::APBCLK0: UART1CKEN Mask         */
+
+#define CLK_APBCLK0_UART2CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK0: UART2CKEN Position     */
+#define CLK_APBCLK0_UART2CKEN_Msk        (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)              /*!< CLK_T::APBCLK0: UART2CKEN Mask         */
+
+#define CLK_APBCLK0_UART3CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK0: UART3CKEN Position     */
+#define CLK_APBCLK0_UART3CKEN_Msk        (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)              /*!< CLK_T::APBCLK0: UART3CKEN Mask         */
+
+#define CLK_APBCLK0_UART4CKEN_Pos        (20)                                              /*!< CLK_T::APBCLK0: UART4CKEN Position     */
+#define CLK_APBCLK0_UART4CKEN_Msk        (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)              /*!< CLK_T::APBCLK0: UART4CKEN Mask         */
+
+#define CLK_APBCLK0_UART5CKEN_Pos        (21)                                              /*!< CLK_T::APBCLK0: UART5CKEN Position     */
+#define CLK_APBCLK0_UART5CKEN_Msk        (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)              /*!< CLK_T::APBCLK0: UART5CKEN Mask         */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos         (24)                                              /*!< CLK_T::APBCLK0: CAN0CKEN Position      */
+#define CLK_APBCLK0_CAN0CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN0CKEN Mask          */
+
+#define CLK_APBCLK0_CAN1CKEN_Pos         (25)                                              /*!< CLK_T::APBCLK0: CAN1CKEN Position      */
+#define CLK_APBCLK0_CAN1CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN1CKEN Mask          */
+
+#define CLK_APBCLK0_OTGCKEN_Pos          (26)                                              /*!< CLK_T::APBCLK0: OTGCKEN Position       */
+#define CLK_APBCLK0_OTGCKEN_Msk          (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)                /*!< CLK_T::APBCLK0: OTGCKEN Mask           */
+
+#define CLK_APBCLK0_USBDCKEN_Pos         (27)                                              /*!< CLK_T::APBCLK0: USBDCKEN Position      */
+#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)               /*!< CLK_T::APBCLK0: USBDCKEN Mask          */
+
+#define CLK_APBCLK0_EADCCKEN_Pos         (28)                                              /*!< CLK_T::APBCLK0: EADCCKEN Position      */
+#define CLK_APBCLK0_EADCCKEN_Msk         (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)               /*!< CLK_T::APBCLK0: EADCCKEN Mask          */
+
+#define CLK_APBCLK0_I2S0CKEN_Pos         (29)                                              /*!< CLK_T::APBCLK0: I2S0CKEN Position      */
+#define CLK_APBCLK0_I2S0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2S0CKEN Mask          */
+
+#define CLK_APBCLK0_HSOTGCKEN_Pos        (30)                                              /*!< CLK_T::APBCLK0: HSOTGCKEN Position     */
+#define CLK_APBCLK0_HSOTGCKEN_Msk        (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos)              /*!< CLK_T::APBCLK0: HSOTGCKEN Mask         */
+
+#define CLK_APBCLK1_SC0CKEN_Pos          (0)                                               /*!< CLK_T::APBCLK1: SC0CKEN Position       */
+#define CLK_APBCLK1_SC0CKEN_Msk          (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)                /*!< CLK_T::APBCLK1: SC0CKEN Mask           */
+
+#define CLK_APBCLK1_SC1CKEN_Pos          (1)                                               /*!< CLK_T::APBCLK1: SC1CKEN Position       */
+#define CLK_APBCLK1_SC1CKEN_Msk          (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)                /*!< CLK_T::APBCLK1: SC1CKEN Mask           */
+
+#define CLK_APBCLK1_SC2CKEN_Pos          (2)                                               /*!< CLK_T::APBCLK1: SC2CKEN Position       */
+#define CLK_APBCLK1_SC2CKEN_Msk          (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)                /*!< CLK_T::APBCLK1: SC2CKEN Mask           */
+
+#define CLK_APBCLK1_SPI4CKEN_Pos         (6)                                               /*!< CLK_T::APBCLK1: SPI4CKEN Position      */
+#define CLK_APBCLK1_SPI4CKEN_Msk         (0x1ul << CLK_APBCLK1_SPI4CKEN_Pos)               /*!< CLK_T::APBCLK1: SPI4CKEN Mask          */
+
+#define CLK_APBCLK1_USCI0CKEN_Pos        (8)                                               /*!< CLK_T::APBCLK1: USCI0CKEN Position     */
+#define CLK_APBCLK1_USCI0CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI0CKEN Mask         */
+
+#define CLK_APBCLK1_USCI1CKEN_Pos        (9)                                               /*!< CLK_T::APBCLK1: USCI1CKEN Position     */
+#define CLK_APBCLK1_USCI1CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI1CKEN Mask         */
+
+#define CLK_APBCLK1_DACCKEN_Pos          (12)                                              /*!< CLK_T::APBCLK1: DACCKEN Position       */
+#define CLK_APBCLK1_DACCKEN_Msk          (0x1ul << CLK_APBCLK1_DACCKEN_Pos)                /*!< CLK_T::APBCLK1: DACCKEN Mask           */
+
+#define CLK_APBCLK1_EPWM0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK1: EPWM0CKEN Position     */
+#define CLK_APBCLK1_EPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_EPWM1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK1: EPWM1CKEN Position     */
+#define CLK_APBCLK1_EPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM0CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK1: BPWM0CKEN Position     */
+#define CLK_APBCLK1_BPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM1CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK1: BPWM1CKEN Position     */
+#define CLK_APBCLK1_BPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_QEI0CKEN_Pos         (22)                                              /*!< CLK_T::APBCLK1: QEI0CKEN Position      */
+#define CLK_APBCLK1_QEI0CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI0CKEN Mask          */
+
+#define CLK_APBCLK1_QEI1CKEN_Pos         (23)                                              /*!< CLK_T::APBCLK1: QEI1CKEN Position      */
+#define CLK_APBCLK1_QEI1CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI1CKEN Mask          */
+
+#define CLK_APBCLK1_ECAP0CKEN_Pos        (26)                                              /*!< CLK_T::APBCLK1: ECAP0CKEN Position     */
+#define CLK_APBCLK1_ECAP0CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP0CKEN Mask         */
+
+#define CLK_APBCLK1_ECAP1CKEN_Pos        (27)                                              /*!< CLK_T::APBCLK1: ECAP1CKEN Position     */
+#define CLK_APBCLK1_ECAP1CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP1CKEN Mask         */
+
+#define CLK_APBCLK1_OPACKEN_Pos          (30)                                              /*!< CLK_T::APBCLK1: OPACKEN Position       */
+#define CLK_APBCLK1_OPACKEN_Msk          (0x1ul << CLK_APBCLK1_OPACKEN_Pos)                /*!< CLK_T::APBCLK1: OPACKEN Mask           */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos          (0)                                               /*!< CLK_T::CLKSEL0: HCLKSEL Position       */
+#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)                /*!< CLK_T::CLKSEL0: HCLKSEL Mask           */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos         (3)                                               /*!< CLK_T::CLKSEL0: STCLKSEL Position      */
+#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)               /*!< CLK_T::CLKSEL0: STCLKSEL Mask          */
+
+#if(0)
+#define CLK_CLKSEL0_PCLK0SEL_Pos         (6)                                               /*!< CLK_T::CLKSEL0: PCLK0SEL Position      */
+#define CLK_CLKSEL0_PCLK0SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos)               /*!< CLK_T::CLKSEL0: PCLK0SEL Mask          */
+
+#define CLK_CLKSEL0_PCLK1SEL_Pos         (7)                                               /*!< CLK_T::CLKSEL0: PCLK1SEL Position      */
+#define CLK_CLKSEL0_PCLK1SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos)               /*!< CLK_T::CLKSEL0: PCLK1SEL Mask          */
+#endif
+
+#define CLK_CLKSEL0_SDH0SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL0: SDH0SEL Position       */
+#define CLK_CLKSEL0_SDH0SEL_Msk          (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos)                /*!< CLK_T::CLKSEL0: SDH0SEL Mask           */
+
+#define CLK_CLKSEL0_SDH1SEL_Pos          (22)                                              /*!< CLK_T::CLKSEL0: SDH1SEL Position       */
+#define CLK_CLKSEL0_SDH1SEL_Msk          (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos)                /*!< CLK_T::CLKSEL0: SDH1SEL Mask           */
+
+#define CLK_CLKSEL1_WDTSEL_Pos           (0)                                               /*!< CLK_T::CLKSEL1: WDTSEL Position        */
+#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)                 /*!< CLK_T::CLKSEL1: WDTSEL Mask            */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos          (8)                                               /*!< CLK_T::CLKSEL1: TMR0SEL Position       */
+#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR0SEL Mask           */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL1: TMR1SEL Position       */
+#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR1SEL Mask           */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL1: TMR2SEL Position       */
+#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR2SEL Mask           */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL1: TMR3SEL Position       */
+#define CLK_CLKSEL1_TMR3SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR3SEL Mask           */
+
+#define CLK_CLKSEL1_UART0SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL1: UART0SEL Position      */
+#define CLK_CLKSEL1_UART0SEL_Msk         (0x3ul << CLK_CLKSEL1_UART0SEL_Pos)               /*!< CLK_T::CLKSEL1: UART0SEL Mask          */
+
+#define CLK_CLKSEL1_UART1SEL_Pos         (26)                                              /*!< CLK_T::CLKSEL1: UART1SEL Position      */
+#define CLK_CLKSEL1_UART1SEL_Msk         (0x3ul << CLK_CLKSEL1_UART1SEL_Pos)               /*!< CLK_T::CLKSEL1: UART1SEL Mask          */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos          (28)                                              /*!< CLK_T::CLKSEL1: CLKOSEL Position       */
+#define CLK_CLKSEL1_CLKOSEL_Msk          (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)                /*!< CLK_T::CLKSEL1: CLKOSEL Mask           */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos          (30)                                              /*!< CLK_T::CLKSEL1: WWDTSEL Position       */
+#define CLK_CLKSEL1_WWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)                /*!< CLK_T::CLKSEL1: WWDTSEL Mask           */
+
+#define CLK_CLKSEL2_EPWM0SEL_Pos         (0)                                               /*!< CLK_T::CLKSEL2: EPWM0SEL Position      */
+#define CLK_CLKSEL2_EPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_EPWM1SEL_Pos         (1)                                               /*!< CLK_T::CLKSEL2: EPWM1SEL Position      */
+#define CLK_CLKSEL2_EPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos          (2)                                               /*!< CLK_T::CLKSEL2: SPI0SEL Position       */
+#define CLK_CLKSEL2_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI0SEL Mask           */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos          (4)                                               /*!< CLK_T::CLKSEL2: SPI1SEL Position       */
+#define CLK_CLKSEL2_SPI1SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI1SEL Mask           */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos          (6)                                               /*!< CLK_T::CLKSEL2: SPI2SEL Position       */
+#define CLK_CLKSEL2_SPI2SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI2SEL Mask           */
+
+#define CLK_CLKSEL2_BPWM0SEL_Pos         (8)                                               /*!< CLK_T::CLKSEL2: BPWM0SEL Position      */
+#define CLK_CLKSEL2_BPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_BPWM1SEL_Pos         (9)                                               /*!< CLK_T::CLKSEL2: BPWM1SEL Position      */
+#define CLK_CLKSEL2_BPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_SPI3SEL_Pos          (10)                                              /*!< CLK_T::CLKSEL2: SPI3SEL Position       */
+#define CLK_CLKSEL2_SPI3SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI3SEL Mask           */
+
+#define CLK_CLKSEL2_SPI4SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL2: SPI4SEL Position       */
+#define CLK_CLKSEL2_SPI4SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI4SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI4SEL Mask           */
+
+#define CLK_CLKSEL3_SC0SEL_Pos           (0)                                               /*!< CLK_T::CLKSEL3: SC0SEL Position        */
+#define CLK_CLKSEL3_SC0SEL_Msk           (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC0SEL Mask            */
+
+#define CLK_CLKSEL3_SC1SEL_Pos           (2)                                               /*!< CLK_T::CLKSEL3: SC1SEL Position        */
+#define CLK_CLKSEL3_SC1SEL_Msk           (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC1SEL Mask            */
+
+#define CLK_CLKSEL3_SC2SEL_Pos           (4)                                               /*!< CLK_T::CLKSEL3: SC2SEL Position        */
+#define CLK_CLKSEL3_SC2SEL_Msk           (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC2SEL Mask            */
+
+#define CLK_CLKSEL3_RTCSEL_Pos           (8)                                               /*!< CLK_T::CLKSEL3: RTCSEL Position        */
+#define CLK_CLKSEL3_RTCSEL_Msk           (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)                 /*!< CLK_T::CLKSEL3: RTCSEL Mask            */
+
+#define CLK_CLKSEL3_I2S0SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL3: I2S0SEL Position       */
+#define CLK_CLKSEL3_I2S0SEL_Msk          (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)                /*!< CLK_T::CLKSEL3: I2S0SEL Mask           */
+
+#define CLK_CLKSEL3_UART2SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL3: UART2SEL Position      */
+#define CLK_CLKSEL3_UART2SEL_Msk         (0x3ul << CLK_CLKSEL3_UART2SEL_Pos)               /*!< CLK_T::CLKSEL3: UART2SEL Mask          */
+
+#define CLK_CLKSEL3_UART3SEL_Pos         (26)                                              /*!< CLK_T::CLKSEL3: UART3SEL Position      */
+#define CLK_CLKSEL3_UART3SEL_Msk         (0x3ul << CLK_CLKSEL3_UART3SEL_Pos)               /*!< CLK_T::CLKSEL3: UART3SEL Mask          */
+
+#define CLK_CLKSEL3_UART4SEL_Pos         (28)                                              /*!< CLK_T::CLKSEL3: UART4SEL Position      */
+#define CLK_CLKSEL3_UART4SEL_Msk         (0x3ul << CLK_CLKSEL3_UART4SEL_Pos)               /*!< CLK_T::CLKSEL3: UART4SEL Mask          */
+
+#define CLK_CLKSEL3_UART5SEL_Pos         (30)                                              /*!< CLK_T::CLKSEL3: UART5SEL Position      */
+#define CLK_CLKSEL3_UART5SEL_Msk         (0x3ul << CLK_CLKSEL3_UART5SEL_Pos)               /*!< CLK_T::CLKSEL3: UART5SEL Mask          */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos          (0)                                               /*!< CLK_T::CLKDIV0: HCLKDIV Position       */
+#define CLK_CLKDIV0_HCLKDIV_Msk          (0xful << CLK_CLKDIV0_HCLKDIV_Pos)                /*!< CLK_T::CLKDIV0: HCLKDIV Mask           */
+
+#define CLK_CLKDIV0_USBDIV_Pos           (4)                                               /*!< CLK_T::CLKDIV0: USBDIV Position        */
+#define CLK_CLKDIV0_USBDIV_Msk           (0xful << CLK_CLKDIV0_USBDIV_Pos)                 /*!< CLK_T::CLKDIV0: USBDIV Mask            */
+
+#define CLK_CLKDIV0_UART0DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV0: UART0DIV Position      */
+#define CLK_CLKDIV0_UART0DIV_Msk         (0xful << CLK_CLKDIV0_UART0DIV_Pos)               /*!< CLK_T::CLKDIV0: UART0DIV Mask          */
+
+#define CLK_CLKDIV0_UART1DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV0: UART1DIV Position      */
+#define CLK_CLKDIV0_UART1DIV_Msk         (0xful << CLK_CLKDIV0_UART1DIV_Pos)               /*!< CLK_T::CLKDIV0: UART1DIV Mask          */
+
+#define CLK_CLKDIV0_EADCDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV0: EADCDIV Position       */
+#define CLK_CLKDIV0_EADCDIV_Msk          (0xfful << CLK_CLKDIV0_EADCDIV_Pos)               /*!< CLK_T::CLKDIV0: EADCDIV Mask           */
+
+#define CLK_CLKDIV0_SDH0DIV_Pos          (24)                                              /*!< CLK_T::CLKDIV0: SDH0DIV Position       */
+#define CLK_CLKDIV0_SDH0DIV_Msk          (0xfful << CLK_CLKDIV0_SDH0DIV_Pos)               /*!< CLK_T::CLKDIV0: SDH0DIV Mask           */
+
+#define CLK_CLKDIV1_SC0DIV_Pos           (0)                                               /*!< CLK_T::CLKDIV1: SC0DIV Position        */
+#define CLK_CLKDIV1_SC0DIV_Msk           (0xfful << CLK_CLKDIV1_SC0DIV_Pos)                /*!< CLK_T::CLKDIV1: SC0DIV Mask            */
+
+#define CLK_CLKDIV1_SC1DIV_Pos           (8)                                               /*!< CLK_T::CLKDIV1: SC1DIV Position        */
+#define CLK_CLKDIV1_SC1DIV_Msk           (0xfful << CLK_CLKDIV1_SC1DIV_Pos)                /*!< CLK_T::CLKDIV1: SC1DIV Mask            */
+
+#define CLK_CLKDIV1_SC2DIV_Pos           (16)                                              /*!< CLK_T::CLKDIV1: SC2DIV Position        */
+#define CLK_CLKDIV1_SC2DIV_Msk           (0xfful << CLK_CLKDIV1_SC2DIV_Pos)                /*!< CLK_T::CLKDIV1: SC2DIV Mask            */
+
+#define CLK_CLKDIV3_EMACDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV3: EMACDIV Position       */
+#define CLK_CLKDIV3_EMACDIV_Msk          (0xfful << CLK_CLKDIV3_EMACDIV_Pos)               /*!< CLK_T::CLKDIV3: EMACDIV Mask           */
+
+#define CLK_CLKDIV3_SDH1DIV_Pos          (24)                                              /*!< CLK_T::CLKDIV3: SDH1DIV Position       */
+#define CLK_CLKDIV3_SDH1DIV_Msk          (0xfful << CLK_CLKDIV3_SDH1DIV_Pos)               /*!< CLK_T::CLKDIV3: SDH1DIV Mask           */
+
+#define CLK_CLKDIV4_UART2DIV_Pos         (0)                                               /*!< CLK_T::CLKDIV4: UART2DIV Position      */
+#define CLK_CLKDIV4_UART2DIV_Msk         (0xful << CLK_CLKDIV4_UART2DIV_Pos)               /*!< CLK_T::CLKDIV4: UART2DIV Mask          */
+
+#define CLK_CLKDIV4_UART3DIV_Pos         (4)                                               /*!< CLK_T::CLKDIV4: UART3DIV Position      */
+#define CLK_CLKDIV4_UART3DIV_Msk         (0xful << CLK_CLKDIV4_UART3DIV_Pos)               /*!< CLK_T::CLKDIV4: UART3DIV Mask          */
+
+#define CLK_CLKDIV4_UART4DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV4: UART4DIV Position      */
+#define CLK_CLKDIV4_UART4DIV_Msk         (0xful << CLK_CLKDIV4_UART4DIV_Pos)               /*!< CLK_T::CLKDIV4: UART4DIV Mask          */
+
+#define CLK_CLKDIV4_UART5DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV4: UART5DIV Position      */
+#define CLK_CLKDIV4_UART5DIV_Msk         (0xful << CLK_CLKDIV4_UART5DIV_Pos)               /*!< CLK_T::CLKDIV4: UART5DIV Mask          */
+
+#if(1)
+#define CLK_PCLKDIV_APB0DIV_Pos          (0)                                               /*!< CLK_T::PCLKDIV: APB0DIV Position       */
+#define CLK_PCLKDIV_APB0DIV_Msk          (0x7ul << CLK_PCLKDIV_APB0DIV_Pos)                /*!< CLK_T::PCLKDIV: APB0DIV Mask           */
+
+#define CLK_PCLKDIV_APB1DIV_Pos          (4)                                               /*!< CLK_T::PCLKDIV: APB1DIV Position       */
+#define CLK_PCLKDIV_APB1DIV_Msk          (0x7ul << CLK_PCLKDIV_APB1DIV_Pos)                /*!< CLK_T::PCLKDIV: APB1DIV Mask           */
+#endif
+
+#define CLK_PLLCTL_FBDIV_Pos             (0)                                               /*!< CLK_T::PLLCTL: FBDIV Position          */
+#define CLK_PLLCTL_FBDIV_Msk             (0x1fful << CLK_PLLCTL_FBDIV_Pos)                 /*!< CLK_T::PLLCTL: FBDIV Mask              */
+
+#define CLK_PLLCTL_INDIV_Pos             (9)                                               /*!< CLK_T::PLLCTL: INDIV Position          */
+#define CLK_PLLCTL_INDIV_Msk             (0x1ful << CLK_PLLCTL_INDIV_Pos)                  /*!< CLK_T::PLLCTL: INDIV Mask              */
+
+#define CLK_PLLCTL_OUTDIV_Pos            (14)                                              /*!< CLK_T::PLLCTL: OUTDIV Position         */
+#define CLK_PLLCTL_OUTDIV_Msk            (0x3ul << CLK_PLLCTL_OUTDIV_Pos)                  /*!< CLK_T::PLLCTL: OUTDIV Mask             */
+
+#define CLK_PLLCTL_PD_Pos                (16)                                              /*!< CLK_T::PLLCTL: PD Position             */
+#define CLK_PLLCTL_PD_Msk                (0x1ul << CLK_PLLCTL_PD_Pos)                      /*!< CLK_T::PLLCTL: PD Mask                 */
+
+#define CLK_PLLCTL_BP_Pos                (17)                                              /*!< CLK_T::PLLCTL: BP Position             */
+#define CLK_PLLCTL_BP_Msk                (0x1ul << CLK_PLLCTL_BP_Pos)                      /*!< CLK_T::PLLCTL: BP Mask                 */
+
+#define CLK_PLLCTL_OE_Pos                (18)                                              /*!< CLK_T::PLLCTL: OE Position             */
+#define CLK_PLLCTL_OE_Msk                (0x1ul << CLK_PLLCTL_OE_Pos)                      /*!< CLK_T::PLLCTL: OE Mask                 */
+
+#define CLK_PLLCTL_PLLSRC_Pos            (19)                                              /*!< CLK_T::PLLCTL: PLLSRC Position         */
+#define CLK_PLLCTL_PLLSRC_Msk            (0x1ul << CLK_PLLCTL_PLLSRC_Pos)                  /*!< CLK_T::PLLCTL: PLLSRC Mask             */
+
+#define CLK_PLLCTL_STBSEL_Pos            (23)                                              /*!< CLK_T::PLLCTL: STBSEL Position         */
+#define CLK_PLLCTL_STBSEL_Msk            (0x1ul << CLK_PLLCTL_STBSEL_Pos)                  /*!< CLK_T::PLLCTL: STBSEL Mask             */
+
+#define CLK_PLLCTL_BANDSEL_Pos           (28)                                              /*!< CLK_T::PLLCTL: BANDSEL Position        */
+#define CLK_PLLCTL_BANDSEL_Msk           (0x1ul << CLK_PLLCTL_BANDSEL_Pos)                 /*!< CLK_T::PLLCTL: BANDSEL Mask            */
+
+#define CLK_STATUS_HXTSTB_Pos            (0)                                               /*!< CLK_T::STATUS: HXTSTB Position         */
+#define CLK_STATUS_HXTSTB_Msk            (0x1ul << CLK_STATUS_HXTSTB_Pos)                  /*!< CLK_T::STATUS: HXTSTB Mask             */
+
+#define CLK_STATUS_LXTSTB_Pos            (1)                                               /*!< CLK_T::STATUS: LXTSTB Position         */
+#define CLK_STATUS_LXTSTB_Msk            (0x1ul << CLK_STATUS_LXTSTB_Pos)                  /*!< CLK_T::STATUS: LXTSTB Mask             */
+
+#define CLK_STATUS_PLLSTB_Pos            (2)                                               /*!< CLK_T::STATUS: PLLSTB Position         */
+#define CLK_STATUS_PLLSTB_Msk            (0x1ul << CLK_STATUS_PLLSTB_Pos)                  /*!< CLK_T::STATUS: PLLSTB Mask             */
+
+#define CLK_STATUS_LIRCSTB_Pos           (3)                                               /*!< CLK_T::STATUS: LIRCSTB Position        */
+#define CLK_STATUS_LIRCSTB_Msk           (0x1ul << CLK_STATUS_LIRCSTB_Pos)                 /*!< CLK_T::STATUS: LIRCSTB Mask            */
+
+#define CLK_STATUS_HIRCSTB_Pos           (4)                                               /*!< CLK_T::STATUS: HIRCSTB Position        */
+#define CLK_STATUS_HIRCSTB_Msk           (0x1ul << CLK_STATUS_HIRCSTB_Pos)                 /*!< CLK_T::STATUS: HIRCSTB Mask            */
+
+#define CLK_STATUS_CLKSFAIL_Pos          (7)                                               /*!< CLK_T::STATUS: CLKSFAIL Position       */
+#define CLK_STATUS_CLKSFAIL_Msk          (0x1ul << CLK_STATUS_CLKSFAIL_Pos)                /*!< CLK_T::STATUS: CLKSFAIL Mask           */
+
+#define CLK_CLKOCTL_FREQSEL_Pos          (0)                                               /*!< CLK_T::CLKOCTL: FREQSEL Position       */
+#define CLK_CLKOCTL_FREQSEL_Msk          (0xful << CLK_CLKOCTL_FREQSEL_Pos)                /*!< CLK_T::CLKOCTL: FREQSEL Mask           */
+
+#define CLK_CLKOCTL_CLKOEN_Pos           (4)                                               /*!< CLK_T::CLKOCTL: CLKOEN Position        */
+#define CLK_CLKOCTL_CLKOEN_Msk           (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)                 /*!< CLK_T::CLKOCTL: CLKOEN Mask            */
+
+#define CLK_CLKOCTL_DIV1EN_Pos           (5)                                               /*!< CLK_T::CLKOCTL: DIV1EN Position        */
+#define CLK_CLKOCTL_DIV1EN_Msk           (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)                 /*!< CLK_T::CLKOCTL: DIV1EN Mask            */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos         (6)                                               /*!< CLK_T::CLKOCTL: CLK1HZEN Position      */
+#define CLK_CLKOCTL_CLK1HZEN_Msk         (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)               /*!< CLK_T::CLKOCTL: CLK1HZEN Mask          */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos          (4)                                               /*!< CLK_T::CLKDCTL: HXTFDEN Position       */
+#define CLK_CLKDCTL_HXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFDEN Mask           */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos          (5)                                               /*!< CLK_T::CLKDCTL: HXTFIEN Position       */
+#define CLK_CLKDCTL_HXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFIEN Mask           */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos          (12)                                              /*!< CLK_T::CLKDCTL: LXTFDEN Position       */
+#define CLK_CLKDCTL_LXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFDEN Mask           */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos          (13)                                              /*!< CLK_T::CLKDCTL: LXTFIEN Position       */
+#define CLK_CLKDCTL_LXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFIEN Mask           */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos         (16)                                              /*!< CLK_T::CLKDCTL: HXTFQDEN Position      */
+#define CLK_CLKDCTL_HXTFQDEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQDEN Mask          */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos         (17)                                              /*!< CLK_T::CLKDCTL: HXTFQIEN Position      */
+#define CLK_CLKDCTL_HXTFQIEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQIEN Mask          */
+
+#define CLK_CLKDSTS_HXTFIF_Pos           (0)                                               /*!< CLK_T::CLKDSTS: HXTFIF Position        */
+#define CLK_CLKDSTS_HXTFIF_Msk           (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: HXTFIF Mask            */
+
+#define CLK_CLKDSTS_LXTFIF_Pos           (1)                                               /*!< CLK_T::CLKDSTS: LXTFIF Position        */
+#define CLK_CLKDSTS_LXTFIF_Msk           (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: LXTFIF Mask            */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos          (8)                                               /*!< CLK_T::CLKDSTS: HXTFQIF Position       */
+#define CLK_CLKDSTS_HXTFQIF_Msk          (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)                /*!< CLK_T::CLKDSTS: HXTFQIF Mask           */
+
+#define CLK_CDUPB_UPERBD_Pos             (0)                                               /*!< CLK_T::CDUPB: UPERBD Position          */
+#define CLK_CDUPB_UPERBD_Msk             (0x3fful << CLK_CDUPB_UPERBD_Pos)                 /*!< CLK_T::CDUPB: UPERBD Mask              */
+
+#define CLK_CDLOWB_LOWERBD_Pos           (0)                                               /*!< CLK_T::CDLOWB: LOWERBD Position        */
+#define CLK_CDLOWB_LOWERBD_Msk           (0x3fful << CLK_CDLOWB_LOWERBD_Pos)               /*!< CLK_T::CDLOWB: LOWERBD Mask            */
+
+#define CLK_PMUCTL_PDMSEL_Pos            (0)                                               /*!< CLK_T::PMUCTL: PDMSEL Position         */
+#define CLK_PMUCTL_PDMSEL_Msk            (0x7ul << CLK_PMUCTL_PDMSEL_Pos)                  /*!< CLK_T::PMUCTL: PDMSEL Mask             */
+
+#define CLK_PMUCTL_WKTMREN_Pos           (8)                                               /*!< CLK_T::PMUCTL: WKTMREN Position        */
+#define CLK_PMUCTL_WKTMREN_Msk           (0x1ul << CLK_PMUCTL_WKTMREN_Pos)                 /*!< CLK_T::PMUCTL: WKTMREN Mask            */
+
+#define CLK_PMUCTL_WKTMRIS_Pos           (9)                                               /*!< CLK_T::PMUCTL: WKTMRIS Position        */
+#define CLK_PMUCTL_WKTMRIS_Msk           (0x7ul << CLK_PMUCTL_WKTMRIS_Pos)                 /*!< CLK_T::PMUCTL: WKTMRIS Mask            */
+
+#define CLK_PMUCTL_WKPINEN_Pos           (16)                                              /*!< CLK_T::PMUCTL: WKPINEN Position        */
+#define CLK_PMUCTL_WKPINEN_Msk           (0x3ul << CLK_PMUCTL_WKPINEN_Pos)                 /*!< CLK_T::PMUCTL: WKPINEN Mask            */
+
+#define CLK_PMUCTL_ACMPSPWK_Pos          (18)                                              /*!< CLK_T::PMUCTL: ACMPSPWK Position       */
+#define CLK_PMUCTL_ACMPSPWK_Msk          (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos)                /*!< CLK_T::PMUCTL: ACMPSPWK Mask           */
+
+#define CLK_PMUCTL_RTCWKEN_Pos           (23)                                              /*!< CLK_T::PMUCTL: RTCWKEN Position        */
+#define CLK_PMUCTL_RTCWKEN_Msk           (0x1ul << CLK_PMUCTL_RTCWKEN_Pos)                 /*!< CLK_T::PMUCTL: RTCWKEN Mask            */
+
+#define CLK_PMUSTS_PINWK_Pos             (0)                                               /*!< CLK_T::PMUSTS: PINWK Position          */
+#define CLK_PMUSTS_PINWK_Msk             (0x1ul << CLK_PMUSTS_PINWK_Pos)                   /*!< CLK_T::PMUSTS: PINWK Mask              */
+
+#define CLK_PMUSTS_TMRWK_Pos             (1)                                               /*!< CLK_T::PMUSTS: TMRWK Position          */
+#define CLK_PMUSTS_TMRWK_Msk             (0x1ul << CLK_PMUSTS_TMRWK_Pos)                   /*!< CLK_T::PMUSTS: TMRWK Mask              */
+
+#define CLK_PMUSTS_RTCWK_Pos             (2)                                               /*!< CLK_T::PMUSTS: RTCWK Position          */
+#define CLK_PMUSTS_RTCWK_Msk             (0x1ul << CLK_PMUSTS_RTCWK_Pos)                   /*!< CLK_T::PMUSTS: RTCWK Mask              */
+
+#define CLK_PMUSTS_GPAWK_Pos             (8)                                               /*!< CLK_T::PMUSTS: GPAWK Position          */
+#define CLK_PMUSTS_GPAWK_Msk             (0x1ul << CLK_PMUSTS_GPAWK_Pos)                   /*!< CLK_T::PMUSTS: GPAWK Mask              */
+
+#define CLK_PMUSTS_GPBWK_Pos             (9)                                               /*!< CLK_T::PMUSTS: GPBWK Position          */
+#define CLK_PMUSTS_GPBWK_Msk             (0x1ul << CLK_PMUSTS_GPBWK_Pos)                   /*!< CLK_T::PMUSTS: GPBWK Mask              */
+
+#define CLK_PMUSTS_GPCWK_Pos             (10)                                              /*!< CLK_T::PMUSTS: GPCWK Position          */
+#define CLK_PMUSTS_GPCWK_Msk             (0x1ul << CLK_PMUSTS_GPCWK_Pos)                   /*!< CLK_T::PMUSTS: GPCWK Mask              */
+
+#define CLK_PMUSTS_GPDWK_Pos             (11)                                              /*!< CLK_T::PMUSTS: GPDWK Position          */
+#define CLK_PMUSTS_GPDWK_Msk             (0x1ul << CLK_PMUSTS_GPDWK_Pos)                   /*!< CLK_T::PMUSTS: GPDWK Mask              */
+
+#define CLK_PMUSTS_LVRWK_Pos             (12)                                              /*!< CLK_T::PMUSTS: LVRWK Position          */
+#define CLK_PMUSTS_LVRWK_Msk             (0x1ul << CLK_PMUSTS_LVRWK_Pos)                   /*!< CLK_T::PMUSTS: LVRWK Mask              */
+
+#define CLK_PMUSTS_BODWK_Pos             (13)                                              /*!< CLK_T::PMUSTS: BODWK Position          */
+#define CLK_PMUSTS_BODWK_Msk             (0x1ul << CLK_PMUSTS_BODWK_Pos)                   /*!< CLK_T::PMUSTS: BODWK Mask              */
+
+#define CLK_PMUSTS_ACMPWK_Pos            (14)                                              /*!< CLK_T::PMUSTS: ACMPWK Position         */
+#define CLK_PMUSTS_ACMPWK_Msk            (0x1ul << CLK_PMUSTS_ACMPWK_Pos)                  /*!< CLK_T::PMUSTS: ACMPWK Mask             */
+
+#define CLK_PMUSTS_CLRWK_Pos             (31)                                              /*!< CLK_T::PMUSTS: CLRWK Position          */
+#define CLK_PMUSTS_CLRWK_Msk             (0x1ul << CLK_PMUSTS_CLRWK_Pos)                   /*!< CLK_T::PMUSTS: CLRWK Mask              */
+
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos     (0)                                               /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position  */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk     (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)           /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask      */
+
+#define CLK_PASWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PASWKCTL: WKEN Position         */
+#define CLK_PASWKCTL_WKEN_Msk            (0x1ul << CLK_PASWKCTL_WKEN_Pos)                  /*!< CLK_T::PASWKCTL: WKEN Mask             */
+
+#define CLK_PASWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PASWKCTL: PRWKEN Position       */
+#define CLK_PASWKCTL_PRWKEN_Msk          (0x1ul << CLK_PASWKCTL_PRWKEN_Pos)                /*!< CLK_T::PASWKCTL: PRWKEN Mask           */
+
+#define CLK_PASWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PASWKCTL: PFWKEN Position       */
+#define CLK_PASWKCTL_PFWKEN_Msk          (0x1ul << CLK_PASWKCTL_PFWKEN_Pos)                /*!< CLK_T::PASWKCTL: PFWKEN Mask           */
+
+#define CLK_PASWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PASWKCTL: WKPSEL Position       */
+#define CLK_PASWKCTL_WKPSEL_Msk          (0xful << CLK_PASWKCTL_WKPSEL_Pos)                /*!< CLK_T::PASWKCTL: WKPSEL Mask           */
+
+#define CLK_PASWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PASWKCTL: DBEN Position         */
+#define CLK_PASWKCTL_DBEN_Msk            (0x1ul << CLK_PASWKCTL_DBEN_Pos)                  /*!< CLK_T::PASWKCTL: DBEN Mask             */
+
+#define CLK_PBSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PBSWKCTL: WKEN Position         */
+#define CLK_PBSWKCTL_WKEN_Msk            (0x1ul << CLK_PBSWKCTL_WKEN_Pos)                  /*!< CLK_T::PBSWKCTL: WKEN Mask             */
+
+#define CLK_PBSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PBSWKCTL: PRWKEN Position       */
+#define CLK_PBSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PRWKEN Mask           */
+
+#define CLK_PBSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PBSWKCTL: PFWKEN Position       */
+#define CLK_PBSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PFWKEN Mask           */
+
+#define CLK_PBSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PBSWKCTL: WKPSEL Position       */
+#define CLK_PBSWKCTL_WKPSEL_Msk          (0xful << CLK_PBSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PBSWKCTL: WKPSEL Mask           */
+
+#define CLK_PBSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PBSWKCTL: DBEN Position         */
+#define CLK_PBSWKCTL_DBEN_Msk            (0x1ul << CLK_PBSWKCTL_DBEN_Pos)                  /*!< CLK_T::PBSWKCTL: DBEN Mask             */
+
+#define CLK_PCSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PCSWKCTL: WKEN Position         */
+#define CLK_PCSWKCTL_WKEN_Msk            (0x1ul << CLK_PCSWKCTL_WKEN_Pos)                  /*!< CLK_T::PCSWKCTL: WKEN Mask             */
+
+#define CLK_PCSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PCSWKCTL: PRWKEN Position       */
+#define CLK_PCSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PRWKEN Mask           */
+
+#define CLK_PCSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PCSWKCTL: PFWKEN Position       */
+#define CLK_PCSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PFWKEN Mask           */
+
+#define CLK_PCSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PCSWKCTL: WKPSEL Position       */
+#define CLK_PCSWKCTL_WKPSEL_Msk          (0xful << CLK_PCSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PCSWKCTL: WKPSEL Mask           */
+
+#define CLK_PCSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PCSWKCTL: DBEN Position         */
+#define CLK_PCSWKCTL_DBEN_Msk            (0x1ul << CLK_PCSWKCTL_DBEN_Pos)                  /*!< CLK_T::PCSWKCTL: DBEN Mask             */
+
+#define CLK_PDSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PDSWKCTL: WKEN Position         */
+#define CLK_PDSWKCTL_WKEN_Msk            (0x1ul << CLK_PDSWKCTL_WKEN_Pos)                  /*!< CLK_T::PDSWKCTL: WKEN Mask             */
+
+#define CLK_PDSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PDSWKCTL: PRWKEN Position       */
+#define CLK_PDSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PRWKEN Mask           */
+
+#define CLK_PDSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PDSWKCTL: PFWKEN Position       */
+#define CLK_PDSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PFWKEN Mask           */
+
+#define CLK_PDSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PDSWKCTL: WKPSEL Position       */
+#define CLK_PDSWKCTL_WKPSEL_Msk          (0xful << CLK_PDSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PDSWKCTL: WKPSEL Mask           */
+
+#define CLK_PDSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PDSWKCTL: DBEN Position         */
+#define CLK_PDSWKCTL_DBEN_Msk            (0x1ul << CLK_PDSWKCTL_DBEN_Pos)                  /*!< CLK_T::PDSWKCTL: DBEN Mask             */
+
+#define CLK_IOPDCTL_IOHR_Pos             (0)                                               /*!< CLK_T::IOPDCTL: IOHR Position          */
+#define CLK_IOPDCTL_IOHR_Msk             (0x1ul << CLK_IOPDCTL_IOHR_Pos)                   /*!< CLK_T::IOPDCTL: IOHR Mask              */
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+
+
+/*---------------------- Flash Memory Controller -------------------------*/
+/**
+    @addtogroup FMC Flash Memory Controller(FMC)
+    Memory Mapped Structure for FMC Controller
+@{ */
+
+typedef struct {
+    /**
+     * @var FMC_T::ISPCTL
+     * Offset: 0x00  ISP Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPEN     |ISP Enable Bit (Write Protect)
+     * |        |          |ISP function enable bit. Set this bit to enable ISP function.
+     * |        |          |0 = ISP function Disabled.
+     * |        |          |1 = ISP function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |BS        |Boot Select (Write Protect)
+     * |        |          |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
+     * |        |          |This bit also functions as chip booting status flag, which can be used to check where chip booted from
+     * |        |          |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+     * |        |          |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+     * |        |          |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |SPUEN     |SPROM Update Enable Bit (Write Protect)
+     * |        |          |0 = SPROM cannot be updated.
+     * |        |          |1 = SPROM can be updated.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |APUEN     |APROM Update Enable Bit (Write Protect)
+     * |        |          |0 = APROM cannot be updated when the chip runs in APROM.
+     * |        |          |1 = APROM can be updated when the chip runs in APROM.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |CFGUEN    |CONFIG Update Enable Bit (Write Protect)
+     * |        |          |0 = CONFIG cannot be updated.
+     * |        |          |1 = CONFIG can be updated.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |LDUEN     |LDROM Update Enable Bit (Write Protect)
+     * |        |          |LDROM update enable bit.
+     * |        |          |0 = LDROM cannot be updated.
+     * |        |          |1 = LDROM can be updated.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |This bit needs to be cleared by writing 1 to it.
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+     * |        |          |(5) SPROM is programmed at SPROM secured mode.
+     * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(7) Erase or Program command at brown-out detected
+     * |        |          |(8) Destination address is illegal, such as over an available range.
+     * |        |          |(9) Invalid ISP commands
+     * |        |          |(10) Vector address is mapping to SPROM region
+     * |        |          |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+     * |        |          |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1
+     * |        |          |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+     * |        |          |(17) Read any content of boot loader with ICE connection
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |BL        |Boot Loader Booting (Write Protect)
+     * |        |          |This bit is initiated with the inversed value of MBS (CONFIG0[5])
+     * |        |          |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
+     * |        |          |This bit is used to check chip boot from Boot Loader or not
+     * |        |          |User should keep original value of this bit when updating FMC_ISPCTL register.
+     * |        |          |0 = Booting from APROM or LDROM.
+     * |        |          |1 = Booting from Boot Loader.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::ISPADDR
+     * Offset: 0x04  ISP Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPADDR   |ISP Address
+     * |        |          |The NuMicro M480 series is equipped with embedded flash
+     * |        |          |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
+     * |        |          |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+     * |        |          |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
+     * |        |          |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
+     * |        |          |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
+     * @var FMC_T::ISPDAT
+     * Offset: 0x08  ISP Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT    |ISP Data
+     * |        |          |Write data to this register before ISP program operation.
+     * |        |          |Read data from this register after ISP read operation.
+     * |        |          |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
+     * |        |          |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment
+     * |        |          |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
+     * |        |          |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
+     * @var FMC_T::ISPCMD
+     * Offset: 0x0C  ISP Command Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |CMD       |ISP Command
+     * |        |          |ISP command table is shown below:
+     * |        |          |0x00= FLASH Read.
+     * |        |          |0x04= Read Unique ID.
+     * |        |          |0x08= Read Flash All-One Result.
+     * |        |          |0x0B= Read Company ID.
+     * |        |          |0x0C= Read Device ID.
+     * |        |          |0x0D= Read Checksum.
+     * |        |          |0x21= FLASH 32-bit Program.
+     * |        |          |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
+     * |        |          |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
+     * |        |          |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1..
+     * |        |          |0x27= FLASH Multi-Word Program.
+     * |        |          |0x28= Run Flash All-One Verification.
+     * |        |          |0x2D= Run Checksum Calculation.
+     * |        |          |0x2E= Vector Remap.
+     * |        |          |0x40= FLASH 64-bit Read.
+     * |        |          |0x61= FLASH 64-bit Program.
+     * |        |          |The other commands are invalid.
+     * @var FMC_T::ISPTRG
+     * Offset: 0x10  ISP Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPGO     |ISP Start Trigger (Write Protect)
+     * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+     * |        |          |0 = ISP operation is finished.
+     * |        |          |1 = ISP is progressed.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::DFBA
+     * Offset: 0x14  Data Flash Base Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DFBA      |Data Flash Base Address
+     * |        |          |This register indicates Data Flash start address. It is a read only register.
+     * |        |          |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
+     * |        |          |This register is valid when DFEN (CONFIG0[0]) =0 .
+     * @var FMC_T::ISPSTS
+     * Offset: 0x40  ISP Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPBUSY   |ISP Busy Flag (Read Only)
+     * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+     * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+     * |        |          |0 = ISP operation is finished.
+     * |        |          |1 = ISP is progressed.
+     * |[2:1]   |CBS       |Boot Selection of CONFIG (Read Only)
+     * |        |          |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+     * |        |          |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+     * |        |          |00 = LDROM with IAP mode.
+     * |        |          |01 = LDROM without IAP mode.
+     * |        |          |10 = APROM with IAP mode.
+     * |        |          |11 = APROM without IAP mode.
+     * |[3]     |MBS       |Boot From Boot Loader Selection Flag (Read Only)
+     * |        |          |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+     * |        |          |0 = Booting from Boot Loader.
+     * |        |          |1 = Booting from LDROM/APROM.(.see CBS bit setting)
+     * |[4]     |FCYCDIS   |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
+     * |        |          |This bit is set if flash access cycle auto-tuning function is disabled
+     * |        |          |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
+     * |        |          |0 = Flash access cycle auto-tuning is enabled.
+     * |        |          |1 = Flash access cycle auto-tuning is disabled.
+     * |[5]     |PGFF      |Flash Program with Fast Verification Flag (Read Only)
+     * |        |          |This bit is set if data is mismatched at ISP programming verification
+     * |        |          |This bit is clear by performing ISP flash erase or ISP read CID operation
+     * |        |          |0 = Flash Program is success.
+     * |        |          |1 = Flash Program is fail. Program data is different with data in the flash memory
+     * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+     * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+     * |        |          |(5) SPROM is programmed at SPROM secured mode.
+     * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(7) Erase or Program command at brown-out detected
+     * |        |          |(8) Destination address is illegal, such as over an available range.
+     * |        |          |(9) Invalid ISP commands
+     * |        |          |(10) Vector address is mapping to SPROM region.
+     * |        |          |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+     * |        |          |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+     * |        |          |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+     * |        |          |(17) Read any content of boot loader with ICE connection
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |ALLONE    |Flash All-one Verification Flag
+     * |        |          |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
+     * |        |          |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete.
+     * |        |          |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
+     * |[23:9]  |VECMAP    |Vector Page Mapping Address (Read Only)
+     * |        |          |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
+     * |[31]    |SCODE     |Security Code Active Flag
+     * |        |          |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation.
+     * |        |          |0 = Secured code is inactive.
+     * |        |          |1 = Secured code is active.
+     * @var FMC_T::CYCCTL
+     * Offset: 0x4C  Flash Access Cycle Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CYCLE     |Flash Access Cycle Control (Write Protect)
+     * |        |          |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1)
+     * |        |          |0000 = CPU access with zero wait cycle ; flash access cycle is 1;.
+     * |        |          |The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
+     * |        |          |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
+     * |        |          |The HCLK working frequency range range is<27MHz
+     * |        |          |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
+     * |        |          | The optimized HCLK working frequency range is 27~54 MHz
+     * |        |          |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
+     * |        |          |The optimized HCLK working frequency range is 54~81MHz
+     * |        |          |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
+     * |        |          | The optimized HCLK working frequency range is81~108MHz
+     * |        |          |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
+     * |        |          |The optimized HCLK working frequency range is 108~135MHz
+     * |        |          |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
+     * |        |          | The optimized HCLK working frequency range is 135~162MHz
+     * |        |          |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
+     * |        |          | The optimized HCLK working frequency range is 162~192MHz
+     * |        |          |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
+     * |        |          |The optimized HCLK working frequency range is >192MHz
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |FADIS     |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
+     * |        |          |Set this bit to disable flash access cycle auto-tuning function
+     * |        |          |0 = Flash access cycle auto-tuning is enabled.
+     * |        |          |1 = Flash access cycle auto-tuning is disabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::KPKEY0
+     * Offset: 0x50  KPROM KEY0 Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KPKEY0    |KPROM KEY0 Data (Write Only)
+     * |        |          |Write KPKEY0 data to this register before KEY Comparison operation.
+     * @var FMC_T::KPKEY1
+     * Offset: 0x54  KPROM KEY1 Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KPKEY1    |KPROM KEY1 Data (Write Only)
+     * |        |          |Write KPKEY1 data to this register before KEY Comparison operation.
+     * @var FMC_T::KPKEY2
+     * Offset: 0x58  KPROM KEY2 Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KPKEY2    |KPROM KEY2 Data (Write Only)
+     * |        |          |Write KPKEY2 data to this register before KEY Comparison operation.
+     * @var FMC_T::KPKEYTRG
+     * Offset: 0x5C  KPROM KEY Comparison Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |KPKEYGO   |KPROM KEY Comparison Start Trigger (Write Protection)
+     * |        |          |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
+     * |        |          |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
+     * |        |          |0 = KEY comparison operation is finished.
+     * |        |          |1 = KEY comparison is progressed.
+     * |        |          |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |TCEN      |Timeout Counting Enable (Write Protection)
+     * |        |          |0 = Timeout counting is disabled.
+     * |        |          |1 = Timeout counting is enabled if input key is matched after key comparison finish.
+     * |        |          |10 minutes is at least for timeout, and average is about 20 minutes.
+     * |        |          |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::KPKEYSTS
+     * Offset: 0x60  KPROM KEY Comparison Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |KEYBUSY   |KEY Comparison Busy (Read Only)
+     * |        |          |0 = KEY comparison is finished.
+     * |        |          |1 = KEY comparison is busy.
+     * |[1]     |KEYLOCK   |KEY LOCK Flag
+     * |        |          |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
+     * |        |          |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
+     * |        |          |This bit also can be set to 1 while
+     * |        |          |  - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+     * |        |          |  - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
+     * |        |          |  - KEYENROM is programmed a non-0xFF value or
+     * |        |          |  - Timeout event or
+     * |        |          |  - FORBID(FMC_KPKEYSTS[3]) is 1
+     * |        |          |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
+     * |        |          |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
+     * |        |          |SPROM write protect is depended on SPFLAG.
+     * |        |          |CONFIG write protect is depended on CFGFLAG
+     * |[2]     |KEYMATCH  |KEY Match Flag (Read Only)
+     * |        |          |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
+     * |        |          |This bit is also cleared to 0 while
+     * |        |          |  - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+     * |        |          |  - Timeout event or
+     * |        |          |  - KPROM is erased or
+     * |        |          |  - KEYENROM is programmed to a non-0xFF value.
+     * |        |          |  - Chip is in power down mode.
+     * |        |          |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
+     * |        |          |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
+     * |[3]     |FORBID    |KEY Comparison Forbidden Flag (Read Only)
+     * |        |          |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
+     * |        |          |0 = KEY comparison is not forbidden.
+     * |        |          |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
+     * |[4]     |KEYFLAG   |KEY Protection Enabled Flag (Read Only)
+     * |        |          |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset
+     * |        |          |This bit is cleared to 0 by hardware while KPROM is erased
+     * |        |          |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
+     * |        |          |0 = Security Key protection is disabled.
+     * |        |          |1 = Security Key protection is enabled.
+     * |[5]     |CFGFLAG   |CONFIG Write-protection Enabled Flag (Read Only)
+     * |        |          |This bit is set while the KEYENROM [0] is 0 at power-on or reset
+     * |        |          |This bit is cleared to 0 by hardware while KPROM is erased
+     * |        |          |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
+     * |        |          |0 = CONFIG write-protection is disabled.
+     * |        |          |1 = CONFIG write-protection is enabled.
+     * |[6]     |SPFLAG    |SPROM Write-protection Enabled Flag (Read Only)
+     * |        |          |This bit is set while the KEYENROM [1] is 0 at power-on or reset
+     * |        |          |This bit is cleared to 0 by hardware while KPROM is erased
+     * |        |          |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0.
+     * |        |          |0 = SPROM write-protection is disabled.
+     * |        |          |1 = SPROM write-protection is enabled.
+     * @var FMC_T::KPKEYCNT
+     * Offset: 0x64  KPROM KEY-Unmatched Counting Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |KPKECNT   |Error Key Entry Counter at Each Power-on (Read Only)
+     * |        |          |KPKECNT is increased when entry keys is wrong in Security Key protection
+     * |        |          |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
+     * |[13:8]  |KPKEMAX   |Maximum Number for Error Key Entry at Each Power-on (Read Only)
+     * |        |          |KPKEMAX is the maximum error key entry number at each power-on
+     * |        |          |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
+     * |        |          |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
+     * |        |          |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
+     * @var FMC_T::KPCNT
+     * Offset: 0x68  KPROM KEY-Unmatched Power-On Counting Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |KPCNT     |Power-on Counter for Error Key Entry(Read Only)
+     * |        |          |KPCNT is the power-on counting for error key entry in Security Key protection
+     * |        |          |KPCNT is cleared to 0 if key comparison is matched.
+     * |[11:8]  |KPMAX     |Power-on Maximum Number for Error Key Entry (Read Only)
+     * |        |          |KPMAX is the power-on maximum number for error key entry
+     * |        |          |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
+     * |        |          |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
+     * |        |          |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
+     * @var FMC_T::MPDAT0
+     * Offset: 0x80  ISP Data0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT0   |ISP Data 0
+     * |        |          |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+     * @var FMC_T::MPDAT1
+     * Offset: 0x84  ISP Data1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT1   |ISP Data 1
+     * |        |          |This register is the second 32-bit data for 64-bit/multi-word programming.
+     * @var FMC_T::MPDAT2
+     * Offset: 0x88  ISP Data2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT2   |ISP Data 2
+     * |        |          |This register is the third 32-bit data for multi-word programming.
+     * @var FMC_T::MPDAT3
+     * Offset: 0x8C  ISP Data3 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT3   |ISP Data 3
+     * |        |          |This register is the fourth 32-bit data for multi-word programming.
+     * @var FMC_T::MPSTS
+     * Offset: 0xC0  ISP Multi-Program Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MPBUSY    |ISP Multi-word Program Busy Flag (Read Only)
+     * |        |          |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+     * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+     * |        |          |0 = ISP Multi-Word program operation is finished.
+     * |        |          |1 = ISP Multi-Word program operation is progressed.
+     * |[1]     |PPGO      |ISP Multi-program Status (Read Only)
+     * |        |          |0 = ISP multi-word program operation is not active.
+     * |        |          |1 = ISP multi-word program operation is in progress.
+     * |[2]     |ISPFF     |ISP Fail Flag (Read Only)
+     * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+     * |        |          |(5) SPROM is programmed at SPROM secured mode.
+     * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(7) Erase or Program command at brown-out detected
+     * |        |          |(8) Destination address is illegal, such as over an available range.
+     * |        |          |(9) Invalid ISP commands
+     * |        |          |(10) Vector address is mapping to SPROM region.
+     * |[4]     |D0        |ISP DATA 0 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+     * |[5]     |D1        |ISP DATA 1 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+     * |[6]     |D2        |ISP DATA 2 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+     * |[7]     |D3        |ISP DATA 3 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+     * @var FMC_T::MPADDR
+     * Offset: 0xC4  ISP Multi-Program Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |MPADDR    |ISP Multi-word Program Address
+     * |        |          |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+     * |        |          |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+     */
+    __IO uint32_t ISPCTL;                /*!< [0x0000] ISP Control Register                                             */
+    __IO uint32_t ISPADDR;               /*!< [0x0004] ISP Address Register                                             */
+    __IO uint32_t ISPDAT;                /*!< [0x0008] ISP Data Register                                                */
+    __IO uint32_t ISPCMD;                /*!< [0x000c] ISP Command Register                                             */
+    __IO uint32_t ISPTRG;                /*!< [0x0010] ISP Trigger Control Register                                     */
+    __I  uint32_t DFBA;                  /*!< [0x0014] Data Flash Base Address                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[10];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t ISPSTS;                /*!< [0x0040] ISP Status Register                                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CYCCTL;                /*!< [0x004c] Flash Access Cycle Control Register                              */
+    __O  uint32_t KPKEY0;                /*!< [0x0050] KPROM KEY0 Data Register                                         */
+    __O  uint32_t KPKEY1;                /*!< [0x0054] KPROM KEY1 Data Register                                         */
+    __O  uint32_t KPKEY2;                /*!< [0x0058] KPROM KEY2 Data Register                                         */
+    __IO uint32_t KPKEYTRG;              /*!< [0x005c] KPROM KEY Comparison Trigger Control Register                    */
+    __IO uint32_t KPKEYSTS;              /*!< [0x0060] KPROM KEY Comparison Status Register                             */
+    __I  uint32_t KPKEYCNT;              /*!< [0x0064] KPROM KEY-Unmatched Counting Register                            */
+    __I  uint32_t KPCNT;                 /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register                   */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t MPDAT0;                /*!< [0x0080] ISP Data0 Register                                               */
+    __IO uint32_t MPDAT1;                /*!< [0x0084] ISP Data1 Register                                               */
+    __IO uint32_t MPDAT2;                /*!< [0x0088] ISP Data2 Register                                               */
+    __IO uint32_t MPDAT3;                /*!< [0x008c] ISP Data3 Register                                               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[12];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t MPSTS;                 /*!< [0x00c0] ISP Multi-Program Status Register                                */
+    __I  uint32_t MPADDR;                /*!< [0x00c4] ISP Multi-Program Address Register                               */
+
+} FMC_T;
+
+/**
+    @addtogroup FMC_CONST FMC Bit Field Definition
+    Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCTL_ISPEN_Pos             (0)                                               /*!< FMC_T::ISPCTL: ISPEN Position          */
+#define FMC_ISPCTL_ISPEN_Msk             (0x1ul << FMC_ISPCTL_ISPEN_Pos)                   /*!< FMC_T::ISPCTL: ISPEN Mask              */
+
+#define FMC_ISPCTL_BS_Pos                (1)                                               /*!< FMC_T::ISPCTL: BS Position             */
+#define FMC_ISPCTL_BS_Msk                (0x1ul << FMC_ISPCTL_BS_Pos)                      /*!< FMC_T::ISPCTL: BS Mask                 */
+
+#define FMC_ISPCTL_SPUEN_Pos             (2)                                               /*!< FMC_T::ISPCTL: SPUEN Position          */
+#define FMC_ISPCTL_SPUEN_Msk             (0x1ul << FMC_ISPCTL_SPUEN_Pos)                   /*!< FMC_T::ISPCTL: SPUEN Mask              */
+
+#define FMC_ISPCTL_APUEN_Pos             (3)                                               /*!< FMC_T::ISPCTL: APUEN Position          */
+#define FMC_ISPCTL_APUEN_Msk             (0x1ul << FMC_ISPCTL_APUEN_Pos)                   /*!< FMC_T::ISPCTL: APUEN Mask              */
+
+#define FMC_ISPCTL_CFGUEN_Pos            (4)                                               /*!< FMC_T::ISPCTL: CFGUEN Position         */
+#define FMC_ISPCTL_CFGUEN_Msk            (0x1ul << FMC_ISPCTL_CFGUEN_Pos)                  /*!< FMC_T::ISPCTL: CFGUEN Mask             */
+
+#define FMC_ISPCTL_LDUEN_Pos             (5)                                               /*!< FMC_T::ISPCTL: LDUEN Position          */
+#define FMC_ISPCTL_LDUEN_Msk             (0x1ul << FMC_ISPCTL_LDUEN_Pos)                   /*!< FMC_T::ISPCTL: LDUEN Mask              */
+
+#define FMC_ISPCTL_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPCTL: ISPFF Position          */
+#define FMC_ISPCTL_ISPFF_Msk             (0x1ul << FMC_ISPCTL_ISPFF_Pos)                   /*!< FMC_T::ISPCTL: ISPFF Mask              */
+
+#define FMC_ISPCTL_BL_Pos                (16)                                              /*!< FMC_T::ISPCTL: BL Position             */
+#define FMC_ISPCTL_BL_Msk                (0x1ul << FMC_ISPCTL_BL_Pos)                      /*!< FMC_T::ISPCTL: BL Mask                 */
+
+#define FMC_ISPADDR_ISPADDR_Pos          (0)                                               /*!< FMC_T::ISPADDR: ISPADDR Position       */
+#define FMC_ISPADDR_ISPADDR_Msk          (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)         /*!< FMC_T::ISPADDR: ISPADDR Mask           */
+
+#define FMC_ISPDAT_ISPDAT_Pos            (0)                                               /*!< FMC_T::ISPDAT: ISPDAT Position         */
+#define FMC_ISPDAT_ISPDAT_Msk            (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)           /*!< FMC_T::ISPDAT: ISPDAT Mask             */
+
+#define FMC_ISPCMD_CMD_Pos               (0)                                               /*!< FMC_T::ISPCMD: CMD Position            */
+#define FMC_ISPCMD_CMD_Msk               (0x7ful << FMC_ISPCMD_CMD_Pos)                    /*!< FMC_T::ISPCMD: CMD Mask                */
+
+#define FMC_ISPTRG_ISPGO_Pos             (0)                                               /*!< FMC_T::ISPTRG: ISPGO Position          */
+#define FMC_ISPTRG_ISPGO_Msk             (0x1ul << FMC_ISPTRG_ISPGO_Pos)                   /*!< FMC_T::ISPTRG: ISPGO Mask              */
+
+#define FMC_DFBA_DFBA_Pos                (0)                                               /*!< FMC_T::DFBA: DFBA Position             */
+#define FMC_DFBA_DFBA_Msk                (0xfffffffful << FMC_DFBA_DFBA_Pos)               /*!< FMC_T::DFBA: DFBA Mask                 */
+
+#define FMC_ISPSTS_ISPBUSY_Pos           (0)                                               /*!< FMC_T::ISPSTS: ISPBUSY Position        */
+#define FMC_ISPSTS_ISPBUSY_Msk           (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)                 /*!< FMC_T::ISPSTS: ISPBUSY Mask            */
+
+#define FMC_ISPSTS_CBS_Pos               (1)                                               /*!< FMC_T::ISPSTS: CBS Position            */
+#define FMC_ISPSTS_CBS_Msk               (0x3ul << FMC_ISPSTS_CBS_Pos)                     /*!< FMC_T::ISPSTS: CBS Mask                */
+
+#define FMC_ISPSTS_MBS_Pos               (3)                                               /*!< FMC_T::ISPSTS: MBS Position            */
+#define FMC_ISPSTS_MBS_Msk               (0x1ul << FMC_ISPSTS_MBS_Pos)                     /*!< FMC_T::ISPSTS: MBS Mask                */
+
+#define FMC_ISPSTS_FCYCDIS_Pos           (4)                                               /*!< FMC_T::ISPSTS: FCYCDIS Position        */
+#define FMC_ISPSTS_FCYCDIS_Msk           (0x1ul << FMC_ISPSTS_FCYCDIS_Pos)                 /*!< FMC_T::ISPSTS: FCYCDIS Mask            */
+
+#define FMC_ISPSTS_PGFF_Pos              (5)                                               /*!< FMC_T::ISPSTS: PGFF Position           */
+#define FMC_ISPSTS_PGFF_Msk              (0x1ul << FMC_ISPSTS_PGFF_Pos)                    /*!< FMC_T::ISPSTS: PGFF Mask               */
+
+#define FMC_ISPSTS_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPSTS: ISPFF Position          */
+#define FMC_ISPSTS_ISPFF_Msk             (0x1ul << FMC_ISPSTS_ISPFF_Pos)                   /*!< FMC_T::ISPSTS: ISPFF Mask              */
+
+#define FMC_ISPSTS_ALLONE_Pos            (7)                                               /*!< FMC_T::ISPSTS: ALLONE Position         */
+#define FMC_ISPSTS_ALLONE_Msk            (0x1ul << FMC_ISPSTS_ALLONE_Pos)                  /*!< FMC_T::ISPSTS: ALLONE Mask             */
+
+#define FMC_ISPSTS_VECMAP_Pos            (9)                                               /*!< FMC_T::ISPSTS: VECMAP Position         */
+#define FMC_ISPSTS_VECMAP_Msk            (0x7ffful << FMC_ISPSTS_VECMAP_Pos)               /*!< FMC_T::ISPSTS: VECMAP Mask             */
+
+#define FMC_ISPSTS_SCODE_Pos             (31)                                              /*!< FMC_T::ISPSTS: SCODE Position          */
+#define FMC_ISPSTS_SCODE_Msk             (0x1ul << FMC_ISPSTS_SCODE_Pos)                   /*!< FMC_T::ISPSTS: SCODE Mask              */
+
+#define FMC_CYCCTL_CYCLE_Pos             (0)                                               /*!< FMC_T::CYCCTL: CYCLE Position          */
+#define FMC_CYCCTL_CYCLE_Msk             (0xful << FMC_CYCCTL_CYCLE_Pos)                   /*!< FMC_T::CYCCTL: CYCLE Mask              */
+
+#define FMC_CYCCTL_FADIS_Pos             (8)                                               /*!< FMC_T::CYCCTL: FADIS Position          */
+#define FMC_CYCCTL_FADIS_Msk             (0x1ul << FMC_CYCCTL_FADIS_Pos)                   /*!< FMC_T::CYCCTL: FADIS Mask              */
+
+#define FMC_KPKEY0_KPKEY0_Pos            (0)                                               /*!< FMC_T::KPKEY0: KPKEY0 Position         */
+#define FMC_KPKEY0_KPKEY0_Msk            (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos)           /*!< FMC_T::KPKEY0: KPKEY0 Mask             */
+
+#define FMC_KPKEY1_KPKEY1_Pos            (0)                                               /*!< FMC_T::KPKEY1: KPKEY1 Position         */
+#define FMC_KPKEY1_KPKEY1_Msk            (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos)           /*!< FMC_T::KPKEY1: KPKEY1 Mask             */
+
+#define FMC_KPKEY2_KPKEY2_Pos            (0)                                               /*!< FMC_T::KPKEY2: KPKEY2 Position         */
+#define FMC_KPKEY2_KPKEY2_Msk            (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos)           /*!< FMC_T::KPKEY2: KPKEY2 Mask             */
+
+#define FMC_KPKEYTRG_KPKEYGO_Pos         (0)                                               /*!< FMC_T::KPKEYTRG: KPKEYGO Position      */
+#define FMC_KPKEYTRG_KPKEYGO_Msk         (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos)               /*!< FMC_T::KPKEYTRG: KPKEYGO Mask          */
+
+#define FMC_KPKEYTRG_TCEN_Pos            (1)                                               /*!< FMC_T::KPKEYTRG: TCEN Position         */
+#define FMC_KPKEYTRG_TCEN_Msk            (0x1ul << FMC_KPKEYTRG_TCEN_Pos)                  /*!< FMC_T::KPKEYTRG: TCEN Mask             */
+
+#define FMC_KPKEYSTS_KEYBUSY_Pos         (0)                                               /*!< FMC_T::KPKEYSTS: KEYBUSY Position      */
+#define FMC_KPKEYSTS_KEYBUSY_Msk         (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos)               /*!< FMC_T::KPKEYSTS: KEYBUSY Mask          */
+
+#define FMC_KPKEYSTS_KEYLOCK_Pos         (1)                                               /*!< FMC_T::KPKEYSTS: KEYLOCK Position      */
+#define FMC_KPKEYSTS_KEYLOCK_Msk         (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos)               /*!< FMC_T::KPKEYSTS: KEYLOCK Mask          */
+
+#define FMC_KPKEYSTS_KEYMATCH_Pos        (2)                                               /*!< FMC_T::KPKEYSTS: KEYMATCH Position     */
+#define FMC_KPKEYSTS_KEYMATCH_Msk        (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos)              /*!< FMC_T::KPKEYSTS: KEYMATCH Mask         */
+
+#define FMC_KPKEYSTS_FORBID_Pos          (3)                                               /*!< FMC_T::KPKEYSTS: FORBID Position       */
+#define FMC_KPKEYSTS_FORBID_Msk          (0x1ul << FMC_KPKEYSTS_FORBID_Pos)                /*!< FMC_T::KPKEYSTS: FORBID Mask           */
+
+#define FMC_KPKEYSTS_KEYFLAG_Pos         (4)                                               /*!< FMC_T::KPKEYSTS: KEYFLAG Position      */
+#define FMC_KPKEYSTS_KEYFLAG_Msk         (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos)               /*!< FMC_T::KPKEYSTS: KEYFLAG Mask          */
+
+#define FMC_KPKEYSTS_CFGFLAG_Pos         (5)                                               /*!< FMC_T::KPKEYSTS: CFGFLAG Position      */
+#define FMC_KPKEYSTS_CFGFLAG_Msk         (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos)               /*!< FMC_T::KPKEYSTS: CFGFLAG Mask          */
+
+#define FMC_KPKEYSTS_SPFLAG_Pos          (6)                                               /*!< FMC_T::KPKEYSTS: SPFLAG Position       */
+#define FMC_KPKEYSTS_SPFLAG_Msk          (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos)                /*!< FMC_T::KPKEYSTS: SPFLAG Mask           */
+
+#define FMC_KPKEYCNT_KPKECNT_Pos         (0)                                               /*!< FMC_T::KPKEYCNT: KPKECNT Position      */
+#define FMC_KPKEYCNT_KPKECNT_Msk         (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos)              /*!< FMC_T::KPKEYCNT: KPKECNT Mask          */
+
+#define FMC_KPKEYCNT_KPKEMAX_Pos         (8)                                               /*!< FMC_T::KPKEYCNT: KPKEMAX Position      */
+#define FMC_KPKEYCNT_KPKEMAX_Msk         (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos)              /*!< FMC_T::KPKEYCNT: KPKEMAX Mask          */
+
+#define FMC_KPCNT_KPCNT_Pos              (0)                                               /*!< FMC_T::KPCNT: KPCNT Position           */
+#define FMC_KPCNT_KPCNT_Msk              (0xful << FMC_KPCNT_KPCNT_Pos)                    /*!< FMC_T::KPCNT: KPCNT Mask               */
+
+#define FMC_KPCNT_KPMAX_Pos              (8)                                               /*!< FMC_T::KPCNT: KPMAX Position           */
+#define FMC_KPCNT_KPMAX_Msk              (0xful << FMC_KPCNT_KPMAX_Pos)                    /*!< FMC_T::KPCNT: KPMAX Mask               */
+
+#define FMC_MPDAT0_ISPDAT0_Pos           (0)                                               /*!< FMC_T::MPDAT0: ISPDAT0 Position        */
+#define FMC_MPDAT0_ISPDAT0_Msk           (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)          /*!< FMC_T::MPDAT0: ISPDAT0 Mask            */
+
+#define FMC_MPDAT1_ISPDAT1_Pos           (0)                                               /*!< FMC_T::MPDAT1: ISPDAT1 Position        */
+#define FMC_MPDAT1_ISPDAT1_Msk           (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)          /*!< FMC_T::MPDAT1: ISPDAT1 Mask            */
+
+#define FMC_MPDAT2_ISPDAT2_Pos           (0)                                               /*!< FMC_T::MPDAT2: ISPDAT2 Position        */
+#define FMC_MPDAT2_ISPDAT2_Msk           (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)          /*!< FMC_T::MPDAT2: ISPDAT2 Mask            */
+
+#define FMC_MPDAT3_ISPDAT3_Pos           (0)                                               /*!< FMC_T::MPDAT3: ISPDAT3 Position        */
+#define FMC_MPDAT3_ISPDAT3_Msk           (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)          /*!< FMC_T::MPDAT3: ISPDAT3 Mask            */
+
+#define FMC_MPSTS_MPBUSY_Pos             (0)                                               /*!< FMC_T::MPSTS: MPBUSY Position          */
+#define FMC_MPSTS_MPBUSY_Msk             (0x1ul << FMC_MPSTS_MPBUSY_Pos)                   /*!< FMC_T::MPSTS: MPBUSY Mask              */
+
+#define FMC_MPSTS_PPGO_Pos               (1)                                               /*!< FMC_T::MPSTS: PPGO Position            */
+#define FMC_MPSTS_PPGO_Msk               (0x1ul << FMC_MPSTS_PPGO_Pos)                     /*!< FMC_T::MPSTS: PPGO Mask                */
+
+#define FMC_MPSTS_ISPFF_Pos              (2)                                               /*!< FMC_T::MPSTS: ISPFF Position           */
+#define FMC_MPSTS_ISPFF_Msk              (0x1ul << FMC_MPSTS_ISPFF_Pos)                    /*!< FMC_T::MPSTS: ISPFF Mask               */
+
+#define FMC_MPSTS_D0_Pos                 (4)                                               /*!< FMC_T::MPSTS: D0 Position              */
+#define FMC_MPSTS_D0_Msk                 (0x1ul << FMC_MPSTS_D0_Pos)                       /*!< FMC_T::MPSTS: D0 Mask                  */
+
+#define FMC_MPSTS_D1_Pos                 (5)                                               /*!< FMC_T::MPSTS: D1 Position              */
+#define FMC_MPSTS_D1_Msk                 (0x1ul << FMC_MPSTS_D1_Pos)                       /*!< FMC_T::MPSTS: D1 Mask                  */
+
+#define FMC_MPSTS_D2_Pos                 (6)                                               /*!< FMC_T::MPSTS: D2 Position              */
+#define FMC_MPSTS_D2_Msk                 (0x1ul << FMC_MPSTS_D2_Pos)                       /*!< FMC_T::MPSTS: D2 Mask                  */
+
+#define FMC_MPSTS_D3_Pos                 (7)                                               /*!< FMC_T::MPSTS: D3 Position              */
+#define FMC_MPSTS_D3_Msk                 (0x1ul << FMC_MPSTS_D3_Pos)                       /*!< FMC_T::MPSTS: D3 Mask                  */
+
+#define FMC_MPADDR_MPADDR_Pos            (0)                                               /*!< FMC_T::MPADDR: MPADDR Position         */
+#define FMC_MPADDR_MPADDR_Msk            (0xfffffffful << FMC_MPADDR_MPADDR_Pos)           /*!< FMC_T::MPADDR: MPADDR Mask             */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+
+
+
+
+/*---------------------- General Purpose Input/Output Controller -------------------------*/
+/**
+    @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+    Memory Mapped Structure for GPIO Controller
+@{ */
+
+
+typedef struct {
+
+    /**
+     * @var GPIO_T::MODE
+     * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0  Port A-H I/O Mode Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|MODEn    |Port A-H I/O Pin[n] Mode Control
+     * |        |          |Determine each I/O mode of Px.n pins.
+     * |        |          |00 = Px.n is in Input mode.
+     * |        |          |01 = Px.n is in Push-pull Output mode.
+     * |        |          |10 = Px.n is in Open-drain Output mode.
+     * |        |          |11 = Px.n is in Quasi-bidirectional mode.
+     * |        |          |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+     * |        |          |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+     * |        |          |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
+     * |        |          |Note2:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::DINOFF
+     * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4  Port A-H Digital Input Path Disable Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n+16]  |DINOFFn   |Port A-H Pin[n] Digital Input Path Disable Control
+     * |        |          |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+     * |        |          |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+     * |        |          |0 = Px.n digital input path Enabled.
+     * |        |          |1 = Px.n digital input path Disabled (digital input tied to low).
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::DOUT
+     * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8  Port A-H Data Output Value
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DOUTn     |Port A-H Pin[n] Output Value
+     * |        |          |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+     * |        |          |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+     * |        |          |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::DATMSK
+     * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC  Port A-H Data Output Write Mask
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DATMSKn    |Port A-H Pin[n] Data Output Write Mask
+     * |        |          |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+     * |        |          |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+     * |        |          |If the write signal is masked, writing data to the protect bit is ignored.
+     * |        |          |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+     * |        |          |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+     * |        |          |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit.
+     * |        |          |Note2:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::PIN
+     * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0  Port A-H Pin Value
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |PINn      |Port A-H Pin[n] Pin Value
+     * |        |          |Each bit of the register reflects the actual status of the respective Px.n pin.
+     * |        |          |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::DBEN
+     * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4  Port A-H De-Bounce Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DBENn     |Port A-H Pin[n] Input Signal De-Bounce Enable Bit
+     * |        |          |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+     * |        |          |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
+     * |        |          |0 = Px.n de-bounce function Disabled.
+     * |        |          |1 = Px.n de-bounce function Enabled.
+     * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+     * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::INTTYPE
+     * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8  Port A-H Interrupt Trigger Type Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |TYPEn     |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
+     * |        |          |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+     * |        |          |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+     * |        |          |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+     * |        |          |0 = Edge trigger interrupt.
+     * |        |          |1 = Level trigger interrupt.
+     * |        |          |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+     * |        |          |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+     * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+     * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::INTEN
+     * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC  Port A-H Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |FLIENn    |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+     * |        |          |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+     * |        |          |Set bit to 1 also enable the pin wake-up function.
+     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+     * |        |          |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+     * |        |          |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+     * |        |          |0 = Px.n level low or high to low interrupt Disabled.
+     * |        |          |1 = Px.n level low or high to low interrupt Enabled.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * |[n+16]  |RHIENn    |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
+     * |        |          |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
+     * |        |          |Set bit to 1 also enable the pin wake-up function.
+     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
+     * |        |          |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
+     * |        |          |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
+     * |        |          |0 = Px.n level high or low to high interrupt Disabled.
+     * |        |          |1 = Px.n level high or low to high interrupt Enabled.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::INTSRC
+     * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0  Port A-H Interrupt Source Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |INTSRCn   |Port A-H Pin[n] Interrupt Source Flag
+     * |        |          |Write Operation :
+     * |        |          |0 = No action.
+     * |        |          |1 = Clear the corresponding pending interrupt.
+     * |        |          |Read Operation :
+     * |        |          |0 = No interrupt at Px.n.
+     * |        |          |1 = Px.n generates an interrupt.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::SMTEN
+     * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4  Port A-H Input Schmitt Trigger Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |SMTENn    |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
+     * |        |          |0 = Px.n input Schmitt trigger function Disabled.
+     * |        |          |1 = Px.n input Schmitt trigger function Enabled.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::SLEWCTL
+     * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8  Port A-H High Slew Rate Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|HSRENn    |Port A-H Pin[n] High Slew Rate Control
+     * |        |          |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
+     * |        |          |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
+     * |        |          |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
+     * |        |          |11 = Reserved.
+     * |        |          |Note:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     * @var GPIO_T::PUSEL
+     * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0  Port A-H Pull-up and Pull-down Selection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|PUSELn    |Port A-H Pin[n] Pull-up and Pull-down Enable Register
+     * |        |          |Determine each I/O Pull-up/pull-down of Px.n pins.
+     * |        |          |00 = Px.n pull-up and pull-up disable.
+     * |        |          |01 = Px.n pull-up enable.
+     * |        |          |10 = Px.n pull-down enable.
+     * |        |          |11 = Px.n pull-up and pull-up disable.
+     * |        |          |Note1:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation
+     * |        |          |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
+     * |        |          |The independent pull-down control register only valid when MODEn set as tri-state mode
+     * |        |          |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
+     * |        |          |Note2:
+     * |        |          |Max. n=15 for port A/B/E/G.
+     * |        |          |Max. n=14 for port C/D.
+     * |        |          |Max. n=11 for port F/H.
+     */
+
+    __IO uint32_t MODE;          /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0  Port A-H I/O Mode Control                       */
+    __IO uint32_t DINOFF;        /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4  Port A-H Digital Input Path Disable Control     */
+    __IO uint32_t DOUT;          /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8  Port A-H Data Output Value                      */
+    __IO uint32_t DATMSK;        /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC  Port A-H Data Output Write Mask                 */
+    __I  uint32_t PIN;           /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0  Port A-H Pin Value                              */
+    __IO uint32_t DBEN;          /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4  Port A-H De-Bounce Enable Control Register      */
+    __IO uint32_t INTTYPE;       /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8  Port A-H Interrupt Trigger Type Control         */
+    __IO uint32_t INTEN;         /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC  Port A-H Interrupt Enable Control Register      */
+    __IO uint32_t INTSRC;        /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0  Port A-H Interrupt Source Flag                  */
+    __IO uint32_t SMTEN;         /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4  Port A-H Input Schmitt Trigger Enable Register  */
+    __IO uint32_t SLEWCTL;       /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8  Port A-H High Slew Rate Control Register        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PUSEL;         /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0  Port A-H Pull-up and Pull-down Enable Register  */
+
+} GPIO_T;
+
+typedef struct {
+
+    /**
+     * @var GPIO_DBCTL_T::DBCTL
+     * Offset: 0x440  Interrupt De-bounce Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DBCLKSEL  |De-Bounce Sampling Cycle Selection
+     * |        |          |0000 = Sample interrupt input once per 1 clocks.
+     * |        |          |0001 = Sample interrupt input once per 2 clocks.
+     * |        |          |0010 = Sample interrupt input once per 4 clocks.
+     * |        |          |0011 = Sample interrupt input once per 8 clocks.
+     * |        |          |0100 = Sample interrupt input once per 16 clocks.
+     * |        |          |0101 = Sample interrupt input once per 32 clocks.
+     * |        |          |0110 = Sample interrupt input once per 64 clocks.
+     * |        |          |0111 = Sample interrupt input once per 128 clocks.
+     * |        |          |1000 = Sample interrupt input once per 256 clocks.
+     * |        |          |1001 = Sample interrupt input once per 2*256 clocks.
+     * |        |          |1010 = Sample interrupt input once per 4*256 clocks.
+     * |        |          |1011 = Sample interrupt input once per 8*256 clocks.
+     * |        |          |1100 = Sample interrupt input once per 16*256 clocks.
+     * |        |          |1101 = Sample interrupt input once per 32*256 clocks.
+     * |        |          |1110 = Sample interrupt input once per 64*256 clocks.
+     * |        |          |1111 = Sample interrupt input once per 128*256 clocks.
+     * |[4]     |DBCLKSRC  |De-Bounce Counter Clock Source Selection
+     * |        |          |0 = De-bounce counter clock source is the HCLK.
+     * |        |          |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+     * |[5]     |ICLKON    |Interrupt Clock On Mode
+     * |        |          |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+     * |        |          |1 = All I/O pins edge detection circuit is always active after reset.
+     * |        |          |Note: It is recommended to disable this bit to save system power if no special application concern.
+     */
+
+    __IO uint32_t DBCTL;         /* Offset: 0x440  Interrupt De-bounce Control Register                              */
+
+} GPIO_DBCTL_T;
+
+/**
+    @addtogroup GPIO_CONST GPIO Bit Field Definition
+    Constant Definitions for GPIO Controller
+@{ */
+
+#define GPIO_MODE_MODE0_Pos              (0)                                               /*!< GPIO_T::MODE: MODE0 Position              */
+#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)                    /*!< GPIO_T::MODE: MODE0 Mask                  */
+
+#define GPIO_MODE_MODE1_Pos              (2)                                               /*!< GPIO_T::MODE: MODE1 Position              */
+#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)                    /*!< GPIO_T::MODE: MODE1 Mask                  */
+
+#define GPIO_MODE_MODE2_Pos              (4)                                               /*!< GPIO_T::MODE: MODE2 Position              */
+#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)                    /*!< GPIO_T::MODE: MODE2 Mask                  */
+
+#define GPIO_MODE_MODE3_Pos              (6)                                               /*!< GPIO_T::MODE: MODE3 Position              */
+#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)                    /*!< GPIO_T::MODE: MODE3 Mask                  */
+
+#define GPIO_MODE_MODE4_Pos              (8)                                               /*!< GPIO_T::MODE: MODE4 Position              */
+#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)                    /*!< GPIO_T::MODE: MODE4 Mask                  */
+
+#define GPIO_MODE_MODE5_Pos              (10)                                              /*!< GPIO_T::MODE: MODE5 Position              */
+#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)                    /*!< GPIO_T::MODE: MODE5 Mask                  */
+
+#define GPIO_MODE_MODE6_Pos              (12)                                              /*!< GPIO_T::MODE: MODE6 Position              */
+#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)                    /*!< GPIO_T::MODE: MODE6 Mask                  */
+
+#define GPIO_MODE_MODE7_Pos              (14)                                              /*!< GPIO_T::MODE: MODE7 Position              */
+#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)                    /*!< GPIO_T::MODE: MODE7 Mask                  */
+
+#define GPIO_MODE_MODE8_Pos              (16)                                              /*!< GPIO_T::MODE: MODE8 Position              */
+#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)                    /*!< GPIO_T::MODE: MODE8 Mask                  */
+
+#define GPIO_MODE_MODE9_Pos              (18)                                              /*!< GPIO_T::MODE: MODE9 Position              */
+#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)                    /*!< GPIO_T::MODE: MODE9 Mask                  */
+
+#define GPIO_MODE_MODE10_Pos             (20)                                              /*!< GPIO_T::MODE: MODE10 Position             */
+#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)                   /*!< GPIO_T::MODE: MODE10 Mask                 */
+
+#define GPIO_MODE_MODE11_Pos             (22)                                              /*!< GPIO_T::MODE: MODE11 Position             */
+#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)                   /*!< GPIO_T::MODE: MODE11 Mask                 */
+
+#define GPIO_MODE_MODE12_Pos             (24)                                              /*!< GPIO_T::MODE: MODE12 Position             */
+#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)                   /*!< GPIO_T::MODE: MODE12 Mask                 */
+
+#define GPIO_MODE_MODE13_Pos             (26)                                              /*!< GPIO_T::MODE: MODE13 Position             */
+#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)                   /*!< GPIO_T::MODE: MODE13 Mask                 */
+
+#define GPIO_MODE_MODE14_Pos             (28)                                              /*!< GPIO_T::MODE: MODE14 Position             */
+#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)                   /*!< GPIO_T::MODE: MODE14 Mask                 */
+
+#define GPIO_MODE_MODE15_Pos             (30)                                              /*!< GPIO_T::MODE: MODE15 Position             */
+#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)                   /*!< GPIO_T::MODE: MODE15 Mask                 */
+
+#define GPIO_DINOFF_DINOFF0_Pos          (16)                                              /*!< GPIO_T::DINOFF: DINOFF0 Position          */
+#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)                /*!< GPIO_T::DINOFF: DINOFF0 Mask              */
+
+#define GPIO_DINOFF_DINOFF1_Pos          (17)                                              /*!< GPIO_T::DINOFF: DINOFF1 Position          */
+#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)                /*!< GPIO_T::DINOFF: DINOFF1 Mask              */
+
+#define GPIO_DINOFF_DINOFF2_Pos          (18)                                              /*!< GPIO_T::DINOFF: DINOFF2 Position          */
+#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)                /*!< GPIO_T::DINOFF: DINOFF2 Mask              */
+
+#define GPIO_DINOFF_DINOFF3_Pos          (19)                                              /*!< GPIO_T::DINOFF: DINOFF3 Position          */
+#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)                /*!< GPIO_T::DINOFF: DINOFF3 Mask              */
+
+#define GPIO_DINOFF_DINOFF4_Pos          (20)                                              /*!< GPIO_T::DINOFF: DINOFF4 Position          */
+#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)                /*!< GPIO_T::DINOFF: DINOFF4 Mask              */
+
+#define GPIO_DINOFF_DINOFF5_Pos          (21)                                              /*!< GPIO_T::DINOFF: DINOFF5 Position          */
+#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)                /*!< GPIO_T::DINOFF: DINOFF5 Mask              */
+
+#define GPIO_DINOFF_DINOFF6_Pos          (22)                                              /*!< GPIO_T::DINOFF: DINOFF6 Position          */
+#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)                /*!< GPIO_T::DINOFF: DINOFF6 Mask              */
+
+#define GPIO_DINOFF_DINOFF7_Pos          (23)                                              /*!< GPIO_T::DINOFF: DINOFF7 Position          */
+#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)                /*!< GPIO_T::DINOFF: DINOFF7 Mask              */
+
+#define GPIO_DINOFF_DINOFF8_Pos          (24)                                              /*!< GPIO_T::DINOFF: DINOFF8 Position          */
+#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)                /*!< GPIO_T::DINOFF: DINOFF8 Mask              */
+
+#define GPIO_DINOFF_DINOFF9_Pos          (25)                                              /*!< GPIO_T::DINOFF: DINOFF9 Position          */
+#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)                /*!< GPIO_T::DINOFF: DINOFF9 Mask              */
+
+#define GPIO_DINOFF_DINOFF10_Pos         (26)                                              /*!< GPIO_T::DINOFF: DINOFF10 Position         */
+#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)               /*!< GPIO_T::DINOFF: DINOFF10 Mask             */
+
+#define GPIO_DINOFF_DINOFF11_Pos         (27)                                              /*!< GPIO_T::DINOFF: DINOFF11 Position         */
+#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)               /*!< GPIO_T::DINOFF: DINOFF11 Mask             */
+
+#define GPIO_DINOFF_DINOFF12_Pos         (28)                                              /*!< GPIO_T::DINOFF: DINOFF12 Position         */
+#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)               /*!< GPIO_T::DINOFF: DINOFF12 Mask             */
+
+#define GPIO_DINOFF_DINOFF13_Pos         (29)                                              /*!< GPIO_T::DINOFF: DINOFF13 Position         */
+#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)               /*!< GPIO_T::DINOFF: DINOFF13 Mask             */
+
+#define GPIO_DINOFF_DINOFF14_Pos         (30)                                              /*!< GPIO_T::DINOFF: DINOFF14 Position         */
+#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)               /*!< GPIO_T::DINOFF: DINOFF14 Mask             */
+
+#define GPIO_DINOFF_DINOFF15_Pos         (31)                                              /*!< GPIO_T::DINOFF: DINOFF15 Position         */
+#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)               /*!< GPIO_T::DINOFF: DINOFF15 Mask             */
+
+#define GPIO_DOUT_DOUT0_Pos              (0)                                               /*!< GPIO_T::DOUT: DOUT0 Position              */
+#define GPIO_DOUT_DOUT0_Msk              (0x1ul << GPIO_DOUT_DOUT0_Pos)                    /*!< GPIO_T::DOUT: DOUT0 Mask                  */
+
+#define GPIO_DOUT_DOUT1_Pos              (1)                                               /*!< GPIO_T::DOUT: DOUT1 Position              */
+#define GPIO_DOUT_DOUT1_Msk              (0x1ul << GPIO_DOUT_DOUT1_Pos)                    /*!< GPIO_T::DOUT: DOUT1 Mask                  */
+
+#define GPIO_DOUT_DOUT2_Pos              (2)                                               /*!< GPIO_T::DOUT: DOUT2 Position              */
+#define GPIO_DOUT_DOUT2_Msk              (0x1ul << GPIO_DOUT_DOUT2_Pos)                    /*!< GPIO_T::DOUT: DOUT2 Mask                  */
+
+#define GPIO_DOUT_DOUT3_Pos              (3)                                               /*!< GPIO_T::DOUT: DOUT3 Position              */
+#define GPIO_DOUT_DOUT3_Msk              (0x1ul << GPIO_DOUT_DOUT3_Pos)                    /*!< GPIO_T::DOUT: DOUT3 Mask                  */
+
+#define GPIO_DOUT_DOUT4_Pos              (4)                                               /*!< GPIO_T::DOUT: DOUT4 Position              */
+#define GPIO_DOUT_DOUT4_Msk              (0x1ul << GPIO_DOUT_DOUT4_Pos)                    /*!< GPIO_T::DOUT: DOUT4 Mask                  */
+
+#define GPIO_DOUT_DOUT5_Pos              (5)                                               /*!< GPIO_T::DOUT: DOUT5 Position              */
+#define GPIO_DOUT_DOUT5_Msk              (0x1ul << GPIO_DOUT_DOUT5_Pos)                    /*!< GPIO_T::DOUT: DOUT5 Mask                  */
+
+#define GPIO_DOUT_DOUT6_Pos              (6)                                               /*!< GPIO_T::DOUT: DOUT6 Position              */
+#define GPIO_DOUT_DOUT6_Msk              (0x1ul << GPIO_DOUT_DOUT6_Pos)                    /*!< GPIO_T::DOUT: DOUT6 Mask                  */
+
+#define GPIO_DOUT_DOUT7_Pos              (7)                                               /*!< GPIO_T::DOUT: DOUT7 Position              */
+#define GPIO_DOUT_DOUT7_Msk              (0x1ul << GPIO_DOUT_DOUT7_Pos)                    /*!< GPIO_T::DOUT: DOUT7 Mask                  */
+
+#define GPIO_DOUT_DOUT8_Pos              (8)                                               /*!< GPIO_T::DOUT: DOUT8 Position              */
+#define GPIO_DOUT_DOUT8_Msk              (0x1ul << GPIO_DOUT_DOUT8_Pos)                    /*!< GPIO_T::DOUT: DOUT8 Mask                  */
+
+#define GPIO_DOUT_DOUT9_Pos              (9)                                               /*!< GPIO_T::DOUT: DOUT9 Position              */
+#define GPIO_DOUT_DOUT9_Msk              (0x1ul << GPIO_DOUT_DOUT9_Pos)                    /*!< GPIO_T::DOUT: DOUT9 Mask                  */
+
+#define GPIO_DOUT_DOUT10_Pos             (10)                                              /*!< GPIO_T::DOUT: DOUT10 Position             */
+#define GPIO_DOUT_DOUT10_Msk             (0x1ul << GPIO_DOUT_DOUT10_Pos)                   /*!< GPIO_T::DOUT: DOUT10 Mask                 */
+
+#define GPIO_DOUT_DOUT11_Pos             (11)                                              /*!< GPIO_T::DOUT: DOUT11 Position             */
+#define GPIO_DOUT_DOUT11_Msk             (0x1ul << GPIO_DOUT_DOUT11_Pos)                   /*!< GPIO_T::DOUT: DOUT11 Mask                 */
+
+#define GPIO_DOUT_DOUT12_Pos             (12)                                              /*!< GPIO_T::DOUT: DOUT12 Position             */
+#define GPIO_DOUT_DOUT12_Msk             (0x1ul << GPIO_DOUT_DOUT12_Pos)                   /*!< GPIO_T::DOUT: DOUT12 Mask                 */
+
+#define GPIO_DOUT_DOUT13_Pos             (13)                                              /*!< GPIO_T::DOUT: DOUT13 Position             */
+#define GPIO_DOUT_DOUT13_Msk             (0x1ul << GPIO_DOUT_DOUT13_Pos)                   /*!< GPIO_T::DOUT: DOUT13 Mask                 */
+
+#define GPIO_DOUT_DOUT14_Pos             (14)                                              /*!< GPIO_T::DOUT: DOUT14 Position             */
+#define GPIO_DOUT_DOUT14_Msk             (0x1ul << GPIO_DOUT_DOUT14_Pos)                   /*!< GPIO_T::DOUT: DOUT14 Mask                 */
+
+#define GPIO_DOUT_DOUT15_Pos             (15)                                              /*!< GPIO_T::DOUT: DOUT15 Position             */
+#define GPIO_DOUT_DOUT15_Msk             (0x1ul << GPIO_DOUT_DOUT15_Pos)                   /*!< GPIO_T::DOUT: DOUT15 Mask                 */
+
+#define GPIO_DATMSK_DATMSK0_Pos          (0)                                               /*!< GPIO_T::DATMSK: DATMSK0 Position       */
+#define GPIO_DATMSK_DATMSK0_Msk          (0x1ul << GPIO_DATMSK_DATMSK0_Pos)                /*!< GPIO_T::DATMSK: DATMSK0 Mask           */
+
+#define GPIO_DATMSK_DATMSK1_Pos          (1)                                               /*!< GPIO_T::DATMSK: DATMSK1 Position       */
+#define GPIO_DATMSK_DATMSK1_Msk          (0x1ul << GPIO_DATMSK_DATMSK1_Pos)                /*!< GPIO_T::DATMSK: DATMSK1 Mask           */
+
+#define GPIO_DATMSK_DATMSK2_Pos          (2)                                               /*!< GPIO_T::DATMSK: DATMSK2 Position       */
+#define GPIO_DATMSK_DATMSK2_Msk          (0x1ul << GPIO_DATMSK_DATMSK2_Pos)                /*!< GPIO_T::DATMSK: DATMSK2 Mask           */
+
+#define GPIO_DATMSK_DATMSK3_Pos          (3)                                               /*!< GPIO_T::DATMSK: DATMSK3 Position       */
+#define GPIO_DATMSK_DATMSK3_Msk          (0x1ul << GPIO_DATMSK_DATMSK3_Pos)                /*!< GPIO_T::DATMSK: DATMSK3 Mask           */
+
+#define GPIO_DATMSK_DATMSK4_Pos          (4)                                               /*!< GPIO_T::DATMSK: DATMSK4 Position       */
+#define GPIO_DATMSK_DATMSK4_Msk          (0x1ul << GPIO_DATMSK_DATMSK4_Pos)                /*!< GPIO_T::DATMSK: DATMSK4 Mask           */
+
+#define GPIO_DATMSK_DATMSK5_Pos          (5)                                               /*!< GPIO_T::DATMSK: DATMSK5 Position       */
+#define GPIO_DATMSK_DATMSK5_Msk          (0x1ul << GPIO_DATMSK_DATMSK5_Pos)                /*!< GPIO_T::DATMSK: DATMSK5 Mask           */
+
+#define GPIO_DATMSK_DATMSK6_Pos          (6)                                               /*!< GPIO_T::DATMSK: DATMSK6 Position       */
+#define GPIO_DATMSK_DATMSK6_Msk          (0x1ul << GPIO_DATMSK_DATMSK6_Pos)                /*!< GPIO_T::DATMSK: DATMSK6 Mask           */
+
+#define GPIO_DATMSK_DATMSK7_Pos          (7)                                               /*!< GPIO_T::DATMSK: DATMSK7 Position       */
+#define GPIO_DATMSK_DATMSK7_Msk          (0x1ul << GPIO_DATMSK_DATMSK7_Pos)                /*!< GPIO_T::DATMSK: DATMSK7 Mask           */
+
+#define GPIO_DATMSK_DATMSK8_Pos          (8)                                               /*!< GPIO_T::DATMSK: DATMSK8 Position       */
+#define GPIO_DATMSK_DATMSK8_Msk          (0x1ul << GPIO_DATMSK_DATMSK8_Pos)                /*!< GPIO_T::DATMSK: DATMSK8 Mask           */
+
+#define GPIO_DATMSK_DATMSK9_Pos          (9)                                               /*!< GPIO_T::DATMSK: DATMSK9 Position       */
+#define GPIO_DATMSK_DATMSK9_Msk          (0x1ul << GPIO_DATMSK_DATMSK9_Pos)                /*!< GPIO_T::DATMSK: DATMSK9 Mask           */
+
+#define GPIO_DATMSK_DATMSK10_Pos         (10)                                              /*!< GPIO_T::DATMSK: DATMSK10 Position      */
+#define GPIO_DATMSK_DATMSK10_Msk         (0x1ul << GPIO_DATMSK_DATMSK10_Pos)               /*!< GPIO_T::DATMSK: DATMSK10 Mask          */
+
+#define GPIO_DATMSK_DATMSK11_Pos         (11)                                              /*!< GPIO_T::DATMSK: DATMSK11 Position      */
+#define GPIO_DATMSK_DATMSK11_Msk         (0x1ul << GPIO_DATMSK_DATMSK11_Pos)               /*!< GPIO_T::DATMSK: DATMSK11 Mask          */
+
+#define GPIO_DATMSK_DATMSK12_Pos         (12)                                              /*!< GPIO_T::DATMSK: DATMSK12 Position      */
+#define GPIO_DATMSK_DATMSK12_Msk         (0x1ul << GPIO_DATMSK_DATMSK12_Pos)               /*!< GPIO_T::DATMSK: DATMSK12 Mask          */
+
+#define GPIO_DATMSK_DATMSK13_Pos         (13)                                              /*!< GPIO_T::DATMSK: DATMSK13 Position      */
+#define GPIO_DATMSK_DATMSK13_Msk         (0x1ul << GPIO_DATMSK_DATMSK13_Pos)               /*!< GPIO_T::DATMSK: DATMSK13 Mask          */
+
+#define GPIO_DATMSK_DATMSK14_Pos         (14)                                              /*!< GPIO_T::DATMSK: DATMSK14 Position      */
+#define GPIO_DATMSK_DATMSK14_Msk         (0x1ul << GPIO_DATMSK_DATMSK14_Pos)               /*!< GPIO_T::DATMSK: DATMSK14 Mask          */
+
+#define GPIO_DATMSK_DATMSK15_Pos         (15)                                              /*!< GPIO_T::DATMSK: DATMSK15 Position      */
+#define GPIO_DATMSK_DATMSK15_Msk         (0x1ul << GPIO_DATMSK_DATMSK15_Pos)               /*!< GPIO_T::DATMSK: DATMSK15 Mask          */
+
+#define GPIO_PIN_PIN0_Pos                (0)                                               /*!< GPIO_T::PIN: PIN0 Position             */
+#define GPIO_PIN_PIN0_Msk                (0x1ul << GPIO_PIN_PIN0_Pos)                      /*!< GPIO_T::PIN: PIN0 Mask                 */
+
+#define GPIO_PIN_PIN1_Pos                (1)                                               /*!< GPIO_T::PIN: PIN1 Position             */
+#define GPIO_PIN_PIN1_Msk                (0x1ul << GPIO_PIN_PIN1_Pos)                      /*!< GPIO_T::PIN: PIN1 Mask                 */
+
+#define GPIO_PIN_PIN2_Pos                (2)                                               /*!< GPIO_T::PIN: PIN2 Position             */
+#define GPIO_PIN_PIN2_Msk                (0x1ul << GPIO_PIN_PIN2_Pos)                      /*!< GPIO_T::PIN: PIN2 Mask                 */
+
+#define GPIO_PIN_PIN3_Pos                (3)                                               /*!< GPIO_T::PIN: PIN3 Position             */
+#define GPIO_PIN_PIN3_Msk                (0x1ul << GPIO_PIN_PIN3_Pos)                      /*!< GPIO_T::PIN: PIN3 Mask                 */
+
+#define GPIO_PIN_PIN4_Pos                (4)                                               /*!< GPIO_T::PIN: PIN4 Position             */
+#define GPIO_PIN_PIN4_Msk                (0x1ul << GPIO_PIN_PIN4_Pos)                      /*!< GPIO_T::PIN: PIN4 Mask                 */
+
+#define GPIO_PIN_PIN5_Pos                (5)                                               /*!< GPIO_T::PIN: PIN5 Position             */
+#define GPIO_PIN_PIN5_Msk                (0x1ul << GPIO_PIN_PIN5_Pos)                      /*!< GPIO_T::PIN: PIN5 Mask                 */
+
+#define GPIO_PIN_PIN6_Pos                (6)                                               /*!< GPIO_T::PIN: PIN6 Position             */
+#define GPIO_PIN_PIN6_Msk                (0x1ul << GPIO_PIN_PIN6_Pos)                      /*!< GPIO_T::PIN: PIN6 Mask                 */
+
+#define GPIO_PIN_PIN7_Pos                (7)                                               /*!< GPIO_T::PIN: PIN7 Position             */
+#define GPIO_PIN_PIN7_Msk                (0x1ul << GPIO_PIN_PIN7_Pos)                      /*!< GPIO_T::PIN: PIN7 Mask                 */
+
+#define GPIO_PIN_PIN8_Pos                (8)                                               /*!< GPIO_T::PIN: PIN8 Position             */
+#define GPIO_PIN_PIN8_Msk                (0x1ul << GPIO_PIN_PIN8_Pos)                      /*!< GPIO_T::PIN: PIN8 Mask                 */
+
+#define GPIO_PIN_PIN9_Pos                (9)                                               /*!< GPIO_T::PIN: PIN9 Position             */
+#define GPIO_PIN_PIN9_Msk                (0x1ul << GPIO_PIN_PIN9_Pos)                      /*!< GPIO_T::PIN: PIN9 Mask                 */
+
+#define GPIO_PIN_PIN10_Pos               (10)                                              /*!< GPIO_T::PIN: PIN10 Position            */
+#define GPIO_PIN_PIN10_Msk               (0x1ul << GPIO_PIN_PIN10_Pos)                     /*!< GPIO_T::PIN: PIN10 Mask                */
+
+#define GPIO_PIN_PIN11_Pos               (11)                                              /*!< GPIO_T::PIN: PIN11 Position            */
+#define GPIO_PIN_PIN11_Msk               (0x1ul << GPIO_PIN_PIN11_Pos)                     /*!< GPIO_T::PIN: PIN11 Mask                */
+
+#define GPIO_PIN_PIN12_Pos               (12)                                              /*!< GPIO_T::PIN: PIN12 Position            */
+#define GPIO_PIN_PIN12_Msk               (0x1ul << GPIO_PIN_PIN12_Pos)                     /*!< GPIO_T::PIN: PIN12 Mask                */
+
+#define GPIO_PIN_PIN13_Pos               (13)                                              /*!< GPIO_T::PIN: PIN13 Position            */
+#define GPIO_PIN_PIN13_Msk               (0x1ul << GPIO_PIN_PIN13_Pos)                     /*!< GPIO_T::PIN: PIN13 Mask                */
+
+#define GPIO_PIN_PIN14_Pos               (14)                                              /*!< GPIO_T::PIN: PIN14 Position            */
+#define GPIO_PIN_PIN14_Msk               (0x1ul << GPIO_PIN_PIN14_Pos)                     /*!< GPIO_T::PIN: PIN14 Mask                */
+
+#define GPIO_PIN_PIN15_Pos               (15)                                              /*!< GPIO_T::PIN: PIN15 Position            */
+#define GPIO_PIN_PIN15_Msk               (0x1ul << GPIO_PIN_PIN15_Pos)                     /*!< GPIO_T::PIN: PIN15 Mask                */
+
+#define GPIO_DBEN_DBEN0_Pos              (0)                                               /*!< GPIO_T::DBEN: DBEN0 Position           */
+#define GPIO_DBEN_DBEN0_Msk              (0x1ul << GPIO_DBEN_DBEN0_Pos)                    /*!< GPIO_T::DBEN: DBEN0 Mask               */
+
+#define GPIO_DBEN_DBEN1_Pos              (1)                                               /*!< GPIO_T::DBEN: DBEN1 Position           */
+#define GPIO_DBEN_DBEN1_Msk              (0x1ul << GPIO_DBEN_DBEN1_Pos)                    /*!< GPIO_T::DBEN: DBEN1 Mask               */
+
+#define GPIO_DBEN_DBEN2_Pos              (2)                                               /*!< GPIO_T::DBEN: DBEN2 Position           */
+#define GPIO_DBEN_DBEN2_Msk              (0x1ul << GPIO_DBEN_DBEN2_Pos)                    /*!< GPIO_T::DBEN: DBEN2 Mask               */
+
+#define GPIO_DBEN_DBEN3_Pos              (3)                                               /*!< GPIO_T::DBEN: DBEN3 Position           */
+#define GPIO_DBEN_DBEN3_Msk              (0x1ul << GPIO_DBEN_DBEN3_Pos)                    /*!< GPIO_T::DBEN: DBEN3 Mask               */
+
+#define GPIO_DBEN_DBEN4_Pos              (4)                                               /*!< GPIO_T::DBEN: DBEN4 Position           */
+#define GPIO_DBEN_DBEN4_Msk              (0x1ul << GPIO_DBEN_DBEN4_Pos)                    /*!< GPIO_T::DBEN: DBEN4 Mask               */
+
+#define GPIO_DBEN_DBEN5_Pos              (5)                                               /*!< GPIO_T::DBEN: DBEN5 Position           */
+#define GPIO_DBEN_DBEN5_Msk              (0x1ul << GPIO_DBEN_DBEN5_Pos)                    /*!< GPIO_T::DBEN: DBEN5 Mask               */
+
+#define GPIO_DBEN_DBEN6_Pos              (6)                                               /*!< GPIO_T::DBEN: DBEN6 Position           */
+#define GPIO_DBEN_DBEN6_Msk              (0x1ul << GPIO_DBEN_DBEN6_Pos)                    /*!< GPIO_T::DBEN: DBEN6 Mask               */
+
+#define GPIO_DBEN_DBEN7_Pos              (7)                                               /*!< GPIO_T::DBEN: DBEN7 Position           */
+#define GPIO_DBEN_DBEN7_Msk              (0x1ul << GPIO_DBEN_DBEN7_Pos)                    /*!< GPIO_T::DBEN: DBEN7 Mask               */
+
+#define GPIO_DBEN_DBEN8_Pos              (8)                                               /*!< GPIO_T::DBEN: DBEN8 Position           */
+#define GPIO_DBEN_DBEN8_Msk              (0x1ul << GPIO_DBEN_DBEN8_Pos)                    /*!< GPIO_T::DBEN: DBEN8 Mask               */
+
+#define GPIO_DBEN_DBEN9_Pos              (9)                                               /*!< GPIO_T::DBEN: DBEN9 Position           */
+#define GPIO_DBEN_DBEN9_Msk              (0x1ul << GPIO_DBEN_DBEN9_Pos)                    /*!< GPIO_T::DBEN: DBEN9 Mask               */
+
+#define GPIO_DBEN_DBEN10_Pos             (10)                                              /*!< GPIO_T::DBEN: DBEN10 Position          */
+#define GPIO_DBEN_DBEN10_Msk             (0x1ul << GPIO_DBEN_DBEN10_Pos)                   /*!< GPIO_T::DBEN: DBEN10 Mask              */
+
+#define GPIO_DBEN_DBEN11_Pos             (11)                                              /*!< GPIO_T::DBEN: DBEN11 Position          */
+#define GPIO_DBEN_DBEN11_Msk             (0x1ul << GPIO_DBEN_DBEN11_Pos)                   /*!< GPIO_T::DBEN: DBEN11 Mask              */
+
+#define GPIO_DBEN_DBEN12_Pos             (12)                                              /*!< GPIO_T::DBEN: DBEN12 Position          */
+#define GPIO_DBEN_DBEN12_Msk             (0x1ul << GPIO_DBEN_DBEN12_Pos)                   /*!< GPIO_T::DBEN: DBEN12 Mask              */
+
+#define GPIO_DBEN_DBEN13_Pos             (13)                                              /*!< GPIO_T::DBEN: DBEN13 Position          */
+#define GPIO_DBEN_DBEN13_Msk             (0x1ul << GPIO_DBEN_DBEN13_Pos)                   /*!< GPIO_T::DBEN: DBEN13 Mask              */
+
+#define GPIO_DBEN_DBEN14_Pos             (14)                                              /*!< GPIO_T::DBEN: DBEN14 Position          */
+#define GPIO_DBEN_DBEN14_Msk             (0x1ul << GPIO_DBEN_DBEN14_Pos)                   /*!< GPIO_T::DBEN: DBEN14 Mask              */
+
+#define GPIO_DBEN_DBEN15_Pos             (15)                                              /*!< GPIO_T::DBEN: DBEN15 Position          */
+#define GPIO_DBEN_DBEN15_Msk             (0x1ul << GPIO_DBEN_DBEN15_Pos)                   /*!< GPIO_T::DBEN: DBEN15 Mask              */
+
+#define GPIO_INTTYPE_TYPE0_Pos           (0)                                               /*!< GPIO_T::INTTYPE: TYPE0 Position        */
+#define GPIO_INTTYPE_TYPE0_Msk           (0x1ul << GPIO_INTTYPE_TYPE0_Pos)                 /*!< GPIO_T::INTTYPE: TYPE0 Mask            */
+
+#define GPIO_INTTYPE_TYPE1_Pos           (1)                                               /*!< GPIO_T::INTTYPE: TYPE1 Position        */
+#define GPIO_INTTYPE_TYPE1_Msk           (0x1ul << GPIO_INTTYPE_TYPE1_Pos)                 /*!< GPIO_T::INTTYPE: TYPE1 Mask            */
+
+#define GPIO_INTTYPE_TYPE2_Pos           (2)                                               /*!< GPIO_T::INTTYPE: TYPE2 Position        */
+#define GPIO_INTTYPE_TYPE2_Msk           (0x1ul << GPIO_INTTYPE_TYPE2_Pos)                 /*!< GPIO_T::INTTYPE: TYPE2 Mask            */
+
+#define GPIO_INTTYPE_TYPE3_Pos           (3)                                               /*!< GPIO_T::INTTYPE: TYPE3 Position        */
+#define GPIO_INTTYPE_TYPE3_Msk           (0x1ul << GPIO_INTTYPE_TYPE3_Pos)                 /*!< GPIO_T::INTTYPE: TYPE3 Mask            */
+
+#define GPIO_INTTYPE_TYPE4_Pos           (4)                                               /*!< GPIO_T::INTTYPE: TYPE4 Position        */
+#define GPIO_INTTYPE_TYPE4_Msk           (0x1ul << GPIO_INTTYPE_TYPE4_Pos)                 /*!< GPIO_T::INTTYPE: TYPE4 Mask            */
+
+#define GPIO_INTTYPE_TYPE5_Pos           (5)                                               /*!< GPIO_T::INTTYPE: TYPE5 Position        */
+#define GPIO_INTTYPE_TYPE5_Msk           (0x1ul << GPIO_INTTYPE_TYPE5_Pos)                 /*!< GPIO_T::INTTYPE: TYPE5 Mask            */
+
+#define GPIO_INTTYPE_TYPE6_Pos           (6)                                               /*!< GPIO_T::INTTYPE: TYPE6 Position        */
+#define GPIO_INTTYPE_TYPE6_Msk           (0x1ul << GPIO_INTTYPE_TYPE6_Pos)                 /*!< GPIO_T::INTTYPE: TYPE6 Mask            */
+
+#define GPIO_INTTYPE_TYPE7_Pos           (7)                                               /*!< GPIO_T::INTTYPE: TYPE7 Position        */
+#define GPIO_INTTYPE_TYPE7_Msk           (0x1ul << GPIO_INTTYPE_TYPE7_Pos)                 /*!< GPIO_T::INTTYPE: TYPE7 Mask            */
+
+#define GPIO_INTTYPE_TYPE8_Pos           (8)                                               /*!< GPIO_T::INTTYPE: TYPE8 Position        */
+#define GPIO_INTTYPE_TYPE8_Msk           (0x1ul << GPIO_INTTYPE_TYPE8_Pos)                 /*!< GPIO_T::INTTYPE: TYPE8 Mask            */
+
+#define GPIO_INTTYPE_TYPE9_Pos           (9)                                               /*!< GPIO_T::INTTYPE: TYPE9 Position        */
+#define GPIO_INTTYPE_TYPE9_Msk           (0x1ul << GPIO_INTTYPE_TYPE9_Pos)                 /*!< GPIO_T::INTTYPE: TYPE9 Mask            */
+
+#define GPIO_INTTYPE_TYPE10_Pos          (10)                                              /*!< GPIO_T::INTTYPE: TYPE10 Position       */
+#define GPIO_INTTYPE_TYPE10_Msk          (0x1ul << GPIO_INTTYPE_TYPE10_Pos)                /*!< GPIO_T::INTTYPE: TYPE10 Mask           */
+
+#define GPIO_INTTYPE_TYPE11_Pos          (11)                                              /*!< GPIO_T::INTTYPE: TYPE11 Position       */
+#define GPIO_INTTYPE_TYPE11_Msk          (0x1ul << GPIO_INTTYPE_TYPE11_Pos)                /*!< GPIO_T::INTTYPE: TYPE11 Mask           */
+
+#define GPIO_INTTYPE_TYPE12_Pos          (12)                                              /*!< GPIO_T::INTTYPE: TYPE12 Position       */
+#define GPIO_INTTYPE_TYPE12_Msk          (0x1ul << GPIO_INTTYPE_TYPE12_Pos)                /*!< GPIO_T::INTTYPE: TYPE12 Mask           */
+
+#define GPIO_INTTYPE_TYPE13_Pos          (13)                                              /*!< GPIO_T::INTTYPE: TYPE13 Position       */
+#define GPIO_INTTYPE_TYPE13_Msk          (0x1ul << GPIO_INTTYPE_TYPE13_Pos)                /*!< GPIO_T::INTTYPE: TYPE13 Mask           */
+
+#define GPIO_INTTYPE_TYPE14_Pos          (14)                                              /*!< GPIO_T::INTTYPE: TYPE14 Position       */
+#define GPIO_INTTYPE_TYPE14_Msk          (0x1ul << GPIO_INTTYPE_TYPE14_Pos)                /*!< GPIO_T::INTTYPE: TYPE14 Mask           */
+
+#define GPIO_INTTYPE_TYPE15_Pos          (15)                                              /*!< GPIO_T::INTTYPE: TYPE15 Position       */
+#define GPIO_INTTYPE_TYPE15_Msk          (0x1ul << GPIO_INTTYPE_TYPE15_Pos)                /*!< GPIO_T::INTTYPE: TYPE15 Mask           */
+
+#define GPIO_INTEN_FLIEN0_Pos            (0)                                               /*!< GPIO_T::INTEN: FLIEN0 Position         */
+#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)                  /*!< GPIO_T::INTEN: FLIEN0 Mask             */
+
+#define GPIO_INTEN_FLIEN1_Pos            (1)                                               /*!< GPIO_T::INTEN: FLIEN1 Position         */
+#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)                  /*!< GPIO_T::INTEN: FLIEN1 Mask             */
+
+#define GPIO_INTEN_FLIEN2_Pos            (2)                                               /*!< GPIO_T::INTEN: FLIEN2 Position         */
+#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)                  /*!< GPIO_T::INTEN: FLIEN2 Mask             */
+
+#define GPIO_INTEN_FLIEN3_Pos            (3)                                               /*!< GPIO_T::INTEN: FLIEN3 Position         */
+#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)                  /*!< GPIO_T::INTEN: FLIEN3 Mask             */
+
+#define GPIO_INTEN_FLIEN4_Pos            (4)                                               /*!< GPIO_T::INTEN: FLIEN4 Position         */
+#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)                  /*!< GPIO_T::INTEN: FLIEN4 Mask             */
+
+#define GPIO_INTEN_FLIEN5_Pos            (5)                                               /*!< GPIO_T::INTEN: FLIEN5 Position         */
+#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)                  /*!< GPIO_T::INTEN: FLIEN5 Mask             */
+
+#define GPIO_INTEN_FLIEN6_Pos            (6)                                               /*!< GPIO_T::INTEN: FLIEN6 Position         */
+#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)                  /*!< GPIO_T::INTEN: FLIEN6 Mask             */
+
+#define GPIO_INTEN_FLIEN7_Pos            (7)                                               /*!< GPIO_T::INTEN: FLIEN7 Position         */
+#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)                  /*!< GPIO_T::INTEN: FLIEN7 Mask             */
+
+#define GPIO_INTEN_FLIEN8_Pos            (8)                                               /*!< GPIO_T::INTEN: FLIEN8 Position         */
+#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)                  /*!< GPIO_T::INTEN: FLIEN8 Mask             */
+
+#define GPIO_INTEN_FLIEN9_Pos            (9)                                               /*!< GPIO_T::INTEN: FLIEN9 Position         */
+#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)                  /*!< GPIO_T::INTEN: FLIEN9 Mask             */
+
+#define GPIO_INTEN_FLIEN10_Pos           (10)                                              /*!< GPIO_T::INTEN: FLIEN10 Position        */
+#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)                 /*!< GPIO_T::INTEN: FLIEN10 Mask            */
+
+#define GPIO_INTEN_FLIEN11_Pos           (11)                                              /*!< GPIO_T::INTEN: FLIEN11 Position        */
+#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)                 /*!< GPIO_T::INTEN: FLIEN11 Mask            */
+
+#define GPIO_INTEN_FLIEN12_Pos           (12)                                              /*!< GPIO_T::INTEN: FLIEN12 Position        */
+#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)                 /*!< GPIO_T::INTEN: FLIEN12 Mask            */
+
+#define GPIO_INTEN_FLIEN13_Pos           (13)                                              /*!< GPIO_T::INTEN: FLIEN13 Position        */
+#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)                 /*!< GPIO_T::INTEN: FLIEN13 Mask            */
+
+#define GPIO_INTEN_FLIEN14_Pos           (14)                                              /*!< GPIO_T::INTEN: FLIEN14 Position        */
+#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)                 /*!< GPIO_T::INTEN: FLIEN14 Mask            */
+
+#define GPIO_INTEN_FLIEN15_Pos           (15)                                              /*!< GPIO_T::INTEN: FLIEN15 Position        */
+#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)                 /*!< GPIO_T::INTEN: FLIEN15 Mask            */
+
+#define GPIO_INTEN_RHIEN0_Pos            (16)                                              /*!< GPIO_T::INTEN: RHIEN0 Position         */
+#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)                  /*!< GPIO_T::INTEN: RHIEN0 Mask             */
+
+#define GPIO_INTEN_RHIEN1_Pos            (17)                                              /*!< GPIO_T::INTEN: RHIEN1 Position         */
+#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)                  /*!< GPIO_T::INTEN: RHIEN1 Mask             */
+
+#define GPIO_INTEN_RHIEN2_Pos            (18)                                              /*!< GPIO_T::INTEN: RHIEN2 Position         */
+#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)                  /*!< GPIO_T::INTEN: RHIEN2 Mask             */
+
+#define GPIO_INTEN_RHIEN3_Pos            (19)                                              /*!< GPIO_T::INTEN: RHIEN3 Position         */
+#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)                  /*!< GPIO_T::INTEN: RHIEN3 Mask             */
+
+#define GPIO_INTEN_RHIEN4_Pos            (20)                                              /*!< GPIO_T::INTEN: RHIEN4 Position         */
+#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)                  /*!< GPIO_T::INTEN: RHIEN4 Mask             */
+
+#define GPIO_INTEN_RHIEN5_Pos            (21)                                              /*!< GPIO_T::INTEN: RHIEN5 Position         */
+#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)                  /*!< GPIO_T::INTEN: RHIEN5 Mask             */
+
+#define GPIO_INTEN_RHIEN6_Pos            (22)                                              /*!< GPIO_T::INTEN: RHIEN6 Position         */
+#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)                  /*!< GPIO_T::INTEN: RHIEN6 Mask             */
+
+#define GPIO_INTEN_RHIEN7_Pos            (23)                                              /*!< GPIO_T::INTEN: RHIEN7 Position         */
+#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)                  /*!< GPIO_T::INTEN: RHIEN7 Mask             */
+
+#define GPIO_INTEN_RHIEN8_Pos            (24)                                              /*!< GPIO_T::INTEN: RHIEN8 Position         */
+#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)                  /*!< GPIO_T::INTEN: RHIEN8 Mask             */
+
+#define GPIO_INTEN_RHIEN9_Pos            (25)                                              /*!< GPIO_T::INTEN: RHIEN9 Position         */
+#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)                  /*!< GPIO_T::INTEN: RHIEN9 Mask             */
+
+#define GPIO_INTEN_RHIEN10_Pos           (26)                                              /*!< GPIO_T::INTEN: RHIEN10 Position        */
+#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)                 /*!< GPIO_T::INTEN: RHIEN10 Mask            */
+
+#define GPIO_INTEN_RHIEN11_Pos           (27)                                              /*!< GPIO_T::INTEN: RHIEN11 Position        */
+#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)                 /*!< GPIO_T::INTEN: RHIEN11 Mask            */
+
+#define GPIO_INTEN_RHIEN12_Pos           (28)                                              /*!< GPIO_T::INTEN: RHIEN12 Position        */
+#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)                 /*!< GPIO_T::INTEN: RHIEN12 Mask            */
+
+#define GPIO_INTEN_RHIEN13_Pos           (29)                                              /*!< GPIO_T::INTEN: RHIEN13 Position        */
+#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)                 /*!< GPIO_T::INTEN: RHIEN13 Mask            */
+
+#define GPIO_INTEN_RHIEN14_Pos           (30)                                              /*!< GPIO_T::INTEN: RHIEN14 Position        */
+#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)                 /*!< GPIO_T::INTEN: RHIEN14 Mask            */
+
+#define GPIO_INTEN_RHIEN15_Pos           (31)                                              /*!< GPIO_T::INTEN: RHIEN15 Position        */
+#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)                 /*!< GPIO_T::INTEN: RHIEN15 Mask            */
+
+#define GPIO_INTSRC_INTSRC0_Pos          (0)                                               /*!< GPIO_T::INTSRC: INTSRC0 Position       */
+#define GPIO_INTSRC_INTSRC0_Msk          (0x1ul << GPIO_INTSRC_INTSRC0_Pos)                /*!< GPIO_T::INTSRC: INTSRC0 Mask           */
+
+#define GPIO_INTSRC_INTSRC1_Pos          (1)                                               /*!< GPIO_T::INTSRC: INTSRC1 Position       */
+#define GPIO_INTSRC_INTSRC1_Msk          (0x1ul << GPIO_INTSRC_INTSRC1_Pos)                /*!< GPIO_T::INTSRC: INTSRC1 Mask           */
+
+#define GPIO_INTSRC_INTSRC2_Pos          (2)                                               /*!< GPIO_T::INTSRC: INTSRC2 Position       */
+#define GPIO_INTSRC_INTSRC2_Msk          (0x1ul << GPIO_INTSRC_INTSRC2_Pos)                /*!< GPIO_T::INTSRC: INTSRC2 Mask           */
+
+#define GPIO_INTSRC_INTSRC3_Pos          (3)                                               /*!< GPIO_T::INTSRC: INTSRC3 Position       */
+#define GPIO_INTSRC_INTSRC3_Msk          (0x1ul << GPIO_INTSRC_INTSRC3_Pos)                /*!< GPIO_T::INTSRC: INTSRC3 Mask           */
+
+#define GPIO_INTSRC_INTSRC4_Pos          (4)                                               /*!< GPIO_T::INTSRC: INTSRC4 Position       */
+#define GPIO_INTSRC_INTSRC4_Msk          (0x1ul << GPIO_INTSRC_INTSRC4_Pos)                /*!< GPIO_T::INTSRC: INTSRC4 Mask           */
+
+#define GPIO_INTSRC_INTSRC5_Pos          (5)                                               /*!< GPIO_T::INTSRC: INTSRC5 Position       */
+#define GPIO_INTSRC_INTSRC5_Msk          (0x1ul << GPIO_INTSRC_INTSRC5_Pos)                /*!< GPIO_T::INTSRC: INTSRC5 Mask           */
+
+#define GPIO_INTSRC_INTSRC6_Pos          (6)                                               /*!< GPIO_T::INTSRC: INTSRC6 Position       */
+#define GPIO_INTSRC_INTSRC6_Msk          (0x1ul << GPIO_INTSRC_INTSRC6_Pos)                /*!< GPIO_T::INTSRC: INTSRC6 Mask           */
+
+#define GPIO_INTSRC_INTSRC7_Pos          (7)                                               /*!< GPIO_T::INTSRC: INTSRC7 Position       */
+#define GPIO_INTSRC_INTSRC7_Msk          (0x1ul << GPIO_INTSRC_INTSRC7_Pos)                /*!< GPIO_T::INTSRC: INTSRC7 Mask           */
+
+#define GPIO_INTSRC_INTSRC8_Pos          (8)                                               /*!< GPIO_T::INTSRC: INTSRC8 Position       */
+#define GPIO_INTSRC_INTSRC8_Msk          (0x1ul << GPIO_INTSRC_INTSRC8_Pos)                /*!< GPIO_T::INTSRC: INTSRC8 Mask           */
+
+#define GPIO_INTSRC_INTSRC9_Pos          (9)                                               /*!< GPIO_T::INTSRC: INTSRC9 Position       */
+#define GPIO_INTSRC_INTSRC9_Msk          (0x1ul << GPIO_INTSRC_INTSRC9_Pos)                /*!< GPIO_T::INTSRC: INTSRC9 Mask           */
+
+#define GPIO_INTSRC_INTSRC10_Pos         (10)                                              /*!< GPIO_T::INTSRC: INTSRC10 Position      */
+#define GPIO_INTSRC_INTSRC10_Msk         (0x1ul << GPIO_INTSRC_INTSRC10_Pos)               /*!< GPIO_T::INTSRC: INTSRC10 Mask          */
+
+#define GPIO_INTSRC_INTSRC11_Pos         (11)                                              /*!< GPIO_T::INTSRC: INTSRC11 Position      */
+#define GPIO_INTSRC_INTSRC11_Msk         (0x1ul << GPIO_INTSRC_INTSRC11_Pos)               /*!< GPIO_T::INTSRC: INTSRC11 Mask          */
+
+#define GPIO_INTSRC_INTSRC12_Pos         (12)                                              /*!< GPIO_T::INTSRC: INTSRC12 Position      */
+#define GPIO_INTSRC_INTSRC12_Msk         (0x1ul << GPIO_INTSRC_INTSRC12_Pos)               /*!< GPIO_T::INTSRC: INTSRC12 Mask          */
+
+#define GPIO_INTSRC_INTSRC13_Pos         (13)                                              /*!< GPIO_T::INTSRC: INTSRC13 Position      */
+#define GPIO_INTSRC_INTSRC13_Msk         (0x1ul << GPIO_INTSRC_INTSRC13_Pos)               /*!< GPIO_T::INTSRC: INTSRC13 Mask          */
+
+#define GPIO_INTSRC_INTSRC14_Pos         (14)                                              /*!< GPIO_T::INTSRC: INTSRC14 Position      */
+#define GPIO_INTSRC_INTSRC14_Msk         (0x1ul << GPIO_INTSRC_INTSRC14_Pos)               /*!< GPIO_T::INTSRC: INTSRC14 Mask          */
+
+#define GPIO_INTSRC_INTSRC15_Pos         (15)                                              /*!< GPIO_T::INTSRC: INTSRC15 Position      */
+#define GPIO_INTSRC_INTSRC15_Msk         (0x1ul << GPIO_INTSRC_INTSRC15_Pos)               /*!< GPIO_T::INTSRC: INTSRC15 Mask          */
+
+#define GPIO_SMTEN_SMTEN0_Pos            (0)                                               /*!< GPIO_T::SMTEN: SMTEN0 Position         */
+#define GPIO_SMTEN_SMTEN0_Msk            (0x1ul << GPIO_SMTEN_SMTEN0_Pos)                  /*!< GPIO_T::SMTEN: SMTEN0 Mask             */
+
+#define GPIO_SMTEN_SMTEN1_Pos            (1)                                               /*!< GPIO_T::SMTEN: SMTEN1 Position         */
+#define GPIO_SMTEN_SMTEN1_Msk            (0x1ul << GPIO_SMTEN_SMTEN1_Pos)                  /*!< GPIO_T::SMTEN: SMTEN1 Mask             */
+
+#define GPIO_SMTEN_SMTEN2_Pos            (2)                                               /*!< GPIO_T::SMTEN: SMTEN2 Position         */
+#define GPIO_SMTEN_SMTEN2_Msk            (0x1ul << GPIO_SMTEN_SMTEN2_Pos)                  /*!< GPIO_T::SMTEN: SMTEN2 Mask             */
+
+#define GPIO_SMTEN_SMTEN3_Pos            (3)                                               /*!< GPIO_T::SMTEN: SMTEN3 Position         */
+#define GPIO_SMTEN_SMTEN3_Msk            (0x1ul << GPIO_SMTEN_SMTEN3_Pos)                  /*!< GPIO_T::SMTEN: SMTEN3 Mask             */
+
+#define GPIO_SMTEN_SMTEN4_Pos            (4)                                               /*!< GPIO_T::SMTEN: SMTEN4 Position         */
+#define GPIO_SMTEN_SMTEN4_Msk            (0x1ul << GPIO_SMTEN_SMTEN4_Pos)                  /*!< GPIO_T::SMTEN: SMTEN4 Mask             */
+
+#define GPIO_SMTEN_SMTEN5_Pos            (5)                                               /*!< GPIO_T::SMTEN: SMTEN5 Position         */
+#define GPIO_SMTEN_SMTEN5_Msk            (0x1ul << GPIO_SMTEN_SMTEN5_Pos)                  /*!< GPIO_T::SMTEN: SMTEN5 Mask             */
+
+#define GPIO_SMTEN_SMTEN6_Pos            (6)                                               /*!< GPIO_T::SMTEN: SMTEN6 Position         */
+#define GPIO_SMTEN_SMTEN6_Msk            (0x1ul << GPIO_SMTEN_SMTEN6_Pos)                  /*!< GPIO_T::SMTEN: SMTEN6 Mask             */
+
+#define GPIO_SMTEN_SMTEN7_Pos            (7)                                               /*!< GPIO_T::SMTEN: SMTEN7 Position         */
+#define GPIO_SMTEN_SMTEN7_Msk            (0x1ul << GPIO_SMTEN_SMTEN7_Pos)                  /*!< GPIO_T::SMTEN: SMTEN7 Mask             */
+
+#define GPIO_SMTEN_SMTEN8_Pos            (8)                                               /*!< GPIO_T::SMTEN: SMTEN8 Position         */
+#define GPIO_SMTEN_SMTEN8_Msk            (0x1ul << GPIO_SMTEN_SMTEN8_Pos)                  /*!< GPIO_T::SMTEN: SMTEN8 Mask             */
+
+#define GPIO_SMTEN_SMTEN9_Pos            (9)                                               /*!< GPIO_T::SMTEN: SMTEN9 Position         */
+#define GPIO_SMTEN_SMTEN9_Msk            (0x1ul << GPIO_SMTEN_SMTEN9_Pos)                  /*!< GPIO_T::SMTEN: SMTEN9 Mask             */
+
+#define GPIO_SMTEN_SMTEN10_Pos           (10)                                              /*!< GPIO_T::SMTEN: SMTEN10 Position        */
+#define GPIO_SMTEN_SMTEN10_Msk           (0x1ul << GPIO_SMTEN_SMTEN10_Pos)                 /*!< GPIO_T::SMTEN: SMTEN10 Mask            */
+
+#define GPIO_SMTEN_SMTEN11_Pos           (11)                                              /*!< GPIO_T::SMTEN: SMTEN11 Position        */
+#define GPIO_SMTEN_SMTEN11_Msk           (0x1ul << GPIO_SMTEN_SMTEN11_Pos)                 /*!< GPIO_T::SMTEN: SMTEN11 Mask            */
+
+#define GPIO_SMTEN_SMTEN12_Pos           (12)                                              /*!< GPIO_T::SMTEN: SMTEN12 Position        */
+#define GPIO_SMTEN_SMTEN12_Msk           (0x1ul << GPIO_SMTEN_SMTEN12_Pos)                 /*!< GPIO_T::SMTEN: SMTEN12 Mask            */
+
+#define GPIO_SMTEN_SMTEN13_Pos           (13)                                              /*!< GPIO_T::SMTEN: SMTEN13 Position        */
+#define GPIO_SMTEN_SMTEN13_Msk           (0x1ul << GPIO_SMTEN_SMTEN13_Pos)                 /*!< GPIO_T::SMTEN: SMTEN13 Mask            */
+
+#define GPIO_SMTEN_SMTEN14_Pos           (14)                                              /*!< GPIO_T::SMTEN: SMTEN14 Position        */
+#define GPIO_SMTEN_SMTEN14_Msk           (0x1ul << GPIO_SMTEN_SMTEN14_Pos)                 /*!< GPIO_T::SMTEN: SMTEN14 Mask            */
+
+#define GPIO_SMTEN_SMTEN15_Pos           (15)                                              /*!< GPIO_T::SMTEN: SMTEN15 Position        */
+#define GPIO_SMTEN_SMTEN15_Msk           (0x1ul << GPIO_SMTEN_SMTEN15_Pos)                 /*!< GPIO_T::SMTEN: SMTEN15 Mask            */
+
+#define GPIO_SLEWCTL_HSREN0_Pos          (0)                                               /*!< GPIO_T::SLEWCTL: HSREN0 Position       */
+#define GPIO_SLEWCTL_HSREN0_Msk          (0x3ul << GPIO_SLEWCTL_HSREN0_Pos)                /*!< GPIO_T::SLEWCTL: HSREN0 Mask           */
+
+#define GPIO_SLEWCTL_HSREN1_Pos          (2)                                               /*!< GPIO_T::SLEWCTL: HSREN1 Position       */
+#define GPIO_SLEWCTL_HSREN1_Msk          (0x3ul << GPIO_SLEWCTL_HSREN1_Pos)                /*!< GPIO_T::SLEWCTL: HSREN1 Mask           */
+
+#define GPIO_SLEWCTL_HSREN2_Pos          (4)                                               /*!< GPIO_T::SLEWCTL: HSREN2 Position       */
+#define GPIO_SLEWCTL_HSREN2_Msk          (0x3ul << GPIO_SLEWCTL_HSREN2_Pos)                /*!< GPIO_T::SLEWCTL: HSREN2 Mask           */
+
+#define GPIO_SLEWCTL_HSREN3_Pos          (6)                                               /*!< GPIO_T::SLEWCTL: HSREN3 Position       */
+#define GPIO_SLEWCTL_HSREN3_Msk          (0x3ul << GPIO_SLEWCTL_HSREN3_Pos)                /*!< GPIO_T::SLEWCTL: HSREN3 Mask           */
+
+#define GPIO_SLEWCTL_HSREN4_Pos          (8)                                               /*!< GPIO_T::SLEWCTL: HSREN4 Position       */
+#define GPIO_SLEWCTL_HSREN4_Msk          (0x3ul << GPIO_SLEWCTL_HSREN4_Pos)                /*!< GPIO_T::SLEWCTL: HSREN4 Mask           */
+
+#define GPIO_SLEWCTL_HSREN5_Pos          (10)                                              /*!< GPIO_T::SLEWCTL: HSREN5 Position       */
+#define GPIO_SLEWCTL_HSREN5_Msk          (0x3ul << GPIO_SLEWCTL_HSREN5_Pos)                /*!< GPIO_T::SLEWCTL: HSREN5 Mask           */
+
+#define GPIO_SLEWCTL_HSREN6_Pos          (12)                                              /*!< GPIO_T::SLEWCTL: HSREN6 Position       */
+#define GPIO_SLEWCTL_HSREN6_Msk          (0x3ul << GPIO_SLEWCTL_HSREN6_Pos)                /*!< GPIO_T::SLEWCTL: HSREN6 Mask           */
+
+#define GPIO_SLEWCTL_HSREN7_Pos          (14)                                              /*!< GPIO_T::SLEWCTL: HSREN7 Position       */
+#define GPIO_SLEWCTL_HSREN7_Msk          (0x3ul << GPIO_SLEWCTL_HSREN7_Pos)                /*!< GPIO_T::SLEWCTL: HSREN7 Mask           */
+
+#define GPIO_SLEWCTL_HSREN8_Pos          (16)                                              /*!< GPIO_T::SLEWCTL: HSREN8 Position       */
+#define GPIO_SLEWCTL_HSREN8_Msk          (0x3ul << GPIO_SLEWCTL_HSREN8_Pos)                /*!< GPIO_T::SLEWCTL: HSREN8 Mask           */
+
+#define GPIO_SLEWCTL_HSREN9_Pos          (18)                                              /*!< GPIO_T::SLEWCTL: HSREN9 Position       */
+#define GPIO_SLEWCTL_HSREN9_Msk          (0x3ul << GPIO_SLEWCTL_HSREN9_Pos)                /*!< GPIO_T::SLEWCTL: HSREN9 Mask           */
+
+#define GPIO_SLEWCTL_HSREN10_Pos         (20)                                              /*!< GPIO_T::SLEWCTL: HSREN10 Position      */
+#define GPIO_SLEWCTL_HSREN10_Msk         (0x3ul << GPIO_SLEWCTL_HSREN10_Pos)               /*!< GPIO_T::SLEWCTL: HSREN10 Mask          */
+
+#define GPIO_SLEWCTL_HSREN11_Pos         (22)                                              /*!< GPIO_T::SLEWCTL: HSREN11 Position      */
+#define GPIO_SLEWCTL_HSREN11_Msk         (0x3ul << GPIO_SLEWCTL_HSREN11_Pos)               /*!< GPIO_T::SLEWCTL: HSREN11 Mask          */
+
+#define GPIO_SLEWCTL_HSREN12_Pos         (24)                                              /*!< GPIO_T::SLEWCTL: HSREN12 Position      */
+#define GPIO_SLEWCTL_HSREN12_Msk         (0x3ul << GPIO_SLEWCTL_HSREN12_Pos)               /*!< GPIO_T::SLEWCTL: HSREN12 Mask          */
+
+#define GPIO_SLEWCTL_HSREN13_Pos         (26)                                              /*!< GPIO_T::SLEWCTL: HSREN13 Position      */
+#define GPIO_SLEWCTL_HSREN13_Msk         (0x3ul << GPIO_SLEWCTL_HSREN13_Pos)               /*!< GPIO_T::SLEWCTL: HSREN13 Mask          */
+
+#define GPIO_SLEWCTL_HSREN14_Pos         (28)                                              /*!< GPIO_T::SLEWCTL: HSREN14 Position      */
+#define GPIO_SLEWCTL_HSREN14_Msk         (0x3ul << GPIO_SLEWCTL_HSREN14_Pos)               /*!< GPIO_T::SLEWCTL: HSREN14 Mask          */
+
+#define GPIO_SLEWCTL_HSREN15_Pos         (30)                                              /*!< GPIO_T::SLEWCTL: HSREN15 Position      */
+#define GPIO_SLEWCTL_HSREN15_Msk         (0x3ul << GPIO_SLEWCTL_HSREN15_Pos)               /*!< GPIO_T::SLEWCTL: HSREN15 Mask          */
+
+#define GPIO_PUSEL_PUSEL0_Pos            (0)                                               /*!< GPIO_T::PUSEL: PUSEL0 Position         */
+#define GPIO_PUSEL_PUSEL0_Msk            (0x3ul << GPIO_PUSEL_PUSEL0_Pos)                  /*!< GPIO_T::PUSEL: PUSEL0 Mask             */
+
+#define GPIO_PUSEL_PUSEL1_Pos            (2)                                               /*!< GPIO_T::PUSEL: PUSEL1 Position         */
+#define GPIO_PUSEL_PUSEL1_Msk            (0x3ul << GPIO_PUSEL_PUSEL1_Pos)                  /*!< GPIO_T::PUSEL: PUSEL1 Mask             */
+
+#define GPIO_PUSEL_PUSEL2_Pos            (4)                                               /*!< GPIO_T::PUSEL: PUSEL2 Position         */
+#define GPIO_PUSEL_PUSEL2_Msk            (0x3ul << GPIO_PUSEL_PUSEL2_Pos)                  /*!< GPIO_T::PUSEL: PUSEL2 Mask             */
+
+#define GPIO_PUSEL_PUSEL3_Pos            (6)                                               /*!< GPIO_T::PUSEL: PUSEL3 Position         */
+#define GPIO_PUSEL_PUSEL3_Msk            (0x3ul << GPIO_PUSEL_PUSEL3_Pos)                  /*!< GPIO_T::PUSEL: PUSEL3 Mask             */
+
+#define GPIO_PUSEL_PUSEL4_Pos            (8)                                               /*!< GPIO_T::PUSEL: PUSEL4 Position         */
+#define GPIO_PUSEL_PUSEL4_Msk            (0x3ul << GPIO_PUSEL_PUSEL4_Pos)                  /*!< GPIO_T::PUSEL: PUSEL4 Mask             */
+
+#define GPIO_PUSEL_PUSEL5_Pos            (10)                                              /*!< GPIO_T::PUSEL: PUSEL5 Position         */
+#define GPIO_PUSEL_PUSEL5_Msk            (0x3ul << GPIO_PUSEL_PUSEL5_Pos)                  /*!< GPIO_T::PUSEL: PUSEL5 Mask             */
+
+#define GPIO_PUSEL_PUSEL6_Pos            (12)                                              /*!< GPIO_T::PUSEL: PUSEL6 Position         */
+#define GPIO_PUSEL_PUSEL6_Msk            (0x3ul << GPIO_PUSEL_PUSEL6_Pos)                  /*!< GPIO_T::PUSEL: PUSEL6 Mask             */
+
+#define GPIO_PUSEL_PUSEL7_Pos            (14)                                              /*!< GPIO_T::PUSEL: PUSEL7 Position         */
+#define GPIO_PUSEL_PUSEL7_Msk            (0x3ul << GPIO_PUSEL_PUSEL7_Pos)                  /*!< GPIO_T::PUSEL: PUSEL7 Mask             */
+
+#define GPIO_PUSEL_PUSEL8_Pos            (16)                                              /*!< GPIO_T::PUSEL: PUSEL8 Position         */
+#define GPIO_PUSEL_PUSEL8_Msk            (0x3ul << GPIO_PUSEL_PUSEL8_Pos)                  /*!< GPIO_T::PUSEL: PUSEL8 Mask             */
+
+#define GPIO_PUSEL_PUSEL9_Pos            (18)                                              /*!< GPIO_T::PUSEL: PUSEL9 Position         */
+#define GPIO_PUSEL_PUSEL9_Msk            (0x3ul << GPIO_PUSEL_PUSEL9_Pos)                  /*!< GPIO_T::PUSEL: PUSEL9 Mask             */
+
+#define GPIO_PUSEL_PUSEL10_Pos           (20)                                              /*!< GPIO_T::PUSEL: PUSEL10 Position        */
+#define GPIO_PUSEL_PUSEL10_Msk           (0x3ul << GPIO_PUSEL_PUSEL10_Pos)                 /*!< GPIO_T::PUSEL: PUSEL10 Mask            */
+
+#define GPIO_PUSEL_PUSEL11_Pos           (22)                                              /*!< GPIO_T::PUSEL: PUSEL11 Position        */
+#define GPIO_PUSEL_PUSEL11_Msk           (0x3ul << GPIO_PUSEL_PUSEL11_Pos)                 /*!< GPIO_T::PUSEL: PUSEL11 Mask            */
+
+#define GPIO_PUSEL_PUSEL12_Pos           (24)                                              /*!< GPIO_T::PUSEL: PUSEL12 Position        */
+#define GPIO_PUSEL_PUSEL12_Msk           (0x3ul << GPIO_PUSEL_PUSEL12_Pos)                 /*!< GPIO_T::PUSEL: PUSEL12 Mask            */
+
+#define GPIO_PUSEL_PUSEL13_Pos           (26)                                              /*!< GPIO_T::PUSEL: PUSEL13 Position        */
+#define GPIO_PUSEL_PUSEL13_Msk           (0x3ul << GPIO_PUSEL_PUSEL13_Pos)                 /*!< GPIO_T::PUSEL: PUSEL13 Mask            */
+
+#define GPIO_PUSEL_PUSEL14_Pos           (28)                                              /*!< GPIO_T::PUSEL: PUSEL14 Position        */
+#define GPIO_PUSEL_PUSEL14_Msk           (0x3ul << GPIO_PUSEL_PUSEL14_Pos)                 /*!< GPIO_T::PUSEL: PUSEL14 Mask            */
+
+#define GPIO_PUSEL_PUSEL15_Pos           (30)                                              /*!< GPIO_T::PUSEL: PUSEL15 Position        */
+#define GPIO_PUSEL_PUSEL15_Msk           (0x3ul << GPIO_PUSEL_PUSEL15_Pos)                 /*!< GPIO_T::PUSEL: PUSEL15 Mask            */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos          (0)                                               /*!< GPIO_T::DBCTL: DBCLKSEL Position          */
+#define GPIO_DBCTL_DBCLKSEL_Msk          (0xFul << GPIO_DBCTL_DBCLKSEL_Pos)                /*!< GPIO_T::DBCTL: DBCLKSEL Mask              */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos          (4)                                               /*!< GPIO_T::DBCTL: DBCLKSRC Position          */
+#define GPIO_DBCTL_DBCLKSRC_Msk          (1ul << GPIO_DBCTL_DBCLKSRC_Pos)                  /*!< GPIO_T::DBCTL: DBCLKSRC Mask              */
+
+#define GPIO_DBCTL_ICLKON_Pos            (5)                                               /*!< GPIO_T::DBCTL: ICLKON Position            */
+#define GPIO_DBCTL_ICLKON_Msk            (1ul << GPIO_DBCTL_ICLKON_Pos)                    /*!< GPIO_T::DBCTL: ICLKON Mask                */
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+
+
+
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
+/**
+    @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
+    Memory Mapped Structure for PDMA Controller
+@{ */
+
+
+typedef struct {
+
+    /**
+     * @var DSCT_T::CTL
+     * Offset: 0x00  Descriptor Table Control Register of PDMA Channel n.
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE    |PDMA Operation Mode Selection
+     * |        |          |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
+     * |        |          |01 = Basic mode: The descriptor table only has one task
+     * |        |          |When this task is finished, the PDMA_INTSTS[n] will be asserted.
+     * |        |          |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
+     * |[2]     |TXTYPE    |Transfer Type
+     * |        |          |0 = Burst transfer type.
+     * |        |          |1 = Single transfer type.
+     * |[6:4]   |BURSIZE   |Burst Size
+     * |        |          |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
+     * |        |          |000 = 128 Transfers.
+     * |        |          |001 = 64 Transfers.
+     * |        |          |010 = 32 Transfers.
+     * |        |          |011 = 16 Transfers.
+     * |        |          |100 = 8 Transfers.
+     * |        |          |101 = 4 Transfers.
+     * |        |          |110 = 2 Transfers.
+     * |        |          |111 = 1 Transfers.
+     * |        |          |Note: This field is only useful in burst transfer type.
+     * |[7]     |TBINTDIS  |Table Interrupt Disable Bit
+     * |        |          |This field can be used to decide whether to enable table interrupt or not
+     * |        |          |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
+     * |        |          |0 = Table interrupt Enabled.
+     * |        |          |1 = Table interrupt Disabled.
+     * |[9:8]   |SAINC     |Source Address Increment
+     * |        |          |This field is used to set the source address increment size.
+     * |        |          |11 = No increment (fixed address).
+     * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+     * |[11:10] |DAINC     |Destination Address Increment
+     * |        |          |This field is used to set the destination address increment size.
+     * |        |          |11 = No increment (fixed address).
+     * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+     * |[13:12] |TXWIDTH   |Transfer Width Selection
+     * |        |          |This field is used for transfer width.
+     * |        |          |00 = One byte (8 bit) is transferred for every operation.
+     * |        |          |01= One half-word (16 bit) is transferred for every operation.
+     * |        |          |10 = One word (32-bit) is transferred for every operation.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
+     * |[14]    |TXACK     |Transfer Acknowledge Selection
+     * |        |          |0 = transfer ack when transfer done.
+     * |        |          |1 = transfer ack when PDMA get transfer data.
+     * |[15]    |STRIDEEN |Stride Mode Enable Bit
+     * |        |          |0 = Stride transfer mode Disabled.
+     * |        |          |1 = Stride transfer mode Enabled.
+     * |[31:16] |TXCNT     |Transfer Count
+     * |        |          |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
+     * |        |          |Note: When PDMA finish each transfer data, this field will be decrease immediately.
+     * @var DSCT_T::SA
+     * Offset: 0x04  Source Address Register of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SA        |PDMA Transfer Source Address Register
+     * |        |          |This field indicates a 32-bit source address of PDMA controller.
+     * @var DSCT_T::DA
+     * Offset: 0x08  Destination Address Register of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DA        |PDMA Transfer Destination Address Register
+     * |        |          |This field indicates a 32-bit destination address of PDMA controller.
+     * @var DSCT_T::NEXT
+     * Offset: 0x0C  Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |EXENEXT   |PDMA Execution Next Descriptor Table Offset
+     * |        |          |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
+     * |        |          |Note: write operation is useless in this field.
+     * |[31:16] |NEXT      |PDMA Next Descriptor Table Offset.
+     * |        |          |This field indicates the offset of the next descriptor table address in system memory.
+     * |        |          |Write Operation:
+     * |        |          |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
+     * |        |          |Read Operation:
+     * |        |          |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
+     * |        |          |Note1: The descriptor table address must be word boundary.
+     * |        |          |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
+     */
+    __IO uint32_t CTL;             /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n.             */
+    __IO uint32_t SA;              /*!< [0x0004] Source Address Register of PDMA Channel n                        */
+    __IO uint32_t DA;              /*!< [0x0008] Destination Address Register of PDMA Channel n                   */
+    __IO uint32_t NEXT;            /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */
+} DSCT_T;
+
+
+typedef struct {
+    /**
+     * @var STRIDE_T::STCR
+     * Offset: 0x500  Stride Transfer Count Register of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |STC       |PDMA Stride Transfer Count
+     * |        |          |The 16-bit register defines the stride transfer count of each row.
+     * @var STRIDE_T::ASOCR
+     * Offset: 0x504  Address Stride Offset Register of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |SASOL     |VDMA Source Address Stride Offset Length
+     * |        |          |The 16-bit register defines the source address stride transfer offset count of each row.
+     * |[31:16] |DASOL     |VDMA Destination Address Stride Offset Length
+     * |        |          |The 16-bit register defines the destination address stride transfer offset count of each row.
+     */
+    __IO uint32_t STCR;           /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0                 */
+    __IO uint32_t ASOCR;          /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0                 */
+} STRIDE_T;
+
+typedef struct {
+
+
+    /**
+     * @var PDMA_T::CURSCAT
+     * Offset: 0x100  Current Scatter-Gather Descriptor Table Address of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURADDR   |PDMA Current Description Address Register (Read Only)
+     * |        |          |This field indicates a 32-bit current external description address of PDMA controller.
+     * |        |          |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
+     * @var PDMA_T::CHCTL
+     * Offset: 0x400  PDMA Channel Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CHENn     |PDMA Channel Enable Bit
+     * |        |          |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
+     * |        |          |0 = PDMA channel [n] Disabled.
+     * |        |          |1 = PDMA channel [n] Enabled.
+     * |        |          |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
+     * @var PDMA_T::PAUSE
+     * Offset: 0x404  PDMA Transfer Stop Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PAUSEn    |PDMA Transfer Pause Control Register (Write Only)
+     * |        |          |User can set PAUSEn bit field to pause the PDMA transfer
+     * |        |          |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
+     * |        |          |If re-enable the paused channel again, the remaining transfers will be processed.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Pause PDMA channel n transfer.
+     * @var PDMA_T::SWREQ
+     * Offset: 0x408  PDMA Software Request Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |SWREQn    |PDMA Software Request Register (Write Only)
+     * |        |          |Set this bit to 1 to generate a software request to PDMA [n].
+     * |        |          |0 = No effect.
+     * |        |          |1 = Generate a software request.
+     * |        |          |Note1: User can read PDMA_TRGSTS register to know which channel is on active
+     * |        |          |Active flag may be triggered by software request or peripheral request.
+     * |        |          |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
+     * @var PDMA_T::TRGSTS
+     * Offset: 0x40C  PDMA Channel Request Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |REQSTSn   |PDMA Channel Request Status (Read Only)
+     * |        |          |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
+     * |        |          |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
+     * |        |          |0 = PDMA Channel n has no request.
+     * |        |          |1 = PDMA Channel n has a request.
+     * |        |          |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
+     * @var PDMA_T::PRISET
+     * Offset: 0x410  PDMA Fixed Priority Setting Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FPRISETn  |PDMA Fixed Priority Setting Register
+     * |        |          |Set this bit to 1 to enable fixed priority level.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set PDMA channel [n] to fixed priority channel.
+     * |        |          |Read Operation:
+     * |        |          |0 = Corresponding PDMA channel is round-robin priority.
+     * |        |          |1 = Corresponding PDMA channel is fixed priority.
+     * |        |          |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
+     * @var PDMA_T::PRICLR
+     * Offset: 0x414  PDMA Fixed Priority Clear Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FPRICLRn  |PDMA Fixed Priority Clear Register (Write Only)
+     * |        |          |Set this bit to 1 to clear fixed priority level.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear PDMA channel [n] fixed priority setting.
+     * |        |          |Note: User can read PDMA_PRISET register to know the channel priority.
+     * @var PDMA_T::INTEN
+     * Offset: 0x418  PDMA Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |INTENn    |PDMA Interrupt Enable Register
+     * |        |          |This field is used for enabling PDMA channel[n] interrupt.
+     * |        |          |0 = PDMA channel n interrupt Disabled.
+     * |        |          |1 = PDMA channel n interrupt Enabled.
+     * @var PDMA_T::INTSTS
+     * Offset: 0x41C  PDMA Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABTIF     |PDMA Read/Write Target Abort Interrupt Flag (Read-only)
+     * |        |          |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
+     * |        |          |0 = No AHB bus ERROR response received.
+     * |        |          |1 = AHB bus ERROR response received.
+     * |[1]     |TDIF      |Transfer Done Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
+     * |        |          |0 = Not finished yet.
+     * |        |          |1 = PDMA channel has finished transmission.
+     * |[2]     |ALIGNF    |Transfer Alignment Interrupt Flag (Read Only)
+     * |        |          |0 = PDMA channel source address and destination address both follow transfer width setting.
+     * |        |          |1 = PDMA channel source address or destination address is not follow transfer width setting.
+     * |[8]     |REQTOF0   |Request Time-out Flag for Channel 0
+     * |        |          |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
+     * |        |          |0 = No request time-out.
+     * |        |          |1 = Peripheral request time-out.
+     * |[9]     |REQTOF1   |Request Time-out Flag for Channel 1
+     * |        |          |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
+     * |        |          |0 = No request time-out.
+     * |        |          |1 = Peripheral request time-out.
+     * @var PDMA_T::ABTSTS
+     * Offset: 0x420  PDMA Channel Read/Write Target Abort Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ABTIFn    |PDMA Read/Write Target Abort Interrupt Status Flag
+     * |        |          |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
+     * |        |          |0 = No AHB bus ERROR response received when channel n transfer.
+     * |        |          |1 = AHB bus ERROR response received when channel n transfer.
+     * @var PDMA_T::TDSTS
+     * Offset: 0x424  PDMA Channel Transfer Done Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TDIFn     |Transfer Done Flag Register
+     * |        |          |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
+     * |        |          |0 = PDMA channel transfer has not finished.
+     * |        |          |1 = PDMA channel has finished transmission.
+     * @var PDMA_T::ALIGN
+     * Offset: 0x428  PDMA Transfer Alignment Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ALIGNn    |Transfer Alignment Flag Register
+     * |        |          |0 = PDMA channel source address and destination address both follow transfer width setting.
+     * |        |          |1 = PDMA channel source address or destination address is not follow transfer width setting.
+     * @var PDMA_T::TACTSTS
+     * Offset: 0x42C  PDMA Transfer Active Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXACTFn   |Transfer on Active Flag Register (Read Only)
+     * |        |          |This bit indicates which PDMA channel is in active.
+     * |        |          |0 = PDMA channel is not finished.
+     * |        |          |1 = PDMA channel is active.
+     * @var PDMA_T::TOUTPSC
+     * Offset: 0x430  PDMA Time-out Prescaler Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TOUTPSC0  |PDMA Channel 0 Time-out Clock Source Prescaler Bits
+     * |        |          |000 = PDMA channel 0 time-out clock source is HCLK/28.
+     * |        |          |001 = PDMA channel 0 time-out clock source is HCLK/29.
+     * |        |          |010 = PDMA channel 0 time-out clock source is HCLK/210.
+     * |        |          |011 = PDMA channel 0 time-out clock source is HCLK/211.
+     * |        |          |100 = PDMA channel 0 time-out clock source is HCLK/212.
+     * |        |          |101 = PDMA channel 0 time-out clock source is HCLK/213.
+     * |        |          |110 = PDMA channel 0 time-out clock source is HCLK/214.
+     * |        |          |111 = PDMA channel 0 time-out clock source is HCLK/215.
+     * |[6:4]   |TOUTPSC1  |PDMA Channel 1 Time-out Clock Source Prescaler Bits
+     * |        |          |000 = PDMA channel 1 time-out clock source is HCLK/28.
+     * |        |          |001 = PDMA channel 1 time-out clock source is HCLK/29.
+     * |        |          |010 = PDMA channel 1 time-out clock source is HCLK/210.
+     * |        |          |011 = PDMA channel 1 time-out clock source is HCLK/211.
+     * |        |          |100 = PDMA channel 1 time-out clock source is HCLK/212.
+     * |        |          |101 = PDMA channel 1 time-out clock source is HCLK/213.
+     * |        |          |110 = PDMA channel 1 time-out clock source is HCLK/214.
+     * |        |          |111 = PDMA channel 1 time-out clock source is HCLK/215.
+     * @var PDMA_T::TOUTEN
+     * Offset: 0x434  PDMA Time-out Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |TOUTENn   |PDMA Time-out Enable Bits
+     * |        |          |0 = PDMA Channel n time-out function Disable.
+     * |        |          |1 = PDMA Channel n time-out function Enable.
+     * @var PDMA_T::TOUTIEN
+     * Offset: 0x438  PDMA Time-out Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |TOUTIENn  |PDMA Time-out Interrupt Enable Bits
+     * |        |          |0 = PDMA Channel n time-out interrupt Disable.
+     * |        |          |1 = PDMA Channel n time-out interrupt Enable.
+     * @var PDMA_T::SCATBA
+     * Offset: 0x43C  PDMA Scatter-Gather Descriptor Table Base Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:16] |SCATBA    |PDMA Scatter-gather Descriptor Table Address Register
+     * |        |          |In Scatter-Gather mode, this is the base address for calculating the next link - list address
+     * |        |          |The next link address equation is
+     * |        |          |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
+     * |        |          |Note: Only useful in Scatter-Gather mode.
+     * @var PDMA_T::TOC0_1
+     * Offset: 0x440  PDMA Time-out Counter Ch1 and Ch0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TOC0      |Time-out Counter for Channel 0
+     * |        |          |This controls the period of time-out function for channel 0
+     * |        |          |The calculation unit is based on 10 kHz clock.
+     * |[31:16] |TOC1      |Time-out Counter for Channel 1
+     * |        |          |This controls the period of time-out function for channel 1
+     * |        |          |The calculation unit is based on 10 kHz clock.
+     * @var PDMA_T::CHRST
+     * Offset: 0x460  PDMA Channel Reset Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CHnRST    |Channel N Reset
+     * |        |          |0 = corresponding channel n not reset.
+     * |        |          |1 = corresponding channel n is reset.
+     * @var PDMA_T::REQSEL0_3
+     * Offset: 0x480  PDMA Request Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC0   |Channel 0 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 0
+     * |        |          |User can configure the peripheral by setting REQSRC0.
+     * |        |          |0 = Disable PDMA peripheral request.
+     * |        |          |1 = Reserved.
+     * |        |          |2 = Channel connects to USB_TX.
+     * |        |          |3 = Channel connects to USB_RX.
+     * |        |          |4 = Channel connects to UART0_TX.
+     * |        |          |5 = Channel connects to UART0_RX.
+     * |        |          |6 = Channel connects to UART1_TX.
+     * |        |          |7 = Channel connects to UART1_RX.
+     * |        |          |8 = Channel connects to UART2_TX.
+     * |        |          |9 = Channel connects to UART2_RX.
+     * |        |          |10=Channel connects to UART3_TX.
+     * |        |          |11 = Channel connects to UART3_RX.
+     * |        |          |12 = Channel connects to UART4_TX.
+     * |        |          |13 = Channel connects to UART4_RX.
+     * |        |          |14 = Channel connects to UART5_TX.
+     * |        |          |15 = Channel connects to UART5_RX.
+     * |        |          |16 = Channel connects to USCI0_TX.
+     * |        |          |17 = Channel connects to USCI0_RX.
+     * |        |          |18 = Channel connects to USCI1_TX.
+     * |        |          |19 = Channel connects to USCI1_RX.
+     * |        |          |20 = Channel connects to SPI0_TX.
+     * |        |          |21 = Channel connects to SPI0_RX.
+     * |        |          |22 = Channel connects to SPI1_TX.
+     * |        |          |23 = Channel connects to SPI1_RX.
+     * |        |          |24 = Channel connects to SPI2_TX.
+     * |        |          |25 = Channel connects to SPI2_RX.
+     * |        |          |26 = Channel connects to SPI3_TX.
+     * |        |          |27 = Channel connects to SPI3_RX.
+     * |        |          |28 = Channel connects to SPI4_TX.
+     * |        |          |29 = Channel connects to SPI4_RX.
+     * |        |          |30 = Reserved.
+     * |        |          |31 = Reserved.
+     * |        |          |32 = Channel connects to EPWM0_P1_RX.
+     * |        |          |33 = Channel connects to EPWM0_P2_RX.
+     * |        |          |34 = Channel connects to EPWM0_P3_RX.
+     * |        |          |35 = Channel connects to EPWM1_P1_RX.
+     * |        |          |36 = Channel connects to EPWM1_P2_RX.
+     * |        |          |37 = Channel connects to EPWM1_P3_RX.
+     * |        |          |38 = Channel connects to I2C0_TX.
+     * |        |          |39 = Channel connects to I2C0_RX.
+     * |        |          |40 = Channel connects to I2C1_TX.
+     * |        |          |41 = Channel connects to I2C1_RX.
+     * |        |          |42 = Channel connects to I2C2_TX.
+     * |        |          |43 = Channel connects to I2C2_RX.
+     * |        |          |44 = Channel connects to I2S0_TX.
+     * |        |          |45 = Channel connects to I2S0_RX.
+     * |        |          |46 = Channel connects to TMR0.
+     * |        |          |47 = Channel connects to TMR1.
+     * |        |          |48 = Channel connects to TMR2.
+     * |        |          |49 = Channel connects to TMR3.
+     * |        |          |50 = Channel connects to ADC_RX.
+     * |        |          |51 = Channel connects to DAC0_TX.
+     * |        |          |52 = Channel connects to DAC1_TX.
+     * |        |          |53 = Channel connects to EPWM0_CH0_TX.
+     * |        |          |54 = Channel connects to EPWM0_CH1_TX.
+     * |        |          |55 = Channel connects to EPWM0_CH2_TX.
+     * |        |          |56 = Channel connects to EPWM0_CH3_TX.
+     * |        |          |57 = Channel connects to EPWM0_CH4_TX.
+     * |        |          |58 = Channel connects to EPWM0_CH5_TX.
+     * |        |          |59 = Channel connects to EPWM1_CH0_TX.
+     * |        |          |60 = Channel connects to EPWM1_CH1_TX.
+     * |        |          |61 = Channel connects to EPWM1_CH2_TX.
+     * |        |          |62 = Channel connects to EPWM1_CH3_TX.
+     * |        |          |63 = Channel connects to EPWM1_CH4_TX.
+     * |        |          |64 = Channel connects to EPWM1_CH5_TX.
+     * |        |          |65 = Channel connects to ETMC_RX.
+     * |        |          |Others = Reserved.
+     * |        |          |Note 1: A peripheral can't assign to two channels at the same time.
+     * |        |          |Note 2: This field is useless when transfer between memory and memory.
+     * |[14:8]  |REQSRC1   |Channel 1 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 1
+     * |        |          |User can configure the peripheral setting by REQSRC1.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC2   |Channel 2 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 2
+     * |        |          |User can configure the peripheral setting by REQSRC2.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC3   |Channel 3 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 3
+     * |        |          |User can configure the peripheral setting by REQSRC3.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * @var PDMA_T::REQSEL4_7
+     * Offset: 0x484  PDMA Request Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC4   |Channel 4 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 4
+     * |        |          |User can configure the peripheral setting by REQSRC4.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[14:8]  |REQSRC5   |Channel 5 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 5
+     * |        |          |User can configure the peripheral setting by REQSRC5.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC6   |Channel 6 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 6
+     * |        |          |User can configure the peripheral setting by REQSRC6.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC7   |Channel 7 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 7
+     * |        |          |User can configure the peripheral setting by REQSRC7.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * @var PDMA_T::REQSEL8_11
+     * Offset: 0x488  PDMA Request Source Select Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC8   |Channel 8 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 8
+     * |        |          |User can configure the peripheral setting by REQSRC8.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[14:8]  |REQSRC9   |Channel 9 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 9
+     * |        |          |User can configure the peripheral setting by REQSRC9.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC10  |Channel 10 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 10
+     * |        |          |User can configure the peripheral setting by REQSRC10.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC11  |Channel 11 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 11
+     * |        |          |User can configure the peripheral setting by REQSRC11.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * @var PDMA_T::REQSEL12_15
+     * Offset: 0x48C  PDMA Request Source Select Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC12  |Channel 12 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 12
+     * |        |          |User can configure the peripheral setting by REQSRC12.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[14:8]  |REQSRC13  |Channel 13 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 13
+     * |        |          |User can configure the peripheral setting by REQSRC13.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC14  |Channel 14 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 14
+     * |        |          |User can configure the peripheral setting by REQSRC14.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC15  |Channel 15 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 15
+     * |        |          |User can configure the peripheral setting by REQSRC15.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     */
+    DSCT_T DSCT[16];
+    __I  uint32_t CURSCAT[16];              /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[176];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CHCTL;                 /*!< [0x0400] PDMA Channel Control Register                                    */
+    __O  uint32_t PAUSE;                 /*!< [0x0404] PDMA Transfer Pause Control Register                              */
+    __O  uint32_t SWREQ;                 /*!< [0x0408] PDMA Software Request Register                                   */
+    __I  uint32_t TRGSTS;                /*!< [0x040c] PDMA Channel Request Status Register                             */
+    __IO uint32_t PRISET;                /*!< [0x0410] PDMA Fixed Priority Setting Register                             */
+    __O  uint32_t PRICLR;                /*!< [0x0414] PDMA Fixed Priority Clear Register                               */
+    __IO uint32_t INTEN;                 /*!< [0x0418] PDMA Interrupt Enable Register                                   */
+    __IO uint32_t INTSTS;                /*!< [0x041c] PDMA Interrupt Status Register                                   */
+    __IO uint32_t ABTSTS;                /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register               */
+    __IO uint32_t TDSTS;                 /*!< [0x0424] PDMA Channel Transfer Done Flag Register                         */
+    __IO uint32_t ALIGN;                 /*!< [0x0428] PDMA Transfer Alignment Status Register                          */
+    __I  uint32_t TACTSTS;               /*!< [0x042c] PDMA Transfer Active Flag Register                               */
+    __IO uint32_t TOUTPSC;               /*!< [0x0430] PDMA Time-out Prescaler Register                                 */
+    __IO uint32_t TOUTEN;                /*!< [0x0434] PDMA Time-out Enable Register                                    */
+    __IO uint32_t TOUTIEN;               /*!< [0x0438] PDMA Time-out Interrupt Enable Register                          */
+    __IO uint32_t SCATBA;                /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register       */
+    __IO uint32_t TOC0_1;                /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CHRST;                 /*!< [0x0460] PDMA Channel Reset Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t REQSEL0_3;             /*!< [0x0480] PDMA Request Source Select Register 0                            */
+    __IO uint32_t REQSEL4_7;             /*!< [0x0484] PDMA Request Source Select Register 1                            */
+    __IO uint32_t REQSEL8_11;            /*!< [0x0488] PDMA Request Source Select Register 2                            */
+    __IO uint32_t REQSEL12_15;           /*!< [0x048c] PDMA Request Source Select Register 3                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[28];
+    /// @endcond //HIDDEN_SYMBOLS
+    STRIDE_T     STRIDE[6];
+} PDMA_T;
+
+/**
+    @addtogroup PDMA_CONST PDMA Bit Field Definition
+    Constant Definitions for PDMA Controller
+@{ */
+
+#define PDMA_DSCT_CTL_OPMODE_Pos        (0)                                               /*!< PDMA_T::DSCT_CTL: OPMODE Position     */
+#define PDMA_DSCT_CTL_OPMODE_Msk        (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)               /*!< PDMA_T::DSCT_CTL: OPMODE Mask         */
+
+#define PDMA_DSCT_CTL_TXTYPE_Pos        (2)                                               /*!< PDMA_T::DSCT_CTL: TXTYPE Position     */
+#define PDMA_DSCT_CTL_TXTYPE_Msk        (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos)               /*!< PDMA_T::DSCT_CTL: TXTYPE Mask         */
+
+#define PDMA_DSCT_CTL_BURSIZE_Pos       (4)                                               /*!< PDMA_T::DSCT_CTL: BURSIZE Position    */
+#define PDMA_DSCT_CTL_BURSIZE_Msk       (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)              /*!< PDMA_T::DSCT_CTL: BURSIZE Mask        */
+
+#define PDMA_DSCT_CTL_TBINTDIS_Pos      (7)                                               /*!< PDMA_T::DSCT_CTL: TBINTDIS Position      */
+#define PDMA_DSCT_CTL_TBINTDIS_Msk      (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)             /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask          */
+
+#define PDMA_DSCT_CTL_SAINC_Pos         (8)                                               /*!< PDMA_T::DSCT_CTL: SAINC Position      */
+#define PDMA_DSCT_CTL_SAINC_Msk         (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)                /*!< PDMA_T::DSCT_CTL: SAINC Mask          */
+
+#define PDMA_DSCT_CTL_DAINC_Pos         (10)                                              /*!< PDMA_T::DSCT_CTL: DAINC Position      */
+#define PDMA_DSCT_CTL_DAINC_Msk         (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)                /*!< PDMA_T::DSCT_CTL: DAINC Mask          */
+
+#define PDMA_DSCT_CTL_TXWIDTH_Pos       (12)                                              /*!< PDMA_T::DSCT_CTL: TXWIDTH Position    */
+#define PDMA_DSCT_CTL_TXWIDTH_Msk       (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)              /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask        */
+
+#define PDMA_DSCT_CTL_TXACK_Pos         (14)                                              /*!< PDMA_T::DSCT_CTL: TXACK Position      */
+#define PDMA_DSCT_CTL_TXACK_Msk         (0x1ul << PDMA_DSCT_CTL_TXACK_Pos)                /*!< PDMA_T::DSCT_CTL: TXACK Mask          */
+
+#define PDMA_DSCT_CTL_STRIDEEN_Pos     (15)                                               /*!< PDMA_T::DSCT_CTL: STRIDEEN Position  */
+#define PDMA_DSCT_CTL_STRIDEEN_Msk     (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos)              /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask      */
+
+#define PDMA_DSCT_CTL_TXCNT_Pos         (16)                                              /*!< PDMA_T::DSCT_CTL: TXCNT Position      */
+#define PDMA_DSCT_CTL_TXCNT_Msk         (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos)             /*!< PDMA_T::DSCT_CTL: TXCNT Mask          */
+
+#define PDMA_DSCT_SA_SA_Pos             (0)                                               /*!< PDMA_T::DSCT_SA: SA Position          */
+#define PDMA_DSCT_SA_SA_Msk             (0xfffffffful << PDMA_DSCT_SA_SA_Pos)             /*!< PDMA_T::DSCT_SA: SA Mask              */
+
+#define PDMA_DSCT_DA_DA_Pos             (0)                                               /*!< PDMA_T::DSCT_DA: DA Position          */
+#define PDMA_DSCT_DA_DA_Msk             (0xfffffffful << PDMA_DSCT_DA_DA_Pos)             /*!< PDMA_T::DSCT_DA: DA Mask              */
+
+#define PDMA_DSCT_NEXT_NEXT_Pos         (0)                                               /*!< PDMA_T::DSCT_NEXT: NEXT Position      */
+#define PDMA_DSCT_NEXT_NEXT_Msk         (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos)             /*!< PDMA_T::DSCT_NEXT: NEXT Mask          */
+
+#define PDMA_DSCT_NEXT_EXENEXT_Pos      (16)                                              /*!< PDMA_T::DSCT_FIRST: NEXT Position     */
+#define PDMA_DSCT_NEXT_EXENEXT_Msk      (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos)           /*!< PDMA_T::DSCT_FIRST: NEXT Mask         */
+
+#define PDMA_CURSCAT_CURADDR_Pos        (0)                                               /*!< PDMA_T::CURSCAT: CURADDR Position     */
+#define PDMA_CURSCAT_CURADDR_Msk        (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)        /*!< PDMA_T::CURSCAT: CURADDR Mask         */
+
+#define PDMA_CHCTL_CHENn_Pos            (0)                                               /*!< PDMA_T::CHCTL: CHENn Position          */
+#define PDMA_CHCTL_CHENn_Msk            (0xfffful << PDMA_CHCTL_CHENn_Pos)                /*!< PDMA_T::CHCTL: CHENn Mask              */
+
+#define PDMA_PAUSE_PAUSEn_Pos           (0)                                               /*!< PDMA_T::PAUSE: PAUSEn Position           */
+#define PDMA_PAUSE_PAUSEn_Msk           (0xfffful << PDMA_PAUSE_PAUSEn_Pos)              /*!< PDMA_T::PAUSE: PAUSEn Mask               */
+
+#define PDMA_SWREQ_SWREQn_Pos            (0)                                               /*!< PDMA_T::SWREQ: SWREQn Position         */
+#define PDMA_SWREQ_SWREQn_Msk            (0xfffful << PDMA_SWREQ_SWREQn_Pos)               /*!< PDMA_T::SWREQ: SWREQn Mask             */
+
+#define PDMA_TRGSTS_REQSTSn_Pos          (0)                                               /*!< PDMA_T::TRGSTS: REQSTSn Position       */
+#define PDMA_TRGSTS_REQSTSn_Msk          (0xfffful << PDMA_TRGSTS_REQSTSn_Pos)             /*!< PDMA_T::TRGSTS: REQSTSn Mask           */
+
+#define PDMA_PRISET_FPRISETn_Pos         (0)                                               /*!< PDMA_T::PRISET: FPRISETn Position      */
+#define PDMA_PRISET_FPRISETn_Msk         (0xfffful << PDMA_PRISET_FPRISETn_Pos)            /*!< PDMA_T::PRISET: FPRISETn Mask          */
+
+#define PDMA_PRICLR_FPRICLRn_Pos         (0)                                               /*!< PDMA_T::PRICLR: FPRICLRn Position      */
+#define PDMA_PRICLR_FPRICLRn_Msk         (0xfffful << PDMA_PRICLR_FPRICLRn_Pos)            /*!< PDMA_T::PRICLR: FPRICLRn Mask          */
+
+#define PDMA_INTEN_INTENn_Pos            (0)                                               /*!< PDMA_T::INTEN: INTENn Position         */
+#define PDMA_INTEN_INTENn_Msk            (0xfffful << PDMA_INTEN_INTENn_Pos)               /*!< PDMA_T::INTEN: INTENn Mask             */
+
+#define PDMA_INTSTS_ABTIF_Pos            (0)                                               /*!< PDMA_T::INTSTS: ABTIF Position         */
+#define PDMA_INTSTS_ABTIF_Msk            (0x1ul << PDMA_INTSTS_ABTIF_Pos)                  /*!< PDMA_T::INTSTS: ABTIF Mask             */
+
+#define PDMA_INTSTS_TDIF_Pos             (1)                                               /*!< PDMA_T::INTSTS: TDIF Position          */
+#define PDMA_INTSTS_TDIF_Msk             (0x1ul << PDMA_INTSTS_TDIF_Pos)                   /*!< PDMA_T::INTSTS: TDIF Mask              */
+
+#define PDMA_INTSTS_ALIGNF_Pos           (2)                                               /*!< PDMA_T::INTSTS: ALIGNF Position        */
+#define PDMA_INTSTS_ALIGNF_Msk           (0x1ul << PDMA_INTSTS_ALIGNF_Pos)                 /*!< PDMA_T::INTSTS: ALIGNF Mask            */
+
+#define PDMA_INTSTS_REQTOF0_Pos          (8)                                               /*!< PDMA_T::INTSTS: REQTOF0 Position       */
+#define PDMA_INTSTS_REQTOF0_Msk          (0x1ul << PDMA_INTSTS_REQTOF0_Pos)                /*!< PDMA_T::INTSTS: REQTOF0 Mask           */
+
+#define PDMA_INTSTS_REQTOF1_Pos          (9)                                               /*!< PDMA_T::INTSTS: REQTOF1 Position       */
+#define PDMA_INTSTS_REQTOF1_Msk          (0x1ul << PDMA_INTSTS_REQTOF1_Pos)                /*!< PDMA_T::INTSTS: REQTOF1 Mask           */
+
+#define PDMA_ABTSTS_ABTIF0_Pos           (0)                                               /*!< PDMA_T::ABTSTS: ABTIF0 Position        */
+#define PDMA_ABTSTS_ABTIF0_Msk           (0x1ul << PDMA_ABTSTS_ABTIF0_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF0 Mask            */
+
+#define PDMA_ABTSTS_ABTIF1_Pos           (1)                                               /*!< PDMA_T::ABTSTS: ABTIF1 Position        */
+#define PDMA_ABTSTS_ABTIF1_Msk           (0x1ul << PDMA_ABTSTS_ABTIF1_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF1 Mask            */
+
+#define PDMA_ABTSTS_ABTIF2_Pos           (2)                                               /*!< PDMA_T::ABTSTS: ABTIF2 Position        */
+#define PDMA_ABTSTS_ABTIF2_Msk           (0x1ul << PDMA_ABTSTS_ABTIF2_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF2 Mask            */
+
+#define PDMA_ABTSTS_ABTIF3_Pos           (3)                                               /*!< PDMA_T::ABTSTS: ABTIF3 Position        */
+#define PDMA_ABTSTS_ABTIF3_Msk           (0x1ul << PDMA_ABTSTS_ABTIF3_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF3 Mask            */
+
+#define PDMA_ABTSTS_ABTIF4_Pos           (4)                                               /*!< PDMA_T::ABTSTS: ABTIF4 Position        */
+#define PDMA_ABTSTS_ABTIF4_Msk           (0x1ul << PDMA_ABTSTS_ABTIF4_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF4 Mask            */
+
+#define PDMA_ABTSTS_ABTIF5_Pos           (5)                                               /*!< PDMA_T::ABTSTS: ABTIF5 Position        */
+#define PDMA_ABTSTS_ABTIF5_Msk           (0x1ul << PDMA_ABTSTS_ABTIF5_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF5 Mask            */
+
+#define PDMA_ABTSTS_ABTIF6_Pos           (6)                                               /*!< PDMA_T::ABTSTS: ABTIF6 Position        */
+#define PDMA_ABTSTS_ABTIF6_Msk           (0x1ul << PDMA_ABTSTS_ABTIF6_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF6 Mask            */
+
+#define PDMA_ABTSTS_ABTIF7_Pos           (7)                                               /*!< PDMA_T::ABTSTS: ABTIF7 Position        */
+#define PDMA_ABTSTS_ABTIF7_Msk           (0x1ul << PDMA_ABTSTS_ABTIF7_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF7 Mask            */
+
+#define PDMA_ABTSTS_ABTIF8_Pos           (8)                                               /*!< PDMA_T::ABTSTS: ABTIF8 Position        */
+#define PDMA_ABTSTS_ABTIF8_Msk           (0x1ul << PDMA_ABTSTS_ABTIF8_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF8 Mask            */
+
+#define PDMA_ABTSTS_ABTIF9_Pos           (9)                                               /*!< PDMA_T::ABTSTS: ABTIF9 Position        */
+#define PDMA_ABTSTS_ABTIF9_Msk           (0x1ul << PDMA_ABTSTS_ABTIF9_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF9 Mask            */
+
+#define PDMA_ABTSTS_ABTIF10_Pos           (10)                                               /*!< PDMA_T::ABTSTS: ABTIF10 Position        */
+#define PDMA_ABTSTS_ABTIF10_Msk           (0x1ul << PDMA_ABTSTS_ABTIF10_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF10 Mask            */
+
+#define PDMA_ABTSTS_ABTIF11_Pos           (11)                                               /*!< PDMA_T::ABTSTS: ABTIF11 Position        */
+#define PDMA_ABTSTS_ABTIF11_Msk           (0x1ul << PDMA_ABTSTS_ABTIF11_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF11 Mask            */
+
+#define PDMA_ABTSTS_ABTIF12_Pos           (12)                                               /*!< PDMA_T::ABTSTS: ABTIF12 Position        */
+#define PDMA_ABTSTS_ABTIF12_Msk           (0x1ul << PDMA_ABTSTS_ABTIF12_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF12 Mask            */
+
+#define PDMA_ABTSTS_ABTIF13_Pos           (13)                                               /*!< PDMA_T::ABTSTS: ABTIF13 Position        */
+#define PDMA_ABTSTS_ABTIF13_Msk           (0x1ul << PDMA_ABTSTS_ABTIF13_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF13 Mask            */
+
+#define PDMA_ABTSTS_ABTIF14_Pos           (14)                                               /*!< PDMA_T::ABTSTS: ABTIF14 Position        */
+#define PDMA_ABTSTS_ABTIF14_Msk           (0x1ul << PDMA_ABTSTS_ABTIF14_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF14 Mask            */
+
+#define PDMA_ABTSTS_ABTIF15_Pos           (15)                                               /*!< PDMA_T::ABTSTS: ABTIF15 Position        */
+#define PDMA_ABTSTS_ABTIF15_Msk           (0x1ul << PDMA_ABTSTS_ABTIF15_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF15 Mask            */
+
+#define PDMA_TDSTS_TDIF0_Pos           (0)                                               /*!< PDMA_T::TDSTS: TDIF0 Position        */
+#define PDMA_TDSTS_TDIF0_Msk           (0x1ul << PDMA_TDSTS_TDIF0_Pos)                   /*!< PDMA_T::TDSTS: TDIF0 Mask            */
+
+#define PDMA_TDSTS_TDIF1_Pos           (1)                                               /*!< PDMA_T::TDSTS: TDIF1 Position        */
+#define PDMA_TDSTS_TDIF1_Msk           (0x1ul << PDMA_TDSTS_TDIF1_Pos)                   /*!< PDMA_T::TDSTS: TDIF1 Mask            */
+
+#define PDMA_TDSTS_TDIF2_Pos           (2)                                               /*!< PDMA_T::TDSTS: TDIF2 Position        */
+#define PDMA_TDSTS_TDIF2_Msk           (0x1ul << PDMA_TDSTS_TDIF2_Pos)                   /*!< PDMA_T::TDSTS: TDIF2 Mask            */
+
+#define PDMA_TDSTS_TDIF3_Pos           (3)                                               /*!< PDMA_T::TDSTS: TDIF3 Position        */
+#define PDMA_TDSTS_TDIF3_Msk           (0x1ul << PDMA_TDSTS_TDIF3_Pos)                   /*!< PDMA_T::TDSTS: TDIF3 Mask            */
+
+#define PDMA_TDSTS_TDIF4_Pos           (4)                                               /*!< PDMA_T::TDSTS: TDIF4 Position        */
+#define PDMA_TDSTS_TDIF4_Msk           (0x1ul << PDMA_TDSTS_TDIF4_Pos)                   /*!< PDMA_T::TDSTS: TDIF4 Mask            */
+
+#define PDMA_TDSTS_TDIF5_Pos           (5)                                               /*!< PDMA_T::TDSTS: TDIF5 Position        */
+#define PDMA_TDSTS_TDIF5_Msk           (0x1ul << PDMA_TDSTS_TDIF5_Pos)                   /*!< PDMA_T::TDSTS: TDIF5 Mask            */
+
+#define PDMA_TDSTS_TDIF6_Pos           (6)                                               /*!< PDMA_T::TDSTS: TDIF6 Position        */
+#define PDMA_TDSTS_TDIF6_Msk           (0x1ul << PDMA_TDSTS_TDIF6_Pos)                   /*!< PDMA_T::TDSTS: TDIF6 Mask            */
+
+#define PDMA_TDSTS_TDIF7_Pos           (7)                                               /*!< PDMA_T::TDSTS: TDIF7 Position        */
+#define PDMA_TDSTS_TDIF7_Msk           (0x1ul << PDMA_TDSTS_TDIF7_Pos)                   /*!< PDMA_T::TDSTS: TDIF7 Mask            */
+
+#define PDMA_TDSTS_TDIF8_Pos           (8)                                               /*!< PDMA_T::TDSTS: TDIF8 Position        */
+#define PDMA_TDSTS_TDIF8_Msk           (0x1ul << PDMA_TDSTS_TDIF8_Pos)                   /*!< PDMA_T::TDSTS: TDIF8 Mask            */
+
+#define PDMA_TDSTS_TDIF9_Pos           (9)                                               /*!< PDMA_T::TDSTS: TDIF9 Position        */
+#define PDMA_TDSTS_TDIF9_Msk           (0x1ul << PDMA_TDSTS_TDIF9_Pos)                   /*!< PDMA_T::TDSTS: TDIF9 Mask            */
+
+#define PDMA_TDSTS_TDIF10_Pos           (10)                                               /*!< PDMA_T::TDSTS: TDIF10 Position        */
+#define PDMA_TDSTS_TDIF10_Msk           (0x1ul << PDMA_TDSTS_TDIF10_Pos)                   /*!< PDMA_T::TDSTS: TDIF10 Mask            */
+
+#define PDMA_TDSTS_TDIF11_Pos           (11)                                               /*!< PDMA_T::TDSTS: TDIF11 Position        */
+#define PDMA_TDSTS_TDIF11_Msk           (0x1ul << PDMA_TDSTS_TDIF11_Pos)                   /*!< PDMA_T::TDSTS: TDIF11 Mask            */
+
+#define PDMA_TDSTS_TDIF12_Pos           (12)                                               /*!< PDMA_T::TDSTS: TDIF12 Position        */
+#define PDMA_TDSTS_TDIF12_Msk           (0x1ul << PDMA_TDSTS_TDIF12_Pos)                   /*!< PDMA_T::TDSTS: TDIF12 Mask            */
+
+#define PDMA_TDSTS_TDIF13_Pos           (13)                                               /*!< PDMA_T::TDSTS: TDIF13 Position        */
+#define PDMA_TDSTS_TDIF13_Msk           (0x1ul << PDMA_TDSTS_TDIF13_Pos)                   /*!< PDMA_T::TDSTS: TDIF13 Mask            */
+
+#define PDMA_TDSTS_TDIF14_Pos           (14)                                               /*!< PDMA_T::TDSTS: TDIF14 Position        */
+#define PDMA_TDSTS_TDIF14_Msk           (0x1ul << PDMA_TDSTS_TDIF14_Pos)                   /*!< PDMA_T::TDSTS: TDIF14 Mask            */
+
+#define PDMA_TDSTS_TDIF15_Pos           (15)                                               /*!< PDMA_T::TDSTS: TDIF15 Position        */
+#define PDMA_TDSTS_TDIF15_Msk           (0x1ul << PDMA_TDSTS_TDIF15_Pos)                   /*!< PDMA_T::TDSTS: TDIF15 Mask            */
+
+#define PDMA_ALIGN_ALIGNn_Pos           (0)                                                /*!< PDMA_T::ALIGN: ALIGNn Position        */
+#define PDMA_ALIGN_ALIGNn_Msk           (0xfffful << PDMA_ALIGN_ALIGNn_Pos)                /*!< PDMA_T::ALIGN: ALIGNn Mask            */
+
+#define PDMA_TACTSTS_TXACTFn_Pos         (0)                                               /*!< PDMA_T::TACTSTS: TXACTFn Position      */
+#define PDMA_TACTSTS_TXACTFn_Msk         (0xfffful << PDMA_TACTSTS_TXACTFn_Pos)            /*!< PDMA_T::TACTSTS: TXACTFn Mask          */
+
+#define PDMA_TOUTPSC_TOUTPSC0_Pos        (0)                                               /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position     */
+#define PDMA_TOUTPSC_TOUTPSC0_Msk        (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos)              /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask         */
+
+#define PDMA_TOUTPSC_TOUTPSC1_Pos        (4)                                               /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position     */
+#define PDMA_TOUTPSC_TOUTPSC1_Msk        (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos)              /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask         */
+
+#define PDMA_TOUTEN_TOUTENn_Pos          (0)                                               /*!< PDMA_T::TOUTEN: TOUTENn Position       */
+#define PDMA_TOUTEN_TOUTENn_Msk          (0x3ul << PDMA_TOUTEN_TOUTENn_Pos)                /*!< PDMA_T::TOUTEN: TOUTENn Mask           */
+
+#define PDMA_TOUTIEN_TOUTIENn_Pos        (0)                                               /*!< PDMA_T::TOUTIEN: TOUTIENn Position     */
+#define PDMA_TOUTIEN_TOUTIENn_Msk        (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos)              /*!< PDMA_T::TOUTIEN: TOUTIENn Mask         */
+
+#define PDMA_SCATBA_SCATBA_Pos           (16)                                              /*!< PDMA_T::SCATBA: SCATBA Position        */
+#define PDMA_SCATBA_SCATBA_Msk           (0xfffful << PDMA_SCATBA_SCATBA_Pos)              /*!< PDMA_T::SCATBA: SCATBA Mask            */
+
+#define PDMA_TOC0_1_TOC0_Pos             (0)                                               /*!< PDMA_T::TOC0_1: TOC0 Position          */
+#define PDMA_TOC0_1_TOC0_Msk             (0xfffful << PDMA_TOC0_1_TOC0_Pos)                /*!< PDMA_T::TOC0_1: TOC0 Mask              */
+
+#define PDMA_TOC0_1_TOC1_Pos             (16)                                              /*!< PDMA_T::TOC0_1: TOC1 Position          */
+#define PDMA_TOC0_1_TOC1_Msk             (0xfffful << PDMA_TOC0_1_TOC1_Pos)                /*!< PDMA_T::TOC0_1: TOC1 Mask              */
+
+#define PDMA_CHRST_CHnRST_Pos            (0)                                               /*!< PDMA_T::CHRST: CHnRST Position         */
+#define PDMA_CHRST_CHnRST_Msk            (0xfffful << PDMA_CHRST_CHnRST_Pos)               /*!< PDMA_T::CHRST: CHnRST Mask             */
+
+#define PDMA_REQSEL0_3_REQSRC0_Pos       (0)                                               /*!< PDMA_T::REQSEL0_3: REQSRC0 Position    */
+#define PDMA_REQSEL0_3_REQSRC0_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC1_Pos       (8)                                               /*!< PDMA_T::REQSEL0_3: REQSRC1 Position    */
+#define PDMA_REQSEL0_3_REQSRC1_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC2_Pos       (16)                                              /*!< PDMA_T::REQSEL0_3: REQSRC2 Position    */
+#define PDMA_REQSEL0_3_REQSRC2_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC3_Pos       (24)                                              /*!< PDMA_T::REQSEL0_3: REQSRC3 Position    */
+#define PDMA_REQSEL0_3_REQSRC3_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC4_Pos       (0)                                               /*!< PDMA_T::REQSEL4_7: REQSRC4 Position    */
+#define PDMA_REQSEL4_7_REQSRC4_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC5_Pos       (8)                                               /*!< PDMA_T::REQSEL4_7: REQSRC5 Position    */
+#define PDMA_REQSEL4_7_REQSRC5_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC6_Pos       (16)                                              /*!< PDMA_T::REQSEL4_7: REQSRC6 Position    */
+#define PDMA_REQSEL4_7_REQSRC6_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC7_Pos       (24)                                              /*!< PDMA_T::REQSEL4_7: REQSRC7 Position    */
+#define PDMA_REQSEL4_7_REQSRC7_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask        */
+
+#define PDMA_REQSEL8_11_REQSRC8_Pos      (0)                                               /*!< PDMA_T::REQSEL8_11: REQSRC8 Position   */
+#define PDMA_REQSEL8_11_REQSRC8_Msk      (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos)           /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask       */
+
+#define PDMA_REQSEL8_11_REQSRC9_Pos      (8)                                               /*!< PDMA_T::REQSEL8_11: REQSRC9 Position   */
+#define PDMA_REQSEL8_11_REQSRC9_Msk      (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos)           /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask       */
+
+#define PDMA_REQSEL8_11_REQSRC10_Pos     (16)                                              /*!< PDMA_T::REQSEL8_11: REQSRC10 Position  */
+#define PDMA_REQSEL8_11_REQSRC10_Msk     (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos)          /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask      */
+
+#define PDMA_REQSEL8_11_REQSRC11_Pos     (24)                                              /*!< PDMA_T::REQSEL8_11: REQSRC11 Position  */
+#define PDMA_REQSEL8_11_REQSRC11_Msk     (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos)          /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask      */
+
+#define PDMA_REQSEL12_15_REQSRC12_Pos    (0)                                               /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */
+#define PDMA_REQSEL12_15_REQSRC12_Msk    (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos)         /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask     */
+
+#define PDMA_REQSEL12_15_REQSRC13_Pos    (8)                                               /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */
+#define PDMA_REQSEL12_15_REQSRC13_Msk    (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos)         /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask     */
+
+#define PDMA_REQSEL12_15_REQSRC14_Pos    (16)                                              /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */
+#define PDMA_REQSEL12_15_REQSRC14_Msk    (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos)         /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask     */
+
+#define PDMA_REQSEL12_15_REQSRC15_Pos    (24)                                              /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */
+#define PDMA_REQSEL12_15_REQSRC15_Msk    (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos)         /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask     */
+
+#define PDMA_STCRn_STC_Pos               (0)                                               /*!< PDMA_T::STCRn: STC Position            */
+#define PDMA_STCRn_STC_Msk               (0xfffful << PDMA_STCRn_STC_Pos)                  /*!< PDMA_T::STCRn: STC Mask                */
+
+#define PDMA_ASOCRn_SASOL_Pos            (0)                                               /*!< PDMA_T::ASOCRn: SASOL Position         */
+#define PDMA_ASOCRn_SASOL_Msk            (0xfffful << PDMA_ASOCRn_SASOL_Pos)               /*!< PDMA_T::ASOCRn: SASOL Mask             */
+
+#define PDMA_ASOCRn_DASOL_Pos            (16)                                              /*!< PDMA_T::ASOCRn: DASOL Position         */
+#define PDMA_ASOCRn_DASOL_Msk            (0xfffful << PDMA_ASOCRn_DASOL_Pos)               /*!< PDMA_T::ASOCRn: DASOL Mask             */
+
+/**@}*/ /* PDMA_CONST */
+/**@}*/ /* end of PDMA register group */
+
+
+
+/*---------------------- Timer Controller -------------------------*/
+/**
+    @addtogroup TIMER Timer Controller(TIMER)
+    Memory Mapped Structure for TIMER Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var TIMER_T::CTL
+     * Offset: 0x00  Timer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |PSC       |Prescale Counter
+     * |        |          |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
+     * |        |          |If this field is 0 (PSC = 0), then there is no scaling.
+     * |        |          |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
+     * |[19]    |INTRGEN   |Inter-timer Trigger Mode Enable Control
+     * |        |          |Setting this bit will enable the inter-timer trigger capture function.
+     * |        |          |The Timer0/2 will be in event counter mode and counting with external clock source or event
+     * |        |          |Also, Timer1/3 will be in trigger-counting mode of capture function.
+     * |        |          |0 = Inter-Timer Trigger Capture mode Disabled.
+     * |        |          |1 = Inter-Timer Trigger Capture mode Enabled.
+     * |        |          |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
+     * |[20]    |PERIOSEL  |Periodic Mode Behavior Selection Enable Bit
+     * |        |          |0 = The behavior selection in periodic mode is Disabled.
+     * |        |          |When user updates CMPDAT while timer is running in periodic mode,
+     * |        |          |CNT will be reset to default value.
+     * |        |          |1 = The behavior selection in periodic mode is Enabled.
+     * |        |          |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
+     * |        |          |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
+     * |        |          |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
+     * |        |          |If updated CMPDAT value < CNT, CNT will be reset to default value.
+     * |[21]    |TGLPINSEL |Toggle-output Pin Select
+     * |        |          |0 = Toggle mode output to TMx (Timer Event Counter Pin).
+     * |        |          |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
+     * |[22]    |CAPSRC    |Capture Pin Source Selection
+     * |        |          |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
+     * |        |          |1 = Capture Function source is from internal ACMP output signal
+     * |        |          |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.
+     * |[23]    |WKEN      |Wake-up Function Enable Bit
+     * |        |          |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
+     * |        |          |0 = Wake-up function Disabled if timer interrupt signal generated.
+     * |        |          |1 = Wake-up function Enabled if timer interrupt signal generated.
+     * |[24]    |EXTCNTEN  |Event Counter Mode Enable Bit
+     * |        |          |This bit is for external counting pin function enabled.
+     * |        |          |0 = Event counter mode Disabled.
+     * |        |          |1 = Event counter mode Enabled.
+     * |        |          |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
+     * |[25]    |ACTSTS    |Timer Active Status Bit (Read Only)
+     * |        |          |This bit indicates the 24-bit up counter status.
+     * |        |          |0 = 24-bit up counter is not active.
+     * |        |          |1 = 24-bit up counter is active.
+     * |        |          |Note: This bit may active when CNT 0 transition to CNT 1.
+     * |[28:27] |OPMODE    |Timer Counting Mode Select
+     * |        |          |00 = The Timer controller is operated in One-shot mode.
+     * |        |          |01 = The Timer controller is operated in Periodic mode.
+     * |        |          |10 = The Timer controller is operated in Toggle-output mode.
+     * |        |          |11 = The Timer controller is operated in Continuous Counting mode.
+     * |[29]    |INTEN     |Timer Interrupt Enable Bit
+     * |        |          |0 = Timer time-out interrupt Disabled.
+     * |        |          |1 = Timer time-out interrupt Enabled.
+     * |        |          |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
+     * |[30]    |CNTEN     |Timer Counting Enable Bit
+     * |        |          |0 = Stops/Suspends counting.
+     * |        |          |1 = Starts counting.
+     * |        |          |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
+     * |        |          |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
+     * |        |          |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects TIMER counting.
+     * |        |          |TIMER counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |TIMER counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var TIMER_T::CMP
+     * Offset: 0x04  Timer Comparator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CMPDAT    |Timer Comparator Value
+     * |        |          |CMPDAT is a 24-bit compared value register
+     * |        |          |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
+     * |        |          |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
+     * |        |          |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
+     * |        |          |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
+     * |        |          |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
+     * @var TIMER_T::INTSTS
+     * Offset: 0x08  Timer Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TIF       |Timer Interrupt Flag
+     * |        |          |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
+     * |        |          |0 = No effect.
+     * |        |          |1 = CNT value matches the CMPDAT value.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |TWKF      |Timer Wake-up Flag
+     * |        |          |This bit indicates the interrupt wake-up flag status of timer.
+     * |        |          |0 = Timer does not cause CPU wake-up.
+     * |        |          |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::CNT
+     * Offset: 0x0C  Timer Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Timer Data Register
+     * |        |          |Read operation.
+     * |        |          |Read this register to get CNT value. For example:
+     * |        |          |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
+     * |        |          |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
+     * |        |          |Write operation.
+     * |        |          |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
+     * |[31]    |RSTACT    |Timer Data Register Reset Active (Read Only)
+     * |        |          |This bit indicates if the counter reset operation active.
+     * |        |          |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
+     * |        |          |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
+     * |        |          |Once the counter reset operation done, timer clear this bit to 0 automatically.
+     * |        |          |0 = Reset operation is done.
+     * |        |          |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
+     * |        |          |Note: This bit is read only.
+     * @var TIMER_T::CAP
+     * Offset: 0x10  Timer Capture Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CAPDAT    |Timer Capture Data Register
+     * |        |          |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
+     * @var TIMER_T::EXTCTL
+     * Offset: 0x14  Timer External Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTPHASE  |Timer External Count Phase
+     * |        |          |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
+     * |        |          |0 = A falling edge of external counting pin will be counted.
+     * |        |          |1 = A rising edge of external counting pin will be counted.
+     * |[3]     |CAPEN     |Timer External Capture Pin Enable Bit
+     * |        |          |This bit enables the TMx_EXT capture pin input function.
+     * |        |          |0 =TMx_EXT (x= 0~3) pin Disabled.
+     * |        |          |1 =TMx_EXT (x= 0~3) pin Enabled.
+     * |[4]     |CAPFUNCS  |Capture Function Selection
+     * |        |          |0 = External Capture Mode Enabled.
+     * |        |          |1 = External Reset Mode Enabled.
+     * |        |          |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
+     * |        |          |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
+     * |[5]     |CAPIEN    |Timer External Capture Interrupt Enable Bit
+     * |        |          |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
+     * |        |          |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
+     * |        |          |Note: CAPIEN is used to enable timer external interrupt
+     * |        |          |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
+     * |        |          |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+     * |[6]     |CAPDBEN   |Timer External Capture Pin De-bounce Enable Bit
+     * |        |          |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
+     * |        |          |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
+     * |        |          |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
+     * |[7]     |CNTDBEN   |Timer Counter Pin De-bounce Enable Bit
+     * |        |          |0 = TMx (x= 0~3) pin de-bounce Disabled.
+     * |        |          |1 = TMx (x= 0~3) pin de-bounce Enabled.
+     * |        |          |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
+     * |[8]     |ACMPSSEL  |ACMP Source Selection to Trigger Capture Function
+     * |        |          |0 = Capture Function source is from internal ACMP0 output signal.
+     * |        |          |1 = Capture Function source is from internal ACMP1 output signal.
+     * |        |          |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
+     * |[14:12] |CAPEDGE   |Timer External Capture Pin Edge Detect
+     * |        |          |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
+     * |        |          |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
+     * |        |          |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
+     * |        |          |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
+     * |        |          |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..
+     * |        |          |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
+     * |        |          |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
+     * |        |          |100, 101 = Reserved.
+     * |[16]    |ECNTSSEL  |Event Counter Source Selection to Trigger Event Counter Function
+     * |        |          |0 = Event Counter input source is from TMx (x= 0~3) pin.
+     * |        |          |1 = Event Counter input source is from USB internal SOF output signal.
+     * @var TIMER_T::EINTSTS
+     * Offset: 0x18  Timer External Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPIF     |Timer External Capture Interrupt Flag
+     * |        |          |This bit indicates the timer external capture interrupt flag status.
+     * |        |          |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
+     * |        |          |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
+     * |        |          |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
+     * |        |          |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
+     * @var TIMER_T::TRGCTL
+     * Offset: 0x1C  Timer Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TRGSSEL   |Trigger Source Select Bit
+     * |        |          |This bit is used to select internal trigger source is form timer time-out interrupt signal or
+     * |        |          |capture interrupt signal.
+     * |        |          |0 = Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC.
+     * |        |          |1 = Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC.
+     * |[1]     |TRGEPWM   |Trigger EPWM Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be as EPWM counter clock source.
+     * |        |          |0 = Timer interrupt trigger EPWM Disabled.
+     * |        |          |1 = Timer interrupt trigger EPWM Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM counter clock source.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source.
+     * |[2]     |TRGEADC   |Trigger EADC Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
+     * |        |          |0 = Timer interrupt trigger EADC Disabled.
+     * |        |          |1 = Timer interrupt trigger EADC Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion.
+     * |[3]     |TRGDAC    |Trigger DAC Enable Bit
+     * |        |          |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
+     * |        |          |0 = Timer interrupt trigger DAC Disabled.
+     * |        |          |1 = Timer interrupt trigger DAC Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
+     * |[4]     |TRGPDMA   |Trigger PDMA Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
+     * |        |          |0 = Timer interrupt trigger PDMA Disabled.
+     * |        |          |1 = Timer interrupt trigger PDMA Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
+     * @var TIMER_T::ALTCTL
+     * Offset: 0x20  Timer Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FUNCSEL   |Function Selection
+     * |        |          |0 = Timer controller is used as timer function.
+     * |        |          |1 = Timer controller is used as PWM function.
+     * |        |          |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
+     * @var TIMER_T::PWMCTL
+     * Offset: 0x40  Timer PWM Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN     |PWM Counter Enable Bit
+     * |        |          |0 = PWM counter and clock prescale Stop Running.
+     * |        |          |1 = PWM counter and clock prescale Start Running.
+     * |[2:1]   |CNTTYPE   |PWM Counter Behavior Type
+     * |        |          |00 = Up count type.
+     * |        |          |01 = Down count type.
+     * |        |          |10 = Up-down count type.
+     * |        |          |11 = Reserved.
+     * |[3]     |CNTMODE   |PWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[8]     |CTRLD     |Center Re-load
+     * |        |          |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
+     * |[9]     |IMMLDEN   |Immediately Load Enable Bit
+     * |        |          |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled
+     * |        |          |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
+     * |        |          |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
+     * |        |          |Note: If IMMLDEN is enabled, CTRLD will be invalid.
+     * |[16]    |OUTMODE   |PWM Output Mode
+     * |        |          |This bit controls the output mode of corresponding PWM channel.
+     * |        |          |0 = PWM independent mode.
+     * |        |          |1 = PWM complementary mode.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt disable.
+     * |        |          |1 = ICE debug mode counter halt enable.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects PWM output.
+     * |        |          |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement disabled.
+     * |        |          |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var TIMER_T::PWMCLKSRC
+     * Offset: 0x44  Timer PWM Counter Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |CLKSRC    |PWM Counter Clock Source Select
+     * |        |          |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
+     * |        |          |000 = TMRx_CLK.
+     * |        |          |001 = Internal TIMER0 time-out or capture event.
+     * |        |          |010 = Internal TIMER1 time-out or capture event.
+     * |        |          |011 = Internal TIMER2 time-out or capture event.
+     * |        |          |100 = Internal TIMER3 time-out or capture event.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
+     * @var TIMER_T::PWMCLKPSC
+     * Offset: 0x48  Timer PWM Counter Clock Pre-scale Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-scale
+     * |        |          |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
+     * |        |          |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
+     * @var TIMER_T::PWMCNTCLR
+     * Offset: 0x4C  Timer PWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR    |Clear PWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
+     * @var TIMER_T::PWMPERIOD
+     * Offset: 0x50  Timer PWM Period Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |PWM Period Register
+     * |        |          |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |In up and down count type:
+     * |        |          |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
+     * |        |          |In up-down count type:
+     * |        |          |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
+     * |        |          |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
+     * @var TIMER_T::PWMCMPDAT
+     * Offset: 0x54  Timer PWM Comparator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMP       |PWM Comparator Register
+     * |        |          |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
+     * @var TIMER_T::PWMDTCTL
+     * Offset: 0x58  Timer PWM Dead-Time Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DTCNT     |Dead-time Counter (Write Protect)
+     * |        |          |The dead-time can be calculated from the following two formulas:
+     * |        |          |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
+     * |        |          |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[16]    |DTEN      |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
+     * |        |          |Dead-time insertion function is only active when PWM complementary mode is enabled
+     * |        |          |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
+     * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+     * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[24]    |DTCKSEL   |Dead-time Clock Select (Write Protect)
+     * |        |          |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
+     * |        |          |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var TIMER_T::PWMCNT
+     * Offset: 0x5C  Timer PWM Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |PWM Counter Value Register (Read Only)
+     * |        |          |User can monitor CNT to know the current counter value in 16-bit period counter.
+     * |[16]    |DIRF      |PWM Counter Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is active in down count.
+     * |        |          |1 = Counter is active up count.
+     * @var TIMER_T::PWMMSKEN
+     * Offset: 0x60  Timer PWM Output Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |PWMx_CH0 Output Mask Enable Bit
+     * |        |          |The PWMx_CH0 output signal will be masked when this bit is enabled
+     * |        |          |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
+     * |        |          |0 = PWMx_CH0 output signal is non-masked.
+     * |        |          |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
+     * |[1]     |MSKEN1    |PWMx_CH1 Output Mask Enable Bit
+     * |        |          |The PWMx_CH1 output signal will be masked when this bit is enabled
+     * |        |          |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
+     * |        |          |0 = PWMx_CH1 output signal is non-masked.
+     * |        |          |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
+     * @var TIMER_T::PWMMSK
+     * Offset: 0x64  Timer PWM Output Mask Data Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |PWMx_CH0 Output Mask Data Control Bit
+     * |        |          |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
+     * |        |          |0 = Output logic Low to PWMx_CH0.
+     * |        |          |1 = Output logic High to PWMx_CH0.
+     * |[1]     |MSKDAT1   |PWMx_CH1 Output Mask Data Control Bit
+     * |        |          |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
+     * |        |          |0 = Output logic Low to PWMx_CH1.
+     * |        |          |1 = Output logic High to PWMx_CH1.
+     * @var TIMER_T::PWMBNF
+     * Offset: 0x68  Timer PWM Brake Pin Noise Filter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKNFEN   |Brake Pin Noise Filter Enable Bit
+     * |        |          |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
+     * |        |          |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
+     * |[3:1]   |BRKNFSEL  |Brake Pin Noise Filter Clock Selection
+     * |        |          |000 = Noise filter clock is PCLKx.
+     * |        |          |001 = Noise filter clock is PCLKx/2.
+     * |        |          |010 = Noise filter clock is PCLKx/4.
+     * |        |          |011 = Noise filter clock is PCLKx/8.
+     * |        |          |100 = Noise filter clock is PCLKx/16.
+     * |        |          |101 = Noise filter clock is PCLKx/32.
+     * |        |          |110 = Noise filter clock is PCLKx/64.
+     * |        |          |111 = Noise filter clock is PCLKx/128.
+     * |[6:4]   |BRKFCNT   |Brake Pin Noise Filter Count
+     * |        |          |The fields is used to control the active noise filter sample time.
+     * |        |          |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.
+     * |[7]     |BRKPINV   |Brake Pin Detection Control Bit
+     * |        |          |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
+     * |        |          |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
+     * |[17:16] |BKPINSRC  |Brake Pin Source Select
+     * |        |          |00 = Brake pin source comes from PWM0_BRAKE0 pin.
+     * |        |          |01 = Brake pin source comes from PWM0_BRAKE1 pin.
+     * |        |          |10 = Brake pin source comes from PWM1_BRAKE0 pin.
+     * |        |          |11 = Brake pin source comes from PWM1_BRAKE1 pin.
+     * @var TIMER_T::PWMFAILBRK
+     * Offset: 0x6C  Timer PWM System Fail Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CSSBRKEN  |Clock Security System Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by clock fail detection Disabled.
+     * |        |          |1 = Brake Function triggered by clock fail detection Enabled.
+     * |[1]     |BODBRKEN  |Brown-out Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by BOD event Disabled.
+     * |        |          |1 = Brake Function triggered by BOD event Enabled.
+     * |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.
+     * |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.
+     * |[3]     |CORBRKEN  |Core Lockup Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by core lockup event Disabled.
+     * |        |          |1 = Brake Function triggered by core lockup event Enabled.
+     * @var TIMER_T::PWMBRKCTL
+     * Offset: 0x70  Timer PWM Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CPO0EBEN  |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |CPO1EBEN  |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[4]     |BRKPEEN   |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
+     * |        |          |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[7]     |SYSEBEN   |Enable System Fail As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = System fail condition as edge-detect brake source Disabled.
+     * |        |          |1 = System fail condition as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |CPO0LBEN  |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP0_O signal as level-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP0_O signal as level-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |CPO1LBEN  |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP1_O signal as level-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP1_O signal as level-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[12]    |BRKPLEN   |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
+     * |        |          |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[15]    |SYSLBEN   |Enable System Fail As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = System fail condition as level-detect brake source Disabled.
+     * |        |          |1 = System fail condition as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[17:16] |BRKAEVEN  |PWM Brake Action Select for PWMx_CH0 (Write Protect)
+     * |        |          |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
+     * |        |          |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
+     * |        |          |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
+     * |        |          |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[19:18] |BRKAODD   |PWM Brake Action Select for PWMx_CH1 (Write Protect)
+     * |        |          |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
+     * |        |          |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
+     * |        |          |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
+     * |        |          |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var TIMER_T::PWMPOLCTL
+     * Offset: 0x74  Timer PWM Pin Output Polar Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |PWMx_CH0 Output Pin Polar Control Bit
+     * |        |          |The bit is used to control polarity state of PWMx_CH0 output pin.
+     * |        |          |0 = PWMx_CH0 output pin polar inverse Disabled.
+     * |        |          |1 = PWMx_CH0 output pin polar inverse Enabled.
+     * |[1]     |PINV1     |PWMx_CH1 Output Pin Polar Control Bit
+     * |        |          |The bit is used to control polarity state of PWMx_CH1 output pin.
+     * |        |          |0 = PWMx_CH1 output pin polar inverse Disabled.
+     * |        |          |1 = PWMx_CH1 output pin polar inverse Enabled.
+     * @var TIMER_T::PWMPOEN
+     * Offset: 0x78  Timer PWM Pin Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |PWMx_CH0 Output Pin Enable Bit
+     * |        |          |0 = PWMx_CH0 pin at tri-state mode.
+     * |        |          |1 = PWMx_CH0 pin in output mode.
+     * |[1]     |POEN1     |PWMx_CH1 Output Pin Enable Bit
+     * |        |          |0 = PWMx_CH1 pin at tri-state mode.
+     * |        |          |1 = PWMx_CH1 pin in output mode.
+     * @var TIMER_T::PWMSWBRK
+     * Offset: 0x7C  Timer PWM Software Trigger Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKETRG   |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLTRG   |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var TIMER_T::PWMINTEN0
+     * Offset: 0x80  Timer PWM Interrupt Enable Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN      |PWM Zero Point Interrupt Enable Bit
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |[1]     |PIEN      |PWM Period Point Interrupt Enable Bit
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note: When in up-down count type, period point means the center point of current PWM period.
+     * |[2]     |CMPUIEN   |PWM Compare Up Count Interrupt Enable Bit
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[3]     |CMPDIEN   |PWM Compare Down Count Interrupt Enable Bit
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * @var TIMER_T::PWMINTEN1
+     * Offset: 0x84  Timer PWM Interrupt Enable Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIEN   |PWM Edge-detect Brake Interrupt Enable (Write Protect)
+     * |        |          |0 = PWM edge-detect brake interrupt Disabled.
+     * |        |          |1 = PWM edge-detect brake interrupt Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLIEN   |PWM Level-detect Brake Interrupt Enable (Write Protect)
+     * |        |          |0 = PWM level-detect brake interrupt Disabled.
+     * |        |          |1 = PWM level-detect brake interrupt Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var TIMER_T::PWMINTSTS0
+     * Offset: 0x88  Timer PWM Interrupt Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF       |PWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter reaches zero.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |PIF       |PWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
+     * |        |          |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[2]     |CMPUIF    |PWM Compare Up Count Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
+     * |        |          |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[3]     |CMPDIF    |PWM Compare Down Count Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
+     * |        |          |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::PWMINTSTS1
+     * Offset: 0x8C  Timer PWM Interrupt Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIF0   |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+     * |        |          |0 = PWMx_CH0 edge-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH0 edge-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |BRKEIF1   |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
+     * |        |          |0 = PWMx_CH1 edge-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH1 edge-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLIF0   |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+     * |        |          |0 = PWMx_CH0 level-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH0 level-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |BRKLIF1   |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
+     * |        |          |0 = PWMx_CH1 level-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH1 level-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[16]    |BRKESTS0  |Edge -detect Brake Status of PWMx_CH0 (Read Only)
+     * |        |          |0 = PWMx_CH0 edge-detect brake state is released.
+     * |        |          |1 = PWMx_CH0 at edge-detect brake state.
+     * |        |          |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
+     * |[17]    |BRKESTS1  |Edge-detect Brake Status of PWMx_CH1 (Read Only)
+     * |        |          |0 = PWMx_CH1 edge-detect brake state is released.
+     * |        |          |1 = PWMx_CH1 at edge-detect brake state.
+     * |        |          |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
+     * |[24]    |BRKLSTS0  |Level-detect Brake Status of PWMx_CH0 (Read Only)
+     * |        |          |0 = PWMx_CH0 level-detect brake state is released.
+     * |        |          |1 = PWMx_CH0 at level-detect brake state.
+     * |        |          |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+     * |[25]    |BRKLSTS1  |Level-detect Brake Status of PWMx_CH1 (Read Only)
+     * |        |          |0 = PWMx_CH1 level-detect brake state is released.
+     * |        |          |1 = PWMx_CH1 at level-detect brake state.
+     * |        |          |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+     * @var TIMER_T::PWMEADCTS
+     * Offset: 0x90  Timer PWM ADC Trigger Source Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TRGSEL    |PWM Counter Event Source Select to Trigger EADC Conversion
+     * |        |          |000 = Trigger EADC conversion at zero point (ZIF).
+     * |        |          |001 = Trigger EADC conversion at period point (PIF).
+     * |        |          |010 = Trigger EADC conversion at zero or period point (ZIF or PIF).
+     * |        |          |011 = Trigger EADC conversion at compare up count point (CMPUIF).
+     * |        |          |100 = Trigger EADC conversion at compare down count point (CMPDIF).
+     * |        |          |Others = Reserved.
+     * |[7]     |TRGEN     |PWM Counter Event Trigger EADC Conversion Enable Bit
+     * |        |          |0 = PWM counter event trigger EADC conversion Disabled.
+     * |        |          |1 = PWM counter event trigger EADC conversion Enabled.
+     * @var TIMER_T::PWMSCTL
+     * Offset: 0x94  Timer PWM Synchronous Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SYNCMODE  |PWM Synchronous Mode Enable Select
+     * |        |          |00 = PWM synchronous function Disabled.
+     * |        |          |01 = PWM synchronous counter start function Enabled.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = PWM synchronous counter clear function Enabled.
+     * |[8]     |SYNCSRC   |PWM Synchronous Counter Start/Clear Source Select
+     * |        |          |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
+     * |        |          |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
+     * |        |          |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
+     * |        |          |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
+     * @var TIMER_T::PWMSTRG
+     * Offset: 0x98  Timer PWM Synchronous Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |STRGEN    |PWM Counter Synchronous Trigger Enable Bit (Write Only)
+     * |        |          |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
+     * |        |          |Note: This bit is only available in TIMER0 and TIMER2.
+     * @var TIMER_T::PWMSTATUS
+     * Offset: 0x9C  Timer PWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAXF   |PWM Counter Equal to 0xFFFF Flag
+     * |        |          |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.
+     * |        |          |1 = Indicates the PWM counter value has reached its maximum value.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[16]    |EADCTRGF  |Trigger EADC Start Conversion Flag
+     * |        |          |0 = PWM counter event trigger EADC start conversion is not occurred.
+     * |        |          |1 = PWM counter event trigger EADC start conversion has occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::PWMPBUF
+     * Offset: 0xA0  Timer PWM Period Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |PWM Period Buffer Register (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var TIMER_T::PWMCMPBUF
+     * Offset: 0xA4  Timer PWM Comparator Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |PWM Comparator Buffer Register (Read Only)
+     * |        |          |Used as CMP active register.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] Timer Control Register                                           */
+    __IO uint32_t CMP;                   /*!< [0x0004] Timer Comparator Register                                        */
+    __IO uint32_t INTSTS;                /*!< [0x0008] Timer Interrupt Status Register                                  */
+    __IO uint32_t CNT;                   /*!< [0x000c] Timer Data Register                                              */
+    __I  uint32_t CAP;                   /*!< [0x0010] Timer Capture Data Register                                      */
+    __IO uint32_t EXTCTL;                /*!< [0x0014] Timer External Control Register                                  */
+    __IO uint32_t EINTSTS;               /*!< [0x0018] Timer External Interrupt Status Register                         */
+    __IO uint32_t TRGCTL;                /*!< [0x001c] Timer Trigger Control Register                                   */
+    __IO uint32_t ALTCTL;                /*!< [0x0020] Timer Alternative Control Register                               */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[7];
+    /** @endcond */
+    __IO uint32_t PWMCTL;                /*!< [0x0040] Timer PWM Control Register                                       */
+    __IO uint32_t PWMCLKSRC;             /*!< [0x0044] Timer PWM Counter Clock Source Register                          */
+    __IO uint32_t PWMCLKPSC;             /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register                       */
+    __IO uint32_t PWMCNTCLR;             /*!< [0x004c] Timer PWM Clear Counter Register                                 */
+    __IO uint32_t PWMPERIOD;             /*!< [0x0050] Timer PWM Period Register                                        */
+    __IO uint32_t PWMCMPDAT;             /*!< [0x0054] Timer PWM Comparator Register                                    */
+    __IO uint32_t PWMDTCTL;              /*!< [0x0058] Timer PWM Dead-Time Control Register                             */
+    __I  uint32_t PWMCNT;                /*!< [0x005c] Timer PWM Counter Register                                       */
+    __IO uint32_t PWMMSKEN;              /*!< [0x0060] Timer PWM Output Mask Enable Register                            */
+    __IO uint32_t PWMMSK;                /*!< [0x0064] Timer PWM Output Mask Data Control Register                      */
+    __IO uint32_t PWMBNF;                /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register                        */
+    __IO uint32_t PWMFAILBRK;            /*!< [0x006c] Timer PWM System Fail Brake Control Register                     */
+    __IO uint32_t PWMBRKCTL;             /*!< [0x0070] Timer PWM Brake Control Register                                 */
+    __IO uint32_t PWMPOLCTL;             /*!< [0x0074] Timer PWM Pin Output Polar Control Register                      */
+    __IO uint32_t PWMPOEN;               /*!< [0x0078] Timer PWM Pin Output Enable Register                             */
+    __O  uint32_t PWMSWBRK;              /*!< [0x007c] Timer PWM Software Trigger Brake Control Register                */
+    __IO uint32_t PWMINTEN0;             /*!< [0x0080] Timer PWM Interrupt Enable Register 0                            */
+    __IO uint32_t PWMINTEN1;             /*!< [0x0084] Timer PWM Interrupt Enable Register 1                            */
+    __IO uint32_t PWMINTSTS0;            /*!< [0x0088] Timer PWM Interrupt Status Register 0                            */
+    __IO uint32_t PWMINTSTS1;            /*!< [0x008c] Timer PWM Interrupt Status Register 1                            */
+    __IO uint32_t PWMEADCTS;             /*!< [0x0090] Timer PWM EADC Trigger Source Select Register                    */
+    __IO uint32_t PWMSCTL;               /*!< [0x0094] Timer PWM Synchronous Control Register                           */
+    __O  uint32_t PWMSTRG;               /*!< [0x0098] Timer PWM Synchronous Trigger Register                           */
+    __IO uint32_t PWMSTATUS;             /*!< [0x009c] Timer PWM Status Register                                        */
+    __I  uint32_t PWMPBUF;               /*!< [0x00a0] Timer PWM Period Buffer Register                                 */
+    __I  uint32_t PWMCMPBUF;             /*!< [0x00a4] Timer PWM Comparator Buffer Register                             */
+
+} TIMER_T;
+
+/**
+    @addtogroup TIMER_CONST TIMER Bit Field Definition
+    Constant Definitions for TIMER Controller
+@{ */
+
+#define TIMER_CTL_PSC_Pos                (0)                                               /*!< TIMER_T::CTL: PSC Position             */
+#define TIMER_CTL_PSC_Msk                (0xfful << TIMER_CTL_PSC_Pos)                     /*!< TIMER_T::CTL: PSC Mask                 */
+
+#define TIMER_CTL_INTRGEN_Pos            (19)                                              /*!< TIMER_T::CTL: INTRGEN Position         */
+#define TIMER_CTL_INTRGEN_Msk            (0x1ul << TIMER_CTL_INTRGEN_Pos)                  /*!< TIMER_T::CTL: INTRGEN Mask             */
+
+#define TIMER_CTL_PERIOSEL_Pos           (20)                                              /*!< TIMER_T::CTL: PERIOSEL Position        */
+#define TIMER_CTL_PERIOSEL_Msk           (0x1ul << TIMER_CTL_PERIOSEL_Pos)                 /*!< TIMER_T::CTL: PERIOSEL Mask            */
+
+#define TIMER_CTL_TGLPINSEL_Pos          (21)                                              /*!< TIMER_T::CTL: TGLPINSEL Position       */
+#define TIMER_CTL_TGLPINSEL_Msk          (0x1ul << TIMER_CTL_TGLPINSEL_Pos)                /*!< TIMER_T::CTL: TGLPINSEL Mask           */
+
+#define TIMER_CTL_CAPSRC_Pos             (22)                                              /*!< TIMER_T::CTL: CAPSRC Position          */
+#define TIMER_CTL_CAPSRC_Msk             (0x1ul << TIMER_CTL_CAPSRC_Pos)                   /*!< TIMER_T::CTL: CAPSRC Mask              */
+
+#define TIMER_CTL_WKEN_Pos               (23)                                              /*!< TIMER_T::CTL: WKEN Position            */
+#define TIMER_CTL_WKEN_Msk               (0x1ul << TIMER_CTL_WKEN_Pos)                     /*!< TIMER_T::CTL: WKEN Mask                */
+
+#define TIMER_CTL_EXTCNTEN_Pos           (24)                                              /*!< TIMER_T::CTL: EXTCNTEN Position        */
+#define TIMER_CTL_EXTCNTEN_Msk           (0x1ul << TIMER_CTL_EXTCNTEN_Pos)                 /*!< TIMER_T::CTL: EXTCNTEN Mask            */
+
+#define TIMER_CTL_ACTSTS_Pos             (25)                                              /*!< TIMER_T::CTL: ACTSTS Position          */
+#define TIMER_CTL_ACTSTS_Msk             (0x1ul << TIMER_CTL_ACTSTS_Pos)                   /*!< TIMER_T::CTL: ACTSTS Mask              */
+
+#define TIMER_CTL_OPMODE_Pos             (27)                                              /*!< TIMER_T::CTL: OPMODE Position          */
+#define TIMER_CTL_OPMODE_Msk             (0x3ul << TIMER_CTL_OPMODE_Pos)                   /*!< TIMER_T::CTL: OPMODE Mask              */
+
+#define TIMER_CTL_INTEN_Pos              (29)                                              /*!< TIMER_T::CTL: INTEN Position           */
+#define TIMER_CTL_INTEN_Msk              (0x1ul << TIMER_CTL_INTEN_Pos)                    /*!< TIMER_T::CTL: INTEN Mask               */
+
+#define TIMER_CTL_CNTEN_Pos              (30)                                              /*!< TIMER_T::CTL: CNTEN Position           */
+#define TIMER_CTL_CNTEN_Msk              (0x1ul << TIMER_CTL_CNTEN_Pos)                    /*!< TIMER_T::CTL: CNTEN Mask               */
+
+#define TIMER_CTL_ICEDEBUG_Pos           (31)                                              /*!< TIMER_T::CTL: ICEDEBUG Position        */
+#define TIMER_CTL_ICEDEBUG_Msk           (0x1ul << TIMER_CTL_ICEDEBUG_Pos)                 /*!< TIMER_T::CTL: ICEDEBUG Mask            */
+
+#define TIMER_CMP_CMPDAT_Pos             (0)                                               /*!< TIMER_T::CMP: CMPDAT Position          */
+#define TIMER_CMP_CMPDAT_Msk             (0xfffffful << TIMER_CMP_CMPDAT_Pos)              /*!< TIMER_T::CMP: CMPDAT Mask              */
+
+#define TIMER_INTSTS_TIF_Pos             (0)                                               /*!< TIMER_T::INTSTS: TIF Position          */
+#define TIMER_INTSTS_TIF_Msk             (0x1ul << TIMER_INTSTS_TIF_Pos)                   /*!< TIMER_T::INTSTS: TIF Mask              */
+
+#define TIMER_INTSTS_TWKF_Pos            (1)                                               /*!< TIMER_T::INTSTS: TWKF Position         */
+#define TIMER_INTSTS_TWKF_Msk            (0x1ul << TIMER_INTSTS_TWKF_Pos)                  /*!< TIMER_T::INTSTS: TWKF Mask             */
+
+#define TIMER_CNT_CNT_Pos                (0)                                               /*!< TIMER_T::CNT: CNT Position             */
+#define TIMER_CNT_CNT_Msk                (0xfffffful << TIMER_CNT_CNT_Pos)                 /*!< TIMER_T::CNT: CNT Mask                 */
+
+#define TIMER_CNT_RSTACT_Pos             (31)                                              /*!< TIMER_T::CNT: RSTACT Position          */
+#define TIMER_CNT_RSTACT_Msk             (0x1ul << TIMER_CNT_RSTACT_Pos)                   /*!< TIMER_T::CNT: RSTACT Mask              */
+
+#define TIMER_CAP_CAPDAT_Pos             (0)                                               /*!< TIMER_T::CAP: CAPDAT Position          */
+#define TIMER_CAP_CAPDAT_Msk             (0xfffffful << TIMER_CAP_CAPDAT_Pos)              /*!< TIMER_T::CAP: CAPDAT Mask              */
+
+#define TIMER_EXTCTL_CNTPHASE_Pos        (0)                                               /*!< TIMER_T::EXTCTL: CNTPHASE Position     */
+#define TIMER_EXTCTL_CNTPHASE_Msk        (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)              /*!< TIMER_T::EXTCTL: CNTPHASE Mask         */
+
+#define TIMER_EXTCTL_CAPEN_Pos           (3)                                               /*!< TIMER_T::EXTCTL: CAPEN Position        */
+#define TIMER_EXTCTL_CAPEN_Msk           (0x1ul << TIMER_EXTCTL_CAPEN_Pos)                 /*!< TIMER_T::EXTCTL: CAPEN Mask            */
+
+#define TIMER_EXTCTL_CAPFUNCS_Pos        (4)                                               /*!< TIMER_T::EXTCTL: CAPFUNCS Position     */
+#define TIMER_EXTCTL_CAPFUNCS_Msk        (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)              /*!< TIMER_T::EXTCTL: CAPFUNCS Mask         */
+
+#define TIMER_EXTCTL_CAPIEN_Pos          (5)                                               /*!< TIMER_T::EXTCTL: CAPIEN Position       */
+#define TIMER_EXTCTL_CAPIEN_Msk          (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)                /*!< TIMER_T::EXTCTL: CAPIEN Mask           */
+
+#define TIMER_EXTCTL_CAPDBEN_Pos         (6)                                               /*!< TIMER_T::EXTCTL: CAPDBEN Position      */
+#define TIMER_EXTCTL_CAPDBEN_Msk         (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)               /*!< TIMER_T::EXTCTL: CAPDBEN Mask          */
+
+#define TIMER_EXTCTL_CNTDBEN_Pos         (7)                                               /*!< TIMER_T::EXTCTL: CNTDBEN Position      */
+#define TIMER_EXTCTL_CNTDBEN_Msk         (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)               /*!< TIMER_T::EXTCTL: CNTDBEN Mask          */
+
+#define TIMER_EXTCTL_ACMPSSEL_Pos        (8)                                               /*!< TIMER_T::EXTCTL: ACMPSSEL Position     */
+#define TIMER_EXTCTL_ACMPSSEL_Msk        (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos)              /*!< TIMER_T::EXTCTL: ACMPSSEL Mask         */
+
+#define TIMER_EXTCTL_CAPEDGE_Pos         (12)                                              /*!< TIMER_T::EXTCTL: CAPEDGE Position      */
+#define TIMER_EXTCTL_CAPEDGE_Msk         (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos)               /*!< TIMER_T::EXTCTL: CAPEDGE Mask          */
+
+#define TIMER_EXTCTL_ECNTSSEL_Pos        (16)                                              /*!< TIMER_T::EXTCTL: ECNTSSEL Position     */
+#define TIMER_EXTCTL_ECNTSSEL_Msk        (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos)              /*!< TIMER_T::EXTCTL: ECNTSSEL Mask         */
+
+#define TIMER_EINTSTS_CAPIF_Pos          (0)                                               /*!< TIMER_T::EINTSTS: CAPIF Position       */
+#define TIMER_EINTSTS_CAPIF_Msk          (0x1ul << TIMER_EINTSTS_CAPIF_Pos)                /*!< TIMER_T::EINTSTS: CAPIF Mask           */
+
+#define TIMER_TRGCTL_TRGSSEL_Pos         (0)                                               /*!< TIMER_T::TRGCTL: TRGSSEL Position      */
+#define TIMER_TRGCTL_TRGSSEL_Msk         (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos)               /*!< TIMER_T::TRGCTL: TRGSSEL Mask          */
+
+#define TIMER_TRGCTL_TRGEPWM_Pos         (1)                                               /*!< TIMER_T::TRGCTL: TRGEPWM Position      */
+#define TIMER_TRGCTL_TRGEPWM_Msk         (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos)               /*!< TIMER_T::TRGCTL: TRGEPWM Mask          */
+
+#define TIMER_TRGCTL_TRGEADC_Pos         (2)                                               /*!< TIMER_T::TRGCTL: TRGEADC Position      */
+#define TIMER_TRGCTL_TRGEADC_Msk         (0x1ul << TIMER_TRGCTL_TRGEADC_Pos)               /*!< TIMER_T::TRGCTL: TRGEADC Mask          */
+
+#define TIMER_TRGCTL_TRGDAC_Pos          (3)                                               /*!< TIMER_T::TRGCTL: TRGDAC Position       */
+#define TIMER_TRGCTL_TRGDAC_Msk          (0x1ul << TIMER_TRGCTL_TRGDAC_Pos)                /*!< TIMER_T::TRGCTL: TRGDAC Mask           */
+
+#define TIMER_TRGCTL_TRGPDMA_Pos         (4)                                               /*!< TIMER_T::TRGCTL: TRGPDMA Position      */
+#define TIMER_TRGCTL_TRGPDMA_Msk         (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos)               /*!< TIMER_T::TRGCTL: TRGPDMA Mask          */
+
+#define TIMER_ALTCTL_FUNCSEL_Pos         (0)                                               /*!< TIMER_T::ALTCTL: FUNCSEL Position      */
+#define TIMER_ALTCTL_FUNCSEL_Msk         (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos)               /*!< TIMER_T::ALTCTL: FUNCSEL Mask          */
+
+#define TIMER_PWMCTL_CNTEN_Pos           (0)                                               /*!< TIMER_T::PWMCTL: CNTEN Position        */
+#define TIMER_PWMCTL_CNTEN_Msk           (0x1ul << TIMER_PWMCTL_CNTEN_Pos)                 /*!< TIMER_T::PWMCTL: CNTEN Mask            */
+
+#define TIMER_PWMCTL_CNTTYPE_Pos         (1)                                               /*!< TIMER_T::PWMCTL: CNTTYPE Position      */
+#define TIMER_PWMCTL_CNTTYPE_Msk         (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos)               /*!< TIMER_T::PWMCTL: CNTTYPE Mask          */
+
+#define TIMER_PWMCTL_CNTMODE_Pos         (3)                                               /*!< TIMER_T::PWMCTL: CNTMODE Position      */
+#define TIMER_PWMCTL_CNTMODE_Msk         (0x1ul << TIMER_PWMCTL_CNTMODE_Pos)               /*!< TIMER_T::PWMCTL: CNTMODE Mask          */
+
+#define TIMER_PWMCTL_CTRLD_Pos           (8)                                               /*!< TIMER_T::PWMCTL: CTRLD Position        */
+#define TIMER_PWMCTL_CTRLD_Msk           (0x1ul << TIMER_PWMCTL_CTRLD_Pos)                 /*!< TIMER_T::PWMCTL: CTRLD Mask            */
+
+#define TIMER_PWMCTL_IMMLDEN_Pos         (9)                                               /*!< TIMER_T::PWMCTL: IMMLDEN Position      */
+#define TIMER_PWMCTL_IMMLDEN_Msk         (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos)               /*!< TIMER_T::PWMCTL: IMMLDEN Mask          */
+
+#define TIMER_PWMCTL_OUTMODE_Pos         (16)                                              /*!< TIMER_T::PWMCTL: OUTMODE Position      */
+#define TIMER_PWMCTL_OUTMODE_Msk         (0x1ul << TIMER_PWMCTL_OUTMODE_Pos)               /*!< TIMER_T::PWMCTL: OUTMODE Mask          */
+
+#define TIMER_PWMCTL_DBGHALT_Pos         (30)                                              /*!< TIMER_T::PWMCTL: DBGHALT Position      */
+#define TIMER_PWMCTL_DBGHALT_Msk         (0x1ul << TIMER_PWMCTL_DBGHALT_Pos)               /*!< TIMER_T::PWMCTL: DBGHALT Mask          */
+
+#define TIMER_PWMCTL_DBGTRIOFF_Pos       (31)                                              /*!< TIMER_T::PWMCTL: DBGTRIOFF Position    */
+#define TIMER_PWMCTL_DBGTRIOFF_Msk       (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos)             /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask        */
+
+#define TIMER_PWMCLKSRC_CLKSRC_Pos       (0)                                               /*!< TIMER_T::PWMCLKSRC: CLKSRC Position    */
+#define TIMER_PWMCLKSRC_CLKSRC_Msk       (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos)             /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask        */
+
+#define TIMER_PWMCLKPSC_CLKPSC_Pos       (0)                                               /*!< TIMER_T::PWMCLKPSC: CLKPSC Position    */
+#define TIMER_PWMCLKPSC_CLKPSC_Msk       (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos)           /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask        */
+
+#define TIMER_PWMCNTCLR_CNTCLR_Pos       (0)                                               /*!< TIMER_T::PWMCNTCLR: CNTCLR Position    */
+#define TIMER_PWMCNTCLR_CNTCLR_Msk       (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos)             /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask        */
+
+#define TIMER_PWMPERIOD_PERIOD_Pos       (0)                                               /*!< TIMER_T::PWMPERIOD: PERIOD Position    */
+#define TIMER_PWMPERIOD_PERIOD_Msk       (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos)          /*!< TIMER_T::PWMPERIOD: PERIOD Mask        */
+
+#define TIMER_PWMCMPDAT_CMP_Pos          (0)                                               /*!< TIMER_T::PWMCMPDAT: CMP Position       */
+#define TIMER_PWMCMPDAT_CMP_Msk          (0xfffful << TIMER_PWMCMPDAT_CMP_Pos)             /*!< TIMER_T::PWMCMPDAT: CMP Mask           */
+
+#define TIMER_PWMDTCTL_DTCNT_Pos         (0)                                               /*!< TIMER_T::PWMDTCTL: DTCNT Position      */
+#define TIMER_PWMDTCTL_DTCNT_Msk         (0xffful << TIMER_PWMDTCTL_DTCNT_Pos)             /*!< TIMER_T::PWMDTCTL: DTCNT Mask          */
+
+#define TIMER_PWMDTCTL_DTEN_Pos          (16)                                              /*!< TIMER_T::PWMDTCTL: DTEN Position       */
+#define TIMER_PWMDTCTL_DTEN_Msk          (0x1ul << TIMER_PWMDTCTL_DTEN_Pos)                /*!< TIMER_T::PWMDTCTL: DTEN Mask           */
+
+#define TIMER_PWMDTCTL_DTCKSEL_Pos       (24)                                              /*!< TIMER_T::PWMDTCTL: DTCKSEL Position    */
+#define TIMER_PWMDTCTL_DTCKSEL_Msk       (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos)             /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask        */
+
+#define TIMER_PWMCNT_CNT_Pos             (0)                                               /*!< TIMER_T::PWMCNT: CNT Position          */
+#define TIMER_PWMCNT_CNT_Msk             (0xfffful << TIMER_PWMCNT_CNT_Pos)                /*!< TIMER_T::PWMCNT: CNT Mask              */
+
+#define TIMER_PWMCNT_DIRF_Pos            (16)                                              /*!< TIMER_T::PWMCNT: DIRF Position         */
+#define TIMER_PWMCNT_DIRF_Msk            (0x1ul << TIMER_PWMCNT_DIRF_Pos)                  /*!< TIMER_T::PWMCNT: DIRF Mask             */
+
+#define TIMER_PWMMSKEN_MSKEN0_Pos        (0)                                               /*!< TIMER_T::PWMMSKEN: MSKEN0 Position     */
+#define TIMER_PWMMSKEN_MSKEN0_Msk        (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos)              /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask         */
+
+#define TIMER_PWMMSKEN_MSKEN1_Pos        (1)                                               /*!< TIMER_T::PWMMSKEN: MSKEN1 Position     */
+#define TIMER_PWMMSKEN_MSKEN1_Msk        (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos)              /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask         */
+
+#define TIMER_PWMMSK_MSKDAT0_Pos         (0)                                               /*!< TIMER_T::PWMMSK: MSKDAT0 Position      */
+#define TIMER_PWMMSK_MSKDAT0_Msk         (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos)               /*!< TIMER_T::PWMMSK: MSKDAT0 Mask          */
+
+#define TIMER_PWMMSK_MSKDAT1_Pos         (1)                                               /*!< TIMER_T::PWMMSK: MSKDAT1 Position      */
+#define TIMER_PWMMSK_MSKDAT1_Msk         (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos)               /*!< TIMER_T::PWMMSK: MSKDAT1 Mask          */
+
+#define TIMER_PWMBNF_BRKNFEN_Pos         (0)                                               /*!< TIMER_T::PWMBNF: BRKNFEN Position      */
+#define TIMER_PWMBNF_BRKNFEN_Msk         (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos)               /*!< TIMER_T::PWMBNF: BRKNFEN Mask          */
+
+#define TIMER_PWMBNF_BRKNFSEL_Pos        (1)                                               /*!< TIMER_T::PWMBNF: BRKNFSEL Position     */
+#define TIMER_PWMBNF_BRKNFSEL_Msk        (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos)              /*!< TIMER_T::PWMBNF: BRKNFSEL Mask         */
+
+#define TIMER_PWMBNF_BRKFCNT_Pos         (4)                                               /*!< TIMER_T::PWMBNF: BRKFCNT Position      */
+#define TIMER_PWMBNF_BRKFCNT_Msk         (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos)               /*!< TIMER_T::PWMBNF: BRKFCNT Mask          */
+
+#define TIMER_PWMBNF_BRKPINV_Pos         (7)                                               /*!< TIMER_T::PWMBNF: BRKPINV Position      */
+#define TIMER_PWMBNF_BRKPINV_Msk         (0x1ul << TIMER_PWMBNF_BRKPINV_Pos)               /*!< TIMER_T::PWMBNF: BRKPINV Mask          */
+
+#define TIMER_PWMBNF_BKPINSRC_Pos        (16)                                              /*!< TIMER_T::PWMBNF: BKPINSRC Position     */
+#define TIMER_PWMBNF_BKPINSRC_Msk        (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos)              /*!< TIMER_T::PWMBNF: BKPINSRC Mask         */
+
+#define TIMER_PWMFAILBRK_CSSBRKEN_Pos    (0)                                               /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */
+#define TIMER_PWMFAILBRK_CSSBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_BODBRKEN_Pos    (1)                                               /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */
+#define TIMER_PWMFAILBRK_BODBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_RAMBRKEN_Pos    (2)                                               /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */
+#define TIMER_PWMFAILBRK_RAMBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_CORBRKEN_Pos    (3)                                               /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */
+#define TIMER_PWMFAILBRK_CORBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask     */
+
+#define TIMER_PWMBRKCTL_CPO0EBEN_Pos     (0)                                               /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position  */
+#define TIMER_PWMBRKCTL_CPO0EBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask      */
+
+#define TIMER_PWMBRKCTL_CPO1EBEN_Pos     (1)                                               /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position  */
+#define TIMER_PWMBRKCTL_CPO1EBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKPEEN_Pos      (4)                                               /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position   */
+#define TIMER_PWMBRKCTL_BRKPEEN_Msk      (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask       */
+
+#define TIMER_PWMBRKCTL_SYSEBEN_Pos      (7)                                               /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position   */
+#define TIMER_PWMBRKCTL_SYSEBEN_Msk      (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos)            /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask       */
+
+#define TIMER_PWMBRKCTL_CPO0LBEN_Pos     (8)                                               /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position  */
+#define TIMER_PWMBRKCTL_CPO0LBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask      */
+
+#define TIMER_PWMBRKCTL_CPO1LBEN_Pos     (9)                                               /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position  */
+#define TIMER_PWMBRKCTL_CPO1LBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKPLEN_Pos      (12)                                              /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position   */
+#define TIMER_PWMBRKCTL_BRKPLEN_Msk      (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask       */
+
+#define TIMER_PWMBRKCTL_SYSLBEN_Pos      (15)                                              /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position   */
+#define TIMER_PWMBRKCTL_SYSLBEN_Msk      (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos)            /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask       */
+
+#define TIMER_PWMBRKCTL_BRKAEVEN_Pos     (16)                                              /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position  */
+#define TIMER_PWMBRKCTL_BRKAEVEN_Msk     (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos)           /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKAODD_Pos      (18)                                              /*!< TIMER_T::PWMBRKCTL: BRKAODD Position   */
+#define TIMER_PWMBRKCTL_BRKAODD_Msk      (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask       */
+
+#define TIMER_PWMPOLCTL_PINV0_Pos        (0)                                               /*!< TIMER_T::PWMPOLCTL: PINV0 Position     */
+#define TIMER_PWMPOLCTL_PINV0_Msk        (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos)              /*!< TIMER_T::PWMPOLCTL: PINV0 Mask         */
+
+#define TIMER_PWMPOLCTL_PINV1_Pos        (1)                                               /*!< TIMER_T::PWMPOLCTL: PINV1 Position     */
+#define TIMER_PWMPOLCTL_PINV1_Msk        (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos)              /*!< TIMER_T::PWMPOLCTL: PINV1 Mask         */
+
+#define TIMER_PWMPOEN_POEN0_Pos          (0)                                               /*!< TIMER_T::PWMPOEN: POEN0 Position       */
+#define TIMER_PWMPOEN_POEN0_Msk          (0x1ul << TIMER_PWMPOEN_POEN0_Pos)                /*!< TIMER_T::PWMPOEN: POEN0 Mask           */
+
+#define TIMER_PWMPOEN_POEN1_Pos          (1)                                               /*!< TIMER_T::PWMPOEN: POEN1 Position       */
+#define TIMER_PWMPOEN_POEN1_Msk          (0x1ul << TIMER_PWMPOEN_POEN1_Pos)                /*!< TIMER_T::PWMPOEN: POEN1 Mask           */
+
+#define TIMER_PWMSWBRK_BRKETRG_Pos       (0)                                               /*!< TIMER_T::PWMSWBRK: BRKETRG Position    */
+#define TIMER_PWMSWBRK_BRKETRG_Msk       (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos)             /*!< TIMER_T::PWMSWBRK: BRKETRG Mask        */
+
+#define TIMER_PWMSWBRK_BRKLTRG_Pos       (8)                                               /*!< TIMER_T::PWMSWBRK: BRKLTRG Position    */
+#define TIMER_PWMSWBRK_BRKLTRG_Msk       (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos)             /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask        */
+
+#define TIMER_PWMINTEN0_ZIEN_Pos         (0)                                               /*!< TIMER_T::PWMINTEN0: ZIEN Position      */
+#define TIMER_PWMINTEN0_ZIEN_Msk         (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos)               /*!< TIMER_T::PWMINTEN0: ZIEN Mask          */
+
+#define TIMER_PWMINTEN0_PIEN_Pos         (1)                                               /*!< TIMER_T::PWMINTEN0: PIEN Position      */
+#define TIMER_PWMINTEN0_PIEN_Msk         (0x1ul << TIMER_PWMINTEN0_PIEN_Pos)               /*!< TIMER_T::PWMINTEN0: PIEN Mask          */
+
+#define TIMER_PWMINTEN0_CMPUIEN_Pos      (2)                                               /*!< TIMER_T::PWMINTEN0: CMPUIEN Position   */
+#define TIMER_PWMINTEN0_CMPUIEN_Msk      (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos)            /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask       */
+
+#define TIMER_PWMINTEN0_CMPDIEN_Pos      (3)                                               /*!< TIMER_T::PWMINTEN0: CMPDIEN Position   */
+#define TIMER_PWMINTEN0_CMPDIEN_Msk      (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos)            /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask       */
+
+#define TIMER_PWMINTEN1_BRKEIEN_Pos      (0)                                               /*!< TIMER_T::PWMINTEN1: BRKEIEN Position   */
+#define TIMER_PWMINTEN1_BRKEIEN_Msk      (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos)            /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask       */
+
+#define TIMER_PWMINTEN1_BRKLIEN_Pos      (8)                                               /*!< TIMER_T::PWMINTEN1: BRKLIEN Position   */
+#define TIMER_PWMINTEN1_BRKLIEN_Msk      (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos)            /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask       */
+
+#define TIMER_PWMINTSTS0_ZIF_Pos         (0)                                               /*!< TIMER_T::PWMINTSTS0: ZIF Position      */
+#define TIMER_PWMINTSTS0_ZIF_Msk         (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos)               /*!< TIMER_T::PWMINTSTS0: ZIF Mask          */
+
+#define TIMER_PWMINTSTS0_PIF_Pos         (1)                                               /*!< TIMER_T::PWMINTSTS0: PIF Position      */
+#define TIMER_PWMINTSTS0_PIF_Msk         (0x1ul << TIMER_PWMINTSTS0_PIF_Pos)               /*!< TIMER_T::PWMINTSTS0: PIF Mask          */
+
+#define TIMER_PWMINTSTS0_CMPUIF_Pos      (2)                                               /*!< TIMER_T::PWMINTSTS0: CMPUIF Position   */
+#define TIMER_PWMINTSTS0_CMPUIF_Msk      (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos)            /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask       */
+
+#define TIMER_PWMINTSTS0_CMPDIF_Pos      (3)                                               /*!< TIMER_T::PWMINTSTS0: CMPDIF Position   */
+#define TIMER_PWMINTSTS0_CMPDIF_Msk      (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos)            /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask       */
+
+#define TIMER_PWMINTSTS1_BRKEIF0_Pos     (0)                                               /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position  */
+#define TIMER_PWMINTSTS1_BRKEIF0_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKEIF1_Pos     (1)                                               /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position  */
+#define TIMER_PWMINTSTS1_BRKEIF1_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKLIF0_Pos     (8)                                               /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position  */
+#define TIMER_PWMINTSTS1_BRKLIF0_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKLIF1_Pos     (9)                                               /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position  */
+#define TIMER_PWMINTSTS1_BRKLIF1_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKESTS0_Pos    (16)                                              /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */
+#define TIMER_PWMINTSTS1_BRKESTS0_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKESTS1_Pos    (17)                                              /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */
+#define TIMER_PWMINTSTS1_BRKESTS1_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKLSTS0_Pos    (24)                                              /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS0_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKLSTS1_Pos    (25)                                              /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS1_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask     */
+
+#define TIMER_PWMEADCTS_TRGSEL_Pos       (0)                                               /*!< TIMER_T::PWMEADCTS: TRGSEL Position    */
+#define TIMER_PWMEADCTS_TRGSEL_Msk       (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos)             /*!< TIMER_T::PWMEADCTS: TRGSEL Mask        */
+
+#define TIMER_PWMEADCTS_TRGEN_Pos        (7)                                               /*!< TIMER_T::PWMEADCTS: TRGEN Position     */
+#define TIMER_PWMEADCTS_TRGEN_Msk        (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos)              /*!< TIMER_T::PWMEADCTS: TRGEN Mask         */
+
+#define TIMER_PWMSCTL_SYNCMODE_Pos       (0)                                               /*!< TIMER_T::PWMSCTL: SYNCMODE Position    */
+#define TIMER_PWMSCTL_SYNCMODE_Msk       (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos)             /*!< TIMER_T::PWMSCTL: SYNCMODE Mask        */
+
+#define TIMER_PWMSCTL_SYNCSRC_Pos        (8)                                               /*!< TIMER_T::PWMSCTL: SYNCSRC Position     */
+#define TIMER_PWMSCTL_SYNCSRC_Msk        (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos)              /*!< TIMER_T::PWMSCTL: SYNCSRC Mask         */
+
+#define TIMER_PWMSTRG_STRGEN_Pos         (0)                                               /*!< TIMER_T::PWMSTRG: STRGEN Position      */
+#define TIMER_PWMSTRG_STRGEN_Msk         (0x1ul << TIMER_PWMSTRG_STRGEN_Pos)               /*!< TIMER_T::PWMSTRG: STRGEN Mask          */
+
+#define TIMER_PWMSTATUS_CNTMAXF_Pos      (0)                                               /*!< TIMER_T::PWMSTATUS: CNTMAXF Position   */
+#define TIMER_PWMSTATUS_CNTMAXF_Msk      (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos)            /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask       */
+
+#define TIMER_PWMSTATUS_EADCTRGF_Pos     (16)                                              /*!< TIMER_T::PWMSTATUS: EADCTRGF Position  */
+#define TIMER_PWMSTATUS_EADCTRGF_Msk     (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos)           /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask      */
+
+#define TIMER_PWMPBUF_PBUF_Pos           (0)                                               /*!< TIMER_T::PWMPBUF: PBUF Position        */
+#define TIMER_PWMPBUF_PBUF_Msk           (0xfffful << TIMER_PWMPBUF_PBUF_Pos)              /*!< TIMER_T::PWMPBUF: PBUF Mask            */
+
+#define TIMER_PWMCMPBUF_CMPBUF_Pos       (0)                                               /*!< TIMER_T::PWMCMPBUF: CMPBUF Position    */
+#define TIMER_PWMCMPBUF_CMPBUF_Msk       (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos)          /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask        */
+
+/**@}*/ /* TIMER_CONST */
+/**@}*/ /* end of TIMER register group */
+
+
+
+/*---------------------- Watch Dog Timer Controller -------------------------*/
+/**
+    @addtogroup WDT Watch Dog Timer Controller(WDT)
+    Memory Mapped Structure for WDT Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var WDT_T::CTL
+     * Offset: 0x00  WDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RSTCNT    |Reset WDT Up Counter (Write Protect)
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the internal 18-bit WDT up counter value.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit will be automatically cleared by hardware.
+     * |[1]     |RSTEN     |WDT Time-out Reset Enable Control (Write Protect)
+     * |        |          |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+     * |        |          |0 = WDT time-out reset function Disabled.
+     * |        |          |1 = WDT time-out reset function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |RSTF      |WDT Time-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by WDT time-out reset or not.
+     * |        |          |0 = WDT time-out reset did not occur.
+     * |        |          |1 = WDT time-out reset occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |IF        |WDT Time-out Interrupt Flag
+     * |        |          |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+     * |        |          |0 = WDT time-out interrupt did not occur.
+     * |        |          |1 = WDT time-out interrupt occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[4]     |WKEN      |WDT Time-out Wake-up Function Control (Write Protect)
+     * |        |          |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
+     * |        |          |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
+     * |        |          |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
+     * |[5]     |WKF       |WDT Time-out Wake-up Flag (Write Protect)
+     * |        |          |This bit indicates the interrupt wake-up flag status of WDT
+     * |        |          |0 = WDT does not cause chip wake-up.
+     * |        |          |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[6]     |INTEN     |WDT Time-out Interrupt Enable Control (Write Protect)
+     * |        |          |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WDT time-out interrupt Disabled.
+     * |        |          |1 = WDT time-out interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |WDTEN     |WDT Enable Control (Write Protect)
+     * |        |          |0 = WDT Disabled (This action will reset the internal up counter value).
+     * |        |          |1 = WDT Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
+     * |[10:8]  |TOUTSEL   |WDT Time-out Interval Selection (Write Protect)
+     * |        |          |These three bits select the time-out interval period for the WDT.
+     * |        |          |000 = 24 * WDT_CLK.
+     * |        |          |001 = 26 * WDT_CLK.
+     * |        |          |010 = 28 * WDT_CLK.
+     * |        |          |011 = 210 * WDT_CLK.
+     * |        |          |100 = 212 * WDT_CLK.
+     * |        |          |101 = 214 * WDT_CLK.
+     * |        |          |110 = 216 * WDT_CLK.
+     * |        |          |111 = 218 * WDT_CLK.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[30]    |SYNC      |WDT Enable Control SYNC Flag Indicator (Read Only)
+     * |        |          |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
+     * |        |          |0 = Set WDTEN bit is completed.
+     * |        |          |1 = Set WDTEN bit is synchronizing and not become active yet..
+     * |        |          |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement affects WDT counting.
+     * |        |          |WDT up counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |WDT up counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var WDT_T::ALTCTL
+     * Offset: 0x04  WDT Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RSTDSEL   |WDT Reset Delay Selection (Write Protect)
+     * |        |          |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened
+     * |        |          |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
+     * |        |          |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+     * |        |          |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+     * |        |          |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+     * |        |          |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This register will be reset to 0 if WDT time-out reset happened.
+     * @var WDT_T::RSTCNT
+     * Offset: 0x08  WDT Reset Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RSTCNT    |WDT Reset Counter Register
+     * |        |          |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
+     * |        |          |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
+     * |        |          |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit
+     * |        |          |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] WDT Control Register                                             */
+    __IO uint32_t ALTCTL;                /*!< [0x0004] WDT Alternative Control Register                                 */
+    __O  uint32_t RSTCNT;                /*!< [0x0008] WDT Reset Counter Register                                       */
+
+} WDT_T;
+
+/**
+    @addtogroup WDT_CONST WDT Bit Field Definition
+    Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_RSTCNT_Pos               (0)                                               /*!< WDT_T::CTL: RSTCNT Position            */
+#define WDT_CTL_RSTCNT_Msk               (0x1ul << WDT_CTL_RSTCNT_Pos)                     /*!< WDT_T::CTL: RSTCNT Mask                */
+
+#define WDT_CTL_RSTEN_Pos                (1)                                               /*!< WDT_T::CTL: RSTEN Position             */
+#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)                      /*!< WDT_T::CTL: RSTEN Mask                 */
+
+#define WDT_CTL_RSTF_Pos                 (2)                                               /*!< WDT_T::CTL: RSTF Position              */
+#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)                       /*!< WDT_T::CTL: RSTF Mask                  */
+
+#define WDT_CTL_IF_Pos                   (3)                                               /*!< WDT_T::CTL: IF Position                */
+#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)                         /*!< WDT_T::CTL: IF Mask                    */
+
+#define WDT_CTL_WKEN_Pos                 (4)                                               /*!< WDT_T::CTL: WKEN Position              */
+#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)                       /*!< WDT_T::CTL: WKEN Mask                  */
+
+#define WDT_CTL_WKF_Pos                  (5)                                               /*!< WDT_T::CTL: WKF Position               */
+#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)                        /*!< WDT_T::CTL: WKF Mask                   */
+
+#define WDT_CTL_INTEN_Pos                (6)                                               /*!< WDT_T::CTL: INTEN Position             */
+#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)                      /*!< WDT_T::CTL: INTEN Mask                 */
+
+#define WDT_CTL_WDTEN_Pos                (7)                                               /*!< WDT_T::CTL: WDTEN Position             */
+#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)                      /*!< WDT_T::CTL: WDTEN Mask                 */
+
+#define WDT_CTL_TOUTSEL_Pos              (8)                                               /*!< WDT_T::CTL: TOUTSEL Position           */
+#define WDT_CTL_TOUTSEL_Msk              (0x7ul << WDT_CTL_TOUTSEL_Pos)                    /*!< WDT_T::CTL: TOUTSEL Mask               */
+
+#define WDT_CTL_SYNC_Pos                 (30)                                              /*!< WDT_T::CTL: SYNC Position              */
+#define WDT_CTL_SYNC_Msk                 (0x1ul << WDT_CTL_SYNC_Pos)                       /*!< WDT_T::CTL: SYNC Mask                  */
+
+#define WDT_CTL_ICEDEBUG_Pos             (31)                                              /*!< WDT_T::CTL: ICEDEBUG Position          */
+#define WDT_CTL_ICEDEBUG_Msk             (0x1ul << WDT_CTL_ICEDEBUG_Pos)                   /*!< WDT_T::CTL: ICEDEBUG Mask              */
+
+#define WDT_ALTCTL_RSTDSEL_Pos           (0)                                               /*!< WDT_T::ALTCTL: RSTDSEL Position        */
+#define WDT_ALTCTL_RSTDSEL_Msk           (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)                 /*!< WDT_T::ALTCTL: RSTDSEL Mask            */
+
+#define WDT_RSTCNT_RSTCNT_Pos            (0)                                               /*!< WDT_T::RSTCNT: RSTCNT Position         */
+#define WDT_RSTCNT_RSTCNT_Msk            (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos)           /*!< WDT_T::RSTCNT: RSTCNT Mask             */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+
+
+/*---------------------- Window Watchdog Timer -------------------------*/
+/**
+    @addtogroup WWDT Window Watchdog Timer(WWDT)
+    Memory Mapped Structure for WWDT Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var WWDT_T::RLDCNT
+     * Offset: 0x00  WWDT Reload Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RLDCNT    |WWDT Reload Counter Register
+     * |        |          |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
+     * |        |          |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
+     * @var WWDT_T::CTL
+     * Offset: 0x04  WWDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTEN    |WWDT Enable Control Bit
+     * |        |          |Set this bit to enable WWDT counter counting.
+     * |        |          |0 = WWDT counter is stopped.
+     * |        |          |1 = WWDT counter is starting counting.
+     * |[1]     |INTEN     |WWDT Interrupt Enable Control Bit
+     * |        |          |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WWDT counter compare match interrupt Disabled.
+     * |        |          |1 = WWDT counter compare match interrupt Enabled.
+     * |[11:8]  |PSCSEL    |WWDT Counter Prescale Period Selection
+     * |        |          |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
+     * |        |          |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
+     * |        |          |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
+     * |        |          |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
+     * |        |          |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
+     * |        |          |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
+     * |        |          |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
+     * |        |          |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
+     * |        |          |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
+     * |        |          |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
+     * |        |          |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
+     * |        |          |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
+     * |        |          |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
+     * |        |          |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
+     * |        |          |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
+     * |        |          |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
+     * |[21:16] |CMPDAT    |WWDT Window Compare Register
+     * |        |          |Set this register to adjust the valid reload window.
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
+     * |        |          |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+     * |        |          |0 = ICE debug mode acknowledgement effects WWDT counting.
+     * |        |          |WWDT down counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |WWDT down counter will keep going no matter CPU is held by ICE or not.
+     * @var WWDT_T::STATUS
+     * Offset: 0x08  WWDT Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTIF    |WWDT Compare Match Interrupt Flag
+     * |        |          |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+     * |        |          |0 = No effect.
+     * |        |          |1 = WWDT counter value matches CMPDAT.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |WWDTRF    |WWDT Timer-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by WWDT time-out reset or not.
+     * |        |          |0 = WWDT time-out reset did not occur.
+     * |        |          |1 = WWDT time-out reset occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var WWDT_T::CNT
+     * Offset: 0x0C  WWDT Counter Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CNTDAT    |WWDT Counter Value
+     * |        |          |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+     */
+    __O  uint32_t RLDCNT;                /*!< [0x0000] WWDT Reload Counter Register                                     */
+    __IO uint32_t CTL;                   /*!< [0x0004] WWDT Control Register                                            */
+    __IO uint32_t STATUS;                /*!< [0x0008] WWDT Status Register                                             */
+    __I  uint32_t CNT;                   /*!< [0x000c] WWDT Counter Value Register                                      */
+
+} WWDT_T;
+
+/**
+    @addtogroup WWDT_CONST WWDT Bit Field Definition
+    Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLDCNT_RLDCNT_Pos           (0)                                               /*!< WWDT_T::RLDCNT: RLDCNT Position        */
+#define WWDT_RLDCNT_RLDCNT_Msk           (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)          /*!< WWDT_T::RLDCNT: RLDCNT Mask            */
+
+#define WWDT_CTL_WWDTEN_Pos              (0)                                               /*!< WWDT_T::CTL: WWDTEN Position           */
+#define WWDT_CTL_WWDTEN_Msk              (0x1ul << WWDT_CTL_WWDTEN_Pos)                    /*!< WWDT_T::CTL: WWDTEN Mask               */
+
+#define WWDT_CTL_INTEN_Pos               (1)                                               /*!< WWDT_T::CTL: INTEN Position            */
+#define WWDT_CTL_INTEN_Msk               (0x1ul << WWDT_CTL_INTEN_Pos)                     /*!< WWDT_T::CTL: INTEN Mask                */
+
+#define WWDT_CTL_PSCSEL_Pos              (8)                                               /*!< WWDT_T::CTL: PSCSEL Position           */
+#define WWDT_CTL_PSCSEL_Msk              (0xful << WWDT_CTL_PSCSEL_Pos)                    /*!< WWDT_T::CTL: PSCSEL Mask               */
+
+#define WWDT_CTL_CMPDAT_Pos              (16)                                              /*!< WWDT_T::CTL: CMPDAT Position           */
+#define WWDT_CTL_CMPDAT_Msk              (0x3ful << WWDT_CTL_CMPDAT_Pos)                   /*!< WWDT_T::CTL: CMPDAT Mask               */
+
+#define WWDT_CTL_ICEDEBUG_Pos            (31)                                              /*!< WWDT_T::CTL: ICEDEBUG Position         */
+#define WWDT_CTL_ICEDEBUG_Msk            (0x1ul << WWDT_CTL_ICEDEBUG_Pos)                  /*!< WWDT_T::CTL: ICEDEBUG Mask             */
+
+#define WWDT_STATUS_WWDTIF_Pos           (0)                                               /*!< WWDT_T::STATUS: WWDTIF Position        */
+#define WWDT_STATUS_WWDTIF_Msk           (0x1ul << WWDT_STATUS_WWDTIF_Pos)                 /*!< WWDT_T::STATUS: WWDTIF Mask            */
+
+#define WWDT_STATUS_WWDTRF_Pos           (1)                                               /*!< WWDT_T::STATUS: WWDTRF Position        */
+#define WWDT_STATUS_WWDTRF_Msk           (0x1ul << WWDT_STATUS_WWDTRF_Pos)                 /*!< WWDT_T::STATUS: WWDTRF Mask            */
+
+#define WWDT_CNT_CNTDAT_Pos              (0)                                               /*!< WWDT_T::CNT: CNTDAT Position           */
+#define WWDT_CNT_CNTDAT_Msk              (0x3ful << WWDT_CNT_CNTDAT_Pos)                   /*!< WWDT_T::CNT: CNTDAT Mask               */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+
+
+/*---------------------- Real Time Clock Controller -------------------------*/
+/**
+    @addtogroup RTC Real Time Clock Controller(RTC)
+    Memory Mapped Structure for RTC Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var RTC_T::INIT
+     * Offset: 0x00  RTC Initiation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INIT_ACTIVE|RTC Active Status (Read Only)
+     * |        |          |0 = RTC is at reset state.
+     * |        |          |1 = RTC is at normal active state.
+     * |[31:1]  |INIT      |RTC Initiation (Write Only)
+     * |        |          |When RTC block is powered on, RTC is at reset state
+     * |        |          |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state
+     * |        |          |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+     * |        |          |The INIT is a write-only field and read value will be always 0.
+     * @var RTC_T::RWEN
+     * Offset: 0x04  RTC Access Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[16]    |RWENF     |RTC Register Access Enable Flag (Read Only)
+     * |        |          |0 = RTC register read/write Disabled.
+     * |        |          |1 = RTC register read/write Enabled.
+     * |        |          |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
+     * |[24]    |RTCBUSY   |RTC Write Busy Flag
+     * |        |          |This bit indicates RTC registers are writable or not.
+     * |        |          |0: RTC registers are writable.
+     * |        |          |1: RTC registers can't write, RTC under Busy Status.
+     * |        |          |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
+     * @var RTC_T::FREQADJ
+     * Offset: 0x08  RTC Frequency Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[21:0]  |FREQADJ   |Frequency Compensation Register
+     * |        |          |User must to get actual LXT frequency for RTC application.
+     * |        |          |FCR = 0x200000 * (32768 / LXT frequency).
+     * |        |          |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
+     * @var RTC_T::TIME
+     * Offset: 0x0C  RTC Time Loading Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit (0~2)
+     * |        |          |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+     * |        |          |(If RTC_TIME[21] is 1, it indicates PM time message).
+     * @var RTC_T::CAL
+     * Offset: 0x10  RTC Calendar Loading Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit (0~9)
+     * @var RTC_T::CLKFMT
+     * Offset: 0x14  RTC Time Scale Selection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |24HEN     |24-hour / 12-hour Time Scale Selection
+     * |        |          |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
+     * |        |          |0 = 12-hour time scale with AM and PM indication selected.
+     * |        |          |1 = 24-hour time scale selected.
+     * @var RTC_T::WEEKDAY
+     * Offset: 0x18  RTC Day of the Week Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |WEEKDAY   |Day of the Week Register
+     * |        |          |000 = Sunday.
+     * |        |          |001 = Monday.
+     * |        |          |010 = Tuesday.
+     * |        |          |011 = Wednesday.
+     * |        |          |100 = Thursday.
+     * |        |          |101 = Friday.
+     * |        |          |110 = Saturday.
+     * |        |          |111 = Reserved.
+     * @var RTC_T::TALM
+     * Offset: 0x1C  RTC Time Alarm Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit of Alarm Setting (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit of Alarm Setting (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit of Alarm Setting (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit of Alarm Setting (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit of Alarm Setting (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit of Alarm Setting (0~2)
+     * |        |          |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+     * |        |          |(If RTC_TIME[21] is 1, it indicates PM time message).
+     * @var RTC_T::CALM
+     * Offset: 0x20  RTC Calendar Alarm Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit of Alarm Setting (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit of Alarm Setting (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit of Alarm Setting (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit of Alarm Setting (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit of Alarm Setting (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit of Alarm Setting (0~9)
+     * @var RTC_T::LEAPYEAR
+     * Offset: 0x24  RTC Leap Year Indicator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LEAPYEAR  |Leap Year Indication Register (Read Only)
+     * |        |          |0 = This year is not a leap year.
+     * |        |          |1 = This year is leap year.
+     * @var RTC_T::INTEN
+     * Offset: 0x28  RTC Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ALMIEN    |Alarm Interrupt Enable Bit
+     * |        |          |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
+     * |        |          |0 = RTC Alarm interrupt Disabled.
+     * |        |          |1 = RTC Alarm interrupt Enabled.
+     * |[1]     |TICKIEN   |Time Tick Interrupt Enable Bit
+     * |        |          |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
+     * |        |          |0 = RTC Time Tick interrupt Disabled.
+     * |        |          |1 = RTC Time Tick interrupt Enabled.
+     * |[8]     |TAMP0IEN  |Tamper 0 Interrupt Enable Bit
+     * |        |          |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
+     * |        |          |0 = Tamper 0 interrupt Disabled.
+     * |        |          |1 = Tamper 0 interrupt Enabled.
+     * |[9]     |TAMP1IEN  |Tamper 1 or Pair 0 Interrupt Enable Bit
+     * |        |          |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
+     * |        |          |0 = Tamper 1 or Pair 0 interrupt Disabled.
+     * |        |          |1 = Tamper 1 or Pair 0 interrupt Enabled.
+     * |[10]    |TAMP2IEN  |Tamper 2 Interrupt Enable Bit
+     * |        |          |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
+     * |        |          |0 = Tamper 2 interrupt Disabled.
+     * |        |          |1 = Tamper 2 interrupt Enabled.
+     * |[11]    |TAMP3IEN  |Tamper 3 or Pair 1 Interrupt Enable Bit
+     * |        |          |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
+     * |        |          |0 = Tamper 3 or Pair 1 interrupt Disabled.
+     * |        |          |1 = Tamper 3 or Pair 1 interrupt Enabled.
+     * |[12]    |TAMP4IEN  |Tamper 4 Interrupt Enable Bit
+     * |        |          |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
+     * |        |          |0 = Tamper 4 interrupt Disabled.
+     * |        |          |1 = Tamper 4 interrupt Enabled.
+     * |[13]    |TAMP5IEN  |Tamper 5 or Pair 2 Interrupt Enable Bit
+     * |        |          |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
+     * |        |          |0 = Tamper 5 or Pair 2 interrupt Disabled.
+     * |        |          |1 = Tamper 5 or Pair 2 interrupt Enabled.
+     * @var RTC_T::INTSTS
+     * Offset: 0x2C  RTC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ALMIF     |RTC Alarm Interrupt Flag
+     * |        |          |0 = Alarm condition is not matched.
+     * |        |          |1 = Alarm condition is matched.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[1]     |TICKIF    |RTC Time Tick Interrupt Flag
+     * |        |          |0 = Tick condition does not occur.
+     * |        |          |1 = Tick condition occur.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[8]     |TAMP0IF   |Tamper 0 Interrupt Flag
+     * |        |          |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).
+     * |        |          |0 = No Tamper 0 interrupt flag is generated.
+     * |        |          |1 = Tamper 0 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * |[9]     |TAMP1IF   |Tamper 1 or Pair 0 Interrupt Flag
+     * |        |          |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13])
+     * |        |          |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.
+     * |        |          |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
+     * |        |          |1 = Tamper 1 or Pair 0 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * |[10]    |TAMP2IF   |Tamper 2 Interrupt Flag
+     * |        |          |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).
+     * |        |          |0 = No Tamper 2 interrupt flag is generated.
+     * |        |          |1 = Tamper 2 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * |[11]    |TAMP3IF   |Tamper 3 or Pair 1 Interrupt Flag
+     * |        |          |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21])
+     * |        |          |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated
+     * |        |          |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.
+     * |        |          |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
+     * |        |          |1 = Tamper 3 or Pair 1 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * |[12]    |TAMP4IF   |Tamper 4 Interrupt Flag
+     * |        |          |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).
+     * |        |          |0 = No Tamper 4 interrupt flag is generated.
+     * |        |          |1 = Tamper 4 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * |[13]    |TAMP5IF   |Tamper 5 or Pair 2 Interrupt Flag
+     * |        |          |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29])
+     * |        |          |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated
+     * |        |          |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.
+     * |        |          |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
+     * |        |          |1 = Tamper 5 or Pair 2 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+     * @var RTC_T::TICK
+     * Offset: 0x30  RTC Time Tick Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TICK      |Time Tick Register
+     * |        |          |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+     * |        |          |000 = Time tick is 1 second.
+     * |        |          |001 = Time tick is 1/2 second.
+     * |        |          |010 = Time tick is 1/4 second.
+     * |        |          |011 = Time tick is 1/8 second.
+     * |        |          |100 = Time tick is 1/16 second.
+     * |        |          |101 = Time tick is 1/32 second.
+     * |        |          |110 = Time tick is 1/64 second.
+     * |        |          |111 = Time tick is 1/128 second.
+     * |        |          |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
+     * @var RTC_T::TAMSK
+     * Offset: 0x34  RTC Time Alarm Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSEC      |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+     * |[1]     |MTENSEC   |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+     * |[2]     |MMIN      |Mask 1-Min Time Digit of Alarm Setting (0~9)
+     * |[3]     |MTENMIN   |Mask 10-Min Time Digit of Alarm Setting (0~5)
+     * |[4]     |MHR       |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+     * |[5]     |MTENHR    |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+     * @var RTC_T::CAMSK
+     * Offset: 0x38  RTC Calendar Alarm Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MDAY      |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+     * |[1]     |MTENDAY   |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+     * |[2]     |MMON      |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+     * |[3]     |MTENMON   |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+     * |[4]     |MYEAR     |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+     * |[5]     |MTENYEAR  |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+     * @var RTC_T::SPRCTL
+     * Offset: 0x3C  RTC Spare Functional Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |SPRRWEN   |Spare Register Enable Bit
+     * |        |          |0 = Spare register is Disabled.
+     * |        |          |1 = Spare register is Enabled.
+     * |        |          |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+     * |[5]     |SPRCSTS   |SPR Clear Flag
+     * |        |          |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.
+     * |        |          |0 = Spare register content is not cleared.
+     * |        |          |1 = Spare register content is cleared.
+     * |        |          |Writes 1 to clear this bit.
+     * |        |          |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero.
+     * @var RTC_T::SPR[20]
+     * Offset: 0x40 ~ 0x8C  RTC Spare Register 0 ~ 19
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SPARE     |Spare Register
+     * |        |          |This field is used to store back-up information defined by user.
+     * |        |          |This field will be cleared by hardware automatically once a tamper pin event is detected.
+     * |        |          |Before storing back-up information in to RTC_SPRx register,
+     * |        |          |user should check REWNF (RTC_RWEN[16]) is enabled.
+     * @var RTC_T::LXTCTL
+     * Offset: 0x100  RTC 32.768 kHz Oscillator Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:1]   |GAIN      |Oscillator Gain Option
+     * |        |          |User can select oscillator gain according to crystal external loading and operating temperature range
+     * |        |          |The larger gain value corresponding to stronger driving capability and higher power consumption.
+     * |        |          |00 = L0 mode.
+     * |        |          |01 = L1 mode.
+     * |        |          |10 = L2 mode.
+     * |        |          |11 = L3 mode.
+     * @var RTC_T::GPIOCTL0
+     * Offset: 0x104  RTC GPIO Control 0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE0   |IO Operation Mode
+     * |        |          |00 = PF.4 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.4 is output push pull mode.
+     * |        |          |10 = PF.4 is open drain mode.
+     * |        |          |11 = PF.4 is quasi-bidirectional mode with internal pull up.
+     * |[2]     |DOUT0     |IO Output Data
+     * |        |          |0 = PF.4 output low.
+     * |        |          |1 = PF.4 output high.
+     * |[3]     |CTLSEL0   |IO Pin State Backup Selection
+     * |        |          |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL0 control register.
+     * |        |          |0 = PF.4 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
+     * |        |          |1 = PF.4 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
+     * |        |          |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[5:4]   |PUSEL0    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.4 I/O pull-up or pull-down.
+     * |        |          |00 = PF.4 pull-up and pull-up disable.
+     * |        |          |01 = PF.4 pull-down enable.
+     * |        |          |10 = PF.4 pull-up enable.
+     * |        |          |11 = PF.4 pull-up and pull-up disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
+     * |[9:8]   |OPMODE1   |IO Operation Mode
+     * |        |          |00 = PF.5 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.5 is output push pull mode.
+     * |        |          |10 = PF.5 is open drain mode.
+     * |        |          |11 = PF.5 is quasi-bidirectional mode with internal pull up.
+     * |[10]    |DOUT1     |IO Output Data
+     * |        |          |0 = PF.5 output low.
+     * |        |          |1 = PF.5 output high.
+     * |[11]    |CTLSEL1   |IO Pin State Backup Selection
+     * |        |          |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL0 control register.
+     * |        |          |0 = PF.5 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
+     * |        |          |1 = PF.5 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
+     * |        |          |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[13:12] |PUSEL1    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.5 I/O pull-up or pull-down.
+     * |        |          |00 = PF.5 pull-up and pull-up disable.
+     * |        |          |01 = PF.5 pull-down enable.
+     * |        |          |10 = PF.5 pull-up enable.
+     * |        |          |11 = PF.5 pull-up and pull-up disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
+     * |[17:16] |OPMODE2   |IO Operation Mode
+     * |        |          |00 = PF.6 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.6 is output push pull mode.
+     * |        |          |10 = PF.6 is open drain mode.
+     * |        |          |11 = PF.6 is quasi-bidirectional mode with internal pull up.
+     * |[18]    |DOUT2     |IO Output Data
+     * |        |          |0 = PF.6 output low.
+     * |        |          |1 = PF.6 output high.
+     * |[19]    |CTLSEL2   |IO Pin State Backup Selection
+     * |        |          |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL0 control register.
+     * |        |          |0 = PF.6 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
+     * |        |          |1 = PF.6 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
+     * |        |          |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[21:20] |PUSEL2    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.6 I/O pull-up or pull-down.
+     * |        |          |00 = PF.6 pull-up and pull-up disable.
+     * |        |          |01 = PF.6 pull-down enable.
+     * |        |          |10 = PF.6 pull-up enable.
+     * |        |          |11 = PF.6 pull-up and pull-up disable.
+     * |        |          |Note1:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
+     * |[25:24] |OPMODE3   |IO Operation Mode
+     * |        |          |00 = PF.7 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.7 is output push pull mode.
+     * |        |          |10 = PF.7 is open drain mode.
+     * |        |          |11 = PF.7 is quasi-bidirectional mode.
+     * |[26]    |DOUT3     |IO Output Data
+     * |        |          |0 = PF.7 output low.
+     * |        |          |1 = PF.7 output high.
+     * |[27]    |CTLSEL3   |IO Pin State Backup Selection
+     * |        |          |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL0 control register.
+     * |        |          |0 = PF.7 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.
+     * |        |          |1 = PF.7 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.
+     * |        |          |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+     * |[29:28] |PUSEL3    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.7 I/O pull-up or pull-down.
+     * |        |          |00 = PF.7 pull-up and pull-down disable.
+     * |        |          |01 = PF.7 pull-down enable.
+     * |        |          |10 = PF.7 pull-up enable.
+     * |        |          |11 = PF.7 pull-up and pull-down disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.
+     * @var RTC_T::GPIOCTL1
+     * Offset: 0x108  RTC GPIO Control 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE4   |IO Operation Mode
+     * |        |          |00 = PF.8 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.8 is output push pull mode.
+     * |        |          |10 = PF.8 is open drain mode.
+     * |        |          |11 = PF.8 is quasi-bidirectional mode.
+     * |[2]     |DOUT4     |IO Output Data
+     * |        |          |0 = PF.8 output low.
+     * |        |          |1 = PF.8 output high.
+     * |[3]     |CTLSEL4   |IO Pin State Backup Selection
+     * |        |          |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL1 control register.
+     * |        |          |0 = PF.8 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.
+     * |        |          |1 = PF.8 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.
+     * |        |          |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+     * |[5:4]   |PUSEL4    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.8 I/O pull-up or pull-down.
+     * |        |          |00 = PF.8 pull-up and pull-down disable.
+     * |        |          |01 = PF.8 pull-down enable.
+     * |        |          |10 = PF.8 pull-up enable.
+     * |        |          |11 = PF.8 pull-up and pull-down disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
+     * |[9:8]   |OPMODE5   |IO Operation Mode
+     * |        |          |00 = PF.9 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.9 is output push pull mode.
+     * |        |          |10 = PF.9 is open drain mode.
+     * |        |          |11 = PF.9 is quasi-bidirectional mode.
+     * |[10]    |DOUT5     |IO Output Data
+     * |        |          |0 = PF.9 output low.
+     * |        |          |1 = PF.9 output high.
+     * |[11]    |CTLSEL5   |IO Pin State Backup Selection
+     * |        |          |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL1 control register.
+     * |        |          |0 = PF.9 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.
+     * |        |          |1 = PF.9 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.
+     * |        |          |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[13:12] |PUSEL5    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.9 I/O pull-up or pull-down.
+     * |        |          |00 = PF.9 pull-up and pull-down disable.
+     * |        |          |01 = PF.9 pull-down enable.
+     * |        |          |10 = PF.9 pull-up enable.
+     * |        |          |11 = PF.9 pull-up and pull-down disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
+     * |[17:16] |OPMODE6   |IO Operation Mode
+     * |        |          |00 = PF.10 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.10 is output push pull mode.
+     * |        |          |10 = PF.10 is open drain mode.
+     * |        |          |11 = PF.10 is quasi-bidirectional mode.
+     * |[18]    |DOUT6     |IO Output Data
+     * |        |          |0 = PF.10 output low.
+     * |        |          |1 = PF.10 output high.
+     * |[19]    |CTLSEL6   |IO Pin State Backup Selection
+     * |        |          |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL1 control register.
+     * |        |          |0 = PF.10 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.
+     * |        |          |1 = PF.10 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.
+     * |        |          |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[21:20] |PUSEL6    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.10 I/O pull-up or pull-down.
+     * |        |          |00 = PF.10 pull-up and pull-down disable.
+     * |        |          |01 = PF.10 pull-down enable.
+     * |        |          |10 = PF.10 pull-up enable.
+     * |        |          |11 = PF.10 pull-up and pull-down disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
+     * |[25:24] |OPMODE7   |IO Operation Mode
+     * |        |          |00 = PF.11 is input only mode, without pull-up resistor.
+     * |        |          |01 = PF.11 is output push pull mode.
+     * |        |          |10 = PF.11 is open drain mode.
+     * |        |          |11 = PF.11 is quasi-bidirectional mode.
+     * |[26]    |DOUT7     |IO Output Data
+     * |        |          |0 = PF.11 output low.
+     * |        |          |1 = PF.11 output high.
+     * |[27]    |CTLSEL7   |IO Pin State Backup Selection
+     * |        |          |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function
+     * |        |          |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or
+     * |        |          |VBAT power domain RTC_GPIOCTL1 control register.
+     * |        |          |0 = PF.11 pin I/O function is controlled by GPIO module.
+     * |        |          |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.
+     * |        |          |1 = PF.11 pin I/O function is controlled by VBAT power domain.
+     * |        |          |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.
+     * |        |          |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+     * |[29:28] |PUSEL7    |IO Pull-up and Pull-down Enable
+     * |        |          |Determine PF.11 I/O pull-up or pull-down.
+     * |        |          |00 = PF.11 pull-up and pull-down disable.
+     * |        |          |01 = PF.11 pull-down enable.
+     * |        |          |10 = PF.11 pull-up enable.
+     * |        |          |11 = PF.11 pull-up and pull-down disable.
+     * |        |          |Note:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.
+     * @var RTC_T::DSTCTL
+     * Offset: 0x110  RTC Daylight Saving Time Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADDHR     |Add 1 Hour
+     * |        |          |0 = No effect.
+     * |        |          |1 = Indicates RTC hour digit has been added one hour for summer time change.
+     * |[1]     |SUBHR     |Subtract 1 Hour
+     * |        |          |0 = No effect.
+     * |        |          |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
+     * |[2]     |DSBAK     |Daylight Saving Back
+     * |        |          |0= Normal mode.
+     * |        |          |1= Daylight saving mode.
+     * @var RTC_T::TAMPCTL
+     * Offset: 0x120  RTC Tamper Pin Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DYN1ISS   |Dynamic Pair 1 Input Source Select
+     * |        |          |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 2.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+     * |[1]     |DYN2ISS   |Dynamic Pair 2 Input Source Select
+     * |        |          |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 4.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+     * |[3:2]   |DYNSRC    |Dynamic Reference Pattern
+     * |        |          |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
+     * |        |          |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.
+     * |        |          |01 = The new reference pattern is repeated previous random value when the reference pattern run out.
+     * |        |          |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
+     * |        |          |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
+     * |[4]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |Setting this bit, the tamper configuration will be reload.
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |        |          |Note: Before set this bit, the tamper configuration should be set to complete.
+     * |[7:5]   |DYNRATE   |Dynamic Change Rate
+     * |        |          |This item is choice the dynamic tamper output change rate.
+     * |        |          |000 = 210 * RTC_CLK.
+     * |        |          |001 = 211 * RTC_CLK.
+     * |        |          |010 = 212 * RTC_CLK.
+     * |        |          |011 = 213 * RTC_CLK.
+     * |        |          |100 = 214 * RTC_CLK.
+     * |        |          |101 = 215 * RTC_CLK.
+     * |        |          |110 = 216 * RTC_CLK.
+     * |        |          |111 = 217 * RTC_CLK.
+     * |        |          |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
+     * |[8]     |TAMP0EN   |Tamper0 Detect Enable Bit
+     * |        |          |0 = Tamper 0 detect Disabled.
+     * |        |          |1 = Tamper 0 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[9]     |TAMP0LV   |Tamper 0 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[10]    |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
+     * |        |          |0 = Tamper 0 de-bounce Disabled.
+     * |        |          |1 = Tamper 0 de-bounce Enabled.
+     * |[12]    |TAMP1EN   |Tamper 1 Detect Enable Bit
+     * |        |          |0 = Tamper 1 detect Disabled.
+     * |        |          |1 = Tamper 1 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[13]    |TAMP1LV   |Tamper 1 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[14]    |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
+     * |        |          |0 = Tamper 1 de-bounce Disabled.
+     * |        |          |1 = Tamper 1 de-bounce Enabled.
+     * |[15]    |DYNPR0EN  |Dynamic Pair 0 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[16]    |TAMP2EN   |Tamper 2 Detect Enable Bit
+     * |        |          |0 = Tamper 2 detect Disabled.
+     * |        |          |1 = Tamper 2 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[17]    |TAMP2LV   |Tamper 2 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[18]    |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
+     * |        |          |0 = Tamper 2 de-bounce Disabled.
+     * |        |          |1 = Tamper 2 de-bounce Enabled.
+     * |[20]    |TAMP3EN   |Tamper 3 Detect Enable Bit
+     * |        |          |0 = Tamper 3 detect Disabled.
+     * |        |          |1 = Tamper 3 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[21]    |TAMP3LV   |Tamper 3 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[22]    |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
+     * |        |          |0 = Tamper 3 de-bounce Disabled.
+     * |        |          |1 = Tamper 3 de-bounce Enabled.
+     * |[23]    |DYNPR1EN  |Dynamic Pair 1 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[24]    |TAMP4EN   |Tamper4 Detect Enable Bit
+     * |        |          |0 = Tamper 4 detect Disabled.
+     * |        |          |1 = Tamper 4 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[25]    |TAMP4LV   |Tamper 4 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[26]    |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
+     * |        |          |0 = Tamper 4 de-bounce Disabled.
+     * |        |          |1 = Tamper 4 de-bounce Enabled.
+     * |[28]    |TAMP5EN   |Tamper 5 Detect Enable Bit
+     * |        |          |0 = Tamper 5 detect Disabled.
+     * |        |          |1 = Tamper 5 detect Enabled.
+     * |        |          |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[29]    |TAMP5LV   |Tamper 5 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[30]    |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
+     * |        |          |0 = Tamper 5 de-bounce Disabled.
+     * |        |          |1 = Tamper 5 de-bounce Enabled.
+     * |[31]    |DYNPR2EN  |Dynamic Pair 2 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * @var RTC_T::TAMPSEED
+     * Offset: 0x128  RTC Tamper Dynamic Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed Value
+     * @var RTC_T::TAMPTIME
+     * Offset: 0x130  RTC Tamper Time Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit of TAMPER Time (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit of TAMPER Time (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit of TAMPER Time (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit of TAMPER Time (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit of TAMPER Time (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit of TAMPER Time (0~2)
+     * |        |          |Note: 24-hour time scale only.
+     * @var RTC_T::TAMPCAL
+     * Offset: 0x134  RTC Tamper Calendar Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit of TAMPER Calendar (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit of TAMPER Calendar (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit of TAMPER Calendar (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit of TAMPER Calendar (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit of TAMPER Calendar (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit of TAMPER Calendar (0~9)
+     */
+    __IO uint32_t INIT;                  /*!< [0x0000] RTC Initiation Register                                          */
+    __IO uint32_t RWEN;                  /*!< [0x0004] RTC Access Enable Register                                       */
+    __IO uint32_t FREQADJ;               /*!< [0x0008] RTC Frequency Compensation Register                              */
+    __IO uint32_t TIME;                  /*!< [0x000c] RTC Time Loading Register                                        */
+    __IO uint32_t CAL;                   /*!< [0x0010] RTC Calendar Loading Register                                    */
+    __IO uint32_t CLKFMT;                /*!< [0x0014] RTC Time Scale Selection Register                                */
+    __IO uint32_t WEEKDAY;               /*!< [0x0018] RTC Day of the Week Register                                     */
+    __IO uint32_t TALM;                  /*!< [0x001c] RTC Time Alarm Register                                          */
+    __IO uint32_t CALM;                  /*!< [0x0020] RTC Calendar Alarm Register                                      */
+    __I  uint32_t LEAPYEAR;              /*!< [0x0024] RTC Leap Year Indicator Register                                 */
+    __IO uint32_t INTEN;                 /*!< [0x0028] RTC Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x002c] RTC Interrupt Status Register                                    */
+    __IO uint32_t TICK;                  /*!< [0x0030] RTC Time Tick Register                                           */
+    __IO uint32_t TAMSK;                 /*!< [0x0034] RTC Time Alarm Mask Register                                     */
+    __IO uint32_t CAMSK;                 /*!< [0x0038] RTC Calendar Alarm Mask Register                                 */
+    __IO uint32_t SPRCTL;                /*!< [0x003c] RTC Spare Functional Control Register                            */
+    __IO uint32_t SPR[20];               /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[28];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t LXTCTL;                /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register                       */
+    __IO uint32_t GPIOCTL0;              /*!< [0x0104] RTC GPIO Control 0 Register                                      */
+    __IO uint32_t GPIOCTL1;              /*!< [0x0108] RTC GPIO Control 1 Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DSTCTL;                /*!< [0x0110] RTC Daylight Saving Time Control Register                        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TAMPCTL;               /*!< [0x0120] RTC Tamper Pin Control Register                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TAMPSEED;              /*!< [0x0128] RTC Tamper Dynamic Seed Register                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t TAMPTIME;              /*!< [0x0130] RTC Tamper Time Register                                         */
+    __I  uint32_t TAMPCAL;               /*!< [0x0134] RTC Tamper Calendar Register                                     */
+
+} RTC_T;
+
+/**
+    @addtogroup RTC_CONST RTC Bit Field Definition
+    Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIT_ACTIVE_Pos         (0)                                               /*!< RTC_T::INIT: INIT_ACTIVE Position      */
+#define RTC_INIT_ACTIVE_Msk         (0x1ul << RTC_INIT_ACTIVE_Pos)               /*!< RTC_T::INIT: INIT_ACTIVE Mask          */
+
+#define RTC_INIT_INIT_Pos                (1)                                               /*!< RTC_T::INIT: INIT Position             */
+#define RTC_INIT_INIT_Msk                (0x7ffffffful << RTC_INIT_INIT_Pos)               /*!< RTC_T::INIT: INIT Mask                 */
+
+#define RTC_RWEN_RWENF_Pos               (16)                                              /*!< RTC_T::RWEN: RWENF Position            */
+#define RTC_RWEN_RWENF_Msk               (0x1ul << RTC_RWEN_RWENF_Pos)                     /*!< RTC_T::RWEN: RWENF Mask                */
+
+#define RTC_RWEN_RTCBUSY_Pos             (24)                                              /*!< RTC_T::RWEN: RTCBUSY Position          */
+#define RTC_RWEN_RTCBUSY_Msk             (0x1ul << RTC_RWEN_RTCBUSY_Pos)                   /*!< RTC_T::RWEN: RTCBUSY Mask              */
+
+#define RTC_FREQADJ_FREQADJ_Pos          (0)                                               /*!< RTC_T::FREQADJ: FREQADJ Position       */
+#define RTC_FREQADJ_FREQADJ_Msk          (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos)           /*!< RTC_T::FREQADJ: FREQADJ Mask           */
+
+#define RTC_TIME_SEC_Pos                 (0)                                               /*!< RTC_T::TIME: SEC Position              */
+#define RTC_TIME_SEC_Msk                 (0xful << RTC_TIME_SEC_Pos)                       /*!< RTC_T::TIME: SEC Mask                  */
+
+#define RTC_TIME_TENSEC_Pos              (4)                                               /*!< RTC_T::TIME: TENSEC Position           */
+#define RTC_TIME_TENSEC_Msk              (0x7ul << RTC_TIME_TENSEC_Pos)                    /*!< RTC_T::TIME: TENSEC Mask               */
+
+#define RTC_TIME_MIN_Pos                 (8)                                               /*!< RTC_T::TIME: MIN Position              */
+#define RTC_TIME_MIN_Msk                 (0xful << RTC_TIME_MIN_Pos)                       /*!< RTC_T::TIME: MIN Mask                  */
+
+#define RTC_TIME_TENMIN_Pos              (12)                                              /*!< RTC_T::TIME: TENMIN Position           */
+#define RTC_TIME_TENMIN_Msk              (0x7ul << RTC_TIME_TENMIN_Pos)                    /*!< RTC_T::TIME: TENMIN Mask               */
+
+#define RTC_TIME_HR_Pos                  (16)                                              /*!< RTC_T::TIME: HR Position               */
+#define RTC_TIME_HR_Msk                  (0xful << RTC_TIME_HR_Pos)                        /*!< RTC_T::TIME: HR Mask                   */
+
+#define RTC_TIME_TENHR_Pos               (20)                                              /*!< RTC_T::TIME: TENHR Position            */
+#define RTC_TIME_TENHR_Msk               (0x3ul << RTC_TIME_TENHR_Pos)                     /*!< RTC_T::TIME: TENHR Mask                */
+
+#define RTC_CAL_DAY_Pos                  (0)                                               /*!< RTC_T::CAL: DAY Position               */
+#define RTC_CAL_DAY_Msk                  (0xful << RTC_CAL_DAY_Pos)                        /*!< RTC_T::CAL: DAY Mask                   */
+
+#define RTC_CAL_TENDAY_Pos               (4)                                               /*!< RTC_T::CAL: TENDAY Position            */
+#define RTC_CAL_TENDAY_Msk               (0x3ul << RTC_CAL_TENDAY_Pos)                     /*!< RTC_T::CAL: TENDAY Mask                */
+
+#define RTC_CAL_MON_Pos                  (8)                                               /*!< RTC_T::CAL: MON Position               */
+#define RTC_CAL_MON_Msk                  (0xful << RTC_CAL_MON_Pos)                        /*!< RTC_T::CAL: MON Mask                   */
+
+#define RTC_CAL_TENMON_Pos               (12)                                              /*!< RTC_T::CAL: TENMON Position            */
+#define RTC_CAL_TENMON_Msk               (0x1ul << RTC_CAL_TENMON_Pos)                     /*!< RTC_T::CAL: TENMON Mask                */
+
+#define RTC_CAL_YEAR_Pos                 (16)                                              /*!< RTC_T::CAL: YEAR Position              */
+#define RTC_CAL_YEAR_Msk                 (0xful << RTC_CAL_YEAR_Pos)                       /*!< RTC_T::CAL: YEAR Mask                  */
+
+#define RTC_CAL_TENYEAR_Pos              (20)                                              /*!< RTC_T::CAL: TENYEAR Position           */
+#define RTC_CAL_TENYEAR_Msk              (0xful << RTC_CAL_TENYEAR_Pos)                    /*!< RTC_T::CAL: TENYEAR Mask               */
+
+#define RTC_CLKFMT_24HEN_Pos             (0)                                               /*!< RTC_T::CLKFMT: 24HEN Position          */
+#define RTC_CLKFMT_24HEN_Msk             (0x1ul << RTC_CLKFMT_24HEN_Pos)                   /*!< RTC_T::CLKFMT: 24HEN Mask              */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos          (0)                                               /*!< RTC_T::WEEKDAY: WEEKDAY Position       */
+#define RTC_WEEKDAY_WEEKDAY_Msk          (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)                /*!< RTC_T::WEEKDAY: WEEKDAY Mask           */
+
+#define RTC_TALM_SEC_Pos                 (0)                                               /*!< RTC_T::TALM: SEC Position              */
+#define RTC_TALM_SEC_Msk                 (0xful << RTC_TALM_SEC_Pos)                       /*!< RTC_T::TALM: SEC Mask                  */
+
+#define RTC_TALM_TENSEC_Pos              (4)                                               /*!< RTC_T::TALM: TENSEC Position           */
+#define RTC_TALM_TENSEC_Msk              (0x7ul << RTC_TALM_TENSEC_Pos)                    /*!< RTC_T::TALM: TENSEC Mask               */
+
+#define RTC_TALM_MIN_Pos                 (8)                                               /*!< RTC_T::TALM: MIN Position              */
+#define RTC_TALM_MIN_Msk                 (0xful << RTC_TALM_MIN_Pos)                       /*!< RTC_T::TALM: MIN Mask                  */
+
+#define RTC_TALM_TENMIN_Pos              (12)                                              /*!< RTC_T::TALM: TENMIN Position           */
+#define RTC_TALM_TENMIN_Msk              (0x7ul << RTC_TALM_TENMIN_Pos)                    /*!< RTC_T::TALM: TENMIN Mask               */
+
+#define RTC_TALM_HR_Pos                  (16)                                              /*!< RTC_T::TALM: HR Position               */
+#define RTC_TALM_HR_Msk                  (0xful << RTC_TALM_HR_Pos)                        /*!< RTC_T::TALM: HR Mask                   */
+
+#define RTC_TALM_TENHR_Pos               (20)                                              /*!< RTC_T::TALM: TENHR Position            */
+#define RTC_TALM_TENHR_Msk               (0x3ul << RTC_TALM_TENHR_Pos)                     /*!< RTC_T::TALM: TENHR Mask                */
+
+#define RTC_CALM_DAY_Pos                 (0)                                               /*!< RTC_T::CALM: DAY Position              */
+#define RTC_CALM_DAY_Msk                 (0xful << RTC_CALM_DAY_Pos)                       /*!< RTC_T::CALM: DAY Mask                  */
+
+#define RTC_CALM_TENDAY_Pos              (4)                                               /*!< RTC_T::CALM: TENDAY Position           */
+#define RTC_CALM_TENDAY_Msk              (0x3ul << RTC_CALM_TENDAY_Pos)                    /*!< RTC_T::CALM: TENDAY Mask               */
+
+#define RTC_CALM_MON_Pos                 (8)                                               /*!< RTC_T::CALM: MON Position              */
+#define RTC_CALM_MON_Msk                 (0xful << RTC_CALM_MON_Pos)                       /*!< RTC_T::CALM: MON Mask                  */
+
+#define RTC_CALM_TENMON_Pos              (12)                                              /*!< RTC_T::CALM: TENMON Position           */
+#define RTC_CALM_TENMON_Msk              (0x1ul << RTC_CALM_TENMON_Pos)                    /*!< RTC_T::CALM: TENMON Mask               */
+
+#define RTC_CALM_YEAR_Pos                (16)                                              /*!< RTC_T::CALM: YEAR Position             */
+#define RTC_CALM_YEAR_Msk                (0xful << RTC_CALM_YEAR_Pos)                      /*!< RTC_T::CALM: YEAR Mask                 */
+
+#define RTC_CALM_TENYEAR_Pos             (20)                                              /*!< RTC_T::CALM: TENYEAR Position          */
+#define RTC_CALM_TENYEAR_Msk             (0xful << RTC_CALM_TENYEAR_Pos)                   /*!< RTC_T::CALM: TENYEAR Mask              */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos        (0)                                               /*!< RTC_T::LEAPYEAR: LEAPYEAR Position     */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk        (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)              /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask         */
+
+#define RTC_INTEN_ALMIEN_Pos             (0)                                               /*!< RTC_T::INTEN: ALMIEN Position          */
+#define RTC_INTEN_ALMIEN_Msk             (0x1ul << RTC_INTEN_ALMIEN_Pos)                   /*!< RTC_T::INTEN: ALMIEN Mask              */
+
+#define RTC_INTEN_TICKIEN_Pos            (1)                                               /*!< RTC_T::INTEN: TICKIEN Position         */
+#define RTC_INTEN_TICKIEN_Msk            (0x1ul << RTC_INTEN_TICKIEN_Pos)                  /*!< RTC_T::INTEN: TICKIEN Mask             */
+
+#define RTC_INTEN_TAMP0IEN_Pos           (8)                                               /*!< RTC_T::INTEN: TAMP0IEN Position        */
+#define RTC_INTEN_TAMP0IEN_Msk           (0x1ul << RTC_INTEN_TAMP0IEN_Pos)                 /*!< RTC_T::INTEN: TAMP0IEN Mask            */
+
+#define RTC_INTEN_TAMP1IEN_Pos           (9)                                               /*!< RTC_T::INTEN: TAMP1IEN Position        */
+#define RTC_INTEN_TAMP1IEN_Msk           (0x1ul << RTC_INTEN_TAMP1IEN_Pos)                 /*!< RTC_T::INTEN: TAMP1IEN Mask            */
+
+#define RTC_INTEN_TAMP2IEN_Pos           (10)                                              /*!< RTC_T::INTEN: TAMP2IEN Position        */
+#define RTC_INTEN_TAMP2IEN_Msk           (0x1ul << RTC_INTEN_TAMP2IEN_Pos)                 /*!< RTC_T::INTEN: TAMP2IEN Mask            */
+
+#define RTC_INTEN_TAMP3IEN_Pos           (11)                                              /*!< RTC_T::INTEN: TAMP3IEN Position        */
+#define RTC_INTEN_TAMP3IEN_Msk           (0x1ul << RTC_INTEN_TAMP3IEN_Pos)                 /*!< RTC_T::INTEN: TAMP3IEN Mask            */
+
+#define RTC_INTEN_TAMP4IEN_Pos           (12)                                              /*!< RTC_T::INTEN: TAMP4IEN Position        */
+#define RTC_INTEN_TAMP4IEN_Msk           (0x1ul << RTC_INTEN_TAMP4IEN_Pos)                 /*!< RTC_T::INTEN: TAMP4IEN Mask            */
+
+#define RTC_INTEN_TAMP5IEN_Pos           (13)                                              /*!< RTC_T::INTEN: TAMP5IEN Position        */
+#define RTC_INTEN_TAMP5IEN_Msk           (0x1ul << RTC_INTEN_TAMP5IEN_Pos)                 /*!< RTC_T::INTEN: TAMP5IEN Mask            */
+
+#define RTC_INTSTS_ALMIF_Pos             (0)                                               /*!< RTC_T::INTSTS: ALMIF Position          */
+#define RTC_INTSTS_ALMIF_Msk             (0x1ul << RTC_INTSTS_ALMIF_Pos)                   /*!< RTC_T::INTSTS: ALMIF Mask              */
+
+#define RTC_INTSTS_TICKIF_Pos            (1)                                               /*!< RTC_T::INTSTS: TICKIF Position         */
+#define RTC_INTSTS_TICKIF_Msk            (0x1ul << RTC_INTSTS_TICKIF_Pos)                  /*!< RTC_T::INTSTS: TICKIF Mask             */
+
+#define RTC_INTSTS_TAMP0IF_Pos           (8)                                               /*!< RTC_T::INTSTS: TAMP0IF Position        */
+#define RTC_INTSTS_TAMP0IF_Msk           (0x1ul << RTC_INTSTS_TAMP0IF_Pos)                 /*!< RTC_T::INTSTS: TAMP0IF Mask            */
+
+#define RTC_INTSTS_TAMP1IF_Pos           (9)                                               /*!< RTC_T::INTSTS: TAMP1IF Position        */
+#define RTC_INTSTS_TAMP1IF_Msk           (0x1ul << RTC_INTSTS_TAMP1IF_Pos)                 /*!< RTC_T::INTSTS: TAMP1IF Mask            */
+
+#define RTC_INTSTS_TAMP2IF_Pos           (10)                                              /*!< RTC_T::INTSTS: TAMP2IF Position        */
+#define RTC_INTSTS_TAMP2IF_Msk           (0x1ul << RTC_INTSTS_TAMP2IF_Pos)                 /*!< RTC_T::INTSTS: TAMP2IF Mask            */
+
+#define RTC_INTSTS_TAMP3IF_Pos           (11)                                              /*!< RTC_T::INTSTS: TAMP3IF Position        */
+#define RTC_INTSTS_TAMP3IF_Msk           (0x1ul << RTC_INTSTS_TAMP3IF_Pos)                 /*!< RTC_T::INTSTS: TAMP3IF Mask            */
+
+#define RTC_INTSTS_TAMP4IF_Pos           (12)                                              /*!< RTC_T::INTSTS: TAMP4IF Position        */
+#define RTC_INTSTS_TAMP4IF_Msk           (0x1ul << RTC_INTSTS_TAMP4IF_Pos)                 /*!< RTC_T::INTSTS: TAMP4IF Mask            */
+
+#define RTC_INTSTS_TAMP5IF_Pos           (13)                                              /*!< RTC_T::INTSTS: TAMP5IF Position        */
+#define RTC_INTSTS_TAMP5IF_Msk           (0x1ul << RTC_INTSTS_TAMP5IF_Pos)                 /*!< RTC_T::INTSTS: TAMP5IF Mask            */
+
+#define RTC_TICK_TICK_Pos                (0)                                               /*!< RTC_T::TICK: TICK Position             */
+#define RTC_TICK_TICK_Msk                (0x7ul << RTC_TICK_TICK_Pos)                      /*!< RTC_T::TICK: TICK Mask                 */
+
+#define RTC_TAMSK_MSEC_Pos               (0)                                               /*!< RTC_T::TAMSK: MSEC Position            */
+#define RTC_TAMSK_MSEC_Msk               (0x1ul << RTC_TAMSK_MSEC_Pos)                     /*!< RTC_T::TAMSK: MSEC Mask                */
+
+#define RTC_TAMSK_MTENSEC_Pos            (1)                                               /*!< RTC_T::TAMSK: MTENSEC Position         */
+#define RTC_TAMSK_MTENSEC_Msk            (0x1ul << RTC_TAMSK_MTENSEC_Pos)                  /*!< RTC_T::TAMSK: MTENSEC Mask             */
+
+#define RTC_TAMSK_MMIN_Pos               (2)                                               /*!< RTC_T::TAMSK: MMIN Position            */
+#define RTC_TAMSK_MMIN_Msk               (0x1ul << RTC_TAMSK_MMIN_Pos)                     /*!< RTC_T::TAMSK: MMIN Mask                */
+
+#define RTC_TAMSK_MTENMIN_Pos            (3)                                               /*!< RTC_T::TAMSK: MTENMIN Position         */
+#define RTC_TAMSK_MTENMIN_Msk            (0x1ul << RTC_TAMSK_MTENMIN_Pos)                  /*!< RTC_T::TAMSK: MTENMIN Mask             */
+
+#define RTC_TAMSK_MHR_Pos                (4)                                               /*!< RTC_T::TAMSK: MHR Position             */
+#define RTC_TAMSK_MHR_Msk                (0x1ul << RTC_TAMSK_MHR_Pos)                      /*!< RTC_T::TAMSK: MHR Mask                 */
+
+#define RTC_TAMSK_MTENHR_Pos             (5)                                               /*!< RTC_T::TAMSK: MTENHR Position          */
+#define RTC_TAMSK_MTENHR_Msk             (0x1ul << RTC_TAMSK_MTENHR_Pos)                   /*!< RTC_T::TAMSK: MTENHR Mask              */
+
+#define RTC_CAMSK_MDAY_Pos               (0)                                               /*!< RTC_T::CAMSK: MDAY Position            */
+#define RTC_CAMSK_MDAY_Msk               (0x1ul << RTC_CAMSK_MDAY_Pos)                     /*!< RTC_T::CAMSK: MDAY Mask                */
+
+#define RTC_CAMSK_MTENDAY_Pos            (1)                                               /*!< RTC_T::CAMSK: MTENDAY Position         */
+#define RTC_CAMSK_MTENDAY_Msk            (0x1ul << RTC_CAMSK_MTENDAY_Pos)                  /*!< RTC_T::CAMSK: MTENDAY Mask             */
+
+#define RTC_CAMSK_MMON_Pos               (2)                                               /*!< RTC_T::CAMSK: MMON Position            */
+#define RTC_CAMSK_MMON_Msk               (0x1ul << RTC_CAMSK_MMON_Pos)                     /*!< RTC_T::CAMSK: MMON Mask                */
+
+#define RTC_CAMSK_MTENMON_Pos            (3)                                               /*!< RTC_T::CAMSK: MTENMON Position         */
+#define RTC_CAMSK_MTENMON_Msk            (0x1ul << RTC_CAMSK_MTENMON_Pos)                  /*!< RTC_T::CAMSK: MTENMON Mask             */
+
+#define RTC_CAMSK_MYEAR_Pos              (4)                                               /*!< RTC_T::CAMSK: MYEAR Position           */
+#define RTC_CAMSK_MYEAR_Msk              (0x1ul << RTC_CAMSK_MYEAR_Pos)                    /*!< RTC_T::CAMSK: MYEAR Mask               */
+
+#define RTC_CAMSK_MTENYEAR_Pos           (5)                                               /*!< RTC_T::CAMSK: MTENYEAR Position        */
+#define RTC_CAMSK_MTENYEAR_Msk           (0x1ul << RTC_CAMSK_MTENYEAR_Pos)                 /*!< RTC_T::CAMSK: MTENYEAR Mask            */
+
+#define RTC_SPRCTL_SPRRWEN_Pos           (2)                                               /*!< RTC_T::SPRCTL: SPRRWEN Position        */
+#define RTC_SPRCTL_SPRRWEN_Msk           (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)                 /*!< RTC_T::SPRCTL: SPRRWEN Mask            */
+
+#define RTC_SPRCTL_SPRCSTS_Pos           (5)                                               /*!< RTC_T::SPRCTL: SPRCSTS Position        */
+#define RTC_SPRCTL_SPRCSTS_Msk           (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)                 /*!< RTC_T::SPRCTL: SPRCSTS Mask            */
+
+#define RTC_SPR0_SPARE_Pos               (0)                                               /*!< RTC_T::SPR0: SPARE Position            */
+#define RTC_SPR0_SPARE_Msk               (0xfffffffful << RTC_SPR0_SPARE_Pos)              /*!< RTC_T::SPR0: SPARE Mask                */
+
+#define RTC_SPR1_SPARE_Pos               (0)                                               /*!< RTC_T::SPR1: SPARE Position            */
+#define RTC_SPR1_SPARE_Msk               (0xfffffffful << RTC_SPR1_SPARE_Pos)              /*!< RTC_T::SPR1: SPARE Mask                */
+
+#define RTC_SPR2_SPARE_Pos               (0)                                               /*!< RTC_T::SPR2: SPARE Position            */
+#define RTC_SPR2_SPARE_Msk               (0xfffffffful << RTC_SPR2_SPARE_Pos)              /*!< RTC_T::SPR2: SPARE Mask                */
+
+#define RTC_SPR3_SPARE_Pos               (0)                                               /*!< RTC_T::SPR3: SPARE Position            */
+#define RTC_SPR3_SPARE_Msk               (0xfffffffful << RTC_SPR3_SPARE_Pos)              /*!< RTC_T::SPR3: SPARE Mask                */
+
+#define RTC_SPR4_SPARE_Pos               (0)                                               /*!< RTC_T::SPR4: SPARE Position            */
+#define RTC_SPR4_SPARE_Msk               (0xfffffffful << RTC_SPR4_SPARE_Pos)              /*!< RTC_T::SPR4: SPARE Mask                */
+
+#define RTC_SPR5_SPARE_Pos               (0)                                               /*!< RTC_T::SPR5: SPARE Position            */
+#define RTC_SPR5_SPARE_Msk               (0xfffffffful << RTC_SPR5_SPARE_Pos)              /*!< RTC_T::SPR5: SPARE Mask                */
+
+#define RTC_SPR6_SPARE_Pos               (0)                                               /*!< RTC_T::SPR6: SPARE Position            */
+#define RTC_SPR6_SPARE_Msk               (0xfffffffful << RTC_SPR6_SPARE_Pos)              /*!< RTC_T::SPR6: SPARE Mask                */
+
+#define RTC_SPR7_SPARE_Pos               (0)                                               /*!< RTC_T::SPR7: SPARE Position            */
+#define RTC_SPR7_SPARE_Msk               (0xfffffffful << RTC_SPR7_SPARE_Pos)              /*!< RTC_T::SPR7: SPARE Mask                */
+
+#define RTC_SPR8_SPARE_Pos               (0)                                               /*!< RTC_T::SPR8: SPARE Position            */
+#define RTC_SPR8_SPARE_Msk               (0xfffffffful << RTC_SPR8_SPARE_Pos)              /*!< RTC_T::SPR8: SPARE Mask                */
+
+#define RTC_SPR9_SPARE_Pos               (0)                                               /*!< RTC_T::SPR9: SPARE Position            */
+#define RTC_SPR9_SPARE_Msk               (0xfffffffful << RTC_SPR9_SPARE_Pos)              /*!< RTC_T::SPR9: SPARE Mask                */
+
+#define RTC_SPR10_SPARE_Pos              (0)                                               /*!< RTC_T::SPR10: SPARE Position           */
+#define RTC_SPR10_SPARE_Msk              (0xfffffffful << RTC_SPR10_SPARE_Pos)             /*!< RTC_T::SPR10: SPARE Mask               */
+
+#define RTC_SPR11_SPARE_Pos              (0)                                               /*!< RTC_T::SPR11: SPARE Position           */
+#define RTC_SPR11_SPARE_Msk              (0xfffffffful << RTC_SPR11_SPARE_Pos)             /*!< RTC_T::SPR11: SPARE Mask               */
+
+#define RTC_SPR12_SPARE_Pos              (0)                                               /*!< RTC_T::SPR12: SPARE Position           */
+#define RTC_SPR12_SPARE_Msk              (0xfffffffful << RTC_SPR12_SPARE_Pos)             /*!< RTC_T::SPR12: SPARE Mask               */
+
+#define RTC_SPR13_SPARE_Pos              (0)                                               /*!< RTC_T::SPR13: SPARE Position           */
+#define RTC_SPR13_SPARE_Msk              (0xfffffffful << RTC_SPR13_SPARE_Pos)             /*!< RTC_T::SPR13: SPARE Mask               */
+
+#define RTC_SPR14_SPARE_Pos              (0)                                               /*!< RTC_T::SPR14: SPARE Position           */
+#define RTC_SPR14_SPARE_Msk              (0xfffffffful << RTC_SPR14_SPARE_Pos)             /*!< RTC_T::SPR14: SPARE Mask               */
+
+#define RTC_SPR15_SPARE_Pos              (0)                                               /*!< RTC_T::SPR15: SPARE Position           */
+#define RTC_SPR15_SPARE_Msk              (0xfffffffful << RTC_SPR15_SPARE_Pos)             /*!< RTC_T::SPR15: SPARE Mask               */
+
+#define RTC_SPR16_SPARE_Pos              (0)                                               /*!< RTC_T::SPR16: SPARE Position           */
+#define RTC_SPR16_SPARE_Msk              (0xfffffffful << RTC_SPR16_SPARE_Pos)             /*!< RTC_T::SPR16: SPARE Mask               */
+
+#define RTC_SPR17_SPARE_Pos              (0)                                               /*!< RTC_T::SPR17: SPARE Position           */
+#define RTC_SPR17_SPARE_Msk              (0xfffffffful << RTC_SPR17_SPARE_Pos)             /*!< RTC_T::SPR17: SPARE Mask               */
+
+#define RTC_SPR18_SPARE_Pos              (0)                                               /*!< RTC_T::SPR18: SPARE Position           */
+#define RTC_SPR18_SPARE_Msk              (0xfffffffful << RTC_SPR18_SPARE_Pos)             /*!< RTC_T::SPR18: SPARE Mask               */
+
+#define RTC_SPR19_SPARE_Pos              (0)                                               /*!< RTC_T::SPR19: SPARE Position           */
+#define RTC_SPR19_SPARE_Msk              (0xfffffffful << RTC_SPR19_SPARE_Pos)             /*!< RTC_T::SPR19: SPARE Mask               */
+
+#define RTC_LXTCTL_GAIN_Pos              (1)                                               /*!< RTC_T::LXTCTL: GAIN Position           */
+#define RTC_LXTCTL_GAIN_Msk              (0x3ul << RTC_LXTCTL_GAIN_Pos)                    /*!< RTC_T::LXTCTL: GAIN Mask               */
+
+#define RTC_GPIOCTL0_OPMODE0_Pos         (0)                                               /*!< RTC_T::GPIOCTL0: OPMODE0 Position      */
+#define RTC_GPIOCTL0_OPMODE0_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE0 Mask          */
+
+#define RTC_GPIOCTL0_DOUT0_Pos           (2)                                               /*!< RTC_T::GPIOCTL0: DOUT0 Position        */
+#define RTC_GPIOCTL0_DOUT0_Msk           (0x1ul << RTC_GPIOCTL0_DOUT0_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT0 Mask            */
+
+#define RTC_GPIOCTL0_CTLSEL0_Pos         (3)                                               /*!< RTC_T::GPIOCTL0: CTLSEL0 Position      */
+#define RTC_GPIOCTL0_CTLSEL0_Msk         (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos)               /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL0_Pos          (4)                                               /*!< RTC_T::GPIOCTL0: PUSEL0 Position       */
+#define RTC_GPIOCTL0_PUSEL0_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL0 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE1_Pos         (8)                                               /*!< RTC_T::GPIOCTL0: OPMODE1 Position      */
+#define RTC_GPIOCTL0_OPMODE1_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE1 Mask          */
+
+#define RTC_GPIOCTL0_DOUT1_Pos           (10)                                              /*!< RTC_T::GPIOCTL0: DOUT1 Position        */
+#define RTC_GPIOCTL0_DOUT1_Msk           (0x1ul << RTC_GPIOCTL0_DOUT1_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT1 Mask            */
+
+#define RTC_GPIOCTL0_CTLSEL1_Pos         (11)                                              /*!< RTC_T::GPIOCTL0: CTLSEL1 Position      */
+#define RTC_GPIOCTL0_CTLSEL1_Msk         (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos)               /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL1_Pos          (12)                                              /*!< RTC_T::GPIOCTL0: PUSEL1 Position       */
+#define RTC_GPIOCTL0_PUSEL1_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL1 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE2_Pos         (16)                                              /*!< RTC_T::GPIOCTL0: OPMODE2 Position      */
+#define RTC_GPIOCTL0_OPMODE2_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE2 Mask          */
+
+#define RTC_GPIOCTL0_DOUT2_Pos           (18)                                              /*!< RTC_T::GPIOCTL0: DOUT2 Position        */
+#define RTC_GPIOCTL0_DOUT2_Msk           (0x1ul << RTC_GPIOCTL0_DOUT2_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT2 Mask            */
+
+#define RTC_GPIOCTL0_CTLSEL2_Pos         (19)                                              /*!< RTC_T::GPIOCTL0: CTLSEL2 Position      */
+#define RTC_GPIOCTL0_CTLSEL2_Msk         (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos)               /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL2_Pos          (20)                                              /*!< RTC_T::GPIOCTL0: PUSEL2 Position       */
+#define RTC_GPIOCTL0_PUSEL2_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL2 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE3_Pos         (24)                                              /*!< RTC_T::GPIOCTL0: OPMODE3 Position      */
+#define RTC_GPIOCTL0_OPMODE3_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE3 Mask          */
+
+#define RTC_GPIOCTL0_DOUT3_Pos           (26)                                              /*!< RTC_T::GPIOCTL0: DOUT3 Position        */
+#define RTC_GPIOCTL0_DOUT3_Msk           (0x1ul << RTC_GPIOCTL0_DOUT3_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT3 Mask            */
+
+#define RTC_GPIOCTL0_CTLSEL3_Pos         (27)                                              /*!< RTC_T::GPIOCTL0: CTLSEL3 Position      */
+#define RTC_GPIOCTL0_CTLSEL3_Msk         (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos)               /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL3_Pos          (28)                                              /*!< RTC_T::GPIOCTL0: PUSEL3 Position       */
+#define RTC_GPIOCTL0_PUSEL3_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL3 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE4_Pos         (0)                                               /*!< RTC_T::GPIOCTL1: OPMODE4 Position      */
+#define RTC_GPIOCTL1_OPMODE4_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE4 Mask          */
+
+#define RTC_GPIOCTL1_DOUT4_Pos           (2)                                               /*!< RTC_T::GPIOCTL1: DOUT4 Position        */
+#define RTC_GPIOCTL1_DOUT4_Msk           (0x1ul << RTC_GPIOCTL1_DOUT4_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT4 Mask            */
+
+#define RTC_GPIOCTL1_CTLSEL4_Pos         (3)                                               /*!< RTC_T::GPIOCTL1: CTLSEL4 Position      */
+#define RTC_GPIOCTL1_CTLSEL4_Msk         (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos)               /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL4_Pos          (4)                                               /*!< RTC_T::GPIOCTL1: PUSEL4 Position       */
+#define RTC_GPIOCTL1_PUSEL4_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL4 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE5_Pos         (8)                                               /*!< RTC_T::GPIOCTL1: OPMODE5 Position      */
+#define RTC_GPIOCTL1_OPMODE5_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE5 Mask          */
+
+#define RTC_GPIOCTL1_DOUT5_Pos           (10)                                              /*!< RTC_T::GPIOCTL1: DOUT5 Position        */
+#define RTC_GPIOCTL1_DOUT5_Msk           (0x1ul << RTC_GPIOCTL1_DOUT5_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT5 Mask            */
+
+#define RTC_GPIOCTL1_CTLSEL5_Pos         (11)                                              /*!< RTC_T::GPIOCTL1: CTLSEL5 Position      */
+#define RTC_GPIOCTL1_CTLSEL5_Msk         (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos)               /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL5_Pos          (12)                                              /*!< RTC_T::GPIOCTL1: PUSEL5 Position       */
+#define RTC_GPIOCTL1_PUSEL5_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL5 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE6_Pos         (16)                                              /*!< RTC_T::GPIOCTL1: OPMODE6 Position      */
+#define RTC_GPIOCTL1_OPMODE6_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE6 Mask          */
+
+#define RTC_GPIOCTL1_DOUT6_Pos           (18)                                              /*!< RTC_T::GPIOCTL1: DOUT6 Position        */
+#define RTC_GPIOCTL1_DOUT6_Msk           (0x1ul << RTC_GPIOCTL1_DOUT6_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT6 Mask            */
+
+#define RTC_GPIOCTL1_CTLSEL6_Pos         (19)                                              /*!< RTC_T::GPIOCTL1: CTLSEL6 Position      */
+#define RTC_GPIOCTL1_CTLSEL6_Msk         (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos)               /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL6_Pos          (20)                                              /*!< RTC_T::GPIOCTL1: PUSEL6 Position       */
+#define RTC_GPIOCTL1_PUSEL6_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL6 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE7_Pos         (24)                                              /*!< RTC_T::GPIOCTL1: OPMODE7 Position      */
+#define RTC_GPIOCTL1_OPMODE7_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE7 Mask          */
+
+#define RTC_GPIOCTL1_DOUT7_Pos           (26)                                              /*!< RTC_T::GPIOCTL1: DOUT7 Position        */
+#define RTC_GPIOCTL1_DOUT7_Msk           (0x1ul << RTC_GPIOCTL1_DOUT7_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT7 Mask            */
+
+#define RTC_GPIOCTL1_CTLSEL7_Pos         (27)                                              /*!< RTC_T::GPIOCTL1: CTLSEL7 Position      */
+#define RTC_GPIOCTL1_CTLSEL7_Msk         (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos)               /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL7_Pos          (28)                                              /*!< RTC_T::GPIOCTL1: PUSEL7 Position       */
+#define RTC_GPIOCTL1_PUSEL7_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL7 Mask           */
+
+#define RTC_DSTCTL_ADDHR_Pos             (0)                                               /*!< RTC_T::DSTCTL: ADDHR Position          */
+#define RTC_DSTCTL_ADDHR_Msk             (0x1ul << RTC_DSTCTL_ADDHR_Pos)                   /*!< RTC_T::DSTCTL: ADDHR Mask              */
+
+#define RTC_DSTCTL_SUBHR_Pos             (1)                                               /*!< RTC_T::DSTCTL: SUBHR Position          */
+#define RTC_DSTCTL_SUBHR_Msk             (0x1ul << RTC_DSTCTL_SUBHR_Pos)                   /*!< RTC_T::DSTCTL: SUBHR Mask              */
+
+#define RTC_DSTCTL_DSBAK_Pos             (2)                                               /*!< RTC_T::DSTCTL: DSBAK Position          */
+#define RTC_DSTCTL_DSBAK_Msk             (0x1ul << RTC_DSTCTL_DSBAK_Pos)                   /*!< RTC_T::DSTCTL: DSBAK Mask              */
+
+#define RTC_TAMPCTL_DYN1ISS_Pos          (0)                                               /*!< RTC_T::TAMPCTL: DYN1ISS Position       */
+#define RTC_TAMPCTL_DYN1ISS_Msk          (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos)                /*!< RTC_T::TAMPCTL: DYN1ISS Mask           */
+
+#define RTC_TAMPCTL_DYN2ISS_Pos          (1)                                               /*!< RTC_T::TAMPCTL: DYN2ISS Position       */
+#define RTC_TAMPCTL_DYN2ISS_Msk          (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos)                /*!< RTC_T::TAMPCTL: DYN2ISS Mask           */
+
+#define RTC_TAMPCTL_DYNSRC_Pos           (2)                                               /*!< RTC_T::TAMPCTL: DYNSRC Position        */
+#define RTC_TAMPCTL_DYNSRC_Msk           (0x3ul << RTC_TAMPCTL_DYNSRC_Pos)                 /*!< RTC_T::TAMPCTL: DYNSRC Mask            */
+
+#define RTC_TAMPCTL_SEEDRLD_Pos          (4)                                               /*!< RTC_T::TAMPCTL: SEEDRLD Position       */
+#define RTC_TAMPCTL_SEEDRLD_Msk          (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos)                /*!< RTC_T::TAMPCTL: SEEDRLD Mask           */
+
+#define RTC_TAMPCTL_DYNRATE_Pos          (5)                                               /*!< RTC_T::TAMPCTL: DYNRATE Position       */
+#define RTC_TAMPCTL_DYNRATE_Msk          (0x7ul << RTC_TAMPCTL_DYNRATE_Pos)                /*!< RTC_T::TAMPCTL: DYNRATE Mask           */
+
+#define RTC_TAMPCTL_TAMP0EN_Pos          (8)                                               /*!< RTC_T::TAMPCTL: TAMP0EN Position       */
+#define RTC_TAMPCTL_TAMP0EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP0EN Mask           */
+
+#define RTC_TAMPCTL_TAMP0LV_Pos          (9)                                               /*!< RTC_T::TAMPCTL: TAMP0LV Position       */
+#define RTC_TAMPCTL_TAMP0LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP0LV Mask           */
+
+#define RTC_TAMPCTL_TAMP0DBEN_Pos        (10)                                              /*!< RTC_T::TAMPCTL: TAMP0DBEN Position     */
+#define RTC_TAMPCTL_TAMP0DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP1EN_Pos          (12)                                              /*!< RTC_T::TAMPCTL: TAMP1EN Position       */
+#define RTC_TAMPCTL_TAMP1EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP1EN Mask           */
+
+#define RTC_TAMPCTL_TAMP1LV_Pos          (13)                                              /*!< RTC_T::TAMPCTL: TAMP1LV Position       */
+#define RTC_TAMPCTL_TAMP1LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP1LV Mask           */
+
+#define RTC_TAMPCTL_TAMP1DBEN_Pos        (14)                                              /*!< RTC_T::TAMPCTL: TAMP1DBEN Position     */
+#define RTC_TAMPCTL_TAMP1DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR0EN_Pos         (15)                                              /*!< RTC_T::TAMPCTL: DYNPR0EN Position      */
+#define RTC_TAMPCTL_DYNPR0EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR0EN Mask          */
+
+#define RTC_TAMPCTL_TAMP2EN_Pos          (16)                                              /*!< RTC_T::TAMPCTL: TAMP2EN Position       */
+#define RTC_TAMPCTL_TAMP2EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP2EN Mask           */
+
+#define RTC_TAMPCTL_TAMP2LV_Pos          (17)                                              /*!< RTC_T::TAMPCTL: TAMP2LV Position       */
+#define RTC_TAMPCTL_TAMP2LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP2LV Mask           */
+
+#define RTC_TAMPCTL_TAMP2DBEN_Pos        (18)                                              /*!< RTC_T::TAMPCTL: TAMP2DBEN Position     */
+#define RTC_TAMPCTL_TAMP2DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP3EN_Pos          (20)                                              /*!< RTC_T::TAMPCTL: TAMP3EN Position       */
+#define RTC_TAMPCTL_TAMP3EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP3EN Mask           */
+
+#define RTC_TAMPCTL_TAMP3LV_Pos          (21)                                              /*!< RTC_T::TAMPCTL: TAMP3LV Position       */
+#define RTC_TAMPCTL_TAMP3LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP3LV Mask           */
+
+#define RTC_TAMPCTL_TAMP3DBEN_Pos        (22)                                              /*!< RTC_T::TAMPCTL: TAMP3DBEN Position     */
+#define RTC_TAMPCTL_TAMP3DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR1EN_Pos         (23)                                              /*!< RTC_T::TAMPCTL: DYNPR1EN Position      */
+#define RTC_TAMPCTL_DYNPR1EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR1EN Mask          */
+
+#define RTC_TAMPCTL_TAMP4EN_Pos          (24)                                              /*!< RTC_T::TAMPCTL: TAMP4EN Position       */
+#define RTC_TAMPCTL_TAMP4EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP4EN Mask           */
+
+#define RTC_TAMPCTL_TAMP4LV_Pos          (25)                                              /*!< RTC_T::TAMPCTL: TAMP4LV Position       */
+#define RTC_TAMPCTL_TAMP4LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP4LV Mask           */
+
+#define RTC_TAMPCTL_TAMP4DBEN_Pos        (26)                                              /*!< RTC_T::TAMPCTL: TAMP4DBEN Position     */
+#define RTC_TAMPCTL_TAMP4DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP5EN_Pos          (28)                                              /*!< RTC_T::TAMPCTL: TAMP5EN Position       */
+#define RTC_TAMPCTL_TAMP5EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP5EN Mask           */
+
+#define RTC_TAMPCTL_TAMP5LV_Pos          (29)                                              /*!< RTC_T::TAMPCTL: TAMP5LV Position       */
+#define RTC_TAMPCTL_TAMP5LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP5LV Mask           */
+
+#define RTC_TAMPCTL_TAMP5DBEN_Pos        (30)                                              /*!< RTC_T::TAMPCTL: TAMP5DBEN Position     */
+#define RTC_TAMPCTL_TAMP5DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR2EN_Pos         (31)                                              /*!< RTC_T::TAMPCTL: DYNPR2EN Position      */
+#define RTC_TAMPCTL_DYNPR2EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR2EN Mask          */
+
+#define RTC_TAMPSEED_SEED_Pos            (0)                                               /*!< RTC_T::TAMPSEED: SEED Position         */
+#define RTC_TAMPSEED_SEED_Msk            (0xfffffffful << RTC_TAMPSEED_SEED_Pos)           /*!< RTC_T::TAMPSEED: SEED Mask             */
+
+#define RTC_TAMPTIME_SEC_Pos             (0)                                               /*!< RTC_T::TAMPTIME: SEC Position          */
+#define RTC_TAMPTIME_SEC_Msk             (0xful << RTC_TAMPTIME_SEC_Pos)                   /*!< RTC_T::TAMPTIME: SEC Mask              */
+
+#define RTC_TAMPTIME_TENSEC_Pos          (4)                                               /*!< RTC_T::TAMPTIME: TENSEC Position       */
+#define RTC_TAMPTIME_TENSEC_Msk          (0x7ul << RTC_TAMPTIME_TENSEC_Pos)                /*!< RTC_T::TAMPTIME: TENSEC Mask           */
+
+#define RTC_TAMPTIME_MIN_Pos             (8)                                               /*!< RTC_T::TAMPTIME: MIN Position          */
+#define RTC_TAMPTIME_MIN_Msk             (0xful << RTC_TAMPTIME_MIN_Pos)                   /*!< RTC_T::TAMPTIME: MIN Mask              */
+
+#define RTC_TAMPTIME_TENMIN_Pos          (12)                                              /*!< RTC_T::TAMPTIME: TENMIN Position       */
+#define RTC_TAMPTIME_TENMIN_Msk          (0x7ul << RTC_TAMPTIME_TENMIN_Pos)                /*!< RTC_T::TAMPTIME: TENMIN Mask           */
+
+#define RTC_TAMPTIME_HR_Pos              (16)                                              /*!< RTC_T::TAMPTIME: HR Position           */
+#define RTC_TAMPTIME_HR_Msk              (0xful << RTC_TAMPTIME_HR_Pos)                    /*!< RTC_T::TAMPTIME: HR Mask               */
+
+#define RTC_TAMPTIME_TENHR_Pos           (20)                                              /*!< RTC_T::TAMPTIME: TENHR Position        */
+#define RTC_TAMPTIME_TENHR_Msk           (0x3ul << RTC_TAMPTIME_TENHR_Pos)                 /*!< RTC_T::TAMPTIME: TENHR Mask            */
+
+#define RTC_TAMPCAL_DAY_Pos              (0)                                               /*!< RTC_T::TAMPCAL: DAY Position           */
+#define RTC_TAMPCAL_DAY_Msk              (0xful << RTC_TAMPCAL_DAY_Pos)                    /*!< RTC_T::TAMPCAL: DAY Mask               */
+
+#define RTC_TAMPCAL_TENDAY_Pos           (4)                                               /*!< RTC_T::TAMPCAL: TENDAY Position        */
+#define RTC_TAMPCAL_TENDAY_Msk           (0x3ul << RTC_TAMPCAL_TENDAY_Pos)                 /*!< RTC_T::TAMPCAL: TENDAY Mask            */
+
+#define RTC_TAMPCAL_MON_Pos              (8)                                               /*!< RTC_T::TAMPCAL: MON Position           */
+#define RTC_TAMPCAL_MON_Msk              (0xful << RTC_TAMPCAL_MON_Pos)                    /*!< RTC_T::TAMPCAL: MON Mask               */
+
+#define RTC_TAMPCAL_TENMON_Pos           (12)                                              /*!< RTC_T::TAMPCAL: TENMON Position        */
+#define RTC_TAMPCAL_TENMON_Msk           (0x1ul << RTC_TAMPCAL_TENMON_Pos)                 /*!< RTC_T::TAMPCAL: TENMON Mask            */
+
+#define RTC_TAMPCAL_YEAR_Pos             (16)                                              /*!< RTC_T::TAMPCAL: YEAR Position          */
+#define RTC_TAMPCAL_YEAR_Msk             (0xful << RTC_TAMPCAL_YEAR_Pos)                   /*!< RTC_T::TAMPCAL: YEAR Mask              */
+
+#define RTC_TAMPCAL_TENYEAR_Pos          (20)                                              /*!< RTC_T::TAMPCAL: TENYEAR Position       */
+#define RTC_TAMPCAL_TENYEAR_Msk          (0xful << RTC_TAMPCAL_TENYEAR_Pos)                /*!< RTC_T::TAMPCAL: TENYEAR Mask           */
+
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+
+
+
+/*---------------------- Pulse Width Modulation Controller -------------------------*/
+/**
+    @addtogroup EPWM Pulse Width Modulation Controller(EPWM)
+    Memory Mapped Structure for EPWM Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var EPWM_T::CTL0
+     * Offset: 0x00  EPWM Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTRLD0    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[1]     |CTRLD1    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[2]     |CTRLD2    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[3]     |CTRLD3    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[4]     |CTRLD4    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[5]     |CTRLD5    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[8]     |WINLDEN0  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[9]     |WINLDEN1  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[10]    |WINLDEN2  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[11]    |WINLDEN3  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[12]    |WINLDEN4  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[13]    |WINLDEN5  |Window Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
+     * |[16]    |IMMLDEN0  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[17]    |IMMLDEN1  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[18]    |IMMLDEN2  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[19]    |IMMLDEN3  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[20]    |IMMLDEN4  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[21]    |IMMLDEN5  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+     * |[24]    |GROUPEN   |Group Function Enable Bit(S)
+     * |        |          |0 = The output waveform of each EPWM channel are independent.
+     * |        |          |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt disable.
+     * |        |          |1 = ICE debug mode counter halt enable.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects EPWM output.
+     * |        |          |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement disabled.
+     * |        |          |EPWM pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var EPWM_T::CTL1
+     * Offset: 0x04  EPWM Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CNTTYPE0  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[3:2]   |CNTTYPE1  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[5:4]   |CNTTYPE2  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[7:6]   |CNTTYPE3  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[9:8]   |CNTTYPE4  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[11:10] |CNTTYPE5  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[16]    |CNTMODE0  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[17]    |CNTMODE1  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[18]    |CNTMODE2  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[19]    |CNTMODE3  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[20]    |CNTMODE4  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[21]    |CNTMODE5  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[24]    |OUTMODE0  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * |[25]    |OUTMODE2  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * |[26]    |OUTMODE4  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * @var EPWM_T::SYNC
+     * Offset: 0x08  EPWM Synchronization Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PHSEN0    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[1]     |PHSEN2    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[2]     |PHSEN4    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[9:8]   |SINSRC0   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[11:10] |SINSRC2   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[13:12] |SINSRC4   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[16]    |SNFLTEN   |EPWM0_SYNC_IN Noise Filter Enable Bits
+     * |        |          |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
+     * |        |          |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
+     * |[19:17] |SFLTCSEL  |SYNC Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[22:20] |SFLTCNT   |SYNC Edge Detector Filter Count
+     * |        |          |The register bits control the counter number of edge detector.
+     * |[23]    |SINPINV   |SYNC Input Pin Inverse
+     * |        |          |0 = The state of pin SYNC is passed to the negative edge detector.
+     * |        |          |1 = The inversed state of pin SYNC is passed to the negative edge detector.
+     * |[24]    |PHSDIR0   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * |[25]    |PHSDIR2   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * |[26]    |PHSDIR4   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * @var EPWM_T::SWSYNC
+     * Offset: 0x0C  EPWM Software Control Synchronization Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SWSYNC0   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * |[1]     |SWSYNC2   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * |[2]     |SWSYNC4   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * @var EPWM_T::CLKSRC
+     * Offset: 0x10  EPWM Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |ECLKSRC0  |EPWM_CH01 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * |[10:8]  |ECLKSRC2  |EPWM_CH23 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * |[18:16] |ECLKSRC4  |EPWM_CH45 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * @var EPWM_T::CLKPSC[3]
+     * Offset: 0x14  EPWM Clock Prescale Register 0/1, 2/3, 4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |EPWM Counter Clock Prescale
+     * |        |          |The clock of EPWM counter is decided by clock prescaler
+     * |        |          |Each EPWM pair share one EPWM counter clock prescaler
+     * |        |          |The clock of EPWM counter is divided by (CLKPSC+ 1)
+     * @var EPWM_T::CNTEN
+     * Offset: 0x20  EPWM Counter Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN0    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[1]     |CNTEN1    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[2]     |CNTEN2    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[3]     |CNTEN3    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[4]     |CNTEN4    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[5]     |CNTEN5    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * @var EPWM_T::CNTCLR
+     * Offset: 0x24  EPWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR0   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[1]     |CNTCLR1   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[2]     |CNTCLR2   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[3]     |CNTCLR3   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[4]     |CNTCLR4   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[5]     |CNTCLR5   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * @var EPWM_T::LOAD
+     * Offset: 0x28  EPWM Load Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LOAD0     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * |[1]     |LOAD1     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * |[2]     |LOAD2     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * |[3]     |LOAD3     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * |[4]     |LOAD4     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * |[5]     |LOAD5     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * @var EPWM_T::PERIOD[6]
+     * Offset: 0x30  EPWM Period Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |EPWM Period Register
+     * |        |          |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |EPWM period time = (PERIOD+1) * EPWM_CLK period.
+     * |        |          |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |EPWM period time = 2 * PERIOD * EPWM_CLK period.
+     * @var EPWM_T::CMPDAT[6]
+     * Offset: 0x50  EPWM Comparator Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMP       |EPWM Comparator Register
+     * |        |          |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
+     * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
+     * |        |          |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+     * @var EPWM_T::DTCTL[3]
+     * Offset: 0x70  EPWM Dead-Time Control Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DTCNT     |Dead-time Counter (Write Protect)
+     * |        |          |The dead-time can be calculated from the following formula:
+     * |        |          |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[16]    |DTEN      |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
+     * |        |          |Dead-time insertion is only active when this pair of complementary EPWM is enabled
+     * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+     * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+     * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[24]    |DTCKSEL   |Dead-time Clock Select (Write Protect)
+     * |        |          |0 = Dead-time clock source from EPWM_CLK.
+     * |        |          |1 = Dead-time clock source from prescaler output.
+     * |        |          |Note: This register is write protected. Refer toREGWRPROT register.
+     * @var EPWM_T::PHS[3]
+     * Offset: 0x80  EPWM Counter Phase Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PHS       |EPWM Synchronous Start Phase Bits
+     * |        |          |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
+     * @var EPWM_T::CNT[6]
+     * Offset: 0x90  EPWM Counter Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |EPWM Data Register (Read Only)
+     * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+     * |[16]    |DIRF      |EPWM Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is Down count.
+     * |        |          |1 = Counter is UP count.
+     * @var EPWM_T::WGCTL0
+     * Offset: 0xB0  EPWM Generation Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |ZPCTL0    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[3:2]   |ZPCTL1    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[5:4]   |ZPCTL2    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[7:6]   |ZPCTL3    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[9:8]   |ZPCTL4    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[11:10] |ZPCTL5    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[17:16] |PRDPCTL0  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[19:18] |PRDPCTL1  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[21:20] |PRDPCTL2  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[23:22] |PRDPCTL3  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[25:24] |PRDPCTL4  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[27:26] |PRDPCTL5  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIODn+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * @var EPWM_T::WGCTL1
+     * Offset: 0xB4  EPWM Generation Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CMPUCTL0  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[3:2]   |CMPUCTL1  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[5:4]   |CMPUCTL2  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[7:6]   |CMPUCTL3  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[9:8]   |CMPUCTL4  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[11:10] |CMPUCTL5  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[17:16] |CMPDCTL0  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[19:18] |CMPDCTL1  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[21:20] |CMPDCTL2  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[23:22] |CMPDCTL3  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[25:24] |CMPDCTL4  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[27:26] |CMPDCTL5  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * @var EPWM_T::MSKEN
+     * Offset: 0xB8  EPWM Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * |[1]     |MSKEN1    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * |[2]     |MSKEN2    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * |[3]     |MSKEN3    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * |[4]     |MSKEN4    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * |[5]     |MSKEN5    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDATn data.
+     * @var EPWM_T::MSK
+     * Offset: 0xBC  EPWM Mask Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * |[1]     |MSKDAT1   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * |[2]     |MSKDAT2   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * |[3]     |MSKDAT3   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * |[4]     |MSKDAT4   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * |[5]     |MSKDAT5   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM channel n.
+     * |        |          |1 = Output logic high to EPWM channel n.
+     * @var EPWM_T::BNF
+     * Offset: 0xC0  EPWM Brake Noise Filter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRK0NFEN  |EPWM Brake 0 Noise Filter Enable Bit
+     * |        |          |0 = Noise filter of EPWM Brake 0 Disabled.
+     * |        |          |1 = Noise filter of EPWM Brake 0 Enabled.
+     * |[3:1]   |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[6:4]   |BRK0FCNT  |Brake 0 Edge Detector Filter Count
+     * |        |          |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
+     * |[7]     |BRK0PINV  |Brake 0 Pin Inverse
+     * |        |          |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
+     * |        |          |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector.
+     * |[8]     |BRK1NFEN  |EPWM Brake 1 Noise Filter Enable Bit
+     * |        |          |0 = Noise filter of EPWM Brake 1 Disabled.
+     * |        |          |1 = Noise filter of EPWM Brake 1 Enabled.
+     * |[11:9]  |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[14:12] |BRK1FCNT  |Brake 1 Edge Detector Filter Count
+     * |        |          |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
+     * |[15]    |BRK1PINV  |Brake 1 Pin Inverse
+     * |        |          |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+     * |        |          |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+     * |[16]    |BK0SRC    |Brake 0 Pin Source Select
+     * |        |          |For EPWM0 setting:
+     * |        |          |0 = Brake 0 pin source come from EPWM0_BRAKE0.
+     * |        |          |1 = Brake 0 pin source come from EPWM1_BRAKE0.
+     * |        |          |For EPWM1 setting:
+     * |        |          |0 = Brake 0 pin source come from EPWM1_BRAKE0.
+     * |        |          |1 = Brake 0 pin source come from EPWM0_BRAKE0.
+     * |[24]    |BK1SRC    |Brake 1 Pin Source Select
+     * |        |          |For EPWM0 setting:
+     * |        |          |0 = Brake 1 pin source come from EPWM0_BRAKE1.
+     * |        |          |1 = Brake 1 pin source come from EPWM1_BRAKE1.
+     * |        |          |For EPWM1 setting:
+     * |        |          |0 = Brake 1 pin source come from EPWM1_BRAKE1.
+     * |        |          |1 = Brake 1 pin source come from EPWM0_BRAKE1.
+     * @var EPWM_T::FAILBRK
+     * Offset: 0xC4  EPWM System Fail Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CSSBRKEN  |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by CSS detection Disabled.
+     * |        |          |1 = Brake Function triggered by CSS detection Enabled.
+     * |[1]     |BODBRKEN  |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by BOD Disabled.
+     * |        |          |1 = Brake Function triggered by BOD Enabled.
+     * |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.
+     * |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.
+     * |[3]     |CORBRKEN  |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by Core lockup detection Disabled.
+     * |        |          |1 = Brake Function triggered by Core lockup detection Enabled.
+     * @var EPWM_T::BRKCTL[3]
+     * Offset: 0xC8  EPWM Brake Edge Detect Control Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP0_O as edge-detect brake source Disabled.
+     * |        |          |1 = ACMP0_O as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP1_O as edge-detect brake source Disabled.
+     * |        |          |1 = ACMP1_O as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[4]     |BRKP0EEN  |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[5]     |BRKP1EEN  |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[7]     |SYSEBEN   |Enable System Fail As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = System Fail condition as edge-detect brake source Disabled.
+     * |        |          |1 = System Fail condition as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP0_O as level-detect brake source Disabled.
+     * |        |          |1 = ACMP0_O as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP1_O as level-detect brake source Disabled.
+     * |        |          |1 = ACMP1_O as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[15]    |SYSLBEN   |Enable System Fail As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = System Fail condition as level-detect brake source Disabled.
+     * |        |          |1 = System Fail condition as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[17:16] |BRKAEVEN  |EPWM Brake Action Select for Even Channel (Write Protect)
+     * |        |          |00 = EPWMx brake event will not affect even channels output.
+     * |        |          |01 = EPWM even channel output tri-state when EPWMx brake event happened.
+     * |        |          |10 = EPWM even channel output low level when EPWMx brake event happened.
+     * |        |          |11 = EPWM even channel output high level when EPWMx brake event happened.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[19:18] |BRKAODD   |EPWM Brake Action Select for Odd Channel (Write Protect)
+     * |        |          |00 = EPWMx brake event will not affect odd channels output.
+     * |        |          |01 = EPWM odd channel output tri-state when EPWMx brake event happened.
+     * |        |          |10 = EPWM odd channel output low level when EPWMx brake event happened.
+     * |        |          |11 = EPWM odd channel output high level when EPWMx brake event happened.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[20]    |EADCEBEN  |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EADCRM as edge-detect brake source Disabled.
+     * |        |          |1 = EADCRM as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[28]    |EADCLBEN  |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EADCRM as level-detect brake source Disabled.
+     * |        |          |1 = EADCRM as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var EPWM_T::POLCTL
+     * Offset: 0xD4  EPWM Pin Polar Inverse Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * |[1]     |PINV1     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * |[2]     |PINV2     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * |[3]     |PINV3     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * |[4]     |PINV4     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * |[5]     |PINV5     |EPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM output.
+     * |        |          |0 = EPWM output polar inverse Disabled.
+     * |        |          |1 = EPWM output polar inverse Enabled.
+     * @var EPWM_T::POEN
+     * Offset: 0xD8  EPWM Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * |[1]     |POEN1     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * |[2]     |POEN2     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * |[3]     |POEN3     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * |[4]     |POEN4     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * |[5]     |POEN5     |EPWM Pin Output Enable Bits
+     * |        |          |0 = EPWM pin at tri-state.
+     * |        |          |1 = EPWM pin in output mode.
+     * @var EPWM_T::SWBRK
+     * Offset: 0xDC  EPWM Software Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKETRG0  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |BRKETRG2  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[2]     |BRKETRG4  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLTRG0  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |BRKLTRG2  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[10]    |BRKLTRG4  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var EPWM_T::INTEN0
+     * Offset: 0xE0  EPWM Interrupt Enable Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN0     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[1]     |ZIEN1     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[2]     |ZIEN2     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[3]     |ZIEN3     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[4]     |ZIEN4     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[5]     |ZIEN5     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[8]     |PIEN0     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[9]     |PIEN1     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[10]    |PIEN2     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[11]    |PIEN3     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[12]    |PIEN4     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[13]    |PIEN5     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[16]    |CMPUIEN0  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[17]    |CMPUIEN1  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[18]    |CMPUIEN2  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[19]    |CMPUIEN3  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[20]    |CMPUIEN4  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[21]    |CMPUIEN5  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[24]    |CMPDIEN0  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[25]    |CMPDIEN1  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[26]    |CMPDIEN2  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[27]    |CMPDIEN3  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[28]    |CMPDIEN4  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[29]    |CMPDIEN5  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * @var EPWM_T::INTEN1
+     * Offset: 0xE4  EPWM Interrupt Enable Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[2]     |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel0/1 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel0/1 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel2/3 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel2/3 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[10]    |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel4/5 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel4/5 Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var EPWM_T::INTSTS0
+     * Offset: 0xE8  EPWM Interrupt Flag Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF0      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[1]     |ZIF1      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[2]     |ZIF2      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[3]     |ZIF3      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[4]     |ZIF4      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[5]     |ZIF5      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[8]     |PIF0      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[9]     |PIF1      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[10]    |PIF2      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[11]    |PIF3      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[12]    |PIF4      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[13]    |PIF5      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[16]    |CMPUIF0   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[17]    |CMPUIF1   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[18]    |CMPUIF2   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[19]    |CMPUIF3   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[20]    |CMPUIF4   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[21]    |CMPUIF5   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[24]    |CMPDIF0   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[25]    |CMPDIF1   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[26]    |CMPDIF2   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[27]    |CMPDIF3   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[28]    |CMPDIF4   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[29]    |CMPDIF5   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * @var EPWM_T::INTSTS1
+     * Offset: 0xEC  EPWM Interrupt Flag Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIF0   |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel0 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[1]     |BRKEIF1   |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel1 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[2]     |BRKEIF2   |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel2 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[3]     |BRKEIF3   |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel3 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[4]     |BRKEIF4   |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel4 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[5]     |BRKEIF5   |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel5 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[8]     |BRKLIF0   |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel0 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[9]     |BRKLIF1   |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel1 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[10]    |BRKLIF2   |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel2 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[11]    |BRKLIF3   |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel3 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[12]    |BRKLIF4   |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel4 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[13]    |BRKLIF5   |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel5 level-detect brake event do not happened.
+     * |        |          |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[16]    |BRKESTS0  |EPWM Channel0 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel0 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
+     * |[17]    |BRKESTS1  |EPWM Channel1 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel1 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
+     * |[18]    |BRKESTS2  |EPWM Channel2 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel2 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
+     * |[19]    |BRKESTS3  |EPWM Channel3 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel3 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
+     * |[20]    |BRKESTS4  |EPWM Channel4 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel4 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
+     * |[21]    |BRKESTS5  |EPWM Channel5 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel5 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
+     * |[24]    |BRKLSTS0  |EPWM Channel0 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel0 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[25]    |BRKLSTS1  |EPWM Channel1 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel1 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[26]    |BRKLSTS2  |EPWM Channel2 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel2 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[27]    |BRKLSTS3  |EPWM Channel3 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel3 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[28]    |BRKLSTS4  |EPWM Channel4 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel4 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[29]    |BRKLSTS5  |EPWM Channel5 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel5 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * @var EPWM_T::DACTRGEN
+     * Offset: 0xF4  EPWM Trigger DAC Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZTE0      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[1]     |ZTE1      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[2]     |ZTE2      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[3]     |ZTE3      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[4]     |ZTE4      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[5]     |ZTE5      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[8]     |PTE0      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[9]     |PTE1      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[10]    |PTE2      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[11]    |PTE3      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[12]    |PTE4      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[13]    |PTE5      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[16]    |CUTRGE0   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[17]    |CUTRGE1   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[18]    |CUTRGE2   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[19]    |CUTRGE3   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[20]    |CUTRGE4   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[21]    |CUTRGE5   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[24]    |CDTRGE0   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[25]    |CDTRGE1   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[26]    |CDTRGE2   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[27]    |CDTRGE3   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[28]    |CDTRGE4   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[29]    |CDTRGE5   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * @var EPWM_T::EADCTS0
+     * Offset: 0xF8  EPWM Trigger EADC Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL0   |EPWM_CH0 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH0 zero point.
+     * |        |          |0001 = EPWM_CH0 period point.
+     * |        |          |0010 = EPWM_CH0 zero or period point.
+     * |        |          |0011 = EPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH1 zero point.
+     * |        |          |0110 = EPWM_CH1 period point.
+     * |        |          |0111 = EPWM_CH1 zero or period point.
+     * |        |          |1000 = EPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH1 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[7]     |TRGEN0    |EPWM_CH0 Trigger EADC enable bit
+     * |[11:8]  |TRGSEL1   |EPWM_CH1 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH0 zero point.
+     * |        |          |0001 = EPWM_CH0 period point.
+     * |        |          |0010 = EPWM_CH0 zero or period point.
+     * |        |          |0011 = EPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH1 zero point.
+     * |        |          |0110 = EPWM_CH1 period point.
+     * |        |          |0111 = EPWM_CH1 zero or period point.
+     * |        |          |1000 = EPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH1 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[15]    |TRGEN1    |EPWM_CH1 Trigger EADC enable bit
+     * |[19:16] |TRGSEL2   |EPWM_CH2 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH2 zero point.
+     * |        |          |0001 = EPWM_CH2 period point.
+     * |        |          |0010 = EPWM_CH2 zero or period point.
+     * |        |          |0011 = EPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH3 zero point.
+     * |        |          |0110 = EPWM_CH3 period point.
+     * |        |          |0111 = EPWM_CH3 zero or period point.
+     * |        |          |1000 = EPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH3 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[23]    |TRGEN2    |EPWM_CH2 Trigger EADC enable bit
+     * |[27:24] |TRGSEL3   |EPWM_CH3 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH2 zero point.
+     * |        |          |0001 = EPWM_CH2 period point.
+     * |        |          |0010 = EPWM_CH2 zero or period point.
+     * |        |          |0011 = EPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH3 zero point.
+     * |        |          |0110 = EPWM_CH3 period point.
+     * |        |          |0111 = EPWM_CH3 zero or period point.
+     * |        |          |1000 = EPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH3 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[31]    |TRGEN3    |EPWM_CH3 Trigger EADC enable bit
+     * @var EPWM_T::EADCTS1
+     * Offset: 0xFC  EPWM Trigger EADC Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL4   |EPWM_CH4 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH4 zero point.
+     * |        |          |0001 = EPWM_CH4 period point.
+     * |        |          |0010 = EPWM_CH4 zero or period point.
+     * |        |          |0011 = EPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH5 zero point.
+     * |        |          |0110 = EPWM_CH5 period point.
+     * |        |          |0111 = EPWM_CH5 zero or period point.
+     * |        |          |1000 = EPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH5 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[7]     |TRGEN4    |EPWM_CH4 Trigger EADC enable bit
+     * |[11:8]  |TRGSEL5   |EPWM_CH5 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH4 zero point.
+     * |        |          |0001 = EPWM_CH4 period point.
+     * |        |          |0010 = EPWM_CH4 zero or period point.
+     * |        |          |0011 = EPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH5 zero point.
+     * |        |          |0110 = EPWM_CH5 period point.
+     * |        |          |0111 = EPWM_CH5 zero or period point.
+     * |        |          |1000 = EPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH5 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[15]    |TRGEN5    |EPWM_CH5 Trigger EADC enable bit
+     * @var EPWM_T::FTCMPDAT[3]
+     * Offset: 0x100  EPWM Free Trigger Compare Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FTCMP     |EPWM Free Trigger Compare Register
+     * |        |          |FTCMP use to compare with even CNTR to trigger EADC
+     * |        |          |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+     * @var EPWM_T::SSCTL
+     * Offset: 0x110  EPWM Synchronous Start Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSEN0     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[1]     |SSEN1     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[2]     |SSEN2     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[3]     |SSEN3     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[4]     |SSEN4     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[5]     |SSEN5     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[9:8]   |SSRC      |EPWM Synchronous Start Source Select Bits
+     * |        |          |00 = Synchronous start source come from EPWM0.
+     * |        |          |01 = Synchronous start source come from EPWM1.
+     * |        |          |10 = Synchronous start source come from BPWM0.
+     * |        |          |11 = Synchronous start source come from BPWM1.
+     * @var EPWM_T::SSTRG
+     * Offset: 0x114  EPWM Synchronous Start Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTSEN    |EPWM Counter Synchronous Start Enable (Write Only)
+     * |        |          |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
+     * |        |          |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
+     * @var EPWM_T::LEBCTL
+     * Offset: 0x118  EPWM Leading Edge Blanking Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LEBEN     |EPWM Leading Edge Blanking Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Enabled.
+     * |[8]     |SRCEN0    |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
+     * |[9]     |SRCEN2    |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
+     * |[10]    |SRCEN4    |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
+     * |[17:16] |TRGTYPE   |EPWM Leading Edge Blanking Trigger Type
+     * |        |          |0 = When detect leading edge blanking source rising edge, blanking counter start counting.
+     * |        |          |1 = When detect leading edge blanking source falling edge, blanking counter start counting.
+     * |        |          |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
+     * |        |          |3 = Reserved.
+     * @var EPWM_T::LEBCNT
+     * Offset: 0x11C  EPWM Leading Edge Blanking Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |LEBCNT    |EPWM Leading Edge Blanking Counter
+     * |        |          |This counter value decides leading edge blanking window size
+     * |        |          |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
+     * @var EPWM_T::STATUS
+     * Offset: 0x120  EPWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAXF0  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[1]     |CNTMAXF1  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[2]     |CNTMAXF2  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[3]     |CNTMAXF3  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[4]     |CNTMAXF4  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[5]     |CNTMAXF5  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[8]     |SYNCINF0  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[9]     |SYNCINF2  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[10]    |SYNCINF4  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[16]    |EADCTRGF0 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[17]    |EADCTRGF1 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[18]    |EADCTRGF2 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[19]    |EADCTRGF3 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[20]    |EADCTRGF4 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[21]    |EADCTRGF5 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[24]    |DACTRGF   |DAC Start of Conversion Flag
+     * |        |          |0 = Indicates no DAC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
+     * @var EPWM_T::IFA[6]
+     * Offset: 0x130  EPWM Interrupt Flag Accumulator Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IFACNT    |EPWM_CHn Interrupt Flag Counter
+     * |        |          |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
+     * |        |          |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
+     * |[29:28] |IFASEL    |EPWM_CHn Interrupt Flag Accumulator Source Select
+     * |        |          |00 = CNT equal to Zero in channel n.
+     * |        |          |01 = CNT equal to PERIOD in channel n.
+     * |        |          |10 = CNT equal to CMPU in channel n.
+     * |        |          |11 = CNT equal to CMPD in channel n.
+     * |[31]    |IFAEN     |EPWM_CHn Interrupt Flag Accumulator Enable Bits
+     * |        |          |0 = EPWM_CHn interrupt flag accumulator disable.
+     * |        |          |1 = EPWM_CHn interrupt flag accumulator enable.
+     * @var EPWM_T::AINTSTS
+     * Offset: 0x150  EPWM Accumulator Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IFAIF0    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[1]     |IFAIF1    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[2]     |IFAIF2    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[3]     |IFAIF3    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[4]     |IFAIF4    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[5]     |IFAIF5    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * @var EPWM_T::AINTEN
+     * Offset: 0x154  EPWM Accumulator Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IFAIEN0   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[1]     |IFAIEN1   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[2]     |IFAIEN2   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[3]     |IFAIEN3   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[4]     |IFAIEN4   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[5]     |IFAIEN5   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * @var EPWM_T::APDMACTL
+     * Offset: 0x158  EPWM Accumulator PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APDMAEN0  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[1]     |APDMAEN1  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[2]     |APDMAEN2  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[3]     |APDMAEN3  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[4]     |APDMAEN4  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[5]     |APDMAEN5  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * @var EPWM_T::CAPINEN
+     * Offset: 0x200  EPWM Capture Input Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPINEN0  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[1]     |CAPINEN1  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[2]     |CAPINEN2  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[3]     |CAPINEN3  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[4]     |CAPINEN4  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[5]     |CAPINEN5  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * @var EPWM_T::CAPCTL
+     * Offset: 0x204  EPWM Capture Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPEN0    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[1]     |CAPEN1    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[2]     |CAPEN2    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[3]     |CAPEN3    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[4]     |CAPEN4    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[5]     |CAPEN5    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[8]     |CAPINV0   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[9]     |CAPINV1   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[10]    |CAPINV2   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[11]    |CAPINV3   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[12]    |CAPINV4   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[13]    |CAPINV5   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[16]    |RCRLDEN0  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[17]    |RCRLDEN1  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[18]    |RCRLDEN2  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[19]    |RCRLDEN3  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[20]    |RCRLDEN4  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[21]    |RCRLDEN5  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[24]    |FCRLDEN0  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[25]    |FCRLDEN1  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[26]    |FCRLDEN2  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[27]    |FCRLDEN3  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[28]    |FCRLDEN4  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[29]    |FCRLDEN5  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * @var EPWM_T::CAPSTS
+     * Offset: 0x208  EPWM Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRLIFOV0  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[1]     |CRLIFOV1  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[2]     |CRLIFOV2  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[3]     |CRLIFOV3  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[4]     |CRLIFOV4  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[5]     |CRLIFOV5  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[8]     |CFLIFOV0  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[9]     |CFLIFOV1  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[10]    |CFLIFOV2  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[11]    |CFLIFOV3  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[12]    |CFLIFOV4  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[13]    |CFLIFOV5  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * @var EPWM_T::RCAPDAT0
+     * Offset: 0x20C  EPWM Rising Capture Data Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT0
+     * Offset: 0x210  EPWM Falling Capture Data Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::RCAPDAT1
+     * Offset: 0x214  EPWM Rising Capture Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT1
+     * Offset: 0x218  EPWM Falling Capture Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::RCAPDAT2
+     * Offset: 0x21C  EPWM Rising Capture Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT2
+     * Offset: 0x220  EPWM Falling Capture Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::RCAPDAT3
+     * Offset: 0x224  EPWM Rising Capture Data Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT3
+     * Offset: 0x228  EPWM Falling Capture Data Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::RCAPDAT4
+     * Offset: 0x22C  EPWM Rising Capture Data Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT4
+     * Offset: 0x230  EPWM Falling Capture Data Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::RCAPDAT5
+     * Offset: 0x234  EPWM Rising Capture Data Register 5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data Register (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::FCAPDAT5
+     * Offset: 0x238  EPWM Falling Capture Data Register 5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data Register (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     * @var EPWM_T::PDMACTL
+     * Offset: 0x23C  EPWM PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CHEN0_1   |Channel 0/1 PDMA Enable
+     * |        |          |0 = Channel 0/1 PDMA function Disabled.
+     * |        |          |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
+     * |[2:1]   |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT0/1.
+     * |        |          |10 = EPWM_FCAPDAT0/1.
+     * |        |          |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1.
+     * |[3]     |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11.
+     * |        |          |0 = EPWM_FCAPDAT0/1 is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT0/1 is the first captured data to memory.
+     * |[4]     |CHSEL0_1  |Select Channel 0/1 to Do PDMA Transfer
+     * |        |          |0 = Channel0.
+     * |        |          |1 = Channel1.
+     * |[8]     |CHEN2_3   |Channel 2/3 PDMA Enable
+     * |        |          |0 = Channel 2/3 PDMA function Disabled.
+     * |        |          |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
+     * |[10:9]  |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT2/3.
+     * |        |          |10 = EPWM_FCAPDAT2/3.
+     * |        |          |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3.
+     * |[11]    |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11.
+     * |        |          |0 = EPWM_FCAPDAT2/3 is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT2/3 is the first captured data to memory.
+     * |[12]    |CHSEL2_3  |Select Channel 2/3 to Do PDMA Transfer
+     * |        |          |0 = Channel2.
+     * |        |          |1 = Channel3.
+     * |[16]    |CHEN4_5   |Channel 4/5 PDMA Enable
+     * |        |          |0 = Channel 4/5 PDMA function Disabled.
+     * |        |          |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
+     * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT4/5.
+     * |        |          |10 = EPWM_FCAPDAT4/5.
+     * |        |          |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5.
+     * |[19]    |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11.
+     * |        |          |0 = EPWM_FCAPDAT4/5 is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT4/5 is the first captured data to memory.
+     * |[20]    |CHSEL4_5  |Select Channel 4/5 to Do PDMA Transfer
+     * |        |          |0 = Channel4.
+     * |        |          |1 = Channel5.
+     * @var EPWM_T::PDMACAP[3]
+     * Offset: 0x240  EPWM Capture Channel 01 PDMA Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CAPBUF    |EPWM Capture PDMA Register (Read Only)
+     * |        |          |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
+     * @var EPWM_T::CAPIEN
+     * Offset: 0x250  EPWM Capture Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPRIEN0  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[1]     |CAPRIEN1  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[2]     |CAPRIEN2  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[3]     |CAPRIEN3  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[4]     |CAPRIEN4  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[5]     |CAPRIEN5  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[8]     |CAPFIEN0  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |[9]     |CAPFIEN1  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |[10]    |CAPFIEN2  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |[11]    |CAPFIEN3  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |[12]    |CAPFIEN4  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |[13]    |CAPFIEN5  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * @var EPWM_T::CAPIF
+     * Offset: 0x254  EPWM Capture Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRLIF0    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[1]     |CRLIF1    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[2]     |CRLIF2    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[3]     |CRLIF3    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[4]     |CRLIF4    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[5]     |CRLIF5    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+     * |[8]     |CFLIF0    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * |[9]     |CFLIF1    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * |[10]    |CFLIF2    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * |[11]    |CFLIF3    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * |[12]    |CFLIF4    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * |[13]    |CFLIF5    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * @var EPWM_T::PBUF[6]
+     * Offset: 0x304  EPWM PERIOD0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |EPWM Period Register Buffer (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var EPWM_T::CMPBUF[6]
+     * Offset: 0x31C  EPWM CMPDAT0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |EPWM Comparator Register Buffer (Read Only)
+     * |        |          |Used as CMP active register.
+     * @var EPWM_T::CPSCBUF[3]
+     * Offset: 0x334  EPWM CLKPSC0_1/2_3/4_5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CPSCBUF   |EPWM Counter Clock Prescale Buffer
+     * |        |          |Use as EPWM counter clock prescale active register.
+     * @var EPWM_T::FTCBUF[3]
+     * Offset: 0x340  EPWM FTCMPDAT0_1/2_3/4_5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FTCMPBUF  |EPWM FTCMPDAT Buffer (Read Only)
+     * |        |          |Used as FTCMPDAT active register.
+     * @var EPWM_T::FTCI
+     * Offset: 0x34C  EPWM FTCMPDAT Indicator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FTCMU0    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[1]     |FTCMU2    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[2]     |FTCMU4    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[8]     |FTCMD0    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     * |[9]     |FTCMD2    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     * |[10]    |FTCMD4    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] EPWM Control Register 0                                           */
+    __IO uint32_t CTL1;                  /*!< [0x0004] EPWM Control Register 1                                           */
+    __IO uint32_t SYNC;                  /*!< [0x0008] EPWM Synchronization Register                                     */
+    __IO uint32_t SWSYNC;                /*!< [0x000c] EPWM Software Control Synchronization Register                    */
+    __IO uint32_t CLKSRC;                /*!< [0x0010] EPWM Clock Source Register                                        */
+    __IO uint32_t CLKPSC[3];             /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5                          */
+    __IO uint32_t CNTEN;                 /*!< [0x0020] EPWM Counter Enable Register                                      */
+    __IO uint32_t CNTCLR;                /*!< [0x0024] EPWM Clear Counter Register                                       */
+    __IO uint32_t LOAD;                  /*!< [0x0028] EPWM Load Register                                                */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PERIOD[6];             /*!< [0x0030] EPWM Period Register 0~5                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CMPDAT[6];             /*!< [0x0050] EPWM Comparator Register 0~5                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DTCTL[3];              /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PHS[3];                /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5                           */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t CNT[6];                /*!< [0x0090] EPWM Counter Register 0~5                                         */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WGCTL0;                /*!< [0x00b0] EPWM Generation Register 0                                        */
+    __IO uint32_t WGCTL1;                /*!< [0x00b4] EPWM Generation Register 1                                        */
+    __IO uint32_t MSKEN;                 /*!< [0x00b8] EPWM Mask Enable Register                                         */
+    __IO uint32_t MSK;                   /*!< [0x00bc] EPWM Mask Data Register                                           */
+    __IO uint32_t BNF;                   /*!< [0x00c0] EPWM Brake Noise Filter Register                                  */
+    __IO uint32_t FAILBRK;               /*!< [0x00c4] EPWM System Fail Brake Control Register                           */
+    __IO uint32_t BRKCTL[3];             /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5               */
+    __IO uint32_t POLCTL;                /*!< [0x00d4] EPWM Pin Polar Inverse Register                                   */
+    __IO uint32_t POEN;                  /*!< [0x00d8] EPWM Output Enable Register                                       */
+    __O  uint32_t SWBRK;                 /*!< [0x00dc] EPWM Software Brake Control Register                              */
+    __IO uint32_t INTEN0;                /*!< [0x00e0] EPWM Interrupt Enable Register 0                                  */
+    __IO uint32_t INTEN1;                /*!< [0x00e4] EPWM Interrupt Enable Register 1                                  */
+    __IO uint32_t INTSTS0;               /*!< [0x00e8] EPWM Interrupt Flag Register 0                                    */
+    __IO uint32_t INTSTS1;               /*!< [0x00ec] EPWM Interrupt Flag Register 1                                    */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE6[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DACTRGEN;              /*!< [0x00f4] EPWM Trigger DAC Enable Register                                  */
+    __IO uint32_t EADCTS0;               /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0                        */
+    __IO uint32_t EADCTS1;               /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1                        */
+    __IO uint32_t FTCMPDAT[3];           /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5                    */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE7[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t SSCTL;                 /*!< [0x0110] EPWM Synchronous Start Control Register                           */
+    __O  uint32_t SSTRG;                 /*!< [0x0114] EPWM Synchronous Start Trigger Register                           */
+    __IO uint32_t LEBCTL;                /*!< [0x0118] EPWM Leading Edge Blanking Control Register                       */
+    __IO uint32_t LEBCNT;                /*!< [0x011c] EPWM Leading Edge Blanking Counter Register                       */
+    __IO uint32_t STATUS;                /*!< [0x0120] EPWM Status Register                                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE8[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t IFA[6];                /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE9[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t AINTSTS;               /*!< [0x0150] EPWM Accumulator Interrupt Flag Register                          */
+    __IO uint32_t AINTEN;                /*!< [0x0154] EPWM Accumulator Interrupt Enable Register                        */
+    __IO uint32_t APDMACTL;              /*!< [0x0158] EPWM Accumulator PDMA Control Register                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE10[41];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPINEN;               /*!< [0x0200] EPWM Capture Input Enable Register                                */
+    __IO uint32_t CAPCTL;                /*!< [0x0204] EPWM Capture Control Register                                     */
+    __I  uint32_t CAPSTS;                /*!< [0x0208] EPWM Capture Status Register                                      */
+    __I  uint32_t RCAPDAT0;              /*!< [0x020c] EPWM Rising Capture Data Register 0                               */
+    __I  uint32_t FCAPDAT0;              /*!< [0x0210] EPWM Falling Capture Data Register 0                              */
+    __I  uint32_t RCAPDAT1;              /*!< [0x0214] EPWM Rising Capture Data Register 1                               */
+    __I  uint32_t FCAPDAT1;              /*!< [0x0218] EPWM Falling Capture Data Register 1                              */
+    __I  uint32_t RCAPDAT2;              /*!< [0x021c] EPWM Rising Capture Data Register 2                               */
+    __I  uint32_t FCAPDAT2;              /*!< [0x0220] EPWM Falling Capture Data Register 2                              */
+    __I  uint32_t RCAPDAT3;              /*!< [0x0224] EPWM Rising Capture Data Register 3                               */
+    __I  uint32_t FCAPDAT3;              /*!< [0x0228] EPWM Falling Capture Data Register 3                              */
+    __I  uint32_t RCAPDAT4;              /*!< [0x022c] EPWM Rising Capture Data Register 4                               */
+    __I  uint32_t FCAPDAT4;              /*!< [0x0230] EPWM Falling Capture Data Register 4                              */
+    __I  uint32_t RCAPDAT5;              /*!< [0x0234] EPWM Rising Capture Data Register 5                               */
+    __I  uint32_t FCAPDAT5;              /*!< [0x0238] EPWM Falling Capture Data Register 5                              */
+    __IO uint32_t PDMACTL;               /*!< [0x023c] EPWM PDMA Control Register                                        */
+    __I  uint32_t PDMACAP[3];            /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE11[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPIEN;                /*!< [0x0250] EPWM Capture Interrupt Enable Register                            */
+    __IO uint32_t CAPIF;                 /*!< [0x0254] EPWM Capture Interrupt Flag Register                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE12[43];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t PBUF[6];               /*!< [0x0304] EPWM PERIOD0~5 Buffer                                             */
+    __I  uint32_t CMPBUF[6];             /*!< [0x031c] EPWM CMPDAT0~5 Buffer                                             */
+    __I  uint32_t CPSCBUF[3];            /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer                                     */
+    __I  uint32_t FTCBUF[3];             /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer                                   */
+    __IO uint32_t FTCI;                  /*!< [0x034c] EPWM FTCMPDAT Indicator Register                                  */
+
+} EPWM_T;
+
+/**
+    @addtogroup EPWM_CONST EPWM Bit Field Definition
+    Constant Definitions for EPWM Controller
+@{ */
+
+#define EPWM_CTL0_CTRLD0_Pos              (0)                                               /*!< EPWM_T::CTL0: CTRLD0 Position           */
+#define EPWM_CTL0_CTRLD0_Msk              (0x1ul << EPWM_CTL0_CTRLD0_Pos)                   /*!< EPWM_T::CTL0: CTRLD0 Mask               */
+
+#define EPWM_CTL0_CTRLD1_Pos              (1)                                               /*!< EPWM_T::CTL0: CTRLD1 Position           */
+#define EPWM_CTL0_CTRLD1_Msk              (0x1ul << EPWM_CTL0_CTRLD1_Pos)                   /*!< EPWM_T::CTL0: CTRLD1 Mask               */
+
+#define EPWM_CTL0_CTRLD2_Pos              (2)                                               /*!< EPWM_T::CTL0: CTRLD2 Position           */
+#define EPWM_CTL0_CTRLD2_Msk              (0x1ul << EPWM_CTL0_CTRLD2_Pos)                    /*!< EPWM_T::CTL0: CTRLD2 Mask               */
+
+#define EPWM_CTL0_CTRLD3_Pos              (3)                                               /*!< EPWM_T::CTL0: CTRLD3 Position           */
+#define EPWM_CTL0_CTRLD3_Msk              (0x1ul << EPWM_CTL0_CTRLD3_Pos)                    /*!< EPWM_T::CTL0: CTRLD3 Mask               */
+
+#define EPWM_CTL0_CTRLD4_Pos              (4)                                               /*!< EPWM_T::CTL0: CTRLD4 Position           */
+#define EPWM_CTL0_CTRLD4_Msk              (0x1ul << EPWM_CTL0_CTRLD4_Pos)                    /*!< EPWM_T::CTL0: CTRLD4 Mask               */
+
+#define EPWM_CTL0_CTRLD5_Pos              (5)                                               /*!< EPWM_T::CTL0: CTRLD5 Position           */
+#define EPWM_CTL0_CTRLD5_Msk              (0x1ul << EPWM_CTL0_CTRLD5_Pos)                    /*!< EPWM_T::CTL0: CTRLD5 Mask               */
+
+#define EPWM_CTL0_WINLDEN0_Pos            (8)                                               /*!< EPWM_T::CTL0: WINLDEN0 Position         */
+#define EPWM_CTL0_WINLDEN0_Msk            (0x1ul << EPWM_CTL0_WINLDEN0_Pos)                  /*!< EPWM_T::CTL0: WINLDEN0 Mask             */
+
+#define EPWM_CTL0_WINLDEN1_Pos            (9)                                               /*!< EPWM_T::CTL0: WINLDEN1 Position         */
+#define EPWM_CTL0_WINLDEN1_Msk            (0x1ul << EPWM_CTL0_WINLDEN1_Pos)                  /*!< EPWM_T::CTL0: WINLDEN1 Mask             */
+
+#define EPWM_CTL0_WINLDEN2_Pos            (10)                                              /*!< EPWM_T::CTL0: WINLDEN2 Position         */
+#define EPWM_CTL0_WINLDEN2_Msk            (0x1ul << EPWM_CTL0_WINLDEN2_Pos)                  /*!< EPWM_T::CTL0: WINLDEN2 Mask             */
+
+#define EPWM_CTL0_WINLDEN3_Pos            (11)                                              /*!< EPWM_T::CTL0: WINLDEN3 Position         */
+#define EPWM_CTL0_WINLDEN3_Msk            (0x1ul << EPWM_CTL0_WINLDEN3_Pos)                  /*!< EPWM_T::CTL0: WINLDEN3 Mask             */
+
+#define EPWM_CTL0_WINLDEN4_Pos            (12)                                              /*!< EPWM_T::CTL0: WINLDEN4 Position         */
+#define EPWM_CTL0_WINLDEN4_Msk            (0x1ul << EPWM_CTL0_WINLDEN4_Pos)                  /*!< EPWM_T::CTL0: WINLDEN4 Mask             */
+
+#define EPWM_CTL0_WINLDEN5_Pos            (13)                                              /*!< EPWM_T::CTL0: WINLDEN5 Position         */
+#define EPWM_CTL0_WINLDEN5_Msk            (0x1ul << EPWM_CTL0_WINLDEN5_Pos)                  /*!< EPWM_T::CTL0: WINLDEN5 Mask             */
+
+#define EPWM_CTL0_IMMLDEN0_Pos            (16)                                              /*!< EPWM_T::CTL0: IMMLDEN0 Position         */
+#define EPWM_CTL0_IMMLDEN0_Msk            (0x1ul << EPWM_CTL0_IMMLDEN0_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN0 Mask             */
+
+#define EPWM_CTL0_IMMLDEN1_Pos            (17)                                              /*!< EPWM_T::CTL0: IMMLDEN1 Position         */
+#define EPWM_CTL0_IMMLDEN1_Msk            (0x1ul << EPWM_CTL0_IMMLDEN1_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN1 Mask             */
+
+#define EPWM_CTL0_IMMLDEN2_Pos            (18)                                              /*!< EPWM_T::CTL0: IMMLDEN2 Position         */
+#define EPWM_CTL0_IMMLDEN2_Msk            (0x1ul << EPWM_CTL0_IMMLDEN2_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN2 Mask             */
+
+#define EPWM_CTL0_IMMLDEN3_Pos            (19)                                              /*!< EPWM_T::CTL0: IMMLDEN3 Position         */
+#define EPWM_CTL0_IMMLDEN3_Msk            (0x1ul << EPWM_CTL0_IMMLDEN3_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN3 Mask             */
+
+#define EPWM_CTL0_IMMLDEN4_Pos            (20)                                              /*!< EPWM_T::CTL0: IMMLDEN4 Position         */
+#define EPWM_CTL0_IMMLDEN4_Msk            (0x1ul << EPWM_CTL0_IMMLDEN4_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN4 Mask             */
+
+#define EPWM_CTL0_IMMLDEN5_Pos            (21)                                              /*!< EPWM_T::CTL0: IMMLDEN5 Position         */
+#define EPWM_CTL0_IMMLDEN5_Msk            (0x1ul << EPWM_CTL0_IMMLDEN5_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN5 Mask             */
+
+#define EPWM_CTL0_GROUPEN_Pos             (24)                                              /*!< EPWM_T::CTL0: GROUPEN Position          */
+#define EPWM_CTL0_GROUPEN_Msk             (0x1ul << EPWM_CTL0_GROUPEN_Pos)                   /*!< EPWM_T::CTL0: GROUPEN Mask              */
+
+#define EPWM_CTL0_DBGHALT_Pos             (30)                                              /*!< EPWM_T::CTL0: DBGHALT Position          */
+#define EPWM_CTL0_DBGHALT_Msk             (0x1ul << EPWM_CTL0_DBGHALT_Pos)                   /*!< EPWM_T::CTL0: DBGHALT Mask              */
+
+#define EPWM_CTL0_DBGTRIOFF_Pos           (31)                                              /*!< EPWM_T::CTL0: DBGTRIOFF Position        */
+#define EPWM_CTL0_DBGTRIOFF_Msk           (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos)                 /*!< EPWM_T::CTL0: DBGTRIOFF Mask            */
+
+#define EPWM_CTL1_CNTTYPE0_Pos            (0)                                               /*!< EPWM_T::CTL1: CNTTYPE0 Position         */
+#define EPWM_CTL1_CNTTYPE0_Msk            (0x3ul << EPWM_CTL1_CNTTYPE0_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE0 Mask             */
+
+#define EPWM_CTL1_CNTTYPE1_Pos            (2)                                               /*!< EPWM_T::CTL1: CNTTYPE1 Position         */
+#define EPWM_CTL1_CNTTYPE1_Msk            (0x3ul << EPWM_CTL1_CNTTYPE1_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE1 Mask             */
+
+#define EPWM_CTL1_CNTTYPE2_Pos            (4)                                               /*!< EPWM_T::CTL1: CNTTYPE2 Position         */
+#define EPWM_CTL1_CNTTYPE2_Msk            (0x3ul << EPWM_CTL1_CNTTYPE2_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE2 Mask             */
+
+#define EPWM_CTL1_CNTTYPE3_Pos            (6)                                               /*!< EPWM_T::CTL1: CNTTYPE3 Position         */
+#define EPWM_CTL1_CNTTYPE3_Msk            (0x3ul << EPWM_CTL1_CNTTYPE3_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE3 Mask             */
+
+#define EPWM_CTL1_CNTTYPE4_Pos            (8)                                               /*!< EPWM_T::CTL1: CNTTYPE4 Position         */
+#define EPWM_CTL1_CNTTYPE4_Msk            (0x3ul << EPWM_CTL1_CNTTYPE4_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE4 Mask             */
+
+#define EPWM_CTL1_CNTTYPE5_Pos            (10)                                              /*!< EPWM_T::CTL1: CNTTYPE5 Position         */
+#define EPWM_CTL1_CNTTYPE5_Msk            (0x3ul << EPWM_CTL1_CNTTYPE5_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE5 Mask             */
+
+#define EPWM_CTL1_CNTMODE0_Pos            (16)                                              /*!< EPWM_T::CTL1: CNTMODE0 Position         */
+#define EPWM_CTL1_CNTMODE0_Msk            (0x1ul << EPWM_CTL1_CNTMODE0_Pos)                  /*!< EPWM_T::CTL1: CNTMODE0 Mask             */
+
+#define EPWM_CTL1_CNTMODE1_Pos            (17)                                              /*!< EPWM_T::CTL1: CNTMODE1 Position         */
+#define EPWM_CTL1_CNTMODE1_Msk            (0x1ul << EPWM_CTL1_CNTMODE1_Pos)                  /*!< EPWM_T::CTL1: CNTMODE1 Mask             */
+
+#define EPWM_CTL1_CNTMODE2_Pos            (18)                                              /*!< EPWM_T::CTL1: CNTMODE2 Position         */
+#define EPWM_CTL1_CNTMODE2_Msk            (0x1ul << EPWM_CTL1_CNTMODE2_Pos)                  /*!< EPWM_T::CTL1: CNTMODE2 Mask             */
+
+#define EPWM_CTL1_CNTMODE3_Pos            (19)                                              /*!< EPWM_T::CTL1: CNTMODE3 Position         */
+#define EPWM_CTL1_CNTMODE3_Msk            (0x1ul << EPWM_CTL1_CNTMODE3_Pos)                  /*!< EPWM_T::CTL1: CNTMODE3 Mask             */
+
+#define EPWM_CTL1_CNTMODE4_Pos            (20)                                              /*!< EPWM_T::CTL1: CNTMODE4 Position         */
+#define EPWM_CTL1_CNTMODE4_Msk            (0x1ul << EPWM_CTL1_CNTMODE4_Pos)                  /*!< EPWM_T::CTL1: CNTMODE4 Mask             */
+
+#define EPWM_CTL1_CNTMODE5_Pos            (21)                                              /*!< EPWM_T::CTL1: CNTMODE5 Position         */
+#define EPWM_CTL1_CNTMODE5_Msk            (0x1ul << EPWM_CTL1_CNTMODE5_Pos)                  /*!< EPWM_T::CTL1: CNTMODE5 Mask             */
+
+#define EPWM_CTL1_OUTMODE0_Pos            (24)                                              /*!< EPWM_T::CTL1: OUTMODE0 Position         */
+#define EPWM_CTL1_OUTMODE0_Msk            (0x1ul << EPWM_CTL1_OUTMODE0_Pos)                  /*!< EPWM_T::CTL1: OUTMODE0 Mask             */
+
+#define EPWM_CTL1_OUTMODE2_Pos            (25)                                              /*!< EPWM_T::CTL1: OUTMODE2 Position         */
+#define EPWM_CTL1_OUTMODE2_Msk            (0x1ul << EPWM_CTL1_OUTMODE2_Pos)                  /*!< EPWM_T::CTL1: OUTMODE2 Mask             */
+
+#define EPWM_CTL1_OUTMODE4_Pos            (26)                                              /*!< EPWM_T::CTL1: OUTMODE4 Position         */
+#define EPWM_CTL1_OUTMODE4_Msk            (0x1ul << EPWM_CTL1_OUTMODE4_Pos)                  /*!< EPWM_T::CTL1: OUTMODE4 Mask             */
+
+#define EPWM_SYNC_PHSEN0_Pos              (0)                                               /*!< EPWM_T::SYNC: PHSEN0 Position           */
+#define EPWM_SYNC_PHSEN0_Msk              (0x1ul << EPWM_SYNC_PHSEN0_Pos)                    /*!< EPWM_T::SYNC: PHSEN0 Mask               */
+
+#define EPWM_SYNC_PHSEN2_Pos              (1)                                               /*!< EPWM_T::SYNC: PHSEN2 Position           */
+#define EPWM_SYNC_PHSEN2_Msk              (0x1ul << EPWM_SYNC_PHSEN2_Pos)                    /*!< EPWM_T::SYNC: PHSEN2 Mask               */
+
+#define EPWM_SYNC_PHSEN4_Pos              (2)                                               /*!< EPWM_T::SYNC: PHSEN4 Position           */
+#define EPWM_SYNC_PHSEN4_Msk              (0x1ul << EPWM_SYNC_PHSEN4_Pos)                    /*!< EPWM_T::SYNC: PHSEN4 Mask               */
+
+#define EPWM_SYNC_SINSRC0_Pos             (8)                                               /*!< EPWM_T::SYNC: SINSRC0 Position          */
+#define EPWM_SYNC_SINSRC0_Msk             (0x3ul << EPWM_SYNC_SINSRC0_Pos)                   /*!< EPWM_T::SYNC: SINSRC0 Mask              */
+
+#define EPWM_SYNC_SINSRC2_Pos             (10)                                              /*!< EPWM_T::SYNC: SINSRC2 Position          */
+#define EPWM_SYNC_SINSRC2_Msk             (0x3ul << EPWM_SYNC_SINSRC2_Pos)                   /*!< EPWM_T::SYNC: SINSRC2 Mask              */
+
+#define EPWM_SYNC_SINSRC4_Pos             (12)                                              /*!< EPWM_T::SYNC: SINSRC4 Position          */
+#define EPWM_SYNC_SINSRC4_Msk             (0x3ul << EPWM_SYNC_SINSRC4_Pos)                   /*!< EPWM_T::SYNC: SINSRC4 Mask              */
+
+#define EPWM_SYNC_SNFLTEN_Pos             (16)                                              /*!< EPWM_T::SYNC: SNFLTEN Position          */
+#define EPWM_SYNC_SNFLTEN_Msk             (0x1ul << EPWM_SYNC_SNFLTEN_Pos)                   /*!< EPWM_T::SYNC: SNFLTEN Mask              */
+
+#define EPWM_SYNC_SFLTCSEL_Pos            (17)                                              /*!< EPWM_T::SYNC: SFLTCSEL Position         */
+#define EPWM_SYNC_SFLTCSEL_Msk            (0x7ul << EPWM_SYNC_SFLTCSEL_Pos)                  /*!< EPWM_T::SYNC: SFLTCSEL Mask             */
+
+#define EPWM_SYNC_SFLTCNT_Pos             (20)                                              /*!< EPWM_T::SYNC: SFLTCNT Position          */
+#define EPWM_SYNC_SFLTCNT_Msk             (0x7ul << EPWM_SYNC_SFLTCNT_Pos)                   /*!< EPWM_T::SYNC: SFLTCNT Mask              */
+
+#define EPWM_SYNC_SINPINV_Pos             (23)                                              /*!< EPWM_T::SYNC: SINPINV Position          */
+#define EPWM_SYNC_SINPINV_Msk             (0x1ul << EPWM_SYNC_SINPINV_Pos)                   /*!< EPWM_T::SYNC: SINPINV Mask              */
+
+#define EPWM_SYNC_PHSDIR0_Pos             (24)                                              /*!< EPWM_T::SYNC: PHSDIR0 Position          */
+#define EPWM_SYNC_PHSDIR0_Msk             (0x1ul << EPWM_SYNC_PHSDIR0_Pos)                   /*!< EPWM_T::SYNC: PHSDIR0 Mask              */
+
+#define EPWM_SYNC_PHSDIR2_Pos             (25)                                              /*!< EPWM_T::SYNC: PHSDIR2 Position          */
+#define EPWM_SYNC_PHSDIR2_Msk             (0x1ul << EPWM_SYNC_PHSDIR2_Pos)                   /*!< EPWM_T::SYNC: PHSDIR2 Mask              */
+
+#define EPWM_SYNC_PHSDIR4_Pos             (26)                                              /*!< EPWM_T::SYNC: PHSDIR4 Position          */
+#define EPWM_SYNC_PHSDIR4_Msk             (0x1ul << EPWM_SYNC_PHSDIR4_Pos)                   /*!< EPWM_T::SYNC: PHSDIR4 Mask              */
+
+#define EPWM_SWSYNC_SWSYNC0_Pos           (0)                                               /*!< EPWM_T::SWSYNC: SWSYNC0 Position        */
+#define EPWM_SWSYNC_SWSYNC0_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC0 Mask            */
+
+#define EPWM_SWSYNC_SWSYNC2_Pos           (1)                                               /*!< EPWM_T::SWSYNC: SWSYNC2 Position        */
+#define EPWM_SWSYNC_SWSYNC2_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC2 Mask            */
+
+#define EPWM_SWSYNC_SWSYNC4_Pos           (2)                                               /*!< EPWM_T::SWSYNC: SWSYNC4 Position        */
+#define EPWM_SWSYNC_SWSYNC4_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC4 Mask            */
+
+#define EPWM_CLKSRC_ECLKSRC0_Pos          (0)                                               /*!< EPWM_T::CLKSRC: ECLKSRC0 Position       */
+#define EPWM_CLKSRC_ECLKSRC0_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask           */
+
+#define EPWM_CLKSRC_ECLKSRC2_Pos          (8)                                               /*!< EPWM_T::CLKSRC: ECLKSRC2 Position       */
+#define EPWM_CLKSRC_ECLKSRC2_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask           */
+
+#define EPWM_CLKSRC_ECLKSRC4_Pos          (16)                                              /*!< EPWM_T::CLKSRC: ECLKSRC4 Position       */
+#define EPWM_CLKSRC_ECLKSRC4_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask           */
+
+#define EPWM_CLKPSC0_1_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC0_1: CLKPSC Position      */
+#define EPWM_CLKPSC0_1_CLKPSC_Msk         (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask          */
+
+#define EPWM_CLKPSC2_3_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC2_3: CLKPSC Position      */
+#define EPWM_CLKPSC2_3_CLKPSC_Msk         (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask          */
+
+#define EPWM_CLKPSC4_5_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC4_5: CLKPSC Position      */
+#define EPWM_CLKPSC4_5_CLKPSC_Msk         (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask          */
+
+#define EPWM_CNTEN_CNTEN0_Pos             (0)                                               /*!< EPWM_T::CNTEN: CNTEN0 Position          */
+#define EPWM_CNTEN_CNTEN0_Msk             (0x1ul << EPWM_CNTEN_CNTEN0_Pos)                   /*!< EPWM_T::CNTEN: CNTEN0 Mask              */
+
+#define EPWM_CNTEN_CNTEN1_Pos             (1)                                               /*!< EPWM_T::CNTEN: CNTEN1 Position          */
+#define EPWM_CNTEN_CNTEN1_Msk             (0x1ul << EPWM_CNTEN_CNTEN1_Pos)                   /*!< EPWM_T::CNTEN: CNTEN1 Mask              */
+
+#define EPWM_CNTEN_CNTEN2_Pos             (2)                                               /*!< EPWM_T::CNTEN: CNTEN2 Position          */
+#define EPWM_CNTEN_CNTEN2_Msk             (0x1ul << EPWM_CNTEN_CNTEN2_Pos)                   /*!< EPWM_T::CNTEN: CNTEN2 Mask              */
+
+#define EPWM_CNTEN_CNTEN3_Pos             (3)                                               /*!< EPWM_T::CNTEN: CNTEN3 Position          */
+#define EPWM_CNTEN_CNTEN3_Msk             (0x1ul << EPWM_CNTEN_CNTEN3_Pos)                   /*!< EPWM_T::CNTEN: CNTEN3 Mask              */
+
+#define EPWM_CNTEN_CNTEN4_Pos             (4)                                               /*!< EPWM_T::CNTEN: CNTEN4 Position          */
+#define EPWM_CNTEN_CNTEN4_Msk             (0x1ul << EPWM_CNTEN_CNTEN4_Pos)                   /*!< EPWM_T::CNTEN: CNTEN4 Mask              */
+
+#define EPWM_CNTEN_CNTEN5_Pos             (5)                                               /*!< EPWM_T::CNTEN: CNTEN5 Position          */
+#define EPWM_CNTEN_CNTEN5_Msk             (0x1ul << EPWM_CNTEN_CNTEN5_Pos)                   /*!< EPWM_T::CNTEN: CNTEN5 Mask              */
+
+#define EPWM_CNTCLR_CNTCLR0_Pos           (0)                                               /*!< EPWM_T::CNTCLR: CNTCLR0 Position        */
+#define EPWM_CNTCLR_CNTCLR0_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR0 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR1_Pos           (1)                                               /*!< EPWM_T::CNTCLR: CNTCLR1 Position        */
+#define EPWM_CNTCLR_CNTCLR1_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR1 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR2_Pos           (2)                                               /*!< EPWM_T::CNTCLR: CNTCLR2 Position        */
+#define EPWM_CNTCLR_CNTCLR2_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR2 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR3_Pos           (3)                                               /*!< EPWM_T::CNTCLR: CNTCLR3 Position        */
+#define EPWM_CNTCLR_CNTCLR3_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR3 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR4_Pos           (4)                                               /*!< EPWM_T::CNTCLR: CNTCLR4 Position        */
+#define EPWM_CNTCLR_CNTCLR4_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR4 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR5_Pos           (5)                                               /*!< EPWM_T::CNTCLR: CNTCLR5 Position        */
+#define EPWM_CNTCLR_CNTCLR5_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR5 Mask            */
+
+#define EPWM_LOAD_LOAD0_Pos               (0)                                               /*!< EPWM_T::LOAD: LOAD0 Position            */
+#define EPWM_LOAD_LOAD0_Msk               (0x1ul << EPWM_LOAD_LOAD0_Pos)                     /*!< EPWM_T::LOAD: LOAD0 Mask                */
+
+#define EPWM_LOAD_LOAD1_Pos               (1)                                               /*!< EPWM_T::LOAD: LOAD1 Position            */
+#define EPWM_LOAD_LOAD1_Msk               (0x1ul << EPWM_LOAD_LOAD1_Pos)                     /*!< EPWM_T::LOAD: LOAD1 Mask                */
+
+#define EPWM_LOAD_LOAD2_Pos               (2)                                               /*!< EPWM_T::LOAD: LOAD2 Position            */
+#define EPWM_LOAD_LOAD2_Msk               (0x1ul << EPWM_LOAD_LOAD2_Pos)                     /*!< EPWM_T::LOAD: LOAD2 Mask                */
+
+#define EPWM_LOAD_LOAD3_Pos               (3)                                               /*!< EPWM_T::LOAD: LOAD3 Position            */
+#define EPWM_LOAD_LOAD3_Msk               (0x1ul << EPWM_LOAD_LOAD3_Pos)                     /*!< EPWM_T::LOAD: LOAD3 Mask                */
+
+#define EPWM_LOAD_LOAD4_Pos               (4)                                               /*!< EPWM_T::LOAD: LOAD4 Position            */
+#define EPWM_LOAD_LOAD4_Msk               (0x1ul << EPWM_LOAD_LOAD4_Pos)                     /*!< EPWM_T::LOAD: LOAD4 Mask                */
+
+#define EPWM_LOAD_LOAD5_Pos               (5)                                               /*!< EPWM_T::LOAD: LOAD5 Position            */
+#define EPWM_LOAD_LOAD5_Msk               (0x1ul << EPWM_LOAD_LOAD5_Pos)                     /*!< EPWM_T::LOAD: LOAD5 Mask                */
+
+#define EPWM_PERIOD0_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD0: PERIOD Position        */
+#define EPWM_PERIOD0_PERIOD_Msk           (0xfffful << EPWM_PERIOD0_PERIOD_Pos)              /*!< EPWM_T::PERIOD0: PERIOD Mask            */
+
+#define EPWM_PERIOD1_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD1: PERIOD Position        */
+#define EPWM_PERIOD1_PERIOD_Msk           (0xfffful << EPWM_PERIOD1_PERIOD_Pos)              /*!< EPWM_T::PERIOD1: PERIOD Mask            */
+
+#define EPWM_PERIOD2_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD2: PERIOD Position        */
+#define EPWM_PERIOD2_PERIOD_Msk           (0xfffful << EPWM_PERIOD2_PERIOD_Pos)              /*!< EPWM_T::PERIOD2: PERIOD Mask            */
+
+#define EPWM_PERIOD3_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD3: PERIOD Position        */
+#define EPWM_PERIOD3_PERIOD_Msk           (0xfffful << EPWM_PERIOD3_PERIOD_Pos)              /*!< EPWM_T::PERIOD3: PERIOD Mask            */
+
+#define EPWM_PERIOD4_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD4: PERIOD Position        */
+#define EPWM_PERIOD4_PERIOD_Msk           (0xfffful << EPWM_PERIOD4_PERIOD_Pos)              /*!< EPWM_T::PERIOD4: PERIOD Mask            */
+
+#define EPWM_PERIOD5_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD5: PERIOD Position        */
+#define EPWM_PERIOD5_PERIOD_Msk           (0xfffful << EPWM_PERIOD5_PERIOD_Pos)              /*!< EPWM_T::PERIOD5: PERIOD Mask            */
+
+#define EPWM_CMPDAT0_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT0: CMP Position           */
+#define EPWM_CMPDAT0_CMP_Msk              (0xfffful << EPWM_CMPDAT0_CMP_Pos)                 /*!< EPWM_T::CMPDAT0: CMP Mask               */
+
+#define EPWM_CMPDAT1_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT1: CMP Position           */
+#define EPWM_CMPDAT1_CMP_Msk              (0xfffful << EPWM_CMPDAT1_CMP_Pos)                 /*!< EPWM_T::CMPDAT1: CMP Mask               */
+
+#define EPWM_CMPDAT2_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT2: CMP Position           */
+#define EPWM_CMPDAT2_CMP_Msk              (0xfffful << EPWM_CMPDAT2_CMP_Pos)                 /*!< EPWM_T::CMPDAT2: CMP Mask               */
+
+#define EPWM_CMPDAT3_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT3: CMP Position           */
+#define EPWM_CMPDAT3_CMP_Msk              (0xfffful << EPWM_CMPDAT3_CMP_Pos)                 /*!< EPWM_T::CMPDAT3: CMP Mask               */
+
+#define EPWM_CMPDAT4_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT4: CMP Position           */
+#define EPWM_CMPDAT4_CMP_Msk              (0xfffful << EPWM_CMPDAT4_CMP_Pos)                 /*!< EPWM_T::CMPDAT4: CMP Mask               */
+
+#define EPWM_CMPDAT5_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT5: CMP Position           */
+#define EPWM_CMPDAT5_CMP_Msk              (0xfffful << EPWM_CMPDAT5_CMP_Pos)                 /*!< EPWM_T::CMPDAT5: CMP Mask               */
+
+#define EPWM_DTCTL0_1_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL0_1: DTCNT Position        */
+#define EPWM_DTCTL0_1_DTCNT_Msk           (0xffful << EPWM_DTCTL0_1_DTCNT_Pos)               /*!< EPWM_T::DTCTL0_1: DTCNT Mask            */
+
+#define EPWM_DTCTL0_1_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL0_1: DTEN Position         */
+#define EPWM_DTCTL0_1_DTEN_Msk            (0x1ul << EPWM_DTCTL0_1_DTEN_Pos)                  /*!< EPWM_T::DTCTL0_1: DTEN Mask             */
+
+#define EPWM_DTCTL0_1_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL0_1: DTCKSEL Position      */
+#define EPWM_DTCTL0_1_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask          */
+
+#define EPWM_DTCTL2_3_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL2_3: DTCNT Position        */
+#define EPWM_DTCTL2_3_DTCNT_Msk           (0xffful << EPWM_DTCTL2_3_DTCNT_Pos)               /*!< EPWM_T::DTCTL2_3: DTCNT Mask            */
+
+#define EPWM_DTCTL2_3_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL2_3: DTEN Position         */
+#define EPWM_DTCTL2_3_DTEN_Msk            (0x1ul << EPWM_DTCTL2_3_DTEN_Pos)                  /*!< EPWM_T::DTCTL2_3: DTEN Mask             */
+
+#define EPWM_DTCTL2_3_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL2_3: DTCKSEL Position      */
+#define EPWM_DTCTL2_3_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask          */
+
+#define EPWM_DTCTL4_5_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL4_5: DTCNT Position        */
+#define EPWM_DTCTL4_5_DTCNT_Msk           (0xffful << EPWM_DTCTL4_5_DTCNT_Pos)               /*!< EPWM_T::DTCTL4_5: DTCNT Mask            */
+
+#define EPWM_DTCTL4_5_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL4_5: DTEN Position         */
+#define EPWM_DTCTL4_5_DTEN_Msk            (0x1ul << EPWM_DTCTL4_5_DTEN_Pos)                  /*!< EPWM_T::DTCTL4_5: DTEN Mask             */
+
+#define EPWM_DTCTL4_5_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL4_5: DTCKSEL Position      */
+#define EPWM_DTCTL4_5_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask          */
+
+#define EPWM_PHS0_1_PHS_Pos               (0)                                               /*!< EPWM_T::PHS0_1: PHS Position            */
+#define EPWM_PHS0_1_PHS_Msk               (0xfffful << EPWM_PHS0_1_PHS_Pos)                  /*!< EPWM_T::PHS0_1: PHS Mask                */
+
+#define EPWM_PHS2_3_PHS_Pos               (0)                                               /*!< EPWM_T::PHS2_3: PHS Position            */
+#define EPWM_PHS2_3_PHS_Msk               (0xfffful << EPWM_PHS2_3_PHS_Pos)                  /*!< EPWM_T::PHS2_3: PHS Mask                */
+
+#define EPWM_PHS4_5_PHS_Pos               (0)                                               /*!< EPWM_T::PHS4_5: PHS Position            */
+#define EPWM_PHS4_5_PHS_Msk               (0xfffful << EPWM_PHS4_5_PHS_Pos)                  /*!< EPWM_T::PHS4_5: PHS Mask                */
+
+#define EPWM_CNT0_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT0: CNT Position              */
+#define EPWM_CNT0_CNT_Msk                 (0xfffful << EPWM_CNT0_CNT_Pos)                    /*!< EPWM_T::CNT0: CNT Mask                  */
+
+#define EPWM_CNT0_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT0: DIRF Position             */
+#define EPWM_CNT0_DIRF_Msk                (0x1ul << EPWM_CNT0_DIRF_Pos)                      /*!< EPWM_T::CNT0: DIRF Mask                 */
+
+#define EPWM_CNT1_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT1: CNT Position              */
+#define EPWM_CNT1_CNT_Msk                 (0xfffful << EPWM_CNT1_CNT_Pos)                    /*!< EPWM_T::CNT1: CNT Mask                  */
+
+#define EPWM_CNT1_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT1: DIRF Position             */
+#define EPWM_CNT1_DIRF_Msk                (0x1ul << EPWM_CNT1_DIRF_Pos)                      /*!< EPWM_T::CNT1: DIRF Mask                 */
+
+#define EPWM_CNT2_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT2: CNT Position              */
+#define EPWM_CNT2_CNT_Msk                 (0xfffful << EPWM_CNT2_CNT_Pos)                    /*!< EPWM_T::CNT2: CNT Mask                  */
+
+#define EPWM_CNT2_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT2: DIRF Position             */
+#define EPWM_CNT2_DIRF_Msk                (0x1ul << EPWM_CNT2_DIRF_Pos)                      /*!< EPWM_T::CNT2: DIRF Mask                 */
+
+#define EPWM_CNT3_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT3: CNT Position              */
+#define EPWM_CNT3_CNT_Msk                 (0xfffful << EPWM_CNT3_CNT_Pos)                    /*!< EPWM_T::CNT3: CNT Mask                  */
+
+#define EPWM_CNT3_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT3: DIRF Position             */
+#define EPWM_CNT3_DIRF_Msk                (0x1ul << EPWM_CNT3_DIRF_Pos)                      /*!< EPWM_T::CNT3: DIRF Mask                 */
+
+#define EPWM_CNT4_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT4: CNT Position              */
+#define EPWM_CNT4_CNT_Msk                 (0xfffful << EPWM_CNT4_CNT_Pos)                    /*!< EPWM_T::CNT4: CNT Mask                  */
+
+#define EPWM_CNT4_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT4: DIRF Position             */
+#define EPWM_CNT4_DIRF_Msk                (0x1ul << EPWM_CNT4_DIRF_Pos)                      /*!< EPWM_T::CNT4: DIRF Mask                 */
+
+#define EPWM_CNT5_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT5: CNT Position              */
+#define EPWM_CNT5_CNT_Msk                 (0xfffful << EPWM_CNT5_CNT_Pos)                    /*!< EPWM_T::CNT5: CNT Mask                  */
+
+#define EPWM_CNT5_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT5: DIRF Position             */
+#define EPWM_CNT5_DIRF_Msk                (0x1ul << EPWM_CNT5_DIRF_Pos)                      /*!< EPWM_T::CNT5: DIRF Mask                 */
+
+#define EPWM_WGCTL0_ZPCTL0_Pos            (0)                                               /*!< EPWM_T::WGCTL0: ZPCTL0 Position         */
+#define EPWM_WGCTL0_ZPCTL0_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL0 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL1_Pos            (2)                                               /*!< EPWM_T::WGCTL0: ZPCTL1 Position         */
+#define EPWM_WGCTL0_ZPCTL1_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL1 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL2_Pos            (4)                                               /*!< EPWM_T::WGCTL0: ZPCTL2 Position         */
+#define EPWM_WGCTL0_ZPCTL2_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL2 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL3_Pos            (6)                                               /*!< EPWM_T::WGCTL0: ZPCTL3 Position         */
+#define EPWM_WGCTL0_ZPCTL3_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL3 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL4_Pos            (8)                                               /*!< EPWM_T::WGCTL0: ZPCTL4 Position         */
+#define EPWM_WGCTL0_ZPCTL4_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL4 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL5_Pos            (10)                                              /*!< EPWM_T::WGCTL0: ZPCTL5 Position         */
+#define EPWM_WGCTL0_ZPCTL5_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL5 Mask             */
+
+#define EPWM_WGCTL0_PRDPCTL0_Pos          (16)                                              /*!< EPWM_T::WGCTL0: PRDPCTL0 Position       */
+#define EPWM_WGCTL0_PRDPCTL0_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL1_Pos          (18)                                              /*!< EPWM_T::WGCTL0: PRDPCTL1 Position       */
+#define EPWM_WGCTL0_PRDPCTL1_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL2_Pos          (20)                                              /*!< EPWM_T::WGCTL0: PRDPCTL2 Position       */
+#define EPWM_WGCTL0_PRDPCTL2_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL3_Pos          (22)                                              /*!< EPWM_T::WGCTL0: PRDPCTL3 Position       */
+#define EPWM_WGCTL0_PRDPCTL3_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL4_Pos          (24)                                              /*!< EPWM_T::WGCTL0: PRDPCTL4 Position       */
+#define EPWM_WGCTL0_PRDPCTL4_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL5_Pos          (26)                                              /*!< EPWM_T::WGCTL0: PRDPCTL5 Position       */
+#define EPWM_WGCTL0_PRDPCTL5_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL0_Pos          (0)                                               /*!< EPWM_T::WGCTL1: CMPUCTL0 Position       */
+#define EPWM_WGCTL1_CMPUCTL0_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL1_Pos          (2)                                               /*!< EPWM_T::WGCTL1: CMPUCTL1 Position       */
+#define EPWM_WGCTL1_CMPUCTL1_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL2_Pos          (4)                                               /*!< EPWM_T::WGCTL1: CMPUCTL2 Position       */
+#define EPWM_WGCTL1_CMPUCTL2_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL3_Pos          (6)                                               /*!< EPWM_T::WGCTL1: CMPUCTL3 Position       */
+#define EPWM_WGCTL1_CMPUCTL3_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL4_Pos          (8)                                               /*!< EPWM_T::WGCTL1: CMPUCTL4 Position       */
+#define EPWM_WGCTL1_CMPUCTL4_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL5_Pos          (10)                                              /*!< EPWM_T::WGCTL1: CMPUCTL5 Position       */
+#define EPWM_WGCTL1_CMPUCTL5_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL0_Pos          (16)                                              /*!< EPWM_T::WGCTL1: CMPDCTL0 Position       */
+#define EPWM_WGCTL1_CMPDCTL0_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL1_Pos          (18)                                              /*!< EPWM_T::WGCTL1: CMPDCTL1 Position       */
+#define EPWM_WGCTL1_CMPDCTL1_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL2_Pos          (20)                                              /*!< EPWM_T::WGCTL1: CMPDCTL2 Position       */
+#define EPWM_WGCTL1_CMPDCTL2_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL3_Pos          (22)                                              /*!< EPWM_T::WGCTL1: CMPDCTL3 Position       */
+#define EPWM_WGCTL1_CMPDCTL3_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL4_Pos          (24)                                              /*!< EPWM_T::WGCTL1: CMPDCTL4 Position       */
+#define EPWM_WGCTL1_CMPDCTL4_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL5_Pos          (26)                                              /*!< EPWM_T::WGCTL1: CMPDCTL5 Position       */
+#define EPWM_WGCTL1_CMPDCTL5_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask           */
+
+#define EPWM_MSKEN_MSKEN0_Pos             (0)                                               /*!< EPWM_T::MSKEN: MSKEN0 Position          */
+#define EPWM_MSKEN_MSKEN0_Msk             (0x1ul << EPWM_MSKEN_MSKEN0_Pos)                   /*!< EPWM_T::MSKEN: MSKEN0 Mask              */
+
+#define EPWM_MSKEN_MSKEN1_Pos             (1)                                               /*!< EPWM_T::MSKEN: MSKEN1 Position          */
+#define EPWM_MSKEN_MSKEN1_Msk             (0x1ul << EPWM_MSKEN_MSKEN1_Pos)                   /*!< EPWM_T::MSKEN: MSKEN1 Mask              */
+
+#define EPWM_MSKEN_MSKEN2_Pos             (2)                                               /*!< EPWM_T::MSKEN: MSKEN2 Position          */
+#define EPWM_MSKEN_MSKEN2_Msk             (0x1ul << EPWM_MSKEN_MSKEN2_Pos)                   /*!< EPWM_T::MSKEN: MSKEN2 Mask              */
+
+#define EPWM_MSKEN_MSKEN3_Pos             (3)                                               /*!< EPWM_T::MSKEN: MSKEN3 Position          */
+#define EPWM_MSKEN_MSKEN3_Msk             (0x1ul << EPWM_MSKEN_MSKEN3_Pos)                   /*!< EPWM_T::MSKEN: MSKEN3 Mask              */
+
+#define EPWM_MSKEN_MSKEN4_Pos             (4)                                               /*!< EPWM_T::MSKEN: MSKEN4 Position          */
+#define EPWM_MSKEN_MSKEN4_Msk             (0x1ul << EPWM_MSKEN_MSKEN4_Pos)                   /*!< EPWM_T::MSKEN: MSKEN4 Mask              */
+
+#define EPWM_MSKEN_MSKEN5_Pos             (5)                                               /*!< EPWM_T::MSKEN: MSKEN5 Position          */
+#define EPWM_MSKEN_MSKEN5_Msk             (0x1ul << EPWM_MSKEN_MSKEN5_Pos)                   /*!< EPWM_T::MSKEN: MSKEN5 Mask              */
+
+#define EPWM_MSK_MSKDAT0_Pos              (0)                                               /*!< EPWM_T::MSK: MSKDAT0 Position           */
+#define EPWM_MSK_MSKDAT0_Msk              (0x1ul << EPWM_MSK_MSKDAT0_Pos)                    /*!< EPWM_T::MSK: MSKDAT0 Mask               */
+
+#define EPWM_MSK_MSKDAT1_Pos              (1)                                               /*!< EPWM_T::MSK: MSKDAT1 Position           */
+#define EPWM_MSK_MSKDAT1_Msk              (0x1ul << EPWM_MSK_MSKDAT1_Pos)                    /*!< EPWM_T::MSK: MSKDAT1 Mask               */
+
+#define EPWM_MSK_MSKDAT2_Pos              (2)                                               /*!< EPWM_T::MSK: MSKDAT2 Position           */
+#define EPWM_MSK_MSKDAT2_Msk              (0x1ul << EPWM_MSK_MSKDAT2_Pos)                    /*!< EPWM_T::MSK: MSKDAT2 Mask               */
+
+#define EPWM_MSK_MSKDAT3_Pos              (3)                                               /*!< EPWM_T::MSK: MSKDAT3 Position           */
+#define EPWM_MSK_MSKDAT3_Msk              (0x1ul << EPWM_MSK_MSKDAT3_Pos)                    /*!< EPWM_T::MSK: MSKDAT3 Mask               */
+
+#define EPWM_MSK_MSKDAT4_Pos              (4)                                               /*!< EPWM_T::MSK: MSKDAT4 Position           */
+#define EPWM_MSK_MSKDAT4_Msk              (0x1ul << EPWM_MSK_MSKDAT4_Pos)                    /*!< EPWM_T::MSK: MSKDAT4 Mask               */
+
+#define EPWM_MSK_MSKDAT5_Pos              (5)                                               /*!< EPWM_T::MSK: MSKDAT5 Position           */
+#define EPWM_MSK_MSKDAT5_Msk              (0x1ul << EPWM_MSK_MSKDAT5_Pos)                    /*!< EPWM_T::MSK: MSKDAT5 Mask               */
+
+#define EPWM_BNF_BRK0NFEN_Pos             (0)                                               /*!< EPWM_T::BNF: BRK0NFEN Position          */
+#define EPWM_BNF_BRK0NFEN_Msk             (0x1ul << EPWM_BNF_BRK0NFEN_Pos)                   /*!< EPWM_T::BNF: BRK0NFEN Mask              */
+
+#define EPWM_BNF_BRK0NFSEL_Pos            (1)                                               /*!< EPWM_T::BNF: BRK0NFSEL Position         */
+#define EPWM_BNF_BRK0NFSEL_Msk            (0x7ul << EPWM_BNF_BRK0NFSEL_Pos)                  /*!< EPWM_T::BNF: BRK0NFSEL Mask             */
+
+#define EPWM_BNF_BRK0FCNT_Pos             (4)                                               /*!< EPWM_T::BNF: BRK0FCNT Position          */
+#define EPWM_BNF_BRK0FCNT_Msk             (0x7ul << EPWM_BNF_BRK0FCNT_Pos)                   /*!< EPWM_T::BNF: BRK0FCNT Mask              */
+
+#define EPWM_BNF_BRK0PINV_Pos             (7)                                               /*!< EPWM_T::BNF: BRK0PINV Position          */
+#define EPWM_BNF_BRK0PINV_Msk             (0x1ul << EPWM_BNF_BRK0PINV_Pos)                   /*!< EPWM_T::BNF: BRK0PINV Mask              */
+
+#define EPWM_BNF_BRK1NFEN_Pos             (8)                                               /*!< EPWM_T::BNF: BRK1NFEN Position          */
+#define EPWM_BNF_BRK1NFEN_Msk             (0x1ul << EPWM_BNF_BRK1NFEN_Pos)                   /*!< EPWM_T::BNF: BRK1NFEN Mask              */
+
+#define EPWM_BNF_BRK1NFSEL_Pos            (9)                                               /*!< EPWM_T::BNF: BRK1NFSEL Position         */
+#define EPWM_BNF_BRK1NFSEL_Msk            (0x7ul << EPWM_BNF_BRK1NFSEL_Pos)                  /*!< EPWM_T::BNF: BRK1NFSEL Mask             */
+
+#define EPWM_BNF_BRK1FCNT_Pos             (12)                                              /*!< EPWM_T::BNF: BRK1FCNT Position          */
+#define EPWM_BNF_BRK1FCNT_Msk             (0x7ul << EPWM_BNF_BRK1FCNT_Pos)                   /*!< EPWM_T::BNF: BRK1FCNT Mask              */
+
+#define EPWM_BNF_BRK1PINV_Pos             (15)                                              /*!< EPWM_T::BNF: BRK1PINV Position          */
+#define EPWM_BNF_BRK1PINV_Msk             (0x1ul << EPWM_BNF_BRK1PINV_Pos)                   /*!< EPWM_T::BNF: BRK1PINV Mask              */
+
+#define EPWM_BNF_BK0SRC_Pos               (16)                                              /*!< EPWM_T::BNF: BK0SRC Position            */
+#define EPWM_BNF_BK0SRC_Msk               (0x1ul << EPWM_BNF_BK0SRC_Pos)                     /*!< EPWM_T::BNF: BK0SRC Mask                */
+
+#define EPWM_BNF_BK1SRC_Pos               (24)                                              /*!< EPWM_T::BNF: BK1SRC Position            */
+#define EPWM_BNF_BK1SRC_Msk               (0x1ul << EPWM_BNF_BK1SRC_Pos)                     /*!< EPWM_T::BNF: BK1SRC Mask                */
+
+#define EPWM_FAILBRK_CSSBRKEN_Pos         (0)                                               /*!< EPWM_T::FAILBRK: CSSBRKEN Position      */
+#define EPWM_FAILBRK_CSSBRKEN_Msk         (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos)               /*!< EPWM_T::FAILBRK: CSSBRKEN Mask          */
+
+#define EPWM_FAILBRK_BODBRKEN_Pos         (1)                                               /*!< EPWM_T::FAILBRK: BODBRKEN Position      */
+#define EPWM_FAILBRK_BODBRKEN_Msk         (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos)               /*!< EPWM_T::FAILBRK: BODBRKEN Mask          */
+
+#define EPWM_FAILBRK_RAMBRKEN_Pos         (2)                                               /*!< EPWM_T::FAILBRK: RAMBRKEN Position      */
+#define EPWM_FAILBRK_RAMBRKEN_Msk         (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos)               /*!< EPWM_T::FAILBRK: RAMBRKEN Mask          */
+
+#define EPWM_FAILBRK_CORBRKEN_Pos         (3)                                               /*!< EPWM_T::FAILBRK: CORBRKEN Position      */
+#define EPWM_FAILBRK_CORBRKEN_Msk         (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos)               /*!< EPWM_T::FAILBRK: CORBRKEN Mask          */
+
+#define EPWM_BRKCTL0_1_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position    */
+#define EPWM_BRKCTL0_1_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL0_1_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position    */
+#define EPWM_BRKCTL0_1_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position    */
+#define EPWM_BRKCTL0_1_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position    */
+#define EPWM_BRKCTL0_1_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL0_1_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position     */
+#define EPWM_BRKCTL0_1_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL0_1_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position    */
+#define EPWM_BRKCTL0_1_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL0_1_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position    */
+#define EPWM_BRKCTL0_1_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position    */
+#define EPWM_BRKCTL0_1_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position    */
+#define EPWM_BRKCTL0_1_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL0_1_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position     */
+#define EPWM_BRKCTL0_1_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL0_1_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position    */
+#define EPWM_BRKCTL0_1_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL0_1: BRKAODD Position     */
+#define EPWM_BRKCTL0_1_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask         */
+
+#define EPWM_BRKCTL0_1_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position    */
+#define EPWM_BRKCTL0_1_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL0_1_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position    */
+#define EPWM_BRKCTL0_1_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position    */
+#define EPWM_BRKCTL2_3_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position    */
+#define EPWM_BRKCTL2_3_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position    */
+#define EPWM_BRKCTL2_3_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position    */
+#define EPWM_BRKCTL2_3_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL2_3_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position     */
+#define EPWM_BRKCTL2_3_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL2_3_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position    */
+#define EPWM_BRKCTL2_3_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position    */
+#define EPWM_BRKCTL2_3_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position    */
+#define EPWM_BRKCTL2_3_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position    */
+#define EPWM_BRKCTL2_3_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL2_3_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position     */
+#define EPWM_BRKCTL2_3_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL2_3_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position    */
+#define EPWM_BRKCTL2_3_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL2_3: BRKAODD Position     */
+#define EPWM_BRKCTL2_3_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask         */
+
+#define EPWM_BRKCTL2_3_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position    */
+#define EPWM_BRKCTL2_3_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL2_3_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position    */
+#define EPWM_BRKCTL2_3_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position    */
+#define EPWM_BRKCTL4_5_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position    */
+#define EPWM_BRKCTL4_5_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position    */
+#define EPWM_BRKCTL4_5_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position    */
+#define EPWM_BRKCTL4_5_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL4_5_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position     */
+#define EPWM_BRKCTL4_5_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL4_5_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position    */
+#define EPWM_BRKCTL4_5_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position    */
+#define EPWM_BRKCTL4_5_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position    */
+#define EPWM_BRKCTL4_5_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position    */
+#define EPWM_BRKCTL4_5_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL4_5_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position     */
+#define EPWM_BRKCTL4_5_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL4_5_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position    */
+#define EPWM_BRKCTL4_5_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL4_5: BRKAODD Position     */
+#define EPWM_BRKCTL4_5_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask         */
+
+#define EPWM_BRKCTL4_5_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position    */
+#define EPWM_BRKCTL4_5_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL4_5_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position    */
+#define EPWM_BRKCTL4_5_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask        */
+
+#define EPWM_POLCTL_PINV0_Pos             (0)                                               /*!< EPWM_T::POLCTL: PINV0 Position          */
+#define EPWM_POLCTL_PINV0_Msk             (0x1ul << EPWM_POLCTL_PINV0_Pos)                   /*!< EPWM_T::POLCTL: PINV0 Mask              */
+
+#define EPWM_POLCTL_PINV1_Pos             (1)                                               /*!< EPWM_T::POLCTL: PINV1 Position          */
+#define EPWM_POLCTL_PINV1_Msk             (0x1ul << EPWM_POLCTL_PINV1_Pos)                   /*!< EPWM_T::POLCTL: PINV1 Mask              */
+
+#define EPWM_POLCTL_PINV2_Pos             (2)                                               /*!< EPWM_T::POLCTL: PINV2 Position          */
+#define EPWM_POLCTL_PINV2_Msk             (0x1ul << EPWM_POLCTL_PINV2_Pos)                   /*!< EPWM_T::POLCTL: PINV2 Mask              */
+
+#define EPWM_POLCTL_PINV3_Pos             (3)                                               /*!< EPWM_T::POLCTL: PINV3 Position          */
+#define EPWM_POLCTL_PINV3_Msk             (0x1ul << EPWM_POLCTL_PINV3_Pos)                   /*!< EPWM_T::POLCTL: PINV3 Mask              */
+
+#define EPWM_POLCTL_PINV4_Pos             (4)                                               /*!< EPWM_T::POLCTL: PINV4 Position          */
+#define EPWM_POLCTL_PINV4_Msk             (0x1ul << EPWM_POLCTL_PINV4_Pos)                   /*!< EPWM_T::POLCTL: PINV4 Mask              */
+
+#define EPWM_POLCTL_PINV5_Pos             (5)                                               /*!< EPWM_T::POLCTL: PINV5 Position          */
+#define EPWM_POLCTL_PINV5_Msk             (0x1ul << EPWM_POLCTL_PINV5_Pos)                   /*!< EPWM_T::POLCTL: PINV5 Mask              */
+
+#define EPWM_POEN_POEN0_Pos               (0)                                               /*!< EPWM_T::POEN: POEN0 Position            */
+#define EPWM_POEN_POEN0_Msk               (0x1ul << EPWM_POEN_POEN0_Pos)                     /*!< EPWM_T::POEN: POEN0 Mask                */
+
+#define EPWM_POEN_POEN1_Pos               (1)                                               /*!< EPWM_T::POEN: POEN1 Position            */
+#define EPWM_POEN_POEN1_Msk               (0x1ul << EPWM_POEN_POEN1_Pos)                     /*!< EPWM_T::POEN: POEN1 Mask                */
+
+#define EPWM_POEN_POEN2_Pos               (2)                                               /*!< EPWM_T::POEN: POEN2 Position            */
+#define EPWM_POEN_POEN2_Msk               (0x1ul << EPWM_POEN_POEN2_Pos)                     /*!< EPWM_T::POEN: POEN2 Mask                */
+
+#define EPWM_POEN_POEN3_Pos               (3)                                               /*!< EPWM_T::POEN: POEN3 Position            */
+#define EPWM_POEN_POEN3_Msk               (0x1ul << EPWM_POEN_POEN3_Pos)                     /*!< EPWM_T::POEN: POEN3 Mask                */
+
+#define EPWM_POEN_POEN4_Pos               (4)                                               /*!< EPWM_T::POEN: POEN4 Position            */
+#define EPWM_POEN_POEN4_Msk               (0x1ul << EPWM_POEN_POEN4_Pos)                     /*!< EPWM_T::POEN: POEN4 Mask                */
+
+#define EPWM_POEN_POEN5_Pos               (5)                                               /*!< EPWM_T::POEN: POEN5 Position            */
+#define EPWM_POEN_POEN5_Msk               (0x1ul << EPWM_POEN_POEN5_Pos)                     /*!< EPWM_T::POEN: POEN5 Mask                */
+
+#define EPWM_SWBRK_BRKETRG0_Pos           (0)                                               /*!< EPWM_T::SWBRK: BRKETRG0 Position        */
+#define EPWM_SWBRK_BRKETRG0_Msk           (0x1ul << EPWM_SWBRK_BRKETRG0_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG0 Mask            */
+
+#define EPWM_SWBRK_BRKETRG2_Pos           (1)                                               /*!< EPWM_T::SWBRK: BRKETRG2 Position        */
+#define EPWM_SWBRK_BRKETRG2_Msk           (0x1ul << EPWM_SWBRK_BRKETRG2_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG2 Mask            */
+
+#define EPWM_SWBRK_BRKETRG4_Pos           (2)                                               /*!< EPWM_T::SWBRK: BRKETRG4 Position        */
+#define EPWM_SWBRK_BRKETRG4_Msk           (0x1ul << EPWM_SWBRK_BRKETRG4_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG4 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG0_Pos           (8)                                               /*!< EPWM_T::SWBRK: BRKLTRG0 Position        */
+#define EPWM_SWBRK_BRKLTRG0_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG0 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG2_Pos           (9)                                               /*!< EPWM_T::SWBRK: BRKLTRG2 Position        */
+#define EPWM_SWBRK_BRKLTRG2_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG2 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG4_Pos           (10)                                              /*!< EPWM_T::SWBRK: BRKLTRG4 Position        */
+#define EPWM_SWBRK_BRKLTRG4_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG4 Mask            */
+
+#define EPWM_INTEN0_ZIEN0_Pos             (0)                                               /*!< EPWM_T::INTEN0: ZIEN0 Position          */
+#define EPWM_INTEN0_ZIEN0_Msk             (0x1ul << EPWM_INTEN0_ZIEN0_Pos)                   /*!< EPWM_T::INTEN0: ZIEN0 Mask              */
+
+#define EPWM_INTEN0_ZIEN1_Pos             (1)                                               /*!< EPWM_T::INTEN0: ZIEN1 Position          */
+#define EPWM_INTEN0_ZIEN1_Msk             (0x1ul << EPWM_INTEN0_ZIEN1_Pos)                   /*!< EPWM_T::INTEN0: ZIEN1 Mask              */
+
+#define EPWM_INTEN0_ZIEN2_Pos             (2)                                               /*!< EPWM_T::INTEN0: ZIEN2 Position          */
+#define EPWM_INTEN0_ZIEN2_Msk             (0x1ul << EPWM_INTEN0_ZIEN2_Pos)                   /*!< EPWM_T::INTEN0: ZIEN2 Mask              */
+
+#define EPWM_INTEN0_ZIEN3_Pos             (3)                                               /*!< EPWM_T::INTEN0: ZIEN3 Position          */
+#define EPWM_INTEN0_ZIEN3_Msk             (0x1ul << EPWM_INTEN0_ZIEN3_Pos)                   /*!< EPWM_T::INTEN0: ZIEN3 Mask              */
+
+#define EPWM_INTEN0_ZIEN4_Pos             (4)                                               /*!< EPWM_T::INTEN0: ZIEN4 Position          */
+#define EPWM_INTEN0_ZIEN4_Msk             (0x1ul << EPWM_INTEN0_ZIEN4_Pos)                   /*!< EPWM_T::INTEN0: ZIEN4 Mask              */
+
+#define EPWM_INTEN0_ZIEN5_Pos             (5)                                               /*!< EPWM_T::INTEN0: ZIEN5 Position          */
+#define EPWM_INTEN0_ZIEN5_Msk             (0x1ul << EPWM_INTEN0_ZIEN5_Pos)                   /*!< EPWM_T::INTEN0: ZIEN5 Mask              */
+
+#define EPWM_INTEN0_PIEN0_Pos             (8)                                               /*!< EPWM_T::INTEN0: PIEN0 Position          */
+#define EPWM_INTEN0_PIEN0_Msk             (0x1ul << EPWM_INTEN0_PIEN0_Pos)                   /*!< EPWM_T::INTEN0: PIEN0 Mask              */
+
+#define EPWM_INTEN0_PIEN1_Pos             (9)                                               /*!< EPWM_T::INTEN0: PIEN1 Position          */
+#define EPWM_INTEN0_PIEN1_Msk             (0x1ul << EPWM_INTEN0_PIEN1_Pos)                   /*!< EPWM_T::INTEN0: PIEN1 Mask              */
+
+#define EPWM_INTEN0_PIEN2_Pos             (10)                                              /*!< EPWM_T::INTEN0: PIEN2 Position          */
+#define EPWM_INTEN0_PIEN2_Msk             (0x1ul << EPWM_INTEN0_PIEN2_Pos)                   /*!< EPWM_T::INTEN0: PIEN2 Mask              */
+
+#define EPWM_INTEN0_PIEN3_Pos             (11)                                              /*!< EPWM_T::INTEN0: PIEN3 Position          */
+#define EPWM_INTEN0_PIEN3_Msk             (0x1ul << EPWM_INTEN0_PIEN3_Pos)                   /*!< EPWM_T::INTEN0: PIEN3 Mask              */
+
+#define EPWM_INTEN0_PIEN4_Pos             (12)                                              /*!< EPWM_T::INTEN0: PIEN4 Position          */
+#define EPWM_INTEN0_PIEN4_Msk             (0x1ul << EPWM_INTEN0_PIEN4_Pos)                   /*!< EPWM_T::INTEN0: PIEN4 Mask              */
+
+#define EPWM_INTEN0_PIEN5_Pos             (13)                                              /*!< EPWM_T::INTEN0: PIEN5 Position          */
+#define EPWM_INTEN0_PIEN5_Msk             (0x1ul << EPWM_INTEN0_PIEN5_Pos)                   /*!< EPWM_T::INTEN0: PIEN5 Mask              */
+
+#define EPWM_INTEN0_CMPUIEN0_Pos          (16)                                              /*!< EPWM_T::INTEN0: CMPUIEN0 Position       */
+#define EPWM_INTEN0_CMPUIEN0_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN0 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN1_Pos          (17)                                              /*!< EPWM_T::INTEN0: CMPUIEN1 Position       */
+#define EPWM_INTEN0_CMPUIEN1_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN1 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN2_Pos          (18)                                              /*!< EPWM_T::INTEN0: CMPUIEN2 Position       */
+#define EPWM_INTEN0_CMPUIEN2_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN2 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN3_Pos          (19)                                              /*!< EPWM_T::INTEN0: CMPUIEN3 Position       */
+#define EPWM_INTEN0_CMPUIEN3_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN3 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN4_Pos          (20)                                              /*!< EPWM_T::INTEN0: CMPUIEN4 Position       */
+#define EPWM_INTEN0_CMPUIEN4_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN4 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN5_Pos          (21)                                              /*!< EPWM_T::INTEN0: CMPUIEN5 Position       */
+#define EPWM_INTEN0_CMPUIEN5_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN5 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN0_Pos          (24)                                              /*!< EPWM_T::INTEN0: CMPDIEN0 Position       */
+#define EPWM_INTEN0_CMPDIEN0_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN0 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN1_Pos          (25)                                              /*!< EPWM_T::INTEN0: CMPDIEN1 Position       */
+#define EPWM_INTEN0_CMPDIEN1_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN1 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN2_Pos          (26)                                              /*!< EPWM_T::INTEN0: CMPDIEN2 Position       */
+#define EPWM_INTEN0_CMPDIEN2_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN2 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN3_Pos          (27)                                              /*!< EPWM_T::INTEN0: CMPDIEN3 Position       */
+#define EPWM_INTEN0_CMPDIEN3_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN3 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN4_Pos          (28)                                              /*!< EPWM_T::INTEN0: CMPDIEN4 Position       */
+#define EPWM_INTEN0_CMPDIEN4_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN4 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN5_Pos          (29)                                              /*!< EPWM_T::INTEN0: CMPDIEN5 Position       */
+#define EPWM_INTEN0_CMPDIEN5_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN5 Mask           */
+
+#define EPWM_INTEN1_BRKEIEN0_1_Pos        (0)                                               /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position     */
+#define EPWM_INTEN1_BRKEIEN0_1_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask         */
+
+#define EPWM_INTEN1_BRKEIEN2_3_Pos        (1)                                               /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position     */
+#define EPWM_INTEN1_BRKEIEN2_3_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask         */
+
+#define EPWM_INTEN1_BRKEIEN4_5_Pos        (2)                                               /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position     */
+#define EPWM_INTEN1_BRKEIEN4_5_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN0_1_Pos        (8)                                               /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position     */
+#define EPWM_INTEN1_BRKLIEN0_1_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN2_3_Pos        (9)                                               /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position     */
+#define EPWM_INTEN1_BRKLIEN2_3_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN4_5_Pos        (10)                                              /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position     */
+#define EPWM_INTEN1_BRKLIEN4_5_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask         */
+
+#define EPWM_INTSTS0_ZIF0_Pos             (0)                                               /*!< EPWM_T::INTSTS0: ZIF0 Position          */
+#define EPWM_INTSTS0_ZIF0_Msk             (0x1ul << EPWM_INTSTS0_ZIF0_Pos)                   /*!< EPWM_T::INTSTS0: ZIF0 Mask              */
+
+#define EPWM_INTSTS0_ZIF1_Pos             (1)                                               /*!< EPWM_T::INTSTS0: ZIF1 Position          */
+#define EPWM_INTSTS0_ZIF1_Msk             (0x1ul << EPWM_INTSTS0_ZIF1_Pos)                   /*!< EPWM_T::INTSTS0: ZIF1 Mask              */
+
+#define EPWM_INTSTS0_ZIF2_Pos             (2)                                               /*!< EPWM_T::INTSTS0: ZIF2 Position          */
+#define EPWM_INTSTS0_ZIF2_Msk             (0x1ul << EPWM_INTSTS0_ZIF2_Pos)                   /*!< EPWM_T::INTSTS0: ZIF2 Mask              */
+
+#define EPWM_INTSTS0_ZIF3_Pos             (3)                                               /*!< EPWM_T::INTSTS0: ZIF3 Position          */
+#define EPWM_INTSTS0_ZIF3_Msk             (0x1ul << EPWM_INTSTS0_ZIF3_Pos)                   /*!< EPWM_T::INTSTS0: ZIF3 Mask              */
+
+#define EPWM_INTSTS0_ZIF4_Pos             (4)                                               /*!< EPWM_T::INTSTS0: ZIF4 Position          */
+#define EPWM_INTSTS0_ZIF4_Msk             (0x1ul << EPWM_INTSTS0_ZIF4_Pos)                   /*!< EPWM_T::INTSTS0: ZIF4 Mask              */
+
+#define EPWM_INTSTS0_ZIF5_Pos             (5)                                               /*!< EPWM_T::INTSTS0: ZIF5 Position          */
+#define EPWM_INTSTS0_ZIF5_Msk             (0x1ul << EPWM_INTSTS0_ZIF5_Pos)                   /*!< EPWM_T::INTSTS0: ZIF5 Mask              */
+
+#define EPWM_INTSTS0_PIF0_Pos             (8)                                               /*!< EPWM_T::INTSTS0: PIF0 Position          */
+#define EPWM_INTSTS0_PIF0_Msk             (0x1ul << EPWM_INTSTS0_PIF0_Pos)                   /*!< EPWM_T::INTSTS0: PIF0 Mask              */
+
+#define EPWM_INTSTS0_PIF1_Pos             (9)                                               /*!< EPWM_T::INTSTS0: PIF1 Position          */
+#define EPWM_INTSTS0_PIF1_Msk             (0x1ul << EPWM_INTSTS0_PIF1_Pos)                   /*!< EPWM_T::INTSTS0: PIF1 Mask              */
+
+#define EPWM_INTSTS0_PIF2_Pos             (10)                                              /*!< EPWM_T::INTSTS0: PIF2 Position          */
+#define EPWM_INTSTS0_PIF2_Msk             (0x1ul << EPWM_INTSTS0_PIF2_Pos)                   /*!< EPWM_T::INTSTS0: PIF2 Mask              */
+
+#define EPWM_INTSTS0_PIF3_Pos             (11)                                              /*!< EPWM_T::INTSTS0: PIF3 Position          */
+#define EPWM_INTSTS0_PIF3_Msk             (0x1ul << EPWM_INTSTS0_PIF3_Pos)                   /*!< EPWM_T::INTSTS0: PIF3 Mask              */
+
+#define EPWM_INTSTS0_PIF4_Pos             (12)                                              /*!< EPWM_T::INTSTS0: PIF4 Position          */
+#define EPWM_INTSTS0_PIF4_Msk             (0x1ul << EPWM_INTSTS0_PIF4_Pos)                   /*!< EPWM_T::INTSTS0: PIF4 Mask              */
+
+#define EPWM_INTSTS0_PIF5_Pos             (13)                                              /*!< EPWM_T::INTSTS0: PIF5 Position          */
+#define EPWM_INTSTS0_PIF5_Msk             (0x1ul << EPWM_INTSTS0_PIF5_Pos)                   /*!< EPWM_T::INTSTS0: PIF5 Mask              */
+
+#define EPWM_INTSTS0_CMPUIF0_Pos          (16)                                              /*!< EPWM_T::INTSTS0: CMPUIF0 Position       */
+#define EPWM_INTSTS0_CMPUIF0_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF0 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF1_Pos          (17)                                              /*!< EPWM_T::INTSTS0: CMPUIF1 Position       */
+#define EPWM_INTSTS0_CMPUIF1_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF1 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF2_Pos          (18)                                              /*!< EPWM_T::INTSTS0: CMPUIF2 Position       */
+#define EPWM_INTSTS0_CMPUIF2_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF2 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF3_Pos          (19)                                              /*!< EPWM_T::INTSTS0: CMPUIF3 Position       */
+#define EPWM_INTSTS0_CMPUIF3_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF3 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF4_Pos          (20)                                              /*!< EPWM_T::INTSTS0: CMPUIF4 Position       */
+#define EPWM_INTSTS0_CMPUIF4_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF4 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF5_Pos          (21)                                              /*!< EPWM_T::INTSTS0: CMPUIF5 Position       */
+#define EPWM_INTSTS0_CMPUIF5_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF5 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF0_Pos          (24)                                              /*!< EPWM_T::INTSTS0: CMPDIF0 Position       */
+#define EPWM_INTSTS0_CMPDIF0_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF0 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF1_Pos          (25)                                              /*!< EPWM_T::INTSTS0: CMPDIF1 Position       */
+#define EPWM_INTSTS0_CMPDIF1_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF1 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF2_Pos          (26)                                              /*!< EPWM_T::INTSTS0: CMPDIF2 Position       */
+#define EPWM_INTSTS0_CMPDIF2_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF2 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF3_Pos          (27)                                              /*!< EPWM_T::INTSTS0: CMPDIF3 Position       */
+#define EPWM_INTSTS0_CMPDIF3_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF3 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF4_Pos          (28)                                              /*!< EPWM_T::INTSTS0: CMPDIF4 Position       */
+#define EPWM_INTSTS0_CMPDIF4_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF4 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF5_Pos          (29)                                              /*!< EPWM_T::INTSTS0: CMPDIF5 Position       */
+#define EPWM_INTSTS0_CMPDIF5_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF0_Pos          (0)                                               /*!< EPWM_T::INTSTS1: BRKEIF0 Position       */
+#define EPWM_INTSTS1_BRKEIF0_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF0 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF1_Pos          (1)                                               /*!< EPWM_T::INTSTS1: BRKEIF1 Position       */
+#define EPWM_INTSTS1_BRKEIF1_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF1 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF2_Pos          (2)                                               /*!< EPWM_T::INTSTS1: BRKEIF2 Position       */
+#define EPWM_INTSTS1_BRKEIF2_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF2 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF3_Pos          (3)                                               /*!< EPWM_T::INTSTS1: BRKEIF3 Position       */
+#define EPWM_INTSTS1_BRKEIF3_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF3 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF4_Pos          (4)                                               /*!< EPWM_T::INTSTS1: BRKEIF4 Position       */
+#define EPWM_INTSTS1_BRKEIF4_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF4 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF5_Pos          (5)                                               /*!< EPWM_T::INTSTS1: BRKEIF5 Position       */
+#define EPWM_INTSTS1_BRKEIF5_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF0_Pos          (8)                                               /*!< EPWM_T::INTSTS1: BRKLIF0 Position       */
+#define EPWM_INTSTS1_BRKLIF0_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF0 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF1_Pos          (9)                                               /*!< EPWM_T::INTSTS1: BRKLIF1 Position       */
+#define EPWM_INTSTS1_BRKLIF1_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF1 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF2_Pos          (10)                                              /*!< EPWM_T::INTSTS1: BRKLIF2 Position       */
+#define EPWM_INTSTS1_BRKLIF2_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF2 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF3_Pos          (11)                                              /*!< EPWM_T::INTSTS1: BRKLIF3 Position       */
+#define EPWM_INTSTS1_BRKLIF3_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF3 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF4_Pos          (12)                                              /*!< EPWM_T::INTSTS1: BRKLIF4 Position       */
+#define EPWM_INTSTS1_BRKLIF4_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF4 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF5_Pos          (13)                                              /*!< EPWM_T::INTSTS1: BRKLIF5 Position       */
+#define EPWM_INTSTS1_BRKLIF5_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKESTS0_Pos         (16)                                              /*!< EPWM_T::INTSTS1: BRKESTS0 Position      */
+#define EPWM_INTSTS1_BRKESTS0_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS0 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS1_Pos         (17)                                              /*!< EPWM_T::INTSTS1: BRKESTS1 Position      */
+#define EPWM_INTSTS1_BRKESTS1_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS1 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS2_Pos         (18)                                              /*!< EPWM_T::INTSTS1: BRKESTS2 Position      */
+#define EPWM_INTSTS1_BRKESTS2_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS2 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS3_Pos         (19)                                              /*!< EPWM_T::INTSTS1: BRKESTS3 Position      */
+#define EPWM_INTSTS1_BRKESTS3_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS3 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS4_Pos         (20)                                              /*!< EPWM_T::INTSTS1: BRKESTS4 Position      */
+#define EPWM_INTSTS1_BRKESTS4_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS4 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS5_Pos         (21)                                              /*!< EPWM_T::INTSTS1: BRKESTS5 Position      */
+#define EPWM_INTSTS1_BRKESTS5_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS5 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS0_Pos         (24)                                              /*!< EPWM_T::INTSTS1: BRKLSTS0 Position      */
+#define EPWM_INTSTS1_BRKLSTS0_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS1_Pos         (25)                                              /*!< EPWM_T::INTSTS1: BRKLSTS1 Position      */
+#define EPWM_INTSTS1_BRKLSTS1_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS2_Pos         (26)                                              /*!< EPWM_T::INTSTS1: BRKLSTS2 Position      */
+#define EPWM_INTSTS1_BRKLSTS2_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS3_Pos         (27)                                              /*!< EPWM_T::INTSTS1: BRKLSTS3 Position      */
+#define EPWM_INTSTS1_BRKLSTS3_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS4_Pos         (28)                                              /*!< EPWM_T::INTSTS1: BRKLSTS4 Position      */
+#define EPWM_INTSTS1_BRKLSTS4_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS5_Pos         (29)                                              /*!< EPWM_T::INTSTS1: BRKLSTS5 Position      */
+#define EPWM_INTSTS1_BRKLSTS5_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask          */
+
+#define EPWM_DACTRGEN_ZTE0_Pos            (0)                                               /*!< EPWM_T::DACTRGEN: ZTE0 Position         */
+#define EPWM_DACTRGEN_ZTE0_Msk            (0x1ul << EPWM_DACTRGEN_ZTE0_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE0 Mask             */
+
+#define EPWM_DACTRGEN_ZTE1_Pos            (1)                                               /*!< EPWM_T::DACTRGEN: ZTE1 Position         */
+#define EPWM_DACTRGEN_ZTE1_Msk            (0x1ul << EPWM_DACTRGEN_ZTE1_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE1 Mask             */
+
+#define EPWM_DACTRGEN_ZTE2_Pos            (2)                                               /*!< EPWM_T::DACTRGEN: ZTE2 Position         */
+#define EPWM_DACTRGEN_ZTE2_Msk            (0x1ul << EPWM_DACTRGEN_ZTE2_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE2 Mask             */
+
+#define EPWM_DACTRGEN_ZTE3_Pos            (3)                                               /*!< EPWM_T::DACTRGEN: ZTE3 Position         */
+#define EPWM_DACTRGEN_ZTE3_Msk            (0x1ul << EPWM_DACTRGEN_ZTE3_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE3 Mask             */
+
+#define EPWM_DACTRGEN_ZTE4_Pos            (4)                                               /*!< EPWM_T::DACTRGEN: ZTE4 Position         */
+#define EPWM_DACTRGEN_ZTE4_Msk            (0x1ul << EPWM_DACTRGEN_ZTE4_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE4 Mask             */
+
+#define EPWM_DACTRGEN_ZTE5_Pos            (5)                                               /*!< EPWM_T::DACTRGEN: ZTE5 Position         */
+#define EPWM_DACTRGEN_ZTE5_Msk            (0x1ul << EPWM_DACTRGEN_ZTE5_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE5 Mask             */
+
+#define EPWM_DACTRGEN_PTE0_Pos            (8)                                               /*!< EPWM_T::DACTRGEN: PTE0 Position         */
+#define EPWM_DACTRGEN_PTE0_Msk            (0x1ul << EPWM_DACTRGEN_PTE0_Pos)                  /*!< EPWM_T::DACTRGEN: PTE0 Mask             */
+
+#define EPWM_DACTRGEN_PTE1_Pos            (9)                                               /*!< EPWM_T::DACTRGEN: PTE1 Position         */
+#define EPWM_DACTRGEN_PTE1_Msk            (0x1ul << EPWM_DACTRGEN_PTE1_Pos)                  /*!< EPWM_T::DACTRGEN: PTE1 Mask             */
+
+#define EPWM_DACTRGEN_PTE2_Pos            (10)                                              /*!< EPWM_T::DACTRGEN: PTE2 Position         */
+#define EPWM_DACTRGEN_PTE2_Msk            (0x1ul << EPWM_DACTRGEN_PTE2_Pos)                  /*!< EPWM_T::DACTRGEN: PTE2 Mask             */
+
+#define EPWM_DACTRGEN_PTE3_Pos            (11)                                              /*!< EPWM_T::DACTRGEN: PTE3 Position         */
+#define EPWM_DACTRGEN_PTE3_Msk            (0x1ul << EPWM_DACTRGEN_PTE3_Pos)                  /*!< EPWM_T::DACTRGEN: PTE3 Mask             */
+
+#define EPWM_DACTRGEN_PTE4_Pos            (12)                                              /*!< EPWM_T::DACTRGEN: PTE4 Position         */
+#define EPWM_DACTRGEN_PTE4_Msk            (0x1ul << EPWM_DACTRGEN_PTE4_Pos)                  /*!< EPWM_T::DACTRGEN: PTE4 Mask             */
+
+#define EPWM_DACTRGEN_PTE5_Pos            (13)                                              /*!< EPWM_T::DACTRGEN: PTE5 Position         */
+#define EPWM_DACTRGEN_PTE5_Msk            (0x1ul << EPWM_DACTRGEN_PTE5_Pos)                  /*!< EPWM_T::DACTRGEN: PTE5 Mask             */
+
+#define EPWM_DACTRGEN_CUTRGE0_Pos         (16)                                              /*!< EPWM_T::DACTRGEN: CUTRGE0 Position      */
+#define EPWM_DACTRGEN_CUTRGE0_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE1_Pos         (17)                                              /*!< EPWM_T::DACTRGEN: CUTRGE1 Position      */
+#define EPWM_DACTRGEN_CUTRGE1_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE2_Pos         (18)                                              /*!< EPWM_T::DACTRGEN: CUTRGE2 Position      */
+#define EPWM_DACTRGEN_CUTRGE2_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE3_Pos         (19)                                              /*!< EPWM_T::DACTRGEN: CUTRGE3 Position      */
+#define EPWM_DACTRGEN_CUTRGE3_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE4_Pos         (20)                                              /*!< EPWM_T::DACTRGEN: CUTRGE4 Position      */
+#define EPWM_DACTRGEN_CUTRGE4_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE5_Pos         (21)                                              /*!< EPWM_T::DACTRGEN: CUTRGE5 Position      */
+#define EPWM_DACTRGEN_CUTRGE5_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE0_Pos         (24)                                              /*!< EPWM_T::DACTRGEN: CDTRGE0 Position      */
+#define EPWM_DACTRGEN_CDTRGE0_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE1_Pos         (25)                                              /*!< EPWM_T::DACTRGEN: CDTRGE1 Position      */
+#define EPWM_DACTRGEN_CDTRGE1_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE2_Pos         (26)                                              /*!< EPWM_T::DACTRGEN: CDTRGE2 Position      */
+#define EPWM_DACTRGEN_CDTRGE2_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE3_Pos         (27)                                              /*!< EPWM_T::DACTRGEN: CDTRGE3 Position      */
+#define EPWM_DACTRGEN_CDTRGE3_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE4_Pos         (28)                                              /*!< EPWM_T::DACTRGEN: CDTRGE4 Position      */
+#define EPWM_DACTRGEN_CDTRGE4_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE5_Pos         (29)                                              /*!< EPWM_T::DACTRGEN: CDTRGE5 Position      */
+#define EPWM_DACTRGEN_CDTRGE5_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask          */
+
+#define EPWM_EADCTS0_TRGSEL0_Pos          (0)                                               /*!< EPWM_T::EADCTS0: TRGSEL0 Position       */
+#define EPWM_EADCTS0_TRGSEL0_Msk          (0xful << EPWM_EADCTS0_TRGSEL0_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL0 Mask           */
+
+#define EPWM_EADCTS0_TRGEN0_Pos           (7)                                               /*!< EPWM_T::EADCTS0: TRGEN0 Position        */
+#define EPWM_EADCTS0_TRGEN0_Msk           (0x1ul << EPWM_EADCTS0_TRGEN0_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN0 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL1_Pos          (8)                                               /*!< EPWM_T::EADCTS0: TRGSEL1 Position       */
+#define EPWM_EADCTS0_TRGSEL1_Msk          (0xful << EPWM_EADCTS0_TRGSEL1_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL1 Mask           */
+
+#define EPWM_EADCTS0_TRGEN1_Pos           (15)                                              /*!< EPWM_T::EADCTS0: TRGEN1 Position        */
+#define EPWM_EADCTS0_TRGEN1_Msk           (0x1ul << EPWM_EADCTS0_TRGEN1_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN1 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL2_Pos          (16)                                              /*!< EPWM_T::EADCTS0: TRGSEL2 Position       */
+#define EPWM_EADCTS0_TRGSEL2_Msk          (0xful << EPWM_EADCTS0_TRGSEL2_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL2 Mask           */
+
+#define EPWM_EADCTS0_TRGEN2_Pos           (23)                                              /*!< EPWM_T::EADCTS0: TRGEN2 Position        */
+#define EPWM_EADCTS0_TRGEN2_Msk           (0x1ul << EPWM_EADCTS0_TRGEN2_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN2 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL3_Pos          (24)                                              /*!< EPWM_T::EADCTS0: TRGSEL3 Position       */
+#define EPWM_EADCTS0_TRGSEL3_Msk          (0xful << EPWM_EADCTS0_TRGSEL3_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL3 Mask           */
+
+#define EPWM_EADCTS0_TRGEN3_Pos           (31)                                              /*!< EPWM_T::EADCTS0: TRGEN3 Position        */
+#define EPWM_EADCTS0_TRGEN3_Msk           (0x1ul << EPWM_EADCTS0_TRGEN3_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN3 Mask            */
+
+#define EPWM_EADCTS1_TRGSEL4_Pos          (0)                                               /*!< EPWM_T::EADCTS1: TRGSEL4 Position       */
+#define EPWM_EADCTS1_TRGSEL4_Msk          (0xful << EPWM_EADCTS1_TRGSEL4_Pos)                /*!< EPWM_T::EADCTS1: TRGSEL4 Mask           */
+
+#define EPWM_EADCTS1_TRGEN4_Pos           (7)                                               /*!< EPWM_T::EADCTS1: TRGEN4 Position        */
+#define EPWM_EADCTS1_TRGEN4_Msk           (0x1ul << EPWM_EADCTS1_TRGEN4_Pos)                 /*!< EPWM_T::EADCTS1: TRGEN4 Mask            */
+
+#define EPWM_EADCTS1_TRGSEL5_Pos          (8)                                               /*!< EPWM_T::EADCTS1: TRGSEL5 Position       */
+#define EPWM_EADCTS1_TRGSEL5_Msk          (0xful << EPWM_EADCTS1_TRGSEL5_Pos)                /*!< EPWM_T::EADCTS1: TRGSEL5 Mask           */
+
+#define EPWM_EADCTS1_TRGEN5_Pos           (15)                                              /*!< EPWM_T::EADCTS1: TRGEN5 Position        */
+#define EPWM_EADCTS1_TRGEN5_Msk           (0x1ul << EPWM_EADCTS1_TRGEN5_Pos)                 /*!< EPWM_T::EADCTS1: TRGEN5 Mask            */
+
+#define EPWM_FTCMPDAT0_1_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position     */
+#define EPWM_FTCMPDAT0_1_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask         */
+
+#define EPWM_FTCMPDAT2_3_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position     */
+#define EPWM_FTCMPDAT2_3_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask         */
+
+#define EPWM_FTCMPDAT4_5_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position     */
+#define EPWM_FTCMPDAT4_5_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask         */
+
+#define EPWM_SSCTL_SSEN0_Pos              (0)                                               /*!< EPWM_T::SSCTL: SSEN0 Position           */
+#define EPWM_SSCTL_SSEN0_Msk              (0x1ul << EPWM_SSCTL_SSEN0_Pos)                    /*!< EPWM_T::SSCTL: SSEN0 Mask               */
+
+#define EPWM_SSCTL_SSEN1_Pos              (1)                                               /*!< EPWM_T::SSCTL: SSEN1 Position           */
+#define EPWM_SSCTL_SSEN1_Msk              (0x1ul << EPWM_SSCTL_SSEN1_Pos)                    /*!< EPWM_T::SSCTL: SSEN1 Mask               */
+
+#define EPWM_SSCTL_SSEN2_Pos              (2)                                               /*!< EPWM_T::SSCTL: SSEN2 Position           */
+#define EPWM_SSCTL_SSEN2_Msk              (0x1ul << EPWM_SSCTL_SSEN2_Pos)                    /*!< EPWM_T::SSCTL: SSEN2 Mask               */
+
+#define EPWM_SSCTL_SSEN3_Pos              (3)                                               /*!< EPWM_T::SSCTL: SSEN3 Position           */
+#define EPWM_SSCTL_SSEN3_Msk              (0x1ul << EPWM_SSCTL_SSEN3_Pos)                    /*!< EPWM_T::SSCTL: SSEN3 Mask               */
+
+#define EPWM_SSCTL_SSEN4_Pos              (4)                                               /*!< EPWM_T::SSCTL: SSEN4 Position           */
+#define EPWM_SSCTL_SSEN4_Msk              (0x1ul << EPWM_SSCTL_SSEN4_Pos)                    /*!< EPWM_T::SSCTL: SSEN4 Mask               */
+
+#define EPWM_SSCTL_SSEN5_Pos              (5)                                               /*!< EPWM_T::SSCTL: SSEN5 Position           */
+#define EPWM_SSCTL_SSEN5_Msk              (0x1ul << EPWM_SSCTL_SSEN5_Pos)                    /*!< EPWM_T::SSCTL: SSEN5 Mask               */
+
+#define EPWM_SSCTL_SSRC_Pos               (8)                                               /*!< EPWM_T::SSCTL: SSRC Position            */
+#define EPWM_SSCTL_SSRC_Msk               (0x3ul << EPWM_SSCTL_SSRC_Pos)                     /*!< EPWM_T::SSCTL: SSRC Mask                */
+
+#define EPWM_SSTRG_CNTSEN_Pos             (0)                                               /*!< EPWM_T::SSTRG: CNTSEN Position          */
+#define EPWM_SSTRG_CNTSEN_Msk             (0x1ul << EPWM_SSTRG_CNTSEN_Pos)                   /*!< EPWM_T::SSTRG: CNTSEN Mask              */
+
+#define EPWM_LEBCTL_LEBEN_Pos             (0)                                               /*!< EPWM_T::LEBCTL: LEBEN Position          */
+#define EPWM_LEBCTL_LEBEN_Msk             (0x1ul << EPWM_LEBCTL_LEBEN_Pos)                   /*!< EPWM_T::LEBCTL: LEBEN Mask              */
+
+#define EPWM_LEBCTL_SRCEN0_Pos            (8)                                               /*!< EPWM_T::LEBCTL: SRCEN0 Position         */
+#define EPWM_LEBCTL_SRCEN0_Msk            (0x1ul << EPWM_LEBCTL_SRCEN0_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN0 Mask             */
+
+#define EPWM_LEBCTL_SRCEN2_Pos            (9)                                               /*!< EPWM_T::LEBCTL: SRCEN2 Position         */
+#define EPWM_LEBCTL_SRCEN2_Msk            (0x1ul << EPWM_LEBCTL_SRCEN2_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN2 Mask             */
+
+#define EPWM_LEBCTL_SRCEN4_Pos            (10)                                              /*!< EPWM_T::LEBCTL: SRCEN4 Position         */
+#define EPWM_LEBCTL_SRCEN4_Msk            (0x1ul << EPWM_LEBCTL_SRCEN4_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN4 Mask             */
+
+#define EPWM_LEBCTL_TRGTYPE_Pos           (16)                                              /*!< EPWM_T::LEBCTL: TRGTYPE Position        */
+#define EPWM_LEBCTL_TRGTYPE_Msk           (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos)                 /*!< EPWM_T::LEBCTL: TRGTYPE Mask            */
+
+#define EPWM_LEBCNT_LEBCNT_Pos            (0)                                               /*!< EPWM_T::LEBCNT: LEBCNT Position         */
+#define EPWM_LEBCNT_LEBCNT_Msk            (0x1fful << EPWM_LEBCNT_LEBCNT_Pos)                /*!< EPWM_T::LEBCNT: LEBCNT Mask             */
+
+#define EPWM_STATUS_CNTMAXF0_Pos          (0)                                               /*!< EPWM_T::STATUS: CNTMAXF0 Position       */
+#define EPWM_STATUS_CNTMAXF0_Msk          (0x1ul << EPWM_STATUS_CNTMAXF0_Pos)                /*!< EPWM_T::STATUS: CNTMAXF0 Mask           */
+
+#define EPWM_STATUS_CNTMAXF1_Pos          (1)                                               /*!< EPWM_T::STATUS: CNTMAXF1 Position       */
+#define EPWM_STATUS_CNTMAXF1_Msk          (0x1ul << EPWM_STATUS_CNTMAXF1_Pos)                /*!< EPWM_T::STATUS: CNTMAXF1 Mask           */
+
+#define EPWM_STATUS_CNTMAXF2_Pos          (2)                                               /*!< EPWM_T::STATUS: CNTMAXF2 Position       */
+#define EPWM_STATUS_CNTMAXF2_Msk          (0x1ul << EPWM_STATUS_CNTMAXF2_Pos)                /*!< EPWM_T::STATUS: CNTMAXF2 Mask           */
+
+#define EPWM_STATUS_CNTMAXF3_Pos          (3)                                               /*!< EPWM_T::STATUS: CNTMAXF3 Position       */
+#define EPWM_STATUS_CNTMAXF3_Msk          (0x1ul << EPWM_STATUS_CNTMAXF3_Pos)                /*!< EPWM_T::STATUS: CNTMAXF3 Mask           */
+
+#define EPWM_STATUS_CNTMAXF4_Pos          (4)                                               /*!< EPWM_T::STATUS: CNTMAXF4 Position       */
+#define EPWM_STATUS_CNTMAXF4_Msk          (0x1ul << EPWM_STATUS_CNTMAXF4_Pos)                /*!< EPWM_T::STATUS: CNTMAXF4 Mask           */
+
+#define EPWM_STATUS_CNTMAXF5_Pos          (5)                                               /*!< EPWM_T::STATUS: CNTMAXF5 Position       */
+#define EPWM_STATUS_CNTMAXF5_Msk          (0x1ul << EPWM_STATUS_CNTMAXF5_Pos)                /*!< EPWM_T::STATUS: CNTMAXF5 Mask           */
+
+#define EPWM_STATUS_SYNCINF0_Pos          (8)                                               /*!< EPWM_T::STATUS: SYNCINF0 Position       */
+#define EPWM_STATUS_SYNCINF0_Msk          (0x1ul << EPWM_STATUS_SYNCINF0_Pos)                /*!< EPWM_T::STATUS: SYNCINF0 Mask           */
+
+#define EPWM_STATUS_SYNCINF2_Pos          (9)                                               /*!< EPWM_T::STATUS: SYNCINF2 Position       */
+#define EPWM_STATUS_SYNCINF2_Msk          (0x1ul << EPWM_STATUS_SYNCINF2_Pos)                /*!< EPWM_T::STATUS: SYNCINF2 Mask           */
+
+#define EPWM_STATUS_SYNCINF4_Pos          (10)                                              /*!< EPWM_T::STATUS: SYNCINF4 Position       */
+#define EPWM_STATUS_SYNCINF4_Msk          (0x1ul << EPWM_STATUS_SYNCINF4_Pos)                /*!< EPWM_T::STATUS: SYNCINF4 Mask           */
+
+#define EPWM_STATUS_EADCTRGF0_Pos         (16)                                              /*!< EPWM_T::STATUS: EADCTRGF0 Position      */
+#define EPWM_STATUS_EADCTRGF0_Msk         (0x1ul << EPWM_STATUS_EADCTRGF0_Pos)               /*!< EPWM_T::STATUS: EADCTRGF0 Mask          */
+
+#define EPWM_STATUS_EADCTRGF1_Pos         (17)                                              /*!< EPWM_T::STATUS: EADCTRGF1 Position      */
+#define EPWM_STATUS_EADCTRGF1_Msk         (0x1ul << EPWM_STATUS_EADCTRGF1_Pos)               /*!< EPWM_T::STATUS: EADCTRGF1 Mask          */
+
+#define EPWM_STATUS_EADCTRGF2_Pos         (18)                                              /*!< EPWM_T::STATUS: EADCTRGF2 Position      */
+#define EPWM_STATUS_EADCTRGF2_Msk         (0x1ul << EPWM_STATUS_EADCTRGF2_Pos)               /*!< EPWM_T::STATUS: EADCTRGF2 Mask          */
+
+#define EPWM_STATUS_EADCTRGF3_Pos         (19)                                              /*!< EPWM_T::STATUS: EADCTRGF3 Position      */
+#define EPWM_STATUS_EADCTRGF3_Msk         (0x1ul << EPWM_STATUS_EADCTRGF3_Pos)               /*!< EPWM_T::STATUS: EADCTRGF3 Mask          */
+
+#define EPWM_STATUS_EADCTRGF4_Pos         (20)                                              /*!< EPWM_T::STATUS: EADCTRGF4 Position      */
+#define EPWM_STATUS_EADCTRGF4_Msk         (0x1ul << EPWM_STATUS_EADCTRGF4_Pos)               /*!< EPWM_T::STATUS: EADCTRGF4 Mask          */
+
+#define EPWM_STATUS_EADCTRGF5_Pos         (21)                                              /*!< EPWM_T::STATUS: EADCTRGF5 Position      */
+#define EPWM_STATUS_EADCTRGF5_Msk         (0x1ul << EPWM_STATUS_EADCTRGF5_Pos)               /*!< EPWM_T::STATUS: EADCTRGF5 Mask          */
+
+#define EPWM_STATUS_DACTRGF_Pos           (24)                                              /*!< EPWM_T::STATUS: DACTRGF Position        */
+#define EPWM_STATUS_DACTRGF_Msk           (0x1ul << EPWM_STATUS_DACTRGF_Pos)                 /*!< EPWM_T::STATUS: DACTRGF Mask            */
+
+#define EPWM_IFA0_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA0: IFACNT Position           */
+#define EPWM_IFA0_IFACNT_Msk              (0xfffful << EPWM_IFA0_IFACNT_Pos)                 /*!< EPWM_T::IFA0: IFACNT Mask               */
+
+#define EPWM_IFA0_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA0: IFASEL Position           */
+#define EPWM_IFA0_IFASEL_Msk              (0x3ul << EPWM_IFA0_IFASEL_Pos)                    /*!< EPWM_T::IFA0: IFASEL Mask               */
+
+#define EPWM_IFA0_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA0: IFAEN Position            */
+#define EPWM_IFA0_IFAEN_Msk               (0x1ul << EPWM_IFA0_IFAEN_Pos)                     /*!< EPWM_T::IFA0: IFAEN Mask                */
+
+#define EPWM_IFA1_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA1: IFACNT Position           */
+#define EPWM_IFA1_IFACNT_Msk              (0xfffful << EPWM_IFA1_IFACNT_Pos)                 /*!< EPWM_T::IFA1: IFACNT Mask               */
+
+#define EPWM_IFA1_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA1: IFASEL Position           */
+#define EPWM_IFA1_IFASEL_Msk              (0x3ul << EPWM_IFA1_IFASEL_Pos)                    /*!< EPWM_T::IFA1: IFASEL Mask               */
+
+#define EPWM_IFA1_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA1: IFAEN Position            */
+#define EPWM_IFA1_IFAEN_Msk               (0x1ul << EPWM_IFA1_IFAEN_Pos)                     /*!< EPWM_T::IFA1: IFAEN Mask                */
+
+#define EPWM_IFA2_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA2: IFACNT Position           */
+#define EPWM_IFA2_IFACNT_Msk              (0xfffful << EPWM_IFA2_IFACNT_Pos)                 /*!< EPWM_T::IFA2: IFACNT Mask               */
+
+#define EPWM_IFA2_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA2: IFASEL Position           */
+#define EPWM_IFA2_IFASEL_Msk              (0x3ul << EPWM_IFA2_IFASEL_Pos)                    /*!< EPWM_T::IFA2: IFASEL Mask               */
+
+#define EPWM_IFA2_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA2: IFAEN Position            */
+#define EPWM_IFA2_IFAEN_Msk               (0x1ul << EPWM_IFA2_IFAEN_Pos)                     /*!< EPWM_T::IFA2: IFAEN Mask                */
+
+#define EPWM_IFA3_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA3: IFACNT Position           */
+#define EPWM_IFA3_IFACNT_Msk              (0xfffful << EPWM_IFA3_IFACNT_Pos)                 /*!< EPWM_T::IFA3: IFACNT Mask               */
+
+#define EPWM_IFA3_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA3: IFASEL Position           */
+#define EPWM_IFA3_IFASEL_Msk              (0x3ul << EPWM_IFA3_IFASEL_Pos)                    /*!< EPWM_T::IFA3: IFASEL Mask               */
+
+#define EPWM_IFA3_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA3: IFAEN Position            */
+#define EPWM_IFA3_IFAEN_Msk               (0x1ul << EPWM_IFA3_IFAEN_Pos)                     /*!< EPWM_T::IFA3: IFAEN Mask                */
+
+#define EPWM_IFA4_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA4: IFACNT Position           */
+#define EPWM_IFA4_IFACNT_Msk              (0xfffful << EPWM_IFA4_IFACNT_Pos)                 /*!< EPWM_T::IFA4: IFACNT Mask               */
+
+#define EPWM_IFA4_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA4: IFASEL Position           */
+#define EPWM_IFA4_IFASEL_Msk              (0x3ul << EPWM_IFA4_IFASEL_Pos)                    /*!< EPWM_T::IFA4: IFASEL Mask               */
+
+#define EPWM_IFA4_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA4: IFAEN Position            */
+#define EPWM_IFA4_IFAEN_Msk               (0x1ul << EPWM_IFA4_IFAEN_Pos)                     /*!< EPWM_T::IFA4: IFAEN Mask                */
+
+#define EPWM_IFA5_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA5: IFACNT Position           */
+#define EPWM_IFA5_IFACNT_Msk              (0xfffful << EPWM_IFA5_IFACNT_Pos)                 /*!< EPWM_T::IFA5: IFACNT Mask               */
+
+#define EPWM_IFA5_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA5: IFASEL Position           */
+#define EPWM_IFA5_IFASEL_Msk              (0x3ul << EPWM_IFA5_IFASEL_Pos)                    /*!< EPWM_T::IFA5: IFASEL Mask               */
+
+#define EPWM_IFA5_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA5: IFAEN Position            */
+#define EPWM_IFA5_IFAEN_Msk               (0x1ul << EPWM_IFA5_IFAEN_Pos)                     /*!< EPWM_T::IFA5: IFAEN Mask                */
+
+#define EPWM_AINTSTS_IFAIF0_Pos           (0)                                               /*!< EPWM_T::AINTSTS: IFAIF0 Position        */
+#define EPWM_AINTSTS_IFAIF0_Msk           (0x1ul << EPWM_AINTSTS_IFAIF0_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF0 Mask            */
+
+#define EPWM_AINTSTS_IFAIF1_Pos           (1)                                               /*!< EPWM_T::AINTSTS: IFAIF1 Position        */
+#define EPWM_AINTSTS_IFAIF1_Msk           (0x1ul << EPWM_AINTSTS_IFAIF1_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF1 Mask            */
+
+#define EPWM_AINTSTS_IFAIF2_Pos           (2)                                               /*!< EPWM_T::AINTSTS: IFAIF2 Position        */
+#define EPWM_AINTSTS_IFAIF2_Msk           (0x1ul << EPWM_AINTSTS_IFAIF2_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF2 Mask            */
+
+#define EPWM_AINTSTS_IFAIF3_Pos           (3)                                               /*!< EPWM_T::AINTSTS: IFAIF3 Position        */
+#define EPWM_AINTSTS_IFAIF3_Msk           (0x1ul << EPWM_AINTSTS_IFAIF3_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF3 Mask            */
+
+#define EPWM_AINTSTS_IFAIF4_Pos           (4)                                               /*!< EPWM_T::AINTSTS: IFAIF4 Position        */
+#define EPWM_AINTSTS_IFAIF4_Msk           (0x1ul << EPWM_AINTSTS_IFAIF4_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF4 Mask            */
+
+#define EPWM_AINTSTS_IFAIF5_Pos           (5)                                               /*!< EPWM_T::AINTSTS: IFAIF5 Position        */
+#define EPWM_AINTSTS_IFAIF5_Msk           (0x1ul << EPWM_AINTSTS_IFAIF5_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF5 Mask            */
+
+#define EPWM_AINTEN_IFAIEN0_Pos           (0)                                               /*!< EPWM_T::AINTEN: IFAIEN0 Position        */
+#define EPWM_AINTEN_IFAIEN0_Msk           (0x1ul << EPWM_AINTEN_IFAIEN0_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN0 Mask            */
+
+#define EPWM_AINTEN_IFAIEN1_Pos           (1)                                               /*!< EPWM_T::AINTEN: IFAIEN1 Position        */
+#define EPWM_AINTEN_IFAIEN1_Msk           (0x1ul << EPWM_AINTEN_IFAIEN1_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN1 Mask            */
+
+#define EPWM_AINTEN_IFAIEN2_Pos           (2)                                               /*!< EPWM_T::AINTEN: IFAIEN2 Position        */
+#define EPWM_AINTEN_IFAIEN2_Msk           (0x1ul << EPWM_AINTEN_IFAIEN2_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN2 Mask            */
+
+#define EPWM_AINTEN_IFAIEN3_Pos           (3)                                               /*!< EPWM_T::AINTEN: IFAIEN3 Position        */
+#define EPWM_AINTEN_IFAIEN3_Msk           (0x1ul << EPWM_AINTEN_IFAIEN3_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN3 Mask            */
+
+#define EPWM_AINTEN_IFAIEN4_Pos           (4)                                               /*!< EPWM_T::AINTEN: IFAIEN4 Position        */
+#define EPWM_AINTEN_IFAIEN4_Msk           (0x1ul << EPWM_AINTEN_IFAIEN4_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN4 Mask            */
+
+#define EPWM_AINTEN_IFAIEN5_Pos           (5)                                               /*!< EPWM_T::AINTEN: IFAIEN5 Position        */
+#define EPWM_AINTEN_IFAIEN5_Msk           (0x1ul << EPWM_AINTEN_IFAIEN5_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN5 Mask            */
+
+#define EPWM_APDMACTL_APDMAEN0_Pos        (0)                                               /*!< EPWM_T::APDMACTL: APDMAEN0 Position     */
+#define EPWM_APDMACTL_APDMAEN0_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN0 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN1_Pos        (1)                                               /*!< EPWM_T::APDMACTL: APDMAEN1 Position     */
+#define EPWM_APDMACTL_APDMAEN1_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN1 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN2_Pos        (2)                                               /*!< EPWM_T::APDMACTL: APDMAEN2 Position     */
+#define EPWM_APDMACTL_APDMAEN2_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN2 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN3_Pos        (3)                                               /*!< EPWM_T::APDMACTL: APDMAEN3 Position     */
+#define EPWM_APDMACTL_APDMAEN3_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN3 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN4_Pos        (4)                                               /*!< EPWM_T::APDMACTL: APDMAEN4 Position     */
+#define EPWM_APDMACTL_APDMAEN4_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN4 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN5_Pos        (5)                                               /*!< EPWM_T::APDMACTL: APDMAEN5 Position     */
+#define EPWM_APDMACTL_APDMAEN5_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN5 Mask         */
+
+#define EPWM_CAPINEN_CAPINEN0_Pos         (0)                                               /*!< EPWM_T::CAPINEN: CAPINEN0 Position      */
+#define EPWM_CAPINEN_CAPINEN0_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN0 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN1_Pos         (1)                                               /*!< EPWM_T::CAPINEN: CAPINEN1 Position      */
+#define EPWM_CAPINEN_CAPINEN1_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN1 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN2_Pos         (2)                                               /*!< EPWM_T::CAPINEN: CAPINEN2 Position      */
+#define EPWM_CAPINEN_CAPINEN2_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN2 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN3_Pos         (3)                                               /*!< EPWM_T::CAPINEN: CAPINEN3 Position      */
+#define EPWM_CAPINEN_CAPINEN3_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN3 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN4_Pos         (4)                                               /*!< EPWM_T::CAPINEN: CAPINEN4 Position      */
+#define EPWM_CAPINEN_CAPINEN4_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN4 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN5_Pos         (5)                                               /*!< EPWM_T::CAPINEN: CAPINEN5 Position      */
+#define EPWM_CAPINEN_CAPINEN5_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN5 Mask          */
+
+#define EPWM_CAPCTL_CAPEN0_Pos            (0)                                               /*!< EPWM_T::CAPCTL: CAPEN0 Position         */
+#define EPWM_CAPCTL_CAPEN0_Msk            (0x1ul << EPWM_CAPCTL_CAPEN0_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN0 Mask             */
+
+#define EPWM_CAPCTL_CAPEN1_Pos            (1)                                               /*!< EPWM_T::CAPCTL: CAPEN1 Position         */
+#define EPWM_CAPCTL_CAPEN1_Msk            (0x1ul << EPWM_CAPCTL_CAPEN1_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN1 Mask             */
+
+#define EPWM_CAPCTL_CAPEN2_Pos            (2)                                               /*!< EPWM_T::CAPCTL: CAPEN2 Position         */
+#define EPWM_CAPCTL_CAPEN2_Msk            (0x1ul << EPWM_CAPCTL_CAPEN2_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN2 Mask             */
+
+#define EPWM_CAPCTL_CAPEN3_Pos            (3)                                               /*!< EPWM_T::CAPCTL: CAPEN3 Position         */
+#define EPWM_CAPCTL_CAPEN3_Msk            (0x1ul << EPWM_CAPCTL_CAPEN3_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN3 Mask             */
+
+#define EPWM_CAPCTL_CAPEN4_Pos            (4)                                               /*!< EPWM_T::CAPCTL: CAPEN4 Position         */
+#define EPWM_CAPCTL_CAPEN4_Msk            (0x1ul << EPWM_CAPCTL_CAPEN4_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN4 Mask             */
+
+#define EPWM_CAPCTL_CAPEN5_Pos            (5)                                               /*!< EPWM_T::CAPCTL: CAPEN5 Position         */
+#define EPWM_CAPCTL_CAPEN5_Msk            (0x1ul << EPWM_CAPCTL_CAPEN5_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN5 Mask             */
+
+#define EPWM_CAPCTL_CAPINV0_Pos           (8)                                               /*!< EPWM_T::CAPCTL: CAPINV0 Position        */
+#define EPWM_CAPCTL_CAPINV0_Msk           (0x1ul << EPWM_CAPCTL_CAPINV0_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV0 Mask            */
+
+#define EPWM_CAPCTL_CAPINV1_Pos           (9)                                               /*!< EPWM_T::CAPCTL: CAPINV1 Position        */
+#define EPWM_CAPCTL_CAPINV1_Msk           (0x1ul << EPWM_CAPCTL_CAPINV1_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV1 Mask            */
+
+#define EPWM_CAPCTL_CAPINV2_Pos           (10)                                              /*!< EPWM_T::CAPCTL: CAPINV2 Position        */
+#define EPWM_CAPCTL_CAPINV2_Msk           (0x1ul << EPWM_CAPCTL_CAPINV2_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV2 Mask            */
+
+#define EPWM_CAPCTL_CAPINV3_Pos           (11)                                              /*!< EPWM_T::CAPCTL: CAPINV3 Position        */
+#define EPWM_CAPCTL_CAPINV3_Msk           (0x1ul << EPWM_CAPCTL_CAPINV3_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV3 Mask            */
+
+#define EPWM_CAPCTL_CAPINV4_Pos           (12)                                              /*!< EPWM_T::CAPCTL: CAPINV4 Position        */
+#define EPWM_CAPCTL_CAPINV4_Msk           (0x1ul << EPWM_CAPCTL_CAPINV4_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV4 Mask            */
+
+#define EPWM_CAPCTL_CAPINV5_Pos           (13)                                              /*!< EPWM_T::CAPCTL: CAPINV5 Position        */
+#define EPWM_CAPCTL_CAPINV5_Msk           (0x1ul << EPWM_CAPCTL_CAPINV5_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV5 Mask            */
+
+#define EPWM_CAPCTL_RCRLDEN0_Pos          (16)                                              /*!< EPWM_T::CAPCTL: RCRLDEN0 Position       */
+#define EPWM_CAPCTL_RCRLDEN0_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN1_Pos          (17)                                              /*!< EPWM_T::CAPCTL: RCRLDEN1 Position       */
+#define EPWM_CAPCTL_RCRLDEN1_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN2_Pos          (18)                                              /*!< EPWM_T::CAPCTL: RCRLDEN2 Position       */
+#define EPWM_CAPCTL_RCRLDEN2_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN3_Pos          (19)                                              /*!< EPWM_T::CAPCTL: RCRLDEN3 Position       */
+#define EPWM_CAPCTL_RCRLDEN3_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN4_Pos          (20)                                              /*!< EPWM_T::CAPCTL: RCRLDEN4 Position       */
+#define EPWM_CAPCTL_RCRLDEN4_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN5_Pos          (21)                                              /*!< EPWM_T::CAPCTL: RCRLDEN5 Position       */
+#define EPWM_CAPCTL_RCRLDEN5_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN0_Pos          (24)                                              /*!< EPWM_T::CAPCTL: FCRLDEN0 Position       */
+#define EPWM_CAPCTL_FCRLDEN0_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN1_Pos          (25)                                              /*!< EPWM_T::CAPCTL: FCRLDEN1 Position       */
+#define EPWM_CAPCTL_FCRLDEN1_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN2_Pos          (26)                                              /*!< EPWM_T::CAPCTL: FCRLDEN2 Position       */
+#define EPWM_CAPCTL_FCRLDEN2_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN3_Pos          (27)                                              /*!< EPWM_T::CAPCTL: FCRLDEN3 Position       */
+#define EPWM_CAPCTL_FCRLDEN3_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN4_Pos          (28)                                              /*!< EPWM_T::CAPCTL: FCRLDEN4 Position       */
+#define EPWM_CAPCTL_FCRLDEN4_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN5_Pos          (29)                                              /*!< EPWM_T::CAPCTL: FCRLDEN5 Position       */
+#define EPWM_CAPCTL_FCRLDEN5_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV0_Pos          (0)                                               /*!< EPWM_T::CAPSTS: CRLIFOV0 Position       */
+#define EPWM_CAPSTS_CRLIFOV0_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV1_Pos          (1)                                               /*!< EPWM_T::CAPSTS: CRLIFOV1 Position       */
+#define EPWM_CAPSTS_CRLIFOV1_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV2_Pos          (2)                                               /*!< EPWM_T::CAPSTS: CRLIFOV2 Position       */
+#define EPWM_CAPSTS_CRLIFOV2_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV3_Pos          (3)                                               /*!< EPWM_T::CAPSTS: CRLIFOV3 Position       */
+#define EPWM_CAPSTS_CRLIFOV3_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV4_Pos          (4)                                               /*!< EPWM_T::CAPSTS: CRLIFOV4 Position       */
+#define EPWM_CAPSTS_CRLIFOV4_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV5_Pos          (5)                                               /*!< EPWM_T::CAPSTS: CRLIFOV5 Position       */
+#define EPWM_CAPSTS_CRLIFOV5_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV0_Pos          (8)                                               /*!< EPWM_T::CAPSTS: CFLIFOV0 Position       */
+#define EPWM_CAPSTS_CFLIFOV0_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV1_Pos          (9)                                               /*!< EPWM_T::CAPSTS: CFLIFOV1 Position       */
+#define EPWM_CAPSTS_CFLIFOV1_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV2_Pos          (10)                                              /*!< EPWM_T::CAPSTS: CFLIFOV2 Position       */
+#define EPWM_CAPSTS_CFLIFOV2_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV3_Pos          (11)                                              /*!< EPWM_T::CAPSTS: CFLIFOV3 Position       */
+#define EPWM_CAPSTS_CFLIFOV3_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV4_Pos          (12)                                              /*!< EPWM_T::CAPSTS: CFLIFOV4 Position       */
+#define EPWM_CAPSTS_CFLIFOV4_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV5_Pos          (13)                                              /*!< EPWM_T::CAPSTS: CFLIFOV5 Position       */
+#define EPWM_CAPSTS_CFLIFOV5_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask           */
+
+#define EPWM_RCAPDAT0_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT0: RCAPDAT Position      */
+#define EPWM_RCAPDAT0_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT0_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT0: FCAPDAT Position      */
+#define EPWM_FCAPDAT0_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT1_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT1: RCAPDAT Position      */
+#define EPWM_RCAPDAT1_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT1_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT1: FCAPDAT Position      */
+#define EPWM_FCAPDAT1_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT2_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT2: RCAPDAT Position      */
+#define EPWM_RCAPDAT2_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT2_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT2: FCAPDAT Position      */
+#define EPWM_FCAPDAT2_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT3_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT3: RCAPDAT Position      */
+#define EPWM_RCAPDAT3_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT3_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT3: FCAPDAT Position      */
+#define EPWM_FCAPDAT3_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT4_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT4: RCAPDAT Position      */
+#define EPWM_RCAPDAT4_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT4_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT4: FCAPDAT Position      */
+#define EPWM_FCAPDAT4_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT5_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT5: RCAPDAT Position      */
+#define EPWM_RCAPDAT5_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT5_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT5: FCAPDAT Position      */
+#define EPWM_FCAPDAT5_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask          */
+
+#define EPWM_PDMACTL_CHEN0_1_Pos          (0)                                               /*!< EPWM_T::PDMACTL: CHEN0_1 Position       */
+#define EPWM_PDMACTL_CHEN0_1_Msk          (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos)                /*!< EPWM_T::PDMACTL: CHEN0_1 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD0_1_Pos        (1)                                               /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position     */
+#define EPWM_PDMACTL_CAPMOD0_1_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask         */
+
+#define EPWM_PDMACTL_CAPORD0_1_Pos        (3)                                               /*!< EPWM_T::PDMACTL: CAPORD0_1 Position     */
+#define EPWM_PDMACTL_CAPORD0_1_Msk        (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos)              /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask         */
+
+#define EPWM_PDMACTL_CHSEL0_1_Pos         (4)                                               /*!< EPWM_T::PDMACTL: CHSEL0_1 Position      */
+#define EPWM_PDMACTL_CHSEL0_1_Msk         (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos)               /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask          */
+
+#define EPWM_PDMACTL_CHEN2_3_Pos          (8)                                               /*!< EPWM_T::PDMACTL: CHEN2_3 Position       */
+#define EPWM_PDMACTL_CHEN2_3_Msk          (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos)                /*!< EPWM_T::PDMACTL: CHEN2_3 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD2_3_Pos        (9)                                               /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position     */
+#define EPWM_PDMACTL_CAPMOD2_3_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask         */
+
+#define EPWM_PDMACTL_CAPORD2_3_Pos        (11)                                              /*!< EPWM_T::PDMACTL: CAPORD2_3 Position     */
+#define EPWM_PDMACTL_CAPORD2_3_Msk        (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos)              /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask         */
+
+#define EPWM_PDMACTL_CHSEL2_3_Pos         (12)                                              /*!< EPWM_T::PDMACTL: CHSEL2_3 Position      */
+#define EPWM_PDMACTL_CHSEL2_3_Msk         (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos)               /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask          */
+
+#define EPWM_PDMACTL_CHEN4_5_Pos          (16)                                              /*!< EPWM_T::PDMACTL: CHEN4_5 Position       */
+#define EPWM_PDMACTL_CHEN4_5_Msk          (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos)                /*!< EPWM_T::PDMACTL: CHEN4_5 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD4_5_Pos        (17)                                              /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position     */
+#define EPWM_PDMACTL_CAPMOD4_5_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask         */
+
+#define EPWM_PDMACTL_CAPORD4_5_Pos        (19)                                              /*!< EPWM_T::PDMACTL: CAPORD4_5 Position     */
+#define EPWM_PDMACTL_CAPORD4_5_Msk        (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos)              /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask         */
+
+#define EPWM_PDMACTL_CHSEL4_5_Pos         (20)                                              /*!< EPWM_T::PDMACTL: CHSEL4_5 Position      */
+#define EPWM_PDMACTL_CHSEL4_5_Msk         (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos)               /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask          */
+
+#define EPWM_PDMACAP0_1_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP0_1: CAPBUF Position     */
+#define EPWM_PDMACAP0_1_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask         */
+
+#define EPWM_PDMACAP2_3_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP2_3: CAPBUF Position     */
+#define EPWM_PDMACAP2_3_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask         */
+
+#define EPWM_PDMACAP4_5_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP4_5: CAPBUF Position     */
+#define EPWM_PDMACAP4_5_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask         */
+
+#define EPWM_CAPIEN_CAPRIEN0_Pos          (0)                                               /*!< EPWM_T::CAPIEN: CAPRIEN0 Position       */
+#define EPWM_CAPIEN_CAPRIEN0_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN1_Pos          (1)                                               /*!< EPWM_T::CAPIEN: CAPRIEN1 Position       */
+#define EPWM_CAPIEN_CAPRIEN1_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN2_Pos          (2)                                               /*!< EPWM_T::CAPIEN: CAPRIEN2 Position       */
+#define EPWM_CAPIEN_CAPRIEN2_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN3_Pos          (3)                                               /*!< EPWM_T::CAPIEN: CAPRIEN3 Position       */
+#define EPWM_CAPIEN_CAPRIEN3_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN4_Pos          (4)                                               /*!< EPWM_T::CAPIEN: CAPRIEN4 Position       */
+#define EPWM_CAPIEN_CAPRIEN4_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN5_Pos          (5)                                               /*!< EPWM_T::CAPIEN: CAPRIEN5 Position       */
+#define EPWM_CAPIEN_CAPRIEN5_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN0_Pos          (8)                                               /*!< EPWM_T::CAPIEN: CAPFIEN0 Position       */
+#define EPWM_CAPIEN_CAPFIEN0_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN1_Pos          (9)                                               /*!< EPWM_T::CAPIEN: CAPFIEN1 Position       */
+#define EPWM_CAPIEN_CAPFIEN1_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN2_Pos          (10)                                              /*!< EPWM_T::CAPIEN: CAPFIEN2 Position       */
+#define EPWM_CAPIEN_CAPFIEN2_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN3_Pos          (11)                                              /*!< EPWM_T::CAPIEN: CAPFIEN3 Position       */
+#define EPWM_CAPIEN_CAPFIEN3_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN4_Pos          (12)                                              /*!< EPWM_T::CAPIEN: CAPFIEN4 Position       */
+#define EPWM_CAPIEN_CAPFIEN4_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN5_Pos          (13)                                              /*!< EPWM_T::CAPIEN: CAPFIEN5 Position       */
+#define EPWM_CAPIEN_CAPFIEN5_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask           */
+
+#define EPWM_CAPIF_CRLIF0_Pos             (0)                                               /*!< EPWM_T::CAPIF: CRLIF0 Position          */
+#define EPWM_CAPIF_CRLIF0_Msk             (0x1ul << EPWM_CAPIF_CRLIF0_Pos)                   /*!< EPWM_T::CAPIF: CRLIF0 Mask              */
+
+#define EPWM_CAPIF_CRLIF1_Pos             (1)                                               /*!< EPWM_T::CAPIF: CRLIF1 Position          */
+#define EPWM_CAPIF_CRLIF1_Msk             (0x1ul << EPWM_CAPIF_CRLIF1_Pos)                   /*!< EPWM_T::CAPIF: CRLIF1 Mask              */
+
+#define EPWM_CAPIF_CRLIF2_Pos             (2)                                               /*!< EPWM_T::CAPIF: CRLIF2 Position          */
+#define EPWM_CAPIF_CRLIF2_Msk             (0x1ul << EPWM_CAPIF_CRLIF2_Pos)                   /*!< EPWM_T::CAPIF: CRLIF2 Mask              */
+
+#define EPWM_CAPIF_CRLIF3_Pos             (3)                                               /*!< EPWM_T::CAPIF: CRLIF3 Position          */
+#define EPWM_CAPIF_CRLIF3_Msk             (0x1ul << EPWM_CAPIF_CRLIF3_Pos)                   /*!< EPWM_T::CAPIF: CRLIF3 Mask              */
+
+#define EPWM_CAPIF_CRLIF4_Pos             (4)                                               /*!< EPWM_T::CAPIF: CRLIF4 Position          */
+#define EPWM_CAPIF_CRLIF4_Msk             (0x1ul << EPWM_CAPIF_CRLIF4_Pos)                   /*!< EPWM_T::CAPIF: CRLIF4 Mask              */
+
+#define EPWM_CAPIF_CRLIF5_Pos             (5)                                               /*!< EPWM_T::CAPIF: CRLIF5 Position          */
+#define EPWM_CAPIF_CRLIF5_Msk             (0x1ul << EPWM_CAPIF_CRLIF5_Pos)                   /*!< EPWM_T::CAPIF: CRLIF5 Mask              */
+
+#define EPWM_CAPIF_CFLIF0_Pos             (8)                                               /*!< EPWM_T::CAPIF: CFLIF0 Position          */
+#define EPWM_CAPIF_CFLIF0_Msk             (0x1ul << EPWM_CAPIF_CFLIF0_Pos)                   /*!< EPWM_T::CAPIF: CFLIF0 Mask              */
+
+#define EPWM_CAPIF_CFLIF1_Pos             (9)                                               /*!< EPWM_T::CAPIF: CFLIF1 Position          */
+#define EPWM_CAPIF_CFLIF1_Msk             (0x1ul << EPWM_CAPIF_CFLIF1_Pos)                   /*!< EPWM_T::CAPIF: CFLIF1 Mask              */
+
+#define EPWM_CAPIF_CFLIF2_Pos             (10)                                              /*!< EPWM_T::CAPIF: CFLIF2 Position          */
+#define EPWM_CAPIF_CFLIF2_Msk             (0x1ul << EPWM_CAPIF_CFLIF2_Pos)                   /*!< EPWM_T::CAPIF: CFLIF2 Mask              */
+
+#define EPWM_CAPIF_CFLIF3_Pos             (11)                                              /*!< EPWM_T::CAPIF: CFLIF3 Position          */
+#define EPWM_CAPIF_CFLIF3_Msk             (0x1ul << EPWM_CAPIF_CFLIF3_Pos)                   /*!< EPWM_T::CAPIF: CFLIF3 Mask              */
+
+#define EPWM_CAPIF_CFLIF4_Pos             (12)                                              /*!< EPWM_T::CAPIF: CFLIF4 Position          */
+#define EPWM_CAPIF_CFLIF4_Msk             (0x1ul << EPWM_CAPIF_CFLIF4_Pos)                   /*!< EPWM_T::CAPIF: CFLIF4 Mask              */
+
+#define EPWM_CAPIF_CFLIF5_Pos             (13)                                              /*!< EPWM_T::CAPIF: CFLIF5 Position          */
+#define EPWM_CAPIF_CFLIF5_Msk             (0x1ul << EPWM_CAPIF_CFLIF5_Pos)                   /*!< EPWM_T::CAPIF: CFLIF5 Mask              */
+
+#define EPWM_PBUF0_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF0: PBUF Position            */
+#define EPWM_PBUF0_PBUF_Msk               (0xfffful << EPWM_PBUF0_PBUF_Pos)                  /*!< EPWM_T::PBUF0: PBUF Mask                */
+
+#define EPWM_PBUF1_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF1: PBUF Position            */
+#define EPWM_PBUF1_PBUF_Msk               (0xfffful << EPWM_PBUF1_PBUF_Pos)                  /*!< EPWM_T::PBUF1: PBUF Mask                */
+
+#define EPWM_PBUF2_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF2: PBUF Position            */
+#define EPWM_PBUF2_PBUF_Msk               (0xfffful << EPWM_PBUF2_PBUF_Pos)                  /*!< EPWM_T::PBUF2: PBUF Mask                */
+
+#define EPWM_PBUF3_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF3: PBUF Position            */
+#define EPWM_PBUF3_PBUF_Msk               (0xfffful << EPWM_PBUF3_PBUF_Pos)                  /*!< EPWM_T::PBUF3: PBUF Mask                */
+
+#define EPWM_PBUF4_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF4: PBUF Position            */
+#define EPWM_PBUF4_PBUF_Msk               (0xfffful << EPWM_PBUF4_PBUF_Pos)                  /*!< EPWM_T::PBUF4: PBUF Mask                */
+
+#define EPWM_PBUF5_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF5: PBUF Position            */
+#define EPWM_PBUF5_PBUF_Msk               (0xfffful << EPWM_PBUF5_PBUF_Pos)                  /*!< EPWM_T::PBUF5: PBUF Mask                */
+
+#define EPWM_CMPBUF0_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF0: CMPBUF Position        */
+#define EPWM_CMPBUF0_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF0: CMPBUF Mask            */
+
+#define EPWM_CMPBUF1_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF1: CMPBUF Position        */
+#define EPWM_CMPBUF1_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF1: CMPBUF Mask            */
+
+#define EPWM_CMPBUF2_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF2: CMPBUF Position        */
+#define EPWM_CMPBUF2_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF2: CMPBUF Mask            */
+
+#define EPWM_CMPBUF3_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF3: CMPBUF Position        */
+#define EPWM_CMPBUF3_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF3: CMPBUF Mask            */
+
+#define EPWM_CMPBUF4_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF4: CMPBUF Position        */
+#define EPWM_CMPBUF4_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF4: CMPBUF Mask            */
+
+#define EPWM_CMPBUF5_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF5: CMPBUF Position        */
+#define EPWM_CMPBUF5_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF5: CMPBUF Mask            */
+
+#define EPWM_CPSCBUF0_1_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position    */
+#define EPWM_CPSCBUF0_1_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask        */
+
+#define EPWM_CPSCBUF2_3_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position    */
+#define EPWM_CPSCBUF2_3_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask        */
+
+#define EPWM_CPSCBUF4_5_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position    */
+#define EPWM_CPSCBUF4_5_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask        */
+
+#define EPWM_FTCBUF0_1_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position    */
+#define EPWM_FTCBUF0_1_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask        */
+
+#define EPWM_FTCBUF2_3_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position    */
+#define EPWM_FTCBUF2_3_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask        */
+
+#define EPWM_FTCBUF4_5_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position    */
+#define EPWM_FTCBUF4_5_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask        */
+
+#define EPWM_FTCI_FTCMU0_Pos              (0)                                               /*!< EPWM_T::FTCI: FTCMU0 Position           */
+#define EPWM_FTCI_FTCMU0_Msk              (0x1ul << EPWM_FTCI_FTCMU0_Pos)                    /*!< EPWM_T::FTCI: FTCMU0 Mask               */
+
+#define EPWM_FTCI_FTCMU2_Pos              (1)                                               /*!< EPWM_T::FTCI: FTCMU2 Position           */
+#define EPWM_FTCI_FTCMU2_Msk              (0x1ul << EPWM_FTCI_FTCMU2_Pos)                    /*!< EPWM_T::FTCI: FTCMU2 Mask               */
+
+#define EPWM_FTCI_FTCMU4_Pos              (2)                                               /*!< EPWM_T::FTCI: FTCMU4 Position           */
+#define EPWM_FTCI_FTCMU4_Msk              (0x1ul << EPWM_FTCI_FTCMU4_Pos)                    /*!< EPWM_T::FTCI: FTCMU4 Mask               */
+
+#define EPWM_FTCI_FTCMD0_Pos              (8)                                               /*!< EPWM_T::FTCI: FTCMD0 Position           */
+#define EPWM_FTCI_FTCMD0_Msk              (0x1ul << EPWM_FTCI_FTCMD0_Pos)                    /*!< EPWM_T::FTCI: FTCMD0 Mask               */
+
+#define EPWM_FTCI_FTCMD2_Pos              (9)                                               /*!< EPWM_T::FTCI: FTCMD2 Position           */
+#define EPWM_FTCI_FTCMD2_Msk              (0x1ul << EPWM_FTCI_FTCMD2_Pos)                    /*!< EPWM_T::FTCI: FTCMD2 Mask               */
+
+#define EPWM_FTCI_FTCMD4_Pos              (10)                                              /*!< EPWM_T::FTCI: FTCMD4 Position           */
+#define EPWM_FTCI_FTCMD4_Msk              (0x1ul << EPWM_FTCI_FTCMD4_Pos)                    /*!< EPWM_T::FTCI: FTCMD4 Mask               */
+
+/**@}*/ /* EPWM_CONST */
+/**@}*/ /* end of EPWM register group */
+
+
+/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
+/**
+    @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
+    Memory Mapped Structure for BPWM Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var BPWM_T::CTL0
+     * Offset: 0x00  BPWM Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTRLD0    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[1]     |CTRLD1    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[2]     |CTRLD2    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[3]     |CTRLD3    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[4]     |CTRLD4    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[5]     |CTRLD5    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[16]    |IMMLDEN0  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[17]    |IMMLDEN1  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[18]    |IMMLDEN2  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[19]    |IMMLDEN3  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[20]    |IMMLDEN4  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[21]    |IMMLDEN5  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt Disabled.
+     * |        |          |1 = ICE debug mode counter halt Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects BPWM output.
+     * |        |          |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var BPWM_T::CTL1
+     * Offset: 0x04  BPWM Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CNTTYPE0  |BPWM Counter Behavior Type 0
+     * |        |          |Each bit n controls corresponding BPWM channel n.
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * @var BPWM_T::CLKSRC
+     * Offset: 0x10  BPWM Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |ECLKSRC0  |BPWM_CH01 External Clock Source Select
+     * |        |          |000 = BPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * @var BPWM_T::CLKPSC
+     * Offset: 0x14  BPWM Clock Prescale Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |BPWM Counter Clock Prescale
+     * |        |          |The clock of BPWM counter is decided by clock prescaler
+     * |        |          |Each BPWM pair share one BPWM counter clock prescaler
+     * |        |          |The clock of BPWM counter is divided by (CLKPSC+ 1)
+     * @var BPWM_T::CNTEN
+     * Offset: 0x20  BPWM Counter Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN0    |BPWM Counter 0 Enable Bit
+     * |        |          |0 = BPWM Counter and clock prescaler stop running.
+     * |        |          |1 = BPWM Counter and clock prescaler start running.
+     * @var BPWM_T::CNTCLR
+     * Offset: 0x24  BPWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR0   |Clear BPWM Counter Control Bit 0
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit BPWM counter to 0000H.
+     * @var BPWM_T::PERIOD
+     * Offset: 0x30  BPWM Period Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |BPWM Period Register
+     * |        |          |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |BPWM period time = (PERIOD+1) * BPWM_CLK period.
+     * |        |          |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |BPWM period time = 2 * PERIOD * BPWM_CLK period.
+     * @var BPWM_T::CMPDAT[6]
+     * Offset: 0x50  BPWM Comparator Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPDAT    |BPWM Comparator Register
+     * |        |          |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
+     * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
+     * @var BPWM_T::CNT
+     * Offset: 0x90  BPWM Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |BPWM Data Register (Read Only)
+     * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+     * |[16]    |DIRF      |BPWM Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is Down count.
+     * |        |          |1 = Counter is UP count.
+     * @var BPWM_T::WGCTL0
+     * Offset: 0xB0  BPWM Generation Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |ZPCTL0    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[3:2]   |ZPCTL1    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[5:4]   |ZPCTL2    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[7:6]   |ZPCTL3    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[9:8]   |ZPCTL4    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[11:10] |ZPCTL5    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[17:16] |PRDPCTL0  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[19:18] |PRDPCTL1  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[21:20] |PRDPCTL2  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[23:22] |PRDPCTL3  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[25:24] |PRDPCTL4  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[27:26] |PRDPCTL5  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * @var BPWM_T::WGCTL1
+     * Offset: 0xB4  BPWM Generation Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CMPUCTL0  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[3:2]   |CMPUCTL1  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[5:4]   |CMPUCTL2  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[7:6]   |CMPUCTL3  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[9:8]   |CMPUCTL4  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[11:10] |CMPUCTL5  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[17:16] |CMPDCTL0  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[19:18] |CMPDCTL1  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[21:20] |CMPDCTL2  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[23:22] |CMPDCTL3  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[25:24] |CMPDCTL4  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[27:26] |CMPDCTL5  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * @var BPWM_T::MSKEN
+     * Offset: 0xB8  BPWM Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[1]     |MSKEN1    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[2]     |MSKEN2    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[3]     |MSKEN3    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[4]     |MSKEN4    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[5]     |MSKEN5    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * @var BPWM_T::MSK
+     * Offset: 0xBC  BPWM Mask Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[1]     |MSKDAT1   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[2]     |MSKDAT2   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[3]     |MSKDAT3   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[4]     |MSKDAT4   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[5]     |MSKDAT5   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * @var BPWM_T::POLCTL
+     * Offset: 0xD4  BPWM Pin Polar Inverse Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[1]     |PINV1     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[2]     |PINV2     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[3]     |PINV3     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[4]     |PINV4     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[5]     |PINV5     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * @var BPWM_T::POEN
+     * Offset: 0xD8  BPWM Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[1]     |POEN1     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[2]     |POEN2     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[3]     |POEN3     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[4]     |POEN4     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[5]     |POEN5     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * @var BPWM_T::INTEN
+     * Offset: 0xE0  BPWM Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN0     |BPWM Zero Point Interrupt 0 Enable Bit
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |[8]     |PIEN0     |BPWM Period Point Interrupt 0 Enable Bit
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note: When up-down counter type period point means center point.
+     * |[16]    |CMPUIEN0  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[17]    |CMPUIEN1  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[18]    |CMPUIEN2  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[19]    |CMPUIEN3  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[20]    |CMPUIEN4  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[21]    |CMPUIEN5  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[24]    |CMPDIEN0  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[25]    |CMPDIEN1  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[26]    |CMPDIEN2  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[27]    |CMPDIEN3  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[28]    |CMPDIEN4  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[29]    |CMPDIEN5  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * @var BPWM_T::INTSTS
+     * Offset: 0xE8  BPWM Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF0      |BPWM Zero Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[8]     |PIF0      |BPWM Period Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
+     * |[16]    |CMPUIF0   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[17]    |CMPUIF1   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[18]    |CMPUIF2   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[19]    |CMPUIF3   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[20]    |CMPUIF4   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[21]    |CMPUIF5   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[24]    |CMPDIF0   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[25]    |CMPDIF1   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[26]    |CMPDIF2   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[27]    |CMPDIF3   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[28]    |CMPDIF4   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[29]    |CMPDIF5   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * @var BPWM_T::EADCTS0
+     * Offset: 0xF8  BPWM Trigger EADC Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL0   |BPWM_CH0 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN0    |BPWM_CH0 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL1   |BPWM_CH1 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN1    |BPWM_CH1 Trigger EADC Enable Bit
+     * |[19:16] |TRGSEL2   |BPWM_CH2 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[23]    |TRGEN2    |BPWM_CH2 Trigger EADC Enable Bit
+     * |[27:24] |TRGSEL3   |BPWM_CH3 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved.
+     * |[31]    |TRGEN3    |BPWM_CH3 Trigger EADC Enable Bit
+     * @var BPWM_T::EADCTS1
+     * Offset: 0xFC  BPWM Trigger EADC Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL4   |BPWM_CH4 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN4    |BPWM_CH4 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL5   |BPWM_CH5 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN5    |BPWM_CH5 Trigger EADC Enable Bit
+     * @var BPWM_T::SSCTL
+     * Offset: 0x110  BPWM Synchronous Start Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSEN0     |BPWM Synchronous Start Function 0 Enable Bit
+     * |        |          |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = BPWM synchronous start function Disabled.
+     * |        |          |1 = BPWM synchronous start function Enabled.
+     * |[9:8]   |SSRC      |BPWM Synchronous Start Source Select
+     * |        |          |00 = Synchronous start source come from PWM0.
+     * |        |          |01 = Synchronous start source come from PWM1.
+     * |        |          |10 = Synchronous start source come from BPWM0.
+     * |        |          |11 = Synchronous start source come from BPWM1.
+     * @var BPWM_T::SSTRG
+     * Offset: 0x114  BPWM Synchronous Start Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTSEN    |BPWM Counter Synchronous Start Enable Bit(Write Only)
+     * |        |          |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
+     * |        |          |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
+     * @var BPWM_T::STATUS
+     * Offset: 0x120  BPWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAX0   |Time-base Counter 0 Equal to 0xFFFF Latched Status
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[16]    |EADCTRG0  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[17]    |EADCTRG1  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[18]    |EADCTRG2  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[19]    |EADCTRG3  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[20]    |EADCTRG4  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[21]    |EADCTRG5  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * @var BPWM_T::CAPINEN
+     * Offset: 0x200  BPWM Capture Input Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPINEN0  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[1]     |CAPINEN1  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[2]     |CAPINEN2  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[3]     |CAPINEN3  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[4]     |CAPINEN4  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[5]     |CAPINEN5  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * @var BPWM_T::CAPCTL
+     * Offset: 0x204  BPWM Capture Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPEN0    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[1]     |CAPEN1    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[2]     |CAPEN2    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[3]     |CAPEN3    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[4]     |CAPEN4    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[5]     |CAPEN5    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[8]     |CAPINV0   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[9]     |CAPINV1   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[10]    |CAPINV2   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[11]    |CAPINV3   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[12]    |CAPINV4   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[13]    |CAPINV5   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[16]    |RCRLDEN0  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[17]    |RCRLDEN1  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[18]    |RCRLDEN2  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[19]    |RCRLDEN3  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[20]    |RCRLDEN4  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[21]    |RCRLDEN5  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[24]    |FCRLDEN0  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[25]    |FCRLDEN1  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[26]    |FCRLDEN2  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[27]    |FCRLDEN3  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[28]    |FCRLDEN4  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[29]    |FCRLDEN5  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * @var BPWM_T::CAPSTS
+     * Offset: 0x208  BPWM Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRIFOV0   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[1]     |CRIFOV1   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[2]     |CRIFOV2   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[3]     |CRIFOV3   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[4]     |CRIFOV4   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[5]     |CRIFOV5   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[8]     |CFIFOV0   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[9]     |CFIFOV1   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[10]    |CFIFOV2   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[11]    |CFIFOV3   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[12]    |CFIFOV4   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[13]    |CFIFOV5   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * @var BPWM_T::RCAPDAT0
+     * Offset: 0x20C  BPWM Rising Capture Data Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT0
+     * Offset: 0x210  BPWM Falling Capture Data Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::RCAPDAT1
+     * Offset: 0x214  BPWM Rising Capture Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT1
+     * Offset: 0x218  BPWM Falling Capture Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::RCAPDAT2
+     * Offset: 0x21C  BPWM Rising Capture Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT2
+     * Offset: 0x220  BPWM Falling Capture Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::RCAPDAT3
+     * Offset: 0x224  BPWM Rising Capture Data Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT3
+     * Offset: 0x228  BPWM Falling Capture Data Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::RCAPDAT4
+     * Offset: 0x22C  BPWM Rising Capture Data Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT4
+     * Offset: 0x230  BPWM Falling Capture Data Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::RCAPDAT5
+     * Offset: 0x234  BPWM Rising Capture Data Register 5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::FCAPDAT5
+     * Offset: 0x238  BPWM Falling Capture Data Register 5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BPWM_T::CAPIEN
+     * Offset: 0x250  BPWM Capture Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CAPRIENn  |BPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[13:8]  |CAPFIENn  |BPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * @var BPWM_T::CAPIF
+     * Offset: 0x254  BPWM Capture Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPRIF0   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[1]     |CAPRIF1   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[2]     |CAPRIF2   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[3]     |CAPRIF3   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[4]     |CAPRIF4   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[5]     |CAPRIF5   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[8]     |CAPFIF0   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[9]     |CAPFIF1   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[10]    |CAPFIF2   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[11]    |CAPFIF3   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[12]    |CAPFIF4   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[13]    |CAPFIF5   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * @var BPWM_T::PBUF
+     * Offset: 0x304  BPWM PERIOD Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |BPWM Period Buffer (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var BPWM_T::CMPBUF[6]
+     * Offset: 0x31C  BPWM CMPDAT 0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |BPWM Comparator Buffer (Read Only)
+     * |        |          |Used as CMP active register.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] BPWM Control Register 0                                          */
+    __IO uint32_t CTL1;                  /*!< [0x0004] BPWM Control Register 1                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CLKSRC;                /*!< [0x0010] BPWM Clock Source Register                                       */
+    __IO uint32_t CLKPSC;                /*!< [0x0014] BPWM Clock Prescale Register                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CNTEN;                 /*!< [0x0020] BPWM Counter Enable Register                                     */
+    __IO uint32_t CNTCLR;                /*!< [0x0024] BPWM Clear Counter Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PERIOD;                /*!< [0x0030] BPWM Period Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CMPDAT[6];             /*!< [0x0050] BPWM Comparator Register 0~5                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[10];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t CNT;                   /*!< [0x0090] BPWM Counter Register                                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WGCTL0;                /*!< [0x00b0] BPWM Generation Register 0                                       */
+    __IO uint32_t WGCTL1;                /*!< [0x00b4] BPWM Generation Register 1                                       */
+    __IO uint32_t MSKEN;                 /*!< [0x00b8] BPWM Mask Enable Register                                        */
+    __IO uint32_t MSK;                   /*!< [0x00bc] BPWM Mask Data Register                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE6[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t POLCTL;                /*!< [0x00d4] BPWM Pin Polar Inverse Register                                  */
+    __IO uint32_t POEN;                  /*!< [0x00d8] BPWM Output Enable Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE7[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t INTEN;                 /*!< [0x00e0] BPWM Interrupt Enable Register                                   */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE8[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t INTSTS;                /*!< [0x00e8] BPWM Interrupt Flag Register                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE9[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t EADCTS0;               /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0                       */
+    __IO uint32_t EADCTS1;               /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE10[4];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t SSCTL;                 /*!< [0x0110] BPWM Synchronous Start Control Register                          */
+    __O  uint32_t SSTRG;                 /*!< [0x0114] BPWM Synchronous Start Trigger Register                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE11[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t STATUS;                /*!< [0x0120] BPWM Status Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE12[55];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPINEN;               /*!< [0x0200] BPWM Capture Input Enable Register                               */
+    __IO uint32_t CAPCTL;                /*!< [0x0204] BPWM Capture Control Register                                    */
+    __I  uint32_t CAPSTS;                /*!< [0x0208] BPWM Capture Status Register                                     */
+    __I  uint32_t RCAPDAT0;              /*!< [0x020c] BPWM Rising Capture Data Register 0                              */
+    __I  uint32_t FCAPDAT0;              /*!< [0x0210] BPWM Falling Capture Data Register 0                             */
+    __I  uint32_t RCAPDAT1;              /*!< [0x0214] BPWM Rising Capture Data Register 1                              */
+    __I  uint32_t FCAPDAT1;              /*!< [0x0218] BPWM Falling Capture Data Register 1                             */
+    __I  uint32_t RCAPDAT2;              /*!< [0x021c] BPWM Rising Capture Data Register 2                              */
+    __I  uint32_t FCAPDAT2;              /*!< [0x0220] BPWM Falling Capture Data Register 2                             */
+    __I  uint32_t RCAPDAT3;              /*!< [0x0224] BPWM Rising Capture Data Register 3                              */
+    __I  uint32_t FCAPDAT3;              /*!< [0x0228] BPWM Falling Capture Data Register 3                             */
+    __I  uint32_t RCAPDAT4;              /*!< [0x022c] BPWM Rising Capture Data Register 4                              */
+    __I  uint32_t FCAPDAT4;              /*!< [0x0230] BPWM Falling Capture Data Register 4                             */
+    __I  uint32_t RCAPDAT5;              /*!< [0x0234] BPWM Rising Capture Data Register 5                              */
+    __I  uint32_t FCAPDAT5;              /*!< [0x0238] BPWM Falling Capture Data Register 5                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE13[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPIEN;                /*!< [0x0250] BPWM Capture Interrupt Enable Register                           */
+    __IO uint32_t CAPIF;                 /*!< [0x0254] BPWM Capture Interrupt Flag Register                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE14[43];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t PBUF;                  /*!< [0x0304] BPWM PERIOD Buffer                                               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE15[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t CMPBUF[6];             /*!< [0x031c] BPWM CMPDAT 0~5 Buffer                                           */
+
+} BPWM_T;
+
+/**
+    @addtogroup BPWM_CONST BPWM Bit Field Definition
+    Constant Definitions for BPWM Controller
+@{ */
+
+#define BPWM_CTL0_CTRLD0_Pos             (0)                                               /*!< BPWM_T::CTL0: CTRLD0 Position          */
+#define BPWM_CTL0_CTRLD0_Msk             (0x1ul << BPWM_CTL0_CTRLD0_Pos)                   /*!< BPWM_T::CTL0: CTRLD0 Mask              */
+
+#define BPWM_CTL0_CTRLD1_Pos             (1)                                               /*!< BPWM_T::CTL0: CTRLD1 Position          */
+#define BPWM_CTL0_CTRLD1_Msk             (0x1ul << BPWM_CTL0_CTRLD1_Pos)                   /*!< BPWM_T::CTL0: CTRLD1 Mask              */
+
+#define BPWM_CTL0_CTRLD2_Pos             (2)                                               /*!< BPWM_T::CTL0: CTRLD2 Position          */
+#define BPWM_CTL0_CTRLD2_Msk             (0x1ul << BPWM_CTL0_CTRLD2_Pos)                   /*!< BPWM_T::CTL0: CTRLD2 Mask              */
+
+#define BPWM_CTL0_CTRLD3_Pos             (3)                                               /*!< BPWM_T::CTL0: CTRLD3 Position          */
+#define BPWM_CTL0_CTRLD3_Msk             (0x1ul << BPWM_CTL0_CTRLD3_Pos)                   /*!< BPWM_T::CTL0: CTRLD3 Mask              */
+
+#define BPWM_CTL0_CTRLD4_Pos             (4)                                               /*!< BPWM_T::CTL0: CTRLD4 Position          */
+#define BPWM_CTL0_CTRLD4_Msk             (0x1ul << BPWM_CTL0_CTRLD4_Pos)                   /*!< BPWM_T::CTL0: CTRLD4 Mask              */
+
+#define BPWM_CTL0_CTRLD5_Pos             (5)                                               /*!< BPWM_T::CTL0: CTRLD5 Position          */
+#define BPWM_CTL0_CTRLD5_Msk             (0x1ul << BPWM_CTL0_CTRLD5_Pos)                   /*!< BPWM_T::CTL0: CTRLD5 Mask              */
+
+#define BPWM_CTL0_IMMLDEN0_Pos           (16)                                              /*!< BPWM_T::CTL0: IMMLDEN0 Position        */
+#define BPWM_CTL0_IMMLDEN0_Msk           (0x1ul << BPWM_CTL0_IMMLDEN0_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN0 Mask            */
+
+#define BPWM_CTL0_IMMLDEN1_Pos           (17)                                              /*!< BPWM_T::CTL0: IMMLDEN1 Position        */
+#define BPWM_CTL0_IMMLDEN1_Msk           (0x1ul << BPWM_CTL0_IMMLDEN1_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN1 Mask            */
+
+#define BPWM_CTL0_IMMLDEN2_Pos           (18)                                              /*!< BPWM_T::CTL0: IMMLDEN2 Position        */
+#define BPWM_CTL0_IMMLDEN2_Msk           (0x1ul << BPWM_CTL0_IMMLDEN2_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN2 Mask            */
+
+#define BPWM_CTL0_IMMLDEN3_Pos           (19)                                              /*!< BPWM_T::CTL0: IMMLDEN3 Position        */
+#define BPWM_CTL0_IMMLDEN3_Msk           (0x1ul << BPWM_CTL0_IMMLDEN3_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN3 Mask            */
+
+#define BPWM_CTL0_IMMLDEN4_Pos           (20)                                              /*!< BPWM_T::CTL0: IMMLDEN4 Position        */
+#define BPWM_CTL0_IMMLDEN4_Msk           (0x1ul << BPWM_CTL0_IMMLDEN4_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN4 Mask            */
+
+#define BPWM_CTL0_IMMLDEN5_Pos           (21)                                              /*!< BPWM_T::CTL0: IMMLDEN5 Position        */
+#define BPWM_CTL0_IMMLDEN5_Msk           (0x1ul << BPWM_CTL0_IMMLDEN5_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN5 Mask            */
+
+#define BPWM_CTL0_DBGHALT_Pos            (30)                                              /*!< BPWM_T::CTL0: DBGHALT Position         */
+#define BPWM_CTL0_DBGHALT_Msk            (0x1ul << BPWM_CTL0_DBGHALT_Pos)                  /*!< BPWM_T::CTL0: DBGHALT Mask             */
+
+#define BPWM_CTL0_DBGTRIOFF_Pos          (31)                                              /*!< BPWM_T::CTL0: DBGTRIOFF Position       */
+#define BPWM_CTL0_DBGTRIOFF_Msk          (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos)                /*!< BPWM_T::CTL0: DBGTRIOFF Mask           */
+
+#define BPWM_CTL1_CNTTYPE0_Pos           (0)                                               /*!< BPWM_T::CTL1: CNTTYPE0 Position        */
+#define BPWM_CTL1_CNTTYPE0_Msk           (0x3ul << BPWM_CTL1_CNTTYPE0_Pos)                 /*!< BPWM_T::CTL1: CNTTYPE0 Mask            */
+
+#define BPWM_CLKSRC_ECLKSRC0_Pos         (0)                                               /*!< BPWM_T::CLKSRC: ECLKSRC0 Position      */
+#define BPWM_CLKSRC_ECLKSRC0_Msk         (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos)               /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask          */
+
+#define BPWM_CLKPSC_CLKPSC_Pos           (0)                                               /*!< BPWM_T::CLKPSC: CLKPSC Position        */
+#define BPWM_CLKPSC_CLKPSC_Msk           (0xffful << BPWM_CLKPSC_CLKPSC_Pos)               /*!< BPWM_T::CLKPSC: CLKPSC Mask            */
+
+#define BPWM_CNTEN_CNTEN0_Pos            (0)                                               /*!< BPWM_T::CNTEN: CNTEN0 Position         */
+#define BPWM_CNTEN_CNTEN0_Msk            (0x1ul << BPWM_CNTEN_CNTEN0_Pos)                  /*!< BPWM_T::CNTEN: CNTEN0 Mask             */
+
+#define BPWM_CNTCLR_CNTCLR0_Pos          (0)                                               /*!< BPWM_T::CNTCLR: CNTCLR0 Position       */
+#define BPWM_CNTCLR_CNTCLR0_Msk          (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos)                /*!< BPWM_T::CNTCLR: CNTCLR0 Mask           */
+
+#define BPWM_PERIOD_PERIOD_Pos           (0)                                               /*!< BPWM_T::PERIOD: PERIOD Position        */
+#define BPWM_PERIOD_PERIOD_Msk           (0xfffful << BPWM_PERIOD_PERIOD_Pos)              /*!< BPWM_T::PERIOD: PERIOD Mask            */
+
+#define BPWM_CMPDAT0_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT0: CMPDAT Position       */
+#define BPWM_CMPDAT0_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT0: CMPDAT Mask           */
+
+#define BPWM_CMPDAT1_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT1: CMPDAT Position       */
+#define BPWM_CMPDAT1_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT1: CMPDAT Mask           */
+
+#define BPWM_CMPDAT2_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT2: CMPDAT Position       */
+#define BPWM_CMPDAT2_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT2: CMPDAT Mask           */
+
+#define BPWM_CMPDAT3_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT3: CMPDAT Position       */
+#define BPWM_CMPDAT3_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT3: CMPDAT Mask           */
+
+#define BPWM_CMPDAT4_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT4: CMPDAT Position       */
+#define BPWM_CMPDAT4_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT4: CMPDAT Mask           */
+
+#define BPWM_CMPDAT5_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT5: CMPDAT Position       */
+#define BPWM_CMPDAT5_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT5: CMPDAT Mask           */
+
+#define BPWM_CNT_CNT_Pos                 (0)                                               /*!< BPWM_T::CNT: CNT Position              */
+#define BPWM_CNT_CNT_Msk                 (0xfffful << BPWM_CNT_CNT_Pos)                    /*!< BPWM_T::CNT: CNT Mask                  */
+
+#define BPWM_CNT_DIRF_Pos                (16)                                              /*!< BPWM_T::CNT: DIRF Position             */
+#define BPWM_CNT_DIRF_Msk                (0x1ul << BPWM_CNT_DIRF_Pos)                      /*!< BPWM_T::CNT: DIRF Mask                 */
+
+#define BPWM_WGCTL0_ZPCTL0_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTL0 Position        */
+#define BPWM_WGCTL0_ZPCTL0_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL0 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL1_Pos           (2)                                               /*!< BPWM_T::WGCTL0: ZPCTL1 Position        */
+#define BPWM_WGCTL0_ZPCTL1_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL1 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL2_Pos           (4)                                               /*!< BPWM_T::WGCTL0: ZPCTL2 Position        */
+#define BPWM_WGCTL0_ZPCTL2_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL2 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL3_Pos           (6)                                               /*!< BPWM_T::WGCTL0: ZPCTL3 Position        */
+#define BPWM_WGCTL0_ZPCTL3_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL3 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL4_Pos           (8)                                               /*!< BPWM_T::WGCTL0: ZPCTL4 Position        */
+#define BPWM_WGCTL0_ZPCTL4_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL4 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL5_Pos           (10)                                              /*!< BPWM_T::WGCTL0: ZPCTL5 Position        */
+#define BPWM_WGCTL0_ZPCTL5_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL5 Mask            */
+
+#define BPWM_WGCTL0_ZPCTLn_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTLn Position        */
+#define BPWM_WGCTL0_ZPCTLn_Msk           (0xffful << BPWM_WGCTL0_ZPCTLn_Pos)               /*!< BPWM_T::WGCTL0: ZPCTLn Mask            */
+
+#define BPWM_WGCTL0_PRDPCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTL0 Position      */
+#define BPWM_WGCTL0_PRDPCTL0_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL0: PRDPCTL1 Position      */
+#define BPWM_WGCTL0_PRDPCTL1_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL0: PRDPCTL2 Position      */
+#define BPWM_WGCTL0_PRDPCTL2_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL0: PRDPCTL3 Position      */
+#define BPWM_WGCTL0_PRDPCTL3_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL0: PRDPCTL4 Position      */
+#define BPWM_WGCTL0_PRDPCTL4_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL0: PRDPCTL5 Position      */
+#define BPWM_WGCTL0_PRDPCTL5_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTLn Position      */
+#define BPWM_WGCTL0_PRDPCTLn_Msk         (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos)             /*!< BPWM_T::WGCTL0: PRDPCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL0_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTL0 Position      */
+#define BPWM_WGCTL1_CMPUCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL1_Pos         (2)                                               /*!< BPWM_T::WGCTL1: CMPUCTL1 Position      */
+#define BPWM_WGCTL1_CMPUCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL2_Pos         (4)                                               /*!< BPWM_T::WGCTL1: CMPUCTL2 Position      */
+#define BPWM_WGCTL1_CMPUCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL3_Pos         (6)                                               /*!< BPWM_T::WGCTL1: CMPUCTL3 Position      */
+#define BPWM_WGCTL1_CMPUCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL4_Pos         (8)                                               /*!< BPWM_T::WGCTL1: CMPUCTL4 Position      */
+#define BPWM_WGCTL1_CMPUCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL5_Pos         (10)                                              /*!< BPWM_T::WGCTL1: CMPUCTL5 Position      */
+#define BPWM_WGCTL1_CMPUCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTLn_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTLn Position      */
+#define BPWM_WGCTL1_CMPUCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPUCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTL0 Position      */
+#define BPWM_WGCTL1_CMPDCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL1: CMPDCTL1 Position      */
+#define BPWM_WGCTL1_CMPDCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL1: CMPDCTL2 Position      */
+#define BPWM_WGCTL1_CMPDCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL1: CMPDCTL3 Position      */
+#define BPWM_WGCTL1_CMPDCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL1: CMPDCTL4 Position      */
+#define BPWM_WGCTL1_CMPDCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL1: CMPDCTL5 Position      */
+#define BPWM_WGCTL1_CMPDCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTLn Position      */
+#define BPWM_WGCTL1_CMPDCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPDCTLn Mask          */
+
+#define BPWM_MSKEN_MSKEN0_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKEN0 Position         */
+#define BPWM_MSKEN_MSKEN0_Msk            (0x1ul << BPWM_MSKEN_MSKEN0_Pos)                  /*!< BPWM_T::MSKEN: MSKEN0 Mask             */
+
+#define BPWM_MSKEN_MSKEN1_Pos            (1)                                               /*!< BPWM_T::MSKEN: MSKEN1 Position         */
+#define BPWM_MSKEN_MSKEN1_Msk            (0x1ul << BPWM_MSKEN_MSKEN1_Pos)                  /*!< BPWM_T::MSKEN: MSKEN1 Mask             */
+
+#define BPWM_MSKEN_MSKEN2_Pos            (2)                                               /*!< BPWM_T::MSKEN: MSKEN2 Position         */
+#define BPWM_MSKEN_MSKEN2_Msk            (0x1ul << BPWM_MSKEN_MSKEN2_Pos)                  /*!< BPWM_T::MSKEN: MSKEN2 Mask             */
+
+#define BPWM_MSKEN_MSKEN3_Pos            (3)                                               /*!< BPWM_T::MSKEN: MSKEN3 Position         */
+#define BPWM_MSKEN_MSKEN3_Msk            (0x1ul << BPWM_MSKEN_MSKEN3_Pos)                  /*!< BPWM_T::MSKEN: MSKEN3 Mask             */
+
+#define BPWM_MSKEN_MSKEN4_Pos            (4)                                               /*!< BPWM_T::MSKEN: MSKEN4 Position         */
+#define BPWM_MSKEN_MSKEN4_Msk            (0x1ul << BPWM_MSKEN_MSKEN4_Pos)                  /*!< BPWM_T::MSKEN: MSKEN4 Mask             */
+
+#define BPWM_MSKEN_MSKEN5_Pos            (5)                                               /*!< BPWM_T::MSKEN: MSKEN5 Position         */
+#define BPWM_MSKEN_MSKEN5_Msk            (0x1ul << BPWM_MSKEN_MSKEN5_Pos)                  /*!< BPWM_T::MSKEN: MSKEN5 Mask             */
+
+#define BPWM_MSKEN_MSKENn_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKENn Position         */
+#define BPWM_MSKEN_MSKENn_Msk            (0x3ful << BPWM_MSKEN_MSKENn_Pos)                 /*!< BPWM_T::MSKEN: MSKENn Mask             */
+
+#define BPWM_MSK_MSKDAT0_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDAT0 Position          */
+#define BPWM_MSK_MSKDAT0_Msk             (0x1ul << BPWM_MSK_MSKDAT0_Pos)                   /*!< BPWM_T::MSK: MSKDAT0 Mask              */
+
+#define BPWM_MSK_MSKDAT1_Pos             (1)                                               /*!< BPWM_T::MSK: MSKDAT1 Position          */
+#define BPWM_MSK_MSKDAT1_Msk             (0x1ul << BPWM_MSK_MSKDAT1_Pos)                   /*!< BPWM_T::MSK: MSKDAT1 Mask              */
+
+#define BPWM_MSK_MSKDAT2_Pos             (2)                                               /*!< BPWM_T::MSK: MSKDAT2 Position          */
+#define BPWM_MSK_MSKDAT2_Msk             (0x1ul << BPWM_MSK_MSKDAT2_Pos)                   /*!< BPWM_T::MSK: MSKDAT2 Mask              */
+
+#define BPWM_MSK_MSKDAT3_Pos             (3)                                               /*!< BPWM_T::MSK: MSKDAT3 Position          */
+#define BPWM_MSK_MSKDAT3_Msk             (0x1ul << BPWM_MSK_MSKDAT3_Pos)                   /*!< BPWM_T::MSK: MSKDAT3 Mask              */
+
+#define BPWM_MSK_MSKDAT4_Pos             (4)                                               /*!< BPWM_T::MSK: MSKDAT4 Position          */
+#define BPWM_MSK_MSKDAT4_Msk             (0x1ul << BPWM_MSK_MSKDAT4_Pos)                   /*!< BPWM_T::MSK: MSKDAT4 Mask              */
+
+#define BPWM_MSK_MSKDAT5_Pos             (5)                                               /*!< BPWM_T::MSK: MSKDAT5 Position          */
+#define BPWM_MSK_MSKDAT5_Msk             (0x1ul << BPWM_MSK_MSKDAT5_Pos)                   /*!< BPWM_T::MSK: MSKDAT5 Mask              */
+
+#define BPWM_MSK_MSKDATn_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDATn Position          */
+#define BPWM_MSK_MSKDATn_Msk             (0x3ful << BPWM_MSK_MSKDATn_Pos)                  /*!< BPWM_T::MSK: MSKDATn Mask              */
+
+#define BPWM_POLCTL_PINV0_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINV0 Position         */
+#define BPWM_POLCTL_PINV0_Msk            (0x1ul << BPWM_POLCTL_PINV0_Pos)                  /*!< BPWM_T::POLCTL: PINV0 Mask             */
+
+#define BPWM_POLCTL_PINV1_Pos            (1)                                               /*!< BPWM_T::POLCTL: PINV1 Position         */
+#define BPWM_POLCTL_PINV1_Msk            (0x1ul << BPWM_POLCTL_PINV1_Pos)                  /*!< BPWM_T::POLCTL: PINV1 Mask             */
+
+#define BPWM_POLCTL_PINV2_Pos            (2)                                               /*!< BPWM_T::POLCTL: PINV2 Position         */
+#define BPWM_POLCTL_PINV2_Msk            (0x1ul << BPWM_POLCTL_PINV2_Pos)                  /*!< BPWM_T::POLCTL: PINV2 Mask             */
+
+#define BPWM_POLCTL_PINV3_Pos            (3)                                               /*!< BPWM_T::POLCTL: PINV3 Position         */
+#define BPWM_POLCTL_PINV3_Msk            (0x1ul << BPWM_POLCTL_PINV3_Pos)                  /*!< BPWM_T::POLCTL: PINV3 Mask             */
+
+#define BPWM_POLCTL_PINV4_Pos            (4)                                               /*!< BPWM_T::POLCTL: PINV4 Position         */
+#define BPWM_POLCTL_PINV4_Msk            (0x1ul << BPWM_POLCTL_PINV4_Pos)                  /*!< BPWM_T::POLCTL: PINV4 Mask             */
+
+#define BPWM_POLCTL_PINV5_Pos            (5)                                               /*!< BPWM_T::POLCTL: PINV5 Position         */
+#define BPWM_POLCTL_PINV5_Msk            (0x1ul << BPWM_POLCTL_PINV5_Pos)                  /*!< BPWM_T::POLCTL: PINV5 Mask             */
+
+#define BPWM_POLCTL_PINVn_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINVn Position         */
+#define BPWM_POLCTL_PINVn_Msk            (0x3ful << BPWM_POLCTL_PINVn_Pos)                 /*!< BPWM_T::POLCTL: PINVn Mask             */
+
+#define BPWM_POEN_POEN0_Pos              (0)                                               /*!< BPWM_T::POEN: POEN0 Position           */
+#define BPWM_POEN_POEN0_Msk              (0x1ul << BPWM_POEN_POEN0_Pos)                    /*!< BPWM_T::POEN: POEN0 Mask               */
+
+#define BPWM_POEN_POEN1_Pos              (1)                                               /*!< BPWM_T::POEN: POEN1 Position           */
+#define BPWM_POEN_POEN1_Msk              (0x1ul << BPWM_POEN_POEN1_Pos)                    /*!< BPWM_T::POEN: POEN1 Mask               */
+
+#define BPWM_POEN_POEN2_Pos              (2)                                               /*!< BPWM_T::POEN: POEN2 Position           */
+#define BPWM_POEN_POEN2_Msk              (0x1ul << BPWM_POEN_POEN2_Pos)                    /*!< BPWM_T::POEN: POEN2 Mask               */
+
+#define BPWM_POEN_POEN3_Pos              (3)                                               /*!< BPWM_T::POEN: POEN3 Position           */
+#define BPWM_POEN_POEN3_Msk              (0x1ul << BPWM_POEN_POEN3_Pos)                    /*!< BPWM_T::POEN: POEN3 Mask               */
+
+#define BPWM_POEN_POEN4_Pos              (4)                                               /*!< BPWM_T::POEN: POEN4 Position           */
+#define BPWM_POEN_POEN4_Msk              (0x1ul << BPWM_POEN_POEN4_Pos)                    /*!< BPWM_T::POEN: POEN4 Mask               */
+
+#define BPWM_POEN_POEN5_Pos              (5)                                               /*!< BPWM_T::POEN: POEN5 Position           */
+#define BPWM_POEN_POEN5_Msk              (0x1ul << BPWM_POEN_POEN5_Pos)                    /*!< BPWM_T::POEN: POEN5 Mask               */
+
+#define BPWM_POEN_POENn_Pos              (0)                                               /*!< BPWM_T::POEN: POENn Position           */
+#define BPWM_POEN_POENn_Msk              (0x3ful << BPWM_POEN_POENn_Pos)                   /*!< BPWM_T::POEN: POENn Mask               */
+
+#define BPWM_INTEN_ZIEN0_Pos             (0)                                               /*!< BPWM_T::INTEN: ZIEN0 Position          */
+#define BPWM_INTEN_ZIEN0_Msk             (0x1ul << BPWM_INTEN_ZIEN0_Pos)                   /*!< BPWM_T::INTEN: ZIEN0 Mask              */
+
+#define BPWM_INTEN_PIEN0_Pos             (8)                                               /*!< BPWM_T::INTEN: PIEN0 Position          */
+#define BPWM_INTEN_PIEN0_Msk             (0x1ul << BPWM_INTEN_PIEN0_Pos)                   /*!< BPWM_T::INTEN: PIEN0 Mask              */
+
+#define BPWM_INTEN_CMPUIEN0_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIEN0 Position       */
+#define BPWM_INTEN_CMPUIEN0_Msk          (0x1ul << BPWM_INTEN_CMPUIEN0_Pos)                /*!< BPWM_T::INTEN: CMPUIEN0 Mask           */
+
+#define BPWM_INTEN_CMPUIEN1_Pos          (17)                                              /*!< BPWM_T::INTEN: CMPUIEN1 Position       */
+#define BPWM_INTEN_CMPUIEN1_Msk          (0x1ul << BPWM_INTEN_CMPUIEN1_Pos)                /*!< BPWM_T::INTEN: CMPUIEN1 Mask           */
+
+#define BPWM_INTEN_CMPUIEN2_Pos          (18)                                              /*!< BPWM_T::INTEN: CMPUIEN2 Position       */
+#define BPWM_INTEN_CMPUIEN2_Msk          (0x1ul << BPWM_INTEN_CMPUIEN2_Pos)                /*!< BPWM_T::INTEN: CMPUIEN2 Mask           */
+
+#define BPWM_INTEN_CMPUIEN3_Pos          (19)                                              /*!< BPWM_T::INTEN: CMPUIEN3 Position       */
+#define BPWM_INTEN_CMPUIEN3_Msk          (0x1ul << BPWM_INTEN_CMPUIEN3_Pos)                /*!< BPWM_T::INTEN: CMPUIEN3 Mask           */
+
+#define BPWM_INTEN_CMPUIEN4_Pos          (20)                                              /*!< BPWM_T::INTEN: CMPUIEN4 Position       */
+#define BPWM_INTEN_CMPUIEN4_Msk          (0x1ul << BPWM_INTEN_CMPUIEN4_Pos)                /*!< BPWM_T::INTEN: CMPUIEN4 Mask           */
+
+#define BPWM_INTEN_CMPUIEN5_Pos          (21)                                              /*!< BPWM_T::INTEN: CMPUIEN5 Position       */
+#define BPWM_INTEN_CMPUIEN5_Msk          (0x1ul << BPWM_INTEN_CMPUIEN5_Pos)                /*!< BPWM_T::INTEN: CMPUIEN5 Mask           */
+
+#define BPWM_INTEN_CMPUIENn_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIENn Position       */
+#define BPWM_INTEN_CMPUIENn_Msk          (0x3ful << BPWM_INTEN_CMPUIENn_Pos)               /*!< BPWM_T::INTEN: CMPUIENn Mask           */
+
+#define BPWM_INTEN_CMPDIEN0_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIEN0 Position       */
+#define BPWM_INTEN_CMPDIEN0_Msk          (0x1ul << BPWM_INTEN_CMPDIEN0_Pos)                /*!< BPWM_T::INTEN: CMPDIEN0 Mask           */
+
+#define BPWM_INTEN_CMPDIEN1_Pos          (25)                                              /*!< BPWM_T::INTEN: CMPDIEN1 Position       */
+#define BPWM_INTEN_CMPDIEN1_Msk          (0x1ul << BPWM_INTEN_CMPDIEN1_Pos)                /*!< BPWM_T::INTEN: CMPDIEN1 Mask           */
+
+#define BPWM_INTEN_CMPDIEN2_Pos          (26)                                              /*!< BPWM_T::INTEN: CMPDIEN2 Position       */
+#define BPWM_INTEN_CMPDIEN2_Msk          (0x1ul << BPWM_INTEN_CMPDIEN2_Pos)                /*!< BPWM_T::INTEN: CMPDIEN2 Mask           */
+
+#define BPWM_INTEN_CMPDIEN3_Pos          (27)                                              /*!< BPWM_T::INTEN: CMPDIEN3 Position       */
+#define BPWM_INTEN_CMPDIEN3_Msk          (0x1ul << BPWM_INTEN_CMPDIEN3_Pos)                /*!< BPWM_T::INTEN: CMPDIEN3 Mask           */
+
+#define BPWM_INTEN_CMPDIEN4_Pos          (28)                                              /*!< BPWM_T::INTEN: CMPDIEN4 Position       */
+#define BPWM_INTEN_CMPDIEN4_Msk          (0x1ul << BPWM_INTEN_CMPDIEN4_Pos)                /*!< BPWM_T::INTEN: CMPDIEN4 Mask           */
+
+#define BPWM_INTEN_CMPDIEN5_Pos          (29)                                              /*!< BPWM_T::INTEN: CMPDIEN5 Position       */
+#define BPWM_INTEN_CMPDIEN5_Msk          (0x1ul << BPWM_INTEN_CMPDIEN5_Pos)                /*!< BPWM_T::INTEN: CMPDIEN5 Mask           */
+
+#define BPWM_INTEN_CMPDIENn_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIENn Position       */
+#define BPWM_INTEN_CMPDIENn_Msk          (0x3ful << BPWM_INTEN_CMPDIENn_Pos)               /*!< BPWM_T::INTEN: CMPDIENn Mask           */
+
+#define BPWM_INTSTS_ZIF0_Pos             (0)                                               /*!< BPWM_T::INTSTS: ZIF0 Position          */
+#define BPWM_INTSTS_ZIF0_Msk             (0x1ul << BPWM_INTSTS_ZIF0_Pos)                   /*!< BPWM_T::INTSTS: ZIF0 Mask              */
+
+#define BPWM_INTSTS_PIF0_Pos             (8)                                               /*!< BPWM_T::INTSTS: PIF0 Position          */
+#define BPWM_INTSTS_PIF0_Msk             (0x1ul << BPWM_INTSTS_PIF0_Pos)                   /*!< BPWM_T::INTSTS: PIF0 Mask              */
+
+#define BPWM_INTSTS_CMPUIF0_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIF0 Position       */
+#define BPWM_INTSTS_CMPUIF0_Msk          (0x1ul << BPWM_INTSTS_CMPUIF0_Pos)                /*!< BPWM_T::INTSTS: CMPUIF0 Mask           */
+
+#define BPWM_INTSTS_CMPUIF1_Pos          (17)                                              /*!< BPWM_T::INTSTS: CMPUIF1 Position       */
+#define BPWM_INTSTS_CMPUIF1_Msk          (0x1ul << BPWM_INTSTS_CMPUIF1_Pos)                /*!< BPWM_T::INTSTS: CMPUIF1 Mask           */
+
+#define BPWM_INTSTS_CMPUIF2_Pos          (18)                                              /*!< BPWM_T::INTSTS: CMPUIF2 Position       */
+#define BPWM_INTSTS_CMPUIF2_Msk          (0x1ul << BPWM_INTSTS_CMPUIF2_Pos)                /*!< BPWM_T::INTSTS: CMPUIF2 Mask           */
+
+#define BPWM_INTSTS_CMPUIF3_Pos          (19)                                              /*!< BPWM_T::INTSTS: CMPUIF3 Position       */
+#define BPWM_INTSTS_CMPUIF3_Msk          (0x1ul << BPWM_INTSTS_CMPUIF3_Pos)                /*!< BPWM_T::INTSTS: CMPUIF3 Mask           */
+
+#define BPWM_INTSTS_CMPUIF4_Pos          (20)                                              /*!< BPWM_T::INTSTS: CMPUIF4 Position       */
+#define BPWM_INTSTS_CMPUIF4_Msk          (0x1ul << BPWM_INTSTS_CMPUIF4_Pos)                /*!< BPWM_T::INTSTS: CMPUIF4 Mask           */
+
+#define BPWM_INTSTS_CMPUIF5_Pos          (21)                                              /*!< BPWM_T::INTSTS: CMPUIF5 Position       */
+#define BPWM_INTSTS_CMPUIF5_Msk          (0x1ul << BPWM_INTSTS_CMPUIF5_Pos)                /*!< BPWM_T::INTSTS: CMPUIF5 Mask           */
+
+#define BPWM_INTSTS_CMPUIFn_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIFn Position       */
+#define BPWM_INTSTS_CMPUIFn_Msk          (0x3ful << BPWM_INTSTS_CMPUIFn_Pos)               /*!< BPWM_T::INTSTS: CMPUIFn Mask           */
+
+#define BPWM_INTSTS_CMPDIF0_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIF0 Position       */
+#define BPWM_INTSTS_CMPDIF0_Msk          (0x1ul << BPWM_INTSTS_CMPDIF0_Pos)                /*!< BPWM_T::INTSTS: CMPDIF0 Mask           */
+
+#define BPWM_INTSTS_CMPDIF1_Pos          (25)                                              /*!< BPWM_T::INTSTS: CMPDIF1 Position       */
+#define BPWM_INTSTS_CMPDIF1_Msk          (0x1ul << BPWM_INTSTS_CMPDIF1_Pos)                /*!< BPWM_T::INTSTS: CMPDIF1 Mask           */
+
+#define BPWM_INTSTS_CMPDIF2_Pos          (26)                                              /*!< BPWM_T::INTSTS: CMPDIF2 Position       */
+#define BPWM_INTSTS_CMPDIF2_Msk          (0x1ul << BPWM_INTSTS_CMPDIF2_Pos)                /*!< BPWM_T::INTSTS: CMPDIF2 Mask           */
+
+#define BPWM_INTSTS_CMPDIF3_Pos          (27)                                              /*!< BPWM_T::INTSTS: CMPDIF3 Position       */
+#define BPWM_INTSTS_CMPDIF3_Msk          (0x1ul << BPWM_INTSTS_CMPDIF3_Pos)                /*!< BPWM_T::INTSTS: CMPDIF3 Mask           */
+
+#define BPWM_INTSTS_CMPDIF4_Pos          (28)                                              /*!< BPWM_T::INTSTS: CMPDIF4 Position       */
+#define BPWM_INTSTS_CMPDIF4_Msk          (0x1ul << BPWM_INTSTS_CMPDIF4_Pos)                /*!< BPWM_T::INTSTS: CMPDIF4 Mask           */
+
+#define BPWM_INTSTS_CMPDIF5_Pos          (29)                                              /*!< BPWM_T::INTSTS: CMPDIF5 Position       */
+#define BPWM_INTSTS_CMPDIF5_Msk          (0x1ul << BPWM_INTSTS_CMPDIF5_Pos)                /*!< BPWM_T::INTSTS: CMPDIF5 Mask           */
+
+#define BPWM_INTSTS_CMPDIFn_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIFn Position       */
+#define BPWM_INTSTS_CMPDIFn_Msk          (0x3ful << BPWM_INTSTS_CMPDIFn_Pos)               /*!< BPWM_T::INTSTS: CMPDIFn Mask           */
+
+#define BPWM_EADCTS0_TRGSEL0_Pos         (0)                                               /*!< BPWM_T::EADCTS0: TRGSEL0 Position      */
+#define BPWM_EADCTS0_TRGSEL0_Msk         (0xful << BPWM_EADCTS0_TRGSEL0_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL0 Mask          */
+
+#define BPWM_EADCTS0_TRGEN0_Pos          (7)                                               /*!< BPWM_T::EADCTS0: TRGEN0 Position       */
+#define BPWM_EADCTS0_TRGEN0_Msk          (0x1ul << BPWM_EADCTS0_TRGEN0_Pos)                /*!< BPWM_T::EADCTS0: TRGEN0 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL1_Pos         (8)                                               /*!< BPWM_T::EADCTS0: TRGSEL1 Position      */
+#define BPWM_EADCTS0_TRGSEL1_Msk         (0xful << BPWM_EADCTS0_TRGSEL1_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL1 Mask          */
+
+#define BPWM_EADCTS0_TRGEN1_Pos          (15)                                              /*!< BPWM_T::EADCTS0: TRGEN1 Position       */
+#define BPWM_EADCTS0_TRGEN1_Msk          (0x1ul << BPWM_EADCTS0_TRGEN1_Pos)                /*!< BPWM_T::EADCTS0: TRGEN1 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL2_Pos         (16)                                              /*!< BPWM_T::EADCTS0: TRGSEL2 Position      */
+#define BPWM_EADCTS0_TRGSEL2_Msk         (0xful << BPWM_EADCTS0_TRGSEL2_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL2 Mask          */
+
+#define BPWM_EADCTS0_TRGEN2_Pos          (23)                                              /*!< BPWM_T::EADCTS0: TRGEN2 Position       */
+#define BPWM_EADCTS0_TRGEN2_Msk          (0x1ul << BPWM_EADCTS0_TRGEN2_Pos)                /*!< BPWM_T::EADCTS0: TRGEN2 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL3_Pos         (24)                                              /*!< BPWM_T::EADCTS0: TRGSEL3 Position      */
+#define BPWM_EADCTS0_TRGSEL3_Msk         (0xful << BPWM_EADCTS0_TRGSEL3_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL3 Mask          */
+
+#define BPWM_EADCTS0_TRGEN3_Pos          (31)                                              /*!< BPWM_T::EADCTS0: TRGEN3 Position       */
+#define BPWM_EADCTS0_TRGEN3_Msk          (0x1ul << BPWM_EADCTS0_TRGEN3_Pos)                /*!< BPWM_T::EADCTS0: TRGEN3 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL4_Pos         (0)                                               /*!< BPWM_T::EADCTS1: TRGSEL4 Position      */
+#define BPWM_EADCTS1_TRGSEL4_Msk         (0xful << BPWM_EADCTS1_TRGSEL4_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL4 Mask          */
+
+#define BPWM_EADCTS1_TRGEN4_Pos          (7)                                               /*!< BPWM_T::EADCTS1: TRGEN4 Position       */
+#define BPWM_EADCTS1_TRGEN4_Msk          (0x1ul << BPWM_EADCTS1_TRGEN4_Pos)                /*!< BPWM_T::EADCTS1: TRGEN4 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL5_Pos         (8)                                               /*!< BPWM_T::EADCTS1: TRGSEL5 Position      */
+#define BPWM_EADCTS1_TRGSEL5_Msk         (0xful << BPWM_EADCTS1_TRGSEL5_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL5 Mask          */
+
+#define BPWM_EADCTS1_TRGEN5_Pos          (15)                                              /*!< BPWM_T::EADCTS1: TRGEN5 Position       */
+#define BPWM_EADCTS1_TRGEN5_Msk          (0x1ul << BPWM_EADCTS1_TRGEN5_Pos)                /*!< BPWM_T::EADCTS1: TRGEN5 Mask           */
+
+#define BPWM_SSCTL_SSEN0_Pos             (0)                                               /*!< BPWM_T::SSCTL: SSEN0 Position          */
+#define BPWM_SSCTL_SSEN0_Msk             (0x1ul << BPWM_SSCTL_SSEN0_Pos)                   /*!< BPWM_T::SSCTL: SSEN0 Mask              */
+
+#define BPWM_SSCTL_SSRC_Pos              (8)                                               /*!< BPWM_T::SSCTL: SSRC Position           */
+#define BPWM_SSCTL_SSRC_Msk              (0x3ul << BPWM_SSCTL_SSRC_Pos)                    /*!< BPWM_T::SSCTL: SSRC Mask               */
+
+#define BPWM_SSTRG_CNTSEN_Pos            (0)                                               /*!< BPWM_T::SSTRG: CNTSEN Position         */
+#define BPWM_SSTRG_CNTSEN_Msk            (0x1ul << BPWM_SSTRG_CNTSEN_Pos)                  /*!< BPWM_T::SSTRG: CNTSEN Mask             */
+
+#define BPWM_STATUS_CNTMAX0_Pos          (0)                                               /*!< BPWM_T::STATUS: CNTMAX0 Position       */
+#define BPWM_STATUS_CNTMAX0_Msk          (0x1ul << BPWM_STATUS_CNTMAX0_Pos)                /*!< BPWM_T::STATUS: CNTMAX0 Mask           */
+
+#define BPWM_STATUS_EADCTRG0_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRG0 Position      */
+#define BPWM_STATUS_EADCTRG0_Msk         (0x1ul << BPWM_STATUS_EADCTRG0_Pos)               /*!< BPWM_T::STATUS: EADCTRG0 Mask          */
+
+#define BPWM_STATUS_EADCTRG1_Pos         (17)                                              /*!< BPWM_T::STATUS: EADCTRG1 Position      */
+#define BPWM_STATUS_EADCTRG1_Msk         (0x1ul << BPWM_STATUS_EADCTRG1_Pos)               /*!< BPWM_T::STATUS: EADCTRG1 Mask          */
+
+#define BPWM_STATUS_EADCTRG2_Pos         (18)                                              /*!< BPWM_T::STATUS: EADCTRG2 Position      */
+#define BPWM_STATUS_EADCTRG2_Msk         (0x1ul << BPWM_STATUS_EADCTRG2_Pos)               /*!< BPWM_T::STATUS: EADCTRG2 Mask          */
+
+#define BPWM_STATUS_EADCTRG3_Pos         (19)                                              /*!< BPWM_T::STATUS: EADCTRG3 Position      */
+#define BPWM_STATUS_EADCTRG3_Msk         (0x1ul << BPWM_STATUS_EADCTRG3_Pos)               /*!< BPWM_T::STATUS: EADCTRG3 Mask          */
+
+#define BPWM_STATUS_EADCTRG4_Pos         (20)                                              /*!< BPWM_T::STATUS: EADCTRG4 Position      */
+#define BPWM_STATUS_EADCTRG4_Msk         (0x1ul << BPWM_STATUS_EADCTRG4_Pos)               /*!< BPWM_T::STATUS: EADCTRG4 Mask          */
+
+#define BPWM_STATUS_EADCTRG5_Pos         (21)                                              /*!< BPWM_T::STATUS: EADCTRG5 Position      */
+#define BPWM_STATUS_EADCTRG5_Msk         (0x1ul << BPWM_STATUS_EADCTRG5_Pos)               /*!< BPWM_T::STATUS: EADCTRG5 Mask          */
+
+#define BPWM_STATUS_EADCTRGn_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRGn Position       */
+#define BPWM_STATUS_EADCTRGn_Msk         (0x3ful << BPWM_STATUS_EADCTRGn_Pos)               /*!< BPWM_T::STATUS: EADCTRGn Mask           */
+
+#define BPWM_CAPINEN_CAPINEN0_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINEN0 Position     */
+#define BPWM_CAPINEN_CAPINEN0_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN0 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN1_Pos        (1)                                               /*!< BPWM_T::CAPINEN: CAPINEN1 Position     */
+#define BPWM_CAPINEN_CAPINEN1_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN1 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN2_Pos        (2)                                               /*!< BPWM_T::CAPINEN: CAPINEN2 Position     */
+#define BPWM_CAPINEN_CAPINEN2_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN2 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN3_Pos        (3)                                               /*!< BPWM_T::CAPINEN: CAPINEN3 Position     */
+#define BPWM_CAPINEN_CAPINEN3_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN3 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN4_Pos        (4)                                               /*!< BPWM_T::CAPINEN: CAPINEN4 Position     */
+#define BPWM_CAPINEN_CAPINEN4_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN4 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN5_Pos        (5)                                               /*!< BPWM_T::CAPINEN: CAPINEN5 Position     */
+#define BPWM_CAPINEN_CAPINEN5_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN5 Mask         */
+
+#define BPWM_CAPINEN_CAPINENn_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINENn Position     */
+#define BPWM_CAPINEN_CAPINENn_Msk        (0x3ful << BPWM_CAPINEN_CAPINENn_Pos)             /*!< BPWM_T::CAPINEN: CAPINENn Mask         */
+
+#define BPWM_CAPCTL_CAPEN0_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPEN0 Position        */
+#define BPWM_CAPCTL_CAPEN0_Msk           (0x1ul << BPWM_CAPCTL_CAPEN0_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN0 Mask            */
+
+#define BPWM_CAPCTL_CAPEN1_Pos           (1)                                               /*!< BPWM_T::CAPCTL: CAPEN1 Position        */
+#define BPWM_CAPCTL_CAPEN1_Msk           (0x1ul << BPWM_CAPCTL_CAPEN1_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN1 Mask            */
+
+#define BPWM_CAPCTL_CAPEN2_Pos           (2)                                               /*!< BPWM_T::CAPCTL: CAPEN2 Position        */
+#define BPWM_CAPCTL_CAPEN2_Msk           (0x1ul << BPWM_CAPCTL_CAPEN2_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN2 Mask            */
+
+#define BPWM_CAPCTL_CAPEN3_Pos           (3)                                               /*!< BPWM_T::CAPCTL: CAPEN3 Position        */
+#define BPWM_CAPCTL_CAPEN3_Msk           (0x1ul << BPWM_CAPCTL_CAPEN3_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN3 Mask            */
+
+#define BPWM_CAPCTL_CAPEN4_Pos           (4)                                               /*!< BPWM_T::CAPCTL: CAPEN4 Position        */
+#define BPWM_CAPCTL_CAPEN4_Msk           (0x1ul << BPWM_CAPCTL_CAPEN4_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN4 Mask            */
+
+#define BPWM_CAPCTL_CAPEN5_Pos           (5)                                               /*!< BPWM_T::CAPCTL: CAPEN5 Position        */
+#define BPWM_CAPCTL_CAPEN5_Msk           (0x1ul << BPWM_CAPCTL_CAPEN5_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN5 Mask            */
+
+#define BPWM_CAPCTL_CAPENn_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPENn Position        */
+#define BPWM_CAPCTL_CAPENn_Msk           (0x3ful << BPWM_CAPCTL_CAPENn_Pos)                /*!< BPWM_T::CAPCTL: CAPENn Mask            */
+
+#define BPWM_CAPCTL_CAPINV0_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINV0 Position       */
+#define BPWM_CAPCTL_CAPINV0_Msk          (0x1ul << BPWM_CAPCTL_CAPINV0_Pos)                /*!< BPWM_T::CAPCTL: CAPINV0 Mask           */
+
+#define BPWM_CAPCTL_CAPINV1_Pos          (9)                                               /*!< BPWM_T::CAPCTL: CAPINV1 Position       */
+#define BPWM_CAPCTL_CAPINV1_Msk          (0x1ul << BPWM_CAPCTL_CAPINV1_Pos)                /*!< BPWM_T::CAPCTL: CAPINV1 Mask           */
+
+#define BPWM_CAPCTL_CAPINV2_Pos          (10)                                              /*!< BPWM_T::CAPCTL: CAPINV2 Position       */
+#define BPWM_CAPCTL_CAPINV2_Msk          (0x1ul << BPWM_CAPCTL_CAPINV2_Pos)                /*!< BPWM_T::CAPCTL: CAPINV2 Mask           */
+
+#define BPWM_CAPCTL_CAPINV3_Pos          (11)                                              /*!< BPWM_T::CAPCTL: CAPINV3 Position       */
+#define BPWM_CAPCTL_CAPINV3_Msk          (0x1ul << BPWM_CAPCTL_CAPINV3_Pos)                /*!< BPWM_T::CAPCTL: CAPINV3 Mask           */
+
+#define BPWM_CAPCTL_CAPINV4_Pos          (12)                                              /*!< BPWM_T::CAPCTL: CAPINV4 Position       */
+#define BPWM_CAPCTL_CAPINV4_Msk          (0x1ul << BPWM_CAPCTL_CAPINV4_Pos)                /*!< BPWM_T::CAPCTL: CAPINV4 Mask           */
+
+#define BPWM_CAPCTL_CAPINV5_Pos          (13)                                              /*!< BPWM_T::CAPCTL: CAPINV5 Position       */
+#define BPWM_CAPCTL_CAPINV5_Msk          (0x1ul << BPWM_CAPCTL_CAPINV5_Pos)                /*!< BPWM_T::CAPCTL: CAPINV5 Mask           */
+
+#define BPWM_CAPCTL_CAPINVn_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINVn Position       */
+#define BPWM_CAPCTL_CAPINVn_Msk          (0x3ful << BPWM_CAPCTL_CAPINVn_Pos)               /*!< BPWM_T::CAPCTL: CAPINVn Mask           */
+
+#define BPWM_CAPCTL_RCRLDEN0_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDEN0 Position      */
+#define BPWM_CAPCTL_RCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN1_Pos         (17)                                              /*!< BPWM_T::CAPCTL: RCRLDEN1 Position      */
+#define BPWM_CAPCTL_RCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN2_Pos         (18)                                              /*!< BPWM_T::CAPCTL: RCRLDEN2 Position      */
+#define BPWM_CAPCTL_RCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN3_Pos         (19)                                              /*!< BPWM_T::CAPCTL: RCRLDEN3 Position      */
+#define BPWM_CAPCTL_RCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN4_Pos         (20)                                              /*!< BPWM_T::CAPCTL: RCRLDEN4 Position      */
+#define BPWM_CAPCTL_RCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN5_Pos         (21)                                              /*!< BPWM_T::CAPCTL: RCRLDEN5 Position      */
+#define BPWM_CAPCTL_RCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_RCRLDENn_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDENn Position      */
+#define BPWM_CAPCTL_RCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: RCRLDENn Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN0_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDEN0 Position      */
+#define BPWM_CAPCTL_FCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN1_Pos         (25)                                              /*!< BPWM_T::CAPCTL: FCRLDEN1 Position      */
+#define BPWM_CAPCTL_FCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN2_Pos         (26)                                              /*!< BPWM_T::CAPCTL: FCRLDEN2 Position      */
+#define BPWM_CAPCTL_FCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN3_Pos         (27)                                              /*!< BPWM_T::CAPCTL: FCRLDEN3 Position      */
+#define BPWM_CAPCTL_FCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN4_Pos         (28)                                              /*!< BPWM_T::CAPCTL: FCRLDEN4 Position      */
+#define BPWM_CAPCTL_FCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN5_Pos         (29)                                              /*!< BPWM_T::CAPCTL: FCRLDEN5 Position      */
+#define BPWM_CAPCTL_FCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_FCRLDENn_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDENn Position      */
+#define BPWM_CAPCTL_FCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: FCRLDENn Mask          */
+
+#define BPWM_CAPSTS_CRIFOV0_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOV0 Position       */
+#define BPWM_CAPSTS_CRIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV1_Pos          (1)                                               /*!< BPWM_T::CAPSTS: CRIFOV1 Position       */
+#define BPWM_CAPSTS_CRIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV2_Pos          (2)                                               /*!< BPWM_T::CAPSTS: CRIFOV2 Position       */
+#define BPWM_CAPSTS_CRIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV3_Pos          (3)                                               /*!< BPWM_T::CAPSTS: CRIFOV3 Position       */
+#define BPWM_CAPSTS_CRIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV4_Pos          (4)                                               /*!< BPWM_T::CAPSTS: CRIFOV4 Position       */
+#define BPWM_CAPSTS_CRIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV5_Pos          (5)                                               /*!< BPWM_T::CAPSTS: CRIFOV5 Position       */
+#define BPWM_CAPSTS_CRIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CRIFOVn_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOVn Position       */
+#define BPWM_CAPSTS_CRIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CRIFOVn Mask           */
+
+#define BPWM_CAPSTS_CFIFOV0_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOV0 Position       */
+#define BPWM_CAPSTS_CFIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV1_Pos          (9)                                               /*!< BPWM_T::CAPSTS: CFIFOV1 Position       */
+#define BPWM_CAPSTS_CFIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV2_Pos          (10)                                              /*!< BPWM_T::CAPSTS: CFIFOV2 Position       */
+#define BPWM_CAPSTS_CFIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV3_Pos          (11)                                              /*!< BPWM_T::CAPSTS: CFIFOV3 Position       */
+#define BPWM_CAPSTS_CFIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV4_Pos          (12)                                              /*!< BPWM_T::CAPSTS: CFIFOV4 Position       */
+#define BPWM_CAPSTS_CFIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV5_Pos          (13)                                              /*!< BPWM_T::CAPSTS: CFIFOV5 Position       */
+#define BPWM_CAPSTS_CFIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CFIFOVn_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOVn Position       */
+#define BPWM_CAPSTS_CFIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CFIFOVn Mask           */
+
+#define BPWM_RCAPDAT0_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT0: RCAPDAT Position     */
+#define BPWM_RCAPDAT0_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT0_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT0: FCAPDAT Position     */
+#define BPWM_FCAPDAT0_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT1_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT1: RCAPDAT Position     */
+#define BPWM_RCAPDAT1_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT1_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT1: FCAPDAT Position     */
+#define BPWM_FCAPDAT1_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT2_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT2: RCAPDAT Position     */
+#define BPWM_RCAPDAT2_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT2_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT2: FCAPDAT Position     */
+#define BPWM_FCAPDAT2_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT3_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT3: RCAPDAT Position     */
+#define BPWM_RCAPDAT3_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT3_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT3: FCAPDAT Position     */
+#define BPWM_FCAPDAT3_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT4_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT4: RCAPDAT Position     */
+#define BPWM_RCAPDAT4_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT4_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT4: FCAPDAT Position     */
+#define BPWM_FCAPDAT4_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT5_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT5: RCAPDAT Position     */
+#define BPWM_RCAPDAT5_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT5_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT5: FCAPDAT Position     */
+#define BPWM_FCAPDAT5_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask         */
+
+#define BPWM_CAPIEN_CAPRIENn_Pos         (0)                                               /*!< BPWM_T::CAPIEN: CAPRIENn Position      */
+#define BPWM_CAPIEN_CAPRIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPRIENn Mask          */
+
+#define BPWM_CAPIEN_CAPFIENn_Pos         (8)                                               /*!< BPWM_T::CAPIEN: CAPFIENn Position      */
+#define BPWM_CAPIEN_CAPFIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPFIENn Mask          */
+
+#define BPWM_CAPIF_CAPRIF0_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIF0 Position        */
+#define BPWM_CAPIF_CAPRIF0_Msk           (0x1ul << BPWM_CAPIF_CAPRIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF0 Mask            */
+
+#define BPWM_CAPIF_CAPRIF1_Pos           (1)                                               /*!< BPWM_T::CAPIF: CAPRIF1 Position        */
+#define BPWM_CAPIF_CAPRIF1_Msk           (0x1ul << BPWM_CAPIF_CAPRIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF1 Mask            */
+
+#define BPWM_CAPIF_CAPRIF2_Pos           (2)                                               /*!< BPWM_T::CAPIF: CAPRIF2 Position        */
+#define BPWM_CAPIF_CAPRIF2_Msk           (0x1ul << BPWM_CAPIF_CAPRIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF2 Mask            */
+
+#define BPWM_CAPIF_CAPRIF3_Pos           (3)                                               /*!< BPWM_T::CAPIF: CAPRIF3 Position        */
+#define BPWM_CAPIF_CAPRIF3_Msk           (0x1ul << BPWM_CAPIF_CAPRIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF3 Mask            */
+
+#define BPWM_CAPIF_CAPRIF4_Pos           (4)                                               /*!< BPWM_T::CAPIF: CAPRIF4 Position        */
+#define BPWM_CAPIF_CAPRIF4_Msk           (0x1ul << BPWM_CAPIF_CAPRIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF4 Mask            */
+
+#define BPWM_CAPIF_CAPRIF5_Pos           (5)                                               /*!< BPWM_T::CAPIF: CAPRIF5 Position        */
+#define BPWM_CAPIF_CAPRIF5_Msk           (0x1ul << BPWM_CAPIF_CAPRIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF5 Mask            */
+
+#define BPWM_CAPIF_CAPRIFn_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIFn Position        */
+#define BPWM_CAPIF_CAPRIFn_Msk           (0x3ful << BPWM_CAPIF_CAPRIFn_Pos)                /*!< BPWM_T::CAPIF: CAPRIFn Mask            */
+
+#define BPWM_CAPIF_CAPFIF0_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIF0 Position        */
+#define BPWM_CAPIF_CAPFIF0_Msk           (0x1ul << BPWM_CAPIF_CAPFIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF0 Mask            */
+
+#define BPWM_CAPIF_CAPFIF1_Pos           (9)                                               /*!< BPWM_T::CAPIF: CAPFIF1 Position        */
+#define BPWM_CAPIF_CAPFIF1_Msk           (0x1ul << BPWM_CAPIF_CAPFIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF1 Mask            */
+
+#define BPWM_CAPIF_CAPFIF2_Pos           (10)                                              /*!< BPWM_T::CAPIF: CAPFIF2 Position        */
+#define BPWM_CAPIF_CAPFIF2_Msk           (0x1ul << BPWM_CAPIF_CAPFIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF2 Mask            */
+
+#define BPWM_CAPIF_CAPFIF3_Pos           (11)                                              /*!< BPWM_T::CAPIF: CAPFIF3 Position        */
+#define BPWM_CAPIF_CAPFIF3_Msk           (0x1ul << BPWM_CAPIF_CAPFIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF3 Mask            */
+
+#define BPWM_CAPIF_CAPFIF4_Pos           (12)                                              /*!< BPWM_T::CAPIF: CAPFIF4 Position        */
+#define BPWM_CAPIF_CAPFIF4_Msk           (0x1ul << BPWM_CAPIF_CAPFIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF4 Mask            */
+
+#define BPWM_CAPIF_CAPFIF5_Pos           (13)                                              /*!< BPWM_T::CAPIF: CAPFIF5 Position        */
+#define BPWM_CAPIF_CAPFIF5_Msk           (0x1ul << BPWM_CAPIF_CAPFIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF5 Mask            */
+
+#define BPWM_CAPIF_CAPFIFn_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIFn Position        */
+#define BPWM_CAPIF_CAPFIFn_Msk           (0x3ful << BPWM_CAPIF_CAPFIFn_Pos)                /*!< BPWM_T::CAPIF: CAPFIFn Mask            */
+
+#define BPWM_PBUF_PBUF_Pos               (0)                                               /*!< BPWM_T::PBUF: PBUF Position            */
+#define BPWM_PBUF_PBUF_Msk               (0xfffful << BPWM_PBUF_PBUF_Pos)                  /*!< BPWM_T::PBUF: PBUF Mask                */
+
+#define BPWM_CMPBUF0_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF0: CMPBUF Position       */
+#define BPWM_CMPBUF0_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF0: CMPBUF Mask           */
+
+#define BPWM_CMPBUF1_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF1: CMPBUF Position       */
+#define BPWM_CMPBUF1_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF1: CMPBUF Mask           */
+
+#define BPWM_CMPBUF2_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF2: CMPBUF Position       */
+#define BPWM_CMPBUF2_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF2: CMPBUF Mask           */
+
+#define BPWM_CMPBUF3_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF3: CMPBUF Position       */
+#define BPWM_CMPBUF3_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF3: CMPBUF Mask           */
+
+#define BPWM_CMPBUF4_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF4: CMPBUF Position       */
+#define BPWM_CMPBUF4_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF4: CMPBUF Mask           */
+
+#define BPWM_CMPBUF5_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF5: CMPBUF Position       */
+#define BPWM_CMPBUF5_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF5: CMPBUF Mask           */
+
+/**@}*/ /* BPWM_CONST */
+/**@}*/ /* end of BPWM register group */
+
+
+
+/*---------------------- Quadrature Encoder Interface -------------------------*/
+/**
+    @addtogroup QEI Quadrature Encoder Interface(QEI)
+    Memory Mapped Structure for QEI Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var QEI_T::CNT
+     * Offset: 0x00  QEI Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |Quadrature Encoder Interface Counter
+     * |        |          |A 32-bit up/down counter
+     * |        |          |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero
+     * |        |          |This register performs an integrator which count value is proportional to the encoder position
+     * |        |          |The pulse counter may be initialized to a predetermined value by one of three events occurs:
+     * |        |          |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
+     * |        |          |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode.
+     * |        |          |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1.
+     * @var QEI_T::CNTHOLD
+     * Offset: 0x04  QEI Counter Hold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTHOLD   |Quadrature Encoder Interface Counter Hold
+     * |        |          |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
+     * @var QEI_T::CNTLATCH
+     * Offset: 0x08  QEI Counter Index Latch Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTLATCH  |Quadrature Encoder Interface Counter Index Latch
+     * |        |          |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
+     * @var QEI_T::CNTCMP
+     * Offset: 0x0C  QEI Counter Compare Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTCMP    |Quadrature Encoder Interface Counter Compare
+     * |        |          |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
+     * |        |          |This register is software writable.
+     * @var QEI_T::CNTMAX
+     * Offset: 0x14  QEI Pre-set Maximum Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTMAX    |Quadrature Encoder Interface Preset Maximum Count
+     * |        |          |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
+     * @var QEI_T::CTL
+     * Offset: 0x18  QEI Controller Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |NFCLKSEL  |Noise Filter Clock Pre-divide Selection
+     * |        |          |To determine the sampling frequency of the Noise Filter clock .
+     * |        |          |000 = QEI_CLK.
+     * |        |          |001 = QEI_CLK/2.
+     * |        |          |010 = QEI_CLK/4.
+     * |        |          |011 = QEI_CLK/16.
+     * |        |          |100 = QEI_CLK/32.
+     * |        |          |101 = QEI_CLK/64.
+     * |[3]     |NFDIS     |QEI Controller Input Noise Filter Disable Bit
+     * |        |          |0 = The noise filter of QEI controller Enabled.
+     * |        |          |1 = The noise filter of QEI controller Disabled.
+     * |[4]     |CHAEN     |QEA Input to QEI Controller Enable Bit
+     * |        |          |0 = QEA input to QEI Controller Disabled.
+     * |        |          |1 = QEA input to QEI Controller Enabled.
+     * |[5]     |CHBEN     |QEB Input to QEI Controller Enable Bit
+     * |        |          |0 = QEB input to QEI Controller Disabled.
+     * |        |          |1 = QEB input to QEI Controller Enabled.
+     * |[6]     |IDXEN     |IDX Input to QEI Controller Enable Bit
+     * |        |          |0 = IDX input to QEI Controller Disabled.
+     * |        |          |1 = IDX input to QEI Controller Enabled.
+     * |[9:8]   |MODE      |QEI Counting Mode Selection
+     * |        |          |There are four quadrature encoder pulse counter operation modes.
+     * |        |          |00 = X4 Free-counting Mode.
+     * |        |          |01 = X2 Free-counting Mode.
+     * |        |          |10 = X4 Compare-counting Mode.
+     * |        |          |11 = X2 Compare-counting Mode.
+     * |[12]    |CHAINV    |Inverse QEA Input Polarity
+     * |        |          |0 = Not inverse QEA input polarity.
+     * |        |          |1 = QEA input polarity is inversed to QEI controller.
+     * |[13]    |CHBINV    |Inverse QEB Input Polarity
+     * |        |          |0 = Not inverse QEB input polarity.
+     * |        |          |1 = QEB input polarity is inversed to QEI controller.
+     * |[14]    |IDXINV    |Inverse IDX Input Polarity
+     * |        |          |0 = Not inverse IDX input polarity.
+     * |        |          |1 = IDX input polarity is inversed to QEI controller.
+     * |[16]    |OVUNIEN   |OVUNF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = OVUNF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = OVUNF can trigger QEI controller interrupt Enabled.
+     * |[17]    |DIRIEN    |DIRCHGF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
+     * |[18]    |CMPIEN    |CMPF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = CMPF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = CMPF can trigger QEI controller interrupt Enabled.
+     * |[19]    |IDXIEN    |IDXF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = The IDXF can trigger QEI interrupt Disabled.
+     * |        |          |1 = The IDXF can trigger QEI interrupt Enabled.
+     * |[20]    |HOLDTMR0  |Hold QEI_CNT by Timer 0
+     * |        |          |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
+     * |[21]    |HOLDTMR1  |Hold QEI_CNT by Timer 1
+     * |        |          |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
+     * |[22]    |HOLDTMR2  |Hold QEI_CNT by Timer 2
+     * |        |          |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
+     * |[23]    |HOLDTMR3  |Hold QEI_CNT by Timer 3
+     * |        |          |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
+     * |[24]    |HOLDCNT   |Hold QEI_CNT Control
+     * |        |          |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])
+     * |        |          |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
+     * |        |          |0 = No operation.
+     * |        |          |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]).
+     * |        |          |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
+     * |[25]    |IDXLATEN  |Index Latch QEI_CNT Enable Bit
+     * |        |          |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX.
+     * |        |          |0 = The index signal latch QEI counter function Disabled.
+     * |        |          |1 = The index signal latch QEI counter function Enabled.
+     * |[27]    |IDXRLDEN  |Index Trigger QEI_CNT Reload Enable Bit
+     * |        |          |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0).
+     * |        |          |0 = Reload function Disabled.
+     * |        |          |1 = QEI_CNT re-initialized by Index signal Enabled.
+     * |[28]    |CMPEN     |The Compare Function Enable Bit
+     * |        |          |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
+     * |        |          |0 = Compare function Disabled.
+     * |        |          |1 = Compare function Enabled.
+     * |[29]    |QEIEN     |Quadrature Encoder Interface Controller Enable Bit
+     * |        |          |0 = QEI controller function Disabled.
+     * |        |          |1 = QEI controller function Enabled.
+     * @var QEI_T::STATUS
+     * Offset: 0x2C  QEI Controller Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IDXF      |IDX Detected Flag
+     * |        |          |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
+     * |        |          |0 = No rising edge detected on signal CHX.
+     * |        |          |1 = A rising edge occurs on signal CHX.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[1]     |CMPF      |Compare-match Flag
+     * |        |          |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[2]     |OVUNF     |QEI Counter Overflow or Underflow Flag
+     * |        |          |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
+    * |        |          |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
+     * |        |          |0 = No overflow or underflow occurs in QEI counter.
+     * |        |          |1 = QEI counter occurs counting overflow or underflow.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[3]     |DIRCHGF   |Direction Change Flag
+     * |        |          |Flag is set by hardware while QEI counter counting direction is changed.
+     * |        |          |Software can clear this bit by writing 1 to it.
+     * |        |          |0 = No change in QEI counter counting direction.
+     * |        |          |1 = QEI counter counting direction is changed.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[8]     |DIRF      |QEI Counter Counting Direction Indication
+     * |        |          |0 = QEI Counter is in down-counting.
+     * |        |          |1 = QEI Counter is in up-counting.
+     * |        |          |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
+     */
+    __IO uint32_t CNT;                   /*!< [0x0000] QEI Counter Register                                             */
+    __IO uint32_t CNTHOLD;               /*!< [0x0004] QEI Counter Hold Register                                        */
+    __IO uint32_t CNTLATCH;              /*!< [0x0008] QEI Counter Index Latch Register                                 */
+    __IO uint32_t CNTCMP;                /*!< [0x000c] QEI Counter Compare Register                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CNTMAX;                /*!< [0x0014] QEI Pre-set Maximum Count Register                               */
+    __IO uint32_t CTL;                   /*!< [0x0018] QEI Controller Control Register                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[4];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t STATUS;                /*!< [0x002c] QEI Controller Status Register                                   */
+
+} QEI_T;
+
+/**
+    @addtogroup QEI_CONST QEI Bit Field Definition
+    Constant Definitions for QEI Controller
+@{ */
+
+#define QEI_CNT_CNT_Pos                  (0)                                               /*!< QEI_T::CNT: CNT Position               */
+#define QEI_CNT_CNT_Msk                  (0xfffffffful << QEI_CNT_CNT_Pos)                 /*!< QEI_T::CNT: CNT Mask                   */
+
+#define QEI_CNTHOLD_CNTHOLD_Pos          (0)                                               /*!< QEI_T::CNTHOLD: CNTHOLD Position       */
+#define QEI_CNTHOLD_CNTHOLD_Msk          (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos)         /*!< QEI_T::CNTHOLD: CNTHOLD Mask           */
+
+#define QEI_CNTLATCH_CNTLATCH_Pos        (0)                                               /*!< QEI_T::CNTLATCH: CNTLATCH Position     */
+#define QEI_CNTLATCH_CNTLATCH_Msk        (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos)       /*!< QEI_T::CNTLATCH: CNTLATCH Mask         */
+
+#define QEI_CNTCMP_CNTCMP_Pos            (0)                                               /*!< QEI_T::CNTCMP: CNTCMP Position         */
+#define QEI_CNTCMP_CNTCMP_Msk            (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos)           /*!< QEI_T::CNTCMP: CNTCMP Mask             */
+
+#define QEI_CNTMAX_CNTMAX_Pos            (0)                                               /*!< QEI_T::CNTMAX: CNTMAX Position         */
+#define QEI_CNTMAX_CNTMAX_Msk            (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos)           /*!< QEI_T::CNTMAX: CNTMAX Mask             */
+
+#define QEI_CTL_NFCLKSEL_Pos             (0)                                               /*!< QEI_T::CTL: NFCLKSEL Position          */
+#define QEI_CTL_NFCLKSEL_Msk             (0x7ul << QEI_CTL_NFCLKSEL_Pos)                   /*!< QEI_T::CTL: NFCLKSEL Mask              */
+
+#define QEI_CTL_NFDIS_Pos                (3)                                               /*!< QEI_T::CTL: NFDIS Position             */
+#define QEI_CTL_NFDIS_Msk                (0x1ul << QEI_CTL_NFDIS_Pos)                      /*!< QEI_T::CTL: NFDIS Mask                 */
+
+#define QEI_CTL_CHAEN_Pos                (4)                                               /*!< QEI_T::CTL: CHAEN Position             */
+#define QEI_CTL_CHAEN_Msk                (0x1ul << QEI_CTL_CHAEN_Pos)                      /*!< QEI_T::CTL: CHAEN Mask                 */
+
+#define QEI_CTL_CHBEN_Pos                (5)                                               /*!< QEI_T::CTL: CHBEN Position             */
+#define QEI_CTL_CHBEN_Msk                (0x1ul << QEI_CTL_CHBEN_Pos)                      /*!< QEI_T::CTL: CHBEN Mask                 */
+
+#define QEI_CTL_IDXEN_Pos                (6)                                               /*!< QEI_T::CTL: IDXEN Position             */
+#define QEI_CTL_IDXEN_Msk                (0x1ul << QEI_CTL_IDXEN_Pos)                      /*!< QEI_T::CTL: IDXEN Mask                 */
+
+#define QEI_CTL_MODE_Pos                 (8)                                               /*!< QEI_T::CTL: MODE Position              */
+#define QEI_CTL_MODE_Msk                 (0x3ul << QEI_CTL_MODE_Pos)                       /*!< QEI_T::CTL: MODE Mask                  */
+
+#define QEI_CTL_CHAINV_Pos               (12)                                              /*!< QEI_T::CTL: CHAINV Position            */
+#define QEI_CTL_CHAINV_Msk               (0x1ul << QEI_CTL_CHAINV_Pos)                     /*!< QEI_T::CTL: CHAINV Mask                */
+
+#define QEI_CTL_CHBINV_Pos               (13)                                              /*!< QEI_T::CTL: CHBINV Position            */
+#define QEI_CTL_CHBINV_Msk               (0x1ul << QEI_CTL_CHBINV_Pos)                     /*!< QEI_T::CTL: CHBINV Mask                */
+
+#define QEI_CTL_IDXINV_Pos               (14)                                              /*!< QEI_T::CTL: IDXINV Position            */
+#define QEI_CTL_IDXINV_Msk               (0x1ul << QEI_CTL_IDXINV_Pos)                     /*!< QEI_T::CTL: IDXINV Mask                */
+
+#define QEI_CTL_OVUNIEN_Pos              (16)                                              /*!< QEI_T::CTL: OVUNIEN Position           */
+#define QEI_CTL_OVUNIEN_Msk              (0x1ul << QEI_CTL_OVUNIEN_Pos)                    /*!< QEI_T::CTL: OVUNIEN Mask               */
+
+#define QEI_CTL_DIRIEN_Pos               (17)                                              /*!< QEI_T::CTL: DIRIEN Position            */
+#define QEI_CTL_DIRIEN_Msk               (0x1ul << QEI_CTL_DIRIEN_Pos)                     /*!< QEI_T::CTL: DIRIEN Mask                */
+
+#define QEI_CTL_CMPIEN_Pos               (18)                                              /*!< QEI_T::CTL: CMPIEN Position            */
+#define QEI_CTL_CMPIEN_Msk               (0x1ul << QEI_CTL_CMPIEN_Pos)                     /*!< QEI_T::CTL: CMPIEN Mask                */
+
+#define QEI_CTL_IDXIEN_Pos               (19)                                              /*!< QEI_T::CTL: IDXIEN Position            */
+#define QEI_CTL_IDXIEN_Msk               (0x1ul << QEI_CTL_IDXIEN_Pos)                     /*!< QEI_T::CTL: IDXIEN Mask                */
+
+#define QEI_CTL_HOLDTMR0_Pos             (20)                                              /*!< QEI_T::CTL: HOLDTMR0 Position          */
+#define QEI_CTL_HOLDTMR0_Msk             (0x1ul << QEI_CTL_HOLDTMR0_Pos)                   /*!< QEI_T::CTL: HOLDTMR0 Mask              */
+
+#define QEI_CTL_HOLDTMR1_Pos             (21)                                              /*!< QEI_T::CTL: HOLDTMR1 Position          */
+#define QEI_CTL_HOLDTMR1_Msk             (0x1ul << QEI_CTL_HOLDTMR1_Pos)                   /*!< QEI_T::CTL: HOLDTMR1 Mask              */
+
+#define QEI_CTL_HOLDTMR2_Pos             (22)                                              /*!< QEI_T::CTL: HOLDTMR2 Position          */
+#define QEI_CTL_HOLDTMR2_Msk             (0x1ul << QEI_CTL_HOLDTMR2_Pos)                   /*!< QEI_T::CTL: HOLDTMR2 Mask              */
+
+#define QEI_CTL_HOLDTMR3_Pos             (23)                                              /*!< QEI_T::CTL: HOLDTMR3 Position          */
+#define QEI_CTL_HOLDTMR3_Msk             (0x1ul << QEI_CTL_HOLDTMR3_Pos)                   /*!< QEI_T::CTL: HOLDTMR3 Mask              */
+
+#define QEI_CTL_HOLDCNT_Pos              (24)                                              /*!< QEI_T::CTL: HOLDCNT Position           */
+#define QEI_CTL_HOLDCNT_Msk              (0x1ul << QEI_CTL_HOLDCNT_Pos)                    /*!< QEI_T::CTL: HOLDCNT Mask               */
+
+#define QEI_CTL_IDXLATEN_Pos             (25)                                              /*!< QEI_T::CTL: IDXLATEN Position          */
+#define QEI_CTL_IDXLATEN_Msk             (0x1ul << QEI_CTL_IDXLATEN_Pos)                   /*!< QEI_T::CTL: IDXLATEN Mask              */
+
+#define QEI_CTL_IDXRLDEN_Pos             (27)                                              /*!< QEI_T::CTL: IDXRLDEN Position          */
+#define QEI_CTL_IDXRLDEN_Msk             (0x1ul << QEI_CTL_IDXRLDEN_Pos)                   /*!< QEI_T::CTL: IDXRLDEN Mask              */
+
+#define QEI_CTL_CMPEN_Pos                (28)                                              /*!< QEI_T::CTL: CMPEN Position             */
+#define QEI_CTL_CMPEN_Msk                (0x1ul << QEI_CTL_CMPEN_Pos)                      /*!< QEI_T::CTL: CMPEN Mask                 */
+
+#define QEI_CTL_QEIEN_Pos                (29)                                              /*!< QEI_T::CTL: QEIEN Position             */
+#define QEI_CTL_QEIEN_Msk                (0x1ul << QEI_CTL_QEIEN_Pos)                      /*!< QEI_T::CTL: QEIEN Mask                 */
+
+#define QEI_STATUS_IDXF_Pos              (0)                                               /*!< QEI_T::STATUS: IDXF Position           */
+#define QEI_STATUS_IDXF_Msk              (0x1ul << QEI_STATUS_IDXF_Pos)                    /*!< QEI_T::STATUS: IDXF Mask               */
+
+#define QEI_STATUS_CMPF_Pos              (1)                                               /*!< QEI_T::STATUS: CMPF Position           */
+#define QEI_STATUS_CMPF_Msk              (0x1ul << QEI_STATUS_CMPF_Pos)                    /*!< QEI_T::STATUS: CMPF Mask               */
+
+#define QEI_STATUS_OVUNF_Pos             (2)                                               /*!< QEI_T::STATUS: OVUNF Position          */
+#define QEI_STATUS_OVUNF_Msk             (0x1ul << QEI_STATUS_OVUNF_Pos)                   /*!< QEI_T::STATUS: OVUNF Mask              */
+
+#define QEI_STATUS_DIRCHGF_Pos           (3)                                               /*!< QEI_T::STATUS: DIRCHGF Position        */
+#define QEI_STATUS_DIRCHGF_Msk           (0x1ul << QEI_STATUS_DIRCHGF_Pos)                 /*!< QEI_T::STATUS: DIRCHGF Mask            */
+
+#define QEI_STATUS_DIRF_Pos              (8)                                               /*!< QEI_T::STATUS: DIRF Position           */
+#define QEI_STATUS_DIRF_Msk              (0x1ul << QEI_STATUS_DIRF_Pos)                    /*!< QEI_T::STATUS: DIRF Mask               */
+
+/**@}*/ /* QEI_CONST */
+/**@}*/ /* end of QEI register group */
+
+
+
+
+
+/*---------------------- Enhanced Input Capture Timer -------------------------*/
+/**
+    @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
+    Memory Mapped Structure for ECAP Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var ECAP_T::CNT
+     * Offset: 0x00  Input Capture Counter (24-bit up counter)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Input Capture Timer/Counter
+     * |        |          |The input Capture Timer/Counter is a 24-bit up-counting counter
+     * |        |          |The clock source for the counter is from the clock divider
+     * @var ECAP_T::HLD0
+     * Offset: 0x04  Input Capture Hold Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD1
+     * Offset: 0x08  Input Capture Hold Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD2
+     * Offset: 0x0C  Input Capture Hold Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::CNTCMP
+     * Offset: 0x10  Input Capture Compare Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNTCMP    |Input Capture Counter Compare Register
+     * |        |          |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
+     * |        |          |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
+     * @var ECAP_T::CTL0
+     * Offset: 0x14  Input Capture Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |NFCLKSEL  |Noise Filter Clock Pre-divide Selection
+     * |        |          |To determine the sampling frequency of the Noise Filter clock
+     * |        |          |000 = CAP_CLK.
+     * |        |          |001 = CAP_CLK/2.
+     * |        |          |010 = CAP_CLK/4.
+     * |        |          |011 = CAP_CLK/16.
+     * |        |          |100 = CAP_CLK/32.
+     * |        |          |101 = CAP_CLK/64.
+     * |[3]     |CAPNFDIS  |Input Capture Noise Filter Disable Control
+     * |        |          |0 = Noise filter of Input Capture Enabled.
+     * |        |          |1 = Noise filter of Input Capture Disabled (Bypass).
+     * |[4]     |IC0EN     |Port Pin IC0 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC0 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC0 input to Input Capture Unit Enabled.
+     * |[5]     |IC1EN     |Port Pin IC1 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC1 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC1 input to Input Capture Unit Enabled.
+     * |[6]     |IC2EN     |Port Pin IC2 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC2 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC2 input to Input Capture Unit Enabled.
+     * |[9:8]   |CAPSEL0   |CAP0 Input Source Selection
+     * |        |          |00 = CAP0 input is from port pin ICAP0.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP0 input is from signal CHA of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[11:10] |CAPSEL1   |CAP1 Input Source Selection
+     * |        |          |00 = CAP1 input is from port pin ICAP1.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP1 input is from signal CHB of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[13:12] |CAPSEL2   |CAP2 Input Source Selection
+     * |        |          |00 = CAP2 input is from port pin ICAP2.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP2 input is from signal CHX of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[16]    |CAPIEN0   |Input Capture Channel 0 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
+     * |[17]    |CAPIEN1   |Input Capture Channel 1 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
+     * |[18]    |CAPIEN2   |Input Capture Channel 2 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
+     * |[20]    |OVIEN     |CAPOVF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
+     * |[21]    |CMPIEN    |CAPCMPF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
+     * |[24]    |CNTEN     |Input Capture Counter Start Counting Control
+     * |        |          |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
+     * |        |          |0 = ECAP_CNT stop counting.
+     * |        |          |1 = ECAP_CNT starts up-counting.
+     * |[25]    |CMPCLREN  |Input Capture Counter Cleared by Compare-match Control
+     * |        |          |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
+     * |        |          |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
+     * |[28]    |CMPEN     |Compare Function Enable Control
+     * |        |          |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
+     * |        |          |0 = The compare function Disabled.
+     * |        |          |1 = The compare function Enabled.
+     * |[29]    |CAPEN     |Input Capture Timer/Counter Enable Control
+     * |        |          |0 = Input Capture function Disabled.
+     * |        |          |1 = Input Capture function Enabled.
+     * @var ECAP_T::CTL1
+     * Offset: 0x18  Input Capture Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |EDGESEL0  |Channel 0 Captured Edge Selection
+     * |        |          |Input capture0 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[3:2]   |EDGESEL1  |Channel 1 Captured Edge Selection
+     * |        |          |Input capture1 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[5:4]   |EDGESEL2  |Channel 2 Captured Edge Selection
+     * |        |          |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[8]     |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE0 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE0 Enabled.
+     * |[9]     |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE1 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE1 Enabled.
+     * |[10]    |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE2 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE2 Enabled.
+     * |[11]    |OVRLDEN   |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
+     * |        |          |0 = The reload triggered by CAPOV Disabled.
+     * |        |          |1 = The reload triggered by CAPOV Enabled.
+     * |[14:12] |CLKSEL    |Capture Timer Clock Divide Selection
+     * |        |          |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
+     * |        |          |000 = CAP_CLK/1.
+     * |        |          |001 = CAP_CLK/4.
+     * |        |          |010 = CAP_CLK/16.
+     * |        |          |011 = CAP_CLK/32.
+     * |        |          |100 = CAP_CLK/64.
+     * |        |          |101 = CAP_CLK/96.
+     * |        |          |110 = CAP_CLK/112.
+     * |        |          |111 = CAP_CLK/128.
+     * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
+     * |        |          |Select the capture timer/counter clock source.
+     * |        |          |00 = CAP_CLK (default).
+     * |        |          |01 = CAP0.
+     * |        |          |10 = CAP1.
+     * |        |          |11 = CAP2.
+     * |[20]    |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
+     * |        |          |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
+     * |[21]    |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
+     * |        |          |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
+     * |[22]    |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
+     * |        |          |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
+     * @var ECAP_T::STATUS
+     * Offset: 0x1C  Input Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPTF0    |Input Capture Channel 0 Triggered Flag
+     * |        |          |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[1]     |CAPTF1    |Input Capture Channel 1 Triggered Flag
+     * |        |          |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[2]     |CAPTF2    |Input Capture Channel 2 Triggered Flag
+     * |        |          |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[4]     |CAPCMPF   |Input Capture Compare-match Flag
+     * |        |          |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
+     * |        |          |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
+     * |        |          |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[5]     |CAPOVF    |Input Capture Counter Overflow Flag
+     * |        |          |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
+     * |        |          |0 = No overflow event has occurred since last clear.
+     * |        |          |1 = Overflow event(s) has/have occurred since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[6]     |CAP0      |Value of Input Channel 0, CAP0 (Read Only)
+     * |        |          |Reflecting the value of input channel 0, CAP0
+     * |        |          |(The bit is read only and write is ignored)
+     * |[7]     |CAP1      |Value of Input Channel 1, CAP1 (Read Only)
+     * |        |          |Reflecting the value of input channel 1, CAP1
+     * |        |          |(The bit is read only and write is ignored)
+     * |[8]     |CAP2      |Value of Input Channel 2, CAP2 (Read Only)
+     * |        |          |Reflecting the value of input channel 2, CAP2.
+     * |        |          |(The bit is read only and write is ignored)
+     */
+    __IO uint32_t CNT;                   /*!< [0x0000] Input Capture Counter                                            */
+    __IO uint32_t HLD0;                  /*!< [0x0004] Input Capture Hold Register 0                                    */
+    __IO uint32_t HLD1;                  /*!< [0x0008] Input Capture Hold Register 1                                    */
+    __IO uint32_t HLD2;                  /*!< [0x000c] Input Capture Hold Register 2                                    */
+    __IO uint32_t CNTCMP;                /*!< [0x0010] Input Capture Compare Register                                   */
+    __IO uint32_t CTL0;                  /*!< [0x0014] Input Capture Control Register 0                                 */
+    __IO uint32_t CTL1;                  /*!< [0x0018] Input Capture Control Register 1                                 */
+    __IO uint32_t STATUS;                /*!< [0x001c] Input Capture Status Register                                    */
+
+} ECAP_T;
+
+/**
+    @addtogroup ECAP_CONST ECAP Bit Field Definition
+    Constant Definitions for ECAP Controller
+@{ */
+
+#define ECAP_CNT_CNT_Pos                 (0)                                               /*!< ECAP_T::CNT: CNT Position              */
+#define ECAP_CNT_CNT_Msk                 (0xfffffful << ECAP_CNT_CNT_Pos)                  /*!< ECAP_T::CNT: CNT Mask                  */
+
+#define ECAP_HLD0_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD0: HOLD Position            */
+#define ECAP_HLD0_HOLD_Msk               (0xfffffful << ECAP_HLD0_HOLD_Pos)                /*!< ECAP_T::HLD0: HOLD Mask                */
+
+#define ECAP_HLD1_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD1: HOLD Position            */
+#define ECAP_HLD1_HOLD_Msk               (0xfffffful << ECAP_HLD1_HOLD_Pos)                /*!< ECAP_T::HLD1: HOLD Mask                */
+
+#define ECAP_HLD2_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD2: HOLD Position            */
+#define ECAP_HLD2_HOLD_Msk               (0xfffffful << ECAP_HLD2_HOLD_Pos)                /*!< ECAP_T::HLD2: HOLD Mask                */
+
+#define ECAP_CNTCMP_CNTCMP_Pos           (0)                                               /*!< ECAP_T::CNTCMP: CNTCMP Position        */
+#define ECAP_CNTCMP_CNTCMP_Msk           (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos)            /*!< ECAP_T::CNTCMP: CNTCMP Mask            */
+
+#define ECAP_CTL0_NFCLKSEL_Pos           (0)                                               /*!< ECAP_T::CTL0: NFCLKSEL Position        */
+#define ECAP_CTL0_NFCLKSEL_Msk           (0x7ul << ECAP_CTL0_NFCLKSEL_Pos)                 /*!< ECAP_T::CTL0: NFCLKSEL Mask            */
+
+#define ECAP_CTL0_CAPNFDIS_Pos           (3)                                               /*!< ECAP_T::CTL0: CAPNFDIS Position        */
+#define ECAP_CTL0_CAPNFDIS_Msk           (0x1ul << ECAP_CTL0_CAPNFDIS_Pos)                 /*!< ECAP_T::CTL0: CAPNFDIS Mask            */
+
+#define ECAP_CTL0_IC0EN_Pos              (4)                                               /*!< ECAP_T::CTL0: IC0EN Position           */
+#define ECAP_CTL0_IC0EN_Msk              (0x1ul << ECAP_CTL0_IC0EN_Pos)                    /*!< ECAP_T::CTL0: IC0EN Mask               */
+
+#define ECAP_CTL0_IC1EN_Pos              (5)                                               /*!< ECAP_T::CTL0: IC1EN Position           */
+#define ECAP_CTL0_IC1EN_Msk              (0x1ul << ECAP_CTL0_IC1EN_Pos)                    /*!< ECAP_T::CTL0: IC1EN Mask               */
+
+#define ECAP_CTL0_IC2EN_Pos              (6)                                               /*!< ECAP_T::CTL0: IC2EN Position           */
+#define ECAP_CTL0_IC2EN_Msk              (0x1ul << ECAP_CTL0_IC2EN_Pos)                    /*!< ECAP_T::CTL0: IC2EN Mask               */
+
+#define ECAP_CTL0_CAPSEL0_Pos            (8)                                               /*!< ECAP_T::CTL0: CAPSEL0 Position         */
+#define ECAP_CTL0_CAPSEL0_Msk            (0x3ul << ECAP_CTL0_CAPSEL0_Pos)                  /*!< ECAP_T::CTL0: CAPSEL0 Mask             */
+
+#define ECAP_CTL0_CAPSEL1_Pos            (10)                                              /*!< ECAP_T::CTL0: CAPSEL1 Position         */
+#define ECAP_CTL0_CAPSEL1_Msk            (0x3ul << ECAP_CTL0_CAPSEL1_Pos)                  /*!< ECAP_T::CTL0: CAPSEL1 Mask             */
+
+#define ECAP_CTL0_CAPSEL2_Pos            (12)                                              /*!< ECAP_T::CTL0: CAPSEL2 Position         */
+#define ECAP_CTL0_CAPSEL2_Msk            (0x3ul << ECAP_CTL0_CAPSEL2_Pos)                  /*!< ECAP_T::CTL0: CAPSEL2 Mask             */
+
+#define ECAP_CTL0_CAPIEN0_Pos            (16)                                              /*!< ECAP_T::CTL0: CAPIEN0 Position         */
+#define ECAP_CTL0_CAPIEN0_Msk            (0x1ul << ECAP_CTL0_CAPIEN0_Pos)                  /*!< ECAP_T::CTL0: CAPIEN0 Mask             */
+
+#define ECAP_CTL0_CAPIEN1_Pos            (17)                                              /*!< ECAP_T::CTL0: CAPIEN1 Position         */
+#define ECAP_CTL0_CAPIEN1_Msk            (0x1ul << ECAP_CTL0_CAPIEN1_Pos)                  /*!< ECAP_T::CTL0: CAPIEN1 Mask             */
+
+#define ECAP_CTL0_CAPIEN2_Pos            (18)                                              /*!< ECAP_T::CTL0: CAPIEN2 Position         */
+#define ECAP_CTL0_CAPIEN2_Msk            (0x1ul << ECAP_CTL0_CAPIEN2_Pos)                  /*!< ECAP_T::CTL0: CAPIEN2 Mask             */
+
+#define ECAP_CTL0_OVIEN_Pos              (20)                                              /*!< ECAP_T::CTL0: OVIEN Position           */
+#define ECAP_CTL0_OVIEN_Msk              (0x1ul << ECAP_CTL0_OVIEN_Pos)                    /*!< ECAP_T::CTL0: OVIEN Mask               */
+
+#define ECAP_CTL0_CMPIEN_Pos             (21)                                              /*!< ECAP_T::CTL0: CMPIEN Position          */
+#define ECAP_CTL0_CMPIEN_Msk             (0x1ul << ECAP_CTL0_CMPIEN_Pos)                   /*!< ECAP_T::CTL0: CMPIEN Mask              */
+
+#define ECAP_CTL0_CNTEN_Pos              (24)                                              /*!< ECAP_T::CTL0: CNTEN Position           */
+#define ECAP_CTL0_CNTEN_Msk              (0x1ul << ECAP_CTL0_CNTEN_Pos)                    /*!< ECAP_T::CTL0: CNTEN Mask               */
+
+#define ECAP_CTL0_CMPCLREN_Pos           (25)                                              /*!< ECAP_T::CTL0: CMPCLREN Position        */
+#define ECAP_CTL0_CMPCLREN_Msk           (0x1ul << ECAP_CTL0_CMPCLREN_Pos)                 /*!< ECAP_T::CTL0: CMPCLREN Mask            */
+
+#define ECAP_CTL0_CMPEN_Pos              (28)                                              /*!< ECAP_T::CTL0: CMPEN Position           */
+#define ECAP_CTL0_CMPEN_Msk              (0x1ul << ECAP_CTL0_CMPEN_Pos)                    /*!< ECAP_T::CTL0: CMPEN Mask               */
+
+#define ECAP_CTL0_CAPEN_Pos              (29)                                              /*!< ECAP_T::CTL0: CAPEN Position           */
+#define ECAP_CTL0_CAPEN_Msk              (0x1ul << ECAP_CTL0_CAPEN_Pos)                    /*!< ECAP_T::CTL0: CAPEN Mask               */
+
+#define ECAP_CTL1_EDGESEL0_Pos           (0)                                               /*!< ECAP_T::CTL1: EDGESEL0 Position        */
+#define ECAP_CTL1_EDGESEL0_Msk           (0x3ul << ECAP_CTL1_EDGESEL0_Pos)                 /*!< ECAP_T::CTL1: EDGESEL0 Mask            */
+
+#define ECAP_CTL1_EDGESEL1_Pos           (2)                                               /*!< ECAP_T::CTL1: EDGESEL1 Position        */
+#define ECAP_CTL1_EDGESEL1_Msk           (0x3ul << ECAP_CTL1_EDGESEL1_Pos)                 /*!< ECAP_T::CTL1: EDGESEL1 Mask            */
+
+#define ECAP_CTL1_EDGESEL2_Pos           (4)                                               /*!< ECAP_T::CTL1: EDGESEL2 Position        */
+#define ECAP_CTL1_EDGESEL2_Msk           (0x3ul << ECAP_CTL1_EDGESEL2_Pos)                 /*!< ECAP_T::CTL1: EDGESEL2 Mask            */
+
+#define ECAP_CTL1_CAP0RLDEN_Pos          (8)                                               /*!< ECAP_T::CTL1: CAP0RLDEN Position       */
+#define ECAP_CTL1_CAP0RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP0RLDEN Mask           */
+
+#define ECAP_CTL1_CAP1RLDEN_Pos          (9)                                               /*!< ECAP_T::CTL1: CAP1RLDEN Position       */
+#define ECAP_CTL1_CAP1RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP1RLDEN Mask           */
+
+#define ECAP_CTL1_CAP2RLDEN_Pos          (10)                                              /*!< ECAP_T::CTL1: CAP2RLDEN Position       */
+#define ECAP_CTL1_CAP2RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP2RLDEN Mask           */
+
+#define ECAP_CTL1_OVRLDEN_Pos            (11)                                              /*!< ECAP_T::CTL1: OVRLDEN Position         */
+#define ECAP_CTL1_OVRLDEN_Msk            (0x1ul << ECAP_CTL1_OVRLDEN_Pos)                  /*!< ECAP_T::CTL1: OVRLDEN Mask             */
+
+#define ECAP_CTL1_CLKSEL_Pos             (12)                                              /*!< ECAP_T::CTL1: CLKSEL Position          */
+#define ECAP_CTL1_CLKSEL_Msk             (0x7ul << ECAP_CTL1_CLKSEL_Pos)                   /*!< ECAP_T::CTL1: CLKSEL Mask              */
+
+#define ECAP_CTL1_CNTSRCSEL_Pos          (16)                                              /*!< ECAP_T::CTL1: CNTSRCSEL Position       */
+#define ECAP_CTL1_CNTSRCSEL_Msk          (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos)                /*!< ECAP_T::CTL1: CNTSRCSEL Mask           */
+
+#define ECAP_CTL1_CAP0CLREN_Pos          (20)                                              /*!< ECAP_T::CTL1: CAP0CLREN Position       */
+#define ECAP_CTL1_CAP0CLREN_Msk          (0x1ul << ECAP_CTL1_CAP0CLREN_Pos)                /*!< ECAP_T::CTL1: CAP0CLREN Mask           */
+
+#define ECAP_CTL1_CAP1CLREN_Pos          (21)                                              /*!< ECAP_T::CTL1: CAP1CLREN Position       */
+#define ECAP_CTL1_CAP1CLREN_Msk          (0x1ul << ECAP_CTL1_CAP1CLREN_Pos)                /*!< ECAP_T::CTL1: CAP1CLREN Mask           */
+
+#define ECAP_CTL1_CAP2CLREN_Pos          (22)                                              /*!< ECAP_T::CTL1: CAP2CLREN Position       */
+#define ECAP_CTL1_CAP2CLREN_Msk          (0x1ul << ECAP_CTL1_CAP2CLREN_Pos)                /*!< ECAP_T::CTL1: CAP2CLREN Mask           */
+
+#define ECAP_STATUS_CAPTF0_Pos           (0)                                               /*!< ECAP_T::STATUS: CAPTF0 Position        */
+#define ECAP_STATUS_CAPTF0_Msk           (0x1ul << ECAP_STATUS_CAPTF0_Pos)                 /*!< ECAP_T::STATUS: CAPTF0 Mask            */
+
+#define ECAP_STATUS_CAPTF1_Pos           (1)                                               /*!< ECAP_T::STATUS: CAPTF1 Position        */
+#define ECAP_STATUS_CAPTF1_Msk           (0x1ul << ECAP_STATUS_CAPTF1_Pos)                 /*!< ECAP_T::STATUS: CAPTF1 Mask            */
+
+#define ECAP_STATUS_CAPTF2_Pos           (2)                                               /*!< ECAP_T::STATUS: CAPTF2 Position        */
+#define ECAP_STATUS_CAPTF2_Msk           (0x1ul << ECAP_STATUS_CAPTF2_Pos)                 /*!< ECAP_T::STATUS: CAPTF2 Mask            */
+
+#define ECAP_STATUS_CAPCMPF_Pos          (4)                                               /*!< ECAP_T::STATUS: CAPCMPF Position       */
+#define ECAP_STATUS_CAPCMPF_Msk          (0x1ul << ECAP_STATUS_CAPCMPF_Pos)                /*!< ECAP_T::STATUS: CAPCMPF Mask           */
+
+#define ECAP_STATUS_CAPOVF_Pos           (5)                                               /*!< ECAP_T::STATUS: CAPOVF Position        */
+#define ECAP_STATUS_CAPOVF_Msk           (0x1ul << ECAP_STATUS_CAPOVF_Pos)                 /*!< ECAP_T::STATUS: CAPOVF Mask            */
+
+#define ECAP_STATUS_CAP0_Pos             (6)                                               /*!< ECAP_T::STATUS: CAP0 Position          */
+#define ECAP_STATUS_CAP0_Msk             (0x1ul << ECAP_STATUS_CAP0_Pos)                   /*!< ECAP_T::STATUS: CAP0 Mask              */
+
+#define ECAP_STATUS_CAP1_Pos             (7)                                               /*!< ECAP_T::STATUS: CAP1 Position          */
+#define ECAP_STATUS_CAP1_Msk             (0x1ul << ECAP_STATUS_CAP1_Pos)                   /*!< ECAP_T::STATUS: CAP1 Mask              */
+
+#define ECAP_STATUS_CAP2_Pos             (8)                                               /*!< ECAP_T::STATUS: CAP2 Position          */
+#define ECAP_STATUS_CAP2_Msk             (0x1ul << ECAP_STATUS_CAP2_Pos)                   /*!< ECAP_T::STATUS: CAP2 Mask              */
+
+/**@}*/ /* ECAP_CONST */
+/**@}*/ /* end of ECAP register group */
+
+
+
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+/**
+    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+    Memory Mapped Structure for UART Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var UART_T::DAT
+     * Offset: 0x00  UART Receive/Transmit Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |Data Receive/Transmit Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing one byte to this register, the data byte will be stored in transmitter FIFO
+     * |        |          |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+     * |        |          |Read Operation:
+     * |        |          |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
+     * |[8]     |PARITY    |Parity Bit Receive/Transmit Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing to this bit, the parity bit will be stored in transmitter FIFO
+     * |        |          |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set,
+     * |        |          |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
+     * |        |          |Read Operation:
+     * |        |          |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
+     * |        |          |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
+     * @var UART_T::INTEN
+     * Offset: 0x04  UART Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIEN    |Receive Data Available Interrupt Enable Bit
+     * |        |          |0 = Receive data available interrupt Disabled.
+     * |        |          |1 = Receive data available interrupt Enabled.
+     * |[1]     |THREIEN   |Transmit Holding Register Empty Interrupt Enable Bit
+     * |        |          |0 = Transmit holding register empty interrupt Disabled.
+     * |        |          |1 = Transmit holding register empty interrupt Enabled.
+     * |[2]     |RLSIEN    |Receive Line Status Interrupt Enable Bit
+     * |        |          |0 = Receive Line Status interrupt Disabled.
+     * |        |          |1 = Receive Line Status interrupt Enabled.
+     * |[3]     |MODEMIEN  |Modem Status Interrupt Enable Bit
+     * |        |          |0 = Modem status interrupt Disabled.
+     * |        |          |1 = Modem status interrupt Enabled.
+     * |[4]     |RXTOIEN   |RX Time-out Interrupt Enable Bit
+     * |        |          |0 = RX time-out interrupt Disabled.
+     * |        |          |1 = RX time-out interrupt Enabled.
+     * |[5]     |BUFERRIEN |Buffer Error Interrupt Enable Bit
+     * |        |          |0 = Buffer error interrupt Disabled.
+     * |        |          |1 = Buffer error interrupt Enabled.
+     * |[6]     |WKIEN     |Wake-up Interrupt Enable Bit
+     * |        |          |0 = Wake-up Interrupt Disabled.
+     * |        |          |1 = Wake-up Interrupt Enabled.
+     * |[8]     |LINIEN    |LIN Bus Interrupt Enable Bit
+     * |        |          |0 = LIN bus interrupt Disabled.
+     * |        |          |1 = LIN bus interrupt Enabled.
+     * |        |          |Note: This bit is used for LIN function mode.
+     * |[11]    |TOCNTEN   |Receive Buffer Time-out Counter Enable Bit
+     * |        |          |0 = Receive Buffer Time-out counter Disabled.
+     * |        |          |1 = Receive Buffer Time-out counter Enabled.
+     * |[12]    |ATORTSEN  |nRTS Auto-flow Control Enable Bit
+     * |        |          |0 = nRTS auto-flow control Disabled.
+     * |        |          |1 = nRTS auto-flow control Enabled.
+     * |        |          |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+     * |[13]    |ATOCTSEN  |nCTS Auto-flow Control Enable Bit
+     * |        |          |0 = nCTS auto-flow control Disabled.
+     * |        |          |1 = nCTS auto-flow control Enabled.
+     * |        |          |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+     * |[14]    |TXPDMAEN  |TX PDMA Enable Bit
+     * |        |          |This bit can enable or disable TX PDMA service.
+     * |        |          |0 = TX PDMA Disabled.
+     * |        |          |1 = TX PDMA Enabled.
+     * |        |          |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+     * |        |          |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop
+     * |        |          |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
+     * |[15]    |RXPDMAEN  |RX PDMA Enable Bit
+     * |        |          |This bit can enable or disable RX PDMA service.
+     * |        |          |0 = RX PDMA Disabled.
+     * |        |          |1 = RX PDMA Enabled.
+     * |        |          |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+     * |        |          |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop
+     * |        |          |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
+     * |[18]    |ABRIEN    |Auto-baud Rate Interrupt Enable Bit
+     * |        |          |0 = Auto-baud rate interrupt Disabled.
+     * |        |          |1 = Auto-baud rate interrupt Enabled.
+     * |[22]    |TXENDIEN  |Transmitter Empty Interrupt Enable Bit
+     * |        |          |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
+     * |        |          |0 = Transmitter empty interrupt Disabled.
+     * |        |          |1 = Transmitter empty interrupt Enabled.
+     * @var UART_T::FIFO
+     * Offset: 0x08  UART FIFO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RXRST     |RX Field Software Reset
+     * |        |          |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the RX internal state machine and pointers.
+     * |        |          |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+     * |        |          |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
+     * |[2]     |TXRST     |TX Field Software Reset
+     * |        |          |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the TX internal state machine and pointers.
+     * |        |          |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+     * |        |          |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
+     * |[7:4]   |RFITL     |RX FIFO Interrupt Trigger Level
+     * |        |          |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+     * |        |          |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+     * |        |          |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+     * |        |          |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+     * |        |          |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+     * |        |          |Others = Reserved.
+     * |[8]     |RXOFF     |Receiver Disable Bit
+     * |        |          |The receiver is disabled or not (set 1 to disable receiver).
+     * |        |          |0 = Receiver Enabled.
+     * |        |          |1 = Receiver Disabled.
+     * |        |          |Note: This bit is used for RS-485 Normal Multi-drop mode
+     * |        |          |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+     * |[19:16] |RTSTRGLV  |nRTS Trigger Level for Auto-flow Control Use
+     * |        |          |0000 = nRTS Trigger Level is 1 byte.
+     * |        |          |0001 = nRTS Trigger Level is 4 bytes.
+     * |        |          |0010 = nRTS Trigger Level is 8 bytes.
+     * |        |          |0011 = nRTS Trigger Level is 14 bytes.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: This field is used for auto nRTS flow control.
+     * @var UART_T::LINE
+     * Offset: 0x0C  UART Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |WLS       |Word Length Selection
+     * |        |          |This field sets UART word length.
+     * |        |          |00 = 5 bits.
+     * |        |          |01 = 6 bits.
+     * |        |          |10 = 7 bits.
+     * |        |          |11 = 8 bits.
+     * |[2]     |NSB       |Number of 'STOP Bit'
+     * |        |          |0 = One 'STOP bit' is generated in the transmitted data.
+     * |        |          |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data
+     * |        |          |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data.
+     * |[3]     |PBE       |Parity Bit Enable Bit
+     * |        |          |0 = Parity bit generated Disabled.
+     * |        |          |1 = Parity bit generated Enabled.
+     * |        |          |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
+     * |[4]     |EPE       |Even Parity Enable Bit
+     * |        |          |0 = Odd number of logic '1's is transmitted and checked in each word.
+     * |        |          |1 = Even number of logic '1's is transmitted and checked in each word.
+     * |        |          |Note: This bit has effect only when PBE (UART_LINE[3]) is set.
+     * |[5]     |SPE       |Stick Parity Enable Bit
+     * |        |          |0 = Stick parity Disabled.
+     * |        |          |1 = Stick parity Enabled.
+     * |        |          |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0
+     * |        |          |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+     * |[6]     |BCB       |Break Control Bit
+     * |        |          |0 = Break Control Disabled.
+     * |        |          |1 = Break Control Enabled.
+     * |        |          |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)
+     * |        |          |This bit acts only on TX line and has no effect on the transmitter logic.
+     * |[7]     |PSS       |Parity Bit Source Selection
+     * |        |          |The parity bit can be selected to be generated and checked automatically or by software.
+     * |        |          |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.
+     * |        |          |1 = Parity bit generated and checked by software.
+     * |        |          |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
+     * |        |          |Note2: If PSS is 0, the parity bit is transmitted and checked automatically
+     * |        |          |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
+     * |[8]     |TXDINV    |TX Data Inverted
+     * |        |          |0 = Transmitted data signal inverted Disabled.
+     * |        |          |1 = Transmitted data signal inverted Enabled.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+     * |[9]     |RXDINV    |RX Data Inverted
+     * |        |          |0 = Received data signal inverted Disabled.
+     * |        |          |1 = Received data signal inverted Enabled.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+     * @var UART_T::MODEM
+     * Offset: 0x10  UART Modem Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RTS       |nRTS (Request-to-send) Signal Control
+     * |        |          |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+     * |        |          |0 = nRTS signal is active.
+     * |        |          |1 = nRTS signal is inactive.
+     * |        |          |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+     * |        |          |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+     * |[9]     |RTSACTLV  |nRTS Pin Active Level
+     * |        |          |This bit defines the active level state of nRTS pin output.
+     * |        |          |0 = nRTS pin output is high level active.
+     * |        |          |1 = nRTS pin output is low level active. (Default)
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |[13]    |RTSSTS    |nRTS Pin Status (Read Only)
+     * |        |          |This bit mirror from nRTS pin output of voltage logic status.
+     * |        |          |0 = nRTS pin output is low level voltage logic state.
+     * |        |          |1 = nRTS pin output is high level voltage logic state.
+     * @var UART_T::MODEMSTS
+     * Offset: 0x14  UART Modem Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTSDETF   |Detect nCTS State Change Flag
+     * |        |          |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+     * |        |          |0 = nCTS input has not change state.
+     * |        |          |1 = nCTS input has change state.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[4]     |CTSSTS    |nCTS Pin Status (Read Only)
+     * |        |          |This bit mirror from nCTS pin input of voltage logic status.
+     * |        |          |0 = nCTS pin input is low level voltage logic state.
+     * |        |          |1 = nCTS pin input is high level voltage logic state.
+     * |        |          |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
+     * |[8]     |CTSACTLV  |nCTS Pin Active Level
+     * |        |          |This bit defines the active level state of nCTS pin input.
+     * |        |          |0 = nCTS pin input is high level active.
+     * |        |          |1 = nCTS pin input is low level active. (Default)
+     * |        |          |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * @var UART_T::FIFOSTS
+     * Offset: 0x18  UART FIFO Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXOVIF    |RX Overflow Error Interrupt Flag
+     * |        |          |This bit is set when RX FIFO overflow.
+     * |        |          |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
+     * |        |          |0 = RX FIFO is not overflow.
+     * |        |          |1 = RX FIFO is overflow.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[1]     |ABRDIF    |Auto-baud Rate Detect Interrupt Flag
+     * |        |          |This bit is set to logic '1' when auto-baud rate detect function is finished.
+     * |        |          |0 = Auto-baud rate detect function is not finished.
+     * |        |          |1 = Auto-baud rate detect function is finished.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[2]     |ABRDTOIF  |Auto-baud Rate Detect Time-out Interrupt Flag
+     * |        |          |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
+     * |        |          |0 = Auto-baud rate counter is underflow.
+     * |        |          |1 = Auto-baud rate counter is overflow.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[3]     |ADDRDETF  |RS-485 Address Byte Detect Flag
+     * |        |          |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+     * |        |          |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+     * |        |          |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * |[4]     |PEF       |Parity Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
+     * |        |          |0 = No parity error is generated.
+     * |        |          |1 = Parity error is generated.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[5]     |FEF       |Framing Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
+     * |        |          |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = No framing error is generated.
+     * |        |          |1 = Framing error is generated.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[6]     |BIF       |Break Interrupt Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0)
+     * |        |          |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+     * |        |          |0 = No Break interrupt is generated.
+     * |        |          |1 = Break interrupt is generated.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[13:8]  |RXPTR     |RX FIFO Pointer (Read Only)
+     * |        |          |This field indicates the RX FIFO Buffer Pointer
+     * |        |          |When UART receives one byte from external device, RXPTR increases one
+     * |        |          |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+     * |        |          |The Maximum value shown in RXPTR is 15
+     * |        |          |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0
+     * |        |          |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15
+     * |[14]    |RXEMPTY   |Receiver FIFO Empty (Read Only)
+     * |        |          |This bit initiate RX FIFO empty or not.
+     * |        |          |0 = RX FIFO is not empty.
+     * |        |          |1 = RX FIFO is empty.
+     * |        |          |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high
+     * |        |          |It will be cleared when UART receives any new data.
+     * |[15]    |RXFULL    |Receiver FIFO Full (Read Only)
+     * |        |          |This bit initiates RX FIFO full or not.
+     * |        |          |0 = RX FIFO is not full.
+     * |        |          |1 = RX FIFO is full.
+     * |        |          |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+     * |[21:16] |TXPTR     |TX FIFO Pointer (Read Only)
+     * |        |          |This field indicates the TX FIFO Buffer Pointer
+     * |        |          |When CPU writes one byte into UART_DAT, TXPTR increases one
+     * |        |          |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+     * |        |          |The Maximum value shown in TXPTR is 15
+     * |        |          |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0
+     * |        |          |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15
+     * |[22]    |TXEMPTY   |Transmitter FIFO Empty (Read Only)
+     * |        |          |This bit indicates TX FIFO empty or not.
+     * |        |          |0 = TX FIFO is not empty.
+     * |        |          |1 = TX FIFO is empty.
+     * |        |          |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high
+     * |        |          |It will be cleared when writing data into UART_DAT (TX FIFO not empty).
+     * |[23]    |TXFULL    |Transmitter FIFO Full (Read Only)
+     * |        |          |This bit indicates TX FIFO full or not.
+     * |        |          |0 = TX FIFO is not full.
+     * |        |          |1 = TX FIFO is full.
+     * |        |          |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+     * |[24]    |TXOVIF    |TX Overflow Error Interrupt Flag
+     * |        |          |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+     * |        |          |0 = TX FIFO is not overflow.
+     * |        |          |1 = TX FIFO is overflow.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[28]    |TXEMPTYF  |Transmitter Empty Flag (Read Only)
+     * |        |          |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+     * |        |          |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.
+     * |        |          |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.
+     * |        |          |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+     * |[29]    |RXIDLE    |RX Idle Status (Read Only)
+     * |        |          |This bit is set by hardware when RX is idle.
+     * |        |          |0 = RX is busy.
+     * |        |          |1 = RX is idle. (Default)
+     * |[31]    |TXRXACT   |TX and RX Active Status (Read Only)
+     * |        |          |This bit indicates TX and RX are active or inactive.
+     * |        |          |0 = TX and RX are inactive.
+     * |        |          |1 = TX and RX are active. (Default)
+     * |        |          |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared
+     * |        |          |The UART controller can not transmit or receive data at this moment
+     * |        |          |Otherwise this bit is set.
+     * @var UART_T::INTSTS
+     * Offset: 0x1C  UART Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIF     |Receive Data Available Interrupt Flag
+     * |        |          |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set
+     * |        |          |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+     * |        |          |0 = No RDA interrupt flag is generated.
+     * |        |          |1 = RDA interrupt flag is generated.
+     * |        |          |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
+     * |[1]     |THREIF    |Transmit Holding Register Empty Interrupt Flag
+     * |        |          |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register
+     * |        |          |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+     * |        |          |0 = No THRE interrupt flag is generated.
+     * |        |          |1 = THRE interrupt flag is generated.
+     * |        |          |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+     * |[2]     |RLSIF     |Receive Line Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set)
+     * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+     * |        |          |0 = No RLS interrupt flag is generated.
+     * |        |          |1 = RLS interrupt flag is generated.
+     * |        |          |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit"
+     * |        |          |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+     * |        |          |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+     * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+     * |[3]     |MODEMIF   |MODEM Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1)
+     * |        |          |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+     * |        |          |0 = No Modem interrupt flag is generated.
+     * |        |          |1 = Modem interrupt flag is generated.
+     * |        |          |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+     * |[4]     |RXTOIF    |RX Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+     * |        |          |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
+     * |        |          |0 = No RX time-out interrupt flag is generated.
+     * |        |          |1 = RX time-out interrupt flag is generated.
+     * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+     * |[5]     |BUFERRIF  |Buffer Error Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+     * |        |          |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct
+     * |        |          |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+     * |        |          |0 = No buffer error interrupt flag is generated.
+     * |        |          |1 = Buffer error interrupt flag is generated.
+     * |        |          |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+     * |[6]     |WKIF      |UART Wake-up Interrupt Flag (Read Only)
+     * |        |          |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
+     * |        |          |0 = No UART wake-up interrupt flag is generated.
+     * |        |          |1 = UART wake-up interrupt flag is generated.
+     * |        |          |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
+     * |[7]     |LINIF     |LIN Bus Interrupt Flag
+     * |        |          |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
+     * |        |          |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+     * |        |          |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+     * |        |          |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+     * |        |          |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
+     * |[8]     |RDAINT    |Receive Data Available Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+     * |        |          |0 = No RDA interrupt is generated.
+     * |        |          |1 = RDA interrupt is generated.
+     * |[9]     |THREINT   |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
+     * |        |          |0 = No THRE interrupt is generated.
+     * |        |          |1 = THRE interrupt is generated.
+     * |[10]    |RLSINT    |Receive Line Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+     * |        |          |0 = No RLS interrupt is generated.
+     * |        |          |1 = RLS interrupt is generated.
+     * |[11]    |MODEMINT  |MODEM Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
+     * |        |          |0 = No Modem interrupt is generated.
+     * |        |          |1 = Modem interrupt is generated.
+     * |[12]    |RXTOINT   |RX Time-out Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+     * |        |          |0 = No RX time-out interrupt is generated.
+     * |        |          |1 = RX time-out interrupt is generated.
+     * |[13]    |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
+     * |        |          |0 = No buffer error interrupt is generated.
+     * |        |          |1 = Buffer error interrupt is generated.
+     * |[14]    |WKINT     |UART Wake-up Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
+     * |        |          |0 = No UART wake-up interrupt is generated.
+     * |        |          |1 = UART wake-up interrupt is generated.
+     * |[15]    |LININT    |LIN Bus Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
+     * |        |          |0 = No LIN Bus interrupt is generated.
+     * |        |          |1 = The LIN Bus interrupt is generated.
+     * |[18]    |HWRLSIF   |PDMA Mode Receive Line Status Flag (Read Only)
+     * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)
+     * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+     * |        |          |0 = No RLS interrupt flag is generated in PDMA mode.
+     * |        |          |1 = RLS interrupt flag is generated in PDMA mode.
+     * |        |          |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit".
+     * |        |          |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+     * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
+     * |[19]    |HWMODIF   |PDMA Mode MODEM Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1))
+     * |        |          |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+     * |        |          |0 = No Modem interrupt flag is generated in PDMA mode.
+     * |        |          |1 = Modem interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
+     * |[20]    |HWTOIF    |PDMA Mode RX Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+     * |        |          |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
+     * |        |          |0 = No RX time-out interrupt flag is generated in PDMA mode.
+     * |        |          |1 = RX time-out interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+     * |[21]    |HWBUFEIF  |PDMA Mode Buffer Error Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+     * |        |          |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct
+     * |        |          |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+     * |        |          |0 = No buffer error interrupt flag is generated in PDMA mode.
+     * |        |          |1 = Buffer error interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+     * |[22]    |TXENDIF   |Transmitter Empty Interrupt Flag
+     * |        |          |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)
+     * |        |          |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
+     * |        |          |0 = No transmitter empty interrupt flag is generated.
+     * |        |          |1 = Transmitter empty interrupt flag is generated.
+     * |        |          |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+     * |[26]    |HWRLSINT  |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+     * |        |          |0 = No RLS interrupt is generated in PDMA mode.
+     * |        |          |1 = RLS interrupt is generated in PDMA mode.
+     * |[27]    |HWMODINT  |PDMA Mode MODEM Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
+     * |        |          |0 = No Modem interrupt is generated in PDMA mode.
+     * |        |          |1 = Modem interrupt is generated in PDMA mode.
+     * |[28]    |HWTOINT   |PDMA Mode RX Time-out Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
+     * |        |          |0 = No RX time-out interrupt is generated in PDMA mode.
+     * |        |          |1 = RX time-out interrupt is generated in PDMA mode.
+     * |[29]    |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
+     * |        |          |0 = No buffer error interrupt is generated in PDMA mode.
+     * |        |          |1 = Buffer error interrupt is generated in PDMA mode.
+     * |[30]    |TXENDINT  |Transmitter Empty Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
+     * |        |          |0 = No Transmitter Empty interrupt is generated.
+     * |        |          |1 = Transmitter Empty interrupt is generated.
+     * |[31]    |ABRINT    |Auto-baud Rate Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
+     * |        |          |0 = No Auto-baud Rate interrupt is generated.
+     * |        |          |1 = The Auto-baud Rate interrupt is generated.
+     * @var UART_T::TOUT
+     * Offset: 0x20  UART Time-out Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TOIC      |Time-out Interrupt Comparator
+     * |        |          |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11])
+     * |        |          |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled
+     * |        |          |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4])
+     * |        |          |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255
+     * |        |          |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+     * |[15:8]  |DLY       |TX Delay Time Value
+     * |        |          |This field is used to programming the transfer delay time between the last stop bit and next start bit
+     * |        |          |The unit is bit time.
+     * @var UART_T::BAUD
+     * Offset: 0x24  UART Baud Rate Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |BRD       |Baud Rate Divider
+     * |        |          |The field indicates the baud rate divider
+     * |        |          |This filed is used in baud rate calculation
+     * |        |          |The detail description is shown in Table 7.15-4.
+     * |[27:24] |EDIVM1    |Extra Divider for BAUD Rate Mode 1
+     * |        |          |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2
+     * |        |          |The detail description is shown in Table 7.15-4
+     * |[28]    |BAUDM0    |BAUD Rate Mode Selection Bit 0
+     * |        |          |This bit is baud rate mode selection bit 0
+     * |        |          |UART provides three baud rate calculation modes
+     * |        |          |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode
+     * |        |          |The detail description is shown in Table 7.15-4.
+     * |[29]    |BAUDM1    |BAUD Rate Mode Selection Bit 1
+     * |        |          |This bit is baud rate mode selection bit 1
+     * |        |          |UART provides three baud rate calculation modes
+     * |        |          |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode
+     * |        |          |The detail description is shown in Table 7.15-4.
+     * |        |          |Note: In IrDA mode must be operated in mode 0.
+     * @var UART_T::IRDA
+     * Offset: 0x28  UART IrDA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXEN      |IrDA Receiver/Transmitter Selection Enable Bit
+     * |        |          |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+     * |        |          |1 = IrDA Transmitter Enabled and Receiver Disabled.
+     * |[5]     |TXINV     |IrDA Inverse Transmitting Output Signal
+     * |        |          |0 = None inverse transmitting signal. (Default).
+     * |        |          |1 = Inverse transmitting output signal.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+     * |[6]     |RXINV     |IrDA Inverse Receive Input Signal
+     * |        |          |0 = None inverse receiving input signal.
+     * |        |          |1 = Inverse receiving input signal. (Default)
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+     * @var UART_T::ALTCTL
+     * Offset: 0x2C  UART Alternate Control/Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |BRKFL     |UART LIN Break Field Length
+     * |        |          |This field indicates a 4-bit LIN TX break field count.
+     * |        |          |Note1: This break field length is BRKFL + 1.
+     * |        |          |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+     * |[6]     |LINRXEN   |LIN RX Enable Bit
+     * |        |          |0 = LIN RX mode Disabled.
+     * |        |          |1 = LIN RX mode Enabled.
+     * |[7]     |LINTXEN   |LIN TX Break Mode Enable Bit
+     * |        |          |0 = LIN TX Break mode Disabled.
+     * |        |          |1 = LIN TX Break mode Enabled.
+     * |        |          |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+     * |[8]     |RS485NMM  |RS-485 Normal Multi-drop Operation Mode (NMM)
+     * |        |          |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+     * |        |          |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+     * |        |          |Note: It cannot be active with RS-485_AAD operation mode.
+     * |[9]     |RS485AAD  |RS-485 Auto Address Detection Operation Mode (AAD)
+     * |        |          |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+     * |        |          |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+     * |        |          |Note: It cannot be active with RS-485_NMM operation mode.
+     * |[10]    |RS485AUD  |RS-485 Auto Direction Function (AUD)
+     * |        |          |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+     * |        |          |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+     * |        |          |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+     * |[15]    |ADDRDEN   |RS-485 Address Detection Enable Bit
+     * |        |          |This bit is used to enable RS-485 Address Detection mode.
+     * |        |          |0 = Address detection mode Disabled.
+     * |        |          |1 = Address detection mode Enabled.
+     * |        |          |Note: This bit is used for RS-485 any operation mode.
+     * |[17]    |ABRIF     |Auto-baud Rate Interrupt Flag (Read Only)
+     * |        |          |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+     * |        |          |0 = No auto-baud rate interrupt flag is generated.
+     * |        |          |1 = Auto-baud rate interrupt flag is generated.
+     * |        |          |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
+     * |[18]    |ABRDEN    |Auto-baud Rate Detect Enable Bit
+     * |        |          |0 = Auto-baud rate detect function Disabled.
+     * |        |          |1 = Auto-baud rate detect function Enabled.
+     * |        |          |Note : This bit is cleared automatically after auto-baud detection is finished.
+     * |[20:19] |ABRDBITS  |Auto-baud Rate Detect Bit Length
+     * |        |          |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+     * |        |          |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+     * |        |          |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+     * |        |          |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+     * |        |          |Note : The calculation of bit number includes the START bit.
+     * |[31:24] |ADDRMV    |Address Match Value
+     * |        |          |This field contains the RS-485 address match values.
+     * |        |          |Note: This field is used for RS-485 auto address detection mode.
+     * @var UART_T::FUNCSEL
+     * Offset: 0x30  UART Function Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |FUNCSEL   |Function Select
+     * |        |          |00 = UART function.
+     * |        |          |01 = LIN function.
+     * |        |          |10 = IrDA function.
+     * |        |          |11 = RS-485 function.
+     * |[3]     |TXRXDIS   |TX and RX Disable Bit
+     * |        |          |Setting this bit can disable TX and RX.
+     * |        |          |0 = TX and RX Enabled.
+     * |        |          |1 = TX and RX Disabled.
+     * |        |          |Note: The TX and RX will not disable immediately when this bit is set
+     * |        |          |The TX and RX complete current task before disable TX and RX
+     * |        |          |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * @var UART_T::LINCTL
+     * Offset: 0x34  UART LIN Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLVEN     |LIN Slave Mode Enable Bit
+     * |        |          |0 = LIN slave mode Disabled.
+     * |        |          |1 = LIN slave mode Enabled.
+     * |[1]     |SLVHDEN   |LIN Slave Header Detection Enable Bit
+     * |        |          |0 = LIN slave header detection Disabled.
+     * |        |          |1 = LIN slave header detection Enabled.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted
+     * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |[2]     |SLVAREN   |LIN Slave Automatic Resynchronization Mode Enable Bit
+     * |        |          |0 = LIN automatic resynchronization Disabled.
+     * |        |          |1 = LIN automatic resynchronization Enabled.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+     * |        |          |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+     * |[3]     |SLVDUEN   |LIN Slave Divider Update Method Enable Bit
+     * |        |          |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+     * |        |          |1 = UART_BAUD is updated at the next received character
+     * |        |          |User must set the bit before checksum reception.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: This bit used for LIN Slave Automatic Resynchronization mode
+     * |        |          |(for Non-Automatic Resynchronization mode, this bit should be kept cleared)
+     * |        |          |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+     * |[4]     |MUTE      |LIN Mute Mode Enable Bit
+     * |        |          |0 = LIN mute mode Disabled.
+     * |        |          |1 = LIN mute mode Enabled.
+     * |        |          |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode).
+     * |[8]     |SENDH     |LIN TX Send Header Enable Bit
+     * |        |          |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]).
+     * |        |          |0 = Send LIN TX header Disabled.
+     * |        |          |1 = Send LIN TX header Enabled.
+     * |        |          |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+     * |        |          |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+     * |[9]     |IDPEN     |LIN ID Parity Enable Bit
+     * |        |          |0 = LIN frame ID parity Disabled.
+     * |        |          |1 = LIN frame ID parity Enabled.
+     * |        |          |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.
+     * |        |          |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
+     * |[10]    |BRKDETEN  |LIN Break Detection Enable Bit
+     * |        |          |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field
+     * |        |          |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+     * |        |          |0 = LIN break detection Disabled .
+     * |        |          |1 = LIN break detection Enabled.
+     * |[11]    |LINRXOFF  |LIN Receiver Disable Bit
+     * |        |          |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.
+     * |        |          |0 = LIN receiver Enabled.
+     * |        |          |1 = LIN receiver Disabled.
+     * |        |          |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+     * |[12]    |BITERREN  |Bit Error Detect Enable Bit
+     * |        |          |0 = Bit error detection function Disabled.
+     * |        |          |1 = Bit error detection function Enabled.
+     * |        |          |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted
+     * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |[19:16] |BRKFL     |LIN Break Field Length
+     * |        |          |This field indicates a 4-bit LIN TX break field count.
+     * |        |          |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+     * |        |          |Note2: This break field length is BRKFL + 1.
+     * |        |          |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+     * |[21:20] |BSL       |LIN Break/Sync Delimiter Length
+     * |        |          |00 = The LIN break/sync delimiter length is 1-bit time.
+     * |        |          |01 = The LIN break/sync delimiter length is 2-bit time.
+     * |        |          |10 = The LIN break/sync delimiter length is 3-bit time.
+     * |        |          |11 = The LIN break/sync delimiter length is 4-bit time.
+     * |        |          |Note: This bit used for LIN master to sending header field.
+     * |[23:22] |HSEL      |LIN Header Select
+     * |        |          |00 = The LIN header includes 'break field'.
+     * |        |          |01 = The LIN header includes 'break field' and 'sync field'.
+     * |        |          |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).
+     * |[31:24] |PID       |LIN PID Bits
+     * |        |          |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+     * |        |          |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+     * |        |          |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+     * |        |          |Note2: This field can be used for LIN master mode or slave mode.
+     * @var UART_T::LINSTS
+     * Offset: 0x38  UART LIN Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLVHDETF  |LIN Slave Header Detection Flag
+     * |        |          |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+     * |        |          |0 = LIN header not detected.
+     * |        |          |1 = LIN header detected (break + sync + frame ID).
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+     * |        |          |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
+     * |[1]     |SLVHEF    |LIN Slave Header Error Flag
+     * |        |          |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it
+     * |        |          |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field',
+     * |        |          |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode',
+     * |        |          |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
+     * |        |          |0 = LIN header error not detected.
+     * |        |          |1 = LIN header error detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and
+     * |        |          |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+     * |[2]     |SLVIDPEF  |LIN Slave ID Parity Error Flag
+     * |        |          |This bit is set by hardware when receipted frame ID parity is not correct.
+     * |        |          |0 = No active.
+     * |        |          |1 = Receipted frame ID parity is not correct.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+     * |[3]     |SLVSYNCF  |LIN Slave Sync Field
+     * |        |          |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode
+     * |        |          |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+     * |        |          |0 = The current character is not at LIN sync state.
+     * |        |          |1 = The current character is at LIN sync state.
+     * |        |          |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |        |          |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+     * |[8]     |BRKDETF   |LIN Break Detection Flag
+     * |        |          |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+     * |        |          |0 = LIN break not detected.
+     * |        |          |1 = LIN break detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
+     * |[9]     |BITEF     |Bit Error Detect Status Flag
+     * |        |          |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
+     * |        |          |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |        |          |0 = Bit error not detected.
+     * |        |          |1 = Bit error detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+     * @var UART_T::BRCOMP
+     * Offset: 0x3C  UART Baud Rate Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |BRCOMP    |Baud Rate Compensation Patten
+     * |        |          |These 9-bits are used to define the relative bit is compensated or not.
+     * |        |          |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
+     * |[31]    |BRCOMPDEC |Baud Rate Compensation Decrease
+     * |        |          |0 = Positive (increase one module clock) compensation for each compensated bit.
+     * |        |          |1 = Negative (decrease one module clock) compensation for each compensated bit.
+     * @var UART_T::WKCTL
+     * Offset: 0x40  UART Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKCTSEN   |nCTS Wake-up Enable Bit
+     * |        |          |0 = nCTS Wake-up system function Disabled.
+     * |        |          |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.
+     * |        |          |nCTS change will wake-up system from Power-down mode.
+     * |[1]     |WKDATEN   |Incoming Data Wake-up Enable Bit
+     * |        |          |0 = Incoming data wake-up system function Disabled.
+     * |        |          |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.
+     * |        |          |incoming data will wake-up system from Power-down mode.
+     * |[2]     |WKRFRTEN  |Received Data FIFO Reached Threshold Wake-up Enable Bit
+     * |        |          |0 = Received Data FIFO reached threshold wake-up system function Disabled.
+     * |        |          |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.
+     * |        |          |in Power-down mode, Received Data FIFO reached threshold will wake-up system from
+     * |        |          |Power-down mode.
+     * |[3]     |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit
+     * |        |          |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.
+     * |        |          |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in.
+     * |        |          |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
+     * |        |          |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
+     * |        |          |and ADDRDEN (UART_ALTCTL[15]) is set to 1.
+     * |[4]     |WKTOUTEN  |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
+     * |        |          |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
+     * |        |          |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the.
+     * |        |          |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up
+     * |        |          |system from Power-down mode.
+     * |        |          |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
+     * @var UART_T::WKSTS
+     * Offset: 0x44  UART Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTSWKF    |nCTS Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by nCTS wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by nCTS wake-up.
+     * |        |          |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * |[1]     |DATWKF    |Incoming Data Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by data wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Incoming Data wake-up.
+     * |        |          |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * |[2]     |RFRTWKF   |Received Data FIFO Reached Threshold Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
+     * |        |          |wake-up .
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.
+     * |        |          |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * |[3]     |RS485WKF  |RS-485 Address Match (AAD Mode) Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.
+     * |        |          |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * |[4]     |TOUTWKF   |Received Data FIFO Threshold Time-out Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out
+     * |        |          |wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out.
+     * |        |          |wake-up.
+     * |        |          |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
+     * |        |          |Note2: This bit can be cleared by writing '1' to it.
+     * @var UART_T::DWKCOMP
+     * Offset: 0x48  UART Incoming Data Wake-up Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |STCOMP    |Start Bit Compensation Value
+     * |        |          |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
+     * |        |          |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
+     */
+    __IO uint32_t DAT;                   /*!< [0x0000] UART Receive/Transmit Buffer Register                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] UART Interrupt Enable Register                                   */
+    __IO uint32_t FIFO;                  /*!< [0x0008] UART FIFO Control Register                                       */
+    __IO uint32_t LINE;                  /*!< [0x000c] UART Line Control Register                                       */
+    __IO uint32_t MODEM;                 /*!< [0x0010] UART Modem Control Register                                      */
+    __IO uint32_t MODEMSTS;              /*!< [0x0014] UART Modem Status Register                                       */
+    __IO uint32_t FIFOSTS;               /*!< [0x0018] UART FIFO Status Register                                        */
+    __IO uint32_t INTSTS;                /*!< [0x001c] UART Interrupt Status Register                                   */
+    __IO uint32_t TOUT;                  /*!< [0x0020] UART Time-out Register                                           */
+    __IO uint32_t BAUD;                  /*!< [0x0024] UART Baud Rate Divider Register                                  */
+    __IO uint32_t IRDA;                  /*!< [0x0028] UART IrDA Control Register                                       */
+    __IO uint32_t ALTCTL;                /*!< [0x002c] UART Alternate Control/Status Register                           */
+    __IO uint32_t FUNCSEL;               /*!< [0x0030] UART Function Select Register                                    */
+    __IO uint32_t LINCTL;                /*!< [0x0034] UART LIN Control Register                                        */
+    __IO uint32_t LINSTS;                /*!< [0x0038] UART LIN Status Register                                         */
+    __IO uint32_t BRCOMP;                /*!< [0x003c] UART Baud Rate Compensation Register                             */
+    __IO uint32_t WKCTL;                 /*!< [0x0040] UART Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0044] UART Wake-up Status Register                                     */
+    __IO uint32_t DWKCOMP;               /*!< [0x0048] UART Incoming Data Wake-up Compensation Register                 */
+
+} UART_T;
+
+/**
+    @addtogroup UART_CONST UART Bit Field Definition
+    Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos                 (0)                                               /*!< UART_T::DAT: DAT Position              */
+#define UART_DAT_DAT_Msk                 (0xfful << UART_DAT_DAT_Pos)                      /*!< UART_T::DAT: DAT Mask                  */
+
+#define UART_DAT_PARITY_Pos              (8)                                               /*!< UART_T::DAT: PARITY Position           */
+#define UART_DAT_PARITY_Msk              (0x1ul << UART_DAT_PARITY_Pos)                    /*!< UART_T::DAT: PARITY Mask               */
+
+#define UART_INTEN_RDAIEN_Pos            (0)                                               /*!< UART_T::INTEN: RDAIEN Position         */
+#define UART_INTEN_RDAIEN_Msk            (0x1ul << UART_INTEN_RDAIEN_Pos)                  /*!< UART_T::INTEN: RDAIEN Mask             */
+
+#define UART_INTEN_THREIEN_Pos           (1)                                               /*!< UART_T::INTEN: THREIEN Position        */
+#define UART_INTEN_THREIEN_Msk           (0x1ul << UART_INTEN_THREIEN_Pos)                 /*!< UART_T::INTEN: THREIEN Mask            */
+
+#define UART_INTEN_RLSIEN_Pos            (2)                                               /*!< UART_T::INTEN: RLSIEN Position         */
+#define UART_INTEN_RLSIEN_Msk            (0x1ul << UART_INTEN_RLSIEN_Pos)                  /*!< UART_T::INTEN: RLSIEN Mask             */
+
+#define UART_INTEN_MODEMIEN_Pos          (3)                                               /*!< UART_T::INTEN: MODEMIEN Position       */
+#define UART_INTEN_MODEMIEN_Msk          (0x1ul << UART_INTEN_MODEMIEN_Pos)                /*!< UART_T::INTEN: MODEMIEN Mask           */
+
+#define UART_INTEN_RXTOIEN_Pos           (4)                                               /*!< UART_T::INTEN: RXTOIEN Position        */
+#define UART_INTEN_RXTOIEN_Msk           (0x1ul << UART_INTEN_RXTOIEN_Pos)                 /*!< UART_T::INTEN: RXTOIEN Mask            */
+
+#define UART_INTEN_BUFERRIEN_Pos         (5)                                               /*!< UART_T::INTEN: BUFERRIEN Position      */
+#define UART_INTEN_BUFERRIEN_Msk         (0x1ul << UART_INTEN_BUFERRIEN_Pos)               /*!< UART_T::INTEN: BUFERRIEN Mask          */
+
+#define UART_INTEN_WKIEN_Pos             (6)                                               /*!< UART_T::INTEN: WKIEN Position          */
+#define UART_INTEN_WKIEN_Msk             (0x1ul << UART_INTEN_WKIEN_Pos)                   /*!< UART_T::INTEN: WKIEN Mask              */
+
+#define UART_INTEN_LINIEN_Pos            (8)                                               /*!< UART_T::INTEN: LINIEN Position         */
+#define UART_INTEN_LINIEN_Msk            (0x1ul << UART_INTEN_LINIEN_Pos)                  /*!< UART_T::INTEN: LINIEN Mask             */
+
+#define UART_INTEN_TOCNTEN_Pos           (11)                                              /*!< UART_T::INTEN: TOCNTEN Position        */
+#define UART_INTEN_TOCNTEN_Msk           (0x1ul << UART_INTEN_TOCNTEN_Pos)                 /*!< UART_T::INTEN: TOCNTEN Mask            */
+
+#define UART_INTEN_ATORTSEN_Pos          (12)                                              /*!< UART_T::INTEN: ATORTSEN Position       */
+#define UART_INTEN_ATORTSEN_Msk          (0x1ul << UART_INTEN_ATORTSEN_Pos)                /*!< UART_T::INTEN: ATORTSEN Mask           */
+
+#define UART_INTEN_ATOCTSEN_Pos          (13)                                              /*!< UART_T::INTEN: ATOCTSEN Position       */
+#define UART_INTEN_ATOCTSEN_Msk          (0x1ul << UART_INTEN_ATOCTSEN_Pos)                /*!< UART_T::INTEN: ATOCTSEN Mask           */
+
+#define UART_INTEN_TXPDMAEN_Pos          (14)                                              /*!< UART_T::INTEN: TXPDMAEN Position       */
+#define UART_INTEN_TXPDMAEN_Msk          (0x1ul << UART_INTEN_TXPDMAEN_Pos)                /*!< UART_T::INTEN: TXPDMAEN Mask           */
+
+#define UART_INTEN_RXPDMAEN_Pos          (15)                                              /*!< UART_T::INTEN: RXPDMAEN Position       */
+#define UART_INTEN_RXPDMAEN_Msk          (0x1ul << UART_INTEN_RXPDMAEN_Pos)                /*!< UART_T::INTEN: RXPDMAEN Mask           */
+
+#define UART_INTEN_ABRIEN_Pos            (18)                                              /*!< UART_T::INTEN: ABRIEN Position         */
+#define UART_INTEN_ABRIEN_Msk            (0x1ul << UART_INTEN_ABRIEN_Pos)                  /*!< UART_T::INTEN: ABRIEN Mask             */
+
+#define UART_INTEN_TXENDIEN_Pos          (22)                                              /*!< UART_T::INTEN: TXENDIEN Position       */
+#define UART_INTEN_TXENDIEN_Msk          (0x1ul << UART_INTEN_TXENDIEN_Pos)                /*!< UART_T::INTEN: TXENDIEN Mask           */
+
+#define UART_FIFO_RXRST_Pos              (1)                                               /*!< UART_T::FIFO: RXRST Position           */
+#define UART_FIFO_RXRST_Msk              (0x1ul << UART_FIFO_RXRST_Pos)                    /*!< UART_T::FIFO: RXRST Mask               */
+
+#define UART_FIFO_TXRST_Pos              (2)                                               /*!< UART_T::FIFO: TXRST Position           */
+#define UART_FIFO_TXRST_Msk              (0x1ul << UART_FIFO_TXRST_Pos)                    /*!< UART_T::FIFO: TXRST Mask               */
+
+#define UART_FIFO_RFITL_Pos              (4)                                               /*!< UART_T::FIFO: RFITL Position           */
+#define UART_FIFO_RFITL_Msk              (0xful << UART_FIFO_RFITL_Pos)                    /*!< UART_T::FIFO: RFITL Mask               */
+
+#define UART_FIFO_RXOFF_Pos              (8)                                               /*!< UART_T::FIFO: RXOFF Position           */
+#define UART_FIFO_RXOFF_Msk              (0x1ul << UART_FIFO_RXOFF_Pos)                    /*!< UART_T::FIFO: RXOFF Mask               */
+
+#define UART_FIFO_RTSTRGLV_Pos           (16)                                              /*!< UART_T::FIFO: RTSTRGLV Position        */
+#define UART_FIFO_RTSTRGLV_Msk           (0xful << UART_FIFO_RTSTRGLV_Pos)                 /*!< UART_T::FIFO: RTSTRGLV Mask            */
+
+#define UART_LINE_WLS_Pos                (0)                                               /*!< UART_T::LINE: WLS Position             */
+#define UART_LINE_WLS_Msk                (0x3ul << UART_LINE_WLS_Pos)                      /*!< UART_T::LINE: WLS Mask                 */
+
+#define UART_LINE_NSB_Pos                (2)                                               /*!< UART_T::LINE: NSB Position             */
+#define UART_LINE_NSB_Msk                (0x1ul << UART_LINE_NSB_Pos)                      /*!< UART_T::LINE: NSB Mask                 */
+
+#define UART_LINE_PBE_Pos                (3)                                               /*!< UART_T::LINE: PBE Position             */
+#define UART_LINE_PBE_Msk                (0x1ul << UART_LINE_PBE_Pos)                      /*!< UART_T::LINE: PBE Mask                 */
+
+#define UART_LINE_EPE_Pos                (4)                                               /*!< UART_T::LINE: EPE Position             */
+#define UART_LINE_EPE_Msk                (0x1ul << UART_LINE_EPE_Pos)                      /*!< UART_T::LINE: EPE Mask                 */
+
+#define UART_LINE_SPE_Pos                (5)                                               /*!< UART_T::LINE: SPE Position             */
+#define UART_LINE_SPE_Msk                (0x1ul << UART_LINE_SPE_Pos)                      /*!< UART_T::LINE: SPE Mask                 */
+
+#define UART_LINE_BCB_Pos                (6)                                               /*!< UART_T::LINE: BCB Position             */
+#define UART_LINE_BCB_Msk                (0x1ul << UART_LINE_BCB_Pos)                      /*!< UART_T::LINE: BCB Mask                 */
+
+#define UART_LINE_PSS_Pos                (7)                                               /*!< UART_T::LINE: PSS Position             */
+#define UART_LINE_PSS_Msk                (0x1ul << UART_LINE_PSS_Pos)                      /*!< UART_T::LINE: PSS Mask                 */
+
+#define UART_LINE_TXDINV_Pos             (8)                                               /*!< UART_T::LINE: TXDINV Position          */
+#define UART_LINE_TXDINV_Msk             (0x1ul << UART_LINE_TXDINV_Pos)                   /*!< UART_T::LINE: TXDINV Mask              */
+
+#define UART_LINE_RXDINV_Pos             (9)                                               /*!< UART_T::LINE: RXDINV Position          */
+#define UART_LINE_RXDINV_Msk             (0x1ul << UART_LINE_RXDINV_Pos)                   /*!< UART_T::LINE: RXDINV Mask              */
+
+#define UART_MODEM_RTS_Pos               (1)                                               /*!< UART_T::MODEM: RTS Position            */
+#define UART_MODEM_RTS_Msk               (0x1ul << UART_MODEM_RTS_Pos)                     /*!< UART_T::MODEM: RTS Mask                */
+
+#define UART_MODEM_RTSACTLV_Pos          (9)                                               /*!< UART_T::MODEM: RTSACTLV Position       */
+#define UART_MODEM_RTSACTLV_Msk          (0x1ul << UART_MODEM_RTSACTLV_Pos)                /*!< UART_T::MODEM: RTSACTLV Mask           */
+
+#define UART_MODEM_RTSSTS_Pos            (13)                                              /*!< UART_T::MODEM: RTSSTS Position         */
+#define UART_MODEM_RTSSTS_Msk            (0x1ul << UART_MODEM_RTSSTS_Pos)                  /*!< UART_T::MODEM: RTSSTS Mask             */
+
+#define UART_MODEMSTS_CTSDETF_Pos        (0)                                               /*!< UART_T::MODEMSTS: CTSDETF Position     */
+#define UART_MODEMSTS_CTSDETF_Msk        (0x1ul << UART_MODEMSTS_CTSDETF_Pos)              /*!< UART_T::MODEMSTS: CTSDETF Mask         */
+
+#define UART_MODEMSTS_CTSSTS_Pos         (4)                                               /*!< UART_T::MODEMSTS: CTSSTS Position      */
+#define UART_MODEMSTS_CTSSTS_Msk         (0x1ul << UART_MODEMSTS_CTSSTS_Pos)               /*!< UART_T::MODEMSTS: CTSSTS Mask          */
+
+#define UART_MODEMSTS_CTSACTLV_Pos       (8)                                               /*!< UART_T::MODEMSTS: CTSACTLV Position    */
+#define UART_MODEMSTS_CTSACTLV_Msk       (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)             /*!< UART_T::MODEMSTS: CTSACTLV Mask        */
+
+#define UART_FIFOSTS_RXOVIF_Pos          (0)                                               /*!< UART_T::FIFOSTS: RXOVIF Position       */
+#define UART_FIFOSTS_RXOVIF_Msk          (0x1ul << UART_FIFOSTS_RXOVIF_Pos)                /*!< UART_T::FIFOSTS: RXOVIF Mask           */
+
+#define UART_FIFOSTS_ABRDIF_Pos          (1)                                               /*!< UART_T::FIFOSTS: ABRDIF Position       */
+#define UART_FIFOSTS_ABRDIF_Msk          (0x1ul << UART_FIFOSTS_ABRDIF_Pos)                /*!< UART_T::FIFOSTS: ABRDIF Mask           */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos        (2)                                               /*!< UART_T::FIFOSTS: ABRDTOIF Position     */
+#define UART_FIFOSTS_ABRDTOIF_Msk        (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos)              /*!< UART_T::FIFOSTS: ABRDTOIF Mask         */
+
+#define UART_FIFOSTS_ADDRDETF_Pos        (3)                                               /*!< UART_T::FIFOSTS: ADDRDETF Position     */
+#define UART_FIFOSTS_ADDRDETF_Msk        (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)              /*!< UART_T::FIFOSTS: ADDRDETF Mask         */
+
+#define UART_FIFOSTS_PEF_Pos             (4)                                               /*!< UART_T::FIFOSTS: PEF Position          */
+#define UART_FIFOSTS_PEF_Msk             (0x1ul << UART_FIFOSTS_PEF_Pos)                   /*!< UART_T::FIFOSTS: PEF Mask              */
+
+#define UART_FIFOSTS_FEF_Pos             (5)                                               /*!< UART_T::FIFOSTS: FEF Position          */
+#define UART_FIFOSTS_FEF_Msk             (0x1ul << UART_FIFOSTS_FEF_Pos)                   /*!< UART_T::FIFOSTS: FEF Mask              */
+
+#define UART_FIFOSTS_BIF_Pos             (6)                                               /*!< UART_T::FIFOSTS: BIF Position          */
+#define UART_FIFOSTS_BIF_Msk             (0x1ul << UART_FIFOSTS_BIF_Pos)                   /*!< UART_T::FIFOSTS: BIF Mask              */
+
+#define UART_FIFOSTS_RXPTR_Pos           (8)                                               /*!< UART_T::FIFOSTS: RXPTR Position        */
+#define UART_FIFOSTS_RXPTR_Msk           (0x3ful << UART_FIFOSTS_RXPTR_Pos)                /*!< UART_T::FIFOSTS: RXPTR Mask            */
+
+#define UART_FIFOSTS_RXEMPTY_Pos         (14)                                              /*!< UART_T::FIFOSTS: RXEMPTY Position      */
+#define UART_FIFOSTS_RXEMPTY_Msk         (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)               /*!< UART_T::FIFOSTS: RXEMPTY Mask          */
+
+#define UART_FIFOSTS_RXFULL_Pos          (15)                                              /*!< UART_T::FIFOSTS: RXFULL Position       */
+#define UART_FIFOSTS_RXFULL_Msk          (0x1ul << UART_FIFOSTS_RXFULL_Pos)                /*!< UART_T::FIFOSTS: RXFULL Mask           */
+
+#define UART_FIFOSTS_TXPTR_Pos           (16)                                              /*!< UART_T::FIFOSTS: TXPTR Position        */
+#define UART_FIFOSTS_TXPTR_Msk           (0x3ful << UART_FIFOSTS_TXPTR_Pos)                /*!< UART_T::FIFOSTS: TXPTR Mask            */
+
+#define UART_FIFOSTS_TXEMPTY_Pos         (22)                                              /*!< UART_T::FIFOSTS: TXEMPTY Position      */
+#define UART_FIFOSTS_TXEMPTY_Msk         (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)               /*!< UART_T::FIFOSTS: TXEMPTY Mask          */
+
+#define UART_FIFOSTS_TXFULL_Pos          (23)                                              /*!< UART_T::FIFOSTS: TXFULL Position       */
+#define UART_FIFOSTS_TXFULL_Msk          (0x1ul << UART_FIFOSTS_TXFULL_Pos)                /*!< UART_T::FIFOSTS: TXFULL Mask           */
+
+#define UART_FIFOSTS_TXOVIF_Pos          (24)                                              /*!< UART_T::FIFOSTS: TXOVIF Position       */
+#define UART_FIFOSTS_TXOVIF_Msk          (0x1ul << UART_FIFOSTS_TXOVIF_Pos)                /*!< UART_T::FIFOSTS: TXOVIF Mask           */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos        (28)                                              /*!< UART_T::FIFOSTS: TXEMPTYF Position     */
+#define UART_FIFOSTS_TXEMPTYF_Msk        (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)              /*!< UART_T::FIFOSTS: TXEMPTYF Mask         */
+
+#define UART_FIFOSTS_RXIDLE_Pos          (29)                                              /*!< UART_T::FIFOSTS: RXIDLE Position       */
+#define UART_FIFOSTS_RXIDLE_Msk          (0x1ul << UART_FIFOSTS_RXIDLE_Pos)                /*!< UART_T::FIFOSTS: RXIDLE Mask           */
+
+#define UART_FIFOSTS_TXRXACT_Pos         (31)                                              /*!< UART_T::FIFOSTS: TXRXACT Position      */
+#define UART_FIFOSTS_TXRXACT_Msk         (0x1ul << UART_FIFOSTS_TXRXACT_Pos)               /*!< UART_T::FIFOSTS: TXRXACT Mask          */
+
+#define UART_INTSTS_RDAIF_Pos            (0)                                               /*!< UART_T::INTSTS: RDAIF Position         */
+#define UART_INTSTS_RDAIF_Msk            (0x1ul << UART_INTSTS_RDAIF_Pos)                  /*!< UART_T::INTSTS: RDAIF Mask             */
+
+#define UART_INTSTS_THREIF_Pos           (1)                                               /*!< UART_T::INTSTS: THREIF Position        */
+#define UART_INTSTS_THREIF_Msk           (0x1ul << UART_INTSTS_THREIF_Pos)                 /*!< UART_T::INTSTS: THREIF Mask            */
+
+#define UART_INTSTS_RLSIF_Pos            (2)                                               /*!< UART_T::INTSTS: RLSIF Position         */
+#define UART_INTSTS_RLSIF_Msk            (0x1ul << UART_INTSTS_RLSIF_Pos)                  /*!< UART_T::INTSTS: RLSIF Mask             */
+
+#define UART_INTSTS_MODEMIF_Pos          (3)                                               /*!< UART_T::INTSTS: MODEMIF Position       */
+#define UART_INTSTS_MODEMIF_Msk          (0x1ul << UART_INTSTS_MODEMIF_Pos)                /*!< UART_T::INTSTS: MODEMIF Mask           */
+
+#define UART_INTSTS_RXTOIF_Pos           (4)                                               /*!< UART_T::INTSTS: RXTOIF Position        */
+#define UART_INTSTS_RXTOIF_Msk           (0x1ul << UART_INTSTS_RXTOIF_Pos)                 /*!< UART_T::INTSTS: RXTOIF Mask            */
+
+#define UART_INTSTS_BUFERRIF_Pos         (5)                                               /*!< UART_T::INTSTS: BUFERRIF Position      */
+#define UART_INTSTS_BUFERRIF_Msk         (0x1ul << UART_INTSTS_BUFERRIF_Pos)               /*!< UART_T::INTSTS: BUFERRIF Mask          */
+
+#define UART_INTSTS_WKIF_Pos             (6)                                               /*!< UART_T::INTSTS: WKIF Position          */
+#define UART_INTSTS_WKIF_Msk             (0x1ul << UART_INTSTS_WKIF_Pos)                   /*!< UART_T::INTSTS: WKIF Mask              */
+
+#define UART_INTSTS_LINIF_Pos            (7)                                               /*!< UART_T::INTSTS: LINIF Position         */
+#define UART_INTSTS_LINIF_Msk            (0x1ul << UART_INTSTS_LINIF_Pos)                  /*!< UART_T::INTSTS: LINIF Mask             */
+
+#define UART_INTSTS_RDAINT_Pos           (8)                                               /*!< UART_T::INTSTS: RDAINT Position        */
+#define UART_INTSTS_RDAINT_Msk           (0x1ul << UART_INTSTS_RDAINT_Pos)                 /*!< UART_T::INTSTS: RDAINT Mask            */
+
+#define UART_INTSTS_THREINT_Pos          (9)                                               /*!< UART_T::INTSTS: THREINT Position       */
+#define UART_INTSTS_THREINT_Msk          (0x1ul << UART_INTSTS_THREINT_Pos)                /*!< UART_T::INTSTS: THREINT Mask           */
+
+#define UART_INTSTS_RLSINT_Pos           (10)                                              /*!< UART_T::INTSTS: RLSINT Position        */
+#define UART_INTSTS_RLSINT_Msk           (0x1ul << UART_INTSTS_RLSINT_Pos)                 /*!< UART_T::INTSTS: RLSINT Mask            */
+
+#define UART_INTSTS_MODEMINT_Pos         (11)                                              /*!< UART_T::INTSTS: MODEMINT Position      */
+#define UART_INTSTS_MODEMINT_Msk         (0x1ul << UART_INTSTS_MODEMINT_Pos)               /*!< UART_T::INTSTS: MODEMINT Mask          */
+
+#define UART_INTSTS_RXTOINT_Pos          (12)                                              /*!< UART_T::INTSTS: RXTOINT Position       */
+#define UART_INTSTS_RXTOINT_Msk          (0x1ul << UART_INTSTS_RXTOINT_Pos)                /*!< UART_T::INTSTS: RXTOINT Mask           */
+
+#define UART_INTSTS_BUFERRINT_Pos        (13)                                              /*!< UART_T::INTSTS: BUFERRINT Position     */
+#define UART_INTSTS_BUFERRINT_Msk        (0x1ul << UART_INTSTS_BUFERRINT_Pos)              /*!< UART_T::INTSTS: BUFERRINT Mask         */
+
+#define UART_INTSTS_WKINT_Pos            (14)                                              /*!< UART_T::INTSTS: WKINT Position         */
+#define UART_INTSTS_WKINT_Msk            (0x1ul << UART_INTSTS_WKINT_Pos)                  /*!< UART_T::INTSTS: WKINT Mask             */
+
+#define UART_INTSTS_LININT_Pos           (15)                                              /*!< UART_T::INTSTS: LININT Position        */
+#define UART_INTSTS_LININT_Msk           (0x1ul << UART_INTSTS_LININT_Pos)                 /*!< UART_T::INTSTS: LININT Mask            */
+
+#define UART_INTSTS_HWRLSIF_Pos          (18)                                              /*!< UART_T::INTSTS: HWRLSIF Position       */
+#define UART_INTSTS_HWRLSIF_Msk          (0x1ul << UART_INTSTS_HWRLSIF_Pos)                /*!< UART_T::INTSTS: HWRLSIF Mask           */
+
+#define UART_INTSTS_HWMODIF_Pos          (19)                                              /*!< UART_T::INTSTS: HWMODIF Position       */
+#define UART_INTSTS_HWMODIF_Msk          (0x1ul << UART_INTSTS_HWMODIF_Pos)                /*!< UART_T::INTSTS: HWMODIF Mask           */
+
+#define UART_INTSTS_HWTOIF_Pos           (20)                                              /*!< UART_T::INTSTS: HWTOIF Position        */
+#define UART_INTSTS_HWTOIF_Msk           (0x1ul << UART_INTSTS_HWTOIF_Pos)                 /*!< UART_T::INTSTS: HWTOIF Mask            */
+
+#define UART_INTSTS_HWBUFEIF_Pos         (21)                                              /*!< UART_T::INTSTS: HWBUFEIF Position      */
+#define UART_INTSTS_HWBUFEIF_Msk         (0x1ul << UART_INTSTS_HWBUFEIF_Pos)               /*!< UART_T::INTSTS: HWBUFEIF Mask          */
+
+#define UART_INTSTS_TXENDIF_Pos          (22)                                              /*!< UART_T::INTSTS: TXENDIF Position       */
+#define UART_INTSTS_TXENDIF_Msk          (0x1ul << UART_INTSTS_TXENDIF_Pos)                /*!< UART_T::INTSTS: TXENDIF Mask           */
+
+#define UART_INTSTS_HWRLSINT_Pos         (26)                                              /*!< UART_T::INTSTS: HWRLSINT Position      */
+#define UART_INTSTS_HWRLSINT_Msk         (0x1ul << UART_INTSTS_HWRLSINT_Pos)               /*!< UART_T::INTSTS: HWRLSINT Mask          */
+
+#define UART_INTSTS_HWMODINT_Pos         (27)                                              /*!< UART_T::INTSTS: HWMODINT Position      */
+#define UART_INTSTS_HWMODINT_Msk         (0x1ul << UART_INTSTS_HWMODINT_Pos)               /*!< UART_T::INTSTS: HWMODINT Mask          */
+
+#define UART_INTSTS_HWTOINT_Pos          (28)                                              /*!< UART_T::INTSTS: HWTOINT Position       */
+#define UART_INTSTS_HWTOINT_Msk          (0x1ul << UART_INTSTS_HWTOINT_Pos)                /*!< UART_T::INTSTS: HWTOINT Mask           */
+
+#define UART_INTSTS_HWBUFEINT_Pos        (29)                                              /*!< UART_T::INTSTS: HWBUFEINT Position     */
+#define UART_INTSTS_HWBUFEINT_Msk        (0x1ul << UART_INTSTS_HWBUFEINT_Pos)              /*!< UART_T::INTSTS: HWBUFEINT Mask         */
+
+#define UART_INTSTS_TXENDINT_Pos         (30)                                              /*!< UART_T::INTSTS: TXENDINT Position      */
+#define UART_INTSTS_TXENDINT_Msk         (0x1ul << UART_INTSTS_TXENDINT_Pos)               /*!< UART_T::INTSTS: TXENDINT Mask          */
+
+#define UART_INTSTS_ABRINT_Pos           (31)                                              /*!< UART_T::INTSTS: ABRINT Position        */
+#define UART_INTSTS_ABRINT_Msk           (0x1ul << UART_INTSTS_ABRINT_Pos)                 /*!< UART_T::INTSTS: ABRINT Mask            */
+
+#define UART_TOUT_TOIC_Pos               (0)                                               /*!< UART_T::TOUT: TOIC Position            */
+#define UART_TOUT_TOIC_Msk               (0xfful << UART_TOUT_TOIC_Pos)                    /*!< UART_T::TOUT: TOIC Mask                */
+
+#define UART_TOUT_DLY_Pos                (8)                                               /*!< UART_T::TOUT: DLY Position             */
+#define UART_TOUT_DLY_Msk                (0xfful << UART_TOUT_DLY_Pos)                     /*!< UART_T::TOUT: DLY Mask                 */
+
+#define UART_BAUD_BRD_Pos                (0)                                               /*!< UART_T::BAUD: BRD Position             */
+#define UART_BAUD_BRD_Msk                (0xfffful << UART_BAUD_BRD_Pos)                   /*!< UART_T::BAUD: BRD Mask                 */
+
+#define UART_BAUD_EDIVM1_Pos             (24)                                              /*!< UART_T::BAUD: EDIVM1 Position          */
+#define UART_BAUD_EDIVM1_Msk             (0xful << UART_BAUD_EDIVM1_Pos)                   /*!< UART_T::BAUD: EDIVM1 Mask              */
+
+#define UART_BAUD_BAUDM0_Pos             (28)                                              /*!< UART_T::BAUD: BAUDM0 Position          */
+#define UART_BAUD_BAUDM0_Msk             (0x1ul << UART_BAUD_BAUDM0_Pos)                   /*!< UART_T::BAUD: BAUDM0 Mask              */
+
+#define UART_BAUD_BAUDM1_Pos             (29)                                              /*!< UART_T::BAUD: BAUDM1 Position          */
+#define UART_BAUD_BAUDM1_Msk             (0x1ul << UART_BAUD_BAUDM1_Pos)                   /*!< UART_T::BAUD: BAUDM1 Mask              */
+
+#define UART_IRDA_TXEN_Pos               (1)                                               /*!< UART_T::IRDA: TXEN Position            */
+#define UART_IRDA_TXEN_Msk               (0x1ul << UART_IRDA_TXEN_Pos)                     /*!< UART_T::IRDA: TXEN Mask                */
+
+#define UART_IRDA_TXINV_Pos              (5)                                               /*!< UART_T::IRDA: TXINV Position           */
+#define UART_IRDA_TXINV_Msk              (0x1ul << UART_IRDA_TXINV_Pos)                    /*!< UART_T::IRDA: TXINV Mask               */
+
+#define UART_IRDA_RXINV_Pos              (6)                                               /*!< UART_T::IRDA: RXINV Position           */
+#define UART_IRDA_RXINV_Msk              (0x1ul << UART_IRDA_RXINV_Pos)                    /*!< UART_T::IRDA: RXINV Mask               */
+
+#define UART_ALTCTL_BRKFL_Pos            (0)                                               /*!< UART_T::ALTCTL: BRKFL Position         */
+#define UART_ALTCTL_BRKFL_Msk            (0xful << UART_ALTCTL_BRKFL_Pos)                  /*!< UART_T::ALTCTL: BRKFL Mask             */
+
+#define UART_ALTCTL_LINRXEN_Pos          (6)                                               /*!< UART_T::ALTCTL: LINRXEN Position       */
+#define UART_ALTCTL_LINRXEN_Msk          (0x1ul << UART_ALTCTL_LINRXEN_Pos)                /*!< UART_T::ALTCTL: LINRXEN Mask           */
+
+#define UART_ALTCTL_LINTXEN_Pos          (7)                                               /*!< UART_T::ALTCTL: LINTXEN Position       */
+#define UART_ALTCTL_LINTXEN_Msk          (0x1ul << UART_ALTCTL_LINTXEN_Pos)                /*!< UART_T::ALTCTL: LINTXEN Mask           */
+
+#define UART_ALTCTL_RS485NMM_Pos         (8)                                               /*!< UART_T::ALTCTL: RS485NMM Position      */
+#define UART_ALTCTL_RS485NMM_Msk         (0x1ul << UART_ALTCTL_RS485NMM_Pos)               /*!< UART_T::ALTCTL: RS485NMM Mask          */
+
+#define UART_ALTCTL_RS485AAD_Pos         (9)                                               /*!< UART_T::ALTCTL: RS485AAD Position      */
+#define UART_ALTCTL_RS485AAD_Msk         (0x1ul << UART_ALTCTL_RS485AAD_Pos)               /*!< UART_T::ALTCTL: RS485AAD Mask          */
+
+#define UART_ALTCTL_RS485AUD_Pos         (10)                                              /*!< UART_T::ALTCTL: RS485AUD Position      */
+#define UART_ALTCTL_RS485AUD_Msk         (0x1ul << UART_ALTCTL_RS485AUD_Pos)               /*!< UART_T::ALTCTL: RS485AUD Mask          */
+
+#define UART_ALTCTL_ADDRDEN_Pos          (15)                                              /*!< UART_T::ALTCTL: ADDRDEN Position       */
+#define UART_ALTCTL_ADDRDEN_Msk          (0x1ul << UART_ALTCTL_ADDRDEN_Pos)                /*!< UART_T::ALTCTL: ADDRDEN Mask           */
+
+#define UART_ALTCTL_ABRIF_Pos            (17)                                              /*!< UART_T::ALTCTL: ABRIF Position         */
+#define UART_ALTCTL_ABRIF_Msk            (0x1ul << UART_ALTCTL_ABRIF_Pos)                  /*!< UART_T::ALTCTL: ABRIF Mask             */
+
+#define UART_ALTCTL_ABRDEN_Pos           (18)                                              /*!< UART_T::ALTCTL: ABRDEN Position        */
+#define UART_ALTCTL_ABRDEN_Msk           (0x1ul << UART_ALTCTL_ABRDEN_Pos)                 /*!< UART_T::ALTCTL: ABRDEN Mask            */
+
+#define UART_ALTCTL_ABRDBITS_Pos         (19)                                              /*!< UART_T::ALTCTL: ABRDBITS Position      */
+#define UART_ALTCTL_ABRDBITS_Msk         (0x3ul << UART_ALTCTL_ABRDBITS_Pos)               /*!< UART_T::ALTCTL: ABRDBITS Mask          */
+
+#define UART_ALTCTL_ADDRMV_Pos           (24)                                              /*!< UART_T::ALTCTL: ADDRMV Position        */
+#define UART_ALTCTL_ADDRMV_Msk           (0xfful << UART_ALTCTL_ADDRMV_Pos)                /*!< UART_T::ALTCTL: ADDRMV Mask            */
+
+#define UART_FUNCSEL_FUNCSEL_Pos         (0)                                               /*!< UART_T::FUNCSEL: FUNCSEL Position      */
+#define UART_FUNCSEL_FUNCSEL_Msk         (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)               /*!< UART_T::FUNCSEL: FUNCSEL Mask          */
+
+#define UART_FUNCSEL_TXRXDIS_Pos         (3)                                               /*!< UART_T::FUNCSEL: TXRXDIS Position      */
+#define UART_FUNCSEL_TXRXDIS_Msk         (0x1ul << UART_FUNCSEL_TXRXDIS_Pos)               /*!< UART_T::FUNCSEL: TXRXDIS Mask          */
+
+#define UART_LINCTL_SLVEN_Pos            (0)                                               /*!< UART_T::LINCTL: SLVEN Position         */
+#define UART_LINCTL_SLVEN_Msk            (0x1ul << UART_LINCTL_SLVEN_Pos)                  /*!< UART_T::LINCTL: SLVEN Mask             */
+
+#define UART_LINCTL_SLVHDEN_Pos          (1)                                               /*!< UART_T::LINCTL: SLVHDEN Position       */
+#define UART_LINCTL_SLVHDEN_Msk          (0x1ul << UART_LINCTL_SLVHDEN_Pos)                /*!< UART_T::LINCTL: SLVHDEN Mask           */
+
+#define UART_LINCTL_SLVAREN_Pos          (2)                                               /*!< UART_T::LINCTL: SLVAREN Position       */
+#define UART_LINCTL_SLVAREN_Msk          (0x1ul << UART_LINCTL_SLVAREN_Pos)                /*!< UART_T::LINCTL: SLVAREN Mask           */
+
+#define UART_LINCTL_SLVDUEN_Pos          (3)                                               /*!< UART_T::LINCTL: SLVDUEN Position       */
+#define UART_LINCTL_SLVDUEN_Msk          (0x1ul << UART_LINCTL_SLVDUEN_Pos)                /*!< UART_T::LINCTL: SLVDUEN Mask           */
+
+#define UART_LINCTL_MUTE_Pos             (4)                                               /*!< UART_T::LINCTL: MUTE Position          */
+#define UART_LINCTL_MUTE_Msk             (0x1ul << UART_LINCTL_MUTE_Pos)                   /*!< UART_T::LINCTL: MUTE Mask              */
+
+#define UART_LINCTL_SENDH_Pos            (8)                                               /*!< UART_T::LINCTL: SENDH Position         */
+#define UART_LINCTL_SENDH_Msk            (0x1ul << UART_LINCTL_SENDH_Pos)                  /*!< UART_T::LINCTL: SENDH Mask             */
+
+#define UART_LINCTL_IDPEN_Pos            (9)                                               /*!< UART_T::LINCTL: IDPEN Position         */
+#define UART_LINCTL_IDPEN_Msk            (0x1ul << UART_LINCTL_IDPEN_Pos)                  /*!< UART_T::LINCTL: IDPEN Mask             */
+
+#define UART_LINCTL_BRKDETEN_Pos         (10)                                              /*!< UART_T::LINCTL: BRKDETEN Position      */
+#define UART_LINCTL_BRKDETEN_Msk         (0x1ul << UART_LINCTL_BRKDETEN_Pos)               /*!< UART_T::LINCTL: BRKDETEN Mask          */
+
+#define UART_LINCTL_LINRXOFF_Pos         (11)                                              /*!< UART_T::LINCTL: LINRXOFF Position      */
+#define UART_LINCTL_LINRXOFF_Msk         (0x1ul << UART_LINCTL_LINRXOFF_Pos)               /*!< UART_T::LINCTL: LINRXOFF Mask          */
+
+#define UART_LINCTL_BITERREN_Pos         (12)                                              /*!< UART_T::LINCTL: BITERREN Position      */
+#define UART_LINCTL_BITERREN_Msk         (0x1ul << UART_LINCTL_BITERREN_Pos)               /*!< UART_T::LINCTL: BITERREN Mask          */
+
+#define UART_LINCTL_BRKFL_Pos            (16)                                              /*!< UART_T::LINCTL: BRKFL Position         */
+#define UART_LINCTL_BRKFL_Msk            (0xful << UART_LINCTL_BRKFL_Pos)                  /*!< UART_T::LINCTL: BRKFL Mask             */
+
+#define UART_LINCTL_BSL_Pos              (20)                                              /*!< UART_T::LINCTL: BSL Position           */
+#define UART_LINCTL_BSL_Msk              (0x3ul << UART_LINCTL_BSL_Pos)                    /*!< UART_T::LINCTL: BSL Mask               */
+
+#define UART_LINCTL_HSEL_Pos             (22)                                              /*!< UART_T::LINCTL: HSEL Position          */
+#define UART_LINCTL_HSEL_Msk             (0x3ul << UART_LINCTL_HSEL_Pos)                   /*!< UART_T::LINCTL: HSEL Mask              */
+
+#define UART_LINCTL_PID_Pos              (24)                                              /*!< UART_T::LINCTL: PID Position           */
+#define UART_LINCTL_PID_Msk              (0xfful << UART_LINCTL_PID_Pos)                   /*!< UART_T::LINCTL: PID Mask               */
+
+#define UART_LINSTS_SLVHDETF_Pos         (0)                                               /*!< UART_T::LINSTS: SLVHDETF Position      */
+#define UART_LINSTS_SLVHDETF_Msk         (0x1ul << UART_LINSTS_SLVHDETF_Pos)               /*!< UART_T::LINSTS: SLVHDETF Mask          */
+
+#define UART_LINSTS_SLVHEF_Pos           (1)                                               /*!< UART_T::LINSTS: SLVHEF Position        */
+#define UART_LINSTS_SLVHEF_Msk           (0x1ul << UART_LINSTS_SLVHEF_Pos)                 /*!< UART_T::LINSTS: SLVHEF Mask            */
+
+#define UART_LINSTS_SLVIDPEF_Pos         (2)                                               /*!< UART_T::LINSTS: SLVIDPEF Position      */
+#define UART_LINSTS_SLVIDPEF_Msk         (0x1ul << UART_LINSTS_SLVIDPEF_Pos)               /*!< UART_T::LINSTS: SLVIDPEF Mask          */
+
+#define UART_LINSTS_SLVSYNCF_Pos         (3)                                               /*!< UART_T::LINSTS: SLVSYNCF Position      */
+#define UART_LINSTS_SLVSYNCF_Msk         (0x1ul << UART_LINSTS_SLVSYNCF_Pos)               /*!< UART_T::LINSTS: SLVSYNCF Mask          */
+
+#define UART_LINSTS_BRKDETF_Pos          (8)                                               /*!< UART_T::LINSTS: BRKDETF Position       */
+#define UART_LINSTS_BRKDETF_Msk          (0x1ul << UART_LINSTS_BRKDETF_Pos)                /*!< UART_T::LINSTS: BRKDETF Mask           */
+
+#define UART_LINSTS_BITEF_Pos            (9)                                               /*!< UART_T::LINSTS: BITEF Position         */
+#define UART_LINSTS_BITEF_Msk            (0x1ul << UART_LINSTS_BITEF_Pos)                  /*!< UART_T::LINSTS: BITEF Mask             */
+
+#define UART_BRCOMP_BRCOMP_Pos           (0)                                               /*!< UART_T::BRCOMP: BRCOMP Position        */
+#define UART_BRCOMP_BRCOMP_Msk           (0x1fful << UART_BRCOMP_BRCOMP_Pos)               /*!< UART_T::BRCOMP: BRCOMP Mask            */
+
+#define UART_BRCOMP_BRCOMPDEC_Pos        (31)                                              /*!< UART_T::BRCOMP: BRCOMPDEC Position     */
+#define UART_BRCOMP_BRCOMPDEC_Msk        (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos)              /*!< UART_T::BRCOMP: BRCOMPDEC Mask         */
+
+#define UART_WKCTL_WKCTSEN_Pos           (0)                                               /*!< UART_T::WKCTL: WKCTSEN Position        */
+#define UART_WKCTL_WKCTSEN_Msk           (0x1ul << UART_WKCTL_WKCTSEN_Pos)                 /*!< UART_T::WKCTL: WKCTSEN Mask            */
+
+#define UART_WKCTL_WKDATEN_Pos           (1)                                               /*!< UART_T::WKCTL: WKDATEN Position        */
+#define UART_WKCTL_WKDATEN_Msk           (0x1ul << UART_WKCTL_WKDATEN_Pos)                 /*!< UART_T::WKCTL: WKDATEN Mask            */
+
+#define UART_WKCTL_WKRFRTEN_Pos          (2)                                               /*!< UART_T::WKCTL: WKRFRTEN Position       */
+#define UART_WKCTL_WKRFRTEN_Msk          (0x1ul << UART_WKCTL_WKRFRTEN_Pos)                /*!< UART_T::WKCTL: WKRFRTEN Mask           */
+
+#define UART_WKCTL_WKRS485EN_Pos         (3)                                               /*!< UART_T::WKCTL: WKRS485EN Position      */
+#define UART_WKCTL_WKRS485EN_Msk         (0x1ul << UART_WKCTL_WKRS485EN_Pos)               /*!< UART_T::WKCTL: WKRS485EN Mask          */
+
+#define UART_WKCTL_WKTOUTEN_Pos          (4)                                               /*!< UART_T::WKCTL: WKTOUTEN Position       */
+#define UART_WKCTL_WKTOUTEN_Msk          (0x1ul << UART_WKCTL_WKTOUTEN_Pos)                /*!< UART_T::WKCTL: WKTOUTEN Mask           */
+
+#define UART_WKSTS_CTSWKF_Pos            (0)                                               /*!< UART_T::WKSTS: CTSWKF Position         */
+#define UART_WKSTS_CTSWKF_Msk            (0x1ul << UART_WKSTS_CTSWKF_Pos)                  /*!< UART_T::WKSTS: CTSWKF Mask             */
+
+#define UART_WKSTS_DATWKF_Pos            (1)                                               /*!< UART_T::WKSTS: DATWKF Position         */
+#define UART_WKSTS_DATWKF_Msk            (0x1ul << UART_WKSTS_DATWKF_Pos)                  /*!< UART_T::WKSTS: DATWKF Mask             */
+
+#define UART_WKSTS_RFRTWKF_Pos           (2)                                               /*!< UART_T::WKSTS: RFRTWKF Position        */
+#define UART_WKSTS_RFRTWKF_Msk           (0x1ul << UART_WKSTS_RFRTWKF_Pos)                 /*!< UART_T::WKSTS: RFRTWKF Mask            */
+
+#define UART_WKSTS_RS485WKF_Pos          (3)                                               /*!< UART_T::WKSTS: RS485WKF Position       */
+#define UART_WKSTS_RS485WKF_Msk          (0x1ul << UART_WKSTS_RS485WKF_Pos)                /*!< UART_T::WKSTS: RS485WKF Mask           */
+
+#define UART_WKSTS_TOUTWKF_Pos           (4)                                               /*!< UART_T::WKSTS: TOUTWKF Position        */
+#define UART_WKSTS_TOUTWKF_Msk           (0x1ul << UART_WKSTS_TOUTWKF_Pos)                 /*!< UART_T::WKSTS: TOUTWKF Mask            */
+
+#define UART_DWKCOMP_STCOMP_Pos          (0)                                               /*!< UART_T::DWKCOMP: STCOMP Position       */
+#define UART_DWKCOMP_STCOMP_Msk          (0xfffful << UART_DWKCOMP_STCOMP_Pos)             /*!< UART_T::DWKCOMP: STCOMP Mask           */
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+
+
+/*---------------------- Ethernet MAC Controller -------------------------*/
+/**
+    @addtogroup EMAC Ethernet MAC Controller(EMAC)
+    Memory Mapped Structure for EMAC Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var EMAC_T::CAMCTL
+     * Offset: 0x00  CAM Comparison Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AUP       |Accept Unicast Packet
+     * |        |          |The AUP controls the unicast packet reception
+     * |        |          |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all unicast packets.
+     * |[1]     |AMP       |Accept Multicast Packet
+     * |        |          |The AMP controls the multicast packet reception
+     * |        |          |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all multicast packets.
+     * |[2]     |ABP       |Accept Broadcast Packet
+     * |        |          |The ABP controls the broadcast packet reception
+     * |        |          |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
+     * |        |          |0 = EMAC receives packet depends on the CAM comparison result.
+     * |        |          |1 = EMAC receives all broadcast packets.
+     * |[3]     |COMPEN    |Complement CAM Comparison Enable Bit
+     * |        |          |The COMPEN controls the complement of the CAM comparison result
+     * |        |          |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
+     * |        |          |configured in CAM entry will be dropped
+     * |        |          |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
+     * |        |          |0 = Complement CAM comparison result Disabled.
+     * |        |          |1 = Complement CAM comparison result Enabled.
+     * |[4]     |CMPEN     |CAM Compare Enable Bit
+     * |        |          |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
+     * |        |          |If software wants to receive a packet with specific destination MAC address, configures the MAC address
+     * |        |          |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
+     * |        |          |0 = CAM comparison function for destination MAC address recognition Disabled.
+     * |        |          |1 = CAM comparison function for destination MAC address recognition Enabled.
+     * @var EMAC_T::CAMEN
+     * Offset: 0x04  CAM Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAMxEN    |CAM Entry X Enable Bit
+     * |        |          |The CAMxEN controls the validation of CAM entry x.
+     * |        |          |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
+     * |        |          |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
+     * |        |          |entries all must be enabled first.
+     * |        |          |0 = CAM entry x Disabled.
+     * |        |          |1 = CAM entry x Enabled.
+     * @var EMAC_T::CAM0M
+     * Offset: 0x08  CAM0 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM0L
+     * Offset: 0x0C  CAM0 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM1M
+     * Offset: 0x10  CAM1 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM1L
+     * Offset: 0x14  CAM1 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM2M
+     * Offset: 0x18  CAM2 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM2L
+     * Offset: 0x1C  CAM2 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM3M
+     * Offset: 0x20  CAM3 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM3L
+     * Offset: 0x24  CAM3 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM4M
+     * Offset: 0x28  CAM4 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM4L
+     * Offset: 0x2C  CAM4 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM5M
+     * Offset: 0x30  CAM5 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM5L
+     * Offset: 0x34  CAM5 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM6M
+     * Offset: 0x38  CAM6 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM6L
+     * Offset: 0x3C  CAM6 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM7M
+     * Offset: 0x40  CAM7 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM7L
+     * Offset: 0x44  CAM7 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM8M
+     * Offset: 0x48  CAM8 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM8L
+     * Offset: 0x4C  CAM8 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM9M
+     * Offset: 0x50  CAM9 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM9L
+     * Offset: 0x54  CAM9 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM10M
+     * Offset: 0x58  CAM10 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM10L
+     * Offset: 0x5C  CAM10 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM11M
+     * Offset: 0x60  CAM11 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM11L
+     * Offset: 0x64  CAM11 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM12M
+     * Offset: 0x68  CAM12 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM12L
+     * Offset: 0x6C  CAM12 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM13M
+     * Offset: 0x70  CAM13 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM13L
+     * Offset: 0x74  CAM13 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM14M
+     * Offset: 0x78  CAM14 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |MACADDR2  |MAC Address Byte 2
+     * |[15:8]  |MACADDR3  |MAC Address Byte 3
+     * |[23:16] |MACADDR4  |MAC Address Byte 4
+     * |[31:24] |MACADDR5  |MAC Address Byte 5
+     * |        |          |The CAMxM keeps the bit 47~16 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM14L
+     * Offset: 0x7C  CAM14 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |MACADDR0  |MAC Address Byte 0
+     * |[31:24] |MACADDR1  |MAC Address Byte 1
+     * |        |          |The CAMxL keeps the bit 15~0 of MAC address
+     * |        |          |The x can be the 0~14
+     * |        |          |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+     * |        |          |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+     * |        |          |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+     * @var EMAC_T::CAM15MSB
+     * Offset: 0x80  CAM15 Most Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |OPCODE    |OP Code Field of PAUSE Control Frame
+     * |        |          |In the PAUSE control frame, an op code field defined and is 0x0001.
+     * |[31:16] |LENGTH    |LENGTH Field of PAUSE Control Frame
+     * |        |          |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
+     * @var EMAC_T::CAM15LSB
+     * Offset: 0x84  CAM15 Least Significant Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:24] |OPERAND   |Pause Parameter
+     * |        |          |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
+     * |        |          |Ethernet MAC Controller paused
+     * |        |          |The unit of the OPERAND is a slot time, the 512-bit time.
+     * @var EMAC_T::TXDSA
+     * Offset: 0x88  Transmit Descriptor Link List Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXDSA     |Transmit Descriptor Link-list Start Address
+     * |        |          |The TXDSA keeps the start address of transmit descriptor link-list
+     * |        |          |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
+     * |        |          |current transmit descriptor start address register (EMAC_CTXDSA)
+     * |        |          |The TXDSA does not be updated by EMAC
+     * |        |          |During the operation, EMAC will ignore the bits [1:0] of TXDSA
+     * |        |          |This means that TX descriptors must locate at word boundary memory address.
+     * @var EMAC_T::RXDSA
+     * Offset: 0x8C  Receive Descriptor Link List Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXDSA     |Receive Descriptor Link-list Start Address
+     * |        |          |The RXDSA keeps the start address of receive descriptor link-list
+     * |        |          |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
+     * |        |          |receive descriptor start address register (EMAC_CRXDSA)
+     * |        |          |The RXDSA does not be updated by EMAC
+     * |        |          |During the operation, EMAC will ignore the bits [1:0] of RXDSA
+     * |        |          |This means that RX descriptors must locate at word boundary memory address.
+     * @var EMAC_T::CTL
+     * Offset: 0x90  MAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXON      |Frame Reception ON
+     * |        |          |The RXON controls the normal packet reception of EMAC
+     * |        |          |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
+     * |        |          |descriptor fetching, packet reception and RX descriptor modification.
+     * |        |          |It is necessary to finish EMAC initial sequence before enable RXON
+     * |        |          |Otherwise, the EMAC operation is undefined.
+     * |        |          |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
+     * |        |          |reception process after the current packet reception finished.
+     * |        |          |0 = Packet reception process stopped.
+     * |        |          |1 = Packet reception process started.
+     * |[1]     |ALP       |Accept Long Packet
+     * |        |          |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
+     * |        |          |If the ALP is set to high, the EMAC will accept the long packet.
+     * |        |          |Otherwise, the long packet will be dropped.
+     * |        |          |0 = Ethernet MAC controller dropped the long packet.
+     * |        |          |1 = Ethernet MAC controller received the long packet.
+     * |[2]     |ARP       |Accept Runt Packet
+     * |        |          |The ARP controls the runt packet, which length is less than 64 bytes, reception
+     * |        |          |If the ARP is set to high, the EMAC will accept the runt packet.
+     * |        |          |Otherwise, the runt packet will be dropped.
+     * |        |          |0 = Ethernet MAC controller dropped the runt packet.
+     * |        |          |1 = Ethernet MAC controller received the runt packet.
+     * |[3]     |ACP       |Accept Control Packet
+     * |        |          |The ACP controls the control frame reception
+     * |        |          |If the ACP is set to high, the EMAC will accept the control frame
+     * |        |          |Otherwise, the control frame will be dropped
+     * |        |          |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
+     * |        |          |0 = Ethernet MAC controller dropped the control frame.
+     * |        |          |1 = Ethernet MAC controller received the control frame.
+     * |[4]     |AEP       |Accept CRC Error Packet
+     * |        |          |The AEP controls the EMAC accepts or drops the CRC error packet
+     * |        |          |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
+     * |        |          |0 = Ethernet MAC controller dropped the CRC error packet.
+     * |        |          |1 = Ethernet MAC controller received the CRC error packet.
+     * |[5]     |STRIPCRC  |Strip CRC Checksum
+     * |        |          |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
+     * |        |          |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
+     * |        |          |0 = The 4 bytes CRC checksum is included in packet length calculation.
+     * |        |          |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
+     * |[6]     |WOLEN     |Wake on LAN Enable Bit
+     * |        |          |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
+     * |        |          |is Magic Packet and wakeup system from Power-down mode.
+     * |        |          |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
+     * |        |          |would generate a wakeup event to wake system up from Power-down mode.
+     * |        |          |0 = Wake-up by Magic Packet function Disabled.
+     * |        |          |1 = Wake-up by Magic Packet function Enabled.
+     * |[8]     |TXON      |Frame Transmission ON
+     * |        |          |The TXON controls the normal packet transmission of EMAC
+     * |        |          |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
+     * |        |          |descriptor fetching, packet transmission and TX descriptor modification.
+     * |        |          |It is must to finish EMAC initial sequence before enable TXON
+     * |        |          |Otherwise, the EMAC operation is undefined.
+     * |        |          |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
+     * |        |          |transmission process after the current packet transmission finished.
+     * |        |          |0 = Packet transmission process stopped.
+     * |        |          |1 = Packet transmission process started.
+     * |[9]     |NODEF     |No Deferral
+     * |        |          |The NODEF controls the enable of deferral exceed counter
+     * |        |          |If NODEF is set to high, the deferral exceed counter is disabled
+     * |        |          |The NODEF is only useful while EMAC is operating on half duplex mode.
+     * |        |          |0 = The deferral exceed counter Enabled.
+     * |        |          |1 = The deferral exceed counter Disabled.
+     * |[16]    |SDPZ      |Send PAUSE Frame
+     * |        |          |The SDPZ controls the PAUSE control frame transmission.
+     * |        |          |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
+     * |        |          |first and the corresponding CAM enable bit of CAMEN register also must be set.
+     * |        |          |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
+     * |        |          |The SDPZ is a self-clear bit
+     * |        |          |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
+     * |        |          |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
+     * |        |          |0 = PAUSE control frame transmission completed.
+     * |        |          |1 = PAUSE control frame transmission Enabled.
+     * |[17]    |SQECHKEN  |SQE Checking Enable Bit
+     * |        |          |The SQECHKEN controls the enable of SQE checking
+     * |        |          |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
+     * |        |          |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
+     * |        |          |or full duplex mode.
+     * |        |          |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
+     * |        |          |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
+     * |[18]    |FUDUP     |Full Duplex Mode Selection
+     * |        |          |The FUDUP controls that if EMAC is operating on full or half duplex mode.
+     * |        |          |0 = EMAC operates in half duplex mode.
+     * |        |          |1 = EMAC operates in full duplex mode.
+     * |[19]    |RMIIRXCTL |RMII RX Control
+     * |        |          |The RMIIRXCTL control the receive data sample in RMII mode
+     * |        |          |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
+     * |        |          |0 = RMII RX control disabled.
+     * |        |          |1 = RMII RX control enabled.
+     * |[20]    |OPMODE    |Operation Mode Selection
+     * |        |          |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
+     * |        |          |The RST (EMAC_CTL[24]) would not affect OPMODE value.
+     * |        |          |0 = EMAC operates in 10Mbps mode.
+     * |        |          |1 = EMAC operates in 100Mbps mode.
+     * |[22]    |RMIIEN    |RMII Mode Enable Bit
+     * |        |          |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
+     * |        |          |interface or RMII interface
+     * |        |          |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
+     * |        |          |0 = Ethernet MAC controller RMII mode Disabled.
+     * |        |          |1 = Ethernet MAC controller RMII mode Enabled.
+     * |        |          |NOTE: This field must keep 1.
+     * |[24]    |RST       |Software Reset
+     * |        |          |The RST implements a reset function to make the EMAC return default state
+     * |        |          |The RST is a self-clear bit
+     * |        |          |This means after the software reset finished, the RST will be cleared automatically
+     * |        |          |Enable RST can also reset all control and status registers, exclusive of the control bits
+     * |        |          |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
+     * |        |          |The EMAC re-initial is necessary after the software reset completed.
+     * |        |          |0 = Software reset completed.
+     * |        |          |1 = Software reset Enabled.
+     * @var EMAC_T::MIIMDAT
+     * Offset: 0x94  MII Management Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DATA      |MII Management Data
+     * |        |          |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
+     * |        |          |Management write command or the data from the registers of external PHY for MII Management read command.
+     * @var EMAC_T::MIIMCTL
+     * Offset: 0x98  MII Management Control and Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |PHYREG    |PHY Register Address
+     * |        |          |The PHYREG keeps the address to indicate which register of external PHY is the target of the
+     * |        |          |MII management command.
+     * |[12:8]  |PHYADDR   |PHY Address
+     * |        |          |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
+     * |[16]    |WRITE     |Write Command
+     * |        |          |The Write defines the MII management command is a read or write.
+     * |        |          |0 = MII management command is a read command.
+     * |        |          |1 = MII management command is a write command.
+     * |[17]    |BUSY      |Busy Bit
+     * |        |          |The BUSY controls the enable of the MII management frame generation
+     * |        |          |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
+     * |        |          |the MII management frame to external PHY through MII Management I/F
+     * |        |          |The BUSY is a self-clear bit
+     * |        |          |This means the BUSY will be cleared automatically after the MII management command finished.
+     * |        |          |0 = MII management command generation finished.
+     * |        |          |1 = MII management command generation Enabled.
+     * |[18]    |PREAMSP   |Preamble Suppress
+     * |        |          |The PREAMSP controls the preamble field generation of MII management frame
+     * |        |          |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
+     * |        |          |0 = Preamble field generation of MII management frame not skipped.
+     * |        |          |1 = Preamble field generation of MII management frame skipped.
+     * |[19]    |MDCON     |MDC Clock ON
+     * |        |          |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
+     * |        |          |0 = MDC clock off.
+     * |        |          |1 = MDC clock on.
+     * @var EMAC_T::FIFOCTL
+     * Offset: 0x9C  FIFO Threshold Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RXFIFOTH  |RXFIFO Low Threshold
+     * |        |          |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO
+     * |        |          |and system memory
+     * |        |          |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold
+     * |        |          |The low threshold is the half of high threshold always
+     * |        |          |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
+     * |        |          |transfer frame data from RXFIFO to system memory
+     * |        |          |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
+     * |        |          |data to system memory.
+     * |        |          |00 = Depend on the burst length setting
+     * |        |          |If the burst length is 8 words, high threshold is 8 words, too.
+     * |        |          |01 = RXFIFO high threshold is 64B and low threshold is 32B.
+     * |        |          |10 = RXFIFO high threshold is 128B and low threshold is 64B.
+     * |        |          |11 = RXFIFO high threshold is 192B and low threshold is 96B.
+     * |[9:8]   |TXFIFOTH  |TXFIFO Low Threshold
+     * |        |          |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system
+     * |        |          |memory and TXFIFO
+     * |        |          |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold
+     * |        |          |The high threshold is the twice of low threshold always
+     * |        |          |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
+     * |        |          |generate request to transfer frame data from system memory to TXFIFO
+     * |        |          |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
+     * |        |          |from system memory to TXFIFO.
+     * |        |          |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network
+     * |        |          |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
+     * |        |          |during the transmission of the frame
+     * |        |          |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
+     * |        |          |out after the frame data are all inside the TXFIFO.
+     * |        |          |00 = Undefined.
+     * |        |          |01 = TXFIFO low threshold is 64B and high threshold is 128B.
+     * |        |          |10 = TXFIFO low threshold is 80B and high threshold is 160B.
+     * |        |          |11 = TXFIFO low threshold is 96B and high threshold is 192B.
+     * |[21:20] |BURSTLEN  |DMA Burst Length
+     * |        |          |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
+     * |        |          |00 = 4 words.
+     * |        |          |01 = 8 words.
+     * |        |          |10 = 16 words.
+     * |        |          |11 = 16 words.
+     * @var EMAC_T::TXST
+     * Offset: 0xA0  Transmit Start Demand Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXST      |Transmit Start Demand
+     * |        |          |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
+     * |        |          |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
+     * |        |          |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
+     * |        |          |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
+     * |        |          |The EMAC_TXST is a write only register and read from this register is undefined.
+     * |        |          |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
+     * @var EMAC_T::RXST
+     * Offset: 0xA4  Receive Start Demand Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXST      |Receive Start Demand
+     * |        |          |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
+     * |        |          |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
+     * |        |          |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
+     * |        |          |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
+     * |        |          |The EMAC_RXST is a write only register and read from this register is undefined.
+     * |        |          |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
+     * @var EMAC_T::MRFL
+     * Offset: 0xA8  Maximum Receive Frame Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MRFL      |Maximum Receive Frame Length
+     * |        |          |The MRFL defines the maximum frame length for received frame
+     * |        |          |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8])
+     * |        |          |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
+     * |        |          |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to
+     * |        |          |receive a frame which length is greater than 1518 bytes.
+     * @var EMAC_T::INTEN
+     * Offset: 0xAC  MAC Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXIEN     |Receive Interrupt Enable Bit
+     * |        |          |The RXIEN controls the RX interrupt generation.
+     * |        |          |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU
+     * |        |          |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1]
+     * |        |          |is set and the corresponding bit of EMAC_INTEN is enabled
+     * |        |          |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
+     * |        |          |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
+     * |        |          |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
+     * |        |          |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
+     * |[1]     |CRCEIEN   |CRC Error Interrupt Enable Bit
+     * |        |          |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation
+     * |        |          |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |CRCEIF (EMAC_INTSTS[1]) is set.
+     * |        |          |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
+     * |        |          |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
+     * |[2]     |RXOVIEN   |Receive FIFO Overflow Interrupt Enable Bit
+     * |        |          |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation
+     * |        |          |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXOVIF (EMAC_INTSTS[2]) is set.
+     * |        |          |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
+     * |[3]     |LPIEN     |Long Packet Interrupt Enable Bit
+     * |        |          |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation
+     * |        |          |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+     * |        |          |generates the RX interrupt to CPU
+     * |        |          |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
+     * |        |          |(EMAC_INTSTS[3]) is set.
+     * |        |          |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
+     * |        |          |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
+     * |[4]     |RXGDIEN   |Receive Good Interrupt Enable Bit
+     * |        |          |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation
+     * |        |          |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXGDIF (EMAC_INTSTS[4]) is set.
+     * |        |          |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
+     * |[5]     |ALIEIEN   |Alignment Error Interrupt Enable Bit
+     * |        |          |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation
+     * |        |          |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |ALIEIF (EMAC_INTSTS[5]) is set.
+     * |        |          |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
+     * |        |          |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
+     * |[6]     |RPIEN     |Runt Packet Interrupt Enable Bit
+     * |        |          |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation
+     * |        |          |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+     * |        |          |generates the RX interrupt to CPU
+     * |        |          |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RPIF (EMAC_INTSTS[6]) is set.
+     * |        |          |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
+     * |        |          |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
+     * |[7]     |MPCOVIEN  |Miss Packet Counter Overrun Interrupt Enable Bit
+     * |        |          |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation
+     * |        |          |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+     * |        |          |the EMAC generates the RX interrupt to CPU
+     * |        |          |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |MPCOVIF (EMAC_INTSTS[7]) is set.
+     * |        |          |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
+     * |        |          |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
+     * |[8]     |MFLEIEN   |Maximum Frame Length Exceed Interrupt Enable Bit
+     * |        |          |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation
+     * |        |          |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |MFLEIF (EMAC_INTSTS[8]) is set.
+     * |        |          |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
+     * |        |          |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
+     * |[9]     |DENIEN    |DMA Early Notification Interrupt Enable Bit
+     * |        |          |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation
+     * |        |          |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |DENIF (EMAC_INTSTS[9]) is set.
+     * |        |          |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
+     * |        |          |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
+     * |[10]    |RDUIEN    |Receive Descriptor Unavailable Interrupt Enable Bit
+     * |        |          |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation
+     * |        |          |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RDUIF (EMAC_MIOSTA[10]) register is set.
+     * |        |          |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
+     * |        |          |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
+     * |[11]    |RXBEIEN   |Receive Bus Error Interrupt Enable Bit
+     * |        |          |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation
+     * |        |          |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |RXBEIF (EMAC_INTSTS[11]) is set.
+     * |        |          |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
+     * |        |          |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
+     * |[14]    |CFRIEN    |Control Frame Receive Interrupt Enable Bit
+     * |        |          |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation
+     * |        |          |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+     * |        |          |EMAC generates the RX interrupt to CPU
+     * |        |          |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |CFRIF (EMAC_INTSTS[14]) register is set.
+     * |        |          |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
+     * |        |          |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
+     * |[15]    |WOLIEN    |Wake on LAN Interrupt Enable Bit
+     * |        |          |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation
+     * |        |          |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+     * |        |          |the EMAC generates the RX interrupt to CPU
+     * |        |          |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+     * |        |          |WOLIF (EMAC_INTSTS[15]) is set.
+     * |        |          |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
+     * |        |          |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
+     * |[16]    |TXIEN     |Transmit Interrupt Enable Bit
+     * |        |          |The TXIEN controls the TX interrupt generation.
+     * |        |          |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU
+     * |        |          |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
+     * |        |          |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled
+     * |        |          |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
+     * |        |          |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
+     * |        |          |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
+     * |        |          |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
+     * |[17]    |TXUDIEN   |Transmit FIFO Underflow Interrupt Enable Bit
+     * |        |          |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation
+     * |        |          |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even
+     * |        |          |the TXUDIF (EMAC_INTSTS[17]) is set.
+     * |        |          |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
+     * |        |          |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
+     * |[18]    |TXCPIEN   |Transmit Completion Interrupt Enable Bit
+     * |        |          |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation
+     * |        |          |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXCPIF (EMAC_INTSTS[18]) is set.
+     * |        |          |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
+     * |[19]    |EXDEFIEN  |Defer Exceed Interrupt Enable Bit
+     * |        |          |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation
+     * |        |          |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |EXDEFIF (EMAC_INTSTS[19]) is set.
+     * |        |          |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
+     * |        |          |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
+     * |[20]    |NCSIEN    |No Carrier Sense Interrupt Enable Bit
+     * |        |          |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation
+     * |        |          |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |NCSIF (EMAC_INTSTS[20]) is set.
+     * |        |          |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
+     * |        |          |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
+     * |[21]    |TXABTIEN  |Transmit Abort Interrupt Enable Bit
+     * |        |          |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation
+     * |        |          |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+     * |        |          |the EMAC generates the TX interrupt to CPU
+     * |        |          |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXABTIF (EMAC_INTSTS[21]) is set.
+     * |        |          |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
+     * |[22]    |LCIEN     |Late Collision Interrupt Enable Bit
+     * |        |          |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation
+     * |        |          |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |LCIF (EMAC_INTSTS[22]) is set.
+     * |        |          |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
+     * |        |          |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
+     * |[23]    |TDUIEN    |Transmit Descriptor Unavailable Interrupt Enable Bit
+     * |        |          |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation
+     * |        |          |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TDUIF (EMAC_INTSTS[23]) is set.
+     * |        |          |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
+     * |        |          |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
+     * |[24]    |TXBEIEN   |Transmit Bus Error Interrupt Enable Bit
+     * |        |          |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation
+     * |        |          |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+     * |        |          |TXBEIF (EMAC_INTSTS[24]) is set.
+     * |        |          |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
+     * |[28]    |TSALMIEN  |Time Stamp Alarm Interrupt Enable Bit
+     * |        |          |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation
+     * |        |          |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the
+     * |        |          |EMAC generates the TX interrupt to CPU
+     * |        |          |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the
+     * |        |          |TXTSALMIF (EMAC_INTEN[28]) is set.
+     * |        |          |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
+     * |        |          |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
+     * @var EMAC_T::INTSTS
+     * Offset: 0xB0  MAC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXIF      |Receive Interrupt
+     * |        |          |The RXIF indicates the RX interrupt status.
+     * |        |          |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates
+     * |        |          |the EMAC generates RX interrupt to CPU
+     * |        |          |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
+     * |        |          |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]
+     * |        |          |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in
+     * |        |          |EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
+     * |        |          |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
+     * |        |          |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
+     * |        |          |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in
+     * |        |          |EMAC_INTEN[15:1] is enabled, too.
+     * |[1]     |CRCEIF    |CRC Error Interrupt
+     * |        |          |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
+     * |        |          |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
+     * |        |          |CRCEIF will not be set.
+     * |        |          |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the CRCEIF status.
+     * |        |          |0 = The frame does not incur CRC error.
+     * |        |          |1 = The frame incurred CRC error.
+     * |[2]     |RXOVIF    |Receive FIFO Overflow Interrupt
+     * |        |          |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
+     * |        |          |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
+     * |        |          |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
+     * |        |          |the RXFIFOTH of FFTCR register, to higher level.
+     * |        |          |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXOVIF status.
+     * |        |          |0 = No RXFIFO overflow occurred during packet reception.
+     * |        |          |1 = RXFIFO overflow occurred during packet reception.
+     * |[3]     |LPIF      |Long Packet Interrupt Flag
+     * |        |          |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
+     * |        |          |incoming packet is dropped
+     * |        |          |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
+     * |        |          |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the LPIF status.
+     * |        |          |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
+     * |        |          |1 = The incoming frame is a long frame and dropped.
+     * |[4]     |RXGDIF    |Receive Good Interrupt
+     * |        |          |The RXGDIF high indicates the frame reception has completed.
+     * |        |          |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXGDIF status.
+     * |        |          |0 = The frame reception has not complete yet.
+     * |        |          |1 = The frame reception has completed.
+     * |[5]     |ALIEIF    |Alignment Error Interrupt
+     * |        |          |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
+     * |        |          |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the ALIEIF status.
+     * |        |          |0 = The frame length is a multiple of byte.
+     * |        |          |1 = The frame length is not a multiple of byte.
+     * |[6]     |RPIF      |Runt Packet Interrupt
+     * |        |          |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
+     * |        |          |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
+     * |        |          |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RPIF status.
+     * |        |          |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
+     * |        |          |1 = The incoming frame is a short frame and dropped.
+     * |[7]     |MPCOVIF   |Missed Packet Counter Overrun Interrupt Flag
+     * |        |          |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
+     * |        |          |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the MPCOVIF status.
+     * |        |          |0 = The MPCNT has not rolled over yet.
+     * |        |          |1 = The MPCNT has rolled over yet.
+     * |[8]     |MFLEIF    |Maximum Frame Length Exceed Interrupt Flag
+     * |        |          |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
+     * |        |          |configured in DMARFC register and the incoming packet is dropped
+     * |        |          |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the MFLEIF status.
+     * |        |          |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
+     * |        |          |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
+     * |[9]     |DENIF     |DMA Early Notification Interrupt
+     * |        |          |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
+     * |        |          |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the DENIF status.
+     * |        |          |0 = The LENGTH field of incoming packet has not received yet.
+     * |        |          |1 = The LENGTH field of incoming packet has received.
+     * |[10]    |RDUIF     |Receive Descriptor Unavailable Interrupt
+     * |        |          |The RDUIF high indicates that there is no available RX descriptor for packet reception and
+     * |        |          |RXDMA will stay at Halt state
+     * |        |          |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
+     * |        |          |make RXDMA leave Halt state while new RX descriptor is available.
+     * |        |          |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RDUIF status.
+     * |        |          |0 = RX descriptor is available.
+     * |        |          |1 = RX descriptor is unavailable.
+     * |[11]    |RXBEIF    |Receive Bus Error Interrupt
+     * |        |          |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
+     * |        |          |system memory through RXDMA during packet reception process
+     * |        |          |Reset EMAC is recommended while RXBEIF status is high.
+     * |        |          |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the RXBEIF status.
+     * |        |          |0 = No ERROR response is received.
+     * |        |          |1 = ERROR response is received.
+     * |[14]    |CFRIF     |Control Frame Receive Interrupt
+     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
+     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
+     * |        |          |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the CFRIF status.
+     * |        |          |0 = The EMAC does not receive the flow control frame.
+     * |        |          |1 = The EMAC receives a flow control frame.
+     * |[15]    |WOLIF     |Wake on LAN Interrupt Flag
+     * |        |          |The WOLIF high indicates EMAC receives a Magic Packet
+     * |        |          |The CFRIF only available while system is in power down mode and WOLEN is set high.
+     * |        |          |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high
+     * |        |          |Write 1 to this bit clears the WOLIF status.
+     * |        |          |0 = The EMAC does not receive the Magic Packet.
+     * |        |          |1 = The EMAC receives a Magic Packet.
+     * |[16]    |TXIF      |Transmit Interrupt
+     * |        |          |The TXIF indicates the TX interrupt status.
+     * |        |          |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates
+     * |        |          |the EMAC generates TX interrupt to CPU
+     * |        |          |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
+     * |        |          |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]
+     * |        |          |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit
+     * |        |          |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high
+     * |        |          |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
+     * |        |          |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
+     * |        |          |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit
+     * |        |          |in EMAC_INTEN[28:17] is enabled, too.
+     * |[17]    |TXUDIF    |Transmit FIFO Underflow Interrupt
+     * |        |          |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
+     * |        |          |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
+     * |        |          |without S/W intervention
+     * |        |          |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
+     * |        |          |the TXFIFOTH of FFTCR register, to higher level.
+     * |        |          |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXUDIF status.
+     * |        |          |0 = No TXFIFO underflow occurred during packet transmission.
+     * |        |          |1 = TXFIFO underflow occurred during packet transmission.
+     * |[18]    |TXCPIF    |Transmit Completion Interrupt
+     * |        |          |The TXCPIF indicates the packet transmission has completed correctly.
+     * |        |          |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXCPIF status.
+     * |        |          |0 = The packet transmission not completed.
+     * |        |          |1 = The packet transmission has completed.
+     * |[19]    |EXDEFIF   |Defer Exceed Interrupt
+     * |        |          |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
+     * |        |          |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
+     * |        |          |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
+     * |        |          |is operating on half-duplex mode.
+     * |        |          |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the EXDEFIF status.
+     * |        |          |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+     * |        |          |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+     * |[20]    |NCSIF     |No Carrier Sense Interrupt
+     * |        |          |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
+     * |        |          |the packet transmission
+     * |        |          |The NCSIF is only available while EMAC is operating on half-duplex mode
+     * |        |          |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the NCSIF status.
+     * |        |          |0 = CRS signal actives correctly.
+     * |        |          |1 = CRS signal does not active at the start of or during the packet transmission.
+     * |[21]    |TXABTIF   |Transmit Abort Interrupt
+     * |        |          |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
+     * |        |          |and then the transmission process for this packet is aborted
+     * |        |          |The transmission abort is only available while EMAC is operating on half-duplex mode.
+     * |        |          |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high
+     * |        |          |Write 1 to this bit clears the TXABTIF status.
+     * |        |          |0 = Packet does not incur 16 consecutive collisions during transmission.
+     * |        |          |1 = Packet incurred 16 consecutive collisions during transmission.
+     * |[22]    |LCIF      |Late Collision Interrupt
+     * |        |          |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
+     * |        |          |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
+     * |        |          |still occurred.
+     * |        |          |The late collision check will only be done while EMAC is operating on half-duplex mode
+     * |        |          |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the LCIF status.
+     * |        |          |0 = No collision occurred in the outside of 64 bytes collision window.
+     * |        |          |1 = Collision occurred in the outside of 64 bytes collision window.
+     * |[23]    |TDUIF     |Transmit Descriptor Unavailable Interrupt
+     * |        |          |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
+     * |        |          |TXDMA will stay at Halt state.
+     * |        |          |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
+     * |        |          |TXDMA leave Halt state while new TX descriptor is available.
+     * |        |          |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TDUIF status.
+     * |        |          |0 = TX descriptor is available.
+     * |        |          |1 = TX descriptor is unavailable.
+     * |[24]    |TXBEIF    |Transmit Bus Error Interrupt
+     * |        |          |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
+     * |        |          |memory through TXDMA during packet transmission process
+     * |        |          |Reset EMAC is recommended while TXBEIF status is high.
+     * |        |          |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TXBEIF status.
+     * |        |          |0 = No ERROR response is received.
+     * |        |          |1 = ERROR response is received.
+     * |[28]    |TSALMIF   |Time Stamp Alarm Interrupt
+     * |        |          |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
+     * |        |          |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
+     * |        |          |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
+     * |        |          |Write 1 to this bit clears the TSALMIF status.
+     * |        |          |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
+     * |        |          |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
+     * @var EMAC_T::GENSTS
+     * Offset: 0xB4  MAC General Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CFR       |Control Frame Received
+     * |        |          |The CFRIF high indicates EMAC receives a flow control frame
+     * |        |          |The CFRIF only available while EMAC is operating on full duplex mode.
+     * |        |          |0 = The EMAC does not receive the flow control frame.
+     * |        |          |1 = The EMAC receives a flow control frame.
+     * |[1]     |RXHALT    |Receive Halted
+     * |        |          |The RXHALT high indicates the next normal packet reception process will be halted because
+     * |        |          |the bit RXON of MCMDR is disabled be S/W.
+     * |        |          |0 = Next normal packet reception process will go on.
+     * |        |          |1 = Next normal packet reception process will be halted.
+     * |[2]     |RXFFULL   |RXFIFO Full
+     * |        |          |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
+     * |        |          |and the following incoming packet will be dropped.
+     * |        |          |0 = The RXFIFO is not full.
+     * |        |          |1 = The RXFIFO is full and the following incoming packet will be dropped.
+     * |[7:4]   |COLCNT    |Collision Count
+     * |        |          |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
+     * |        |          |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
+     * |        |          |0 and bit TXABTIF will be set to 1.
+     * |[8]     |DEF       |Deferred Transmission
+     * |        |          |The DEF high indicates the packet transmission has deferred once
+     * |        |          |The DEF is only available while EMAC is operating on half-duplex mode.
+     * |        |          |0 = Packet transmission does not defer.
+     * |        |          |1 = Packet transmission has deferred once.
+     * |[9]     |TXPAUSED  |Transmission Paused
+     * |        |          |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
+     * |        |          |because EMAC received a PAUSE control frame.
+     * |        |          |0 = Next normal packet transmission process will go on.
+     * |        |          |1 = Next normal packet transmission process will be paused.
+     * |[10]    |SQE       |Signal Quality Error
+     * |        |          |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
+     * |        |          |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
+     * |        |          |is operating on 10Mbps half-duplex mode.
+     * |        |          |0 = No SQE error found at end of packet transmission.
+     * |        |          |1 = SQE error found at end of packet transmission.
+     * |[11]    |TXHALT    |Transmission Halted
+     * |        |          |The TXHALT high indicates the next normal packet transmission process will be halted because
+     * |        |          |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
+     * |        |          |0 = Next normal packet transmission process will go on.
+     * |        |          |1 = Next normal packet transmission process will be halted.
+     * |[12]    |RPSTS     |Remote Pause Status
+     * |        |          |The RPSTS indicates that remote pause counter down counting actives.
+     * |        |          |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
+     * |        |          |counter down counting
+     * |        |          |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
+     * |        |          |transmission until the down counting done.
+     * |        |          |0 = Remote pause counter down counting done.
+     * |        |          |1 = Remote pause counter down counting actives.
+     * @var EMAC_T::MPCNT
+     * Offset: 0xB8  Missed Packet Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MPCNT     |Miss Packet Count
+     * |        |          |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
+     * |        |          |The following type of receiving error makes missed packet counter increase:
+     * |        |          |1. Incoming packet is incurred RXFIFO overflow.
+     * |        |          |2. Incoming packet is dropped due to RXON is disabled.
+     * |        |          |3. Incoming packet is incurred CRC error.
+     * @var EMAC_T::RPCNT
+     * Offset: 0xBC  MAC Receive Pause Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RPCNT     |MAC Receive Pause Count
+     * |        |          |The RPCNT keeps the OPERAND field of the PAUSE control frame
+     * |        |          |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
+     * @var EMAC_T::FRSTS
+     * Offset: 0xC8  DMA Receive Frame Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXFLT     |Receive Frame LENGTH
+     * |        |          |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
+     * |        |          |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has
+     * |        |          |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
+     * |        |          |And, the content of LENGTH field will be stored in RXFLT.
+     * @var EMAC_T::CTXDSA
+     * Offset: 0xCC  Current Transmit Descriptor Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CTXDSA    |Current Transmit Descriptor Start Address
+     * |        |          |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
+     * |        |          |The CTXDSA is read only and write to this register has no effect.
+     * @var EMAC_T::CTXBSA
+     * Offset: 0xD0  Current Transmit Buffer Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CTXBSA    |Current Transmit Buffer Start Address
+     * |        |          |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
+     * |        |          |The CTXBSA is read only and write to this register has no effect.
+     * @var EMAC_T::CRXDSA
+     * Offset: 0xD4  Current Receive Descriptor Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CRXDSA    |Current Receive Descriptor Start Address
+     * |        |          |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
+     * |        |          |The CRXDSA is read only and write to this register has no effect.
+     * @var EMAC_T::CRXBSA
+     * Offset: 0xD8  Current Receive Buffer Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CRXBSA    |Current Receive Buffer Start Address
+     * |        |          |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
+     * |        |          |The CRXBSA is read only and write to this register has no effect.
+     * @var EMAC_T::TSCTL
+     * Offset: 0x100  Time Stamp Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TSEN      |Time Stamp Function Enable Bit
+     * |        |          |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
+     * |        |          |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
+     * |        |          |to disable IEEE 1588 PTP time stamp function.
+     * |        |          |0 = I EEE 1588 PTP time stamp function Disabled.
+     * |        |          |1 = IEEE 1588 PTP time stamp function Enabled.
+     * |[1]     |TSIEN     |Time Stamp Counter Initialization Enable Bit
+     * |        |          |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
+     * |        |          |and EMAC_UPDSUBSEC to PTP time stamp counter.
+     * |        |          |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
+     * |        |          |0 = Time stamp counter initialization done.
+     * |        |          |1 = Time stamp counter initialization Enabled.
+     * |[2]     |TSMODE    |Time Stamp Fine Update Enable Bit
+     * |        |          |This bit chooses the time stamp counter update mode.
+     * |        |          |0 = Time stamp counter is in coarse update mode.
+     * |        |          |1 = Time stamp counter is in fine update mode.
+     * |[3]     |TSUPDATE  |Time Stamp Counter Time Update Enable Bit
+     * |        |          |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
+     * |        |          |EMAC_UPDSUBSEC to PTP time stamp counter.
+     * |        |          |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
+     * |        |          |0 = No action.
+     * |        |          |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
+     * |[5]     |TSALMEN   |Time Stamp Alarm Enable Bit
+     * |        |          |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when
+     * |        |          |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * |        |          |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * |        |          |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+     * @var EMAC_T::TSSEC
+     * Offset: 0x110  Time Stamp Counter Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second
+     * |        |          |This register reflects the bit [63:32] value of 64-bit reference timing counter
+     * |        |          |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+     * @var EMAC_T::TSSUBSEC
+     * Offset: 0x114  Time Stamp Counter Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second
+     * |        |          |This register reflects the bit [31:0] value of 64-bit reference timing counter
+     * |        |          |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+     * @var EMAC_T::TSINC
+     * Offset: 0x118  Time Stamp Increment Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNTINC    |Time Stamp Counter Increment
+     * |        |          |Time stamp counter increment value.
+     * |        |          |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
+     * |        |          |time when it wants to increase the EMAC_TSSUBSEC value.
+     * @var EMAC_T::TSADDEND
+     * Offset: 0x11C  Time Stamp Addend Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ADDEND    |Time Stamp Counter Addend
+     * |        |          |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
+     * |        |          |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
+     * |        |          |with this 32-bit value in each HCLK
+     * |        |          |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
+     * |        |          |value kept in register EMAC_TSINC.
+     * @var EMAC_T::UPDSEC
+     * Offset: 0x120  Time Stamp Update Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second Update
+     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
+     * |        |          |EMAC loads this 32-bit value to EMAC_TSSEC directly
+     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
+     * @var EMAC_T::UPDSUBSEC
+     * Offset: 0x124  Time Stamp Update Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Update
+     * |        |          |When TSIEN (EMAC_TSCTL[1]) is high
+     * |        |          |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
+     * |        |          |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
+     * @var EMAC_T::ALMSEC
+     * Offset: 0x128  Time Stamp Alarm Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEC       |Time Stamp Counter Second Alarm
+     * |        |          |Time stamp counter second part alarm value.
+     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+     * @var EMAC_T::ALMSUBSEC
+     * Offset: 0x12C  Time Stamp Alarm Sub Second Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SUBSEC    |Time Stamp Counter Sub-second Alarm
+     * |        |          |Time stamp counter sub-second part alarm value.
+     * |        |          |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+     * |        |          |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+     * |        |          |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+     */
+    __IO uint32_t CAMCTL;                /*!< [0x0000] CAM Comparison Control Register                                  */
+    __IO uint32_t CAMEN;                 /*!< [0x0004] CAM Enable Register                                              */
+    __IO uint32_t CAM0M;                 /*!< [0x0008] CAM0 Most Significant Word Register                              */
+    __IO uint32_t CAM0L;                 /*!< [0x000c] CAM0 Least Significant Word Register                             */
+    __IO uint32_t CAM1M;                 /*!< [0x0010] CAM1 Most Significant Word Register                              */
+    __IO uint32_t CAM1L;                 /*!< [0x0014] CAM1 Least Significant Word Register                             */
+    __IO uint32_t CAM2M;                 /*!< [0x0018] CAM2 Most Significant Word Register                              */
+    __IO uint32_t CAM2L;                 /*!< [0x001c] CAM2 Least Significant Word Register                             */
+    __IO uint32_t CAM3M;                 /*!< [0x0020] CAM3 Most Significant Word Register                              */
+    __IO uint32_t CAM3L;                 /*!< [0x0024] CAM3 Least Significant Word Register                             */
+    __IO uint32_t CAM4M;                 /*!< [0x0028] CAM4 Most Significant Word Register                              */
+    __IO uint32_t CAM4L;                 /*!< [0x002c] CAM4 Least Significant Word Register                             */
+    __IO uint32_t CAM5M;                 /*!< [0x0030] CAM5 Most Significant Word Register                              */
+    __IO uint32_t CAM5L;                 /*!< [0x0034] CAM5 Least Significant Word Register                             */
+    __IO uint32_t CAM6M;                 /*!< [0x0038] CAM6 Most Significant Word Register                              */
+    __IO uint32_t CAM6L;                 /*!< [0x003c] CAM6 Least Significant Word Register                             */
+    __IO uint32_t CAM7M;                 /*!< [0x0040] CAM7 Most Significant Word Register                              */
+    __IO uint32_t CAM7L;                 /*!< [0x0044] CAM7 Least Significant Word Register                             */
+    __IO uint32_t CAM8M;                 /*!< [0x0048] CAM8 Most Significant Word Register                              */
+    __IO uint32_t CAM8L;                 /*!< [0x004c] CAM8 Least Significant Word Register                             */
+    __IO uint32_t CAM9M;                 /*!< [0x0050] CAM9 Most Significant Word Register                              */
+    __IO uint32_t CAM9L;                 /*!< [0x0054] CAM9 Least Significant Word Register                             */
+    __IO uint32_t CAM10M;                /*!< [0x0058] CAM10 Most Significant Word Register                             */
+    __IO uint32_t CAM10L;                /*!< [0x005c] CAM10 Least Significant Word Register                            */
+    __IO uint32_t CAM11M;                /*!< [0x0060] CAM11 Most Significant Word Register                             */
+    __IO uint32_t CAM11L;                /*!< [0x0064] CAM11 Least Significant Word Register                            */
+    __IO uint32_t CAM12M;                /*!< [0x0068] CAM12 Most Significant Word Register                             */
+    __IO uint32_t CAM12L;                /*!< [0x006c] CAM12 Least Significant Word Register                            */
+    __IO uint32_t CAM13M;                /*!< [0x0070] CAM13 Most Significant Word Register                             */
+    __IO uint32_t CAM13L;                /*!< [0x0074] CAM13 Least Significant Word Register                            */
+    __IO uint32_t CAM14M;                /*!< [0x0078] CAM14 Most Significant Word Register                             */
+    __IO uint32_t CAM14L;                /*!< [0x007c] CAM14 Least Significant Word Register                            */
+    __IO uint32_t CAM15MSB;              /*!< [0x0080] CAM15 Most Significant Word Register                             */
+    __IO uint32_t CAM15LSB;              /*!< [0x0084] CAM15 Least Significant Word Register                            */
+    __IO uint32_t TXDSA;                 /*!< [0x0088] Transmit Descriptor Link List Start Address Register             */
+    __IO uint32_t RXDSA;                 /*!< [0x008c] Receive Descriptor Link List Start Address Register              */
+    __IO uint32_t CTL;                   /*!< [0x0090] MAC Control Register                                             */
+    __IO uint32_t MIIMDAT;               /*!< [0x0094] MII Management Data Register                                     */
+    __IO uint32_t MIIMCTL;               /*!< [0x0098] MII Management Control and Address Register                      */
+    __IO uint32_t FIFOCTL;               /*!< [0x009c] FIFO Threshold Control Register                                  */
+    __O  uint32_t TXST;                  /*!< [0x00a0] Transmit Start Demand Register                                   */
+    __O  uint32_t RXST;                  /*!< [0x00a4] Receive Start Demand Register                                    */
+    __IO uint32_t MRFL;                  /*!< [0x00a8] Maximum Receive Frame Control Register                           */
+    __IO uint32_t INTEN;                 /*!< [0x00ac] MAC Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x00b0] MAC Interrupt Status Register                                    */
+    __IO uint32_t GENSTS;                /*!< [0x00b4] MAC General Status Register                                      */
+    __IO uint32_t MPCNT;                 /*!< [0x00b8] Missed Packet Count Register                                     */
+    __I  uint32_t RPCNT;                 /*!< [0x00bc] MAC Receive Pause Count Register                                 */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[2];
+    /** @endcond */
+    __IO uint32_t FRSTS;                 /*!< [0x00c8] DMA Receive Frame Status Register                                */
+    __I  uint32_t CTXDSA;                /*!< [0x00cc] Current Transmit Descriptor Start Address Register               */
+    __I  uint32_t CTXBSA;                /*!< [0x00d0] Current Transmit Buffer Start Address Register                   */
+    __I  uint32_t CRXDSA;                /*!< [0x00d4] Current Receive Descriptor Start Address Register                */
+    __I  uint32_t CRXBSA;                /*!< [0x00d8] Current Receive Buffer Start Address Register                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE1[9];
+    /** @endcond */
+    __IO uint32_t TSCTL;                 /*!< [0x0100] Time Stamp Control Register                                      */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE2[3];
+    /** @endcond */
+    __I  uint32_t TSSEC;                 /*!< [0x0110] Time Stamp Counter Second Register                               */
+    __I  uint32_t TSSUBSEC;              /*!< [0x0114] Time Stamp Counter Sub Second Register                           */
+    __IO uint32_t TSINC;                 /*!< [0x0118] Time Stamp Increment Register                                    */
+    __IO uint32_t TSADDEND;              /*!< [0x011c] Time Stamp Addend Register                                       */
+    __IO uint32_t UPDSEC;                /*!< [0x0120] Time Stamp Update Second Register                                */
+    __IO uint32_t UPDSUBSEC;             /*!< [0x0124] Time Stamp Update Sub Second Register                            */
+    __IO uint32_t ALMSEC;                /*!< [0x0128] Time Stamp Alarm Second Register                                 */
+    __IO uint32_t ALMSUBSEC;             /*!< [0x012c] Time Stamp Alarm Sub Second Register                             */
+
+} EMAC_T;
+
+/**
+    @addtogroup EMAC_CONST EMAC Bit Field Definition
+    Constant Definitions for EMAC Controller
+@{ */
+
+#define EMAC_CAMCTL_AUP_Pos              (0)                                               /*!< EMAC_T::CAMCTL: AUP Position           */
+#define EMAC_CAMCTL_AUP_Msk              (0x1ul << EMAC_CAMCTL_AUP_Pos)                    /*!< EMAC_T::CAMCTL: AUP Mask               */
+
+#define EMAC_CAMCTL_AMP_Pos              (1)                                               /*!< EMAC_T::CAMCTL: AMP Position           */
+#define EMAC_CAMCTL_AMP_Msk              (0x1ul << EMAC_CAMCTL_AMP_Pos)                    /*!< EMAC_T::CAMCTL: AMP Mask               */
+
+#define EMAC_CAMCTL_ABP_Pos              (2)                                               /*!< EMAC_T::CAMCTL: ABP Position           */
+#define EMAC_CAMCTL_ABP_Msk              (0x1ul << EMAC_CAMCTL_ABP_Pos)                    /*!< EMAC_T::CAMCTL: ABP Mask               */
+
+#define EMAC_CAMCTL_COMPEN_Pos           (3)                                               /*!< EMAC_T::CAMCTL: COMPEN Position        */
+#define EMAC_CAMCTL_COMPEN_Msk           (0x1ul << EMAC_CAMCTL_COMPEN_Pos)                 /*!< EMAC_T::CAMCTL: COMPEN Mask            */
+
+#define EMAC_CAMCTL_CMPEN_Pos            (4)                                               /*!< EMAC_T::CAMCTL: CMPEN Position         */
+#define EMAC_CAMCTL_CMPEN_Msk            (0x1ul << EMAC_CAMCTL_CMPEN_Pos)                  /*!< EMAC_T::CAMCTL: CMPEN Mask             */
+
+#define EMAC_CAMEN_CAMxEN_Pos            (0)                                               /*!< EMAC_T::CAMEN: CAMxEN Position         */
+#define EMAC_CAMEN_CAMxEN_Msk            (0x1ul << EMAC_CAMEN_CAMxEN_Pos)                  /*!< EMAC_T::CAMEN: CAMxEN Mask             */
+
+#define EMAC_CAM0M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM0M: MACADDR2 Position       */
+#define EMAC_CAM0M_MACADDR2_Msk          (0xfful << EMAC_CAM0M_MACADDR2_Pos)               /*!< EMAC_T::CAM0M: MACADDR2 Mask           */
+
+#define EMAC_CAM0M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM0M: MACADDR3 Position       */
+#define EMAC_CAM0M_MACADDR3_Msk          (0xfful << EMAC_CAM0M_MACADDR3_Pos)               /*!< EMAC_T::CAM0M: MACADDR3 Mask           */
+
+#define EMAC_CAM0M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM0M: MACADDR4 Position       */
+#define EMAC_CAM0M_MACADDR4_Msk          (0xfful << EMAC_CAM0M_MACADDR4_Pos)               /*!< EMAC_T::CAM0M: MACADDR4 Mask           */
+
+#define EMAC_CAM0M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM0M: MACADDR5 Position       */
+#define EMAC_CAM0M_MACADDR5_Msk          (0xfful << EMAC_CAM0M_MACADDR5_Pos)               /*!< EMAC_T::CAM0M: MACADDR5 Mask           */
+
+#define EMAC_CAM0L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM0L: MACADDR0 Position       */
+#define EMAC_CAM0L_MACADDR0_Msk          (0xfful << EMAC_CAM0L_MACADDR0_Pos)               /*!< EMAC_T::CAM0L: MACADDR0 Mask           */
+
+#define EMAC_CAM0L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM0L: MACADDR1 Position       */
+#define EMAC_CAM0L_MACADDR1_Msk          (0xfful << EMAC_CAM0L_MACADDR1_Pos)               /*!< EMAC_T::CAM0L: MACADDR1 Mask           */
+
+#define EMAC_CAM1M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM1M: MACADDR2 Position       */
+#define EMAC_CAM1M_MACADDR2_Msk          (0xfful << EMAC_CAM1M_MACADDR2_Pos)               /*!< EMAC_T::CAM1M: MACADDR2 Mask           */
+
+#define EMAC_CAM1M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM1M: MACADDR3 Position       */
+#define EMAC_CAM1M_MACADDR3_Msk          (0xfful << EMAC_CAM1M_MACADDR3_Pos)               /*!< EMAC_T::CAM1M: MACADDR3 Mask           */
+
+#define EMAC_CAM1M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM1M: MACADDR4 Position       */
+#define EMAC_CAM1M_MACADDR4_Msk          (0xfful << EMAC_CAM1M_MACADDR4_Pos)               /*!< EMAC_T::CAM1M: MACADDR4 Mask           */
+
+#define EMAC_CAM1M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM1M: MACADDR5 Position       */
+#define EMAC_CAM1M_MACADDR5_Msk          (0xfful << EMAC_CAM1M_MACADDR5_Pos)               /*!< EMAC_T::CAM1M: MACADDR5 Mask           */
+
+#define EMAC_CAM1L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM1L: MACADDR0 Position       */
+#define EMAC_CAM1L_MACADDR0_Msk          (0xfful << EMAC_CAM1L_MACADDR0_Pos)               /*!< EMAC_T::CAM1L: MACADDR0 Mask           */
+
+#define EMAC_CAM1L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM1L: MACADDR1 Position       */
+#define EMAC_CAM1L_MACADDR1_Msk          (0xfful << EMAC_CAM1L_MACADDR1_Pos)               /*!< EMAC_T::CAM1L: MACADDR1 Mask           */
+
+#define EMAC_CAM2M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM2M: MACADDR2 Position       */
+#define EMAC_CAM2M_MACADDR2_Msk          (0xfful << EMAC_CAM2M_MACADDR2_Pos)               /*!< EMAC_T::CAM2M: MACADDR2 Mask           */
+
+#define EMAC_CAM2M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM2M: MACADDR3 Position       */
+#define EMAC_CAM2M_MACADDR3_Msk          (0xfful << EMAC_CAM2M_MACADDR3_Pos)               /*!< EMAC_T::CAM2M: MACADDR3 Mask           */
+
+#define EMAC_CAM2M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM2M: MACADDR4 Position       */
+#define EMAC_CAM2M_MACADDR4_Msk          (0xfful << EMAC_CAM2M_MACADDR4_Pos)               /*!< EMAC_T::CAM2M: MACADDR4 Mask           */
+
+#define EMAC_CAM2M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM2M: MACADDR5 Position       */
+#define EMAC_CAM2M_MACADDR5_Msk          (0xfful << EMAC_CAM2M_MACADDR5_Pos)               /*!< EMAC_T::CAM2M: MACADDR5 Mask           */
+
+#define EMAC_CAM2L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM2L: MACADDR0 Position       */
+#define EMAC_CAM2L_MACADDR0_Msk          (0xfful << EMAC_CAM2L_MACADDR0_Pos)               /*!< EMAC_T::CAM2L: MACADDR0 Mask           */
+
+#define EMAC_CAM2L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM2L: MACADDR1 Position       */
+#define EMAC_CAM2L_MACADDR1_Msk          (0xfful << EMAC_CAM2L_MACADDR1_Pos)               /*!< EMAC_T::CAM2L: MACADDR1 Mask           */
+
+#define EMAC_CAM3M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM3M: MACADDR2 Position       */
+#define EMAC_CAM3M_MACADDR2_Msk          (0xfful << EMAC_CAM3M_MACADDR2_Pos)               /*!< EMAC_T::CAM3M: MACADDR2 Mask           */
+
+#define EMAC_CAM3M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM3M: MACADDR3 Position       */
+#define EMAC_CAM3M_MACADDR3_Msk          (0xfful << EMAC_CAM3M_MACADDR3_Pos)               /*!< EMAC_T::CAM3M: MACADDR3 Mask           */
+
+#define EMAC_CAM3M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM3M: MACADDR4 Position       */
+#define EMAC_CAM3M_MACADDR4_Msk          (0xfful << EMAC_CAM3M_MACADDR4_Pos)               /*!< EMAC_T::CAM3M: MACADDR4 Mask           */
+
+#define EMAC_CAM3M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM3M: MACADDR5 Position       */
+#define EMAC_CAM3M_MACADDR5_Msk          (0xfful << EMAC_CAM3M_MACADDR5_Pos)               /*!< EMAC_T::CAM3M: MACADDR5 Mask           */
+
+#define EMAC_CAM3L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM3L: MACADDR0 Position       */
+#define EMAC_CAM3L_MACADDR0_Msk          (0xfful << EMAC_CAM3L_MACADDR0_Pos)               /*!< EMAC_T::CAM3L: MACADDR0 Mask           */
+
+#define EMAC_CAM3L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM3L: MACADDR1 Position       */
+#define EMAC_CAM3L_MACADDR1_Msk          (0xfful << EMAC_CAM3L_MACADDR1_Pos)               /*!< EMAC_T::CAM3L: MACADDR1 Mask           */
+
+#define EMAC_CAM4M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM4M: MACADDR2 Position       */
+#define EMAC_CAM4M_MACADDR2_Msk          (0xfful << EMAC_CAM4M_MACADDR2_Pos)               /*!< EMAC_T::CAM4M: MACADDR2 Mask           */
+
+#define EMAC_CAM4M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM4M: MACADDR3 Position       */
+#define EMAC_CAM4M_MACADDR3_Msk          (0xfful << EMAC_CAM4M_MACADDR3_Pos)               /*!< EMAC_T::CAM4M: MACADDR3 Mask           */
+
+#define EMAC_CAM4M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM4M: MACADDR4 Position       */
+#define EMAC_CAM4M_MACADDR4_Msk          (0xfful << EMAC_CAM4M_MACADDR4_Pos)               /*!< EMAC_T::CAM4M: MACADDR4 Mask           */
+
+#define EMAC_CAM4M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM4M: MACADDR5 Position       */
+#define EMAC_CAM4M_MACADDR5_Msk          (0xfful << EMAC_CAM4M_MACADDR5_Pos)               /*!< EMAC_T::CAM4M: MACADDR5 Mask           */
+
+#define EMAC_CAM4L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM4L: MACADDR0 Position       */
+#define EMAC_CAM4L_MACADDR0_Msk          (0xfful << EMAC_CAM4L_MACADDR0_Pos)               /*!< EMAC_T::CAM4L: MACADDR0 Mask           */
+
+#define EMAC_CAM4L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM4L: MACADDR1 Position       */
+#define EMAC_CAM4L_MACADDR1_Msk          (0xfful << EMAC_CAM4L_MACADDR1_Pos)               /*!< EMAC_T::CAM4L: MACADDR1 Mask           */
+
+#define EMAC_CAM5M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM5M: MACADDR2 Position       */
+#define EMAC_CAM5M_MACADDR2_Msk          (0xfful << EMAC_CAM5M_MACADDR2_Pos)               /*!< EMAC_T::CAM5M: MACADDR2 Mask           */
+
+#define EMAC_CAM5M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM5M: MACADDR3 Position       */
+#define EMAC_CAM5M_MACADDR3_Msk          (0xfful << EMAC_CAM5M_MACADDR3_Pos)               /*!< EMAC_T::CAM5M: MACADDR3 Mask           */
+
+#define EMAC_CAM5M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM5M: MACADDR4 Position       */
+#define EMAC_CAM5M_MACADDR4_Msk          (0xfful << EMAC_CAM5M_MACADDR4_Pos)               /*!< EMAC_T::CAM5M: MACADDR4 Mask           */
+
+#define EMAC_CAM5M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM5M: MACADDR5 Position       */
+#define EMAC_CAM5M_MACADDR5_Msk          (0xfful << EMAC_CAM5M_MACADDR5_Pos)               /*!< EMAC_T::CAM5M: MACADDR5 Mask           */
+
+#define EMAC_CAM5L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM5L: MACADDR0 Position       */
+#define EMAC_CAM5L_MACADDR0_Msk          (0xfful << EMAC_CAM5L_MACADDR0_Pos)               /*!< EMAC_T::CAM5L: MACADDR0 Mask           */
+
+#define EMAC_CAM5L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM5L: MACADDR1 Position       */
+#define EMAC_CAM5L_MACADDR1_Msk          (0xfful << EMAC_CAM5L_MACADDR1_Pos)               /*!< EMAC_T::CAM5L: MACADDR1 Mask           */
+
+#define EMAC_CAM6M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM6M: MACADDR2 Position       */
+#define EMAC_CAM6M_MACADDR2_Msk          (0xfful << EMAC_CAM6M_MACADDR2_Pos)               /*!< EMAC_T::CAM6M: MACADDR2 Mask           */
+
+#define EMAC_CAM6M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM6M: MACADDR3 Position       */
+#define EMAC_CAM6M_MACADDR3_Msk          (0xfful << EMAC_CAM6M_MACADDR3_Pos)               /*!< EMAC_T::CAM6M: MACADDR3 Mask           */
+
+#define EMAC_CAM6M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM6M: MACADDR4 Position       */
+#define EMAC_CAM6M_MACADDR4_Msk          (0xfful << EMAC_CAM6M_MACADDR4_Pos)               /*!< EMAC_T::CAM6M: MACADDR4 Mask           */
+
+#define EMAC_CAM6M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM6M: MACADDR5 Position       */
+#define EMAC_CAM6M_MACADDR5_Msk          (0xfful << EMAC_CAM6M_MACADDR5_Pos)               /*!< EMAC_T::CAM6M: MACADDR5 Mask           */
+
+#define EMAC_CAM6L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM6L: MACADDR0 Position       */
+#define EMAC_CAM6L_MACADDR0_Msk          (0xfful << EMAC_CAM6L_MACADDR0_Pos)               /*!< EMAC_T::CAM6L: MACADDR0 Mask           */
+
+#define EMAC_CAM6L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM6L: MACADDR1 Position       */
+#define EMAC_CAM6L_MACADDR1_Msk          (0xfful << EMAC_CAM6L_MACADDR1_Pos)               /*!< EMAC_T::CAM6L: MACADDR1 Mask           */
+
+#define EMAC_CAM7M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM7M: MACADDR2 Position       */
+#define EMAC_CAM7M_MACADDR2_Msk          (0xfful << EMAC_CAM7M_MACADDR2_Pos)               /*!< EMAC_T::CAM7M: MACADDR2 Mask           */
+
+#define EMAC_CAM7M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM7M: MACADDR3 Position       */
+#define EMAC_CAM7M_MACADDR3_Msk          (0xfful << EMAC_CAM7M_MACADDR3_Pos)               /*!< EMAC_T::CAM7M: MACADDR3 Mask           */
+
+#define EMAC_CAM7M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM7M: MACADDR4 Position       */
+#define EMAC_CAM7M_MACADDR4_Msk          (0xfful << EMAC_CAM7M_MACADDR4_Pos)               /*!< EMAC_T::CAM7M: MACADDR4 Mask           */
+
+#define EMAC_CAM7M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM7M: MACADDR5 Position       */
+#define EMAC_CAM7M_MACADDR5_Msk          (0xfful << EMAC_CAM7M_MACADDR5_Pos)               /*!< EMAC_T::CAM7M: MACADDR5 Mask           */
+
+#define EMAC_CAM7L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM7L: MACADDR0 Position       */
+#define EMAC_CAM7L_MACADDR0_Msk          (0xfful << EMAC_CAM7L_MACADDR0_Pos)               /*!< EMAC_T::CAM7L: MACADDR0 Mask           */
+
+#define EMAC_CAM7L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM7L: MACADDR1 Position       */
+#define EMAC_CAM7L_MACADDR1_Msk          (0xfful << EMAC_CAM7L_MACADDR1_Pos)               /*!< EMAC_T::CAM7L: MACADDR1 Mask           */
+
+#define EMAC_CAM8M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM8M: MACADDR2 Position       */
+#define EMAC_CAM8M_MACADDR2_Msk          (0xfful << EMAC_CAM8M_MACADDR2_Pos)               /*!< EMAC_T::CAM8M: MACADDR2 Mask           */
+
+#define EMAC_CAM8M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM8M: MACADDR3 Position       */
+#define EMAC_CAM8M_MACADDR3_Msk          (0xfful << EMAC_CAM8M_MACADDR3_Pos)               /*!< EMAC_T::CAM8M: MACADDR3 Mask           */
+
+#define EMAC_CAM8M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM8M: MACADDR4 Position       */
+#define EMAC_CAM8M_MACADDR4_Msk          (0xfful << EMAC_CAM8M_MACADDR4_Pos)               /*!< EMAC_T::CAM8M: MACADDR4 Mask           */
+
+#define EMAC_CAM8M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM8M: MACADDR5 Position       */
+#define EMAC_CAM8M_MACADDR5_Msk          (0xfful << EMAC_CAM8M_MACADDR5_Pos)               /*!< EMAC_T::CAM8M: MACADDR5 Mask           */
+
+#define EMAC_CAM8L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM8L: MACADDR0 Position       */
+#define EMAC_CAM8L_MACADDR0_Msk          (0xfful << EMAC_CAM8L_MACADDR0_Pos)               /*!< EMAC_T::CAM8L: MACADDR0 Mask           */
+
+#define EMAC_CAM8L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM8L: MACADDR1 Position       */
+#define EMAC_CAM8L_MACADDR1_Msk          (0xfful << EMAC_CAM8L_MACADDR1_Pos)               /*!< EMAC_T::CAM8L: MACADDR1 Mask           */
+
+#define EMAC_CAM9M_MACADDR2_Pos          (0)                                               /*!< EMAC_T::CAM9M: MACADDR2 Position       */
+#define EMAC_CAM9M_MACADDR2_Msk          (0xfful << EMAC_CAM9M_MACADDR2_Pos)               /*!< EMAC_T::CAM9M: MACADDR2 Mask           */
+
+#define EMAC_CAM9M_MACADDR3_Pos          (8)                                               /*!< EMAC_T::CAM9M: MACADDR3 Position       */
+#define EMAC_CAM9M_MACADDR3_Msk          (0xfful << EMAC_CAM9M_MACADDR3_Pos)               /*!< EMAC_T::CAM9M: MACADDR3 Mask           */
+
+#define EMAC_CAM9M_MACADDR4_Pos          (16)                                              /*!< EMAC_T::CAM9M: MACADDR4 Position       */
+#define EMAC_CAM9M_MACADDR4_Msk          (0xfful << EMAC_CAM9M_MACADDR4_Pos)               /*!< EMAC_T::CAM9M: MACADDR4 Mask           */
+
+#define EMAC_CAM9M_MACADDR5_Pos          (24)                                              /*!< EMAC_T::CAM9M: MACADDR5 Position       */
+#define EMAC_CAM9M_MACADDR5_Msk          (0xfful << EMAC_CAM9M_MACADDR5_Pos)               /*!< EMAC_T::CAM9M: MACADDR5 Mask           */
+
+#define EMAC_CAM9L_MACADDR0_Pos          (16)                                              /*!< EMAC_T::CAM9L: MACADDR0 Position       */
+#define EMAC_CAM9L_MACADDR0_Msk          (0xfful << EMAC_CAM9L_MACADDR0_Pos)               /*!< EMAC_T::CAM9L: MACADDR0 Mask           */
+
+#define EMAC_CAM9L_MACADDR1_Pos          (24)                                              /*!< EMAC_T::CAM9L: MACADDR1 Position       */
+#define EMAC_CAM9L_MACADDR1_Msk          (0xfful << EMAC_CAM9L_MACADDR1_Pos)               /*!< EMAC_T::CAM9L: MACADDR1 Mask           */
+
+#define EMAC_CAM10M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM10M: MACADDR2 Position      */
+#define EMAC_CAM10M_MACADDR2_Msk         (0xfful << EMAC_CAM10M_MACADDR2_Pos)              /*!< EMAC_T::CAM10M: MACADDR2 Mask          */
+
+#define EMAC_CAM10M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM10M: MACADDR3 Position      */
+#define EMAC_CAM10M_MACADDR3_Msk         (0xfful << EMAC_CAM10M_MACADDR3_Pos)              /*!< EMAC_T::CAM10M: MACADDR3 Mask          */
+
+#define EMAC_CAM10M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM10M: MACADDR4 Position      */
+#define EMAC_CAM10M_MACADDR4_Msk         (0xfful << EMAC_CAM10M_MACADDR4_Pos)              /*!< EMAC_T::CAM10M: MACADDR4 Mask          */
+
+#define EMAC_CAM10M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM10M: MACADDR5 Position      */
+#define EMAC_CAM10M_MACADDR5_Msk         (0xfful << EMAC_CAM10M_MACADDR5_Pos)              /*!< EMAC_T::CAM10M: MACADDR5 Mask          */
+
+#define EMAC_CAM10L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM10L: MACADDR0 Position      */
+#define EMAC_CAM10L_MACADDR0_Msk         (0xfful << EMAC_CAM10L_MACADDR0_Pos)              /*!< EMAC_T::CAM10L: MACADDR0 Mask          */
+
+#define EMAC_CAM10L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM10L: MACADDR1 Position      */
+#define EMAC_CAM10L_MACADDR1_Msk         (0xfful << EMAC_CAM10L_MACADDR1_Pos)              /*!< EMAC_T::CAM10L: MACADDR1 Mask          */
+
+#define EMAC_CAM11M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM11M: MACADDR2 Position      */
+#define EMAC_CAM11M_MACADDR2_Msk         (0xfful << EMAC_CAM11M_MACADDR2_Pos)              /*!< EMAC_T::CAM11M: MACADDR2 Mask          */
+
+#define EMAC_CAM11M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM11M: MACADDR3 Position      */
+#define EMAC_CAM11M_MACADDR3_Msk         (0xfful << EMAC_CAM11M_MACADDR3_Pos)              /*!< EMAC_T::CAM11M: MACADDR3 Mask          */
+
+#define EMAC_CAM11M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM11M: MACADDR4 Position      */
+#define EMAC_CAM11M_MACADDR4_Msk         (0xfful << EMAC_CAM11M_MACADDR4_Pos)              /*!< EMAC_T::CAM11M: MACADDR4 Mask          */
+
+#define EMAC_CAM11M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM11M: MACADDR5 Position      */
+#define EMAC_CAM11M_MACADDR5_Msk         (0xfful << EMAC_CAM11M_MACADDR5_Pos)              /*!< EMAC_T::CAM11M: MACADDR5 Mask          */
+
+#define EMAC_CAM11L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM11L: MACADDR0 Position      */
+#define EMAC_CAM11L_MACADDR0_Msk         (0xfful << EMAC_CAM11L_MACADDR0_Pos)              /*!< EMAC_T::CAM11L: MACADDR0 Mask          */
+
+#define EMAC_CAM11L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM11L: MACADDR1 Position      */
+#define EMAC_CAM11L_MACADDR1_Msk         (0xfful << EMAC_CAM11L_MACADDR1_Pos)              /*!< EMAC_T::CAM11L: MACADDR1 Mask          */
+
+#define EMAC_CAM12M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM12M: MACADDR2 Position      */
+#define EMAC_CAM12M_MACADDR2_Msk         (0xfful << EMAC_CAM12M_MACADDR2_Pos)              /*!< EMAC_T::CAM12M: MACADDR2 Mask          */
+
+#define EMAC_CAM12M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM12M: MACADDR3 Position      */
+#define EMAC_CAM12M_MACADDR3_Msk         (0xfful << EMAC_CAM12M_MACADDR3_Pos)              /*!< EMAC_T::CAM12M: MACADDR3 Mask          */
+
+#define EMAC_CAM12M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM12M: MACADDR4 Position      */
+#define EMAC_CAM12M_MACADDR4_Msk         (0xfful << EMAC_CAM12M_MACADDR4_Pos)              /*!< EMAC_T::CAM12M: MACADDR4 Mask          */
+
+#define EMAC_CAM12M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM12M: MACADDR5 Position      */
+#define EMAC_CAM12M_MACADDR5_Msk         (0xfful << EMAC_CAM12M_MACADDR5_Pos)              /*!< EMAC_T::CAM12M: MACADDR5 Mask          */
+
+#define EMAC_CAM12L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM12L: MACADDR0 Position      */
+#define EMAC_CAM12L_MACADDR0_Msk         (0xfful << EMAC_CAM12L_MACADDR0_Pos)              /*!< EMAC_T::CAM12L: MACADDR0 Mask          */
+
+#define EMAC_CAM12L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM12L: MACADDR1 Position      */
+#define EMAC_CAM12L_MACADDR1_Msk         (0xfful << EMAC_CAM12L_MACADDR1_Pos)              /*!< EMAC_T::CAM12L: MACADDR1 Mask          */
+
+#define EMAC_CAM13M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM13M: MACADDR2 Position      */
+#define EMAC_CAM13M_MACADDR2_Msk         (0xfful << EMAC_CAM13M_MACADDR2_Pos)              /*!< EMAC_T::CAM13M: MACADDR2 Mask          */
+
+#define EMAC_CAM13M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM13M: MACADDR3 Position      */
+#define EMAC_CAM13M_MACADDR3_Msk         (0xfful << EMAC_CAM13M_MACADDR3_Pos)              /*!< EMAC_T::CAM13M: MACADDR3 Mask          */
+
+#define EMAC_CAM13M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM13M: MACADDR4 Position      */
+#define EMAC_CAM13M_MACADDR4_Msk         (0xfful << EMAC_CAM13M_MACADDR4_Pos)              /*!< EMAC_T::CAM13M: MACADDR4 Mask          */
+
+#define EMAC_CAM13M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM13M: MACADDR5 Position      */
+#define EMAC_CAM13M_MACADDR5_Msk         (0xfful << EMAC_CAM13M_MACADDR5_Pos)              /*!< EMAC_T::CAM13M: MACADDR5 Mask          */
+
+#define EMAC_CAM13L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM13L: MACADDR0 Position      */
+#define EMAC_CAM13L_MACADDR0_Msk         (0xfful << EMAC_CAM13L_MACADDR0_Pos)              /*!< EMAC_T::CAM13L: MACADDR0 Mask          */
+
+#define EMAC_CAM13L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM13L: MACADDR1 Position      */
+#define EMAC_CAM13L_MACADDR1_Msk         (0xfful << EMAC_CAM13L_MACADDR1_Pos)              /*!< EMAC_T::CAM13L: MACADDR1 Mask          */
+
+#define EMAC_CAM14M_MACADDR2_Pos         (0)                                               /*!< EMAC_T::CAM14M: MACADDR2 Position      */
+#define EMAC_CAM14M_MACADDR2_Msk         (0xfful << EMAC_CAM14M_MACADDR2_Pos)              /*!< EMAC_T::CAM14M: MACADDR2 Mask          */
+
+#define EMAC_CAM14M_MACADDR3_Pos         (8)                                               /*!< EMAC_T::CAM14M: MACADDR3 Position      */
+#define EMAC_CAM14M_MACADDR3_Msk         (0xfful << EMAC_CAM14M_MACADDR3_Pos)              /*!< EMAC_T::CAM14M: MACADDR3 Mask          */
+
+#define EMAC_CAM14M_MACADDR4_Pos         (16)                                              /*!< EMAC_T::CAM14M: MACADDR4 Position      */
+#define EMAC_CAM14M_MACADDR4_Msk         (0xfful << EMAC_CAM14M_MACADDR4_Pos)              /*!< EMAC_T::CAM14M: MACADDR4 Mask          */
+
+#define EMAC_CAM14M_MACADDR5_Pos         (24)                                              /*!< EMAC_T::CAM14M: MACADDR5 Position      */
+#define EMAC_CAM14M_MACADDR5_Msk         (0xfful << EMAC_CAM14M_MACADDR5_Pos)              /*!< EMAC_T::CAM14M: MACADDR5 Mask          */
+
+#define EMAC_CAM14L_MACADDR0_Pos         (16)                                              /*!< EMAC_T::CAM14L: MACADDR0 Position      */
+#define EMAC_CAM14L_MACADDR0_Msk         (0xfful << EMAC_CAM14L_MACADDR0_Pos)              /*!< EMAC_T::CAM14L: MACADDR0 Mask          */
+
+#define EMAC_CAM14L_MACADDR1_Pos         (24)                                              /*!< EMAC_T::CAM14L: MACADDR1 Position      */
+#define EMAC_CAM14L_MACADDR1_Msk         (0xfful << EMAC_CAM14L_MACADDR1_Pos)              /*!< EMAC_T::CAM14L: MACADDR1 Mask          */
+
+#define EMAC_CAM15MSB_OPCODE_Pos         (0)                                               /*!< EMAC_T::CAM15MSB: OPCODE Position      */
+#define EMAC_CAM15MSB_OPCODE_Msk         (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)            /*!< EMAC_T::CAM15MSB: OPCODE Mask          */
+
+#define EMAC_CAM15MSB_LENGTH_Pos         (16)                                              /*!< EMAC_T::CAM15MSB: LENGTH Position      */
+#define EMAC_CAM15MSB_LENGTH_Msk         (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)            /*!< EMAC_T::CAM15MSB: LENGTH Mask          */
+
+#define EMAC_CAM15LSB_OPERAND_Pos        (24)                                              /*!< EMAC_T::CAM15LSB: OPERAND Position     */
+#define EMAC_CAM15LSB_OPERAND_Msk        (0xfful << EMAC_CAM15LSB_OPERAND_Pos)             /*!< EMAC_T::CAM15LSB: OPERAND Mask         */
+
+#define EMAC_TXDSA_TXDSA_Pos             (0)                                               /*!< EMAC_T::TXDSA: TXDSA Position          */
+#define EMAC_TXDSA_TXDSA_Msk             (0xfffffffful << EMAC_TXDSA_TXDSA_Pos)            /*!< EMAC_T::TXDSA: TXDSA Mask              */
+
+#define EMAC_RXDSA_RXDSA_Pos             (0)                                               /*!< EMAC_T::RXDSA: RXDSA Position          */
+#define EMAC_RXDSA_RXDSA_Msk             (0xfffffffful << EMAC_RXDSA_RXDSA_Pos)            /*!< EMAC_T::RXDSA: RXDSA Mask              */
+
+#define EMAC_CTL_RXON_Pos                (0)                                               /*!< EMAC_T::CTL: RXON Position             */
+#define EMAC_CTL_RXON_Msk                (0x1ul << EMAC_CTL_RXON_Pos)                      /*!< EMAC_T::CTL: RXON Mask                 */
+
+#define EMAC_CTL_ALP_Pos                 (1)                                               /*!< EMAC_T::CTL: ALP Position              */
+#define EMAC_CTL_ALP_Msk                 (0x1ul << EMAC_CTL_ALP_Pos)                       /*!< EMAC_T::CTL: ALP Mask                  */
+
+#define EMAC_CTL_ARP_Pos                 (2)                                               /*!< EMAC_T::CTL: ARP Position              */
+#define EMAC_CTL_ARP_Msk                 (0x1ul << EMAC_CTL_ARP_Pos)                       /*!< EMAC_T::CTL: ARP Mask                  */
+
+#define EMAC_CTL_ACP_Pos                 (3)                                               /*!< EMAC_T::CTL: ACP Position              */
+#define EMAC_CTL_ACP_Msk                 (0x1ul << EMAC_CTL_ACP_Pos)                       /*!< EMAC_T::CTL: ACP Mask                  */
+
+#define EMAC_CTL_AEP_Pos                 (4)                                               /*!< EMAC_T::CTL: AEP Position              */
+#define EMAC_CTL_AEP_Msk                 (0x1ul << EMAC_CTL_AEP_Pos)                       /*!< EMAC_T::CTL: AEP Mask                  */
+
+#define EMAC_CTL_STRIPCRC_Pos            (5)                                               /*!< EMAC_T::CTL: STRIPCRC Position         */
+#define EMAC_CTL_STRIPCRC_Msk            (0x1ul << EMAC_CTL_STRIPCRC_Pos)                  /*!< EMAC_T::CTL: STRIPCRC Mask             */
+
+#define EMAC_CTL_WOLEN_Pos               (6)                                               /*!< EMAC_T::CTL: WOLEN Position            */
+#define EMAC_CTL_WOLEN_Msk               (0x1ul << EMAC_CTL_WOLEN_Pos)                     /*!< EMAC_T::CTL: WOLEN Mask                */
+
+#define EMAC_CTL_TXON_Pos                (8)                                               /*!< EMAC_T::CTL: TXON Position             */
+#define EMAC_CTL_TXON_Msk                (0x1ul << EMAC_CTL_TXON_Pos)                      /*!< EMAC_T::CTL: TXON Mask                 */
+
+#define EMAC_CTL_NODEF_Pos               (9)                                               /*!< EMAC_T::CTL: NODEF Position            */
+#define EMAC_CTL_NODEF_Msk               (0x1ul << EMAC_CTL_NODEF_Pos)                     /*!< EMAC_T::CTL: NODEF Mask                */
+
+#define EMAC_CTL_SDPZ_Pos                (16)                                              /*!< EMAC_T::CTL: SDPZ Position             */
+#define EMAC_CTL_SDPZ_Msk                (0x1ul << EMAC_CTL_SDPZ_Pos)                      /*!< EMAC_T::CTL: SDPZ Mask                 */
+
+#define EMAC_CTL_SQECHKEN_Pos            (17)                                              /*!< EMAC_T::CTL: SQECHKEN Position         */
+#define EMAC_CTL_SQECHKEN_Msk            (0x1ul << EMAC_CTL_SQECHKEN_Pos)                  /*!< EMAC_T::CTL: SQECHKEN Mask             */
+
+#define EMAC_CTL_FUDUP_Pos               (18)                                              /*!< EMAC_T::CTL: FUDUP Position            */
+#define EMAC_CTL_FUDUP_Msk               (0x1ul << EMAC_CTL_FUDUP_Pos)                     /*!< EMAC_T::CTL: FUDUP Mask                */
+
+#define EMAC_CTL_RMIIRXCTL_Pos           (19)                                              /*!< EMAC_T::CTL: RMIIRXCTL Position        */
+#define EMAC_CTL_RMIIRXCTL_Msk           (0x1ul << EMAC_CTL_RMIIRXCTL_Pos)                 /*!< EMAC_T::CTL: RMIIRXCTL Mask            */
+
+#define EMAC_CTL_OPMODE_Pos              (20)                                              /*!< EMAC_T::CTL: OPMODE Position           */
+#define EMAC_CTL_OPMODE_Msk              (0x1ul << EMAC_CTL_OPMODE_Pos)                    /*!< EMAC_T::CTL: OPMODE Mask               */
+
+#define EMAC_CTL_RMIIEN_Pos              (22)                                              /*!< EMAC_T::CTL: RMIIEN Position           */
+#define EMAC_CTL_RMIIEN_Msk              (0x1ul << EMAC_CTL_RMIIEN_Pos)                    /*!< EMAC_T::CTL: RMIIEN Mask               */
+
+#define EMAC_CTL_RST_Pos                 (24)                                              /*!< EMAC_T::CTL: RST Position              */
+#define EMAC_CTL_RST_Msk                 (0x1ul << EMAC_CTL_RST_Pos)                       /*!< EMAC_T::CTL: RST Mask                  */
+
+#define EMAC_MIIMDAT_DATA_Pos            (0)                                               /*!< EMAC_T::MIIMDAT: DATA Position         */
+#define EMAC_MIIMDAT_DATA_Msk            (0xfffful << EMAC_MIIMDAT_DATA_Pos)               /*!< EMAC_T::MIIMDAT: DATA Mask             */
+
+#define EMAC_MIIMCTL_PHYREG_Pos          (0)                                               /*!< EMAC_T::MIIMCTL: PHYREG Position       */
+#define EMAC_MIIMCTL_PHYREG_Msk          (0x1ful << EMAC_MIIMCTL_PHYREG_Pos)               /*!< EMAC_T::MIIMCTL: PHYREG Mask           */
+
+#define EMAC_MIIMCTL_PHYADDR_Pos         (8)                                               /*!< EMAC_T::MIIMCTL: PHYADDR Position      */
+#define EMAC_MIIMCTL_PHYADDR_Msk         (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos)              /*!< EMAC_T::MIIMCTL: PHYADDR Mask          */
+
+#define EMAC_MIIMCTL_WRITE_Pos           (16)                                              /*!< EMAC_T::MIIMCTL: WRITE Position        */
+#define EMAC_MIIMCTL_WRITE_Msk           (0x1ul << EMAC_MIIMCTL_WRITE_Pos)                 /*!< EMAC_T::MIIMCTL: WRITE Mask            */
+
+#define EMAC_MIIMCTL_BUSY_Pos            (17)                                              /*!< EMAC_T::MIIMCTL: BUSY Position         */
+#define EMAC_MIIMCTL_BUSY_Msk            (0x1ul << EMAC_MIIMCTL_BUSY_Pos)                  /*!< EMAC_T::MIIMCTL: BUSY Mask             */
+
+#define EMAC_MIIMCTL_PREAMSP_Pos         (18)                                              /*!< EMAC_T::MIIMCTL: PREAMSP Position      */
+#define EMAC_MIIMCTL_PREAMSP_Msk         (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos)               /*!< EMAC_T::MIIMCTL: PREAMSP Mask          */
+
+#define EMAC_MIIMCTL_MDCON_Pos           (19)                                              /*!< EMAC_T::MIIMCTL: MDCON Position        */
+#define EMAC_MIIMCTL_MDCON_Msk           (0x1ul << EMAC_MIIMCTL_MDCON_Pos)                 /*!< EMAC_T::MIIMCTL: MDCON Mask            */
+
+#define EMAC_FIFOCTL_RXFIFOTH_Pos        (0)                                               /*!< EMAC_T::FIFOCTL: RXFIFOTH Position     */
+#define EMAC_FIFOCTL_RXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos)              /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask         */
+
+#define EMAC_FIFOCTL_TXFIFOTH_Pos        (8)                                               /*!< EMAC_T::FIFOCTL: TXFIFOTH Position     */
+#define EMAC_FIFOCTL_TXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos)              /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask         */
+
+#define EMAC_FIFOCTL_BURSTLEN_Pos        (20)                                              /*!< EMAC_T::FIFOCTL: BURSTLEN Position     */
+#define EMAC_FIFOCTL_BURSTLEN_Msk        (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos)              /*!< EMAC_T::FIFOCTL: BURSTLEN Mask         */
+
+#define EMAC_TXST_TXST_Pos               (0)                                               /*!< EMAC_T::TXST: TXST Position            */
+#define EMAC_TXST_TXST_Msk               (0xfffffffful << EMAC_TXST_TXST_Pos)              /*!< EMAC_T::TXST: TXST Mask                */
+
+#define EMAC_RXST_RXST_Pos               (0)                                               /*!< EMAC_T::RXST: RXST Position            */
+#define EMAC_RXST_RXST_Msk               (0xfffffffful << EMAC_RXST_RXST_Pos)              /*!< EMAC_T::RXST: RXST Mask                */
+
+#define EMAC_MRFL_MRFL_Pos               (0)                                               /*!< EMAC_T::MRFL: MRFL Position            */
+#define EMAC_MRFL_MRFL_Msk               (0xfffful << EMAC_MRFL_MRFL_Pos)                  /*!< EMAC_T::MRFL: MRFL Mask                */
+
+#define EMAC_INTEN_RXIEN_Pos             (0)                                               /*!< EMAC_T::INTEN: RXIEN Position          */
+#define EMAC_INTEN_RXIEN_Msk             (0x1ul << EMAC_INTEN_RXIEN_Pos)                   /*!< EMAC_T::INTEN: RXIEN Mask              */
+
+#define EMAC_INTEN_CRCEIEN_Pos           (1)                                               /*!< EMAC_T::INTEN: CRCEIEN Position        */
+#define EMAC_INTEN_CRCEIEN_Msk           (0x1ul << EMAC_INTEN_CRCEIEN_Pos)                 /*!< EMAC_T::INTEN: CRCEIEN Mask            */
+
+#define EMAC_INTEN_RXOVIEN_Pos           (2)                                               /*!< EMAC_T::INTEN: RXOVIEN Position        */
+#define EMAC_INTEN_RXOVIEN_Msk           (0x1ul << EMAC_INTEN_RXOVIEN_Pos)                 /*!< EMAC_T::INTEN: RXOVIEN Mask            */
+
+#define EMAC_INTEN_LPIEN_Pos             (3)                                               /*!< EMAC_T::INTEN: LPIEN Position          */
+#define EMAC_INTEN_LPIEN_Msk             (0x1ul << EMAC_INTEN_LPIEN_Pos)                   /*!< EMAC_T::INTEN: LPIEN Mask              */
+
+#define EMAC_INTEN_RXGDIEN_Pos           (4)                                               /*!< EMAC_T::INTEN: RXGDIEN Position        */
+#define EMAC_INTEN_RXGDIEN_Msk           (0x1ul << EMAC_INTEN_RXGDIEN_Pos)                 /*!< EMAC_T::INTEN: RXGDIEN Mask            */
+
+#define EMAC_INTEN_ALIEIEN_Pos           (5)                                               /*!< EMAC_T::INTEN: ALIEIEN Position        */
+#define EMAC_INTEN_ALIEIEN_Msk           (0x1ul << EMAC_INTEN_ALIEIEN_Pos)                 /*!< EMAC_T::INTEN: ALIEIEN Mask            */
+
+#define EMAC_INTEN_RPIEN_Pos             (6)                                               /*!< EMAC_T::INTEN: RPIEN Position          */
+#define EMAC_INTEN_RPIEN_Msk             (0x1ul << EMAC_INTEN_RPIEN_Pos)                   /*!< EMAC_T::INTEN: RPIEN Mask              */
+
+#define EMAC_INTEN_MPCOVIEN_Pos          (7)                                               /*!< EMAC_T::INTEN: MPCOVIEN Position       */
+#define EMAC_INTEN_MPCOVIEN_Msk          (0x1ul << EMAC_INTEN_MPCOVIEN_Pos)                /*!< EMAC_T::INTEN: MPCOVIEN Mask           */
+
+#define EMAC_INTEN_MFLEIEN_Pos           (8)                                               /*!< EMAC_T::INTEN: MFLEIEN Position        */
+#define EMAC_INTEN_MFLEIEN_Msk           (0x1ul << EMAC_INTEN_MFLEIEN_Pos)                 /*!< EMAC_T::INTEN: MFLEIEN Mask            */
+
+#define EMAC_INTEN_DENIEN_Pos            (9)                                               /*!< EMAC_T::INTEN: DENIEN Position         */
+#define EMAC_INTEN_DENIEN_Msk            (0x1ul << EMAC_INTEN_DENIEN_Pos)                  /*!< EMAC_T::INTEN: DENIEN Mask             */
+
+#define EMAC_INTEN_RDUIEN_Pos            (10)                                              /*!< EMAC_T::INTEN: RDUIEN Position         */
+#define EMAC_INTEN_RDUIEN_Msk            (0x1ul << EMAC_INTEN_RDUIEN_Pos)                  /*!< EMAC_T::INTEN: RDUIEN Mask             */
+
+#define EMAC_INTEN_RXBEIEN_Pos           (11)                                              /*!< EMAC_T::INTEN: RXBEIEN Position        */
+#define EMAC_INTEN_RXBEIEN_Msk           (0x1ul << EMAC_INTEN_RXBEIEN_Pos)                 /*!< EMAC_T::INTEN: RXBEIEN Mask            */
+
+#define EMAC_INTEN_CFRIEN_Pos            (14)                                              /*!< EMAC_T::INTEN: CFRIEN Position         */
+#define EMAC_INTEN_CFRIEN_Msk            (0x1ul << EMAC_INTEN_CFRIEN_Pos)                  /*!< EMAC_T::INTEN: CFRIEN Mask             */
+
+#define EMAC_INTEN_WOLIEN_Pos            (15)                                              /*!< EMAC_T::INTEN: WOLIEN Position         */
+#define EMAC_INTEN_WOLIEN_Msk            (0x1ul << EMAC_INTEN_WOLIEN_Pos)                  /*!< EMAC_T::INTEN: WOLIEN Mask             */
+
+#define EMAC_INTEN_TXIEN_Pos             (16)                                              /*!< EMAC_T::INTEN: TXIEN Position          */
+#define EMAC_INTEN_TXIEN_Msk             (0x1ul << EMAC_INTEN_TXIEN_Pos)                   /*!< EMAC_T::INTEN: TXIEN Mask              */
+
+#define EMAC_INTEN_TXUDIEN_Pos           (17)                                              /*!< EMAC_T::INTEN: TXUDIEN Position        */
+#define EMAC_INTEN_TXUDIEN_Msk           (0x1ul << EMAC_INTEN_TXUDIEN_Pos)                 /*!< EMAC_T::INTEN: TXUDIEN Mask            */
+
+#define EMAC_INTEN_TXCPIEN_Pos           (18)                                              /*!< EMAC_T::INTEN: TXCPIEN Position        */
+#define EMAC_INTEN_TXCPIEN_Msk           (0x1ul << EMAC_INTEN_TXCPIEN_Pos)                 /*!< EMAC_T::INTEN: TXCPIEN Mask            */
+
+#define EMAC_INTEN_EXDEFIEN_Pos          (19)                                              /*!< EMAC_T::INTEN: EXDEFIEN Position       */
+#define EMAC_INTEN_EXDEFIEN_Msk          (0x1ul << EMAC_INTEN_EXDEFIEN_Pos)                /*!< EMAC_T::INTEN: EXDEFIEN Mask           */
+
+#define EMAC_INTEN_NCSIEN_Pos            (20)                                              /*!< EMAC_T::INTEN: NCSIEN Position         */
+#define EMAC_INTEN_NCSIEN_Msk            (0x1ul << EMAC_INTEN_NCSIEN_Pos)                  /*!< EMAC_T::INTEN: NCSIEN Mask             */
+
+#define EMAC_INTEN_TXABTIEN_Pos          (21)                                              /*!< EMAC_T::INTEN: TXABTIEN Position       */
+#define EMAC_INTEN_TXABTIEN_Msk          (0x1ul << EMAC_INTEN_TXABTIEN_Pos)                /*!< EMAC_T::INTEN: TXABTIEN Mask           */
+
+#define EMAC_INTEN_LCIEN_Pos             (22)                                              /*!< EMAC_T::INTEN: LCIEN Position          */
+#define EMAC_INTEN_LCIEN_Msk             (0x1ul << EMAC_INTEN_LCIEN_Pos)                   /*!< EMAC_T::INTEN: LCIEN Mask              */
+
+#define EMAC_INTEN_TDUIEN_Pos            (23)                                              /*!< EMAC_T::INTEN: TDUIEN Position         */
+#define EMAC_INTEN_TDUIEN_Msk            (0x1ul << EMAC_INTEN_TDUIEN_Pos)                  /*!< EMAC_T::INTEN: TDUIEN Mask             */
+
+#define EMAC_INTEN_TXBEIEN_Pos           (24)                                              /*!< EMAC_T::INTEN: TXBEIEN Position        */
+#define EMAC_INTEN_TXBEIEN_Msk           (0x1ul << EMAC_INTEN_TXBEIEN_Pos)                 /*!< EMAC_T::INTEN: TXBEIEN Mask            */
+
+#define EMAC_INTEN_TSALMIEN_Pos          (28)                                              /*!< EMAC_T::INTEN: TSALMIEN Position       */
+#define EMAC_INTEN_TSALMIEN_Msk          (0x1ul << EMAC_INTEN_TSALMIEN_Pos)                /*!< EMAC_T::INTEN: TSALMIEN Mask           */
+
+#define EMAC_INTSTS_RXIF_Pos             (0)                                               /*!< EMAC_T::INTSTS: RXIF Position          */
+#define EMAC_INTSTS_RXIF_Msk             (0x1ul << EMAC_INTSTS_RXIF_Pos)                   /*!< EMAC_T::INTSTS: RXIF Mask              */
+
+#define EMAC_INTSTS_CRCEIF_Pos           (1)                                               /*!< EMAC_T::INTSTS: CRCEIF Position        */
+#define EMAC_INTSTS_CRCEIF_Msk           (0x1ul << EMAC_INTSTS_CRCEIF_Pos)                 /*!< EMAC_T::INTSTS: CRCEIF Mask            */
+
+#define EMAC_INTSTS_RXOVIF_Pos           (2)                                               /*!< EMAC_T::INTSTS: RXOVIF Position        */
+#define EMAC_INTSTS_RXOVIF_Msk           (0x1ul << EMAC_INTSTS_RXOVIF_Pos)                 /*!< EMAC_T::INTSTS: RXOVIF Mask            */
+
+#define EMAC_INTSTS_LPIF_Pos             (3)                                               /*!< EMAC_T::INTSTS: LPIF Position          */
+#define EMAC_INTSTS_LPIF_Msk             (0x1ul << EMAC_INTSTS_LPIF_Pos)                   /*!< EMAC_T::INTSTS: LPIF Mask              */
+
+#define EMAC_INTSTS_RXGDIF_Pos           (4)                                               /*!< EMAC_T::INTSTS: RXGDIF Position        */
+#define EMAC_INTSTS_RXGDIF_Msk           (0x1ul << EMAC_INTSTS_RXGDIF_Pos)                 /*!< EMAC_T::INTSTS: RXGDIF Mask            */
+
+#define EMAC_INTSTS_ALIEIF_Pos           (5)                                               /*!< EMAC_T::INTSTS: ALIEIF Position        */
+#define EMAC_INTSTS_ALIEIF_Msk           (0x1ul << EMAC_INTSTS_ALIEIF_Pos)                 /*!< EMAC_T::INTSTS: ALIEIF Mask            */
+
+#define EMAC_INTSTS_RPIF_Pos             (6)                                               /*!< EMAC_T::INTSTS: RPIF Position          */
+#define EMAC_INTSTS_RPIF_Msk             (0x1ul << EMAC_INTSTS_RPIF_Pos)                   /*!< EMAC_T::INTSTS: RPIF Mask              */
+
+#define EMAC_INTSTS_MPCOVIF_Pos          (7)                                               /*!< EMAC_T::INTSTS: MPCOVIF Position       */
+#define EMAC_INTSTS_MPCOVIF_Msk          (0x1ul << EMAC_INTSTS_MPCOVIF_Pos)                /*!< EMAC_T::INTSTS: MPCOVIF Mask           */
+
+#define EMAC_INTSTS_MFLEIF_Pos           (8)                                               /*!< EMAC_T::INTSTS: MFLEIF Position        */
+#define EMAC_INTSTS_MFLEIF_Msk           (0x1ul << EMAC_INTSTS_MFLEIF_Pos)                 /*!< EMAC_T::INTSTS: MFLEIF Mask            */
+
+#define EMAC_INTSTS_DENIF_Pos            (9)                                               /*!< EMAC_T::INTSTS: DENIF Position         */
+#define EMAC_INTSTS_DENIF_Msk            (0x1ul << EMAC_INTSTS_DENIF_Pos)                  /*!< EMAC_T::INTSTS: DENIF Mask             */
+
+#define EMAC_INTSTS_RDUIF_Pos            (10)                                              /*!< EMAC_T::INTSTS: RDUIF Position         */
+#define EMAC_INTSTS_RDUIF_Msk            (0x1ul << EMAC_INTSTS_RDUIF_Pos)                  /*!< EMAC_T::INTSTS: RDUIF Mask             */
+
+#define EMAC_INTSTS_RXBEIF_Pos           (11)                                              /*!< EMAC_T::INTSTS: RXBEIF Position        */
+#define EMAC_INTSTS_RXBEIF_Msk           (0x1ul << EMAC_INTSTS_RXBEIF_Pos)                 /*!< EMAC_T::INTSTS: RXBEIF Mask            */
+
+#define EMAC_INTSTS_CFRIF_Pos            (14)                                              /*!< EMAC_T::INTSTS: CFRIF Position         */
+#define EMAC_INTSTS_CFRIF_Msk            (0x1ul << EMAC_INTSTS_CFRIF_Pos)                  /*!< EMAC_T::INTSTS: CFRIF Mask             */
+
+#define EMAC_INTSTS_WOLIF_Pos            (15)                                              /*!< EMAC_T::INTSTS: WOLIF Position         */
+#define EMAC_INTSTS_WOLIF_Msk            (0x1ul << EMAC_INTSTS_WOLIF_Pos)                  /*!< EMAC_T::INTSTS: WOLIF Mask             */
+
+#define EMAC_INTSTS_TXIF_Pos             (16)                                              /*!< EMAC_T::INTSTS: TXIF Position          */
+#define EMAC_INTSTS_TXIF_Msk             (0x1ul << EMAC_INTSTS_TXIF_Pos)                   /*!< EMAC_T::INTSTS: TXIF Mask              */
+
+#define EMAC_INTSTS_TXUDIF_Pos           (17)                                              /*!< EMAC_T::INTSTS: TXUDIF Position        */
+#define EMAC_INTSTS_TXUDIF_Msk           (0x1ul << EMAC_INTSTS_TXUDIF_Pos)                 /*!< EMAC_T::INTSTS: TXUDIF Mask            */
+
+#define EMAC_INTSTS_TXCPIF_Pos           (18)                                              /*!< EMAC_T::INTSTS: TXCPIF Position        */
+#define EMAC_INTSTS_TXCPIF_Msk           (0x1ul << EMAC_INTSTS_TXCPIF_Pos)                 /*!< EMAC_T::INTSTS: TXCPIF Mask            */
+
+#define EMAC_INTSTS_EXDEFIF_Pos          (19)                                              /*!< EMAC_T::INTSTS: EXDEFIF Position       */
+#define EMAC_INTSTS_EXDEFIF_Msk          (0x1ul << EMAC_INTSTS_EXDEFIF_Pos)                /*!< EMAC_T::INTSTS: EXDEFIF Mask           */
+
+#define EMAC_INTSTS_NCSIF_Pos            (20)                                              /*!< EMAC_T::INTSTS: NCSIF Position         */
+#define EMAC_INTSTS_NCSIF_Msk            (0x1ul << EMAC_INTSTS_NCSIF_Pos)                  /*!< EMAC_T::INTSTS: NCSIF Mask             */
+
+#define EMAC_INTSTS_TXABTIF_Pos          (21)                                              /*!< EMAC_T::INTSTS: TXABTIF Position       */
+#define EMAC_INTSTS_TXABTIF_Msk          (0x1ul << EMAC_INTSTS_TXABTIF_Pos)                /*!< EMAC_T::INTSTS: TXABTIF Mask           */
+
+#define EMAC_INTSTS_LCIF_Pos             (22)                                              /*!< EMAC_T::INTSTS: LCIF Position          */
+#define EMAC_INTSTS_LCIF_Msk             (0x1ul << EMAC_INTSTS_LCIF_Pos)                   /*!< EMAC_T::INTSTS: LCIF Mask              */
+
+#define EMAC_INTSTS_TDUIF_Pos            (23)                                              /*!< EMAC_T::INTSTS: TDUIF Position         */
+#define EMAC_INTSTS_TDUIF_Msk            (0x1ul << EMAC_INTSTS_TDUIF_Pos)                  /*!< EMAC_T::INTSTS: TDUIF Mask             */
+
+#define EMAC_INTSTS_TXBEIF_Pos           (24)                                              /*!< EMAC_T::INTSTS: TXBEIF Position        */
+#define EMAC_INTSTS_TXBEIF_Msk           (0x1ul << EMAC_INTSTS_TXBEIF_Pos)                 /*!< EMAC_T::INTSTS: TXBEIF Mask            */
+
+#define EMAC_INTSTS_TSALMIF_Pos          (28)                                              /*!< EMAC_T::INTSTS: TSALMIF Position       */
+#define EMAC_INTSTS_TSALMIF_Msk          (0x1ul << EMAC_INTSTS_TSALMIF_Pos)                /*!< EMAC_T::INTSTS: TSALMIF Mask           */
+
+#define EMAC_GENSTS_CFR_Pos              (0)                                               /*!< EMAC_T::GENSTS: CFR Position           */
+#define EMAC_GENSTS_CFR_Msk              (0x1ul << EMAC_GENSTS_CFR_Pos)                    /*!< EMAC_T::GENSTS: CFR Mask               */
+
+#define EMAC_GENSTS_RXHALT_Pos           (1)                                               /*!< EMAC_T::GENSTS: RXHALT Position        */
+#define EMAC_GENSTS_RXHALT_Msk           (0x1ul << EMAC_GENSTS_RXHALT_Pos)                 /*!< EMAC_T::GENSTS: RXHALT Mask            */
+
+#define EMAC_GENSTS_RXFFULL_Pos          (2)                                               /*!< EMAC_T::GENSTS: RXFFULL Position       */
+#define EMAC_GENSTS_RXFFULL_Msk          (0x1ul << EMAC_GENSTS_RXFFULL_Pos)                /*!< EMAC_T::GENSTS: RXFFULL Mask           */
+
+#define EMAC_GENSTS_COLCNT_Pos           (4)                                               /*!< EMAC_T::GENSTS: COLCNT Position        */
+#define EMAC_GENSTS_COLCNT_Msk           (0xful << EMAC_GENSTS_COLCNT_Pos)                 /*!< EMAC_T::GENSTS: COLCNT Mask            */
+
+#define EMAC_GENSTS_DEF_Pos              (8)                                               /*!< EMAC_T::GENSTS: DEF Position           */
+#define EMAC_GENSTS_DEF_Msk              (0x1ul << EMAC_GENSTS_DEF_Pos)                    /*!< EMAC_T::GENSTS: DEF Mask               */
+
+#define EMAC_GENSTS_TXPAUSED_Pos         (9)                                               /*!< EMAC_T::GENSTS: TXPAUSED Position      */
+#define EMAC_GENSTS_TXPAUSED_Msk         (0x1ul << EMAC_GENSTS_TXPAUSED_Pos)               /*!< EMAC_T::GENSTS: TXPAUSED Mask          */
+
+#define EMAC_GENSTS_SQE_Pos              (10)                                              /*!< EMAC_T::GENSTS: SQE Position           */
+#define EMAC_GENSTS_SQE_Msk              (0x1ul << EMAC_GENSTS_SQE_Pos)                    /*!< EMAC_T::GENSTS: SQE Mask               */
+
+#define EMAC_GENSTS_TXHALT_Pos           (11)                                              /*!< EMAC_T::GENSTS: TXHALT Position        */
+#define EMAC_GENSTS_TXHALT_Msk           (0x1ul << EMAC_GENSTS_TXHALT_Pos)                 /*!< EMAC_T::GENSTS: TXHALT Mask            */
+
+#define EMAC_GENSTS_RPSTS_Pos            (12)                                              /*!< EMAC_T::GENSTS: RPSTS Position         */
+#define EMAC_GENSTS_RPSTS_Msk            (0x1ul << EMAC_GENSTS_RPSTS_Pos)                  /*!< EMAC_T::GENSTS: RPSTS Mask             */
+
+#define EMAC_MPCNT_MPCNT_Pos             (0)                                               /*!< EMAC_T::MPCNT: MPCNT Position          */
+#define EMAC_MPCNT_MPCNT_Msk             (0xfffful << EMAC_MPCNT_MPCNT_Pos)                /*!< EMAC_T::MPCNT: MPCNT Mask              */
+
+#define EMAC_RPCNT_RPCNT_Pos             (0)                                               /*!< EMAC_T::RPCNT: RPCNT Position          */
+#define EMAC_RPCNT_RPCNT_Msk             (0xfffful << EMAC_RPCNT_RPCNT_Pos)                /*!< EMAC_T::RPCNT: RPCNT Mask              */
+
+#define EMAC_FRSTS_RXFLT_Pos             (0)                                               /*!< EMAC_T::FRSTS: RXFLT Position          */
+#define EMAC_FRSTS_RXFLT_Msk             (0xfffful << EMAC_FRSTS_RXFLT_Pos)                /*!< EMAC_T::FRSTS: RXFLT Mask              */
+
+#define EMAC_CTXDSA_CTXDSA_Pos           (0)                                               /*!< EMAC_T::CTXDSA: CTXDSA Position        */
+#define EMAC_CTXDSA_CTXDSA_Msk           (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)          /*!< EMAC_T::CTXDSA: CTXDSA Mask            */
+
+#define EMAC_CTXBSA_CTXBSA_Pos           (0)                                               /*!< EMAC_T::CTXBSA: CTXBSA Position        */
+#define EMAC_CTXBSA_CTXBSA_Msk           (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)          /*!< EMAC_T::CTXBSA: CTXBSA Mask            */
+
+#define EMAC_CRXDSA_CRXDSA_Pos           (0)                                               /*!< EMAC_T::CRXDSA: CRXDSA Position        */
+#define EMAC_CRXDSA_CRXDSA_Msk           (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)          /*!< EMAC_T::CRXDSA: CRXDSA Mask            */
+
+#define EMAC_CRXBSA_CRXBSA_Pos           (0)                                               /*!< EMAC_T::CRXBSA: CRXBSA Position        */
+#define EMAC_CRXBSA_CRXBSA_Msk           (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)          /*!< EMAC_T::CRXBSA: CRXBSA Mask            */
+
+#define EMAC_TSCTL_TSEN_Pos              (0)                                               /*!< EMAC_T::TSCTL: TSEN Position           */
+#define EMAC_TSCTL_TSEN_Msk              (0x1ul << EMAC_TSCTL_TSEN_Pos)                    /*!< EMAC_T::TSCTL: TSEN Mask               */
+
+#define EMAC_TSCTL_TSIEN_Pos             (1)                                               /*!< EMAC_T::TSCTL: TSIEN Position          */
+#define EMAC_TSCTL_TSIEN_Msk             (0x1ul << EMAC_TSCTL_TSIEN_Pos)                   /*!< EMAC_T::TSCTL: TSIEN Mask              */
+
+#define EMAC_TSCTL_TSMODE_Pos            (2)                                               /*!< EMAC_T::TSCTL: TSMODE Position         */
+#define EMAC_TSCTL_TSMODE_Msk            (0x1ul << EMAC_TSCTL_TSMODE_Pos)                  /*!< EMAC_T::TSCTL: TSMODE Mask             */
+
+#define EMAC_TSCTL_TSUPDATE_Pos          (3)                                               /*!< EMAC_T::TSCTL: TSUPDATE Position       */
+#define EMAC_TSCTL_TSUPDATE_Msk          (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)                /*!< EMAC_T::TSCTL: TSUPDATE Mask           */
+
+#define EMAC_TSCTL_TSALMEN_Pos           (5)                                               /*!< EMAC_T::TSCTL: TSALMEN Position        */
+#define EMAC_TSCTL_TSALMEN_Msk           (0x1ul << EMAC_TSCTL_TSALMEN_Pos)                 /*!< EMAC_T::TSCTL: TSALMEN Mask            */
+
+#define EMAC_TSSEC_SEC_Pos               (0)                                               /*!< EMAC_T::TSSEC: SEC Position            */
+#define EMAC_TSSEC_SEC_Msk               (0xfffffffful << EMAC_TSSEC_SEC_Pos)              /*!< EMAC_T::TSSEC: SEC Mask                */
+
+#define EMAC_TSSUBSEC_SUBSEC_Pos         (0)                                               /*!< EMAC_T::TSSUBSEC: SUBSEC Position      */
+#define EMAC_TSSUBSEC_SUBSEC_Msk         (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)        /*!< EMAC_T::TSSUBSEC: SUBSEC Mask          */
+
+#define EMAC_TSINC_CNTINC_Pos            (0)                                               /*!< EMAC_T::TSINC: CNTINC Position         */
+#define EMAC_TSINC_CNTINC_Msk            (0xfful << EMAC_TSINC_CNTINC_Pos)                 /*!< EMAC_T::TSINC: CNTINC Mask             */
+
+#define EMAC_TSADDEND_ADDEND_Pos         (0)                                               /*!< EMAC_T::TSADDEND: ADDEND Position      */
+#define EMAC_TSADDEND_ADDEND_Msk         (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)        /*!< EMAC_T::TSADDEND: ADDEND Mask          */
+
+#define EMAC_UPDSEC_SEC_Pos              (0)                                               /*!< EMAC_T::UPDSEC: SEC Position           */
+#define EMAC_UPDSEC_SEC_Msk              (0xfffffffful << EMAC_UPDSEC_SEC_Pos)             /*!< EMAC_T::UPDSEC: SEC Mask               */
+
+#define EMAC_UPDSUBSEC_SUBSEC_Pos        (0)                                               /*!< EMAC_T::UPDSUBSEC: SUBSEC Position     */
+#define EMAC_UPDSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos)       /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask         */
+
+#define EMAC_ALMSEC_SEC_Pos              (0)                                               /*!< EMAC_T::ALMSEC: SEC Position           */
+#define EMAC_ALMSEC_SEC_Msk              (0xfffffffful << EMAC_ALMSEC_SEC_Pos)             /*!< EMAC_T::ALMSEC: SEC Mask               */
+
+#define EMAC_ALMSUBSEC_SUBSEC_Pos        (0)                                               /*!< EMAC_T::ALMSUBSEC: SUBSEC Position     */
+#define EMAC_ALMSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos)       /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask         */
+
+/**@}*/ /* EMAC_CONST */
+/**@}*/ /* end of EMAC register group */
+
+
+
+/*---------------------- Smart Card Host Interface Controller -------------------------*/
+/**
+    @addtogroup SC Smart Card Host Interface Controller(SC)
+    Memory Mapped Structure for SC Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var SC_T::DAT
+     * Offset: 0x00  SC Receive/Transmit Holding Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |Receive/Transmit Holding Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing data to DAT, the SC will send out an 8-bit data.
+     * |        |          |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
+     * |        |          |Read Operation:
+     * |        |          |By reading DAT, the SC will return an 8-bit received data.
+     * @var SC_T::CTL
+     * Offset: 0x04  SC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SCEN      |SC Controller Enable Bit
+     * |        |          |Set this bit to 1 to enable SC operation. If this bit is cleared,
+     * |        |          |0 = SC will force all transition to IDLE state.
+     * |        |          |1 = SC controller is enabled and all function can work correctly.
+     * |        |          |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
+     * |[1]     |RXOFF     |RX Transition Disable Control Bit
+     * |        |          |This bit is used for disable Rx transition function.
+     * |        |          |0 = The receiver Enabled.
+     * |        |          |1 = The receiver Disabled.
+     * |        |          |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+     * |[2]     |TXOFF     |TX Transition Disable Control Bit
+     * |        |          |This bit is used for disable Tx transition function.
+     * |        |          |0 = The transceiver Enabled.
+     * |        |          |1 = The transceiver Disabled.
+     * |[3]     |AUTOCEN   |Auto Convention Enable Bit
+     * |        |          |This bit is used for enable auto convention function.
+     * |        |          |0 = Auto-convention Disabled.
+     * |        |          |1 = Auto-convention Enabled.
+     * |        |          |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR)
+     * |        |          |state and the first data must be 0x3B or 0x3F.
+     * |        |          |After hardware received first data and stored it at buffer, hardware will decided the convention and
+     * |        |          |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F.
+     * |        |          |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00
+     * |        |          |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
+     * |        |          |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an
+     * |        |          |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
+     * |[5:4]   |CONSEL    |Convention Selection
+     * |        |          |00 = Direct convention.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = Inverse convention.
+     * |        |          |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+     * |[7:6]   |RXTRGLV   |Rx Buffer Trigger Level
+     * |        |          |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
+     * |        |          |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
+     * |        |          |00 = Rx Buffer Trigger Level with 01 bytes.
+     * |        |          |01 = Rx Buffer Trigger Level with 02 bytes.
+     * |        |          |10 = Rx Buffer Trigger Level with 03 bytes.
+     * |        |          |11 = Reserved.
+     * |[12:8]  |BGT       |Block Guard Time (BGT)
+     * |        |          |Block guard time means the minimum interval between the leading edges of two consecutive characters
+     * |        |          |between different transfer directions
+     * |        |          |This field indicates the counter for the bit length of block guard time
+     * |        |          |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this
+     * |        |          |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
+     * |        |          |Note: The real block guard time is BGT + 1.
+     * |[14:13] |TMRSEL    |Timer Channel Selection
+     * |        |          |00 = All internal timer function Disabled.
+     * |        |          |11 = Internal 24 bit timer and two 8 bit timers Enabled
+     * |        |          |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
+     * |        |          |Other configurations are reserved
+     * |[15]    |NSB       |Stop Bit Length
+     * |        |          |This field indicates the length of stop bit.
+     * |        |          |0 = The stop bit length is 2 ETU.
+     * |        |          |1= The stop bit length is 1 ETU.
+     * |        |          |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
+     * |        |          |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
+     * |[18:16] |RXRTY     |RX Error Retry Count Number
+     * |        |          |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
+     * |        |          |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
+     * |        |          |Note2: This field cannot be changed when RXRTYEN enabled
+     * |        |          |The change flow is to disable RXRTYEN first and then fill in new retry value.
+     * |[19]    |RXRTYEN   |RX Error Retry Enable Bit
+     * |        |          |This bit enables receiver retry function when parity error has occurred.
+     * |        |          |0 = RX error retry function Disabled.
+     * |        |          |1 = RX error retry function Enabled.
+     * |        |          |Note: User must fill in the RXRTY value before enabling this bit.
+     * |[22:20] |TXRTY     |TX Error Retry Count Number
+     * |        |          |This field indicates the maximum number of transmitter retries that are allowed when parity
+     * |        |          |error has occurred.
+     * |        |          |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
+     * |        |          |Note2: This field cannot be changed when TXRTYEN enabled
+     * |        |          |The change flow is to disable TXRTYEN first and then fill in new retry value.
+     * |[23]    |TXRTYEN   |TX Error Retry Enable Bit
+     * |        |          |This bit enables transmitter retry function when parity error has occurred.
+     * |        |          |0 = TX error retry function Disabled.
+     * |        |          |1 = TX error retry function Enabled.
+     * |[25:24] |CDDBSEL   |Card Detect De-bounce Selection
+     * |        |          |This field indicates the card detect de-bounce selection.
+     * |        |          |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce
+     * |        |          |sample card removal once per 128 SC module clocks.
+     * |        |          |Other configurations are reserved.
+     * |[26]    |CDLV      |Card Detect Level Selection
+     * |        |          |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
+     * |        |          |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
+     * |        |          |Note: User must select card detect level before Smart Card controller enabled.
+     * |[30]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
+     * |        |          |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::ALTCTL
+     * Offset: 0x08  SC Alternate Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXRST     |TX Software Reset
+     * |        |          |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the TX internal state machine and pointers.
+     * |        |          |Note: This bit will be auto cleared after reset is complete.
+     * |[1]     |RXRST     |Rx Software Reset
+     * |        |          |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the Rx internal state machine and pointers.
+     * |        |          |Note: This bit will be auto cleared after reset is complete.
+     * |[2]     |DACTEN    |Deactivation Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by deactivation sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Deactivation sequence generator Enabled.
+     * |        |          |Note1: When the deactivation sequence completed, this bit will be cleared automatically and
+     * |        |          |the INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[3]     |ACTEN     |Activation Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by activation sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Activation sequence generator Enabled.
+     * |        |          |Note1: When the activation sequence completed, this bit will be cleared automatically and the
+     * |        |          |INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |        |          |Note4: During the activation sequence, RX is disabled automatically and can not receive data
+     * |        |          |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
+     * |[4]     |WARSTEN   |Warm Reset Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by warm reset sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Warm reset sequence generator Enabled.
+     * |        |          |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the
+     * |        |          |INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |        |          |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
+     * |        |          |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform
+     * |        |          |warm reset sequence.
+     * |[5]     |CNTEN0    |Internal Timer0 Start Enable Bit
+     * |        |          |This bit enables Timer 0 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will
+     * |        |          |be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[6]     |CNTEN1    |Internal Timer1 Start Enable Bit
+     * |        |          |This bit enables Timer 1 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
+     * |        |          |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will
+     * |        |          |be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[7]     |CNTEN2    |Internal Timer2 Start Enable Bit
+     * |        |          |This bit enables Timer 2 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
+     * |        |          |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will
+     * |        |          |be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[9:8]   |INITSEL   |Initial Timing Selection
+     * |        |          |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
+     * |        |          |The unit of initial timing is SC module clock.
+     * |        |          |Activation: refer to SC Activation Sequence in Figure 7.17-54.
+     * |        |          |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5.
+     * |        |          |Deactivation: refer to Deactivation Sequence in Figure 7.17-56.
+     * |        |          |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation
+     * |        |          |at most 128 SC module clock cycles.
+     * |[11]    |ADACEN    |Auto Deactivation When Card Removal
+     * |        |          |This bit is used for enable hardware auto deactivation when smart card is removed.
+     * |        |          |0 = Auto deactivation Disabled.
+     * |        |          |1 = Auto deactivation Enabled.
+     * |        |          |Note: When the card is removed, hardware will stop any process and then do deactivation sequence
+     * |        |          |if this bit is set
+     * |        |          |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
+     * |[12]    |RXBGTEN   |Receiver Block Guard Time Function Enable Bit
+     * |        |          |This bit enables the receiver block guard time function.
+     * |        |          |0 = Receiver block guard time function Disabled.
+     * |        |          |1 = Receiver block guard time function Enabled.
+     * |[13]    |ACTSTS0   |Internal Timer0 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer0.
+     * |        |          |0 = Timer0 is not active.
+     * |        |          |1 = Timer0 is active.
+     * |        |          |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
+     * |[14]    |ACTSTS1   |Internal Timer1 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer1.
+     * |        |          |0 = Timer1 is not active.
+     * |        |          |1 = Timer1 is active.
+     * |        |          |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
+     * |[15]    |ACTSTS2   |Internal Timer2 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer2.
+     * |        |          |0 = Timer2 is not active.
+     * |        |          |1 = Timer2 is active.
+     * |        |          |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::EGT
+     * Offset: 0x0C  SC Extra Guard Time Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |EGT       |Extra Guard Time
+     * |        |          |This field indicates the extra guard time value.
+     * |        |          |Note: The extra guard time unit is ETU base.
+     * @var SC_T::RXTOUT
+     * Offset: 0x10  SC Receive Buffer Time-out Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |RFTM      |SC Receiver FIFO Time-out Counter
+     * |        |          |The time-out down counter resets and starts counting whenever the RX buffer received a new data
+     * |        |          |Once the counter decrease to 1 and no new data is received or CPU does not read data by
+     * |        |          |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will
+     * |        |          |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled.
+     * |        |          |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
+     * |        |          |Note2: Filling in all 0 to this field indicates to disable this function.
+     * @var SC_T::ETUCTL
+     * Offset: 0x14  SC Element Time Unit Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |ETURDIV   |ETU Rate Divider
+     * |        |          |The field is used for ETU clock rate divider.
+     * |        |          |The real ETU is ETURDIV + 1.
+     * |        |          |Note: User can configure this field, but this field must be greater than 0x04.
+     * @var SC_T::INTEN
+     * Offset: 0x18  SC Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIEN    |Receive Data Reach Interrupt Enable Bit
+     * |        |          |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
+     * |        |          |0 = Receive data reach trigger level interrupt Disabled.
+     * |        |          |1 = Receive data reach trigger level interrupt Enabled.
+     * |[1]     |TBEIEN    |Transmit Buffer Empty Interrupt Enable Bit
+     * |        |          |This field is used to enable transmit buffer empty interrupt.
+     * |        |          |0 = Transmit buffer empty interrupt Disabled.
+     * |        |          |1 = Transmit buffer empty interrupt Enabled.
+     * |[2]     |TERRIEN   |Transfer Error Interrupt Enable Bit
+     * |        |          |This field is used to enable transfer error interrupt
+     * |        |          |The transfer error states is at SCn_STATUS register which includes receiver break error
+     * |        |          |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive
+     * |        |          |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
+     * |        |          |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error
+     * |        |          |TXOVERR (SCn_STATUS[30]).
+     * |        |          |0 = Transfer error interrupt Disabled.
+     * |        |          |1 = Transfer error interrupt Enabled.
+     * |[3]     |TMR0IEN   |Timer0 Interrupt Enable Bit
+     * |        |          |This field is used to enable Timer0 interrupt function.
+     * |        |          |0 = Timer0 interrupt Disabled.
+     * |        |          |1 = Timer0 interrupt Enabled.
+     * |[4]     |TMR1IEN   |Timer1 Interrupt Enable Bit
+     * |        |          |This field is used to enable the Timer1 interrupt function.
+     * |        |          |0 = Timer1 interrupt Disabled.
+     * |        |          |1 = Timer1 interrupt Enabled.
+     * |[5]     |TMR2IEN   |Timer2 Interrupt Enable Bit
+     * |        |          |This field is used to enable Timer2 interrupt function.
+     * |        |          |0 = Timer2 interrupt Disabled.
+     * |        |          |1 = Timer2 interrupt Enabled.
+     * |[6]     |BGTIEN    |Block Guard Time Interrupt Enable Bit
+     * |        |          |This field is used to enable block guard time interrupt in receive direction.
+     * |        |          |0 = Block guard time interrupt Disabled.
+     * |        |          |1 = Block guard time interrupt Enabled.
+     * |        |          |Note: This bit is valid only for receive direction block guard time.
+     * |[7]     |CDIEN     |Card Detect Interrupt Enable Bit
+     * |        |          |This field is used to enable card detect interrupt
+     * |        |          |The card detect status is CDPINSTS (SCn_STATUS[13]).
+     * |        |          |0 = Card detect interrupt Disabled.
+     * |        |          |1 = Card detect interrupt Enabled.
+     * |[8]     |INITIEN   |Initial End Interrupt Enable Bit
+     * |        |          |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation
+     * |        |          |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
+     * |        |          |0 = Initial end interrupt Disabled.
+     * |        |          |1 = Initial end interrupt Enabled.
+     * |[9]     |RXTOIEN   |Receiver Buffer Time-out Interrupt Enable Bit
+     * |        |          |This field is used to enable receiver buffer time-out interrupt.
+     * |        |          |0 = Receiver buffer time-out interrupt Disabled.
+     * |        |          |1 = Receiver buffer time-out interrupt Enabled.
+     * |[10]    |ACERRIEN  |Auto Convention Error Interrupt Enable Bit
+     * |        |          |This field is used to enable auto-convention error interrupt.
+     * |        |          |0 = Auto-convention error interrupt Disabled.
+     * |        |          |1 = Auto-convention error interrupt Enabled.
+     * @var SC_T::INTSTS
+     * Offset: 0x1C  SC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIF     |Receive Data Reach Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
+     * |        |          |0 = Number of receive buffer is less than RXTRGLV setting.
+     * |        |          |1 = Number of receive buffer data equals the RXTRGLV setting.
+     * |        |          |Note: This bit is read only
+     * |        |          |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV,
+     * |        |          |this bit will be cleared automatically.
+     * |[1]     |TBEIF     |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for transmit buffer empty interrupt status flag.
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty.
+     * |        |          |Note: This bit is read only
+     * |        |          |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit
+     * |        |          |will be cleared automatically.
+     * |[2]     |TERRIF    |Transfer Error Interrupt Status Flag
+     * |        |          |This field is used for transfer error interrupt status flag
+     * |        |          |The transfer error states is at SCn_STATUS register which includes receiver break error
+     * |        |          |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive
+     * |        |          |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]),
+     * |        |          |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error
+     * |        |          |TXOVERR (SCn_STATUS[30]).
+     * |        |          |0 = Transfer error interrupt did not occur.
+     * |        |          |1 = Transfer error interrupt occurred.
+     * |        |          |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[3]     |TMR0IF    |Timer0 Interrupt Status Flag
+     * |        |          |This field is used for Timer0 interrupt status flag.
+     * |        |          |0 = Timer0 interrupt did not occur.
+     * |        |          |1 = Timer0 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[4]     |TMR1IF    |Timer1 Interrupt Status Flag
+     * |        |          |This field is used for Timer1 interrupt status flag.
+     * |        |          |0 = Timer1 interrupt did not occur.
+     * |        |          |1 = Timer1 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[5]     |TMR2IF    |Timer2 Interrupt Status Flag
+     * |        |          |This field is used for Timer2 interrupt status flag.
+     * |        |          |0 = Timer2 interrupt did not occur.
+     * |        |          |1 = Timer2 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[6]     |BGTIF     |Block Guard Time Interrupt Status Flag
+     * |        |          |This field is used for indicate block guard time interrupt status flag in receive direction.
+     * |        |          |0 = Block guard time interrupt did not occur.
+     * |        |          |1 = Block guard time interrupt occurred.
+     * |        |          |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[7]     |CDIF      |Card Detect Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for card detect interrupt status flag
+     * |        |          |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
+     * |        |          |0 = Card detect event did not occur.
+     * |        |          |1 = Card detect event occurred.
+     * |        |          |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
+     * |[8]     |INITIF    |Initial End Interrupt Status Flag
+     * |        |          |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2]))
+     * |        |          |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
+     * |        |          |0 = Initial sequence is not complete.
+     * |        |          |1 = Initial sequence is completed.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[9]     |RXTOIF    |Receive Buffer Time-out Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for indicate receive buffer time-out interrupt status flag.
+     * |        |          |0 = Receive buffer time-out interrupt did not occur.
+     * |        |          |1 = Receive buffer time-out interrupt occurred.
+     * |        |          |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT
+     * |        |          |register to clear it.
+     * |[10]    |ACERRIF   |Auto Convention Error Interrupt Status Flag
+     * |        |          |This field indicates auto convention sequence error.
+     * |        |          |0 = Received TS at ATR state is 0x3B or 0x3F.
+     * |        |          |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * @var SC_T::STATUS
+     * Offset: 0x20  SC Transfer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXOV      |Receive Overflow Error Status Flag
+     * |        |          |This bit is set when Rx buffer overflow.
+     * |        |          |0 = Rx buffer is not overflow.
+     * |        |          |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[1]     |RXEMPTY   |Receive Buffer Empty Status Flag (Read Only)
+     * |        |          |This bit indicates Rx buffer empty or not.
+     * |        |          |0 = Rx buffer is not empty.
+     * |        |          |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
+     * |[2]     |RXFULL    |Receive Buffer Full Status Flag (Read Only)
+     * |        |          |This bit indicates Rx buffer full or not.
+     * |        |          |0 = Rx buffer count is less than 4.
+     * |        |          |1 = Rx buffer count equals to 4.
+     * |[4]     |PEF       |Receiver Parity Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
+     * |        |          |0 = Receiver parity error flag did not occur.
+     * |        |          |1 = Receiver parity error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
+     * |        |          |set this flag.
+     * |[5]     |FEF       |Receiver Frame Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is,
+     * |        |          |the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = Receiver frame error flag did not occur.
+     * |        |          |1 = Receiver frame error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not
+     * |        |          |set this flag.
+     * |[6]     |BEF       |Receiver Break Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state
+     * |        |          |(logic 0) is longer than a full word transmission time (that is, the total time of start bit +
+     * |        |          |data bits + parity bit + stop bit).
+     * |        |          |0 = Receiver break error flag did not occur.
+     * |        |          |1 = Receiver break error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set
+     * |        |          |this flag.
+     * |[8]     |TXOV      |Transmit Overflow Error Interrupt Status Flag
+     * |        |          |This bit is set when Tx buffer overflow.
+     * |        |          |0 = Tx buffer is not overflow.
+     * |        |          |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[9]     |TXEMPTY   |Transmit Buffer Empty Status Flag (Read Only)
+     * |        |          |This bit indicates TX buffer empty or not.
+     * |        |          |0 = Tx buffer is not empty.
+     * |        |          |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter
+     * |        |          |Shift Register.
+     * |        |          |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
+     * |[10]    |TXFULL    |Transmit Buffer Full Status Flag (Read Only)
+     * |        |          |This bit indicates Tx buffer full or not.
+     * |        |          |0 = Tx buffer count is less than 4.
+     * |        |          |1 = Tx buffer count equals to 4.
+     * |[11]    |CREMOVE   |Card Removal Status of SCn_CD Pin
+     * |        |          |This bit is set whenever card has been removal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Card removed.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
+     * |[12]    |CINSERT   |Card Insert Status of SCn_CD Pin
+     * |        |          |This bit is set whenever card has been inserted.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Card insert.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
+     * |[13]    |CDPINSTS  |Card Detect Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_CD.
+     * |        |          |0 = The SCn_CD pin state at low.
+     * |        |          |1 = The SCn_CD pin state at high.
+     * |[18:16] |RXPOINT   |Receive Buffer Pointer Status (Read Only)
+     * |        |          |This field indicates the Rx buffer pointer status
+     * |        |          |When SC controller receives one byte from external device, RXPOINT increases one
+     * |        |          |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
+     * |[21]    |RXRERR    |Receiver Retry Error
+     * |        |          |This bit is used for receiver error retry and set by hardware.
+     * |        |          |0 = No Rx retry transfer.
+     * |        |          |1 = Rx has any error and retries transfer.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+     * |        |          |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]),
+     * |        |          |hardware will not set this flag.
+     * |[22]    |RXOVERR   |Receiver over Retry Error
+     * |        |          |This bit is used for receiver retry counts over than retry number limitation.
+     * |        |          |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
+     * |        |          |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware
+     * |        |          |will not set this flag.
+     * |[23]    |RXACT     |Receiver in Active Status Flag (Read Only)
+     * |        |          |This bit indicates Rx transfer status.
+     * |        |          |0 = This bit is cleared automatically when Rx transfer is finished.
+     * |        |          |1 = This bit is set by hardware when Rx transfer is in active.
+     * |        |          |Note: This bit is read only.
+     * |[26:24] |TXPOINT   |Transmit Buffer Pointer Status (Read Only)
+     * |        |          |This field indicates the Tx buffer pointer status
+     * |        |          |When CPU writes data into SCn_DAT, TXPOINT increases one
+     * |        |          |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
+     * |[29]    |TXRERR    |Transmitter Retry Error
+     * |        |          |This bit is used for indicate transmitter error retry and set by hardware.
+     * |        |          |0 = No Tx retry transfer.
+     * |        |          |1 = Tx has any error and retries transfer.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is a flag and cannot generate any interrupt to CPU.
+     * |[30]    |TXOVERR   |Transmitter over Retry Error
+     * |        |          |This bit is used for transmitter retry counts over than retry number limitation.
+     * |        |          |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
+     * |        |          |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[31]    |TXACT     |Transmit in Active Status Flag (Read Only)
+     * |        |          |This bit indicates Tx transmit status.
+     * |        |          |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission
+     * |        |          |has completed.
+     * |        |          |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP
+     * |        |          |bit of the last byte has not been transmitted.
+     * |        |          |Note: This bit is read only.
+     * @var SC_T::PINCTL
+     * Offset: 0x24  SC Pin Control State Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PWREN     |SCn_PWR Pin Signal
+     * |        |          |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
+     * |        |          |Write this field to drive SCn_PWR pin
+     * |        |          |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
+     * |        |          |Read this field to get SCn_PWR signal status.
+     * |        |          |0 = SCn_PWR signal status is low.
+     * |        |          |1 = SCn_PWR signal status is high.
+     * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[1]     |RSTEN     |SCn_RST Pin Signal
+     * |        |          |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
+     * |        |          |Write this field to drive SCn_RST pin.
+     * |        |          |0 = Drive SCn_RST pin to low.
+     * |        |          |1 = Drive SCn_RST pin to high.
+     * |        |          |Read this field to get SCn_RST signal status.
+     * |        |          |0 = SCn_RST signal status is low.
+     * |        |          |1 = SCn_RST signal status is high.
+     * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[6]     |CLKKEEP   |SC Clock Enable Bit
+     * |        |          |0 = SC clock generation Disabled.
+     * |        |          |1 = SC clock always keeps free running.
+     * |        |          |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[9]     |SCDATA    |SCn_DATA Pin Signal
+     * |        |          |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
+     * |        |          |0 = Drive SCn_DATA pin to low.
+     * |        |          |1 = Drive SCn_DATA pin to high.
+     * |        |          |Read this field to get SCn_DATA signal status.
+     * |        |          |0 = SCn_DATA signal status is low.
+     * |        |          |1 = SCn_DATA signal status is high.
+     * |        |          |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
+     * |        |          |Thus, do not fill in this field when SC is in these modes.
+     * |[11]    |PWRINV    |SCn_PWR Pin Inverse
+     * |        |          |This bit is used for inverse the SCn_PWR pin.
+     * |        |          |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
+     * |        |          |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0.
+     * |        |          |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1.
+     * |        |          |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1.
+     * |        |          |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0.
+     * |        |          |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
+     * |[16]    |DATASTS   |SCn_DATA Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_DATA.
+     * |        |          |0 = The SCn_DATA pin status is low.
+     * |        |          |1 = The SCn_DATA pin status is high.
+     * |[17]    |PWRSTS    |SCn_PWR Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_PWR.
+     * |        |          |0 = SCn_PWR pin to low.
+     * |        |          |1 = SCn_PWR pin to high.
+     * |[18]    |RSTSTS    |SCn_RST Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_RST.
+     * |        |          |0 = SCn_RST pin is low.
+     * |        |          |1 = SCn_RST pin is high.
+     * |[30]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL0
+     * Offset: 0x28  SC Internal Timer0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Timer0 Counter Value
+     * |        |          |This field indicates the internal Timer0 counter values.
+     * |        |          |Note: Unit of Timer0 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer0 Operation Mode Selection
+     * |        |          |This field indicates the internal 24-bit Timer0 operation selection.
+     * |        |          |Refer to Table 7.17-3 for programming Timer0.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL1
+     * Offset: 0x2C  SC Internal Timer1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNT       |Timer 1 Counter Value
+     * |        |          |This field indicates the internal Timer1 counter values.
+     * |        |          |Note: Unit of Timer1 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer 1 Operation Mode Selection
+     * |        |          |This field indicates the internal 8-bit Timer1 operation selection.
+     * |        |          |Refer to Table 7.17-3 for programming Timer1.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL2
+     * Offset: 0x30  SC Internal Timer2 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNT       |Timer 2 Counter Value
+     * |        |          |This field indicates the internal Timer2 counter values.
+     * |        |          |Note: Unit of Timer2 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer 2 Operation Mode Selection
+     * |        |          |This field indicates the internal 8-bit Timer2 operation selection
+     * |        |          |Refer to Table 7.17-3 for programming Timer2.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::UARTCTL
+     * Offset: 0x34  SC UART Mode Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |UARTEN    |UART Mode Enable Bit
+     * |        |          |Sets this bit to enable UART mode function.
+     * |        |          |0 = Smart Card mode.
+     * |        |          |1 = UART mode.
+     * |        |          |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
+     * |        |          |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
+     * |        |          |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
+     * |[5:4]   |WLS       |Word Length Selection
+     * |        |          |This field is used for select UART data length.
+     * |        |          |00 = Word length is 8 bits.
+     * |        |          |01 = Word length is 7 bits.
+     * |        |          |10 = Word length is 6 bits.
+     * |        |          |11 = Word length is 5 bits.
+     * |        |          |Note: In smart card mode, this WLS must be '00'.
+     * |[6]     |PBOFF     |Parity Bit Disable Control
+     * |        |          |Sets this bit is used for disable parity check function.
+     * |        |          |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
+     * |        |          |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+     * |        |          |Note: In smart card mode, this field must be '0' (default setting is with parity bit).
+     * |[7]     |OPE       |Odd Parity Enable Bit
+     * |        |          |This is used for odd/even parity selection.
+     * |        |          |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+     * |        |          |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+     * |        |          |Note: This bit has effect only when PBOFF bit is '0'.
+     * @var SC_T::ACTCTL
+     * Offset: 0x4C  SC Activation Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |T1EXT     |T1 Extend Time of Hardware Activation
+     * |        |          |This field provide the configurable cycles to extend the activation time T1 period.
+     * |        |          |The cycle scaling factor is 2048.
+     * |        |          |Extend cycles = (filled value * 2048) cycles.
+     * |        |          |Refer to SC activation sequence in Figure 7.17-4.
+     * |        |          |For example,
+     * |        |          |SCLK = 4MHz, each cycle = 0.25us,.
+     * |        |          |Filled 20 to this field
+     * |        |          |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
+     * |        |          |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
+     */
+    __IO uint32_t DAT;                   /*!< [0x0000] SC Receive/Transmit Holding Buffer Register                      */
+    __IO uint32_t CTL;                   /*!< [0x0004] SC Control Register                                              */
+    __IO uint32_t ALTCTL;                /*!< [0x0008] SC Alternate Control Register                                    */
+    __IO uint32_t EGT;                   /*!< [0x000c] SC Extra Guard Time Register                                     */
+    __IO uint32_t RXTOUT;                /*!< [0x0010] SC Receive Buffer Time-out Counter Register                      */
+    __IO uint32_t ETUCTL;                /*!< [0x0014] SC Element Time Unit Control Register                            */
+    __IO uint32_t INTEN;                 /*!< [0x0018] SC Interrupt Enable Control Register                             */
+    __IO uint32_t INTSTS;                /*!< [0x001c] SC Interrupt Status Register                                     */
+    __IO uint32_t STATUS;                /*!< [0x0020] SC Transfer Status Register                                      */
+    __IO uint32_t PINCTL;                /*!< [0x0024] SC Pin Control State Register                                    */
+    __IO uint32_t TMRCTL0;               /*!< [0x0028] SC Internal Timer0 Control Register                              */
+    __IO uint32_t TMRCTL1;               /*!< [0x002c] SC Internal Timer1 Control Register                              */
+    __IO uint32_t TMRCTL2;               /*!< [0x0030] SC Internal Timer2 Control Register                              */
+    __IO uint32_t UARTCTL;               /*!< [0x0034] SC UART Mode Control Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE0[5];
+    /** @endcond */
+    __IO uint32_t ACTCTL;                /*!< [0x004c] SC Activation Control Register                                   */
+
+} SC_T;
+
+/**
+    @addtogroup SC_CONST SC Bit Field Definition
+    Constant Definitions for SC Controller
+@{ */
+
+#define SC_DAT_DAT_Pos                   (0)                                               /*!< SC_T::DAT: DAT Position                */
+#define SC_DAT_DAT_Msk                   (0xfful << SC_DAT_DAT_Pos)                        /*!< SC_T::DAT: DAT Mask                    */
+
+#define SC_CTL_SCEN_Pos                  (0)                                               /*!< SC_T::CTL: SCEN Position               */
+#define SC_CTL_SCEN_Msk                  (0x1ul << SC_CTL_SCEN_Pos)                        /*!< SC_T::CTL: SCEN Mask                   */
+
+#define SC_CTL_RXOFF_Pos                 (1)                                               /*!< SC_T::CTL: RXOFF Position              */
+#define SC_CTL_RXOFF_Msk                 (0x1ul << SC_CTL_RXOFF_Pos)                       /*!< SC_T::CTL: RXOFF Mask                  */
+
+#define SC_CTL_TXOFF_Pos                 (2)                                               /*!< SC_T::CTL: TXOFF Position              */
+#define SC_CTL_TXOFF_Msk                 (0x1ul << SC_CTL_TXOFF_Pos)                       /*!< SC_T::CTL: TXOFF Mask                  */
+
+#define SC_CTL_AUTOCEN_Pos               (3)                                               /*!< SC_T::CTL: AUTOCEN Position            */
+#define SC_CTL_AUTOCEN_Msk               (0x1ul << SC_CTL_AUTOCEN_Pos)                     /*!< SC_T::CTL: AUTOCEN Mask                */
+
+#define SC_CTL_CONSEL_Pos                (4)                                               /*!< SC_T::CTL: CONSEL Position             */
+#define SC_CTL_CONSEL_Msk                (0x3ul << SC_CTL_CONSEL_Pos)                      /*!< SC_T::CTL: CONSEL Mask                 */
+
+#define SC_CTL_RXTRGLV_Pos               (6)                                               /*!< SC_T::CTL: RXTRGLV Position            */
+#define SC_CTL_RXTRGLV_Msk               (0x3ul << SC_CTL_RXTRGLV_Pos)                     /*!< SC_T::CTL: RXTRGLV Mask                */
+
+#define SC_CTL_BGT_Pos                   (8)                                               /*!< SC_T::CTL: BGT Position                */
+#define SC_CTL_BGT_Msk                   (0x1ful << SC_CTL_BGT_Pos)                        /*!< SC_T::CTL: BGT Mask                    */
+
+#define SC_CTL_TMRSEL_Pos                (13)                                              /*!< SC_T::CTL: TMRSEL Position             */
+#define SC_CTL_TMRSEL_Msk                (0x3ul << SC_CTL_TMRSEL_Pos)                      /*!< SC_T::CTL: TMRSEL Mask                 */
+
+#define SC_CTL_NSB_Pos                   (15)                                              /*!< SC_T::CTL: NSB Position                */
+#define SC_CTL_NSB_Msk                   (0x1ul << SC_CTL_NSB_Pos)                         /*!< SC_T::CTL: NSB Mask                    */
+
+#define SC_CTL_RXRTY_Pos                 (16)                                              /*!< SC_T::CTL: RXRTY Position              */
+#define SC_CTL_RXRTY_Msk                 (0x7ul << SC_CTL_RXRTY_Pos)                       /*!< SC_T::CTL: RXRTY Mask                  */
+
+#define SC_CTL_RXRTYEN_Pos               (19)                                              /*!< SC_T::CTL: RXRTYEN Position            */
+#define SC_CTL_RXRTYEN_Msk               (0x1ul << SC_CTL_RXRTYEN_Pos)                     /*!< SC_T::CTL: RXRTYEN Mask                */
+
+#define SC_CTL_TXRTY_Pos                 (20)                                              /*!< SC_T::CTL: TXRTY Position              */
+#define SC_CTL_TXRTY_Msk                 (0x7ul << SC_CTL_TXRTY_Pos)                       /*!< SC_T::CTL: TXRTY Mask                  */
+
+#define SC_CTL_TXRTYEN_Pos               (23)                                              /*!< SC_T::CTL: TXRTYEN Position            */
+#define SC_CTL_TXRTYEN_Msk               (0x1ul << SC_CTL_TXRTYEN_Pos)                     /*!< SC_T::CTL: TXRTYEN Mask                */
+
+#define SC_CTL_CDDBSEL_Pos               (24)                                              /*!< SC_T::CTL: CDDBSEL Position            */
+#define SC_CTL_CDDBSEL_Msk               (0x3ul << SC_CTL_CDDBSEL_Pos)                     /*!< SC_T::CTL: CDDBSEL Mask                */
+
+#define SC_CTL_CDLV_Pos                  (26)                                              /*!< SC_T::CTL: CDLV Position               */
+#define SC_CTL_CDLV_Msk                  (0x1ul << SC_CTL_CDLV_Pos)                        /*!< SC_T::CTL: CDLV Mask                   */
+
+#define SC_CTL_SYNC_Pos                  (30)                                              /*!< SC_T::CTL: SYNC Position               */
+#define SC_CTL_SYNC_Msk                  (0x1ul << SC_CTL_SYNC_Pos)                        /*!< SC_T::CTL: SYNC Mask                   */
+
+#define SC_ALTCTL_TXRST_Pos              (0)                                               /*!< SC_T::ALTCTL: TXRST Position           */
+#define SC_ALTCTL_TXRST_Msk              (0x1ul << SC_ALTCTL_TXRST_Pos)                    /*!< SC_T::ALTCTL: TXRST Mask               */
+
+#define SC_ALTCTL_RXRST_Pos              (1)                                               /*!< SC_T::ALTCTL: RXRST Position           */
+#define SC_ALTCTL_RXRST_Msk              (0x1ul << SC_ALTCTL_RXRST_Pos)                    /*!< SC_T::ALTCTL: RXRST Mask               */
+
+#define SC_ALTCTL_DACTEN_Pos             (2)                                               /*!< SC_T::ALTCTL: DACTEN Position          */
+#define SC_ALTCTL_DACTEN_Msk             (0x1ul << SC_ALTCTL_DACTEN_Pos)                   /*!< SC_T::ALTCTL: DACTEN Mask              */
+
+#define SC_ALTCTL_ACTEN_Pos              (3)                                               /*!< SC_T::ALTCTL: ACTEN Position           */
+#define SC_ALTCTL_ACTEN_Msk              (0x1ul << SC_ALTCTL_ACTEN_Pos)                    /*!< SC_T::ALTCTL: ACTEN Mask               */
+
+#define SC_ALTCTL_WARSTEN_Pos            (4)                                               /*!< SC_T::ALTCTL: WARSTEN Position         */
+#define SC_ALTCTL_WARSTEN_Msk            (0x1ul << SC_ALTCTL_WARSTEN_Pos)                  /*!< SC_T::ALTCTL: WARSTEN Mask             */
+
+#define SC_ALTCTL_CNTEN0_Pos             (5)                                               /*!< SC_T::ALTCTL: CNTEN0 Position          */
+#define SC_ALTCTL_CNTEN0_Msk             (0x1ul << SC_ALTCTL_CNTEN0_Pos)                   /*!< SC_T::ALTCTL: CNTEN0 Mask              */
+
+#define SC_ALTCTL_CNTEN1_Pos             (6)                                               /*!< SC_T::ALTCTL: CNTEN1 Position          */
+#define SC_ALTCTL_CNTEN1_Msk             (0x1ul << SC_ALTCTL_CNTEN1_Pos)                   /*!< SC_T::ALTCTL: CNTEN1 Mask              */
+
+#define SC_ALTCTL_CNTEN2_Pos             (7)                                               /*!< SC_T::ALTCTL: CNTEN2 Position          */
+#define SC_ALTCTL_CNTEN2_Msk             (0x1ul << SC_ALTCTL_CNTEN2_Pos)                   /*!< SC_T::ALTCTL: CNTEN2 Mask              */
+
+#define SC_ALTCTL_INITSEL_Pos            (8)                                               /*!< SC_T::ALTCTL: INITSEL Position         */
+#define SC_ALTCTL_INITSEL_Msk            (0x3ul << SC_ALTCTL_INITSEL_Pos)                  /*!< SC_T::ALTCTL: INITSEL Mask             */
+
+#define SC_ALTCTL_ADACEN_Pos             (11)                                              /*!< SC_T::ALTCTL: ADACEN Position          */
+#define SC_ALTCTL_ADACEN_Msk             (0x1ul << SC_ALTCTL_ADACEN_Pos)                   /*!< SC_T::ALTCTL: ADACEN Mask              */
+
+#define SC_ALTCTL_RXBGTEN_Pos            (12)                                              /*!< SC_T::ALTCTL: RXBGTEN Position         */
+#define SC_ALTCTL_RXBGTEN_Msk            (0x1ul << SC_ALTCTL_RXBGTEN_Pos)                  /*!< SC_T::ALTCTL: RXBGTEN Mask             */
+
+#define SC_ALTCTL_ACTSTS0_Pos            (13)                                              /*!< SC_T::ALTCTL: ACTSTS0 Position         */
+#define SC_ALTCTL_ACTSTS0_Msk            (0x1ul << SC_ALTCTL_ACTSTS0_Pos)                  /*!< SC_T::ALTCTL: ACTSTS0 Mask             */
+
+#define SC_ALTCTL_ACTSTS1_Pos            (14)                                              /*!< SC_T::ALTCTL: ACTSTS1 Position         */
+#define SC_ALTCTL_ACTSTS1_Msk            (0x1ul << SC_ALTCTL_ACTSTS1_Pos)                  /*!< SC_T::ALTCTL: ACTSTS1 Mask             */
+
+#define SC_ALTCTL_ACTSTS2_Pos            (15)                                              /*!< SC_T::ALTCTL: ACTSTS2 Position         */
+#define SC_ALTCTL_ACTSTS2_Msk            (0x1ul << SC_ALTCTL_ACTSTS2_Pos)                  /*!< SC_T::ALTCTL: ACTSTS2 Mask             */
+
+#define SC_ALTCTL_SYNC_Pos               (31)                                              /*!< SC_T::ALTCTL: SYNC Position            */
+#define SC_ALTCTL_SYNC_Msk               (0x1ul << SC_ALTCTL_SYNC_Pos)                     /*!< SC_T::ALTCTL: SYNC Mask                */
+
+#define SC_EGT_EGT_Pos                   (0)                                               /*!< SC_T::EGT: EGT Position                */
+#define SC_EGT_EGT_Msk                   (0xfful << SC_EGT_EGT_Pos)                        /*!< SC_T::EGT: EGT Mask                    */
+
+#define SC_RXTOUT_RFTM_Pos               (0)                                               /*!< SC_T::RXTOUT: RFTM Position            */
+#define SC_RXTOUT_RFTM_Msk               (0x1fful << SC_RXTOUT_RFTM_Pos)                   /*!< SC_T::RXTOUT: RFTM Mask                */
+
+#define SC_ETUCTL_ETURDIV_Pos            (0)                                               /*!< SC_T::ETUCTL: ETURDIV Position         */
+#define SC_ETUCTL_ETURDIV_Msk            (0xffful << SC_ETUCTL_ETURDIV_Pos)                /*!< SC_T::ETUCTL: ETURDIV Mask             */
+
+#define SC_INTEN_RDAIEN_Pos              (0)                                               /*!< SC_T::INTEN: RDAIEN Position           */
+#define SC_INTEN_RDAIEN_Msk              (0x1ul << SC_INTEN_RDAIEN_Pos)                    /*!< SC_T::INTEN: RDAIEN Mask               */
+
+#define SC_INTEN_TBEIEN_Pos              (1)                                               /*!< SC_T::INTEN: TBEIEN Position           */
+#define SC_INTEN_TBEIEN_Msk              (0x1ul << SC_INTEN_TBEIEN_Pos)                    /*!< SC_T::INTEN: TBEIEN Mask               */
+
+#define SC_INTEN_TERRIEN_Pos             (2)                                               /*!< SC_T::INTEN: TERRIEN Position          */
+#define SC_INTEN_TERRIEN_Msk             (0x1ul << SC_INTEN_TERRIEN_Pos)                   /*!< SC_T::INTEN: TERRIEN Mask              */
+
+#define SC_INTEN_TMR0IEN_Pos             (3)                                               /*!< SC_T::INTEN: TMR0IEN Position          */
+#define SC_INTEN_TMR0IEN_Msk             (0x1ul << SC_INTEN_TMR0IEN_Pos)                   /*!< SC_T::INTEN: TMR0IEN Mask              */
+
+#define SC_INTEN_TMR1IEN_Pos             (4)                                               /*!< SC_T::INTEN: TMR1IEN Position          */
+#define SC_INTEN_TMR1IEN_Msk             (0x1ul << SC_INTEN_TMR1IEN_Pos)                   /*!< SC_T::INTEN: TMR1IEN Mask              */
+
+#define SC_INTEN_TMR2IEN_Pos             (5)                                               /*!< SC_T::INTEN: TMR2IEN Position          */
+#define SC_INTEN_TMR2IEN_Msk             (0x1ul << SC_INTEN_TMR2IEN_Pos)                   /*!< SC_T::INTEN: TMR2IEN Mask              */
+
+#define SC_INTEN_BGTIEN_Pos              (6)                                               /*!< SC_T::INTEN: BGTIEN Position           */
+#define SC_INTEN_BGTIEN_Msk              (0x1ul << SC_INTEN_BGTIEN_Pos)                    /*!< SC_T::INTEN: BGTIEN Mask               */
+
+#define SC_INTEN_CDIEN_Pos               (7)                                               /*!< SC_T::INTEN: CDIEN Position            */
+#define SC_INTEN_CDIEN_Msk               (0x1ul << SC_INTEN_CDIEN_Pos)                     /*!< SC_T::INTEN: CDIEN Mask                */
+
+#define SC_INTEN_INITIEN_Pos             (8)                                               /*!< SC_T::INTEN: INITIEN Position          */
+#define SC_INTEN_INITIEN_Msk             (0x1ul << SC_INTEN_INITIEN_Pos)                   /*!< SC_T::INTEN: INITIEN Mask              */
+
+#define SC_INTEN_RXTOIEN_Pos             (9)                                               /*!< SC_T::INTEN: RXTOIEN Position          */
+#define SC_INTEN_RXTOIEN_Msk             (0x1ul << SC_INTEN_RXTOIEN_Pos)                   /*!< SC_T::INTEN: RXTOIEN Mask              */
+
+#define SC_INTEN_ACERRIEN_Pos            (10)                                              /*!< SC_T::INTEN: ACERRIEN Position         */
+#define SC_INTEN_ACERRIEN_Msk            (0x1ul << SC_INTEN_ACERRIEN_Pos)                  /*!< SC_T::INTEN: ACERRIEN Mask             */
+
+#define SC_INTSTS_RDAIF_Pos              (0)                                               /*!< SC_T::INTSTS: RDAIF Position           */
+#define SC_INTSTS_RDAIF_Msk              (0x1ul << SC_INTSTS_RDAIF_Pos)                    /*!< SC_T::INTSTS: RDAIF Mask               */
+
+#define SC_INTSTS_TBEIF_Pos              (1)                                               /*!< SC_T::INTSTS: TBEIF Position           */
+#define SC_INTSTS_TBEIF_Msk              (0x1ul << SC_INTSTS_TBEIF_Pos)                    /*!< SC_T::INTSTS: TBEIF Mask               */
+
+#define SC_INTSTS_TERRIF_Pos             (2)                                               /*!< SC_T::INTSTS: TERRIF Position          */
+#define SC_INTSTS_TERRIF_Msk             (0x1ul << SC_INTSTS_TERRIF_Pos)                   /*!< SC_T::INTSTS: TERRIF Mask              */
+
+#define SC_INTSTS_TMR0IF_Pos             (3)                                               /*!< SC_T::INTSTS: TMR0IF Position          */
+#define SC_INTSTS_TMR0IF_Msk             (0x1ul << SC_INTSTS_TMR0IF_Pos)                   /*!< SC_T::INTSTS: TMR0IF Mask              */
+
+#define SC_INTSTS_TMR1IF_Pos             (4)                                               /*!< SC_T::INTSTS: TMR1IF Position          */
+#define SC_INTSTS_TMR1IF_Msk             (0x1ul << SC_INTSTS_TMR1IF_Pos)                   /*!< SC_T::INTSTS: TMR1IF Mask              */
+
+#define SC_INTSTS_TMR2IF_Pos             (5)                                               /*!< SC_T::INTSTS: TMR2IF Position          */
+#define SC_INTSTS_TMR2IF_Msk             (0x1ul << SC_INTSTS_TMR2IF_Pos)                   /*!< SC_T::INTSTS: TMR2IF Mask              */
+
+#define SC_INTSTS_BGTIF_Pos              (6)                                               /*!< SC_T::INTSTS: BGTIF Position           */
+#define SC_INTSTS_BGTIF_Msk              (0x1ul << SC_INTSTS_BGTIF_Pos)                    /*!< SC_T::INTSTS: BGTIF Mask               */
+
+#define SC_INTSTS_CDIF_Pos               (7)                                               /*!< SC_T::INTSTS: CDIF Position            */
+#define SC_INTSTS_CDIF_Msk               (0x1ul << SC_INTSTS_CDIF_Pos)                     /*!< SC_T::INTSTS: CDIF Mask                */
+
+#define SC_INTSTS_INITIF_Pos             (8)                                               /*!< SC_T::INTSTS: INITIF Position          */
+#define SC_INTSTS_INITIF_Msk             (0x1ul << SC_INTSTS_INITIF_Pos)                   /*!< SC_T::INTSTS: INITIF Mask              */
+
+#define SC_INTSTS_RXTOIF_Pos             (9)                                               /*!< SC_T::INTSTS: RXTOIF Position          */
+#define SC_INTSTS_RXTOIF_Msk             (0x1ul << SC_INTSTS_RXTOIF_Pos)                   /*!< SC_T::INTSTS: RXTOIF Mask              */
+
+#define SC_INTSTS_ACERRIF_Pos            (10)                                              /*!< SC_T::INTSTS: ACERRIF Position         */
+#define SC_INTSTS_ACERRIF_Msk            (0x1ul << SC_INTSTS_ACERRIF_Pos)                  /*!< SC_T::INTSTS: ACERRIF Mask             */
+
+#define SC_STATUS_RXOV_Pos               (0)                                               /*!< SC_T::STATUS: RXOV Position            */
+#define SC_STATUS_RXOV_Msk               (0x1ul << SC_STATUS_RXOV_Pos)                     /*!< SC_T::STATUS: RXOV Mask                */
+
+#define SC_STATUS_RXEMPTY_Pos            (1)                                               /*!< SC_T::STATUS: RXEMPTY Position         */
+#define SC_STATUS_RXEMPTY_Msk            (0x1ul << SC_STATUS_RXEMPTY_Pos)                  /*!< SC_T::STATUS: RXEMPTY Mask             */
+
+#define SC_STATUS_RXFULL_Pos             (2)                                               /*!< SC_T::STATUS: RXFULL Position          */
+#define SC_STATUS_RXFULL_Msk             (0x1ul << SC_STATUS_RXFULL_Pos)                   /*!< SC_T::STATUS: RXFULL Mask              */
+
+#define SC_STATUS_PEF_Pos                (4)                                               /*!< SC_T::STATUS: PEF Position             */
+#define SC_STATUS_PEF_Msk                (0x1ul << SC_STATUS_PEF_Pos)                      /*!< SC_T::STATUS: PEF Mask                 */
+
+#define SC_STATUS_FEF_Pos                (5)                                               /*!< SC_T::STATUS: FEF Position             */
+#define SC_STATUS_FEF_Msk                (0x1ul << SC_STATUS_FEF_Pos)                      /*!< SC_T::STATUS: FEF Mask                 */
+
+#define SC_STATUS_BEF_Pos                (6)                                               /*!< SC_T::STATUS: BEF Position             */
+#define SC_STATUS_BEF_Msk                (0x1ul << SC_STATUS_BEF_Pos)                      /*!< SC_T::STATUS: BEF Mask                 */
+
+#define SC_STATUS_TXOV_Pos               (8)                                               /*!< SC_T::STATUS: TXOV Position            */
+#define SC_STATUS_TXOV_Msk               (0x1ul << SC_STATUS_TXOV_Pos)                     /*!< SC_T::STATUS: TXOV Mask                */
+
+#define SC_STATUS_TXEMPTY_Pos            (9)                                               /*!< SC_T::STATUS: TXEMPTY Position         */
+#define SC_STATUS_TXEMPTY_Msk            (0x1ul << SC_STATUS_TXEMPTY_Pos)                  /*!< SC_T::STATUS: TXEMPTY Mask             */
+
+#define SC_STATUS_TXFULL_Pos             (10)                                              /*!< SC_T::STATUS: TXFULL Position          */
+#define SC_STATUS_TXFULL_Msk             (0x1ul << SC_STATUS_TXFULL_Pos)                   /*!< SC_T::STATUS: TXFULL Mask              */
+
+#define SC_STATUS_CREMOVE_Pos            (11)                                              /*!< SC_T::STATUS: CREMOVE Position         */
+#define SC_STATUS_CREMOVE_Msk            (0x1ul << SC_STATUS_CREMOVE_Pos)                  /*!< SC_T::STATUS: CREMOVE Mask             */
+
+#define SC_STATUS_CINSERT_Pos            (12)                                              /*!< SC_T::STATUS: CINSERT Position         */
+#define SC_STATUS_CINSERT_Msk            (0x1ul << SC_STATUS_CINSERT_Pos)                  /*!< SC_T::STATUS: CINSERT Mask             */
+
+#define SC_STATUS_CDPINSTS_Pos           (13)                                              /*!< SC_T::STATUS: CDPINSTS Position        */
+#define SC_STATUS_CDPINSTS_Msk           (0x1ul << SC_STATUS_CDPINSTS_Pos)                 /*!< SC_T::STATUS: CDPINSTS Mask            */
+
+#define SC_STATUS_RXPOINT_Pos            (16)                                              /*!< SC_T::STATUS: RXPOINT Position         */
+#define SC_STATUS_RXPOINT_Msk            (0x7ul << SC_STATUS_RXPOINT_Pos)                  /*!< SC_T::STATUS: RXPOINT Mask             */
+
+#define SC_STATUS_RXRERR_Pos             (21)                                              /*!< SC_T::STATUS: RXRERR Position          */
+#define SC_STATUS_RXRERR_Msk             (0x1ul << SC_STATUS_RXRERR_Pos)                   /*!< SC_T::STATUS: RXRERR Mask              */
+
+#define SC_STATUS_RXOVERR_Pos            (22)                                              /*!< SC_T::STATUS: RXOVERR Position         */
+#define SC_STATUS_RXOVERR_Msk            (0x1ul << SC_STATUS_RXOVERR_Pos)                  /*!< SC_T::STATUS: RXOVERR Mask             */
+
+#define SC_STATUS_RXACT_Pos              (23)                                              /*!< SC_T::STATUS: RXACT Position           */
+#define SC_STATUS_RXACT_Msk              (0x1ul << SC_STATUS_RXACT_Pos)                    /*!< SC_T::STATUS: RXACT Mask               */
+
+#define SC_STATUS_TXPOINT_Pos            (24)                                              /*!< SC_T::STATUS: TXPOINT Position         */
+#define SC_STATUS_TXPOINT_Msk            (0x7ul << SC_STATUS_TXPOINT_Pos)                  /*!< SC_T::STATUS: TXPOINT Mask             */
+
+#define SC_STATUS_TXRERR_Pos             (29)                                              /*!< SC_T::STATUS: TXRERR Position          */
+#define SC_STATUS_TXRERR_Msk             (0x1ul << SC_STATUS_TXRERR_Pos)                   /*!< SC_T::STATUS: TXRERR Mask              */
+
+#define SC_STATUS_TXOVERR_Pos            (30)                                              /*!< SC_T::STATUS: TXOVERR Position         */
+#define SC_STATUS_TXOVERR_Msk            (0x1ul << SC_STATUS_TXOVERR_Pos)                  /*!< SC_T::STATUS: TXOVERR Mask             */
+
+#define SC_STATUS_TXACT_Pos              (31)                                              /*!< SC_T::STATUS: TXACT Position           */
+#define SC_STATUS_TXACT_Msk              (0x1ul << SC_STATUS_TXACT_Pos)                    /*!< SC_T::STATUS: TXACT Mask               */
+
+#define SC_PINCTL_PWREN_Pos              (0)                                               /*!< SC_T::PINCTL: PWREN Position           */
+#define SC_PINCTL_PWREN_Msk              (0x1ul << SC_PINCTL_PWREN_Pos)                    /*!< SC_T::PINCTL: PWREN Mask               */
+
+#define SC_PINCTL_RSTEN_Pos              (1)                                               /*!< SC_T::PINCTL: RSTEN Position           */
+#define SC_PINCTL_RSTEN_Msk              (0x1ul << SC_PINCTL_RSTEN_Pos)                    /*!< SC_T::PINCTL: RSTEN Mask               */
+
+#define SC_PINCTL_CLKKEEP_Pos            (6)                                               /*!< SC_T::PINCTL: CLKKEEP Position         */
+#define SC_PINCTL_CLKKEEP_Msk            (0x1ul << SC_PINCTL_CLKKEEP_Pos)                  /*!< SC_T::PINCTL: CLKKEEP Mask             */
+
+#define SC_PINCTL_SCDATA_Pos             (9)                                               /*!< SC_T::PINCTL: SCDATA Position          */
+#define SC_PINCTL_SCDATA_Msk             (0x1ul << SC_PINCTL_SCDATA_Pos)                   /*!< SC_T::PINCTL: SCDATA Mask              */
+
+#define SC_PINCTL_PWRINV_Pos             (11)                                              /*!< SC_T::PINCTL: PWRINV Position          */
+#define SC_PINCTL_PWRINV_Msk             (0x1ul << SC_PINCTL_PWRINV_Pos)                   /*!< SC_T::PINCTL: PWRINV Mask              */
+
+#define SC_PINCTL_DATASTS_Pos            (16)                                              /*!< SC_T::PINCTL: DATASTS Position         */
+#define SC_PINCTL_DATASTS_Msk            (0x1ul << SC_PINCTL_DATASTS_Pos)                  /*!< SC_T::PINCTL: DATASTS Mask             */
+
+#define SC_PINCTL_PWRSTS_Pos             (17)                                              /*!< SC_T::PINCTL: PWRSTS Position          */
+#define SC_PINCTL_PWRSTS_Msk             (0x1ul << SC_PINCTL_PWRSTS_Pos)                   /*!< SC_T::PINCTL: PWRSTS Mask              */
+
+#define SC_PINCTL_RSTSTS_Pos             (18)                                              /*!< SC_T::PINCTL: RSTSTS Position          */
+#define SC_PINCTL_RSTSTS_Msk             (0x1ul << SC_PINCTL_RSTSTS_Pos)                   /*!< SC_T::PINCTL: RSTSTS Mask              */
+
+#define SC_PINCTL_SYNC_Pos               (30)                                              /*!< SC_T::PINCTL: SYNC Position            */
+#define SC_PINCTL_SYNC_Msk               (0x1ul << SC_PINCTL_SYNC_Pos)                     /*!< SC_T::PINCTL: SYNC Mask                */
+
+#define SC_TMRCTL0_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL0: CNT Position            */
+#define SC_TMRCTL0_CNT_Msk               (0xfffffful << SC_TMRCTL0_CNT_Pos)                /*!< SC_T::TMRCTL0: CNT Mask                */
+
+#define SC_TMRCTL0_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL0: OPMODE Position         */
+#define SC_TMRCTL0_OPMODE_Msk            (0xful << SC_TMRCTL0_OPMODE_Pos)                  /*!< SC_T::TMRCTL0: OPMODE Mask             */
+
+#define SC_TMRCTL0_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL0: SYNC Position           */
+#define SC_TMRCTL0_SYNC_Msk              (0x1ul << SC_TMRCTL0_SYNC_Pos)                    /*!< SC_T::TMRCTL0: SYNC Mask               */
+
+#define SC_TMRCTL1_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL1: CNT Position            */
+#define SC_TMRCTL1_CNT_Msk               (0xfful << SC_TMRCTL1_CNT_Pos)                    /*!< SC_T::TMRCTL1: CNT Mask                */
+
+#define SC_TMRCTL1_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL1: OPMODE Position         */
+#define SC_TMRCTL1_OPMODE_Msk            (0xful << SC_TMRCTL1_OPMODE_Pos)                  /*!< SC_T::TMRCTL1: OPMODE Mask             */
+
+#define SC_TMRCTL1_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL1: SYNC Position           */
+#define SC_TMRCTL1_SYNC_Msk              (0x1ul << SC_TMRCTL1_SYNC_Pos)                    /*!< SC_T::TMRCTL1: SYNC Mask               */
+
+#define SC_TMRCTL2_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL2: CNT Position            */
+#define SC_TMRCTL2_CNT_Msk               (0xfful << SC_TMRCTL2_CNT_Pos)                    /*!< SC_T::TMRCTL2: CNT Mask                */
+
+#define SC_TMRCTL2_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL2: OPMODE Position         */
+#define SC_TMRCTL2_OPMODE_Msk            (0xful << SC_TMRCTL2_OPMODE_Pos)                  /*!< SC_T::TMRCTL2: OPMODE Mask             */
+
+#define SC_TMRCTL2_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL2: SYNC Position           */
+#define SC_TMRCTL2_SYNC_Msk              (0x1ul << SC_TMRCTL2_SYNC_Pos)                    /*!< SC_T::TMRCTL2: SYNC Mask               */
+
+#define SC_UARTCTL_UARTEN_Pos            (0)                                               /*!< SC_T::UARTCTL: UARTEN Position         */
+#define SC_UARTCTL_UARTEN_Msk            (0x1ul << SC_UARTCTL_UARTEN_Pos)                  /*!< SC_T::UARTCTL: UARTEN Mask             */
+
+#define SC_UARTCTL_WLS_Pos               (4)                                               /*!< SC_T::UARTCTL: WLS Position            */
+#define SC_UARTCTL_WLS_Msk               (0x3ul << SC_UARTCTL_WLS_Pos)                     /*!< SC_T::UARTCTL: WLS Mask                */
+
+#define SC_UARTCTL_PBOFF_Pos             (6)                                               /*!< SC_T::UARTCTL: PBOFF Position          */
+#define SC_UARTCTL_PBOFF_Msk             (0x1ul << SC_UARTCTL_PBOFF_Pos)                   /*!< SC_T::UARTCTL: PBOFF Mask              */
+
+#define SC_UARTCTL_OPE_Pos               (7)                                               /*!< SC_T::UARTCTL: OPE Position            */
+#define SC_UARTCTL_OPE_Msk               (0x1ul << SC_UARTCTL_OPE_Pos)                     /*!< SC_T::UARTCTL: OPE Mask                */
+
+#define SC_ACTCTL_T1EXT_Pos              (0)                                               /*!< SC_T::ACTCTL: T1EXT Position           */
+#define SC_ACTCTL_T1EXT_Msk              (0x1ful << SC_ACTCTL_T1EXT_Pos)                   /*!< SC_T::ACTCTL: T1EXT Mask               */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+
+
+/*---------------------- I2S Interface Controller -------------------------*/
+/**
+    @addtogroup I2S I2S Interface Controller(I2S)
+    Memory Mapped Structure for I2S Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var I2S_T::CTL0
+     * Offset: 0x00  I2S Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SEN     |I2S Controller Enable Control
+     * |        |          |0 = I2S controller Disabled.
+     * |        |          |1 = I2S controller Enabled.
+     * |[1]     |TXEN      |Transmit Enable Control
+     * |        |          |0 = Data transmission Disabled.
+     * |        |          |1 = Data transmission Enabled.
+     * |[2]     |RXEN      |Receive Enable Control
+     * |        |          |0 = Data receiving Disabled.
+     * |        |          |1 = Data receiving Enabled.
+     * |[3]     |MUTE      |Transmit Mute Enable Control
+     * |        |          |0 = Transmit data is shifted from buffer.
+     * |        |          |1 = Send zero on transmit channel.
+     * |[5:4]   |DATWIDTH  |Data Width
+     * |        |          |This bit field is used to define the bit-width of data word in each audio channel
+     * |        |          |00 = The bit-width of data word is 8-bit.
+     * |        |          |01 = The bit-width of data word is 16-bit.
+     * |        |          |10 = The bit-width of data word is 24-bit.
+     * |        |          |11 = The bit-width of data word is 32-bit.
+     * |[6]     |MONO      |Monaural Data Control
+     * |        |          |0 = Data is stereo format.
+     * |        |          |1 = Data is monaural format.
+     * |        |          |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
+     * |[7]     |ORDER     |Stereo Data Order in FIFO
+     * |        |          |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
+     * |        |          |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
+     * |        |          |0 = Even channel data at high byte in 8-bit/16-bit data width.
+     * |        |          |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
+     * |        |          |1 = Even channel data at low byte.
+     * |        |          | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
+     * |[8]     |SLAVE     |Slave Mode Enable Control
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |        |          |Note: I2S can operate as master or slave
+     * |        |          |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
+     * |        |          |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
+     * |[15]    |MCLKEN    |Master Clock Enable Control
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
+     * |        |          |0 = Master clock Disabled.
+     * |        |          |1 = Master clock Enabled.
+     * |[18]    |TXFBCLR   |Transmit FIFO Buffer Clear
+     * |        |          |0 = No Effect.
+     * |        |          |1 = Clear TX FIFO.
+     * |        |          |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
+     * |        |          |Note2: This bit is clear by hardware automatically, read it return zero.
+     * |[19]    |RXFBCLR   |Receive FIFO Buffer Clear
+     * |        |          |0 = No Effect.
+     * |        |          |1 = Clear RX FIFO.
+     * |        |          |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
+     * |        |          |Note2: This bit is cleared by hardware automatically, read it return zero.
+     * |[20]    |TXPDMAEN  |Transmit PDMA Enable Control
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[21]    |RXPDMAEN  |Receive PDMA Enable Control
+     * |        |          |0 = Receiver PDMA function Disabled.
+     * |        |          |1 = Receiver PDMA function Enabled.
+     * |[23]    |RXLCH     |Receive Left Channel Enable Control
+     * |        |          |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
+     * |        |          |0 = Receives channel1 data in MONO mode.
+     * |        |          |1 = Receives channel0 data in MONO mode.
+     * |[26:24] |FORMAT    |Data Format Selection
+     * |        |          |000 = I2S standard data format.
+     * |        |          |001 = I2S with MSB justified.
+     * |        |          |010 = I2S with LSB justified.
+     * |        |          |011 = Reserved.
+     * |        |          |100 = PCM standard data format.
+     * |        |          |101 = PCM with MSB justified.
+     * |        |          |110 = PCM with LSB justified.
+     * |        |          |111 = Reserved.
+     * |[27]    |PCMSYNC   |PCM Synchronization Pulse Length Selection
+     * |        |          |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
+     * |        |          |0 = One BCLK period.
+     * |        |          |1 = One channel period.
+     * |        |          |Note: This bit is only available in master mode
+     * |[29:28] |CHWIDTH   |Channel Width
+     * |        |          |This bit fields are used to define the length of audio channel
+     * |        |          |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
+     * |        |          |00 = The bit-width of each audio channel is 8-bit.
+     * |        |          |01 = The bit-width of each audio channel is 16-bit.
+     * |        |          |10 = The bit-width of each audio channel is 24-bit.
+     * |        |          |11 = The bit-width of each audio channel is 32-bit.
+     * |[31:30] |TDMCHNUM  |TDM Channel Number
+     * |        |          |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
+     * |        |          |00 = 2 channels in audio frame.
+     * |        |          |01 = 4 channels in audio frame.
+     * |        |          |10 = 6 channels in audio frame.
+     * |        |          |11 = 8 channels in audio frame.
+     * @var I2S_T::CLKDIV
+     * Offset: 0x04  I2S Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |MCLKDIV   |Master Clock Divider
+     * |        |          |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
+     * |        |          |If MCLKDIV is set to 0, MCLK is the same as external clock input.
+     * |        |          |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
+     * |        |          |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
+     * |        |          |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
+     * |        |          |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
+     * |[16:8]  |BCLKDIV   |Bit Clock Divider
+     * |        |          |The I2S controller will generate bit clock in Master mode
+     * |        |          |Software can program these bit fields to generate sampling rate clock frequency.
+     * |        |          |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
+     * |        |          |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
+     * @var I2S_T::IEN
+     * Offset: 0x08  I2S Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXUDFIEN  |Receive FIFO Underflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
+     * |[1]     |RXOVFIEN  |Receive FIFO Overflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
+     * |[2]     |RXTHIEN   |Receive FIFO Threshold Level Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
+     * |        |          |If RXTHIEN bit is enabled, interrupt occur.
+     * |[8]     |TXUDFIEN  |Transmit FIFO Underflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
+     * |[9]     |TXOVFIEN  |Transmit FIFO Overflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
+     * |[10]    |TXTHIEN   |Transmit FIFO Threshold Level Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
+     * |[16]    |CH0ZCIEN  |Channel0 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
+     * |        |          |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[17]    |CH1ZCIEN  |Channel1 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
+     * |        |          |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[18]    |CH2ZCIEN  |Channel2 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[19]    |CH3ZCIEN  |Channel3 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[20]    |CH4ZCIEN  |Channel4 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[21]    |CH5ZCIEN  |Channel5 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[22]    |CH6ZCIEN  |Channel6 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[23]    |CH7ZCIEN  |Channel7 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * @var I2S_T::STATUS0
+     * Offset: 0x0C  I2S Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SINT    |I2S Interrupt Flag (Read Only)
+     * |        |          |0 = No I2S interrupt.
+     * |        |          |1 = I2S interrupt.
+     * |        |          |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
+     * |[1]     |I2SRXINT  |I2S Receive Interrupt (Read Only)
+     * |        |          |0 = No receive interrupt.
+     * |        |          |1 = Receive interrupt.
+     * |[2]     |I2STXINT  |I2S Transmit Interrupt (Read Only)
+     * |        |          |0 = No transmit interrupt.
+     * |        |          |1 = Transmit interrupt.
+     * |[5:3]   |DATACH    |Transmission Data Channel (Read Only)
+     * |        |          |This bit fields are used to indicate which audio channel is current transmit data belong.
+     * |        |          |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
+     * |        |          |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
+     * |        |          |010 = channel2 (available while 4-channel TDM PCM mode).
+     * |        |          |011 = channel3 (available while 4-channel TDM PCM mode).
+     * |        |          |100 = channel4 (available while 6-channel TDM PCM mode).
+     * |        |          |101 = channel5 (available while 6-channel TDM PCM mode).
+     * |        |          |110 = channel6 (available while 8-channel TDM PCM mode).
+     * |        |          |111 = channel7 (available while 8-channel TDM PCM mode).
+     * |[8]     |RXUDIF    |Receive FIFO Underflow Interrupt Flag
+     * |        |          |0 = No underflow occur.
+     * |        |          |1 = Underflow occur.
+     * |        |          |Note1: When receive FIFO is empty, and software reads the receive FIFO again
+     * |        |          |This bit will be set to 1, and it indicates underflow situation occurs.
+     * |        |          |Note2: Write 1 to clear this bit to zero
+     * |[9]     |RXOVIF    |Receive FIFO Overflow Interrupt Flag
+     * |        |          |0 = No overflow occur.
+     * |        |          |1 = Overflow occur.
+     * |        |          |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
+     * |        |          |Note2: Write 1 to clear this bit to 0.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = Data word(s) in FIFO is not higher than threshold level.
+     * |        |          |1 = Data word(s) in FIFO is higher than threshold level.
+     * |        |          |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
+     * |        |          |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
+     * |[11]    |RXFULL    |Receive FIFO Full (Read Only)
+     * |        |          |0 = Not full.
+     * |        |          |1 = Full.
+     * |        |          |Note: This bit reflects data words number in receive FIFO is 16.
+     * |[12]    |RXEMPTY   |Receive FIFO Empty (Read Only)
+     * |        |          |0 = Not empty.
+     * |        |          |1 = Empty.
+     * |        |          |Note: This bit reflects data words number in receive FIFO is zero
+     * |[16]    |TXUDIF    |Transmit FIFO Underflow Interrupt Flag
+     * |        |          |0 = No underflow.
+     * |        |          |1 = Underflow.
+     * |        |          |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
+     * |        |          |Note2: Write 1 to clear this bit to 0.
+     * |[17]    |TXOVIF    |Transmit FIFO Overflow Interrupt Flag
+     * |        |          |0 = No overflow.
+     * |        |          |1 = Overflow.
+     * |        |          |Note1: Write data to transmit FIFO when it is full and this bit set to 1
+     * |        |          |Note2: Write 1 to clear this bit to 0.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = Data word(s) in FIFO is higher than threshold level.
+     * |        |          |1 = Data word(s) in FIFO is equal or lower than threshold level.
+     * |        |          |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
+     * |        |          |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
+     * |[19]    |TXFULL    |Transmit FIFO Full (Read Only)
+     * |        |          |This bit reflect data word number in transmit FIFO is 16
+     * |        |          |0 = Not full.
+     * |        |          |1 = Full.
+     * |[20]    |TXEMPTY   |Transmit FIFO Empty (Read Only)
+     * |        |          |This bit reflect data word number in transmit FIFO is zero
+     * |        |          |0 = Not empty.
+     * |        |          |1 = Empty.
+     * |[21]    |TXBUSY    |Transmit Busy (Read Only)
+     * |        |          |0 = Transmit shift buffer is empty.
+     * |        |          |1 = Transmit shift buffer is busy.
+     * |        |          |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
+     * |        |          |And set to 1 when 1st data is load to shift buffer
+     * @var I2S_T::TXFIFO
+     * Offset: 0x10  I2S Transmit FIFO Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXFIFO    |Transmit FIFO Bits
+     * |        |          |I2S contains 16 words (16x32 bit) data buffer for data transmit
+     * |        |          |Write data to this register to prepare data for transmit
+     * |        |          |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
+     * @var I2S_T::RXFIFO
+     * Offset: 0x14  I2S Receive FIFO Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXFIFO    |Receive FIFO Bits
+     * |        |          |I2S contains 16 words (16x32 bit) data buffer for data receive
+     * |        |          |Read this register to get data in FIFO
+     * |        |          |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
+     * @var I2S_T::CTL1
+     * Offset: 0x20  I2S Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CH0ZCEN   |Channel0 Zero-cross Detection Enable Control
+     * |        |          |0 = channel0 zero-cross detect Disabled.
+     * |        |          |1 = channel0 zero-cross detect Enabled.
+     * |        |          |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |        |          |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
+     * |        |          |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
+     * |[1]     |CH1ZCEN   |Channel1 Zero-cross Detect Enable Control
+     * |        |          |0 = channel1 zero-cross detect Disabled.
+     * |        |          |1 = channel1 zero-cross detect Enabled.
+     * |        |          |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |        |          |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
+     * |        |          |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
+     * |[2]     |CH2ZCEN   |Channel2 Zero-cross Detect Enable Control
+     * |        |          |0 = channel2 zero-cross detect Disabled.
+     * |        |          |1 = channel2 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
+     * |        |          |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
+     * |[3]     |CH3ZCEN   |Channel3 Zero-cross Detect Enable Control
+     * |        |          |0 = channel3 zero-cross detect Disabled.
+     * |        |          |1 = channel3 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
+     * |        |          |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
+     * |[4]     |CH4ZCEN   |Channel4 Zero-cross Detect Enable Control
+     * |        |          |0 = channel4 zero-cross detect Disabled.
+     * |        |          |1 = channel4 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
+     * |        |          |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
+     * |[5]     |CH5ZCEN   |Channel5 Zero-cross Detect Enable Control
+     * |        |          |0 = channel5 zero-cross detect Disabled.
+     * |        |          |1 = channel5 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
+     * |        |          |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
+     * |[6]     |CH6ZCEN   |Channel6 Zero-cross Detect Enable Control
+     * |        |          |0 = channel6 zero-cross detect Disabled.
+     * |        |          |1 = channel6 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
+     * |        |          |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
+     * |[7]     |CH7ZCEN   |Channel7 Zero-cross Detect Enable Control
+     * |        |          |0 = channel7 zero-cross detect Disabled.
+     * |        |          |1 = channel7 zero-cross detect Enabled.
+     * |        |          |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
+     * |        |          |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
+     * |[11:8]  |TXTH      |Transmit FIFO Threshold Level
+     * |        |          |0000 = 0 data word in transmit FIFO.
+     * |        |          |0001 = 1 data word in transmit FIFO.
+     * |        |          |0010 = 2 data words in transmit FIFO.
+     * |        |          |...
+     * |        |          |1110 = 14 data words in transmit FIFO.
+     * |        |          |1111 = 15 data words in transmit FIFO.
+     * |        |          |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
+     * |[19:16] |RXTH      |Receive FIFO Threshold Level
+     * |        |          |0000 = 1 data word in receive FIFO.
+     * |        |          |0001 = 2 data words in receive FIFO.
+     * |        |          |0010 = 3 data words in receive FIFO.
+     * |        |          |...
+     * |        |          |1110 = 15 data words in receive FIFO.
+     * |        |          |1111 = 16 data words in receive FIFO.
+     * |        |          |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
+     * |[24]    |PBWIDTH   |Peripheral Bus Data Width Selection
+     * |        |          |This bit is used to choice the available data width of APB bus
+     * |        |          |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
+     * |        |          |0 = 32 bits data width.
+     * |        |          |1 = 16 bits data width.
+     * |        |          |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
+     * |        |          |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
+     * |        |          |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
+     * |[25]    |PB16ORD   |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
+     * |        |          |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
+     * |        |          |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
+     * |        |          |0 = Low 16-bit read/write access first.
+     * |        |          |1 = High 16-bit read/write access first.
+     * |        |          |Note: This bit is available while PBWIDTH = 1.
+     * @var I2S_T::STATUS1
+     * Offset: 0x24  I2S Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CH0ZCIF   |Channel0 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel0.
+     * |        |          |1 = Channel0 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[1]     |CH1ZCIF   |Channel1 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel1.
+     * |        |          |1 = Channel1 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[2]     |CH2ZCIF   |Channel2 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel2.
+     * |        |          |1 = Channel2 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[3]     |CH3ZCIF   |Channel3 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel3.
+     * |        |          |1 = Channel3 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[4]     |CH4ZCIF   |Channel4 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel4.
+     * |        |          |1 = Channel4 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[5]     |CH5ZCIF   |Channel5 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel5.
+     * |        |          |1 = Channel5 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[6]     |CH6ZCIF   |Channel6 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel6.
+     * |        |          |1 = Channel6 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[7]     |CH7ZCIF   |Channel7 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel7.
+     * |        |          |1 = Channel7 zero-cross is detected.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[12:8]  |TXCNT     |Transmit FIFO Level (Read Only)
+     * |        |          |These bits indicate the number of available entries in transmit FIFO
+     * |        |          |00000 = No data.
+     * |        |          |00001 = 1 word in transmit FIFO.
+     * |        |          |00010 = 2 words in transmit FIFO.
+     * |        |          |...
+     * |        |          |01110 = 14 words in transmit FIFO.
+     * |        |          |01111 = 15 words in transmit FIFO.
+     * |        |          |10000 = 16 words in transmit FIFO.
+     * |        |          |Others are reserved.
+     * |[20:16] |RXCNT     |Receive FIFO Level (Read Only)
+     * |        |          |These bits indicate the number of available entries in receive FIFO
+     * |        |          |00000 = No data.
+     * |        |          |00001 = 1 word in receive FIFO.
+     * |        |          |00010 = 2 words in receive FIFO.
+     * |        |          |...
+     * |        |          |01110 = 14 words in receive FIFO.
+     * |        |          |01111 = 15 words in receive FIFO.
+     * |        |          |10000 = 16 words in receive FIFO.
+     * |        |          |Others are reserved.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] I2S Control Register 0                                           */
+    __IO uint32_t CLKDIV;                /*!< [0x0004] I2S Clock Divider Register                                       */
+    __IO uint32_t IEN;                   /*!< [0x0008] I2S Interrupt Enable Register                                    */
+    __IO uint32_t STATUS0;               /*!< [0x000c] I2S Status Register 0                                            */
+    __O  uint32_t TXFIFO;                /*!< [0x0010] I2S Transmit FIFO Register                                       */
+    __I  uint32_t RXFIFO;                /*!< [0x0014] I2S Receive FIFO Register                                        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL1;                  /*!< [0x0020] I2S Control Register 1                                           */
+    __IO uint32_t STATUS1;               /*!< [0x0024] I2S Status Register 1                                            */
+
+} I2S_T;
+
+/**
+    @addtogroup I2S_CONST I2S Bit Field Definition
+    Constant Definitions for I2S Controller
+@{ */
+
+#define I2S_CTL0_I2SEN_Pos               (0)                                               /*!< I2S_T::CTL0: I2SEN Position            */
+#define I2S_CTL0_I2SEN_Msk               (0x1ul << I2S_CTL0_I2SEN_Pos)                     /*!< I2S_T::CTL0: I2SEN Mask                */
+
+#define I2S_CTL0_TXEN_Pos                (1)                                               /*!< I2S_T::CTL0: TXEN Position             */
+#define I2S_CTL0_TXEN_Msk                (0x1ul << I2S_CTL0_TXEN_Pos)                      /*!< I2S_T::CTL0: TXEN Mask                 */
+
+#define I2S_CTL0_RXEN_Pos                (2)                                               /*!< I2S_T::CTL0: RXEN Position             */
+#define I2S_CTL0_RXEN_Msk                (0x1ul << I2S_CTL0_RXEN_Pos)                      /*!< I2S_T::CTL0: RXEN Mask                 */
+
+#define I2S_CTL0_MUTE_Pos                (3)                                               /*!< I2S_T::CTL0: MUTE Position             */
+#define I2S_CTL0_MUTE_Msk                (0x1ul << I2S_CTL0_MUTE_Pos)                      /*!< I2S_T::CTL0: MUTE Mask                 */
+
+#define I2S_CTL0_DATWIDTH_Pos            (4)                                               /*!< I2S_T::CTL0: DATWIDTH Position         */
+#define I2S_CTL0_DATWIDTH_Msk            (0x3ul << I2S_CTL0_DATWIDTH_Pos)                  /*!< I2S_T::CTL0: DATWIDTH Mask             */
+
+#define I2S_CTL0_MONO_Pos                (6)                                               /*!< I2S_T::CTL0: MONO Position             */
+#define I2S_CTL0_MONO_Msk                (0x1ul << I2S_CTL0_MONO_Pos)                      /*!< I2S_T::CTL0: MONO Mask                 */
+
+#define I2S_CTL0_ORDER_Pos               (7)                                               /*!< I2S_T::CTL0: ORDER Position            */
+#define I2S_CTL0_ORDER_Msk               (0x1ul << I2S_CTL0_ORDER_Pos)                     /*!< I2S_T::CTL0: ORDER Mask                */
+
+#define I2S_CTL0_SLAVE_Pos               (8)                                               /*!< I2S_T::CTL0: SLAVE Position            */
+#define I2S_CTL0_SLAVE_Msk               (0x1ul << I2S_CTL0_SLAVE_Pos)                     /*!< I2S_T::CTL0: SLAVE Mask                */
+
+#define I2S_CTL0_MCLKEN_Pos              (15)                                              /*!< I2S_T::CTL0: MCLKEN Position           */
+#define I2S_CTL0_MCLKEN_Msk              (0x1ul << I2S_CTL0_MCLKEN_Pos)                    /*!< I2S_T::CTL0: MCLKEN Mask               */
+
+#define I2S_CTL0_TXFBCLR_Pos             (18)                                              /*!< I2S_T::CTL0: TXFBCLR Position          */
+#define I2S_CTL0_TXFBCLR_Msk             (0x1ul << I2S_CTL0_TXFBCLR_Pos)                   /*!< I2S_T::CTL0: TXFBCLR Mask              */
+
+#define I2S_CTL0_RXFBCLR_Pos             (19)                                              /*!< I2S_T::CTL0: RXFBCLR Position          */
+#define I2S_CTL0_RXFBCLR_Msk             (0x1ul << I2S_CTL0_RXFBCLR_Pos)                   /*!< I2S_T::CTL0: RXFBCLR Mask              */
+
+#define I2S_CTL0_TXPDMAEN_Pos            (20)                                              /*!< I2S_T::CTL0: TXPDMAEN Position         */
+#define I2S_CTL0_TXPDMAEN_Msk            (0x1ul << I2S_CTL0_TXPDMAEN_Pos)                  /*!< I2S_T::CTL0: TXPDMAEN Mask             */
+
+#define I2S_CTL0_RXPDMAEN_Pos            (21)                                              /*!< I2S_T::CTL0: RXPDMAEN Position         */
+#define I2S_CTL0_RXPDMAEN_Msk            (0x1ul << I2S_CTL0_RXPDMAEN_Pos)                  /*!< I2S_T::CTL0: RXPDMAEN Mask             */
+
+#define I2S_CTL0_RXLCH_Pos               (23)                                              /*!< I2S_T::CTL0: RXLCH Position            */
+#define I2S_CTL0_RXLCH_Msk               (0x1ul << I2S_CTL0_RXLCH_Pos)                     /*!< I2S_T::CTL0: RXLCH Mask                */
+
+#define I2S_CTL0_FORMAT_Pos              (24)                                              /*!< I2S_T::CTL0: FORMAT Position           */
+#define I2S_CTL0_FORMAT_Msk              (0x7ul << I2S_CTL0_FORMAT_Pos)                    /*!< I2S_T::CTL0: FORMAT Mask               */
+
+#define I2S_CTL0_PCMSYNC_Pos             (27)                                              /*!< I2S_T::CTL0: PCMSYNC Position          */
+#define I2S_CTL0_PCMSYNC_Msk             (0x1ul << I2S_CTL0_PCMSYNC_Pos)                   /*!< I2S_T::CTL0: PCMSYNC Mask              */
+
+#define I2S_CTL0_CHWIDTH_Pos             (28)                                              /*!< I2S_T::CTL0: CHWIDTH Position          */
+#define I2S_CTL0_CHWIDTH_Msk             (0x3ul << I2S_CTL0_CHWIDTH_Pos)                   /*!< I2S_T::CTL0: CHWIDTH Mask              */
+
+#define I2S_CTL0_TDMCHNUM_Pos            (30)                                              /*!< I2S_T::CTL0: TDMCHNUM Position         */
+#define I2S_CTL0_TDMCHNUM_Msk            (0x3ul << I2S_CTL0_TDMCHNUM_Pos)                  /*!< I2S_T::CTL0: TDMCHNUM Mask             */
+
+#define I2S_CLKDIV_MCLKDIV_Pos           (0)                                               /*!< I2S_T::CLKDIV: MCLKDIV Position        */
+#define I2S_CLKDIV_MCLKDIV_Msk           (0x3ful << I2S_CLKDIV_MCLKDIV_Pos)                /*!< I2S_T::CLKDIV: MCLKDIV Mask            */
+
+#define I2S_CLKDIV_BCLKDIV_Pos           (8)                                               /*!< I2S_T::CLKDIV: BCLKDIV Position        */
+#define I2S_CLKDIV_BCLKDIV_Msk           (0x1fful << I2S_CLKDIV_BCLKDIV_Pos)               /*!< I2S_T::CLKDIV: BCLKDIV Mask            */
+
+#define I2S_IEN_RXUDFIEN_Pos             (0)                                               /*!< I2S_T::IEN: RXUDFIEN Position          */
+#define I2S_IEN_RXUDFIEN_Msk             (0x1ul << I2S_IEN_RXUDFIEN_Pos)                   /*!< I2S_T::IEN: RXUDFIEN Mask              */
+
+#define I2S_IEN_RXOVFIEN_Pos             (1)                                               /*!< I2S_T::IEN: RXOVFIEN Position          */
+#define I2S_IEN_RXOVFIEN_Msk             (0x1ul << I2S_IEN_RXOVFIEN_Pos)                   /*!< I2S_T::IEN: RXOVFIEN Mask              */
+
+#define I2S_IEN_RXTHIEN_Pos              (2)                                               /*!< I2S_T::IEN: RXTHIEN Position           */
+#define I2S_IEN_RXTHIEN_Msk              (0x1ul << I2S_IEN_RXTHIEN_Pos)                    /*!< I2S_T::IEN: RXTHIEN Mask               */
+
+#define I2S_IEN_TXUDFIEN_Pos             (8)                                               /*!< I2S_T::IEN: TXUDFIEN Position          */
+#define I2S_IEN_TXUDFIEN_Msk             (0x1ul << I2S_IEN_TXUDFIEN_Pos)                   /*!< I2S_T::IEN: TXUDFIEN Mask              */
+
+#define I2S_IEN_TXOVFIEN_Pos             (9)                                               /*!< I2S_T::IEN: TXOVFIEN Position          */
+#define I2S_IEN_TXOVFIEN_Msk             (0x1ul << I2S_IEN_TXOVFIEN_Pos)                   /*!< I2S_T::IEN: TXOVFIEN Mask              */
+
+#define I2S_IEN_TXTHIEN_Pos              (10)                                              /*!< I2S_T::IEN: TXTHIEN Position           */
+#define I2S_IEN_TXTHIEN_Msk              (0x1ul << I2S_IEN_TXTHIEN_Pos)                    /*!< I2S_T::IEN: TXTHIEN Mask               */
+
+#define I2S_IEN_CH0ZCIEN_Pos             (16)                                              /*!< I2S_T::IEN: CH0ZCIEN Position          */
+#define I2S_IEN_CH0ZCIEN_Msk             (0x1ul << I2S_IEN_CH0ZCIEN_Pos)                   /*!< I2S_T::IEN: CH0ZCIEN Mask              */
+
+#define I2S_IEN_CH1ZCIEN_Pos             (17)                                              /*!< I2S_T::IEN: CH1ZCIEN Position          */
+#define I2S_IEN_CH1ZCIEN_Msk             (0x1ul << I2S_IEN_CH1ZCIEN_Pos)                   /*!< I2S_T::IEN: CH1ZCIEN Mask              */
+
+#define I2S_IEN_CH2ZCIEN_Pos             (18)                                              /*!< I2S_T::IEN: CH2ZCIEN Position          */
+#define I2S_IEN_CH2ZCIEN_Msk             (0x1ul << I2S_IEN_CH2ZCIEN_Pos)                   /*!< I2S_T::IEN: CH2ZCIEN Mask              */
+
+#define I2S_IEN_CH3ZCIEN_Pos             (19)                                              /*!< I2S_T::IEN: CH3ZCIEN Position          */
+#define I2S_IEN_CH3ZCIEN_Msk             (0x1ul << I2S_IEN_CH3ZCIEN_Pos)                   /*!< I2S_T::IEN: CH3ZCIEN Mask              */
+
+#define I2S_IEN_CH4ZCIEN_Pos             (20)                                              /*!< I2S_T::IEN: CH4ZCIEN Position          */
+#define I2S_IEN_CH4ZCIEN_Msk             (0x1ul << I2S_IEN_CH4ZCIEN_Pos)                   /*!< I2S_T::IEN: CH4ZCIEN Mask              */
+
+#define I2S_IEN_CH5ZCIEN_Pos             (21)                                              /*!< I2S_T::IEN: CH5ZCIEN Position          */
+#define I2S_IEN_CH5ZCIEN_Msk             (0x1ul << I2S_IEN_CH5ZCIEN_Pos)                   /*!< I2S_T::IEN: CH5ZCIEN Mask              */
+
+#define I2S_IEN_CH6ZCIEN_Pos             (22)                                              /*!< I2S_T::IEN: CH6ZCIEN Position          */
+#define I2S_IEN_CH6ZCIEN_Msk             (0x1ul << I2S_IEN_CH6ZCIEN_Pos)                   /*!< I2S_T::IEN: CH6ZCIEN Mask              */
+
+#define I2S_IEN_CH7ZCIEN_Pos             (23)                                              /*!< I2S_T::IEN: CH7ZCIEN Position          */
+#define I2S_IEN_CH7ZCIEN_Msk             (0x1ul << I2S_IEN_CH7ZCIEN_Pos)                   /*!< I2S_T::IEN: CH7ZCIEN Mask              */
+
+#define I2S_STATUS0_I2SINT_Pos           (0)                                               /*!< I2S_T::STATUS0: I2SINT Position        */
+#define I2S_STATUS0_I2SINT_Msk           (0x1ul << I2S_STATUS0_I2SINT_Pos)                 /*!< I2S_T::STATUS0: I2SINT Mask            */
+
+#define I2S_STATUS0_I2SRXINT_Pos         (1)                                               /*!< I2S_T::STATUS0: I2SRXINT Position      */
+#define I2S_STATUS0_I2SRXINT_Msk         (0x1ul << I2S_STATUS0_I2SRXINT_Pos)               /*!< I2S_T::STATUS0: I2SRXINT Mask          */
+
+#define I2S_STATUS0_I2STXINT_Pos         (2)                                               /*!< I2S_T::STATUS0: I2STXINT Position      */
+#define I2S_STATUS0_I2STXINT_Msk         (0x1ul << I2S_STATUS0_I2STXINT_Pos)               /*!< I2S_T::STATUS0: I2STXINT Mask          */
+
+#define I2S_STATUS0_DATACH_Pos           (3)                                               /*!< I2S_T::STATUS0: DATACH Position        */
+#define I2S_STATUS0_DATACH_Msk           (0x7ul << I2S_STATUS0_DATACH_Pos)                 /*!< I2S_T::STATUS0: DATACH Mask            */
+
+#define I2S_STATUS0_RXUDIF_Pos           (8)                                               /*!< I2S_T::STATUS0: RXUDIF Position        */
+#define I2S_STATUS0_RXUDIF_Msk           (0x1ul << I2S_STATUS0_RXUDIF_Pos)                 /*!< I2S_T::STATUS0: RXUDIF Mask            */
+
+#define I2S_STATUS0_RXOVIF_Pos           (9)                                               /*!< I2S_T::STATUS0: RXOVIF Position        */
+#define I2S_STATUS0_RXOVIF_Msk           (0x1ul << I2S_STATUS0_RXOVIF_Pos)                 /*!< I2S_T::STATUS0: RXOVIF Mask            */
+
+#define I2S_STATUS0_RXTHIF_Pos           (10)                                              /*!< I2S_T::STATUS0: RXTHIF Position        */
+#define I2S_STATUS0_RXTHIF_Msk           (0x1ul << I2S_STATUS0_RXTHIF_Pos)                 /*!< I2S_T::STATUS0: RXTHIF Mask            */
+
+#define I2S_STATUS0_RXFULL_Pos           (11)                                              /*!< I2S_T::STATUS0: RXFULL Position        */
+#define I2S_STATUS0_RXFULL_Msk           (0x1ul << I2S_STATUS0_RXFULL_Pos)                 /*!< I2S_T::STATUS0: RXFULL Mask            */
+
+#define I2S_STATUS0_RXEMPTY_Pos          (12)                                              /*!< I2S_T::STATUS0: RXEMPTY Position       */
+#define I2S_STATUS0_RXEMPTY_Msk          (0x1ul << I2S_STATUS0_RXEMPTY_Pos)                /*!< I2S_T::STATUS0: RXEMPTY Mask           */
+
+#define I2S_STATUS0_TXUDIF_Pos           (16)                                              /*!< I2S_T::STATUS0: TXUDIF Position        */
+#define I2S_STATUS0_TXUDIF_Msk           (0x1ul << I2S_STATUS0_TXUDIF_Pos)                 /*!< I2S_T::STATUS0: TXUDIF Mask            */
+
+#define I2S_STATUS0_TXOVIF_Pos           (17)                                              /*!< I2S_T::STATUS0: TXOVIF Position        */
+#define I2S_STATUS0_TXOVIF_Msk           (0x1ul << I2S_STATUS0_TXOVIF_Pos)                 /*!< I2S_T::STATUS0: TXOVIF Mask            */
+
+#define I2S_STATUS0_TXTHIF_Pos           (18)                                              /*!< I2S_T::STATUS0: TXTHIF Position        */
+#define I2S_STATUS0_TXTHIF_Msk           (0x1ul << I2S_STATUS0_TXTHIF_Pos)                 /*!< I2S_T::STATUS0: TXTHIF Mask            */
+
+#define I2S_STATUS0_TXFULL_Pos           (19)                                              /*!< I2S_T::STATUS0: TXFULL Position        */
+#define I2S_STATUS0_TXFULL_Msk           (0x1ul << I2S_STATUS0_TXFULL_Pos)                 /*!< I2S_T::STATUS0: TXFULL Mask            */
+
+#define I2S_STATUS0_TXEMPTY_Pos          (20)                                              /*!< I2S_T::STATUS0: TXEMPTY Position       */
+#define I2S_STATUS0_TXEMPTY_Msk          (0x1ul << I2S_STATUS0_TXEMPTY_Pos)                /*!< I2S_T::STATUS0: TXEMPTY Mask           */
+
+#define I2S_STATUS0_TXBUSY_Pos           (21)                                              /*!< I2S_T::STATUS0: TXBUSY Position        */
+#define I2S_STATUS0_TXBUSY_Msk           (0x1ul << I2S_STATUS0_TXBUSY_Pos)                 /*!< I2S_T::STATUS0: TXBUSY Mask            */
+
+#define I2S_TXFIFO_TXFIFO_Pos            (0)                                               /*!< I2S_T::TXFIFO: TXFIFO Position         */
+#define I2S_TXFIFO_TXFIFO_Msk            (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)           /*!< I2S_T::TXFIFO: TXFIFO Mask             */
+
+#define I2S_RXFIFO_RXFIFO_Pos            (0)                                               /*!< I2S_T::RXFIFO: RXFIFO Position         */
+#define I2S_RXFIFO_RXFIFO_Msk            (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos)           /*!< I2S_T::RXFIFO: RXFIFO Mask             */
+
+#define I2S_CTL1_CH0ZCEN_Pos             (0)                                               /*!< I2S_T::CTL1: CH0ZCEN Position          */
+#define I2S_CTL1_CH0ZCEN_Msk             (0x1ul << I2S_CTL1_CH0ZCEN_Pos)                   /*!< I2S_T::CTL1: CH0ZCEN Mask              */
+
+#define I2S_CTL1_CH1ZCEN_Pos             (1)                                               /*!< I2S_T::CTL1: CH1ZCEN Position          */
+#define I2S_CTL1_CH1ZCEN_Msk             (0x1ul << I2S_CTL1_CH1ZCEN_Pos)                   /*!< I2S_T::CTL1: CH1ZCEN Mask              */
+
+#define I2S_CTL1_CH2ZCEN_Pos             (2)                                               /*!< I2S_T::CTL1: CH2ZCEN Position          */
+#define I2S_CTL1_CH2ZCEN_Msk             (0x1ul << I2S_CTL1_CH2ZCEN_Pos)                   /*!< I2S_T::CTL1: CH2ZCEN Mask              */
+
+#define I2S_CTL1_CH3ZCEN_Pos             (3)                                               /*!< I2S_T::CTL1: CH3ZCEN Position          */
+#define I2S_CTL1_CH3ZCEN_Msk             (0x1ul << I2S_CTL1_CH3ZCEN_Pos)                   /*!< I2S_T::CTL1: CH3ZCEN Mask              */
+
+#define I2S_CTL1_CH4ZCEN_Pos             (4)                                               /*!< I2S_T::CTL1: CH4ZCEN Position          */
+#define I2S_CTL1_CH4ZCEN_Msk             (0x1ul << I2S_CTL1_CH4ZCEN_Pos)                   /*!< I2S_T::CTL1: CH4ZCEN Mask              */
+
+#define I2S_CTL1_CH5ZCEN_Pos             (5)                                               /*!< I2S_T::CTL1: CH5ZCEN Position          */
+#define I2S_CTL1_CH5ZCEN_Msk             (0x1ul << I2S_CTL1_CH5ZCEN_Pos)                   /*!< I2S_T::CTL1: CH5ZCEN Mask              */
+
+#define I2S_CTL1_CH6ZCEN_Pos             (6)                                               /*!< I2S_T::CTL1: CH6ZCEN Position          */
+#define I2S_CTL1_CH6ZCEN_Msk             (0x1ul << I2S_CTL1_CH6ZCEN_Pos)                   /*!< I2S_T::CTL1: CH6ZCEN Mask              */
+
+#define I2S_CTL1_CH7ZCEN_Pos             (7)                                               /*!< I2S_T::CTL1: CH7ZCEN Position          */
+#define I2S_CTL1_CH7ZCEN_Msk             (0x1ul << I2S_CTL1_CH7ZCEN_Pos)                   /*!< I2S_T::CTL1: CH7ZCEN Mask              */
+
+#define I2S_CTL1_TXTH_Pos                (8)                                               /*!< I2S_T::CTL1: TXTH Position             */
+#define I2S_CTL1_TXTH_Msk                (0xful << I2S_CTL1_TXTH_Pos)                      /*!< I2S_T::CTL1: TXTH Mask                 */
+
+#define I2S_CTL1_RXTH_Pos                (16)                                              /*!< I2S_T::CTL1: RXTH Position             */
+#define I2S_CTL1_RXTH_Msk                (0xful << I2S_CTL1_RXTH_Pos)                      /*!< I2S_T::CTL1: RXTH Mask                 */
+
+#define I2S_CTL1_PBWIDTH_Pos             (24)                                              /*!< I2S_T::CTL1: PBWIDTH Position          */
+#define I2S_CTL1_PBWIDTH_Msk             (0x1ul << I2S_CTL1_PBWIDTH_Pos)                   /*!< I2S_T::CTL1: PBWIDTH Mask              */
+
+#define I2S_CTL1_PB16ORD_Pos             (25)                                              /*!< I2S_T::CTL1: PB16ORD Position          */
+#define I2S_CTL1_PB16ORD_Msk             (0x1ul << I2S_CTL1_PB16ORD_Pos)                   /*!< I2S_T::CTL1: PB16ORD Mask              */
+
+#define I2S_STATUS1_CH0ZCIF_Pos          (0)                                               /*!< I2S_T::STATUS1: CH0ZCIF Position       */
+#define I2S_STATUS1_CH0ZCIF_Msk          (0x1ul << I2S_STATUS1_CH0ZCIF_Pos)                /*!< I2S_T::STATUS1: CH0ZCIF Mask           */
+
+#define I2S_STATUS1_CH1ZCIF_Pos          (1)                                               /*!< I2S_T::STATUS1: CH1ZCIF Position       */
+#define I2S_STATUS1_CH1ZCIF_Msk          (0x1ul << I2S_STATUS1_CH1ZCIF_Pos)                /*!< I2S_T::STATUS1: CH1ZCIF Mask           */
+
+#define I2S_STATUS1_CH2ZCIF_Pos          (2)                                               /*!< I2S_T::STATUS1: CH2ZCIF Position       */
+#define I2S_STATUS1_CH2ZCIF_Msk          (0x1ul << I2S_STATUS1_CH2ZCIF_Pos)                /*!< I2S_T::STATUS1: CH2ZCIF Mask           */
+
+#define I2S_STATUS1_CH3ZCIF_Pos          (3)                                               /*!< I2S_T::STATUS1: CH3ZCIF Position       */
+#define I2S_STATUS1_CH3ZCIF_Msk          (0x1ul << I2S_STATUS1_CH3ZCIF_Pos)                /*!< I2S_T::STATUS1: CH3ZCIF Mask           */
+
+#define I2S_STATUS1_CH4ZCIF_Pos          (4)                                               /*!< I2S_T::STATUS1: CH4ZCIF Position       */
+#define I2S_STATUS1_CH4ZCIF_Msk          (0x1ul << I2S_STATUS1_CH4ZCIF_Pos)                /*!< I2S_T::STATUS1: CH4ZCIF Mask           */
+
+#define I2S_STATUS1_CH5ZCIF_Pos          (5)                                               /*!< I2S_T::STATUS1: CH5ZCIF Position       */
+#define I2S_STATUS1_CH5ZCIF_Msk          (0x1ul << I2S_STATUS1_CH5ZCIF_Pos)                /*!< I2S_T::STATUS1: CH5ZCIF Mask           */
+
+#define I2S_STATUS1_CH6ZCIF_Pos          (6)                                               /*!< I2S_T::STATUS1: CH6ZCIF Position       */
+#define I2S_STATUS1_CH6ZCIF_Msk          (0x1ul << I2S_STATUS1_CH6ZCIF_Pos)                /*!< I2S_T::STATUS1: CH6ZCIF Mask           */
+
+#define I2S_STATUS1_CH7ZCIF_Pos          (7)                                               /*!< I2S_T::STATUS1: CH7ZCIF Position       */
+#define I2S_STATUS1_CH7ZCIF_Msk          (0x1ul << I2S_STATUS1_CH7ZCIF_Pos)                /*!< I2S_T::STATUS1: CH7ZCIF Mask           */
+
+#define I2S_STATUS1_TXCNT_Pos            (8)                                               /*!< I2S_T::STATUS1: TXCNT Position         */
+#define I2S_STATUS1_TXCNT_Msk            (0x1ful << I2S_STATUS1_TXCNT_Pos)                 /*!< I2S_T::STATUS1: TXCNT Mask             */
+
+#define I2S_STATUS1_RXCNT_Pos            (16)                                              /*!< I2S_T::STATUS1: RXCNT Position         */
+#define I2S_STATUS1_RXCNT_Msk            (0x1ful << I2S_STATUS1_RXCNT_Pos)                 /*!< I2S_T::STATUS1: RXCNT Mask             */
+
+/**@}*/ /* I2S_CONST */
+/**@}*/ /* end of I2S register group */
+
+
+
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/
+/**
+    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+    Memory Mapped Structure for SPI Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var SPI_T::CTL
+     * Offset: 0x00  SPI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPIEN     |SPI Transfer Control Enable Bit
+     * |        |          |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
+     * |        |          |In Slave mode, this device is ready to receive data when this bit is set to 1.
+     * |        |          |0 = Transfer control Disabled.
+     * |        |          |1 = Transfer control Enabled.
+     * |        |          |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
+     * |[1]     |RXNEG     |Receive on Negative Edge
+     * |        |          |0 = Received data input signal is latched on the rising edge of SPI bus clock.
+     * |        |          |1 = Received data input signal is latched on the falling edge of SPI bus clock.
+     * |[2]     |TXNEG     |Transmit on Negative Edge
+     * |        |          |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
+     * |        |          |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
+     * |[3]     |CLKPOL    |Clock Polarity
+     * |        |          |0 = SPI bus clock is idle low.
+     * |        |          |1 = SPI bus clock is idle high.
+     * |[7:4]   |SUSPITV   |Suspend Interval (Master Only)
+     * |        |          |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
+     * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+     * |        |          |The default value is 0x3
+     * |        |          |The period of the suspend interval is obtained according to the following equation.
+     * |        |          |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
+     * |        |          |Example:
+     * |        |          |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
+     * |        |          |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
+     * |        |          |.....
+     * |        |          |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
+     * |        |          |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
+     * |[12:8]  |DWIDTH    |Data Width
+     * |        |          |This field specifies how many bits can be transmitted / received in one transaction
+     * |        |          |The minimum bit length is 8 bits and can up to 32 bits.
+     * |        |          |DWIDTH = 0x08 .... 8 bits.
+     * |        |          |DWIDTH = 0x09 .... 9 bits.
+     * |        |          |.....
+     * |        |          |DWIDTH = 0x1F .... 31 bits.
+     * |        |          |DWIDTH = 0x00 .... 32 bits.
+     * |        |          |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
+     * |        |          |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4.
+     * |[13]    |LSB       |Send LSB First
+     * |        |          |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
+     * |[14]    |HALFDPX   |SPI Half-duplex Transfer Enable Bit
+     * |        |          |This bit is used to select full-duplex or half-duplex for SPI transfer
+     * |        |          |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
+     * |        |          |0 = SPI operates in full-duplex transfer.
+     * |        |          |1 = SPI operates in half-duplex transfer.
+     * |[15]    |RXONLY    |Receive-only Mode Enable Bit (Master Only)
+     * |        |          |This bit field is only available in Master mode
+     * |        |          |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
+     * |        |          |0 = Receive-only mode Disabled.
+     * |        |          |1 = Receive-only mode Enabled.
+     * |[16]    |TWOBIT    |2-bit Transfer Mode Enable Bit (Only Supported in SPI0)
+     * |        |          |0 = 2-Bit Transfer mode Disabled.
+     * |        |          |1 = 2-Bit Transfer mode Enabled.
+     * |        |          |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
+     * |        |          |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
+     * |[17]    |UNITIEN   |Unit Transfer Interrupt Enable Bit
+     * |        |          |0 = SPI unit transfer interrupt Disabled.
+     * |        |          |1 = SPI unit transfer interrupt Enabled.
+     * |[18]    |SLAVE     |Slave Mode Control
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[19]    |REORDER   |Byte Reorder Function Enable Bit
+     * |        |          |0 = Byte Reorder function Disabled.
+     * |        |          |1 = Byte Reorder function Enabled
+     * |        |          |A byte suspend interval will be inserted among each byte
+     * |        |          |The period of the byte suspend interval depends on the setting of SUSPITV.
+     * |        |          |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+     * |[20]    |DATDIR    |Data Port Direction Control
+     * |        |          |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
+     * |        |          |0 = SPI data is input direction.
+     * |        |          |1 = SPI data is output direction.
+     * |[21]    |DUALIOEN  |Dual I/O Mode Enable Bit (Only Supported in SPI0)
+     * |        |          |0 = Dual I/O mode Disabled.
+     * |        |          |1 = Dual I/O mode Enabled.
+     * |[22]    |QUADIOEN  |Quad I/O Mode Enable Bit (Only Supported in SPI0)
+     * |        |          |0 = Quad I/O mode Disabled.
+     * |        |          |1 = Quad I/O mode Enabled.
+     * @var SPI_T::CLKDIV
+     * Offset: 0x04  SPI Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |DIVIDER   |Clock Divider
+     * |        |          |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
+     * |        |          |The frequency is obtained according to the following equation.
+     * |        |          |where
+     * |        |          |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
+     * |        |          |Note: Not supported in I2S mode.
+     * @var SPI_T::SSCTL
+     * Offset: 0x08  SPI Slave Select Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SS        |Slave Selection Control (Master Only)
+     * |        |          |If AUTOSS bit is cleared to 0,
+     * |        |          |0 = set the SPIx_SS line to inactive state.
+     * |        |          |1 = set the SPIx_SS line to active state.
+     * |        |          |If the AUTOSS bit is set to 1,
+     * |        |          |0 = Keep the SPIx_SS line at inactive state.
+     * |        |          |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
+     * |        |          |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
+     * |[2]     |SSACTPOL  |Slave Selection Active Polarity
+     * |        |          |This bit defines the active polarity of slave selection signal (SPIx_SS).
+     * |        |          |0 = The slave selection signal SPIx_SS is active low.
+     * |        |          |1 = The slave selection signal SPIx_SS is active high.
+     * |[3]     |AUTOSS    |Automatic Slave Selection Function Enable Bit (Master Only)
+     * |        |          |0 = Automatic slave selection function Disabled
+     * |        |          |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
+     * |        |          |1 = Automatic slave selection function Enabled.
+     * |[4]     |SLV3WIRE  |Slave 3-wire Mode Enable Bit (Only Supported in SPI0)
+     * |        |          |Slave 3-wire mode is only available in SPI0
+     * |        |          |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins.
+     * |        |          |0 = 4-wire bi-direction interface.
+     * |        |          |1 = 3-wire bi-direction interface.
+     * |[5]     |SLVTOIEN  |Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)
+     * |        |          |0 = Slave mode time-out interrupt Disabled.
+     * |        |          |1 = Slave mode time-out interrupt Enabled.
+     * |[6]     |SLVTORST  |Slave Mode Time-out Reset Control (Only Supported in SPI0)
+     * |        |          |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
+     * |        |          |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
+     * |[8]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Bit
+     * |        |          |0 = Slave mode bit count error interrupt Disabled.
+     * |        |          |1 = Slave mode bit count error interrupt Enabled.
+     * |[9]     |SLVURIEN  |Slave Mode TX Under Run Interrupt Enable Bit
+     * |        |          |0 = Slave mode TX under run interrupt Disabled.
+     * |        |          |1 = Slave mode TX under run interrupt Enabled.
+     * |[12]    |SSACTIEN  |Slave Select Active Interrupt Enable Bit
+     * |        |          |0 = Slave select active interrupt Disabled.
+     * |        |          |1 = Slave select active interrupt Enabled.
+     * |[13]    |SSINAIEN  |Slave Select Inactive Interrupt Enable Bit
+     * |        |          |0 = Slave select inactive interrupt Disabled.
+     * |        |          |1 = Slave select inactive interrupt Enabled.
+     * |[31:16] |SLVTOCNT  |Slave Mode Time-out Period (Only Supported in SPI0)
+     * |        |          |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
+     * |        |          |The clock source of the time-out counter is Slave peripheral clock
+     * |        |          |If the value is 0, it indicates the slave mode time-out function is disabled.
+     * @var SPI_T::PDMACTL
+     * Offset: 0x0C  SPI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXPDMAEN  |Transmit PDMA Enable Bit
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |        |          |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
+     * |        |          |User can enable TX PDMA function firstly or enable both functions simultaneously.
+     * |[1]     |RXPDMAEN  |Receive PDMA Enable Bit
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[2]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
+     * @var SPI_T::FIFOCTL
+     * Offset: 0x10  SPI FIFO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset receive FIFO pointer and receive circuit
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |[1]     |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset transmit FIFO pointer and transmit circuit
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |        |          |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
+     * |[2]     |RXTHIEN   |Receive FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = RX FIFO threshold interrupt Disabled.
+     * |        |          |1 = RX FIFO threshold interrupt Enabled.
+     * |[3]     |TXTHIEN   |Transmit FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = TX FIFO threshold interrupt Disabled.
+     * |        |          |1 = TX FIFO threshold interrupt Enabled.
+     * |[4]     |RXTOIEN   |Slave Receive Time-out Interrupt Enable Bit
+     * |        |          |0 = Receive time-out interrupt Disabled.
+     * |        |          |1 = Receive time-out interrupt Enabled.
+     * |[5]     |RXOVIEN   |Receive FIFO Overrun Interrupt Enable Bit
+     * |        |          |0 = Receive FIFO overrun interrupt Disabled.
+     * |        |          |1 = Receive FIFO overrun interrupt Enabled.
+     * |[6]     |TXUFPOL   |TX Underflow Data Polarity
+     * |        |          |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
+     * |        |          |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
+     * |        |          |Note:
+     * |        |          |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
+     * |        |          |2. This bit should be set as 0 in I2S mode.
+     * |        |          |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
+     * |        |          |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
+     * |[7]     |TXUFIEN   |TX Underflow Interrupt Enable Bit
+     * |        |          |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
+     * |        |          |This bit is used to enable the TX underflow interrupt.
+     * |        |          |0 = Slave TX underflow interrupt Disabled.
+     * |        |          |1 = Slave TX underflow interrupt Enabled.
+     * |[8]     |RXFBCLR   |Receive FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear receive FIFO pointer
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The RX shift register will not be cleared.
+     * |[9]     |TXFBCLR   |Transmit FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear transmit FIFO pointer
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The TX shift register will not be cleared.
+     * |[26:24] |RXTH      |Receive FIFO Threshold
+     * |        |          |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
+     * |        |          |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
+     * |[30:28] |TXTH      |Transmit FIFO Threshold
+     * |        |          |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
+     * |        |          |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length
+     * @var SPI_T::STATUS
+     * Offset: 0x14  SPI Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |Busy Status (Read Only)
+     * |        |          |0 = SPI controller is in idle state.
+     * |        |          |1 = SPI controller is in busy state.
+     * |        |          |The following listing are the bus busy conditions:
+     * |        |          |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
+     * |        |          |b
+     * |        |          |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
+     * |        |          |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
+     * |        |          |d
+     * |        |          |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+     * |        |          |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+     * |[1]     |UNITIF    |Unit Transfer Interrupt Flag
+     * |        |          |0 = No transaction has been finished since this bit was cleared to 0.
+     * |        |          |1 = SPI controller has finished one unit transfer.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[2]     |SSACTIF   |Slave Select Active Interrupt Flag
+     * |        |          |0 = Slave select active interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select active interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[3]     |SSINAIF   |Slave Select Inactive Interrupt Flag
+     * |        |          |0 = Slave select inactive interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select inactive interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[4]     |SSLINE    |Slave Select Line Bus Status (Read Only)
+     * |        |          |0 = The slave select line status is 0.
+     * |        |          |1 = The slave select line status is 1.
+     * |        |          |Note: This bit is only available in Slave mode
+     * |        |          |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
+     * |[5]     |SLVTOIF   |Slave Time-out Interrupt Flag (Only Supported in SPI0)
+     * |        |          |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started
+     * |        |          |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
+     * |        |          |0 = Slave time-out is not active.
+     * |        |          |1 = Slave time-out is active.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[6]     |SLVBEIF   |Slave Mode Bit Count Error Interrupt Flag
+     * |        |          |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave mode bit count error event.
+     * |        |          |1 = Slave mode bit count error event occurs.
+     * |        |          |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
+     * |        |          |This bit will be cleared by writing 1 to it.
+     * |[7]     |SLVURIF   |Slave Mode TX Under Run Interrupt Flag
+     * |        |          |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave TX under run event.
+     * |        |          |1 = Slave TX under run event occurs.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not empty.
+     * |        |          |1 = Receive FIFO buffer is empty.
+     * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not full.
+     * |        |          |1 = Receive FIFO buffer is full.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+     * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+     * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+     * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+     * |        |          |0 = No FIFO is overrun.
+     * |        |          |1 = Receive FIFO is overrun.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[12]    |RXTOIF    |Receive Time-out Interrupt Flag
+     * |        |          |0 = No receive FIFO time-out event.
+     * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
+     * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[15]    |SPIENSTS  |SPI Enable Status (Read Only)
+     * |        |          |0 = The SPI controller is disabled.
+     * |        |          |1 = The SPI controller is enabled.
+     * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock
+     * |        |          |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
+     * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not empty.
+     * |        |          |1 = Transmit FIFO buffer is empty.
+     * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not full.
+     * |        |          |1 = Transmit FIFO buffer is full.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+     * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+     * |[19]    |TXUFIF    |TX Underflow Interrupt Flag
+     * |        |          |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+     * |        |          |0 = No effect.
+     * |        |          |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+     * |        |          |Note 1: This bit will be cleared by writing 1 to it.
+     * |        |          |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+     * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+     * |        |          |0 = The reset function of TXRST or RXRST is done.
+     * |        |          |1 = Doing the reset function of TXRST or RXRST.
+     * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+     * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+     * |[27:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+     * |[31:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+     * @var SPI_T::TX
+     * Offset: 0x20  SPI Data Transmit Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TX        |Data Transmit Register
+     * |        |          |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
+     * |        |          |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
+     * |        |          |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
+     * |        |          |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
+     * |        |          |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
+     * |        |          |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
+     * |        |          |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
+     * @var SPI_T::RX
+     * Offset: 0x30  SPI Data Receive Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RX        |Data Receive Register
+     * |        |          |There are 4-level FIFO buffers in this controller
+     * |        |          |The data receive register holds the data received from SPI data input pin
+     * |        |          |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register
+     * |        |          |This is a read only register.
+     * @var SPI_T::I2SCTL
+     * Offset: 0x60  I2S Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SEN     |I2S Controller Enable Bit
+     * |        |          |0 = Disabled I2S mode.
+     * |        |          |1 = Enabled I2S mode.
+     * |        |          |Note:
+     * |        |          |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
+     * |        |          |2
+     * |        |          |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
+     * |[1]     |TXEN      |Transmit Enable Bit
+     * |        |          |0 = Data transmit Disabled.
+     * |        |          |1 = Data transmit Enabled.
+     * |[2]     |RXEN      |Receive Enable Bit
+     * |        |          |0 = Data receive Disabled.
+     * |        |          |1 = Data receive Enabled.
+     * |[3]     |MUTE      |Transmit Mute Enable Bit
+     * |        |          |0 = Transmit data is shifted from buffer.
+     * |        |          |1 = Transmit channel zero.
+     * |[5:4]   |WDWIDTH   |Word Width
+     * |        |          |00 = data size is 8-bit.
+     * |        |          |01 = data size is 16-bit.
+     * |        |          |10 = data size is 24-bit.
+     * |        |          |11 = data size is 32-bit.
+     * |[6]     |MONO      |Monaural Data
+     * |        |          |0 = Data is stereo format.
+     * |        |          |1 = Data is monaural format.
+     * |[7]     |ORDER     |Stereo Data Order in FIFO
+     * |        |          |0 = Left channel data at high byte.
+     * |        |          |1 = Left channel data at low byte.
+     * |[8]     |SLAVE     |Slave Mode
+     * |        |          |I2S can operate as master or slave
+     * |        |          |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip
+     * |        |          |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[15]    |MCLKEN    |Master Clock Enable Bit
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
+     * |        |          |0 = Master clock Disabled.
+     * |        |          |1 = Master clock Enabled.
+     * |[16]    |RZCEN     |Right Channel Zero Cross Detection Enable Bit
+     * |        |          |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
+     * |        |          |This function is only available in transmit operation.
+     * |        |          |0 = Right channel zero cross detection Disabled.
+     * |        |          |1 = Right channel zero cross detection Enabled.
+     * |[17]    |LZCEN     |Left Channel Zero Cross Detection Enable Bit
+     * |        |          |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
+     * |        |          |This function is only available in transmit operation.
+     * |        |          |0 = Left channel zero cross detection Disabled.
+     * |        |          |1 = Left channel zero cross detection Enabled.
+     * |[23]    |RXLCH     |Receive Left Channel Enable Bit
+     * |        |          |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+     * |        |          |0 = Receive right channel data in Mono mode.
+     * |        |          |1 = Receive left channel data in Mono mode.
+     * |[24]    |RZCIEN    |Right Channel Zero Cross Interrupt Enable Bit
+     * |        |          |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[25]    |LZCIEN    |Left Channel Zero Cross Interrupt Enable Bit
+     * |        |          |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[29:28] |FORMAT    |Data Format Selection
+     * |        |          |00 = I2S data format.
+     * |        |          |01 = MSB justified data format.
+     * |        |          |10 = PCM mode A.
+     * |        |          |11 = PCM mode B.
+     * @var SPI_T::I2SCLK
+     * Offset: 0x64  I2S Clock Divider Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |MCLKDIV   |Master Clock Divider
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
+     * |        |          |The frequency of master clock, fMCLK, is determined by the following expressions:
+     * |        |          |If MCLKDIV >= 1,.
+     * |        |          |If MCLKDIV = 0,.
+     * |        |          |where
+     * |        |          |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2
+     * |        |          |In general, the master clock rate is 256 times sampling clock rate.
+     * |[17:8]  |BCLKDIV   |Bit Clock Divider
+     * |        |          |The I2S controller will generate bit clock in Master mode
+     * |        |          |The clock frequency of bit clock , fBCLK, is determined by the following expression:
+     * |        |          |where
+     * |        |          |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+     * |        |          |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
+     * |        |          |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
+     * @var SPI_T::I2SSTS
+     * Offset: 0x68  I2S Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4]     |RIGHT     |Right Channel (Read Only)
+     * |        |          |This bit indicates the current transmit data is belong to which channel.
+     * |        |          |0 = Left channel.
+     * |        |          |1 = Right channel.
+     * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not empty.
+     * |        |          |1 = Receive FIFO buffer is empty.
+     * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not full.
+     * |        |          |1 = Receive FIFO buffer is full.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+     * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+     * |        |          |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+     * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+     * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[12]    |RXTOIF    |Receive Time-out Interrupt Flag
+     * |        |          |0 = No receive FIFO time-out event.
+     * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
+     * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[15]    |I2SENSTS  |I2S Enable Status (Read Only)
+     * |        |          |0 = The SPI/I2S control logic is disabled.
+     * |        |          |1 = The SPI/I2S control logic is enabled.
+     * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock
+     * |        |          |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
+     * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not empty.
+     * |        |          |1 = Transmit FIFO buffer is empty.
+     * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not full.
+     * |        |          |1 = Transmit FIFO buffer is full.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+     * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+     * |        |          |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+     * |[19]    |TXUFIF    |Transmit FIFO Underflow Interrupt Flag
+     * |        |          |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[20]    |RZCIF     |Right Channel Zero Cross Interrupt Flag
+     * |        |          |0 = No zero cross event occurred on right channel.
+     * |        |          |1 = Zero cross event occurred on right channel.
+     * |[21]    |LZCIF     |Left Channel Zero Cross Interrupt Flag
+     * |        |          |0 = No zero cross event occurred on left channel.
+     * |        |          |1 = Zero cross event occurred on left channel.
+     * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+     * |        |          |0 = The reset function of TXRST or RXRST is done.
+     * |        |          |1 = Doing the reset function of TXRST or RXRST.
+     * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+     * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+     * |[26:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+     * |[30:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] SPI Control Register                                             */
+    __IO uint32_t CLKDIV;                /*!< [0x0004] SPI Clock Divider Register                                       */
+    __IO uint32_t SSCTL;                 /*!< [0x0008] SPI Slave Select Control Register                                */
+    __IO uint32_t PDMACTL;               /*!< [0x000c] SPI PDMA Control Register                                        */
+    __IO uint32_t FIFOCTL;               /*!< [0x0010] SPI FIFO Control Register                                        */
+    __IO uint32_t STATUS;                /*!< [0x0014] SPI Status Register                                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __O  uint32_t TX;                    /*!< [0x0020] SPI Data Transmit Register                                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t RX;                    /*!< [0x0030] SPI Data Receive Register                                        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[11];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t I2SCTL;                /*!< [0x0060] I2S Control Register                                             */
+    __IO uint32_t I2SCLK;                /*!< [0x0064] I2S Clock Divider Control Register                               */
+    __IO uint32_t I2SSTS;                /*!< [0x0068] I2S Status Register                                              */
+
+} SPI_T;
+
+/**
+    @addtogroup SPI_CONST SPI Bit Field Definition
+    Constant Definitions for SPI Controller
+@{ */
+
+#define SPI_CTL_SPIEN_Pos                (0)                                               /*!< SPI_T::CTL: SPIEN Position             */
+#define SPI_CTL_SPIEN_Msk                (0x1ul << SPI_CTL_SPIEN_Pos)                      /*!< SPI_T::CTL: SPIEN Mask                 */
+
+#define SPI_CTL_RXNEG_Pos                (1)                                               /*!< SPI_T::CTL: RXNEG Position             */
+#define SPI_CTL_RXNEG_Msk                (0x1ul << SPI_CTL_RXNEG_Pos)                      /*!< SPI_T::CTL: RXNEG Mask                 */
+
+#define SPI_CTL_TXNEG_Pos                (2)                                               /*!< SPI_T::CTL: TXNEG Position             */
+#define SPI_CTL_TXNEG_Msk                (0x1ul << SPI_CTL_TXNEG_Pos)                      /*!< SPI_T::CTL: TXNEG Mask                 */
+
+#define SPI_CTL_CLKPOL_Pos               (3)                                               /*!< SPI_T::CTL: CLKPOL Position            */
+#define SPI_CTL_CLKPOL_Msk               (0x1ul << SPI_CTL_CLKPOL_Pos)                     /*!< SPI_T::CTL: CLKPOL Mask                */
+
+#define SPI_CTL_SUSPITV_Pos              (4)                                               /*!< SPI_T::CTL: SUSPITV Position           */
+#define SPI_CTL_SUSPITV_Msk              (0xful << SPI_CTL_SUSPITV_Pos)                    /*!< SPI_T::CTL: SUSPITV Mask               */
+
+#define SPI_CTL_DWIDTH_Pos               (8)                                               /*!< SPI_T::CTL: DWIDTH Position            */
+#define SPI_CTL_DWIDTH_Msk               (0x1ful << SPI_CTL_DWIDTH_Pos)                    /*!< SPI_T::CTL: DWIDTH Mask                */
+
+#define SPI_CTL_LSB_Pos                  (13)                                              /*!< SPI_T::CTL: LSB Position               */
+#define SPI_CTL_LSB_Msk                  (0x1ul << SPI_CTL_LSB_Pos)                        /*!< SPI_T::CTL: LSB Mask                   */
+
+#define SPI_CTL_HALFDPX_Pos              (14)                                              /*!< SPI_T::CTL: HALFDPX Position           */
+#define SPI_CTL_HALFDPX_Msk              (0x1ul << SPI_CTL_HALFDPX_Pos)                    /*!< SPI_T::CTL: HALFDPX Mask               */
+
+#define SPI_CTL_RXONLY_Pos               (15)                                              /*!< SPI_T::CTL: RXONLY Position            */
+#define SPI_CTL_RXONLY_Msk               (0x1ul << SPI_CTL_RXONLY_Pos)                     /*!< SPI_T::CTL: RXONLY Mask                */
+
+#define SPI_CTL_TWOBIT_Pos               (16)                                              /*!< SPI_T::CTL: TWOBIT Position            */
+#define SPI_CTL_TWOBIT_Msk               (0x1ul << SPI_CTL_TWOBIT_Pos)                     /*!< SPI_T::CTL: TWOBIT Mask                */
+
+#define SPI_CTL_UNITIEN_Pos              (17)                                              /*!< SPI_T::CTL: UNITIEN Position           */
+#define SPI_CTL_UNITIEN_Msk              (0x1ul << SPI_CTL_UNITIEN_Pos)                    /*!< SPI_T::CTL: UNITIEN Mask               */
+
+#define SPI_CTL_SLAVE_Pos                (18)                                              /*!< SPI_T::CTL: SLAVE Position             */
+#define SPI_CTL_SLAVE_Msk                (0x1ul << SPI_CTL_SLAVE_Pos)                      /*!< SPI_T::CTL: SLAVE Mask                 */
+
+#define SPI_CTL_REORDER_Pos              (19)                                              /*!< SPI_T::CTL: REORDER Position           */
+#define SPI_CTL_REORDER_Msk              (0x1ul << SPI_CTL_REORDER_Pos)                    /*!< SPI_T::CTL: REORDER Mask               */
+
+#define SPI_CTL_DATDIR_Pos               (20)                                              /*!< SPI_T::CTL: DATDIR Position            */
+#define SPI_CTL_DATDIR_Msk               (0x1ul << SPI_CTL_DATDIR_Pos)                     /*!< SPI_T::CTL: DATDIR Mask                */
+
+#define SPI_CTL_DUALIOEN_Pos             (21)                                              /*!< SPI_T::CTL: DUALIOEN Position          */
+#define SPI_CTL_DUALIOEN_Msk             (0x1ul << SPI_CTL_DUALIOEN_Pos)                   /*!< SPI_T::CTL: DUALIOEN Mask              */
+
+#define SPI_CTL_QUADIOEN_Pos             (22)                                              /*!< SPI_T::CTL: QUADIOEN Position          */
+#define SPI_CTL_QUADIOEN_Msk             (0x1ul << SPI_CTL_QUADIOEN_Pos)                   /*!< SPI_T::CTL: QUADIOEN Mask              */
+
+#define SPI_CLKDIV_DIVIDER_Pos           (0)                                               /*!< SPI_T::CLKDIV: DIVIDER Position        */
+#define SPI_CLKDIV_DIVIDER_Msk           (0x1fful << SPI_CLKDIV_DIVIDER_Pos)               /*!< SPI_T::CLKDIV: DIVIDER Mask            */
+
+#define SPI_SSCTL_SS_Pos                 (0)                                               /*!< SPI_T::SSCTL: SS Position              */
+#define SPI_SSCTL_SS_Msk                 (0x1ul << SPI_SSCTL_SS_Pos)                       /*!< SPI_T::SSCTL: SS Mask                  */
+
+#define SPI_SSCTL_SSACTPOL_Pos           (2)                                               /*!< SPI_T::SSCTL: SSACTPOL Position        */
+#define SPI_SSCTL_SSACTPOL_Msk           (0x1ul << SPI_SSCTL_SSACTPOL_Pos)                 /*!< SPI_T::SSCTL: SSACTPOL Mask            */
+
+#define SPI_SSCTL_AUTOSS_Pos             (3)                                               /*!< SPI_T::SSCTL: AUTOSS Position          */
+#define SPI_SSCTL_AUTOSS_Msk             (0x1ul << SPI_SSCTL_AUTOSS_Pos)                   /*!< SPI_T::SSCTL: AUTOSS Mask              */
+
+#define SPI_SSCTL_SLV3WIRE_Pos           (4)                                               /*!< SPI_T::SSCTL: SLV3WIRE Position        */
+#define SPI_SSCTL_SLV3WIRE_Msk           (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)                 /*!< SPI_T::SSCTL: SLV3WIRE Mask            */
+
+#define SPI_SSCTL_SLVTOIEN_Pos           (5)                                               /*!< SPI_T::SSCTL: SLVTOIEN Position        */
+#define SPI_SSCTL_SLVTOIEN_Msk           (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)                 /*!< SPI_T::SSCTL: SLVTOIEN Mask            */
+
+#define SPI_SSCTL_SLVTORST_Pos           (6)                                               /*!< SPI_T::SSCTL: SLVTORST Position        */
+#define SPI_SSCTL_SLVTORST_Msk           (0x1ul << SPI_SSCTL_SLVTORST_Pos)                 /*!< SPI_T::SSCTL: SLVTORST Mask            */
+
+#define SPI_SSCTL_SLVBEIEN_Pos           (8)                                               /*!< SPI_T::SSCTL: SLVBEIEN Position        */
+#define SPI_SSCTL_SLVBEIEN_Msk           (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)                 /*!< SPI_T::SSCTL: SLVBEIEN Mask            */
+
+#define SPI_SSCTL_SLVURIEN_Pos           (9)                                               /*!< SPI_T::SSCTL: SLVURIEN Position        */
+#define SPI_SSCTL_SLVURIEN_Msk           (0x1ul << SPI_SSCTL_SLVURIEN_Pos)                 /*!< SPI_T::SSCTL: SLVURIEN Mask            */
+
+#define SPI_SSCTL_SSACTIEN_Pos           (12)                                              /*!< SPI_T::SSCTL: SSACTIEN Position        */
+#define SPI_SSCTL_SSACTIEN_Msk           (0x1ul << SPI_SSCTL_SSACTIEN_Pos)                 /*!< SPI_T::SSCTL: SSACTIEN Mask            */
+
+#define SPI_SSCTL_SSINAIEN_Pos           (13)                                              /*!< SPI_T::SSCTL: SSINAIEN Position        */
+#define SPI_SSCTL_SSINAIEN_Msk           (0x1ul << SPI_SSCTL_SSINAIEN_Pos)                 /*!< SPI_T::SSCTL: SSINAIEN Mask            */
+
+#define SPI_SSCTL_SLVTOCNT_Pos           (16)                                              /*!< SPI_T::SSCTL: SLVTOCNT Position        */
+#define SPI_SSCTL_SLVTOCNT_Msk           (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)              /*!< SPI_T::SSCTL: SLVTOCNT Mask            */
+
+#define SPI_PDMACTL_TXPDMAEN_Pos         (0)                                               /*!< SPI_T::PDMACTL: TXPDMAEN Position      */
+#define SPI_PDMACTL_TXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: TXPDMAEN Mask          */
+
+#define SPI_PDMACTL_RXPDMAEN_Pos         (1)                                               /*!< SPI_T::PDMACTL: RXPDMAEN Position      */
+#define SPI_PDMACTL_RXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: RXPDMAEN Mask          */
+
+#define SPI_PDMACTL_PDMARST_Pos          (2)                                               /*!< SPI_T::PDMACTL: PDMARST Position       */
+#define SPI_PDMACTL_PDMARST_Msk          (0x1ul << SPI_PDMACTL_PDMARST_Pos)                /*!< SPI_T::PDMACTL: PDMARST Mask           */
+
+#define SPI_FIFOCTL_RXRST_Pos            (0)                                               /*!< SPI_T::FIFOCTL: RXRST Position         */
+#define SPI_FIFOCTL_RXRST_Msk            (0x1ul << SPI_FIFOCTL_RXRST_Pos)                  /*!< SPI_T::FIFOCTL: RXRST Mask             */
+
+#define SPI_FIFOCTL_TXRST_Pos            (1)                                               /*!< SPI_T::FIFOCTL: TXRST Position         */
+#define SPI_FIFOCTL_TXRST_Msk            (0x1ul << SPI_FIFOCTL_TXRST_Pos)                  /*!< SPI_T::FIFOCTL: TXRST Mask             */
+
+#define SPI_FIFOCTL_RXTHIEN_Pos          (2)                                               /*!< SPI_T::FIFOCTL: RXTHIEN Position       */
+#define SPI_FIFOCTL_RXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTHIEN Mask           */
+
+#define SPI_FIFOCTL_TXTHIEN_Pos          (3)                                               /*!< SPI_T::FIFOCTL: TXTHIEN Position       */
+#define SPI_FIFOCTL_TXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: TXTHIEN Mask           */
+
+#define SPI_FIFOCTL_RXTOIEN_Pos          (4)                                               /*!< SPI_T::FIFOCTL: RXTOIEN Position       */
+#define SPI_FIFOCTL_RXTOIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTOIEN Mask           */
+
+#define SPI_FIFOCTL_RXOVIEN_Pos          (5)                                               /*!< SPI_T::FIFOCTL: RXOVIEN Position       */
+#define SPI_FIFOCTL_RXOVIEN_Msk          (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)                /*!< SPI_T::FIFOCTL: RXOVIEN Mask           */
+
+#define SPI_FIFOCTL_TXUFPOL_Pos          (6)                                               /*!< SPI_T::FIFOCTL: TXUFPOL Position       */
+#define SPI_FIFOCTL_TXUFPOL_Msk          (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)                /*!< SPI_T::FIFOCTL: TXUFPOL Mask           */
+
+#define SPI_FIFOCTL_TXUFIEN_Pos          (7)                                               /*!< SPI_T::FIFOCTL: TXUFIEN Position       */
+#define SPI_FIFOCTL_TXUFIEN_Msk          (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)                /*!< SPI_T::FIFOCTL: TXUFIEN Mask           */
+
+#define SPI_FIFOCTL_RXFBCLR_Pos          (8)                                               /*!< SPI_T::FIFOCTL: RXFBCLR Position       */
+#define SPI_FIFOCTL_RXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: RXFBCLR Mask           */
+
+#define SPI_FIFOCTL_TXFBCLR_Pos          (9)                                               /*!< SPI_T::FIFOCTL: TXFBCLR Position       */
+#define SPI_FIFOCTL_TXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: TXFBCLR Mask           */
+
+#define SPI_FIFOCTL_RXTH_Pos             (24)                                              /*!< SPI_T::FIFOCTL: RXTH Position          */
+#define SPI_FIFOCTL_RXTH_Msk             (0x7ul << SPI_FIFOCTL_RXTH_Pos)                   /*!< SPI_T::FIFOCTL: RXTH Mask              */
+
+#define SPI_FIFOCTL_TXTH_Pos             (28)                                              /*!< SPI_T::FIFOCTL: TXTH Position          */
+#define SPI_FIFOCTL_TXTH_Msk             (0x7ul << SPI_FIFOCTL_TXTH_Pos)                   /*!< SPI_T::FIFOCTL: TXTH Mask              */
+
+#define SPI_STATUS_BUSY_Pos              (0)                                               /*!< SPI_T::STATUS: BUSY Position           */
+#define SPI_STATUS_BUSY_Msk              (0x1ul << SPI_STATUS_BUSY_Pos)                    /*!< SPI_T::STATUS: BUSY Mask               */
+
+#define SPI_STATUS_UNITIF_Pos            (1)                                               /*!< SPI_T::STATUS: UNITIF Position         */
+#define SPI_STATUS_UNITIF_Msk            (0x1ul << SPI_STATUS_UNITIF_Pos)                  /*!< SPI_T::STATUS: UNITIF Mask             */
+
+#define SPI_STATUS_SSACTIF_Pos           (2)                                               /*!< SPI_T::STATUS: SSACTIF Position        */
+#define SPI_STATUS_SSACTIF_Msk           (0x1ul << SPI_STATUS_SSACTIF_Pos)                 /*!< SPI_T::STATUS: SSACTIF Mask            */
+
+#define SPI_STATUS_SSINAIF_Pos           (3)                                               /*!< SPI_T::STATUS: SSINAIF Position        */
+#define SPI_STATUS_SSINAIF_Msk           (0x1ul << SPI_STATUS_SSINAIF_Pos)                 /*!< SPI_T::STATUS: SSINAIF Mask            */
+
+#define SPI_STATUS_SSLINE_Pos            (4)                                               /*!< SPI_T::STATUS: SSLINE Position         */
+#define SPI_STATUS_SSLINE_Msk            (0x1ul << SPI_STATUS_SSLINE_Pos)                  /*!< SPI_T::STATUS: SSLINE Mask             */
+
+#define SPI_STATUS_SLVTOIF_Pos           (5)                                               /*!< SPI_T::STATUS: SLVTOIF Position        */
+#define SPI_STATUS_SLVTOIF_Msk           (0x1ul << SPI_STATUS_SLVTOIF_Pos)                 /*!< SPI_T::STATUS: SLVTOIF Mask            */
+
+#define SPI_STATUS_SLVBEIF_Pos           (6)                                               /*!< SPI_T::STATUS: SLVBEIF Position        */
+#define SPI_STATUS_SLVBEIF_Msk           (0x1ul << SPI_STATUS_SLVBEIF_Pos)                 /*!< SPI_T::STATUS: SLVBEIF Mask            */
+
+#define SPI_STATUS_SLVURIF_Pos           (7)                                               /*!< SPI_T::STATUS: SLVURIF Position        */
+#define SPI_STATUS_SLVURIF_Msk           (0x1ul << SPI_STATUS_SLVURIF_Pos)                 /*!< SPI_T::STATUS: SLVURIF Mask            */
+
+#define SPI_STATUS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::STATUS: RXEMPTY Position        */
+#define SPI_STATUS_RXEMPTY_Msk           (0x1ul << SPI_STATUS_RXEMPTY_Pos)                 /*!< SPI_T::STATUS: RXEMPTY Mask            */
+
+#define SPI_STATUS_RXFULL_Pos            (9)                                               /*!< SPI_T::STATUS: RXFULL Position         */
+#define SPI_STATUS_RXFULL_Msk            (0x1ul << SPI_STATUS_RXFULL_Pos)                  /*!< SPI_T::STATUS: RXFULL Mask             */
+
+#define SPI_STATUS_RXTHIF_Pos            (10)                                              /*!< SPI_T::STATUS: RXTHIF Position         */
+#define SPI_STATUS_RXTHIF_Msk            (0x1ul << SPI_STATUS_RXTHIF_Pos)                  /*!< SPI_T::STATUS: RXTHIF Mask             */
+
+#define SPI_STATUS_RXOVIF_Pos            (11)                                              /*!< SPI_T::STATUS: RXOVIF Position         */
+#define SPI_STATUS_RXOVIF_Msk            (0x1ul << SPI_STATUS_RXOVIF_Pos)                  /*!< SPI_T::STATUS: RXOVIF Mask             */
+
+#define SPI_STATUS_RXTOIF_Pos            (12)                                              /*!< SPI_T::STATUS: RXTOIF Position         */
+#define SPI_STATUS_RXTOIF_Msk            (0x1ul << SPI_STATUS_RXTOIF_Pos)                  /*!< SPI_T::STATUS: RXTOIF Mask             */
+
+#define SPI_STATUS_SPIENSTS_Pos          (15)                                              /*!< SPI_T::STATUS: SPIENSTS Position       */
+#define SPI_STATUS_SPIENSTS_Msk          (0x1ul << SPI_STATUS_SPIENSTS_Pos)                /*!< SPI_T::STATUS: SPIENSTS Mask           */
+
+#define SPI_STATUS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::STATUS: TXEMPTY Position        */
+#define SPI_STATUS_TXEMPTY_Msk           (0x1ul << SPI_STATUS_TXEMPTY_Pos)                 /*!< SPI_T::STATUS: TXEMPTY Mask            */
+
+#define SPI_STATUS_TXFULL_Pos            (17)                                              /*!< SPI_T::STATUS: TXFULL Position         */
+#define SPI_STATUS_TXFULL_Msk            (0x1ul << SPI_STATUS_TXFULL_Pos)                  /*!< SPI_T::STATUS: TXFULL Mask             */
+
+#define SPI_STATUS_TXTHIF_Pos            (18)                                              /*!< SPI_T::STATUS: TXTHIF Position         */
+#define SPI_STATUS_TXTHIF_Msk            (0x1ul << SPI_STATUS_TXTHIF_Pos)                  /*!< SPI_T::STATUS: TXTHIF Mask             */
+
+#define SPI_STATUS_TXUFIF_Pos            (19)                                              /*!< SPI_T::STATUS: TXUFIF Position         */
+#define SPI_STATUS_TXUFIF_Msk            (0x1ul << SPI_STATUS_TXUFIF_Pos)                  /*!< SPI_T::STATUS: TXUFIF Mask             */
+
+#define SPI_STATUS_TXRXRST_Pos           (23)                                              /*!< SPI_T::STATUS: TXRXRST Position        */
+#define SPI_STATUS_TXRXRST_Msk           (0x1ul << SPI_STATUS_TXRXRST_Pos)                 /*!< SPI_T::STATUS: TXRXRST Mask            */
+
+#define SPI_STATUS_RXCNT_Pos             (24)                                              /*!< SPI_T::STATUS: RXCNT Position          */
+#define SPI_STATUS_RXCNT_Msk             (0xful << SPI_STATUS_RXCNT_Pos)                   /*!< SPI_T::STATUS: RXCNT Mask              */
+
+#define SPI_STATUS_TXCNT_Pos             (28)                                              /*!< SPI_T::STATUS: TXCNT Position          */
+#define SPI_STATUS_TXCNT_Msk             (0xful << SPI_STATUS_TXCNT_Pos)                   /*!< SPI_T::STATUS: TXCNT Mask              */
+
+#define SPI_TX_TX_Pos                    (0)                                               /*!< SPI_T::TX: TX Position                 */
+#define SPI_TX_TX_Msk                    (0xfffffffful << SPI_TX_TX_Pos)                   /*!< SPI_T::TX: TX Mask                     */
+
+#define SPI_RX_RX_Pos                    (0)                                               /*!< SPI_T::RX: RX Position                 */
+#define SPI_RX_RX_Msk                    (0xfffffffful << SPI_RX_RX_Pos)                   /*!< SPI_T::RX: RX Mask                     */
+
+#define SPI_I2SCTL_I2SEN_Pos             (0)                                               /*!< SPI_T::I2SCTL: I2SEN Position          */
+#define SPI_I2SCTL_I2SEN_Msk             (0x1ul << SPI_I2SCTL_I2SEN_Pos)                   /*!< SPI_T::I2SCTL: I2SEN Mask              */
+
+#define SPI_I2SCTL_TXEN_Pos              (1)                                               /*!< SPI_T::I2SCTL: TXEN Position           */
+#define SPI_I2SCTL_TXEN_Msk              (0x1ul << SPI_I2SCTL_TXEN_Pos)                    /*!< SPI_T::I2SCTL: TXEN Mask               */
+
+#define SPI_I2SCTL_RXEN_Pos              (2)                                               /*!< SPI_T::I2SCTL: RXEN Position           */
+#define SPI_I2SCTL_RXEN_Msk              (0x1ul << SPI_I2SCTL_RXEN_Pos)                    /*!< SPI_T::I2SCTL: RXEN Mask               */
+
+#define SPI_I2SCTL_MUTE_Pos              (3)                                               /*!< SPI_T::I2SCTL: MUTE Position           */
+#define SPI_I2SCTL_MUTE_Msk              (0x1ul << SPI_I2SCTL_MUTE_Pos)                    /*!< SPI_T::I2SCTL: MUTE Mask               */
+
+#define SPI_I2SCTL_WDWIDTH_Pos           (4)                                               /*!< SPI_T::I2SCTL: WDWIDTH Position        */
+#define SPI_I2SCTL_WDWIDTH_Msk           (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)                 /*!< SPI_T::I2SCTL: WDWIDTH Mask            */
+
+#define SPI_I2SCTL_MONO_Pos              (6)                                               /*!< SPI_T::I2SCTL: MONO Position           */
+#define SPI_I2SCTL_MONO_Msk              (0x1ul << SPI_I2SCTL_MONO_Pos)                    /*!< SPI_T::I2SCTL: MONO Mask               */
+
+#define SPI_I2SCTL_ORDER_Pos             (7)                                               /*!< SPI_T::I2SCTL: ORDER Position          */
+#define SPI_I2SCTL_ORDER_Msk             (0x1ul << SPI_I2SCTL_ORDER_Pos)                   /*!< SPI_T::I2SCTL: ORDER Mask              */
+
+#define SPI_I2SCTL_SLAVE_Pos             (8)                                               /*!< SPI_T::I2SCTL: SLAVE Position          */
+#define SPI_I2SCTL_SLAVE_Msk             (0x1ul << SPI_I2SCTL_SLAVE_Pos)                   /*!< SPI_T::I2SCTL: SLAVE Mask              */
+
+#define SPI_I2SCTL_MCLKEN_Pos            (15)                                              /*!< SPI_T::I2SCTL: MCLKEN Position         */
+#define SPI_I2SCTL_MCLKEN_Msk            (0x1ul << SPI_I2SCTL_MCLKEN_Pos)                  /*!< SPI_T::I2SCTL: MCLKEN Mask             */
+
+#define SPI_I2SCTL_RZCEN_Pos             (16)                                              /*!< SPI_T::I2SCTL: RZCEN Position          */
+#define SPI_I2SCTL_RZCEN_Msk             (0x1ul << SPI_I2SCTL_RZCEN_Pos)                   /*!< SPI_T::I2SCTL: RZCEN Mask              */
+
+#define SPI_I2SCTL_LZCEN_Pos             (17)                                              /*!< SPI_T::I2SCTL: LZCEN Position          */
+#define SPI_I2SCTL_LZCEN_Msk             (0x1ul << SPI_I2SCTL_LZCEN_Pos)                   /*!< SPI_T::I2SCTL: LZCEN Mask              */
+
+#define SPI_I2SCTL_RXLCH_Pos             (23)                                              /*!< SPI_T::I2SCTL: RXLCH Position          */
+#define SPI_I2SCTL_RXLCH_Msk             (0x1ul << SPI_I2SCTL_RXLCH_Pos)                   /*!< SPI_T::I2SCTL: RXLCH Mask              */
+
+#define SPI_I2SCTL_RZCIEN_Pos            (24)                                              /*!< SPI_T::I2SCTL: RZCIEN Position         */
+#define SPI_I2SCTL_RZCIEN_Msk            (0x1ul << SPI_I2SCTL_RZCIEN_Pos)                  /*!< SPI_T::I2SCTL: RZCIEN Mask             */
+
+#define SPI_I2SCTL_LZCIEN_Pos            (25)                                              /*!< SPI_T::I2SCTL: LZCIEN Position         */
+#define SPI_I2SCTL_LZCIEN_Msk            (0x1ul << SPI_I2SCTL_LZCIEN_Pos)                  /*!< SPI_T::I2SCTL: LZCIEN Mask             */
+
+#define SPI_I2SCTL_FORMAT_Pos            (28)                                              /*!< SPI_T::I2SCTL: FORMAT Position         */
+#define SPI_I2SCTL_FORMAT_Msk            (0x3ul << SPI_I2SCTL_FORMAT_Pos)                  /*!< SPI_T::I2SCTL: FORMAT Mask             */
+
+#define SPI_I2SCLK_MCLKDIV_Pos           (0)                                               /*!< SPI_T::I2SCLK: MCLKDIV Position        */
+#define SPI_I2SCLK_MCLKDIV_Msk           (0x7ful << SPI_I2SCLK_MCLKDIV_Pos)                /*!< SPI_T::I2SCLK: MCLKDIV Mask            */
+
+#define SPI_I2SCLK_BCLKDIV_Pos           (8)                                               /*!< SPI_T::I2SCLK: BCLKDIV Position        */
+#define SPI_I2SCLK_BCLKDIV_Msk           (0x3fful << SPI_I2SCLK_BCLKDIV_Pos)               /*!< SPI_T::I2SCLK: BCLKDIV Mask            */
+
+#define SPI_I2SSTS_RIGHT_Pos             (4)                                               /*!< SPI_T::I2SSTS: RIGHT Position          */
+#define SPI_I2SSTS_RIGHT_Msk             (0x1ul << SPI_I2SSTS_RIGHT_Pos)                   /*!< SPI_T::I2SSTS: RIGHT Mask              */
+
+#define SPI_I2SSTS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::I2SSTS: RXEMPTY Position        */
+#define SPI_I2SSTS_RXEMPTY_Msk           (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: RXEMPTY Mask            */
+
+#define SPI_I2SSTS_RXFULL_Pos            (9)                                               /*!< SPI_T::I2SSTS: RXFULL Position         */
+#define SPI_I2SSTS_RXFULL_Msk            (0x1ul << SPI_I2SSTS_RXFULL_Pos)                  /*!< SPI_T::I2SSTS: RXFULL Mask             */
+
+#define SPI_I2SSTS_RXTHIF_Pos            (10)                                              /*!< SPI_T::I2SSTS: RXTHIF Position         */
+#define SPI_I2SSTS_RXTHIF_Msk            (0x1ul << SPI_I2SSTS_RXTHIF_Pos)                  /*!< SPI_T::I2SSTS: RXTHIF Mask             */
+
+#define SPI_I2SSTS_RXOVIF_Pos            (11)                                              /*!< SPI_T::I2SSTS: RXOVIF Position         */
+#define SPI_I2SSTS_RXOVIF_Msk            (0x1ul << SPI_I2SSTS_RXOVIF_Pos)                  /*!< SPI_T::I2SSTS: RXOVIF Mask             */
+
+#define SPI_I2SSTS_RXTOIF_Pos            (12)                                              /*!< SPI_T::I2SSTS: RXTOIF Position         */
+#define SPI_I2SSTS_RXTOIF_Msk            (0x1ul << SPI_I2SSTS_RXTOIF_Pos)                  /*!< SPI_T::I2SSTS: RXTOIF Mask             */
+
+#define SPI_I2SSTS_I2SENSTS_Pos          (15)                                              /*!< SPI_T::I2SSTS: I2SENSTS Position       */
+#define SPI_I2SSTS_I2SENSTS_Msk          (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)                /*!< SPI_T::I2SSTS: I2SENSTS Mask           */
+
+#define SPI_I2SSTS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::I2SSTS: TXEMPTY Position        */
+#define SPI_I2SSTS_TXEMPTY_Msk           (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: TXEMPTY Mask            */
+
+#define SPI_I2SSTS_TXFULL_Pos            (17)                                              /*!< SPI_T::I2SSTS: TXFULL Position         */
+#define SPI_I2SSTS_TXFULL_Msk            (0x1ul << SPI_I2SSTS_TXFULL_Pos)                  /*!< SPI_T::I2SSTS: TXFULL Mask             */
+
+#define SPI_I2SSTS_TXTHIF_Pos            (18)                                              /*!< SPI_T::I2SSTS: TXTHIF Position         */
+#define SPI_I2SSTS_TXTHIF_Msk            (0x1ul << SPI_I2SSTS_TXTHIF_Pos)                  /*!< SPI_T::I2SSTS: TXTHIF Mask             */
+
+#define SPI_I2SSTS_TXUFIF_Pos            (19)                                              /*!< SPI_T::I2SSTS: TXUFIF Position         */
+#define SPI_I2SSTS_TXUFIF_Msk            (0x1ul << SPI_I2SSTS_TXUFIF_Pos)                  /*!< SPI_T::I2SSTS: TXUFIF Mask             */
+
+#define SPI_I2SSTS_RZCIF_Pos             (20)                                              /*!< SPI_T::I2SSTS: RZCIF Position          */
+#define SPI_I2SSTS_RZCIF_Msk             (0x1ul << SPI_I2SSTS_RZCIF_Pos)                   /*!< SPI_T::I2SSTS: RZCIF Mask              */
+
+#define SPI_I2SSTS_LZCIF_Pos             (21)                                              /*!< SPI_T::I2SSTS: LZCIF Position          */
+#define SPI_I2SSTS_LZCIF_Msk             (0x1ul << SPI_I2SSTS_LZCIF_Pos)                   /*!< SPI_T::I2SSTS: LZCIF Mask              */
+
+#define SPI_I2SSTS_TXRXRST_Pos           (23)                                              /*!< SPI_T::I2SSTS: TXRXRST Position        */
+#define SPI_I2SSTS_TXRXRST_Msk           (0x1ul << SPI_I2SSTS_TXRXRST_Pos)                 /*!< SPI_T::I2SSTS: TXRXRST Mask            */
+
+#define SPI_I2SSTS_RXCNT_Pos             (24)                                              /*!< SPI_T::I2SSTS: RXCNT Position          */
+#define SPI_I2SSTS_RXCNT_Msk             (0x7ul << SPI_I2SSTS_RXCNT_Pos)                   /*!< SPI_T::I2SSTS: RXCNT Mask              */
+
+#define SPI_I2SSTS_TXCNT_Pos             (28)                                              /*!< SPI_T::I2SSTS: TXCNT Position          */
+#define SPI_I2SSTS_TXCNT_Msk             (0x7ul << SPI_I2SSTS_TXCNT_Pos)                   /*!< SPI_T::I2SSTS: TXCNT Mask              */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+
+
+
+/*---------------------- SPIM Serial Interface Controller Master Mode (SPIM) -------------------------*/
+/**
+    @addtogroup SPIM Serial Interface Controller Master Mode (SPIM)
+    Memory Mapped Structure for SPIM Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var SPIM_T::CTL0
+     * Offset: 0x00  Control and Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CIPHOFF   |Cipher Disable Control
+     * |        |          |0 = Cipher function Enabled.
+     * |        |          |1 = Cipher function Disabled.
+     * |        |          |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+     * |        |          |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+     * |        |          |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+     * |        |          |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10.
+     * |        |          |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8.
+     * |[2]     |BALEN     |Balance the AHB Control Time Between Cipher Enable and Disable Control
+     * |        |          |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation
+     * |        |          |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.
+     * |        |          |Note: Only useful when cipher is disabled.
+     * |[5]     |B4ADDREN  |4-byte Address Mode Enable Control
+     * |        |          |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled.
+     * |        |          |1 = 4-byte address mode is enabled.
+     * |        |          |Note: Used for DMA write mode, DMA read mode, and DMM mode.
+     * |[6]     |IEN       |Interrupt Enable Control
+     * |        |          |0 = SPIM Interrupt Disabled.
+     * |        |          |1 = SPIM Interrupt Enabled.
+     * |[7]     |IF        |Interrupt Flag
+     * |        |          |(1) Write Operation :
+     * |        |          |0 = No effect.
+     * |        |          |1 = Write 1 to clear.
+     * |        |          |(2) Read Operation :
+     * |        |          |0 = The transfer has not finished yet.
+     * |        |          |1 = The transfer has done.
+     * |[12:8]  |DWIDTH    |Transmit/Receive Bit Length
+     * |        |          |This specifies how many bits are transmitted/received in one transmit/receive transaction.
+     * |        |          |0x7 = 8 bits.
+     * |        |          |0xF = 16 bits.
+     * |        |          |0x17 = 24 bits.
+     * |        |          |0x1F = 32 bits.
+     * |        |          |Others = Incorrect transfer result.
+     * |        |          |Note1: Only used for normal I/O mode.
+     * |        |          |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
+     * |[14:13] |BURSTNUM  |Transmit/Receive Burst Number
+     * |        |          |This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
+     * |        |          |0x0 = Only one transmit/receive transaction will be executed in one transfer.
+     * |        |          |0x1 = Two successive transmit/receive transactions will be executed in one transfer.
+     * |        |          |0x2 = Three successive transmit/receive transactions will be executed in one transfer.
+     * |        |          |0x3 = Four successive transmit/receive transactions will be executed in one transfer.
+     * |        |          |Note: Only used for normal I/O Mode.
+     * |[15]    |QDIODIR   |SPI Interface Direction Select for Quad/Dual Mode
+     * |        |          |0 = Interface signals are input.
+     * |        |          |1 = Interface signals are output.
+     * |        |          |Note: Only used for normal I/O mode.
+     * |[19:16] |SUSPITV   |Suspend Interval
+     * |        |          |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer
+     * |        |          |The default value is 0x00
+     * |        |          |When BURSTNUM = 00, setting this field has no effect on transfer
+     * |        |          |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock):
+     * |        |          |  (SUSPITV+2)*period of AHB clock
+     * |        |          |  0x0 = 2 AHB clock cycles.
+     * |        |          |  0x1 = 3 AHB clock cycles.
+     * |        |          |  ......
+     * |        |          |  0xE = 16 AHB clock cycles.
+     * |        |          |  0xF = 17 AHB clock cycles.
+     * |        |          |  Note: Only used for normal I/O mode.
+     * |[21:20] |BITMODE   |SPI Interface Bit Mode
+     * |        |          |0x0 = Standard mode.
+     * |        |          |0x1 = Dual mode.
+     * |        |          |0x2 = Quad mode.
+     * |        |          |0x3 = Reserved.
+     * |        |          |Note: Only used for normal I/O mode.
+     * |[23:22] |OPMODE    |SPI Function Operation Mode
+     * |        |          |0x0 = Normal I/O mode. (Note1) (Note3)
+     * |        |          |0x1 = DMA write mode. (Note2) (Note3)
+     * |        |          |0x2 = DMA read mode. (Note3)
+     * |        |          |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4)
+     * |        |          |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+     * |        |          |Note2 : In DMA write mode, hardware will send just one page program command per operation
+     * |        |          |Users must take care of cross-page cases
+     * |        |          |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+     * |        |          |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data
+     * |        |          |Please user check size of used SPI flash component to know access address range of external SPI flash.
+     * |        |          |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data
+     * |        |          |Please user check size of used SPI flash component to know access address range of external SPI flash.
+     * |[31:24] |CMDCODE   |Page Program Command Code (Note4)
+     * |        |          |(1) 0x02 = Page program (Used for DMA Write mode).
+     * |        |          |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3)
+     * |        |          |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3)
+     * |        |          |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3)
+     * |        |          |The Others = Reserved.
+     * |        |          |Read Command Code :
+     * |        |          |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode).
+     * |        |          |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode).
+     * |        |          |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency
+     * |        |          |(Note2)
+     * |        |          |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode).
+     * |        |          |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode).
+     * |        |          |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock
+     * |        |          |(Note2)
+     * |        |          |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode).
+     * |        |          |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode).
+     * |        |          |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read
+     * |        |          |(Note2)
+     * |        |          |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode).
+     * |        |          |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode).
+     * |        |          |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode).
+     * |        |          |The Others command codes are Reserved.
+     * |        |          |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK)
+     * |        |          |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock
+     * |        |          |(Note2)
+     * |        |          |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands.
+     * |        |          |Note2: See SPI flash specifications for support items.
+     * |        |          |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5.
+     * |        |          |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash
+     * |        |          |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
+     * @var SPIM_T::CTL1
+     * Offset: 0x04  Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPIMEN    |Go and Busy Status
+     * |        |          |(1) Write Operation :
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start the transfer
+     * |        |          |This bit remains set during the transfer and is automatically cleared after transfer finished.
+     * |        |          |(2) Read Operation :
+     * |        |          |0 = The transfer has done.
+     * |        |          |1 = The transfer has not finished yet.
+     * |        |          |Note: All registers should be set before writing 1 to the SPIMEN bit
+     * |        |          |When a transfer is in progress, you should not write to any register of this peripheral.
+     * |[1]     |CACHEOFF  |Cache Memory Function Disable Control
+     * |        |          |0 = Cache memory function enable. (Default value)
+     * |        |          |1 = Cache memory function disable.
+     * |        |          |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically
+     * |        |          |When CCM mode is disabled, the cache function can be enable or disable by user.
+     * |[2]     |CCMEN     |CCM (Core Coupled Memory) Mode Enable Control
+     * |        |          |0 = CCM mode disable. (Default value)
+     * |        |          |1 = CCM mode enable.
+     * |        |          |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically
+     * |        |          |When CCM mode is disabled, the cache function can be enabled or disabled by user.
+     * |        |          |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master
+     * |        |          |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master.
+     * |        |          |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status
+     * |        |          |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
+     * |[3]     |CDINVAL   |Cache Data Invalid Enable Control
+     * |        |          |(1) Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically.
+     * |        |          |(2) Read Operation : No effect
+     * |        |          |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1
+     * |        |          |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1.
+     * |[4]     |SS        |Slave Select Active Enable Control
+     * |        |          |0 = SPIM_SS is in active level.
+     * |        |          |1 = SPIM_SS is in inactive level (Default).
+     * |        |          |Note: This interface can only drive one device/slave at a given time
+     * |        |          |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer
+     * |        |          |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2.
+     * |[5]     |SSACTPOL  |Slave Select Active Level
+     * |        |          |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2.
+     * |        |          |0 = The SPIM_SS slave select signal is active low.
+     * |        |          |1 = The SPIM_SS slave select signal is active high.
+     * |[11:8]  |IDLETIME  |Idle Time Interval
+     * |        |          |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses.
+     * |        |          |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time.
+     * |        |          |Note1: Only used for DMM mode.
+     * |        |          |Note2 : AHB clock cycle time = 1/AHB clock frequency.
+     * |[31:16] |DIVIDER   |Clock Divider Register
+     * |        |          |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin
+     * |        |          |The desired frequency is obtained according to the following equation:
+     * |        |          |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK.
+     * |        |          |Note2: SCLK is serial SPI output clock.
+     * |        |          |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock.
+     * |        |          |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ...
+     * @var SPIM_T::RXCLKDLY
+     * Offset: 0x0C  RX Clock Delay Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DWDELSEL  |SPI flash deselect time interval of DMA write mode
+     * |        |          |For DMA write mode only
+     * |        |          |This register sets the deselect time interval of SPI flash (i.e.
+     * |        |          |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode
+     * |        |          |(Note1)
+     * |        |          |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2).
+     * |        |          |Note1: Please user check the used external SPI flash component to set this register value
+     * |        |          |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation.
+     * |        |          |Note2: AHB clock cycle time = 1/AHB clock frequency.
+     * |[18:16] |RDDLYSEL  |Sampling Clock Delay Selection for Received Data
+     * |        |          |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
+     * |        |          |Determine the number of inserted delay cycles
+     * |        |          |Used to adjust the sampling clock of received data to latch the correct data.
+     * |        |          |0x0 : No delay. (Default Value)
+     * |        |          |0x1 : Delay 1 SPI flash clock.
+     * |        |          |0x2 : Delay 2 SPI flash clocks.
+     * |        |          |0x3 : Delay 3 SPI flash clocks.
+     * |        |          |...
+     * |        |          |0x7 : Delay 7 SPI flash clocks
+     * |        |          |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows.
+     * |        |          |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately
+     * |        |          |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).
+     * |        |          |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1
+     * |        |          |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly.
+     * |[20]    |RDEDGE    |Sampling Clock Edge Selection for Received Data
+     * |        |          |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
+     * |        |          |0 : Use SPI input clock rising edge to sample received data. (Default Value)
+     * |        |          |1 : Use SPI input clock falling edge to sample received data.
+     * @var SPIM_T::RX[4]
+     * Offset: 0x10 ~ 0x1C  Data Receive Register 0 ~ 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXDAT     |Data Receive Register
+     * |        |          |The Data Receive Registers hold the received data of the last executed transfer.
+     * |        |          |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]
+     * |        |          |If BURSTNUM > 0, received data are held in the most significant RXDAT register first.
+     * |        |          |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
+     * |        |          |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first.
+     * |        |          |In a byte, received data are held in the most significant bit of RXDAT register first.
+     * |        |          |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0].
+     * |        |          |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16].
+     * |        |          |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ...,
+     * |        |          |SPIM_RX0[0].
+     * @var SPIM_T::TX[4]
+     * Offset: 0x20 ~ 0x2C  Data Transmit Register 0 ~ 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXDAT     |Data Transmit Register
+     * |        |          |The Data Transmit Registers hold the data to be transmitted in next transfer.
+     * |        |          |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]
+     * |        |          |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first.
+     * |        |          |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
+     * |        |          |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first.
+     * |        |          |In a byte, data are transmitted in the most significant bit of TXDAT register first.
+     * |        |          |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer.
+     * |        |          |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer.
+     * |        |          |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ...,
+     * |        |          |SPIM_TX0[0] in next transfer.
+     * @var SPIM_T::SRAMADDR
+     * Offset: 0x30  SRAM Memory Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ADDR      |SRAM Memory Address
+     * |        |          |For DMA Read mode, this is the destination address for DMA transfer.
+     * |        |          |For DMA Write mode, this is the source address for DMA transfer.
+     * |        |          |Note: This address must be word-aligned.
+     * @var SPIM_T::DMACNT
+     * Offset: 0x34  DMA Transfer Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |DMACNT    |DMA Transfer Byte Count Register
+     * |        |          |It indicates the transfer length for DMA process.
+     * |        |          |Note1: The unit for counting is byte.
+     * |        |          |Note2: The number must be the multiple of 4.
+     * |        |          |Note3: Please check specification of used SPI flash to know maximum byte length of page program.
+     * @var SPIM_T::FADDR
+     * Offset: 0x38  SPI Flash Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ADDR      |SPI Flash Address Register
+     * |        |          |For DMA Read mode, this is the source address for DMA transfer.
+     * |        |          |For DMA Write mode, this is the destination address for DMA transfer.
+     * |        |          |Note 1 : This address must be word-aligned.
+     * |        |          |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data
+     * |        |          |Please user check size of used SPI flash component to know access address range of external SPI flash.
+     * @var SPIM_T::KEY1
+     * Offset: 0x3C  Cipher Key1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY1      |Cipher Key1 Register
+     * |        |          |This is the KEY1 data for cipher function.
+     * |        |          |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+     * |        |          |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+     * |        |          |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+     * @var SPIM_T::KEY2
+     * Offset: 0x40  Cipher Key2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY2      |Cipher Key2 Register
+     * |        |          |This is the KEY2 data for cipher function.
+     * |        |          |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
+     * |        |          |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
+     * |        |          |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
+     * @var SPIM_T::DMMCTL
+     * Offset: 0x44  Direct Memory Mapping Mode Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:8]  |CRMDAT    |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0)
+     * |        |          |Only for direct memory mapping mode
+     * |        |          |Set the mode bits data for continuous read mode (or performance enhance mode).
+     * |        |          |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active
+     * |        |          |(Note1)
+     * |        |          |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values.
+     * |        |          |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]).
+     * |[20:16] |DESELTIM  |SPI Flash Deselect Time
+     * |        |          |Only for direct memory mapping mode
+     * |        |          |Set the minimum time width of SPI flash deselect time (i.e.
+     * |        |          |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8.
+     * |        |          |(1) Cache function disable :
+     * |        |          |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time.
+     * |        |          |(2) Cache function enable :
+     * |        |          |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time.
+     * |        |          |Note1 : AHB clock cycle time = 1/AHB clock frequency.
+     * |        |          |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10
+     * |        |          |When cipher encryption/decryption is disabled, please set this register value >= 0x8.
+     * |        |          |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
+     * |[24]    |BWEN      |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0)
+     * |        |          |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7"
+     * |        |          |0 = Burst Wrap Mode Disable. (Default)
+     * |        |          |1 = Burst Wrap Mode Enable.
+     * |        |          |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance
+     * |        |          |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size)
+     * |        |          |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly.
+     * |[25]    |CREN      |Continuous Read Mode Enable Control
+     * |        |          |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2)
+     * |        |          |0 = Continuous Read Mode Disable. (Default)
+     * |        |          |1 = Continuous Read Mode Enable.
+     * |        |          |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data.
+     * |        |          |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications
+     * |        |          |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash.
+     * |[26]    |UACTSCLK  |User Sets SPI Flash Active SCLK Time
+     * |        |          |Only for direct memory mapping mode, DMA write mode, and DMA read mode
+     * |        |          |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically
+     * |        |          |(Default value)
+     * |        |          |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually.
+     * |        |          |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
+     * |[31:28] |ACTSCLKT  |SPI Flash Active SCLK Time
+     * |        |          |Only for direct memory mapping mode, DMA write mode, and DMA read mode
+     * |        |          |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8.
+     * |        |          |(1) ACTSCLKT = 0 (function disable) :.
+     * |        |          |Time interval = 1 AHB clock cycle time.
+     * |        |          |(2) ACTSCLKT != 0 (function enable) :
+     * |        |          |Time interval = (ACTSCLKT + 3) * AHB clock cycle time.
+     * |        |          |Note1 : AHB clock cycle time = 1/AHB clock frequency.
+     * |        |          |Note2 : SCLK is SPI output clock
+     * |        |          |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
+     * @var SPIM_T::CTL2
+     * Offset: 0x48  Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[16]    |USETEN    |User Set Value Enable Control
+     * |        |          |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7
+     * |        |          |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically.
+     * |        |          |Dummy cycle number (DCNUM) :
+     * |        |          |Dummy cycle number for read command 0x03 : 0x0
+     * |        |          |Dummy cycle number for read command 0x0B : 0x8
+     * |        |          |Dummy cycle number for read command 0x3B : 0x8
+     * |        |          |Dummy cycle number for read command 0xBB : 0x0
+     * |        |          |Dummy cycle number for read command 0xEB : 0x4
+     * |        |          |Dummy cycle number for read command 0xE7 : 0x2
+     * |        |          |Mode bits data for continuous read mode (CRMDAT) : 0x20
+     * |        |          |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually.
+     * |        |          |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
+     * |[20]    |DTRMPOFF  |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED
+     * |        |          |Only for direct memory mapping mode and DMA read mode (Note1)
+     * |        |          |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
+     * |        |          |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
+     * |        |          |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
+     * |[28:24] |DCNUM     |Dummy Cycle Number
+     * |        |          |Only for direct memory mapping mode and DMA read mode (Note1)
+     * |        |          |Set number of dummy cycles
+     * |        |          |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 :
+     * |        |          |When read command code do not need any dummy cycles (i.e.
+     * |        |          |dummy cycle number = 0x0), user must set DCNUM to 0x0.
+     * |        |          |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification.
+     * |        |          |For command code 0xBB, if there is only dummy cycle number (i.e.
+     * |        |          |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification.
+     * |        |          |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification.
+     * |        |          |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED :
+     * |        |          |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification.
+     * |        |          |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types
+     * |        |          |Please check the used SPI flash specification to know the setting value of this number of dummy cycles.
+     * @var SPIM_T::VERSION
+     * Offset: 0x4C  SPIM Version Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MINOR     |SPIM Design MINOR Version Number
+     * |        |          |Minor version number is dependent on ECO version control
+     * |        |          |0x0000: (current Minor Version Number)
+     * |[23:16] |SUB       |SPIM Design SUB Version Number
+     * |        |          |Sub version number is relative to key feature
+     * |        |          |0x02: (current Sub Version Number)
+     * |[31:24] |MAJOR     |SPIM Design MAJOR Version Number
+     * |        |          |Major version number is correlated to Product Line
+     * |        |          |0x02: (current Major Version Number)
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] Control and Status Register 0                                    */
+    __IO uint32_t CTL1;                  /*!< [0x0004] Control Register 1                                               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t RXCLKDLY;              /*!< [0x000c] RX Clock Delay Control Register                                  */
+    __I  uint32_t RX[4];                 /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3                             */
+    __IO uint32_t TX[4];                 /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3                            */
+    __IO uint32_t SRAMADDR;              /*!< [0x0030] SRAM Memory Address Register                                     */
+    __IO uint32_t DMACNT;                /*!< [0x0034] DMA Transfer Byte Count Register                                 */
+    __IO uint32_t FADDR;                 /*!< [0x0038] SPI Flash Address Register                                       */
+    __O  uint32_t KEY1;                  /*!< [0x003c] Cipher Key1 Register                                             */
+    __O  uint32_t KEY2;                  /*!< [0x0040] Cipher Key2 Register                                             */
+    __IO uint32_t DMMCTL;                /*!< [0x0044] Direct Memory Mapping Mode Control Register                      */
+    __IO uint32_t CTL2;                  /*!< [0x0048] Control Register 2                                               */
+    __I  uint32_t VERSION;               /*!< [0x004c] SPIM Version Control Register                                    */
+
+} SPIM_T;
+
+/**
+    @addtogroup SPIM_CONST SPIM Bit Field Definition
+    Constant Definitions for SPIM Controller
+@{ */
+
+#define SPIM_CTL0_CIPHOFF_Pos            (0)                                               /*!< SPIM_T::CTL0: CIPHOFF Position         */
+#define SPIM_CTL0_CIPHOFF_Msk            (0x1ul << SPIM_CTL0_CIPHOFF_Pos)                  /*!< SPIM_T::CTL0: CIPHOFF Mask             */
+
+#define SPIM_CTL0_BALEN_Pos              (2)                                               /*!< SPIM_T::CTL0: BALEN Position           */
+#define SPIM_CTL0_BALEN_Msk              (0x1ul << SPIM_CTL0_BALEN_Pos)                    /*!< SPIM_T::CTL0: BALEN Mask               */
+
+#define SPIM_CTL0_B4ADDREN_Pos           (5)                                               /*!< SPIM_T::CTL0: B4ADDREN Position        */
+#define SPIM_CTL0_B4ADDREN_Msk           (0x1ul << SPIM_CTL0_B4ADDREN_Pos)                 /*!< SPIM_T::CTL0: B4ADDREN Mask            */
+
+#define SPIM_CTL0_IEN_Pos                (6)                                               /*!< SPIM_T::CTL0: IEN Position             */
+#define SPIM_CTL0_IEN_Msk                (0x1ul << SPIM_CTL0_IEN_Pos)                      /*!< SPIM_T::CTL0: IEN Mask                 */
+
+#define SPIM_CTL0_IF_Pos                 (7)                                               /*!< SPIM_T::CTL0: IF Position              */
+#define SPIM_CTL0_IF_Msk                 (0x1ul << SPIM_CTL0_IF_Pos)                       /*!< SPIM_T::CTL0: IF Mask                  */
+
+#define SPIM_CTL0_DWIDTH_Pos             (8)                                               /*!< SPIM_T::CTL0: DWIDTH Position          */
+#define SPIM_CTL0_DWIDTH_Msk             (0x1ful << SPIM_CTL0_DWIDTH_Pos)                  /*!< SPIM_T::CTL0: DWIDTH Mask              */
+
+#define SPIM_CTL0_BURSTNUM_Pos           (13)                                              /*!< SPIM_T::CTL0: BURSTNUM Position        */
+#define SPIM_CTL0_BURSTNUM_Msk           (0x3ul << SPIM_CTL0_BURSTNUM_Pos)                 /*!< SPIM_T::CTL0: BURSTNUM Mask            */
+
+#define SPIM_CTL0_QDIODIR_Pos            (15)                                              /*!< SPIM_T::CTL0: QDIODIR Position         */
+#define SPIM_CTL0_QDIODIR_Msk            (0x1ul << SPIM_CTL0_QDIODIR_Pos)                  /*!< SPIM_T::CTL0: QDIODIR Mask             */
+
+#define SPIM_CTL0_SUSPITV_Pos            (16)                                              /*!< SPIM_T::CTL0: SUSPITV Position         */
+#define SPIM_CTL0_SUSPITV_Msk            (0xful << SPIM_CTL0_SUSPITV_Pos)                  /*!< SPIM_T::CTL0: SUSPITV Mask             */
+
+#define SPIM_CTL0_BITMODE_Pos            (20)                                              /*!< SPIM_T::CTL0: BITMODE Position         */
+#define SPIM_CTL0_BITMODE_Msk            (0x3ul << SPIM_CTL0_BITMODE_Pos)                  /*!< SPIM_T::CTL0: BITMODE Mask             */
+
+#define SPIM_CTL0_OPMODE_Pos             (22)                                              /*!< SPIM_T::CTL0: OPMODE Position          */
+#define SPIM_CTL0_OPMODE_Msk             (0x3ul << SPIM_CTL0_OPMODE_Pos)                   /*!< SPIM_T::CTL0: OPMODE Mask              */
+
+#define SPIM_CTL0_CMDCODE_Pos            (24)                                              /*!< SPIM_T::CTL0: CMDCODE Position         */
+#define SPIM_CTL0_CMDCODE_Msk            (0xfful << SPIM_CTL0_CMDCODE_Pos)                 /*!< SPIM_T::CTL0: CMDCODE Mask             */
+
+#define SPIM_CTL1_SPIMEN_Pos             (0)                                               /*!< SPIM_T::CTL1: SPIMEN Position          */
+#define SPIM_CTL1_SPIMEN_Msk             (0x1ul << SPIM_CTL1_SPIMEN_Pos)                   /*!< SPIM_T::CTL1: SPIMEN Mask              */
+
+#define SPIM_CTL1_CACHEOFF_Pos           (1)                                               /*!< SPIM_T::CTL1: CACHEOFF Position        */
+#define SPIM_CTL1_CACHEOFF_Msk           (0x1ul << SPIM_CTL1_CACHEOFF_Pos)                 /*!< SPIM_T::CTL1: CACHEOFF Mask            */
+
+#define SPIM_CTL1_CCMEN_Pos              (2)                                               /*!< SPIM_T::CTL1: CCMEN Position           */
+#define SPIM_CTL1_CCMEN_Msk              (0x1ul << SPIM_CTL1_CCMEN_Pos)                    /*!< SPIM_T::CTL1: CCMEN Mask               */
+
+#define SPIM_CTL1_CDINVAL_Pos            (3)                                               /*!< SPIM_T::CTL1: CDINVAL Position         */
+#define SPIM_CTL1_CDINVAL_Msk            (0x1ul << SPIM_CTL1_CDINVAL_Pos)                  /*!< SPIM_T::CTL1: CDINVAL Mask             */
+
+#define SPIM_CTL1_SS_Pos                 (4)                                               /*!< SPIM_T::CTL1: SS Position              */
+#define SPIM_CTL1_SS_Msk                 (0x1ul << SPIM_CTL1_SS_Pos)                       /*!< SPIM_T::CTL1: SS Mask                  */
+
+#define SPIM_CTL1_SSACTPOL_Pos           (5)                                               /*!< SPIM_T::CTL1: SSACTPOL Position        */
+#define SPIM_CTL1_SSACTPOL_Msk           (0x1ul << SPIM_CTL1_SSACTPOL_Pos)                 /*!< SPIM_T::CTL1: SSACTPOL Mask            */
+
+#define SPIM_CTL1_IDLETIME_Pos           (8)                                               /*!< SPIM_T::CTL1: IDLETIME Position        */
+#define SPIM_CTL1_IDLETIME_Msk           (0xful << SPIM_CTL1_IDLETIME_Pos)                 /*!< SPIM_T::CTL1: IDLETIME Mask            */
+
+#define SPIM_CTL1_DIVIDER_Pos            (16)                                              /*!< SPIM_T::CTL1: DIVIDER Position         */
+#define SPIM_CTL1_DIVIDER_Msk            (0xfffful << SPIM_CTL1_DIVIDER_Pos)               /*!< SPIM_T::CTL1: DIVIDER Mask             */
+
+#define SPIM_RXCLKDLY_DWDELSEL_Pos       (0)                                               /*!< SPIM_T::RXCLKDLY: DWDELSEL Position    */
+#define SPIM_RXCLKDLY_DWDELSEL_Msk       (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos)            /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask        */
+
+#define SPIM_RXCLKDLY_RDDLYSEL_Pos       (16)                                              /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position    */
+#define SPIM_RXCLKDLY_RDDLYSEL_Msk       (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos)             /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask        */
+
+#define SPIM_RXCLKDLY_RDEDGE_Pos         (20)                                              /*!< SPIM_T::RXCLKDLY: RDEDGE Position      */
+#define SPIM_RXCLKDLY_RDEDGE_Msk         (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos)               /*!< SPIM_T::RXCLKDLY: RDEDGE Mask          */
+
+#define SPIM_RX_RXDAT_Pos                (0)                                               /*!< SPIM_T::RX[4]: RXDAT Position          */
+#define SPIM_RX_RXDAT_Msk                (0xfffffffful << SPIM_RX_RXDAT_Pos)               /*!< SPIM_T::RX[4]: RXDAT Mask              */
+
+#define SPIM_TX_TXDAT_Pos                (0)                                               /*!< SPIM_T::TX[4]: TXDAT Position          */
+#define SPIM_TX_TXDAT_Msk                (0xfffffffful << SPIM_TX_TXDAT_Pos)               /*!< SPIM_T::TX[4]: TXDAT Mask              */
+
+#define SPIM_SRAMADDR_ADDR_Pos           (0)                                               /*!< SPIM_T::SRAMADDR: ADDR Position        */
+#define SPIM_SRAMADDR_ADDR_Msk           (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos)          /*!< SPIM_T::SRAMADDR: ADDR Mask            */
+
+#define SPIM_DMACNT_DMACNT_Pos           (0)                                               /*!< SPIM_T::DMACNT: DMACNT Position        */
+#define SPIM_DMACNT_DMACNT_Msk           (0xfffffful << SPIM_DMACNT_DMACNT_Pos)            /*!< SPIM_T::DMACNT: DMACNT Mask            */
+
+#define SPIM_FADDR_ADDR_Pos              (0)                                               /*!< SPIM_T::FADDR: ADDR Position           */
+#define SPIM_FADDR_ADDR_Msk              (0xfffffffful << SPIM_FADDR_ADDR_Pos)             /*!< SPIM_T::FADDR: ADDR Mask               */
+
+#define SPIM_KEY1_KEY1_Pos               (0)                                               /*!< SPIM_T::KEY1: KEY1 Position            */
+#define SPIM_KEY1_KEY1_Msk               (0xfffffffful << SPIM_KEY1_KEY1_Pos)              /*!< SPIM_T::KEY1: KEY1 Mask                */
+
+#define SPIM_KEY2_KEY2_Pos               (0)                                               /*!< SPIM_T::KEY2: KEY2 Position            */
+#define SPIM_KEY2_KEY2_Msk               (0xfffffffful << SPIM_KEY2_KEY2_Pos)              /*!< SPIM_T::KEY2: KEY2 Mask                */
+
+#define SPIM_DMMCTL_CRMDAT_Pos           (8)                                               /*!< SPIM_T::DMMCTL: CRMDAT Position        */
+#define SPIM_DMMCTL_CRMDAT_Msk           (0xfful << SPIM_DMMCTL_CRMDAT_Pos)                /*!< SPIM_T::DMMCTL: CRMDAT Mask            */
+
+#define SPIM_DMMCTL_DESELTIM_Pos         (16)                                              /*!< SPIM_T::DMMCTL: DESELTIM Position      */
+#define SPIM_DMMCTL_DESELTIM_Msk         (0x1ful << SPIM_DMMCTL_DESELTIM_Pos)              /*!< SPIM_T::DMMCTL: DESELTIM Mask          */
+
+#define SPIM_DMMCTL_BWEN_Pos             (24)                                              /*!< SPIM_T::DMMCTL: BWEN Position          */
+#define SPIM_DMMCTL_BWEN_Msk             (0x1ul << SPIM_DMMCTL_BWEN_Pos)                   /*!< SPIM_T::DMMCTL: BWEN Mask              */
+
+#define SPIM_DMMCTL_CREN_Pos             (25)                                              /*!< SPIM_T::DMMCTL: CREN Position          */
+#define SPIM_DMMCTL_CREN_Msk             (0x1ul << SPIM_DMMCTL_CREN_Pos)                   /*!< SPIM_T::DMMCTL: CREN Mask              */
+
+#define SPIM_DMMCTL_UACTSCLK_Pos         (26)                                              /*!< SPIM_T::DMMCTL: UACTSCLK Position      */
+#define SPIM_DMMCTL_UACTSCLK_Msk         (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos)               /*!< SPIM_T::DMMCTL: UACTSCLK Mask          */
+
+#define SPIM_DMMCTL_ACTSCLKT_Pos         (28)                                              /*!< SPIM_T::DMMCTL: ACTSCLKT Position      */
+#define SPIM_DMMCTL_ACTSCLKT_Msk         (0xful << SPIM_DMMCTL_ACTSCLKT_Pos)               /*!< SPIM_T::DMMCTL: ACTSCLKT Mask          */
+
+#define SPIM_CTL2_USETEN_Pos             (16)                                              /*!< SPIM_T::CTL2: USETEN Position          */
+#define SPIM_CTL2_USETEN_Msk             (0x1ul << SPIM_CTL2_USETEN_Pos)                   /*!< SPIM_T::CTL2: USETEN Mask              */
+
+#define SPIM_CTL2_DTRMPOFF_Pos           (20)                                              /*!< SPIM_T::CTL2: DTRMPOFF Position        */
+#define SPIM_CTL2_DTRMPOFF_Msk           (0x1ul << SPIM_CTL2_DTRMPOFF_Pos)                 /*!< SPIM_T::CTL2: DTRMPOFF Mask            */
+
+#define SPIM_CTL2_DCNUM_Pos              (24)                                              /*!< SPIM_T::CTL2: DCNUM Position           */
+#define SPIM_CTL2_DCNUM_Msk              (0x1ful << SPIM_CTL2_DCNUM_Pos)                   /*!< SPIM_T::CTL2: DCNUM Mask               */
+
+#define SPIM_VERSION_MINOR_Pos           (0)                                               /*!< SPIM_T::VERSION: MINOR Position        */
+#define SPIM_VERSION_MINOR_Msk           (0xfffful << SPIM_VERSION_MINOR_Pos)              /*!< SPIM_T::VERSION: MINOR Mask            */
+
+#define SPIM_VERSION_SUB_Pos             (16)                                              /*!< SPIM_T::VERSION: SUB Position          */
+#define SPIM_VERSION_SUB_Msk             (0xfful << SPIM_VERSION_SUB_Pos)                  /*!< SPIM_T::VERSION: SUB Mask              */
+
+#define SPIM_VERSION_MAJOR_Pos           (24)                                              /*!< SPIM_T::VERSION: MAJOR Position        */
+#define SPIM_VERSION_MAJOR_Msk           (0xfful << SPIM_VERSION_MAJOR_Pos)                /*!< SPIM_T::VERSION: MAJOR Mask            */
+
+/**@}*/ /* SPIM_CONST */
+/**@}*/ /* end of SPIM register group */
+
+
+
+
+/*---------------------- Inter-IC Bus Controller -------------------------*/
+/**
+    @addtogroup I2C Inter-IC Bus Controller(I2C)
+    Memory Mapped Structure for I2C Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var I2C_T::CTL0
+     * Offset: 0x00  I2C Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |AA        |Assert Acknowledge Control
+     * |        |          |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+     * |        |          |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
+     * |[3]     |SI        |I2C Interrupt Flag
+     * |        |          |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
+     * |        |          |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
+     * |        |          |SI must be cleared by software
+     * |        |          |Clear SI by writing 1 to this bit.
+     * |        |          |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
+     * |[4]     |STO       |I2C STOP Control
+     * |        |          |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
+     * |        |          |This bit will be cleared by hardware automatically.
+     * |[5]     |STA       |I2C START Control
+     * |        |          |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+     * |[6]     |I2CEN     |I2C Controller Enable Bit
+     * |        |          |Set to enable I2C serial function controller
+     * |        |          |When I2CEN=1 the I2C serial function enable
+     * |        |          |The multi-function pin function must set to SDA, and SCL of I2C function first.
+     * |        |          |0 = I2C controller Disabled.
+     * |        |          |1 = I2C controller Enabled.
+     * |[7]     |INTEN     |Enable Interrupt
+     * |        |          |0 = I2C interrupt Disabled.
+     * |        |          |1 = I2C interrupt Enabled.
+     * @var I2C_T::ADDR0
+     * Offset: 0x04  I2C Slave Address Register0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * |        |          |Note: When software set 10'h000, the address can not be used.
+     * @var I2C_T::DAT
+     * Offset: 0x08  I2C Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |I2C Data
+     * |        |          |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
+     * @var I2C_T::STATUS0
+     * Offset: 0x0C  I2C Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |STATUS    |I2C Status
+     * |        |          |The three least significant bits are always 0
+     * |        |          |The five most significant bits contain the status code
+     * |        |          |There are 28 possible status codes
+     * |        |          |When the content of I2C_STATUS is F8H, no serial interrupt is requested
+     * |        |          |Others I2C_STATUS values correspond to defined I2C states
+     * |        |          |When each of these states is entered, a status interrupt is requested (SI = 1)
+     * |        |          |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
+     * |        |          |In addition, states 00H stands for a Bus Error
+     * |        |          |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+     * |        |          |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
+     * @var I2C_T::CLKDIV
+     * Offset: 0x10  I2C Clock Divided Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DIVIDER   |I2C Clock Divided
+     * |        |          |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
+     * |        |          |Note: The minimum value of I2C_CLKDIV is 4.
+     * @var I2C_T::TOCTL
+     * Offset: 0x14  I2C Time-out Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOIF      |Time-out Flag
+     * |        |          |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[1]     |TOCDIV4   |Time-out Counter Input Clock Divided by 4
+     * |        |          |When Enabled, The time-out period is extend 4 times.
+     * |        |          |0 = Time-out period is extend 4 times Disabled.
+     * |        |          |1 = Time-out period is extend 4 times Enabled.
+     * |[2]     |TOCEN     |Time-out Counter Enable Bit
+     * |        |          |When Enabled, the 14-bit time-out counter will start counting when SI is clear
+     * |        |          |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
+     * |        |          |0 = Time-out counter Disabled.
+     * |        |          |1 = Time-out counter Enabled.
+     * @var I2C_T::ADDR1
+     * Offset: 0x18  I2C Slave Address Register1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * |        |          |Note: When software set 10'h000, the address can not be used.
+     * @var I2C_T::ADDR2
+     * Offset: 0x1C  I2C Slave Address Register2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * |        |          |Note: When software set 10'h000, the address can not be used.
+     * @var I2C_T::ADDR3
+     * Offset: 0x20  I2C Slave Address Register3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * |        |          |Note: When software set 10'h000, the address can not be used.
+     * @var I2C_T::ADDRMSK0
+     * Offset: 0x24  I2C Slave Address Mask Register0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK1
+     * Offset: 0x28  I2C Slave Address Mask Register1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK2
+     * Offset: 0x2C  I2C Slave Address Mask Register2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK3
+     * Offset: 0x30  I2C Slave Address Mask Register3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::WKCTL
+     * Offset: 0x3C  I2C Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |I2C Wake-up Enable Bit
+     * |        |          |0 = I2C wake-up function Disabled.
+     * |        |          |1 = I2C wake-up function Enabled.
+     * |[7]     |NHDBUSEN  |I2C No Hold BUS Enable Bit
+     * |        |          |0 = I2C hold bus after wake-up.
+     * |        |          |1 = I2C don't hold bus after wake-up.
+     * |        |          |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
+     * |        |          |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
+     * @var I2C_T::WKSTS
+     * Offset: 0x40  I2C Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKIF      |I2C Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode by I2C, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * |[1]     |WKAKDONE  |Wakeup Address Frame Acknowledge Bit Done
+     * |        |          |0 = The ACK bit cycle of address match frame isn't done.
+     * |        |          |1 = The ACK bit cycle of address match frame is done in power-down.
+     * |        |          |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
+     * |[2]     |WRSTSWK   |Read/Write Status Bit in Address Wakeup Frame
+     * |        |          |0 = Write command be record on the address match wakeup frame.
+     * |        |          |1 = Read command be record on the address match wakeup frame.
+     * |        |          |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
+     * @var I2C_T::CTL1
+     * Offset: 0x44  I2C Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function disable.
+     * |        |          |1 = Transmit PDMA function enable.
+     * |[1]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function disable.
+     * |        |          |1 = Receive PDMA function enable.
+     * |[2]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the I2C request to PDMA.
+     * |[8]     |PDMASTR   |PDMA Stretch Bit
+     * |        |          |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
+     * |        |          |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
+     * |        |          |(only master TX)
+     * |[9]     |ADDR10EN  |Address 10-bit Function Enable
+     * |        |          |0 = Address match 10-bit function is disabled.
+     * |        |          |1 = Address match 10-bit function is enabled.
+     * @var I2C_T::STATUS1
+     * Offset: 0x48  I2C Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADMAT0    |I2C Address 0 Match Status Register
+     * |        |          |When address 0 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[1]     |ADMAT1    |I2C Address 1 Match Status Register
+     * |        |          |When address 1 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[2]     |ADMAT2    |I2C Address 2 Match Status Register
+     * |        |          |When address 2 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[3]     |ADMAT3    |I2C Address 3 Match Status Register
+     * |        |          |When address 3 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[8]     |ONBUSY    |On Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected.
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |        |          |Note:This bit is read only.
+     * @var I2C_T::TMCTL
+     * Offset: 0x4C  I2C Timing Configure Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |STCTL     |Setup Time Configure Control Register
+     * |        |          |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
+     * |        |          |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
+     * |        |          |Note: Setup time setting should not make SCL output less than three PCLKs.
+     * |[24:16] |HTCTL     |Hold Time Configure Control Register
+     * |        |          |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
+     * |        |          |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
+     * @var I2C_T::BUSCTL
+     * Offset: 0x50  I2C Bus Management Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACKMEN    |Acknowledge Control by Manual
+     * |        |          |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
+     * |        |          |0 = Slave byte control Disabled.
+     * |        |          |1 = Slave byte control Enabled
+     * |        |          |The 9th bit can response the ACK or NACK according the received data by user
+     * |        |          |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
+     * |        |          |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
+     * |[1]     |PECEN     |Packet Error Checking Calculation Enable Bit
+     * |        |          |0 = Packet Error Checking Calculation Disabled.
+     * |        |          |1 = Packet Error Checking Calculation Enabled.
+     * |        |          |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
+     * |[2]     |BMDEN     |Bus Management Device Default Address Enable Bit
+     * |        |          |0 = Device default address Disable
+     * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
+     * |        |          |1 = Device default address Enabled
+     * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
+     * |[3]     |BMHEN     |Bus Management Host Enable Bit
+     * |        |          |0 = Host function Disabled.
+     * |        |          |1 = Host function Enabled.
+     * |[4]     |ALERTEN   |Bus Management Alert Enable Bit
+     * |        |          |Device Mode (BMHEN=0).
+     * |        |          |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
+     * |        |          |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
+     * |        |          |Host Mode (BMHEN=1).
+     * |        |          |0 = BM_ALERT pin not supported.
+     * |        |          |1 = BM_ALERT pin supported.
+     * |[5]     |SCTLOSTS  |Suspend/Control Data Output Status
+     * |        |          |0 = The output of SUSCON pin is low.
+     * |        |          |1 = The output of SUSCON pin is high.
+     * |[6]     |SCTLOEN   |Suspend or Control Pin Output Enable Bit
+     * |        |          |0 = The SUSCON pin in input.
+     * |        |          |1 = The output enable is active on the SUSCON pin.
+     * |[7]     |BUSEN     |BUS Enable Bit
+     * |        |          |0 = The system management function is Disabled.
+     * |        |          |1 = The system management function is Enable.
+     * |        |          |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
+     * |[8]     |PECTXEN   |Packet Error Checking Byte Transmission/Reception
+     * |        |          |0 = No PEC transfer.
+     * |        |          |1 = PEC transmission is requested.
+     * |        |          |Note: This bit has no effect in slave mode when ACKMEN=0.
+     * |[9]     |TIDLE     |Timer Check in Idle State
+     * |        |          |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
+     * |        |          |This bit is used to define which condition is enabled.
+     * |        |          |0 = The BUSTOUT is used to calculate the clock low period in bus active.
+     * |        |          |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
+     * |        |          |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
+     * |[10]    |PECCLR    |PEC Clear at Repeat Start
+     * |        |          |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
+     * |        |          |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
+     * |        |          |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
+     * |        |          |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled.
+     * |[11]    |ACKM9SI   |Acknowledge Manual Enable Extra SI Interrupt
+     * |        |          |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
+     * |        |          |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
+     * |[12]    |BCDIEN    |Packet Error Checking Byte Count Done Interrupt Enable Bit
+     * |        |          |0 = Indicates the byte count done interrupt is Disabled.
+     * |        |          |1 = Indicates the byte count done interrupt is Enabled.
+     * |        |          |Note: This bit is used in PECEN=1.
+     * |[13]    |PECDIEN   |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
+     * |        |          |0 = Indicates the PEC transfer done interrupt is Disabled.
+     * |        |          |1 = Indicates the PEC transfer done interrupt is Enabled.
+     * |        |          |Note: This bit is used in PECEN=1.
+     * @var I2C_T::BUSTCTL
+     * Offset: 0x54  I2C Bus Management Timer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSTOEN   |Bus Time Out Enable Bit
+     * |        |          |0 = Indicates the bus clock low time-out detection is Disabled.
+     * |        |          |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
+     * |[1]     |CLKTOEN   |Cumulative Clock Low Time Out Enable Bit
+     * |        |          |0 = Indicates the cumulative clock low time-out detection is Disabled.
+     * |        |          |1 = Indicates the cumulative clock low time-out detection is Enabled.
+     * |        |          |For Master, it calculates the period from START to ACK
+     * |        |          |For Slave, it calculates the period from START to STOP
+     * |[2]     |BUSTOIEN  |Time-out Interrupt Enable Bit
+     * |        |          |BUSY =1.
+     * |        |          |0 = Indicates the SCLK low time-out interrupt is Disabled.
+     * |        |          |1 = Indicates the SCLK low time-out interrupt is Enabled.
+     * |        |          |BUSY =0.
+     * |        |          |0 = Indicates the bus IDLE time-out interrupt is Disabled.
+     * |        |          |1 = Indicates the bus IDLE time-out interrupt is Enabled.
+     * |[3]     |CLKTOIEN  |Extended Clock Time Out Interrupt Enable Bit
+     * |        |          |0 = Indicates the clock time out interrupt is Disabled.
+     * |        |          |1 = Indicates the clock time out interrupt is Enabled.
+     * |[4]     |TORSTEN   |Time Out Reset Enable Bit
+     * |        |          |0 = Indicates the I2C state machine reset is Disable.
+     * |        |          |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
+     * @var I2C_T::BUSSTS
+     * Offset: 0x58  I2C Bus Management Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |[1]     |BCDONE    |Byte Count Transmission/Receive Done
+     * |        |          |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
+     * |        |          |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[2]     |PECERR    |PEC Error in Reception
+     * |        |          |0 = Indicates the PEC value equal the received PEC data packet.
+     * |        |          |1 = Indicates the PEC value doesn't match the receive PEC data packet.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[3]     |ALERT     |SMBus Alert Status
+     * |        |          |Device Mode (BMHEN =0).
+     * |        |          |0 = Indicates SMBALERT pin state is low.
+     * |        |          |1 = Indicates SMBALERT pin state is high.
+     * |        |          |Host Mode (BMHEN =1).
+     * |        |          |0 = No SMBALERT event.
+     * |        |          |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
+     * |        |          |Note:
+     * |        |          |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
+     * |        |          |2. Software can write 1 to clear this bit.
+     * |[4]     |SCTLDIN   |Bus Suspend or Control Signal Input Status
+     * |        |          |0 = The input status of SUSCON pin is 0.
+     * |        |          |1 = The input status of SUSCON pin is 1.
+     * |[5]     |BUSTO     |Bus Time-out Status
+     * |        |          |0 = Indicates that there is no any time-out or external clock time-out.
+     * |        |          |1 = Indicates that a time-out or external clock time-out occurred.
+     * |        |          |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[6]     |CLKTO     |Clock Low Cumulate Time-out Status
+     * |        |          |0 = Indicates that the cumulative clock low is no any time-out.
+     * |        |          |1 = Indicates that the cumulative clock low time-out occurred.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[7]     |PECDONE   |PEC Byte Transmission/Receive Done
+     * |        |          |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
+     * |        |          |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * @var I2C_T::PKTSIZE
+     * Offset: 0x5C  I2C Packet Error Checking Byte Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |PLDSIZE   |Transfer Byte Number
+     * |        |          |The transmission or receive byte number in one transaction when the PECEN is set
+     * |        |          |The maximum transaction or receive byte is 256 Bytes.
+     * |        |          |Notice: The byte number counting includes address, command code, and data frame.
+     * @var I2C_T::PKTCRC
+     * Offset: 0x60  I2C Packet Error Checking Byte Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |PECCRC    |Packet Error Checking Byte Value
+     * |        |          |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
+     * |        |          |It is read only.
+     * @var I2C_T::BUSTOUT
+     * Offset: 0x64  I2C Bus Management Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |BUSTO     |Bus Management Time-out Value
+     * |        |          |Indicate the bus time-out value in bus is IDLE or SCLK low.
+     * |        |          |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
+     * @var I2C_T::CLKTOUT
+     * Offset: 0x68  I2C Bus Management Clock Low Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CLKTO     |Bus Clock Low Timer
+     * |        |          |The field is used to configure the cumulative clock extension time-out.
+     * |        |          |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] I2C Control Register 0                                           */
+    __IO uint32_t ADDR0;                 /*!< [0x0004] I2C Slave Address Register0                                      */
+    __IO uint32_t DAT;                   /*!< [0x0008] I2C Data Register                                                */
+    __I  uint32_t STATUS0;               /*!< [0x000c] I2C Status Register 0                                            */
+    __IO uint32_t CLKDIV;                /*!< [0x0010] I2C Clock Divided Register                                       */
+    __IO uint32_t TOCTL;                 /*!< [0x0014] I2C Time-out Control Register                                    */
+    __IO uint32_t ADDR1;                 /*!< [0x0018] I2C Slave Address Register1                                      */
+    __IO uint32_t ADDR2;                 /*!< [0x001c] I2C Slave Address Register2                                      */
+    __IO uint32_t ADDR3;                 /*!< [0x0020] I2C Slave Address Register3                                      */
+    __IO uint32_t ADDRMSK0;              /*!< [0x0024] I2C Slave Address Mask Register0                                 */
+    __IO uint32_t ADDRMSK1;              /*!< [0x0028] I2C Slave Address Mask Register1                                 */
+    __IO uint32_t ADDRMSK2;              /*!< [0x002c] I2C Slave Address Mask Register2                                 */
+    __IO uint32_t ADDRMSK3;              /*!< [0x0030] I2C Slave Address Mask Register3                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WKCTL;                 /*!< [0x003c] I2C Wake-up Control Register                                     */
+    __IO uint32_t WKSTS;                 /*!< [0x0040] I2C Wake-up Status Register                                      */
+    __IO uint32_t CTL1;                  /*!< [0x0044] I2C Control Register 1                                           */
+    __IO uint32_t STATUS1;               /*!< [0x0048] I2C Status Register 1                                            */
+    __IO uint32_t TMCTL;                 /*!< [0x004c] I2C Timing Configure Control Register                            */
+    __IO uint32_t BUSCTL;                /*!< [0x0050] I2C Bus Management Control Register                              */
+    __IO uint32_t BUSTCTL;               /*!< [0x0054] I2C Bus Management Timer Control Register                        */
+    __IO uint32_t BUSSTS;                /*!< [0x0058] I2C Bus Management Status Register                               */
+    __IO uint32_t PKTSIZE;               /*!< [0x005c] I2C Packet Error Checking Byte Number Register                   */
+    __I  uint32_t PKTCRC;                /*!< [0x0060] I2C Packet Error Checking Byte Value Register                    */
+    __IO uint32_t BUSTOUT;               /*!< [0x0064] I2C Bus Management Timer Register                                */
+    __IO uint32_t CLKTOUT;               /*!< [0x0068] I2C Bus Management Clock Low Timer Register                      */
+
+} I2C_T;
+
+/**
+    @addtogroup I2C_CONST I2C Bit Field Definition
+    Constant Definitions for I2C Controller
+@{ */
+
+#define I2C_CTL0_AA_Pos                  (2)                                               /*!< I2C_T::CTL: AA Position                */
+#define I2C_CTL0_AA_Msk                  (0x1ul << I2C_CTL0_AA_Pos)                        /*!< I2C_T::CTL: AA Mask                    */
+
+#define I2C_CTL0_SI_Pos                  (3)                                               /*!< I2C_T::CTL: SI Position                */
+#define I2C_CTL0_SI_Msk                  (0x1ul << I2C_CTL0_SI_Pos)                        /*!< I2C_T::CTL: SI Mask                    */
+
+#define I2C_CTL0_STO_Pos                 (4)                                               /*!< I2C_T::CTL: STO Position               */
+#define I2C_CTL0_STO_Msk                 (0x1ul << I2C_CTL0_STO_Pos)                       /*!< I2C_T::CTL: STO Mask                   */
+
+#define I2C_CTL0_STA_Pos                 (5)                                               /*!< I2C_T::CTL: STA Position               */
+#define I2C_CTL0_STA_Msk                 (0x1ul << I2C_CTL0_STA_Pos)                       /*!< I2C_T::CTL: STA Mask                   */
+
+#define I2C_CTL0_I2CEN_Pos               (6)                                               /*!< I2C_T::CTL: I2CEN Position             */
+#define I2C_CTL0_I2CEN_Msk               (0x1ul << I2C_CTL0_I2CEN_Pos)                     /*!< I2C_T::CTL: I2CEN Mask                 */
+
+#define I2C_CTL0_INTEN_Pos               (7)                                               /*!< I2C_T::CTL: INTEN Position             */
+#define I2C_CTL0_INTEN_Msk               (0x1ul << I2C_CTL0_INTEN_Pos)                     /*!< I2C_T::CTL: INTEN Mask                 */
+
+#define I2C_ADDR0_GC_Pos                 (0)                                               /*!< I2C_T::ADDR0: GC Position              */
+#define I2C_ADDR0_GC_Msk                 (0x1ul << I2C_ADDR0_GC_Pos)                       /*!< I2C_T::ADDR0: GC Mask                  */
+
+#define I2C_ADDR0_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR0: ADDR Position            */
+#define I2C_ADDR0_ADDR_Msk               (0x3fful << I2C_ADDR0_ADDR_Pos)                   /*!< I2C_T::ADDR0: ADDR Mask                */
+
+#define I2C_DAT_DAT_Pos                  (0)                                               /*!< I2C_T::DAT: DAT Position               */
+#define I2C_DAT_DAT_Msk                  (0xfful << I2C_DAT_DAT_Pos)                       /*!< I2C_T::DAT: DAT Mask                   */
+
+#define I2C_STATUS0_STATUS_Pos           (0)                                               /*!< I2C_T::STATUS: STATUS Position         */
+#define I2C_STATUS0_STATUS_Msk           (0xfful << I2C_STATUS_STATUS0_Pos)                /*!< I2C_T::STATUS: STATUS Mask             */
+
+#define I2C_CLKDIV_DIVIDER_Pos           (0)                                               /*!< I2C_T::CLKDIV: DIVIDER Position        */
+#define I2C_CLKDIV_DIVIDER_Msk           (0x3fful << I2C_CLKDIV_DIVIDER_Pos)               /*!< I2C_T::CLKDIV: DIVIDER Mask            */
+
+#define I2C_TOCTL_TOIF_Pos               (0)                                               /*!< I2C_T::TOCTL: TOIF Position            */
+#define I2C_TOCTL_TOIF_Msk               (0x1ul << I2C_TOCTL_TOIF_Pos)                     /*!< I2C_T::TOCTL: TOIF Mask                */
+
+#define I2C_TOCTL_TOCDIV4_Pos            (1)                                               /*!< I2C_T::TOCTL: TOCDIV4 Position         */
+#define I2C_TOCTL_TOCDIV4_Msk            (0x1ul << I2C_TOCTL_TOCDIV4_Pos)                  /*!< I2C_T::TOCTL: TOCDIV4 Mask             */
+
+#define I2C_TOCTL_TOCEN_Pos              (2)                                               /*!< I2C_T::TOCTL: TOCEN Position           */
+#define I2C_TOCTL_TOCEN_Msk              (0x1ul << I2C_TOCTL_TOCEN_Pos)                    /*!< I2C_T::TOCTL: TOCEN Mask               */
+
+#define I2C_ADDR1_GC_Pos                 (0)                                               /*!< I2C_T::ADDR1: GC Position              */
+#define I2C_ADDR1_GC_Msk                 (0x1ul << I2C_ADDR1_GC_Pos)                       /*!< I2C_T::ADDR1: GC Mask                  */
+
+#define I2C_ADDR1_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR1: ADDR Position            */
+#define I2C_ADDR1_ADDR_Msk               (0x3fful << I2C_ADDR1_ADDR_Pos)                   /*!< I2C_T::ADDR1: ADDR Mask                */
+
+#define I2C_ADDR2_GC_Pos                 (0)                                               /*!< I2C_T::ADDR2: GC Position              */
+#define I2C_ADDR2_GC_Msk                 (0x1ul << I2C_ADDR2_GC_Pos)                       /*!< I2C_T::ADDR2: GC Mask                  */
+
+#define I2C_ADDR2_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR2: ADDR Position            */
+#define I2C_ADDR2_ADDR_Msk               (0x3fful << I2C_ADDR2_ADDR_Pos)                   /*!< I2C_T::ADDR2: ADDR Mask                */
+
+#define I2C_ADDR3_GC_Pos                 (0)                                               /*!< I2C_T::ADDR3: GC Position              */
+#define I2C_ADDR3_GC_Msk                 (0x1ul << I2C_ADDR3_GC_Pos)                       /*!< I2C_T::ADDR3: GC Mask                  */
+
+#define I2C_ADDR3_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR3: ADDR Position            */
+#define I2C_ADDR3_ADDR_Msk               (0x3fful << I2C_ADDR3_ADDR_Pos)                   /*!< I2C_T::ADDR3: ADDR Mask                */
+
+#define I2C_ADDRMSK0_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK0: ADDRMSK Position      */
+#define I2C_ADDRMSK0_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK0: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK1_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK1: ADDRMSK Position      */
+#define I2C_ADDRMSK1_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK1: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK2_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK2: ADDRMSK Position      */
+#define I2C_ADDRMSK2_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK2: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK3_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK3: ADDRMSK Position      */
+#define I2C_ADDRMSK3_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK3: ADDRMSK Mask          */
+
+#define I2C_WKCTL_WKEN_Pos               (0)                                               /*!< I2C_T::WKCTL: WKEN Position            */
+#define I2C_WKCTL_WKEN_Msk               (0x1ul << I2C_WKCTL_WKEN_Pos)                     /*!< I2C_T::WKCTL: WKEN Mask                */
+
+#define I2C_WKCTL_NHDBUSEN_Pos           (7)                                               /*!< I2C_T::WKCTL: NHDBUSEN Position        */
+#define I2C_WKCTL_NHDBUSEN_Msk           (0x1ul << I2C_WKCTL_NHDBUSEN_Pos)                 /*!< I2C_T::WKCTL: NHDBUSEN Mask            */
+
+#define I2C_WKSTS_WKIF_Pos               (0)                                               /*!< I2C_T::WKSTS: WKIF Position            */
+#define I2C_WKSTS_WKIF_Msk               (0x1ul << I2C_WKSTS_WKIF_Pos)                     /*!< I2C_T::WKSTS: WKIF Mask                */
+
+#define I2C_WKSTS_WKAKDONE_Pos           (1)                                               /*!< I2C_T::WKSTS: WKAKDONE Position        */
+#define I2C_WKSTS_WKAKDONE_Msk           (0x1ul << I2C_WKSTS_WKAKDONE_Pos)                 /*!< I2C_T::WKSTS: WKAKDONE Mask            */
+
+#define I2C_WKSTS_WRSTSWK_Pos            (2)                                               /*!< I2C_T::WKSTS: WRSTSWK Position         */
+#define I2C_WKSTS_WRSTSWK_Msk            (0x1ul << I2C_WKSTS_WRSTSWK_Pos)                  /*!< I2C_T::WKSTS: WRSTSWK Mask             */
+
+#define I2C_CTL1_TXPDMAEN_Pos            (0)                                               /*!< I2C_T::CTL1: TXPDMAEN Position         */
+#define I2C_CTL1_TXPDMAEN_Msk            (0x1ul << I2C_CTL1_TXPDMAEN_Pos)                  /*!< I2C_T::CTL1: TXPDMAEN Mask             */
+
+#define I2C_CTL1_RXPDMAEN_Pos            (1)                                               /*!< I2C_T::CTL1: RXPDMAEN Position         */
+#define I2C_CTL1_RXPDMAEN_Msk            (0x1ul << I2C_CTL1_RXPDMAEN_Pos)                  /*!< I2C_T::CTL1: RXPDMAEN Mask             */
+
+#define I2C_CTL1_PDMARST_Pos             (2)                                               /*!< I2C_T::CTL1: PDMARST Position          */
+#define I2C_CTL1_PDMARST_Msk             (0x1ul << I2C_CTL1_PDMARST_Pos)                   /*!< I2C_T::CTL1: PDMARST Mask              */
+
+#define I2C_CTL1_PDMASTR_Pos             (8)                                               /*!< I2C_T::CTL1: PDMASTR Position          */
+#define I2C_CTL1_PDMASTR_Msk             (0x1ul << I2C_CTL1_PDMASTR_Pos)                   /*!< I2C_T::CTL1: PDMASTR Mask              */
+
+#define I2C_CTL1_ADDR10EN_Pos            (9)                                               /*!< I2C_T::CTL1: ADDR10EN Position         */
+#define I2C_CTL1_ADDR10EN_Msk            (0x1ul << I2C_CTL1_ADDR10EN_Pos)                  /*!< I2C_T::CTL1: ADDR10EN Mask             */
+
+#define I2C_STATUS1_ADMAT0_Pos           (0)                                               /*!< I2C_T::STATUS1: ADMAT0 Position        */
+#define I2C_STATUS1_ADMAT0_Msk           (0x1ul << I2C_STATUS1_ADMAT0_Pos)                 /*!< I2C_T::STATUS1: ADMAT0 Mask            */
+
+#define I2C_STATUS1_ADMAT1_Pos           (1)                                               /*!< I2C_T::STATUS1: ADMAT1 Position        */
+#define I2C_STATUS1_ADMAT1_Msk           (0x1ul << I2C_STATUS1_ADMAT1_Pos)                 /*!< I2C_T::STATUS1: ADMAT1 Mask            */
+
+#define I2C_STATUS1_ADMAT2_Pos           (2)                                               /*!< I2C_T::STATUS1: ADMAT2 Position        */
+#define I2C_STATUS1_ADMAT2_Msk           (0x1ul << I2C_STATUS1_ADMAT2_Pos)                 /*!< I2C_T::STATUS1: ADMAT2 Mask            */
+
+#define I2C_STATUS1_ADMAT3_Pos           (3)                                               /*!< I2C_T::STATUS1: ADMAT3 Position        */
+#define I2C_STATUS1_ADMAT3_Msk           (0x1ul << I2C_STATUS1_ADMAT3_Pos)                 /*!< I2C_T::STATUS1: ADMAT3 Mask            */
+
+#define I2C_STATUS1_ONBUSY_Pos           (8)                                               /*!< I2C_T::STATUS1: ONBUSY Position        */
+#define I2C_STATUS1_ONBUSY_Msk           (0x1ul << I2C_STATUS1_ONBUSY_Pos)                 /*!< I2C_T::STATUS1: ONBUSY Mask            */
+
+#define I2C_TMCTL_STCTL_Pos              (0)                                               /*!< I2C_T::TMCTL: STCTL Position           */
+#define I2C_TMCTL_STCTL_Msk              (0x1fful << I2C_TMCTL_STCTL_Pos)                  /*!< I2C_T::TMCTL: STCTL Mask               */
+
+#define I2C_TMCTL_HTCTL_Pos              (16)                                              /*!< I2C_T::TMCTL: HTCTL Position           */
+#define I2C_TMCTL_HTCTL_Msk              (0x1fful << I2C_TMCTL_HTCTL_Pos)                  /*!< I2C_T::TMCTL: HTCTL Mask               */
+
+#define I2C_BUSCTL_ACKMEN_Pos            (0)                                               /*!< I2C_T::BUSCTL: ACKMEN Position         */
+#define I2C_BUSCTL_ACKMEN_Msk            (0x1ul << I2C_BUSCTL_ACKMEN_Pos)                  /*!< I2C_T::BUSCTL: ACKMEN Mask             */
+
+#define I2C_BUSCTL_PECEN_Pos             (1)                                               /*!< I2C_T::BUSCTL: PECEN Position          */
+#define I2C_BUSCTL_PECEN_Msk             (0x1ul << I2C_BUSCTL_PECEN_Pos)                   /*!< I2C_T::BUSCTL: PECEN Mask              */
+
+#define I2C_BUSCTL_BMDEN_Pos             (2)                                               /*!< I2C_T::BUSCTL: BMDEN Position          */
+#define I2C_BUSCTL_BMDEN_Msk             (0x1ul << I2C_BUSCTL_BMDEN_Pos)                   /*!< I2C_T::BUSCTL: BMDEN Mask              */
+
+#define I2C_BUSCTL_BMHEN_Pos             (3)                                               /*!< I2C_T::BUSCTL: BMHEN Position          */
+#define I2C_BUSCTL_BMHEN_Msk             (0x1ul << I2C_BUSCTL_BMHEN_Pos)                   /*!< I2C_T::BUSCTL: BMHEN Mask              */
+
+#define I2C_BUSCTL_ALERTEN_Pos           (4)                                               /*!< I2C_T::BUSCTL: ALERTEN Position        */
+#define I2C_BUSCTL_ALERTEN_Msk           (0x1ul << I2C_BUSCTL_ALERTEN_Pos)                 /*!< I2C_T::BUSCTL: ALERTEN Mask            */
+
+#define I2C_BUSCTL_SCTLOSTS_Pos          (5)                                               /*!< I2C_T::BUSCTL: SCTLOSTS Position       */
+#define I2C_BUSCTL_SCTLOSTS_Msk          (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)                /*!< I2C_T::BUSCTL: SCTLOSTS Mask           */
+
+#define I2C_BUSCTL_SCTLOEN_Pos           (6)                                               /*!< I2C_T::BUSCTL: SCTLOEN Position        */
+#define I2C_BUSCTL_SCTLOEN_Msk           (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)                 /*!< I2C_T::BUSCTL: SCTLOEN Mask            */
+
+#define I2C_BUSCTL_BUSEN_Pos             (7)                                               /*!< I2C_T::BUSCTL: BUSEN Position          */
+#define I2C_BUSCTL_BUSEN_Msk             (0x1ul << I2C_BUSCTL_BUSEN_Pos)                   /*!< I2C_T::BUSCTL: BUSEN Mask              */
+
+#define I2C_BUSCTL_PECTXEN_Pos           (8)                                               /*!< I2C_T::BUSCTL: PECTXEN Position        */
+#define I2C_BUSCTL_PECTXEN_Msk           (0x1ul << I2C_BUSCTL_PECTXEN_Pos)                 /*!< I2C_T::BUSCTL: PECTXEN Mask            */
+
+#define I2C_BUSCTL_TIDLE_Pos             (9)                                               /*!< I2C_T::BUSCTL: TIDLE Position          */
+#define I2C_BUSCTL_TIDLE_Msk             (0x1ul << I2C_BUSCTL_TIDLE_Pos)                   /*!< I2C_T::BUSCTL: TIDLE Mask              */
+
+#define I2C_BUSCTL_PECCLR_Pos            (10)                                              /*!< I2C_T::BUSCTL: PECCLR Position         */
+#define I2C_BUSCTL_PECCLR_Msk            (0x1ul << I2C_BUSCTL_PECCLR_Pos)                  /*!< I2C_T::BUSCTL: PECCLR Mask             */
+
+#define I2C_BUSCTL_ACKM9SI_Pos           (11)                                              /*!< I2C_T::BUSCTL: ACKM9SI Position        */
+#define I2C_BUSCTL_ACKM9SI_Msk           (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)                 /*!< I2C_T::BUSCTL: ACKM9SI Mask            */
+
+#define I2C_BUSCTL_BCDIEN_Pos            (12)                                              /*!< I2C_T::BUSCTL: BCDIEN Position         */
+#define I2C_BUSCTL_BCDIEN_Msk            (0x1ul << I2C_BUSCTL_BCDIEN_Pos)                  /*!< I2C_T::BUSCTL: BCDIEN Mask             */
+
+#define I2C_BUSCTL_PECDIEN_Pos           (13)                                              /*!< I2C_T::BUSCTL: PECDIEN Position        */
+#define I2C_BUSCTL_PECDIEN_Msk           (0x1ul << I2C_BUSCTL_PECDIEN_Pos)                 /*!< I2C_T::BUSCTL: PECDIEN Mask            */
+
+#define I2C_BUSTCTL_BUSTOEN_Pos          (0)                                               /*!< I2C_T::BUSTCTL: BUSTOEN Position       */
+#define I2C_BUSTCTL_BUSTOEN_Msk          (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)                /*!< I2C_T::BUSTCTL: BUSTOEN Mask           */
+
+#define I2C_BUSTCTL_CLKTOEN_Pos          (1)                                               /*!< I2C_T::BUSTCTL: CLKTOEN Position       */
+#define I2C_BUSTCTL_CLKTOEN_Msk          (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)                /*!< I2C_T::BUSTCTL: CLKTOEN Mask           */
+
+#define I2C_BUSTCTL_BUSTOIEN_Pos         (2)                                               /*!< I2C_T::BUSTCTL: BUSTOIEN Position      */
+#define I2C_BUSTCTL_BUSTOIEN_Msk         (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)               /*!< I2C_T::BUSTCTL: BUSTOIEN Mask          */
+
+#define I2C_BUSTCTL_CLKTOIEN_Pos         (3)                                               /*!< I2C_T::BUSTCTL: CLKTOIEN Position      */
+#define I2C_BUSTCTL_CLKTOIEN_Msk         (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)               /*!< I2C_T::BUSTCTL: CLKTOIEN Mask          */
+
+#define I2C_BUSTCTL_TORSTEN_Pos          (4)                                               /*!< I2C_T::BUSTCTL: TORSTEN Position       */
+#define I2C_BUSTCTL_TORSTEN_Msk          (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)                /*!< I2C_T::BUSTCTL: TORSTEN Mask           */
+
+#define I2C_BUSSTS_BUSY_Pos              (0)                                               /*!< I2C_T::BUSSTS: BUSY Position           */
+#define I2C_BUSSTS_BUSY_Msk              (0x1ul << I2C_BUSSTS_BUSY_Pos)                    /*!< I2C_T::BUSSTS: BUSY Mask               */
+
+#define I2C_BUSSTS_BCDONE_Pos            (1)                                               /*!< I2C_T::BUSSTS: BCDONE Position         */
+#define I2C_BUSSTS_BCDONE_Msk            (0x1ul << I2C_BUSSTS_BCDONE_Pos)                  /*!< I2C_T::BUSSTS: BCDONE Mask             */
+
+#define I2C_BUSSTS_PECERR_Pos            (2)                                               /*!< I2C_T::BUSSTS: PECERR Position         */
+#define I2C_BUSSTS_PECERR_Msk            (0x1ul << I2C_BUSSTS_PECERR_Pos)                  /*!< I2C_T::BUSSTS: PECERR Mask             */
+
+#define I2C_BUSSTS_ALERT_Pos             (3)                                               /*!< I2C_T::BUSSTS: ALERT Position          */
+#define I2C_BUSSTS_ALERT_Msk             (0x1ul << I2C_BUSSTS_ALERT_Pos)                   /*!< I2C_T::BUSSTS: ALERT Mask              */
+
+#define I2C_BUSSTS_SCTLDIN_Pos           (4)                                               /*!< I2C_T::BUSSTS: SCTLDIN Position        */
+#define I2C_BUSSTS_SCTLDIN_Msk           (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)                 /*!< I2C_T::BUSSTS: SCTLDIN Mask            */
+
+#define I2C_BUSSTS_BUSTO_Pos             (5)                                               /*!< I2C_T::BUSSTS: BUSTO Position          */
+#define I2C_BUSSTS_BUSTO_Msk             (0x1ul << I2C_BUSSTS_BUSTO_Pos)                   /*!< I2C_T::BUSSTS: BUSTO Mask              */
+
+#define I2C_BUSSTS_CLKTO_Pos             (6)                                               /*!< I2C_T::BUSSTS: CLKTO Position          */
+#define I2C_BUSSTS_CLKTO_Msk             (0x1ul << I2C_BUSSTS_CLKTO_Pos)                   /*!< I2C_T::BUSSTS: CLKTO Mask              */
+
+#define I2C_BUSSTS_PECDONE_Pos           (7)                                               /*!< I2C_T::BUSSTS: PECDONE Position        */
+#define I2C_BUSSTS_PECDONE_Msk           (0x1ul << I2C_BUSSTS_PECDONE_Pos)                 /*!< I2C_T::BUSSTS: PECDONE Mask            */
+
+#define I2C_PKTSIZE_PLDSIZE_Pos          (0)                                               /*!< I2C_T::PKTSIZE: PLDSIZE Position       */
+#define I2C_PKTSIZE_PLDSIZE_Msk          (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos)              /*!< I2C_T::PKTSIZE: PLDSIZE Mask           */
+
+#define I2C_PKTCRC_PECCRC_Pos            (0)                                               /*!< I2C_T::PKTCRC: PECCRC Position         */
+#define I2C_PKTCRC_PECCRC_Msk            (0xfful << I2C_PKTCRC_PECCRC_Pos)                 /*!< I2C_T::PKTCRC: PECCRC Mask             */
+
+#define I2C_BUSTOUT_BUSTO_Pos            (0)                                               /*!< I2C_T::BUSTOUT: BUSTO Position         */
+#define I2C_BUSTOUT_BUSTO_Msk            (0xfful << I2C_BUSTOUT_BUSTO_Pos)                 /*!< I2C_T::BUSTOUT: BUSTO Mask             */
+
+#define I2C_CLKTOUT_CLKTO_Pos            (0)                                               /*!< I2C_T::CLKTOUT: CLKTO Position         */
+#define I2C_CLKTOUT_CLKTO_Msk            (0xfful << I2C_CLKTOUT_CLKTO_Pos)                 /*!< I2C_T::CLKTOUT: CLKTO Mask             */
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+
+
+/*---------------------- UART Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup UUART UART Mode of USCI Controller(UUART)
+    Memory Mapped Structure for UUART Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var UUART_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Note: Other bit combinations are reserved.
+     * @var UUART_T::INTEN
+     * Offset: 0x04  USCI Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIEN   |Transmit Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit start event.
+     * |        |          |0 = The transmit start interrupt is disabled.
+     * |        |          |1 = The transmit start interrupt is enabled.
+     * |[2]     |TXENDIEN  |Transmit End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit finish event.
+     * |        |          |0 = The transmit finish interrupt is disabled.
+     * |        |          |1 = The transmit finish interrupt is enabled.
+     * |[3]     |RXSTIEN   |Receive Start Interrupt Enable BIt
+     * |        |          |This bit enables the interrupt generation in case of a receive start event.
+     * |        |          |0 = The receive start interrupt is disabled.
+     * |        |          |1 = The receive start interrupt is enabled.
+     * |[4]     |RXENDIEN  |Receive End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive finish event.
+     * |        |          |0 = The receive end interrupt is disabled.
+     * |        |          |1 = The receive end interrupt is enabled.
+     * @var UUART_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source signal of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source signal of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fSAMP_CLK = fDIV_CLK.
+     * |        |          |01 = fSAMP_CLK = fPROT_CLK.
+     * |        |          |10 = fSAMP_CLK = fSCLK.
+     * |        |          |11 = fSAMP_CLK = fREF_CLK.
+     * |[4]     |TMCNTEN   |Timing Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Timing measurement counter is Disabled.
+     * |        |          |1 = Timing measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Timing Measurement Counter Clock Source Selection
+     * |        |          |0 = Timing measurement counter with fPROT_CLK.
+     * |        |          |1 = Timing measurement counter with fDIV_CLK.
+     * |[9:8]   |PDSCNT    |Pre-divider for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
+     * |        |          |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+     * |[14:10] |DSCNT     |Denominator for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+     * |        |          |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+     * |        |          |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and
+     * |        |          |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55
+     * |        |          |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var UUART_T::DATIN0
+     * Offset: 0x10  USCI Input Data Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Signal Synchronization Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or
+     * |        |          |the synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * |[4:3]   |EDGEDET   |Input Signal   Edge Detection Mode
+     * |        |          |This bit field selects which edge actives the trigger event of input data signal.
+     * |        |          |00 = The trigger event activation is disabled.
+     * |        |          |01 = A rising   edge activates the trigger event of input data signal.
+     * |        |          |10 = A falling edge activates the trigger event of input data signal.
+     * |        |          |11 = Both edges activate the trigger event of input data signal.
+     * |        |          |Note: In UART function mode, it is suggested to   set this bit field as 10.
+     * @var UUART_T::CTLIN0
+     * Offset: 0x20  USCI Input Control Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or
+     * |        |          |the synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The   synchronized signal can be taken as input for the data shift unit.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * @var UUART_T::CLKIN
+     * Offset: 0x28  USCI Input Clock Signal Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal or
+     * |        |          |the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * @var UUART_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[5]     |DATOINV   |Data Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
+     * |        |          |0 = The value of USCIx_DAT1 is equal to the data shift register.
+     * |        |          |1 = The value of USCIx_DAT1 is the inversion of data shift register.
+     * |[7]     |CTLOINV   |Control Signal Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal control signal and the output control signal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = The control signal will be inverted before its output.
+     * |        |          |Note: In UART protocol, the control signal means nRTS signal.
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0: The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1: Reserved.
+     * |        |          |0x2: Reserved.
+     * |        |          |0x3: Reserved.
+     * |        |          |0x4: The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5: The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |..
+     * |        |          |0xF: The data word contains 15 bits located at bit positions [14:0].
+     * |        |          |Note: In UART protocol, the length can be configured as 6~13 bits.
+     * @var UUART_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission.
+     * @var UUART_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * |        |          |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
+     * @var UUART_T::BUFCTL
+     * Offset: 0x38  USCI Transmit/Receive Buffer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7]     |TXCLR     |Clear Transmit Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[14]    |RXOVIEN   |Receive Buffer Overrun Error Interrupt Enable Control
+     * |        |          |0 = Receive overrun interrupt Disabled.
+     * |        |          |1 = Receive overrun interrupt Enabled.
+     * |[15]    |RXCLR     |Clear Receive Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[16]    |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[17]    |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+     * |        |          |Note 1: It is cleared automatically after one PCLK cycle.
+     * |        |          |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1.
+     * @var UUART_T::BUFSTS
+     * Offset: 0x3C  USCI Transmit/Receive Buffer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXEMPTY   |Receive Buffer Empty Indicator
+     * |        |          |0 = Receive buffer is not empty.
+     * |        |          |1 = Receive buffer is empty.
+     * |[1]     |RXFULL    |Receive Buffer Full Indicator
+     * |        |          |0 = Receive buffer is not full.
+     * |        |          |1 = Receive buffer is full.
+     * |[3]     |RXOVIF    |Receive Buffer Over-run Error Interrupt Status
+     * |        |          |This bit indicates that a receive buffer overrun error event has been detected
+     * |        |          |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
+     * |        |          |It is cleared by software writes 1 to this bit.
+     * |        |          |0 = A receive buffer overrun error event has not been detected.
+     * |        |          |1 = A receive buffer overrun error event has been detected.
+     * |[8]     |TXEMPTY   |Transmit Buffer Empty Indicator
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty.
+     * |[9]     |TXFULL    |Transmit Buffer Full Indicator
+     * |        |          |0 = Transmit buffer is not full.
+     * |        |          |1 = Transmit buffer is full.
+     * @var UUART_T::PDMACTL
+     * Offset: 0x40  USCI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
+     * |[1]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[2]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[3]     |PDMAEN    |PDMA Mode Enable Bit
+     * |        |          |0 = PDMA function Disabled.
+     * |        |          |1 = PDMA function Enabled.
+     * @var UUART_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[2]     |PDBOPT    |Power Down Blocking Option
+     * |        |          |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+     * |        |          |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+     * @var UUART_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var UUART_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |STOPB     |Stop Bits
+     * |        |          |This bit defines the number of stop bits in an UART frame.
+     * |        |          |0 = The number of stop bits is 1.
+     * |        |          |1 = The number of stop bits is 2.
+     * |[1]     |PARITYEN  |Parity Enable Bit
+     * |        |          |This bit defines the parity bit is enabled in an UART frame.
+     * |        |          |0 = The parity bit Disabled.
+     * |        |          |1 = The parity bit Enabled.
+     * |[2]     |EVENPARITY|Even Parity Enable Bit
+     * |        |          |0 = Odd number of logic 1's is transmitted and checked in each word.
+     * |        |          |1 = Even number of logic 1's is transmitted and checked in each word.
+     * |        |          |Note: This bit has effect only when PARITYEN is set.
+     * |[3]     |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
+     * |        |          |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal.
+     * |        |          |0 = nRTS auto-flow control Disabled.
+     * |        |          |1 = nRTS auto-flow control Enabled.
+     * |        |          |Note: This bit has effect only when the RTSAUDIREN is not set.
+     * |[4]     |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
+     * |        |          |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
+     * |        |          |0 = nCTS auto-flow control Disabled.
+     * |        |          |1 = nCTS auto-flow control Enabled.
+     * |[5]     |RTSAUDIREN|nRTS Auto Direction Enable Bit
+     * |        |          |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
+     * |        |          |0 = nRTS auto direction control Disabled.
+     * |        |          |1 = nRTS auto direction control Enabled.
+     * |        |          |Note 1: This bit is used for nRTS auto direction control for RS485.
+     * |        |          |Note 2: This bit has effect only when the RTSAUTOEN is not set.
+     * |[6]     |ABREN     |Auto-baud Rate Detect Enable Bit
+     * |        |          |0 = Auto-baud rate detect function Disabled.
+     * |        |          |1 = Auto-baud rate detect function Enabled.
+     * |        |          |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit
+     * |        |          |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled).
+     * |[9]     |DATWKEN   |Data Wake-up Mode Enable Bit
+     * |        |          |0 = Data wake-up mode Disabled.
+     * |        |          |1 = Data wake-up mode Enabled.
+     * |[10]    |CTSWKEN   |nCTS Wake-up Mode Enable Bit
+     * |        |          |0 = nCTS wake-up mode Disabled.
+     * |        |          |1 = nCTS wake-up mode Enabled.
+     * |[14:11] |WAKECNT   |Wake-up Counter
+     * |        |          |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
+     * |[24:16] |BRDETITV  |Baud Rate Detection Interval
+     * |        |          |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits
+     * |        |          |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55)
+     * |        |          |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set.
+     * |        |          |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
+     * |[26]    |STICKEN   |Stick Parity Enable Bit
+     * |        |          |0 = Stick parity Disabled.
+     * |        |          |1 = Stick parity Enabled.
+     * |        |          |Note: Refer to RS-485 Support section for detail information.
+     * |[29]    |BCEN      |Transmit Break Control Enable Bit
+     * |        |          |0 = Transmit Break Control Disabled.
+     * |        |          |1 = Transmit Break Control Enabled.
+     * |        |          |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0)
+     * |        |          |This bit acts only on TX line and has no effect on the transmitter logic.
+     * |[31]    |PROTEN    |UART Protocol Enable Bit
+     * |        |          |0 = UART Protocol Disabled.
+     * |        |          |1 = UART Protocol Enabled.
+     * @var UUART_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |ABRIEN    |Auto-baud Rate Interrupt Enable Bit
+     * |        |          |0 = Auto-baud rate interrupt Disabled.
+     * |        |          |1 = Auto-baud rate interrupt Enabled.
+     * |[2]     |RLSIEN    |Receive Line Status Interrupt Enable Bit
+     * |        |          |0 = Receive line status interrupt Disabled.
+     * |        |          |1 = Receive line status interrupt Enabled.
+     * |        |          |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
+     * @var UUART_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIF    |Transmit Start Interrupt Flag
+     * |        |          |0 = A transmit start interrupt status has not occurred.
+     * |        |          |1 = A transmit start interrupt status has occurred.
+     * |        |          |Note 1: It is cleared by software writing one into this bit.
+     * |        |          |Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
+     * |[2]     |TXENDIF   |Transmit End Interrupt Flag
+     * |        |          |0 = A transmit end interrupt status has not occurred.
+     * |        |          |1 = A transmit end interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[3]     |RXSTIF    |Receive Start Interrupt Flag
+     * |        |          |0 = A receive start interrupt status has not occurred.
+     * |        |          |1 = A receive start interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[4]     |RXENDIF   |Receive End Interrupt Flag
+     * |        |          |0 = A receive finish interrupt status has not occurred.
+     * |        |          |1 = A receive finish interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[5]     |PARITYERR |Parity Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
+     * |        |          |0 = No parity error is generated.
+     * |        |          |1 = Parity error is generated.
+     * |        |          |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+     * |[6]     |FRMERR    |Framing Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
+     * |        |          |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = No framing error is generated.
+     * |        |          |1 = Framing error is generated.
+     * |        |          |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+     * |[7]     |BREAK     |Break Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state'
+     * |        |          |(logic 0) for longer than a full word transmission time (that is, the total time of  start bit + data bits + parity + stop bits).
+     * |        |          |0 = No Break is generated.
+     * |        |          |1 = Break is generated in the receiver bus.
+     * |        |          |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
+     * |[9]     |ABRDETIF  |Auto-baud Rate Interrupt Flag
+     * |        |          |This bit is set when auto-baud rate detection is done among the falling edge of the input data
+     * |        |          |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated
+     * |        |          |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
+     * |        |          |0 = Auto-baud rate detect function is not done.
+     * |        |          |1 = One Bit auto-baud rate detect function is done.
+     * |        |          |Note: This bit can be cleared by writing '1' to it.
+     * |[10]    |RXBUSY    |RX Bus Status Flag (Read Only)
+     * |        |          |This bit indicates the busy status of the receiver.
+     * |        |          |0 = The receiver is Idle.
+     * |        |          |1 = The receiver is BUSY.
+     * |[11]    |ABERRSTS  |Auto-baud Rate Error Status
+     * |        |          |This bit is set when auto-baud rate detection counter overrun
+     * |        |          |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and
+     * |        |          |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again.
+     * |        |          |0 = Auto-baud rate detect counter is not overrun.
+     * |        |          |1 = Auto-baud rate detect counter is overrun.
+     * |        |          |Note 1: This bit is set at the same time of ABRDETIF.
+     * |        |          |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
+     * |[16]    |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
+     * |        |          |This bit used to indicate the current status of the internal synchronized nCTS signal.
+     * |        |          |0 = The internal synchronized nCTS is low.
+     * |        |          |1 = The internal synchronized nCTS is high.
+     * |[17]    |CTSLV     |nCTS Pin Status (Read Only)
+     * |        |          |This bit used to monitor the current status of nCTS pin input.
+     * |        |          |0 = nCTS pin input is low level voltage logic state.
+     * |        |          |1 = nCTS pin input is high level voltage logic state.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] USCI Interrupt Enable Register                                   */
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DATIN0;                /*!< [0x0010] USCI Input Data Signal Configuration Register 0                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTLIN0;                /*!< [0x0020] USCI Input Control Signal Configuration Register 0               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CLKIN;                 /*!< [0x0028] USCI Input Clock Signal Configuration Register                   */
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __IO uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __IO uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    __IO uint32_t BUFCTL;                /*!< [0x0038] USCI Transmit/Receive Buffer Control Register                    */
+    __IO uint32_t BUFSTS;                /*!< [0x003c] USCI Transmit/Receive Buffer Status Register                     */
+    __IO uint32_t PDMACTL;               /*!< [0x0040] USCI PDMA Control Register                                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[4];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+
+} UUART_T;
+
+/**
+    @addtogroup UUART_CONST UUART Bit Field Definition
+    Constant Definitions for UUART Controller
+@{ */
+
+#define UUART_CTL_FUNMODE_Pos            (0)                                               /*!< UUART_T::CTL: FUNMODE Position         */
+#define UUART_CTL_FUNMODE_Msk            (0x7ul << UUART_CTL_FUNMODE_Pos)                  /*!< UUART_T::CTL: FUNMODE Mask             */
+
+#define UUART_INTEN_TXSTIEN_Pos          (1)                                               /*!< UUART_T::INTEN: TXSTIEN Position       */
+#define UUART_INTEN_TXSTIEN_Msk          (0x1ul << UUART_INTEN_TXSTIEN_Pos)                /*!< UUART_T::INTEN: TXSTIEN Mask           */
+
+#define UUART_INTEN_TXENDIEN_Pos         (2)                                               /*!< UUART_T::INTEN: TXENDIEN Position      */
+#define UUART_INTEN_TXENDIEN_Msk         (0x1ul << UUART_INTEN_TXENDIEN_Pos)               /*!< UUART_T::INTEN: TXENDIEN Mask          */
+
+#define UUART_INTEN_RXSTIEN_Pos          (3)                                               /*!< UUART_T::INTEN: RXSTIEN Position       */
+#define UUART_INTEN_RXSTIEN_Msk          (0x1ul << UUART_INTEN_RXSTIEN_Pos)                /*!< UUART_T::INTEN: RXSTIEN Mask           */
+
+#define UUART_INTEN_RXENDIEN_Pos         (4)                                               /*!< UUART_T::INTEN: RXENDIEN Position      */
+#define UUART_INTEN_RXENDIEN_Msk         (0x1ul << UUART_INTEN_RXENDIEN_Pos)               /*!< UUART_T::INTEN: RXENDIEN Mask          */
+
+#define UUART_BRGEN_RCLKSEL_Pos          (0)                                               /*!< UUART_T::BRGEN: RCLKSEL Position       */
+#define UUART_BRGEN_RCLKSEL_Msk          (0x1ul << UUART_BRGEN_RCLKSEL_Pos)                /*!< UUART_T::BRGEN: RCLKSEL Mask           */
+
+#define UUART_BRGEN_PTCLKSEL_Pos         (1)                                               /*!< UUART_T::BRGEN: PTCLKSEL Position      */
+#define UUART_BRGEN_PTCLKSEL_Msk         (0x1ul << UUART_BRGEN_PTCLKSEL_Pos)               /*!< UUART_T::BRGEN: PTCLKSEL Mask          */
+
+#define UUART_BRGEN_SPCLKSEL_Pos         (2)                                               /*!< UUART_T::BRGEN: SPCLKSEL Position      */
+#define UUART_BRGEN_SPCLKSEL_Msk         (0x3ul << UUART_BRGEN_SPCLKSEL_Pos)               /*!< UUART_T::BRGEN: SPCLKSEL Mask          */
+
+#define UUART_BRGEN_TMCNTEN_Pos          (4)                                               /*!< UUART_T::BRGEN: TMCNTEN Position       */
+#define UUART_BRGEN_TMCNTEN_Msk          (0x1ul << UUART_BRGEN_TMCNTEN_Pos)                /*!< UUART_T::BRGEN: TMCNTEN Mask           */
+
+#define UUART_BRGEN_TMCNTSRC_Pos         (5)                                               /*!< UUART_T::BRGEN: TMCNTSRC Position      */
+#define UUART_BRGEN_TMCNTSRC_Msk         (0x1ul << UUART_BRGEN_TMCNTSRC_Pos)               /*!< UUART_T::BRGEN: TMCNTSRC Mask          */
+
+#define UUART_BRGEN_PDSCNT_Pos           (8)                                               /*!< UUART_T::BRGEN: PDSCNT Position        */
+#define UUART_BRGEN_PDSCNT_Msk           (0x3ul << UUART_BRGEN_PDSCNT_Pos)                 /*!< UUART_T::BRGEN: PDSCNT Mask            */
+
+#define UUART_BRGEN_DSCNT_Pos            (10)                                              /*!< UUART_T::BRGEN: DSCNT Position         */
+#define UUART_BRGEN_DSCNT_Msk            (0x1ful << UUART_BRGEN_DSCNT_Pos)                 /*!< UUART_T::BRGEN: DSCNT Mask             */
+
+#define UUART_BRGEN_CLKDIV_Pos           (16)                                              /*!< UUART_T::BRGEN: CLKDIV Position        */
+#define UUART_BRGEN_CLKDIV_Msk           (0x3fful << UUART_BRGEN_CLKDIV_Pos)               /*!< UUART_T::BRGEN: CLKDIV Mask            */
+
+#define UUART_DATIN0_SYNCSEL_Pos         (0)                                               /*!< UUART_T::DATIN0: SYNCSEL Position      */
+#define UUART_DATIN0_SYNCSEL_Msk         (0x1ul << UUART_DATIN0_SYNCSEL_Pos)               /*!< UUART_T::DATIN0: SYNCSEL Mask          */
+
+#define UUART_DATIN0_ININV_Pos           (2)                                               /*!< UUART_T::DATIN0: ININV Position        */
+#define UUART_DATIN0_ININV_Msk           (0x1ul << UUART_DATIN0_ININV_Pos)                 /*!< UUART_T::DATIN0: ININV Mask            */
+
+#define UUART_DATIN0_EDGEDET_Pos         (3)                                               /*!< UUART_T::DATIN0: EDGEDET Position      */
+#define UUART_DATIN0_EDGEDET_Msk         (0x3ul << UUART_DATIN0_EDGEDET_Pos)               /*!< UUART_T::DATIN0: EDGEDET Mask          */
+
+#define UUART_CTLIN0_SYNCSEL_Pos         (0)                                               /*!< UUART_T::CTLIN0: SYNCSEL Position      */
+#define UUART_CTLIN0_SYNCSEL_Msk         (0x1ul << UUART_CTLIN0_SYNCSEL_Pos)               /*!< UUART_T::CTLIN0: SYNCSEL Mask          */
+
+#define UUART_CTLIN0_ININV_Pos           (2)                                               /*!< UUART_T::CTLIN0: ININV Position        */
+#define UUART_CTLIN0_ININV_Msk           (0x1ul << UUART_CTLIN0_ININV_Pos)                 /*!< UUART_T::CTLIN0: ININV Mask            */
+
+#define UUART_CLKIN_SYNCSEL_Pos          (0)                                               /*!< UUART_T::CLKIN: SYNCSEL Position       */
+#define UUART_CLKIN_SYNCSEL_Msk          (0x1ul << UUART_CLKIN_SYNCSEL_Pos)                /*!< UUART_T::CLKIN: SYNCSEL Mask           */
+
+#define UUART_LINECTL_LSB_Pos            (0)                                               /*!< UUART_T::LINECTL: LSB Position         */
+#define UUART_LINECTL_LSB_Msk            (0x1ul << UUART_LINECTL_LSB_Pos)                  /*!< UUART_T::LINECTL: LSB Mask             */
+
+#define UUART_LINECTL_DATOINV_Pos        (5)                                               /*!< UUART_T::LINECTL: DATOINV Position     */
+#define UUART_LINECTL_DATOINV_Msk        (0x1ul << UUART_LINECTL_DATOINV_Pos)              /*!< UUART_T::LINECTL: DATOINV Mask         */
+
+#define UUART_LINECTL_CTLOINV_Pos        (7)                                               /*!< UUART_T::LINECTL: CTLOINV Position     */
+#define UUART_LINECTL_CTLOINV_Msk        (0x1ul << UUART_LINECTL_CTLOINV_Pos)              /*!< UUART_T::LINECTL: CTLOINV Mask         */
+
+#define UUART_LINECTL_DWIDTH_Pos         (8)                                               /*!< UUART_T::LINECTL: DWIDTH Position      */
+#define UUART_LINECTL_DWIDTH_Msk         (0xful << UUART_LINECTL_DWIDTH_Pos)               /*!< UUART_T::LINECTL: DWIDTH Mask          */
+
+#define UUART_TXDAT_TXDAT_Pos            (0)                                               /*!< UUART_T::TXDAT: TXDAT Position         */
+#define UUART_TXDAT_TXDAT_Msk            (0xfffful << UUART_TXDAT_TXDAT_Pos)               /*!< UUART_T::TXDAT: TXDAT Mask             */
+
+#define UUART_RXDAT_RXDAT_Pos            (0)                                               /*!< UUART_T::RXDAT: RXDAT Position         */
+#define UUART_RXDAT_RXDAT_Msk            (0xfffful << UUART_RXDAT_RXDAT_Pos)               /*!< UUART_T::RXDAT: RXDAT Mask             */
+
+#define UUART_BUFCTL_TXCLR_Pos           (7)                                               /*!< UUART_T::BUFCTL: TXCLR Position        */
+#define UUART_BUFCTL_TXCLR_Msk           (0x1ul << UUART_BUFCTL_TXCLR_Pos)                 /*!< UUART_T::BUFCTL: TXCLR Mask            */
+
+#define UUART_BUFCTL_RXOVIEN_Pos         (14)                                              /*!< UUART_T::BUFCTL: RXOVIEN Position      */
+#define UUART_BUFCTL_RXOVIEN_Msk         (0x1ul << UUART_BUFCTL_RXOVIEN_Pos)               /*!< UUART_T::BUFCTL: RXOVIEN Mask          */
+
+#define UUART_BUFCTL_RXCLR_Pos           (15)                                              /*!< UUART_T::BUFCTL: RXCLR Position        */
+#define UUART_BUFCTL_RXCLR_Msk           (0x1ul << UUART_BUFCTL_RXCLR_Pos)                 /*!< UUART_T::BUFCTL: RXCLR Mask            */
+
+#define UUART_BUFCTL_TXRST_Pos           (16)                                              /*!< UUART_T::BUFCTL: TXRST Position        */
+#define UUART_BUFCTL_TXRST_Msk           (0x1ul << UUART_BUFCTL_TXRST_Pos)                 /*!< UUART_T::BUFCTL: TXRST Mask            */
+
+#define UUART_BUFCTL_RXRST_Pos           (17)                                              /*!< UUART_T::BUFCTL: RXRST Position        */
+#define UUART_BUFCTL_RXRST_Msk           (0x1ul << UUART_BUFCTL_RXRST_Pos)                 /*!< UUART_T::BUFCTL: RXRST Mask            */
+
+#define UUART_BUFSTS_RXEMPTY_Pos         (0)                                               /*!< UUART_T::BUFSTS: RXEMPTY Position      */
+#define UUART_BUFSTS_RXEMPTY_Msk         (0x1ul << UUART_BUFSTS_RXEMPTY_Pos)               /*!< UUART_T::BUFSTS: RXEMPTY Mask          */
+
+#define UUART_BUFSTS_RXFULL_Pos          (1)                                               /*!< UUART_T::BUFSTS: RXFULL Position       */
+#define UUART_BUFSTS_RXFULL_Msk          (0x1ul << UUART_BUFSTS_RXFULL_Pos)                /*!< UUART_T::BUFSTS: RXFULL Mask           */
+
+#define UUART_BUFSTS_RXOVIF_Pos          (3)                                               /*!< UUART_T::BUFSTS: RXOVIF Position       */
+#define UUART_BUFSTS_RXOVIF_Msk          (0x1ul << UUART_BUFSTS_RXOVIF_Pos)                /*!< UUART_T::BUFSTS: RXOVIF Mask           */
+
+#define UUART_BUFSTS_TXEMPTY_Pos         (8)                                               /*!< UUART_T::BUFSTS: TXEMPTY Position      */
+#define UUART_BUFSTS_TXEMPTY_Msk         (0x1ul << UUART_BUFSTS_TXEMPTY_Pos)               /*!< UUART_T::BUFSTS: TXEMPTY Mask          */
+
+#define UUART_BUFSTS_TXFULL_Pos          (9)                                               /*!< UUART_T::BUFSTS: TXFULL Position       */
+#define UUART_BUFSTS_TXFULL_Msk          (0x1ul << UUART_BUFSTS_TXFULL_Pos)                /*!< UUART_T::BUFSTS: TXFULL Mask           */
+
+#define UUART_PDMACTL_PDMARST_Pos        (0)                                               /*!< UUART_T::PDMACTL: PDMARST Position     */
+#define UUART_PDMACTL_PDMARST_Msk        (0x1ul << UUART_PDMACTL_PDMARST_Pos)              /*!< UUART_T::PDMACTL: PDMARST Mask         */
+
+#define UUART_PDMACTL_TXPDMAEN_Pos       (1)                                               /*!< UUART_T::PDMACTL: TXPDMAEN Position    */
+#define UUART_PDMACTL_TXPDMAEN_Msk       (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos)             /*!< UUART_T::PDMACTL: TXPDMAEN Mask        */
+
+#define UUART_PDMACTL_RXPDMAEN_Pos       (2)                                               /*!< UUART_T::PDMACTL: RXPDMAEN Position    */
+#define UUART_PDMACTL_RXPDMAEN_Msk       (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos)             /*!< UUART_T::PDMACTL: RXPDMAEN Mask        */
+
+#define UUART_PDMACTL_PDMAEN_Pos         (3)                                               /*!< UUART_T::PDMACTL: PDMAEN Position      */
+#define UUART_PDMACTL_PDMAEN_Msk         (0x1ul << UUART_PDMACTL_PDMAEN_Pos)               /*!< UUART_T::PDMACTL: PDMAEN Mask          */
+
+#define UUART_WKCTL_WKEN_Pos             (0)                                               /*!< UUART_T::WKCTL: WKEN Position          */
+#define UUART_WKCTL_WKEN_Msk             (0x1ul << UUART_WKCTL_WKEN_Pos)                   /*!< UUART_T::WKCTL: WKEN Mask              */
+
+#define UUART_WKCTL_PDBOPT_Pos           (2)                                               /*!< UUART_T::WKCTL: PDBOPT Position        */
+#define UUART_WKCTL_PDBOPT_Msk           (0x1ul << UUART_WKCTL_PDBOPT_Pos)                 /*!< UUART_T::WKCTL: PDBOPT Mask            */
+
+#define UUART_WKSTS_WKF_Pos              (0)                                               /*!< UUART_T::WKSTS: WKF Position           */
+#define UUART_WKSTS_WKF_Msk              (0x1ul << UUART_WKSTS_WKF_Pos)                    /*!< UUART_T::WKSTS: WKF Mask               */
+
+#define UUART_PROTCTL_STOPB_Pos          (0)                                               /*!< UUART_T::PROTCTL: STOPB Position       */
+#define UUART_PROTCTL_STOPB_Msk          (0x1ul << UUART_PROTCTL_STOPB_Pos)                /*!< UUART_T::PROTCTL: STOPB Mask           */
+
+#define UUART_PROTCTL_PARITYEN_Pos       (1)                                               /*!< UUART_T::PROTCTL: PARITYEN Position    */
+#define UUART_PROTCTL_PARITYEN_Msk       (0x1ul << UUART_PROTCTL_PARITYEN_Pos)             /*!< UUART_T::PROTCTL: PARITYEN Mask        */
+
+#define UUART_PROTCTL_EVENPARITY_Pos     (2)                                               /*!< UUART_T::PROTCTL: EVENPARITY Position  */
+#define UUART_PROTCTL_EVENPARITY_Msk     (0x1ul << UUART_PROTCTL_EVENPARITY_Pos)           /*!< UUART_T::PROTCTL: EVENPARITY Mask      */
+
+#define UUART_PROTCTL_RTSAUTOEN_Pos      (3)                                               /*!< UUART_T::PROTCTL: RTSAUTOEN Position   */
+#define UUART_PROTCTL_RTSAUTOEN_Msk      (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos)            /*!< UUART_T::PROTCTL: RTSAUTOEN Mask       */
+
+#define UUART_PROTCTL_CTSAUTOEN_Pos      (4)                                               /*!< UUART_T::PROTCTL: CTSAUTOEN Position   */
+#define UUART_PROTCTL_CTSAUTOEN_Msk      (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos)            /*!< UUART_T::PROTCTL: CTSAUTOEN Mask       */
+
+#define UUART_PROTCTL_RTSAUDIREN_Pos     (5)                                               /*!< UUART_T::PROTCTL: RTSAUDIREN Position  */
+#define UUART_PROTCTL_RTSAUDIREN_Msk     (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos)           /*!< UUART_T::PROTCTL: RTSAUDIREN Mask      */
+
+#define UUART_PROTCTL_ABREN_Pos          (6)                                               /*!< UUART_T::PROTCTL: ABREN Position       */
+#define UUART_PROTCTL_ABREN_Msk          (0x1ul << UUART_PROTCTL_ABREN_Pos)                /*!< UUART_T::PROTCTL: ABREN Mask           */
+
+#define UUART_PROTCTL_DATWKEN_Pos        (9)                                               /*!< UUART_T::PROTCTL: DATWKEN Position     */
+#define UUART_PROTCTL_DATWKEN_Msk        (0x1ul << UUART_PROTCTL_DATWKEN_Pos)              /*!< UUART_T::PROTCTL: DATWKEN Mask         */
+
+#define UUART_PROTCTL_CTSWKEN_Pos        (10)                                              /*!< UUART_T::PROTCTL: CTSWKEN Position     */
+#define UUART_PROTCTL_CTSWKEN_Msk        (0x1ul << UUART_PROTCTL_CTSWKEN_Pos)              /*!< UUART_T::PROTCTL: CTSWKEN Mask         */
+
+#define UUART_PROTCTL_WAKECNT_Pos        (11)                                              /*!< UUART_T::PROTCTL: WAKECNT Position     */
+#define UUART_PROTCTL_WAKECNT_Msk        (0xful << UUART_PROTCTL_WAKECNT_Pos)              /*!< UUART_T::PROTCTL: WAKECNT Mask         */
+
+#define UUART_PROTCTL_BRDETITV_Pos       (16)                                              /*!< UUART_T::PROTCTL: BRDETITV Position    */
+#define UUART_PROTCTL_BRDETITV_Msk       (0x1fful << UUART_PROTCTL_BRDETITV_Pos)           /*!< UUART_T::PROTCTL: BRDETITV Mask        */
+
+#define UUART_PROTCTL_STICKEN_Pos        (26)                                              /*!< UUART_T::PROTCTL: STICKEN Position     */
+#define UUART_PROTCTL_STICKEN_Msk        (0x1ul << UUART_PROTCTL_STICKEN_Pos)              /*!< UUART_T::PROTCTL: STICKEN Mask         */
+
+#define UUART_PROTCTL_BCEN_Pos           (29)                                              /*!< UUART_T::PROTCTL: BCEN Position        */
+#define UUART_PROTCTL_BCEN_Msk           (0x1ul << UUART_PROTCTL_BCEN_Pos)                 /*!< UUART_T::PROTCTL: BCEN Mask            */
+
+#define UUART_PROTCTL_PROTEN_Pos         (31)                                              /*!< UUART_T::PROTCTL: PROTEN Position      */
+#define UUART_PROTCTL_PROTEN_Msk         (0x1ul << UUART_PROTCTL_PROTEN_Pos)               /*!< UUART_T::PROTCTL: PROTEN Mask          */
+
+#define UUART_PROTIEN_ABRIEN_Pos         (1)                                               /*!< UUART_T::PROTIEN: ABRIEN Position      */
+#define UUART_PROTIEN_ABRIEN_Msk         (0x1ul << UUART_PROTIEN_ABRIEN_Pos)               /*!< UUART_T::PROTIEN: ABRIEN Mask          */
+
+#define UUART_PROTIEN_RLSIEN_Pos         (2)                                               /*!< UUART_T::PROTIEN: RLSIEN Position      */
+#define UUART_PROTIEN_RLSIEN_Msk         (0x1ul << UUART_PROTIEN_RLSIEN_Pos)               /*!< UUART_T::PROTIEN: RLSIEN Mask          */
+
+#define UUART_PROTSTS_TXSTIF_Pos         (1)                                               /*!< UUART_T::PROTSTS: TXSTIF Position      */
+#define UUART_PROTSTS_TXSTIF_Msk         (0x1ul << UUART_PROTSTS_TXSTIF_Pos)               /*!< UUART_T::PROTSTS: TXSTIF Mask          */
+
+#define UUART_PROTSTS_TXENDIF_Pos        (2)                                               /*!< UUART_T::PROTSTS: TXENDIF Position     */
+#define UUART_PROTSTS_TXENDIF_Msk        (0x1ul << UUART_PROTSTS_TXENDIF_Pos)              /*!< UUART_T::PROTSTS: TXENDIF Mask         */
+
+#define UUART_PROTSTS_RXSTIF_Pos         (3)                                               /*!< UUART_T::PROTSTS: RXSTIF Position      */
+#define UUART_PROTSTS_RXSTIF_Msk         (0x1ul << UUART_PROTSTS_RXSTIF_Pos)               /*!< UUART_T::PROTSTS: RXSTIF Mask          */
+
+#define UUART_PROTSTS_RXENDIF_Pos        (4)                                               /*!< UUART_T::PROTSTS: RXENDIF Position     */
+#define UUART_PROTSTS_RXENDIF_Msk        (0x1ul << UUART_PROTSTS_RXENDIF_Pos)              /*!< UUART_T::PROTSTS: RXENDIF Mask         */
+
+#define UUART_PROTSTS_PARITYERR_Pos      (5)                                               /*!< UUART_T::PROTSTS: PARITYERR Position   */
+#define UUART_PROTSTS_PARITYERR_Msk      (0x1ul << UUART_PROTSTS_PARITYERR_Pos)            /*!< UUART_T::PROTSTS: PARITYERR Mask       */
+
+#define UUART_PROTSTS_FRMERR_Pos         (6)                                               /*!< UUART_T::PROTSTS: FRMERR Position      */
+#define UUART_PROTSTS_FRMERR_Msk         (0x1ul << UUART_PROTSTS_FRMERR_Pos)               /*!< UUART_T::PROTSTS: FRMERR Mask          */
+
+#define UUART_PROTSTS_BREAK_Pos          (7)                                               /*!< UUART_T::PROTSTS: BREAK Position       */
+#define UUART_PROTSTS_BREAK_Msk          (0x1ul << UUART_PROTSTS_BREAK_Pos)                /*!< UUART_T::PROTSTS: BREAK Mask           */
+
+#define UUART_PROTSTS_ABRDETIF_Pos       (9)                                               /*!< UUART_T::PROTSTS: ABRDETIF Position    */
+#define UUART_PROTSTS_ABRDETIF_Msk       (0x1ul << UUART_PROTSTS_ABRDETIF_Pos)             /*!< UUART_T::PROTSTS: ABRDETIF Mask        */
+
+#define UUART_PROTSTS_RXBUSY_Pos         (10)                                              /*!< UUART_T::PROTSTS: RXBUSY Position      */
+#define UUART_PROTSTS_RXBUSY_Msk         (0x1ul << UUART_PROTSTS_RXBUSY_Pos)               /*!< UUART_T::PROTSTS: RXBUSY Mask          */
+
+#define UUART_PROTSTS_ABERRSTS_Pos       (11)                                              /*!< UUART_T::PROTSTS: ABERRSTS Position    */
+#define UUART_PROTSTS_ABERRSTS_Msk       (0x1ul << UUART_PROTSTS_ABERRSTS_Pos)             /*!< UUART_T::PROTSTS: ABERRSTS Mask        */
+
+#define UUART_PROTSTS_CTSSYNCLV_Pos      (16)                                              /*!< UUART_T::PROTSTS: CTSSYNCLV Position   */
+#define UUART_PROTSTS_CTSSYNCLV_Msk      (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos)            /*!< UUART_T::PROTSTS: CTSSYNCLV Mask       */
+
+#define UUART_PROTSTS_CTSLV_Pos          (17)                                              /*!< UUART_T::PROTSTS: CTSLV Position       */
+#define UUART_PROTSTS_CTSLV_Msk          (0x1ul << UUART_PROTSTS_CTSLV_Pos)                /*!< UUART_T::PROTSTS: CTSLV Mask           */
+
+/**@}*/ /* UUART_CONST */
+/**@}*/ /* end of UUART register group */
+
+
+/*---------------------- SPI Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup USPI SPI Mode of USCI Controller(USPI)
+    Memory Mapped Structure for USPI Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var USPI_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Note: Other bit combinations are reserved.
+     * @var USPI_T::INTEN
+     * Offset: 0x04  USCI Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIEN   |Transmit Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit start event.
+     * |        |          |0 = The transmit start interrupt is disabled.
+     * |        |          |1 = The transmit start interrupt is enabled.
+     * |[2]     |TXENDIEN  |Transmit End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit finish event.
+     * |        |          |0 = The transmit finish interrupt is disabled.
+     * |        |          |1 = The transmit finish interrupt is enabled.
+     * |[3]     |RXSTIEN   |Receive Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive start event.
+     * |        |          |0 = The receive start interrupt is disabled.
+     * |        |          |1 = The receive start interrupt is enabled.
+     * |[4]     |RXENDIEN  |Receive End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive finish event.
+     * |        |          |0 = The receive end interrupt is disabled.
+     * |        |          |1 = The receive end interrupt is enabled.
+     * @var USPI_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fDIV_CLK.
+     * |        |          |01 = fPROT_CLK.
+     * |        |          |10 = fSCLK.
+     * |        |          |11 = fREF_CLK.
+     * |[4]     |TMCNTEN   |Time Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Time measurement counter is Disabled.
+     * |        |          |1 = Time measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Time Measurement Counter Clock Source Selection
+     * |        |          |0 = Time measurement counter with fPROT_CLK.
+     * |        |          |1 = Time measurement counter with fDIV_CLK.
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var USPI_T::DATIN0
+     * Offset: 0x10  USCI Input Data Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Signal Synchronization Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the   synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, we suggest this bit   should be set as 0.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * |        |          |Note: In SPI protocol, we suggest this bit   should be set as 0.
+     * @var USPI_T::CTLIN0
+     * Offset: 0x20  USCI Input Control Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the   synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, we suggest this bit   should be set as 0.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * @var USPI_T::CLKIN
+     * Offset: 0x28  USCI Input Clock Signal Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal or the synchronized (and   optionally filtered) signal can be used as input for the data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, we suggest this bit   should be set as 0.
+     * @var USPI_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[5]     |DATOINV   |Data Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
+     * |        |          |0 = Data output level is not inverted.
+     * |        |          |1 = Data output level is inverted.
+     * |[7]     |CTLOINV   |Control Signal Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal control signal and the output control signal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = The control signal will be inverted before its output.
+     * |        |          |Note: The control signal has different definitions in different protocol
+     * |        |          |In SPI protocol, the control signal means slave select signal
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0: The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1: Reserved.
+     * |        |          |0x2: Reserved.
+     * |        |          |0x3: Reserved.
+     * |        |          |0x4: The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5: The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |...
+     * |        |          |0xF: The data word contains 15 bits located at bit positions [14:0].
+     * @var USPI_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission
+     * |        |          |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
+     * |[16]    |PORTDIR   |Port Direction Control
+     * |        |          |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
+     * |        |          |It is used to define the direction of the data port pin
+     * |        |          |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
+     * |        |          |0 = The data pin is configured as output mode.
+     * |        |          |1 = The data pin is configured as input mode.
+     * @var USPI_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * @var USPI_T::BUFCTL
+     * Offset: 0x38  USCI Transmit/Receive Buffer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6]     |TXUDRIEN  |Slave Transmit Under Run Interrupt Enable Bit
+     * |        |          |0 = Transmit under-run interrupt Disabled.
+     * |        |          |1 = Transmit under-run interrupt Enabled.
+     * |[7]     |TXCLR     |Clear Transmit Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The transmit buffer is cleared
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[14]    |RXOVIEN   |Receive Buffer Overrun Interrupt Enable Bit
+     * |        |          |0 = Receive overrun interrupt Disabled.
+     * |        |          |1 = Receive overrun interrupt Enabled.
+     * |[15]    |RXCLR     |Clear Receive Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The receive buffer is cleared
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[16]    |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[17]    |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * @var USPI_T::BUFSTS
+     * Offset: 0x3C  USCI Transmit/Receive Buffer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXEMPTY   |Receive Buffer Empty Indicator
+     * |        |          |0 = Receive buffer is not empty.
+     * |        |          |1 = Receive buffer is empty.
+     * |[1]     |RXFULL    |Receive Buffer Full Indicator
+     * |        |          |0 = Receive buffer is not full.
+     * |        |          |1 = Receive buffer is full.
+     * |[3]     |RXOVIF    |Receive Buffer Over-run Interrupt Status
+     * |        |          |This bit indicates that a receive buffer overrun event has been detected
+     * |        |          |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
+     * |        |          |It is cleared by software writes 1 to this bit.
+     * |        |          |0 = A receive buffer overrun event has not been detected.
+     * |        |          |1 = A receive buffer overrun event has been detected.
+     * |[8]     |TXEMPTY   |Transmit Buffer Empty Indicator
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty and available for the next transmission datum.
+     * |[9]     |TXFULL    |Transmit Buffer Full Indicator
+     * |        |          |0 = Transmit buffer is not full.
+     * |        |          |1 = Transmit buffer is full.
+     * |[11]    |TXUDRIF   |Transmit Buffer Under-run Interrupt Status
+     * |        |          |This bit indicates that a transmit buffer under-run event has been detected
+     * |        |          |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
+     * |        |          |It is cleared by software writes 1 to this bit
+     * |        |          |0 = A transmit buffer under-run event has not been detected.
+     * |        |          |1 = A transmit buffer under-run event has been detected.
+     * @var USPI_T::PDMACTL
+     * Offset: 0x40  USCI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
+     * |[1]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[2]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[3]     |PDMAEN    |PDMA Mode Enable Bit
+     * |        |          |0 = PDMA function Disabled.
+     * |        |          |1 = PDMA function Enabled.
+     * |        |          |Notice: The I2C is not supporting PDMA function.
+     * @var USPI_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[1]     |WKADDREN  |Wake-up Address Match Enable Bit
+     * |        |          |0 = The chip is woken up according data toggle.
+     * |        |          |1 = The chip is woken up according address match.
+     * |[2]     |PDBOPT    |Power Down Blocking Option
+     * |        |          |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+     * |        |          |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+     * @var USPI_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var USPI_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLAVE     |Slave Mode Selection
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[1]     |SLV3WIRE  |Slave 3-wire Mode Selection (Slave Only)
+     * |        |          |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
+     * |        |          |0 = 4-wire bi-direction interface.
+     * |        |          |1 = 3-wire bi-direction interface.
+     * |[2]     |SS        |Slave Select Control (Master Only)
+     * |        |          |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
+     * |        |          |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
+     * |        |          |Note: In SPI protocol, the internal slave select signal is active high.
+     * |[3]     |AUTOSS    |Automatic Slave Select Function Enable (Master Only)
+     * |        |          |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
+     * |        |          |1 = Slave select signal will be generated automatically
+     * |        |          |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
+     * |[7:6]   |SCLKMODE  |Serial Bus Clock Mode
+     * |        |          |This bit field defines the SCLK idle status, data transmit, and data receive edge.
+     * |        |          |MODE0 = The idle state of SPI clock is low level
+     * |        |          |Data is transmitted with falling edge and received with rising edge.
+     * |        |          |MODE1 = The idle state of SPI clock is low level
+     * |        |          |Data is transmitted with rising edge and received with falling edge.
+     * |        |          |MODE2 = The idle state of SPI clock is high level
+     * |        |          |Data is transmitted with rising edge and received with falling edge.
+     * |        |          |MODE3 = The idle state of SPI clock is high level
+     * |        |          |Data is transmitted with falling edge and received with rising edge.
+     * |[11:8]  |SUSPITV   |Suspend Interval (Master Only)
+     * |        |          |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
+     * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+     * |        |          |The default value is 0x3
+     * |        |          |The period of the suspend interval is obtained according to the following equation.
+     * |        |          |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
+     * |        |          |Example:
+     * |        |          |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
+     * |        |          |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
+     * |        |          |.....
+     * |        |          |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
+     * |        |          |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
+     * |[14:12] |TSMSEL    |Transmit Data Mode Selection
+     * |        |          |This bit field describes how receive and transmit data is shifted in and out.
+     * |        |          |TSMSEL = 000b: Full-duplex SPI.
+     * |        |          |TSMSEL = 100b: Half-duplex SPI.
+     * |        |          |Other values are reserved.
+     * |        |          |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
+     * |[25:16] |SLVTOCNT  |Slave Mode Time-out Period (Slave Only)
+     * |        |          |In Slave mode, this bit field is used for Slave time-out period
+     * |        |          |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
+     * |        |          |Writing 0x0 into this bit field will disable the Slave time-out function.
+     * |        |          |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
+     * |[28]    |TXUDRPOL  |Transmit Under-run Data Polarity (for Slave)
+     * |        |          |This bit defines the transmitting data level when no data is available for transferring.
+     * |        |          |0 = The output data level is 0 if TX under run event occurs.
+     * |        |          |1 = The output data level is 1 if TX under run event occurs.
+     * |[31]    |PROTEN    |SPI Protocol Enable Bit
+     * |        |          |0 = SPI Protocol Disabled.
+     * |        |          |1 = SPI Protocol Enabled.
+     * @var USPI_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSINAIEN  |Slave Select Inactive Interrupt Enable Control
+     * |        |          |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
+     * |        |          |0 = Slave select inactive interrupt generation Disabled.
+     * |        |          |1 = Slave select inactive interrupt generation Enabled.
+     * |[1]     |SSACTIEN  |Slave Select Active Interrupt Enable Control
+     * |        |          |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
+     * |        |          |0 = Slave select active interrupt generation Disabled.
+     * |        |          |1 = Slave select active interrupt generation Enabled.
+     * |[2]     |SLVTOIEN  |Slave Time-out Interrupt Enable Control
+     * |        |          |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
+     * |        |          |0 = The Slave time-out interrupt Disabled.
+     * |        |          |1 = The Slave time-out interrupt Enabled.
+     * |[3]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Control
+     * |        |          |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
+     * |        |          |Bit count error event occurs.
+     * |        |          |0 = The Slave mode bit count error interrupt Disabled.
+     * |        |          |1 = The Slave mode bit count error interrupt Enabled.
+     * @var USPI_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIF    |Transmit Start Interrupt Flag
+     * |        |          |0 = Transmit start event does not occur.
+     * |        |          |1 = Transmit start event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit
+     * |[2]     |TXENDIF   |Transmit End Interrupt Flag
+     * |        |          |0 = Transmit end event does not occur.
+     * |        |          |1 = Transmit end event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit
+     * |[3]     |RXSTIF    |Receive Start Interrupt Flag
+     * |        |          |0 = Receive start event does not occur.
+     * |        |          |1 = Receive start event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit
+     * |[4]     |RXENDIF   |Receive End Interrupt Flag
+     * |        |          |0 = Receive end event does not occur.
+     * |        |          |1 = Receive end event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit
+     * |[5]     |SLVTOIF   |Slave Time-out Interrupt Flag (for Slave Only)
+     * |        |          |0 = Slave time-out event does not occur.
+     * |        |          |1 = Slave time-out event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit
+     * |[6]     |SLVBEIF   |Slave Bit Count Error Interrupt Flag (for Slave Only)
+     * |        |          |0 = Slave bit count error event does not occur.
+     * |        |          |1 = Slave bit count error event occurs.
+     * |        |          |Note: It is cleared by software writes 1 to this bit.
+     * |[8]     |SSINAIF   |Slave Select Inactive Interrupt Flag (for Slave Only)
+     * |        |          |This bit indicates that the internal slave select signal has changed to inactive
+     * |        |          |It is cleared by software writes 1 to this bit
+     * |        |          |0 = The slave select signal has not changed to inactive.
+     * |        |          |1 = The slave select signal has changed to inactive.
+     * |        |          |Note: The internal slave select signal is active high.
+     * |[9]     |SSACTIF   |Slave Select Active Interrupt Flag (for Slave Only)
+     * |        |          |This bit indicates that the internal slave select signal has changed to active
+     * |        |          |It is cleared by software writes one to this bit
+     * |        |          |0 = The slave select signal has not changed to active.
+     * |        |          |1 = The slave select signal has changed to active.
+     * |        |          |Note: The internal slave select signal is active high.
+     * |[16]    |SSLINE    |Slave Select Line Bus Status (Read Only)
+     * |        |          |This bit is only available in Slave mode
+     * |        |          |It used to monitor the current status of the input slave select signal on the bus.
+     * |        |          |0 = The slave select line status is 0.
+     * |        |          |1 = The slave select line status is 1.
+     * |[17]    |BUSY      |Busy Status (Read Only)
+     * |        |          |0 = SPI is in idle state.
+     * |        |          |1 = SPI is in busy state.
+     * |        |          |The following listing are the bus busy conditions:
+     * |        |          |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
+     * |        |          |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
+     * |        |          |c
+     * |        |          |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+     * |        |          |d
+     * |        |          |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+     * |[18]    |SLVUDR    |Slave Mode Transmit Under-run Status (Read Only)
+     * |        |          |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
+     * |        |          |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
+     * |        |          |0 = Slave transmit under-run event does not occur.
+     * |        |          |1 = Slave transmit under-run event occurs.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] USCI Interrupt Enable Register                                   */
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DATIN0;                /*!< [0x0010] USCI Input Data Signal Configuration Register 0                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTLIN0;                /*!< [0x0020] USCI Input Control Signal Configuration Register 0               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CLKIN;                 /*!< [0x0028] USCI Input Clock Signal Configuration Register                   */
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __O  uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __I  uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    __IO uint32_t BUFCTL;                /*!< [0x0038] USCI Transmit/Receive Buffer Control Register                    */
+    __IO uint32_t BUFSTS;                /*!< [0x003c] USCI Transmit/Receive Buffer Status Register                     */
+    __IO uint32_t PDMACTL;               /*!< [0x0040] USCI PDMA Control Register                                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[4];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+
+} USPI_T;
+
+/**
+    @addtogroup USPI_CONST USPI Bit Field Definition
+    Constant Definitions for USPI Controller
+@{ */
+
+#define USPI_CTL_FUNMODE_Pos             (0)                                               /*!< USPI_T::CTL: FUNMODE Position          */
+#define USPI_CTL_FUNMODE_Msk             (0x7ul << USPI_CTL_FUNMODE_Pos)                   /*!< USPI_T::CTL: FUNMODE Mask              */
+
+#define USPI_INTEN_TXSTIEN_Pos           (1)                                               /*!< USPI_T::INTEN: TXSTIEN Position        */
+#define USPI_INTEN_TXSTIEN_Msk           (0x1ul << USPI_INTEN_TXSTIEN_Pos)                 /*!< USPI_T::INTEN: TXSTIEN Mask            */
+
+#define USPI_INTEN_TXENDIEN_Pos          (2)                                               /*!< USPI_T::INTEN: TXENDIEN Position       */
+#define USPI_INTEN_TXENDIEN_Msk          (0x1ul << USPI_INTEN_TXENDIEN_Pos)                /*!< USPI_T::INTEN: TXENDIEN Mask           */
+
+#define USPI_INTEN_RXSTIEN_Pos           (3)                                               /*!< USPI_T::INTEN: RXSTIEN Position        */
+#define USPI_INTEN_RXSTIEN_Msk           (0x1ul << USPI_INTEN_RXSTIEN_Pos)                 /*!< USPI_T::INTEN: RXSTIEN Mask            */
+
+#define USPI_INTEN_RXENDIEN_Pos          (4)                                               /*!< USPI_T::INTEN: RXENDIEN Position       */
+#define USPI_INTEN_RXENDIEN_Msk          (0x1ul << USPI_INTEN_RXENDIEN_Pos)                /*!< USPI_T::INTEN: RXENDIEN Mask           */
+
+#define USPI_BRGEN_RCLKSEL_Pos           (0)                                               /*!< USPI_T::BRGEN: RCLKSEL Position        */
+#define USPI_BRGEN_RCLKSEL_Msk           (0x1ul << USPI_BRGEN_RCLKSEL_Pos)                 /*!< USPI_T::BRGEN: RCLKSEL Mask            */
+
+#define USPI_BRGEN_PTCLKSEL_Pos          (1)                                               /*!< USPI_T::BRGEN: PTCLKSEL Position       */
+#define USPI_BRGEN_PTCLKSEL_Msk          (0x1ul << USPI_BRGEN_PTCLKSEL_Pos)                /*!< USPI_T::BRGEN: PTCLKSEL Mask           */
+
+#define USPI_BRGEN_SPCLKSEL_Pos          (2)                                               /*!< USPI_T::BRGEN: SPCLKSEL Position       */
+#define USPI_BRGEN_SPCLKSEL_Msk          (0x3ul << USPI_BRGEN_SPCLKSEL_Pos)                /*!< USPI_T::BRGEN: SPCLKSEL Mask           */
+
+#define USPI_BRGEN_TMCNTEN_Pos           (4)                                               /*!< USPI_T::BRGEN: TMCNTEN Position        */
+#define USPI_BRGEN_TMCNTEN_Msk           (0x1ul << USPI_BRGEN_TMCNTEN_Pos)                 /*!< USPI_T::BRGEN: TMCNTEN Mask            */
+
+#define USPI_BRGEN_TMCNTSRC_Pos          (5)                                               /*!< USPI_T::BRGEN: TMCNTSRC Position       */
+#define USPI_BRGEN_TMCNTSRC_Msk          (0x1ul << USPI_BRGEN_TMCNTSRC_Pos)                /*!< USPI_T::BRGEN: TMCNTSRC Mask           */
+
+#define USPI_BRGEN_CLKDIV_Pos            (16)                                              /*!< USPI_T::BRGEN: CLKDIV Position         */
+#define USPI_BRGEN_CLKDIV_Msk            (0x3fful << USPI_BRGEN_CLKDIV_Pos)                /*!< USPI_T::BRGEN: CLKDIV Mask             */
+
+#define USPI_DATIN0_SYNCSEL_Pos          (0)                                               /*!< USPI_T::DATIN0: SYNCSEL Position       */
+#define USPI_DATIN0_SYNCSEL_Msk          (0x1ul << USPI_DATIN0_SYNCSEL_Pos)                /*!< USPI_T::DATIN0: SYNCSEL Mask           */
+
+#define USPI_DATIN0_ININV_Pos            (2)                                               /*!< USPI_T::DATIN0: ININV Position         */
+#define USPI_DATIN0_ININV_Msk            (0x1ul << USPI_DATIN0_ININV_Pos)                  /*!< USPI_T::DATIN0: ININV Mask             */
+
+#define USPI_CTLIN0_SYNCSEL_Pos          (0)                                               /*!< USPI_T::CTLIN0: SYNCSEL Position       */
+#define USPI_CTLIN0_SYNCSEL_Msk          (0x1ul << USPI_CTLIN0_SYNCSEL_Pos)                /*!< USPI_T::CTLIN0: SYNCSEL Mask           */
+
+#define USPI_CTLIN0_ININV_Pos            (2)                                               /*!< USPI_T::CTLIN0: ININV Position         */
+#define USPI_CTLIN0_ININV_Msk            (0x1ul << USPI_CTLIN0_ININV_Pos)                  /*!< USPI_T::CTLIN0: ININV Mask             */
+
+#define USPI_CLKIN_SYNCSEL_Pos           (0)                                               /*!< USPI_T::CLKIN: SYNCSEL Position        */
+#define USPI_CLKIN_SYNCSEL_Msk           (0x1ul << USPI_CLKIN_SYNCSEL_Pos)                 /*!< USPI_T::CLKIN: SYNCSEL Mask            */
+
+#define USPI_LINECTL_LSB_Pos             (0)                                               /*!< USPI_T::LINECTL: LSB Position          */
+#define USPI_LINECTL_LSB_Msk             (0x1ul << USPI_LINECTL_LSB_Pos)                   /*!< USPI_T::LINECTL: LSB Mask              */
+
+#define USPI_LINECTL_DATOINV_Pos         (5)                                               /*!< USPI_T::LINECTL: DATOINV Position      */
+#define USPI_LINECTL_DATOINV_Msk         (0x1ul << USPI_LINECTL_DATOINV_Pos)               /*!< USPI_T::LINECTL: DATOINV Mask          */
+
+#define USPI_LINECTL_CTLOINV_Pos         (7)                                               /*!< USPI_T::LINECTL: CTLOINV Position      */
+#define USPI_LINECTL_CTLOINV_Msk         (0x1ul << USPI_LINECTL_CTLOINV_Pos)               /*!< USPI_T::LINECTL: CTLOINV Mask          */
+
+#define USPI_LINECTL_DWIDTH_Pos          (8)                                               /*!< USPI_T::LINECTL: DWIDTH Position       */
+#define USPI_LINECTL_DWIDTH_Msk          (0xful << USPI_LINECTL_DWIDTH_Pos)                /*!< USPI_T::LINECTL: DWIDTH Mask           */
+
+#define USPI_TXDAT_TXDAT_Pos             (0)                                               /*!< USPI_T::TXDAT: TXDAT Position          */
+#define USPI_TXDAT_TXDAT_Msk             (0xfffful << USPI_TXDAT_TXDAT_Pos)                /*!< USPI_T::TXDAT: TXDAT Mask              */
+
+#define USPI_TXDAT_PORTDIR_Pos           (16)                                              /*!< USPI_T::TXDAT: PORTDIR Position        */
+#define USPI_TXDAT_PORTDIR_Msk           (0x1ul << USPI_TXDAT_PORTDIR_Pos)                 /*!< USPI_T::TXDAT: PORTDIR Mask            */
+
+#define USPI_RXDAT_RXDAT_Pos             (0)                                               /*!< USPI_T::RXDAT: RXDAT Position          */
+#define USPI_RXDAT_RXDAT_Msk             (0xfffful << USPI_RXDAT_RXDAT_Pos)                /*!< USPI_T::RXDAT: RXDAT Mask              */
+
+#define USPI_BUFCTL_TXUDRIEN_Pos         (6)                                               /*!< USPI_T::BUFCTL: TXUDRIEN Position      */
+#define USPI_BUFCTL_TXUDRIEN_Msk         (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos)               /*!< USPI_T::BUFCTL: TXUDRIEN Mask          */
+
+#define USPI_BUFCTL_TXCLR_Pos            (7)                                               /*!< USPI_T::BUFCTL: TXCLR Position         */
+#define USPI_BUFCTL_TXCLR_Msk            (0x1ul << USPI_BUFCTL_TXCLR_Pos)                  /*!< USPI_T::BUFCTL: TXCLR Mask             */
+
+#define USPI_BUFCTL_RXOVIEN_Pos          (14)                                              /*!< USPI_T::BUFCTL: RXOVIEN Position       */
+#define USPI_BUFCTL_RXOVIEN_Msk          (0x1ul << USPI_BUFCTL_RXOVIEN_Pos)                /*!< USPI_T::BUFCTL: RXOVIEN Mask           */
+
+#define USPI_BUFCTL_RXCLR_Pos            (15)                                              /*!< USPI_T::BUFCTL: RXCLR Position         */
+#define USPI_BUFCTL_RXCLR_Msk            (0x1ul << USPI_BUFCTL_RXCLR_Pos)                  /*!< USPI_T::BUFCTL: RXCLR Mask             */
+
+#define USPI_BUFCTL_TXRST_Pos            (16)                                              /*!< USPI_T::BUFCTL: TXRST Position         */
+#define USPI_BUFCTL_TXRST_Msk            (0x1ul << USPI_BUFCTL_TXRST_Pos)                  /*!< USPI_T::BUFCTL: TXRST Mask             */
+
+#define USPI_BUFCTL_RXRST_Pos            (17)                                              /*!< USPI_T::BUFCTL: RXRST Position         */
+#define USPI_BUFCTL_RXRST_Msk            (0x1ul << USPI_BUFCTL_RXRST_Pos)                  /*!< USPI_T::BUFCTL: RXRST Mask             */
+
+#define USPI_BUFSTS_RXEMPTY_Pos          (0)                                               /*!< USPI_T::BUFSTS: RXEMPTY Position       */
+#define USPI_BUFSTS_RXEMPTY_Msk          (0x1ul << USPI_BUFSTS_RXEMPTY_Pos)                /*!< USPI_T::BUFSTS: RXEMPTY Mask           */
+
+#define USPI_BUFSTS_RXFULL_Pos           (1)                                               /*!< USPI_T::BUFSTS: RXFULL Position        */
+#define USPI_BUFSTS_RXFULL_Msk           (0x1ul << USPI_BUFSTS_RXFULL_Pos)                 /*!< USPI_T::BUFSTS: RXFULL Mask            */
+
+#define USPI_BUFSTS_RXOVIF_Pos           (3)                                               /*!< USPI_T::BUFSTS: RXOVIF Position        */
+#define USPI_BUFSTS_RXOVIF_Msk           (0x1ul << USPI_BUFSTS_RXOVIF_Pos)                 /*!< USPI_T::BUFSTS: RXOVIF Mask            */
+
+#define USPI_BUFSTS_TXEMPTY_Pos          (8)                                               /*!< USPI_T::BUFSTS: TXEMPTY Position       */
+#define USPI_BUFSTS_TXEMPTY_Msk          (0x1ul << USPI_BUFSTS_TXEMPTY_Pos)                /*!< USPI_T::BUFSTS: TXEMPTY Mask           */
+
+#define USPI_BUFSTS_TXFULL_Pos           (9)                                               /*!< USPI_T::BUFSTS: TXFULL Position        */
+#define USPI_BUFSTS_TXFULL_Msk           (0x1ul << USPI_BUFSTS_TXFULL_Pos)                 /*!< USPI_T::BUFSTS: TXFULL Mask            */
+
+#define USPI_BUFSTS_TXUDRIF_Pos          (11)                                              /*!< USPI_T::BUFSTS: TXUDRIF Position       */
+#define USPI_BUFSTS_TXUDRIF_Msk          (0x1ul << USPI_BUFSTS_TXUDRIF_Pos)                /*!< USPI_T::BUFSTS: TXUDRIF Mask           */
+
+#define USPI_PDMACTL_PDMARST_Pos         (0)                                               /*!< USPI_T::PDMACTL: PDMARST Position      */
+#define USPI_PDMACTL_PDMARST_Msk         (0x1ul << USPI_PDMACTL_PDMARST_Pos)               /*!< USPI_T::PDMACTL: PDMARST Mask          */
+
+#define USPI_PDMACTL_TXPDMAEN_Pos        (1)                                               /*!< USPI_T::PDMACTL: TXPDMAEN Position     */
+#define USPI_PDMACTL_TXPDMAEN_Msk        (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos)              /*!< USPI_T::PDMACTL: TXPDMAEN Mask         */
+
+#define USPI_PDMACTL_RXPDMAEN_Pos        (2)                                               /*!< USPI_T::PDMACTL: RXPDMAEN Position     */
+#define USPI_PDMACTL_RXPDMAEN_Msk        (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos)              /*!< USPI_T::PDMACTL: RXPDMAEN Mask         */
+
+#define USPI_PDMACTL_PDMAEN_Pos          (3)                                               /*!< USPI_T::PDMACTL: PDMAEN Position       */
+#define USPI_PDMACTL_PDMAEN_Msk          (0x1ul << USPI_PDMACTL_PDMAEN_Pos)                /*!< USPI_T::PDMACTL: PDMAEN Mask           */
+
+#define USPI_WKCTL_WKEN_Pos              (0)                                               /*!< USPI_T::WKCTL: WKEN Position           */
+#define USPI_WKCTL_WKEN_Msk              (0x1ul << USPI_WKCTL_WKEN_Pos)                    /*!< USPI_T::WKCTL: WKEN Mask               */
+
+#define USPI_WKCTL_WKADDREN_Pos          (1)                                               /*!< USPI_T::WKCTL: WKADDREN Position       */
+#define USPI_WKCTL_WKADDREN_Msk          (0x1ul << USPI_WKCTL_WKADDREN_Pos)                /*!< USPI_T::WKCTL: WKADDREN Mask           */
+
+#define USPI_WKCTL_PDBOPT_Pos            (2)                                               /*!< USPI_T::WKCTL: PDBOPT Position         */
+#define USPI_WKCTL_PDBOPT_Msk            (0x1ul << USPI_WKCTL_PDBOPT_Pos)                  /*!< USPI_T::WKCTL: PDBOPT Mask             */
+
+#define USPI_WKSTS_WKF_Pos               (0)                                               /*!< USPI_T::WKSTS: WKF Position            */
+#define USPI_WKSTS_WKF_Msk               (0x1ul << USPI_WKSTS_WKF_Pos)                     /*!< USPI_T::WKSTS: WKF Mask                */
+
+#define USPI_PROTCTL_SLAVE_Pos           (0)                                               /*!< USPI_T::PROTCTL: SLAVE Position        */
+#define USPI_PROTCTL_SLAVE_Msk           (0x1ul << USPI_PROTCTL_SLAVE_Pos)                 /*!< USPI_T::PROTCTL: SLAVE Mask            */
+
+#define USPI_PROTCTL_SLV3WIRE_Pos        (1)                                               /*!< USPI_T::PROTCTL: SLV3WIRE Position     */
+#define USPI_PROTCTL_SLV3WIRE_Msk        (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos)              /*!< USPI_T::PROTCTL: SLV3WIRE Mask         */
+
+#define USPI_PROTCTL_SS_Pos              (2)                                               /*!< USPI_T::PROTCTL: SS Position           */
+#define USPI_PROTCTL_SS_Msk              (0x1ul << USPI_PROTCTL_SS_Pos)                    /*!< USPI_T::PROTCTL: SS Mask               */
+
+#define USPI_PROTCTL_AUTOSS_Pos          (3)                                               /*!< USPI_T::PROTCTL: AUTOSS Position       */
+#define USPI_PROTCTL_AUTOSS_Msk          (0x1ul << USPI_PROTCTL_AUTOSS_Pos)                /*!< USPI_T::PROTCTL: AUTOSS Mask           */
+
+#define USPI_PROTCTL_SCLKMODE_Pos        (6)                                               /*!< USPI_T::PROTCTL: SCLKMODE Position     */
+#define USPI_PROTCTL_SCLKMODE_Msk        (0x3ul << USPI_PROTCTL_SCLKMODE_Pos)              /*!< USPI_T::PROTCTL: SCLKMODE Mask         */
+
+#define USPI_PROTCTL_SUSPITV_Pos         (8)                                               /*!< USPI_T::PROTCTL: SUSPITV Position      */
+#define USPI_PROTCTL_SUSPITV_Msk         (0xful << USPI_PROTCTL_SUSPITV_Pos)               /*!< USPI_T::PROTCTL: SUSPITV Mask          */
+
+#define USPI_PROTCTL_TSMSEL_Pos          (12)                                              /*!< USPI_T::PROTCTL: TSMSEL Position       */
+#define USPI_PROTCTL_TSMSEL_Msk          (0x7ul << USPI_PROTCTL_TSMSEL_Pos)                /*!< USPI_T::PROTCTL: TSMSEL Mask           */
+
+#define USPI_PROTCTL_SLVTOCNT_Pos        (16)                                              /*!< USPI_T::PROTCTL: SLVTOCNT Position     */
+#define USPI_PROTCTL_SLVTOCNT_Msk        (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos)            /*!< USPI_T::PROTCTL: SLVTOCNT Mask         */
+
+#define USPI_PROTCTL_TXUDRPOL_Pos        (28)                                              /*!< USPI_T::PROTCTL: TXUDRPOL Position     */
+#define USPI_PROTCTL_TXUDRPOL_Msk        (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos)              /*!< USPI_T::PROTCTL: TXUDRPOL Mask         */
+
+#define USPI_PROTCTL_PROTEN_Pos          (31)                                              /*!< USPI_T::PROTCTL: PROTEN Position       */
+#define USPI_PROTCTL_PROTEN_Msk          (0x1ul << USPI_PROTCTL_PROTEN_Pos)                /*!< USPI_T::PROTCTL: PROTEN Mask           */
+
+#define USPI_PROTIEN_SSINAIEN_Pos        (0)                                               /*!< USPI_T::PROTIEN: SSINAIEN Position     */
+#define USPI_PROTIEN_SSINAIEN_Msk        (0x1ul << USPI_PROTIEN_SSINAIEN_Pos)              /*!< USPI_T::PROTIEN: SSINAIEN Mask         */
+
+#define USPI_PROTIEN_SSACTIEN_Pos        (1)                                               /*!< USPI_T::PROTIEN: SSACTIEN Position     */
+#define USPI_PROTIEN_SSACTIEN_Msk        (0x1ul << USPI_PROTIEN_SSACTIEN_Pos)              /*!< USPI_T::PROTIEN: SSACTIEN Mask         */
+
+#define USPI_PROTIEN_SLVTOIEN_Pos        (2)                                               /*!< USPI_T::PROTIEN: SLVTOIEN Position     */
+#define USPI_PROTIEN_SLVTOIEN_Msk        (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos)              /*!< USPI_T::PROTIEN: SLVTOIEN Mask         */
+
+#define USPI_PROTIEN_SLVBEIEN_Pos        (3)                                               /*!< USPI_T::PROTIEN: SLVBEIEN Position     */
+#define USPI_PROTIEN_SLVBEIEN_Msk        (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos)              /*!< USPI_T::PROTIEN: SLVBEIEN Mask         */
+
+#define USPI_PROTSTS_TXSTIF_Pos          (1)                                               /*!< USPI_T::PROTSTS: TXSTIF Position       */
+#define USPI_PROTSTS_TXSTIF_Msk          (0x1ul << USPI_PROTSTS_TXSTIF_Pos)                /*!< USPI_T::PROTSTS: TXSTIF Mask           */
+
+#define USPI_PROTSTS_TXENDIF_Pos         (2)                                               /*!< USPI_T::PROTSTS: TXENDIF Position      */
+#define USPI_PROTSTS_TXENDIF_Msk         (0x1ul << USPI_PROTSTS_TXENDIF_Pos)               /*!< USPI_T::PROTSTS: TXENDIF Mask          */
+
+#define USPI_PROTSTS_RXSTIF_Pos          (3)                                               /*!< USPI_T::PROTSTS: RXSTIF Position       */
+#define USPI_PROTSTS_RXSTIF_Msk          (0x1ul << USPI_PROTSTS_RXSTIF_Pos)                /*!< USPI_T::PROTSTS: RXSTIF Mask           */
+
+#define USPI_PROTSTS_RXENDIF_Pos         (4)                                               /*!< USPI_T::PROTSTS: RXENDIF Position      */
+#define USPI_PROTSTS_RXENDIF_Msk         (0x1ul << USPI_PROTSTS_RXENDIF_Pos)               /*!< USPI_T::PROTSTS: RXENDIF Mask          */
+
+#define USPI_PROTSTS_SLVTOIF_Pos         (5)                                               /*!< USPI_T::PROTSTS: SLVTOIF Position      */
+#define USPI_PROTSTS_SLVTOIF_Msk         (0x1ul << USPI_PROTSTS_SLVTOIF_Pos)               /*!< USPI_T::PROTSTS: SLVTOIF Mask          */
+
+#define USPI_PROTSTS_SLVBEIF_Pos         (6)                                               /*!< USPI_T::PROTSTS: SLVBEIF Position      */
+#define USPI_PROTSTS_SLVBEIF_Msk         (0x1ul << USPI_PROTSTS_SLVBEIF_Pos)               /*!< USPI_T::PROTSTS: SLVBEIF Mask          */
+
+#define USPI_PROTSTS_SSINAIF_Pos         (8)                                               /*!< USPI_T::PROTSTS: SSINAIF Position      */
+#define USPI_PROTSTS_SSINAIF_Msk         (0x1ul << USPI_PROTSTS_SSINAIF_Pos)               /*!< USPI_T::PROTSTS: SSINAIF Mask          */
+
+#define USPI_PROTSTS_SSACTIF_Pos         (9)                                               /*!< USPI_T::PROTSTS: SSACTIF Position      */
+#define USPI_PROTSTS_SSACTIF_Msk         (0x1ul << USPI_PROTSTS_SSACTIF_Pos)               /*!< USPI_T::PROTSTS: SSACTIF Mask          */
+
+#define USPI_PROTSTS_SSLINE_Pos          (16)                                              /*!< USPI_T::PROTSTS: SSLINE Position       */
+#define USPI_PROTSTS_SSLINE_Msk          (0x1ul << USPI_PROTSTS_SSLINE_Pos)                /*!< USPI_T::PROTSTS: SSLINE Mask           */
+
+#define USPI_PROTSTS_BUSY_Pos            (17)                                              /*!< USPI_T::PROTSTS: BUSY Position         */
+#define USPI_PROTSTS_BUSY_Msk            (0x1ul << USPI_PROTSTS_BUSY_Pos)                  /*!< USPI_T::PROTSTS: BUSY Mask             */
+
+#define USPI_PROTSTS_SLVUDR_Pos          (18)                                              /*!< USPI_T::PROTSTS: SLVUDR Position       */
+#define USPI_PROTSTS_SLVUDR_Msk          (0x1ul << USPI_PROTSTS_SLVUDR_Pos)                /*!< USPI_T::PROTSTS: SLVUDR Mask           */
+
+/**@}*/ /* USPI_CONST */
+/**@}*/ /* end of USPI register group */
+
+/*---------------------- I2C Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup UI2C I2C Mode of USCI Controller(UI2C)
+    Memory Mapped Structure for UI2C Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var UI2C_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Note: Other bit combinations are reserved.
+     * @var UI2C_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source signal of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source signal of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fSAMP_CLK = fDIV_CLK.
+     * |        |          |01 = fSAMP_CLK = fPROT_CLK.
+     * |        |          |10 = fSAMP_CLK = fSCLK.
+     * |        |          |11 = fSAMP_CLK = fREF_CLK.
+     * |[4]     |TMCNTEN   |Time Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Time measurement counter is Disabled.
+     * |        |          |1 = Time measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Time Measurement Counter Clock Source Selection
+     * |        |          |0 = Time measurement counter with fPROT_CLK.
+     * |        |          |1 = Time measurement counter with fDIV_CLK.
+     * |[9:8]   |PDSCNT    |Pre-divider for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
+     * |        |          |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+     * |[14:10] |DSCNT     |Denominator for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+     * |        |          |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+     * |        |          |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var UI2C_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0: The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1: Reserved.
+     * |        |          |0x2: Reserved.
+     * |        |          |0x3: Reserved.
+     * |        |          |0x4: The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5: The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |...
+     * |        |          |0xF: The data word contains 15 bits located at bit positions [14:0].
+     * |        |          |Note: In UART protocol, the length can be configured as 6~13 bits
+     * |        |          |And in I2C protocol, the length fixed as 8 bits.
+     * @var UI2C_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission.
+     * @var UI2C_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * |        |          |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
+     * |        |          |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
+     * @var UI2C_T::DEVADDR0
+     * Offset: 0x44  USCI Device Address Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DEVADDR   |Device Address
+     * |        |          |In I2C protocol, this bit field contains the programmed slave address
+     * |        |          |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+     * |        |          |Then the second address byte is also compared to DEVADDR[7:0].
+     * |        |          |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
+     * |        |          |Note 2: When software set 10'h000, the address can not be used.
+     * @var UI2C_T::DEVADDR1
+     * Offset: 0x48  USCI Device Address Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DEVADDR   |Device Address
+     * |        |          |In I2C protocol, this bit field contains the programmed slave address
+     * |        |          |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+     * |        |          |Then the second address byte is also compared to DEVADDR[7:0].
+     * |        |          |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode.
+     * |        |          |Note 2: When software set 10'h000, the address can not be used.
+     * @var UI2C_T::ADDRMSK0
+     * Offset: 0x4C  USCI Device Address Mask Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |ADDRMSK   |USCI Device Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |USCI support multiple address recognition with two address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var UI2C_T::ADDRMSK1
+     * Offset: 0x50  USCI Device Address Mask Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |ADDRMSK   |USCI Device Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |USCI support multiple address recognition with two address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var UI2C_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[1]     |WKADDREN  |Wake-up Address Match Enable Bit
+     * |        |          |0 = The chip is woken up according data toggle.
+     * |        |          |1 = The chip is woken up according address match.
+     * @var UI2C_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var UI2C_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GCFUNC    |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[1]     |AA        |Assert Acknowledge Control
+     * |        |          |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+     * |        |          |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
+     * |[2]     |STO       |I2C STOP Control
+     * |        |          |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
+     * |        |          |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1).
+     * |[3]     |STA       |I2C START Control
+     * |        |          |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+     * |[4]     |ADDR10EN  |Address 10-bit Function Enable Bit
+     * |        |          |0 = Address match 10 bit function is disabled.
+     * |        |          |1 = Address match 10 bit function is enabled.
+     * |[5]     |PTRG      |I2C Protocol Trigger (Write Only)
+     * |        |          |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
+     * |        |          |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
+     * |        |          |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
+     * |        |          |1 = I2C's stretch active.
+     * |[8]     |SCLOUTEN  |SCL Output Enable Bit
+     * |        |          |This bit enables monitor pulling SCL to low
+     * |        |          |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
+     * |        |          |0 = SCL output will be forced high due to open drain mechanism.
+     * |        |          |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
+     * |[9]     |MONEN     |Monitor Mode Enable Bit
+     * |        |          |This bit enables monitor mode
+     * |        |          |In monitor mode the SDA output will be put in high impedance mode
+     * |        |          |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
+     * |        |          |0 = The monitor mode is disabled.
+     * |        |          |1 = The monitor mode is enabled.
+     * |        |          |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
+     * |[25:16] |TOCNT     |Time-out Clock Cycle
+     * |        |          |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear
+     * |        |          |The time-out is enable when TOCNT bigger than 0.
+     * |        |          |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
+     * |[31]    |PROTEN    |I2C Protocol Enable Bit
+     * |        |          |0 = I2C Protocol disable.
+     * |        |          |1 = I2C Protocol enable.
+     * @var UI2C_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOIEN     |Time-out Interrupt Enable Control
+     * |        |          |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
+     * |        |          |0 = The time-out interrupt is disabled.
+     * |        |          |1 = The time-out interrupt is enabled.
+     * |[1]     |STARIEN   |Start Condition Received Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a start condition is detected.
+     * |        |          |0 = The start condition interrupt is disabled.
+     * |        |          |1 = The start condition interrupt is enabled.
+     * |[2]     |STORIEN   |Stop Condition Received Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a stop condition is detected.
+     * |        |          |0 = The stop condition interrupt is disabled.
+     * |        |          |1 = The stop condition interrupt is enabled.
+     * |[3]     |NACKIEN   |Non - Acknowledge Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
+     * |        |          |0 = The non - acknowledge interrupt is disabled.
+     * |        |          |1 = The non - acknowledge interrupt is enabled.
+     * |[4]     |ARBLOIEN  |Arbitration Lost Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
+     * |        |          |0 = The arbitration lost interrupt is disabled.
+     * |        |          |1 = The arbitration lost interrupt is enabled.
+     * |[5]     |ERRIEN    |Error Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).
+     * |        |          |0 = The error interrupt is disabled.
+     * |        |          |1 = The error interrupt is enabled.
+     * |[6]     |ACKIEN    |Acknowledge Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
+     * |        |          |0 = The acknowledge interrupt is disabled.
+     * |        |          |1 = The acknowledge interrupt is enabled.
+     * @var UI2C_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5]     |TOIF      |Time-out Interrupt Flag
+     * |        |          |0 = A time-out interrupt status has not occurred.
+     * |        |          |1 = A time-out interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit
+     * |[6]     |ONBUSY    |On Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |[8]     |STARIF    |Start Condition Received Interrupt Flag
+     * |        |          |This bit indicates that a start condition or repeated start condition has been detected on master mode
+     * |        |          |However, this bit also indicates that a repeated start condition has been detected on slave mode.
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1.
+     * |        |          |0 = A start condition has not yet been detected.
+     * |        |          |1 = A start condition has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[9]     |STORIF    |Stop Condition Received Interrupt Flag
+     * |        |          |This bit indicates that a stop condition has been detected on the I2C bus lines
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1.
+     * |        |          |0 = A stop condition has not yet been detected.
+     * |        |          |1 = A stop condition has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |        |          |Note: This bit is set when slave RX mode.
+     * |[10]    |NACKIF    |Non - Acknowledge Received Interrupt Flag
+     * |        |          |This bit indicates that a non - acknowledge has been received in master mode
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1.
+     * |        |          |0 = A non - acknowledge has not been received.
+     * |        |          |1 = A non - acknowledge has been received.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[11]    |ARBLOIF   |Arbitration Lost Interrupt Flag
+     * |        |          |This bit indicates that an arbitration has been lost
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1.
+     * |        |          |0 = An arbitration has not been lost.
+     * |        |          |1 = An arbitration has been lost.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[12]    |ERRIF     |Error Interrupt Flag
+     * |        |          |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+     * |        |          |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1.
+     * |        |          |0 = An I2C error has not been detected.
+     * |        |          |1 = An I2C error has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |        |          |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode.
+     * |[13]    |ACKIF     |Acknowledge Received Interrupt Flag
+     * |        |          |This bit indicates that an acknowledge has been received in master mode
+     * |        |          |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1.
+     * |        |          |0 = An acknowledge has not been received.
+     * |        |          |1 = An acknowledge has been received.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[14]    |SLASEL    |Slave Select Status
+     * |        |          |This bit indicates that this device has been selected as slave.
+     * |        |          |0 = The device is not selected as slave.
+     * |        |          |1 = The device is selected as slave.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+     * |[15]    |SLAREAD   |Slave Read Request Status
+     * |        |          |This bit indicates that a slave read request has been detected.
+     * |        |          |0 = A slave R/W bit is 1 has not been detected.
+     * |        |          |1 = A slave R/W bit is 1 has been detected.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+     * |[16]    |WKAKDONE  |Wakeup Address Frame Acknowledge Bit Done
+     * |        |          |0 = The ACK bit cycle of address match frame isn't done.
+     * |        |          |1 = The ACK bit cycle of address match frame is done in power-down.
+     * |        |          |Note: This bit can't release when WKUPIF is set.
+     * |[17]    |WRSTSWK   |Read/Write Status Bit in Address Wakeup Frame
+     * |        |          |0 = Write command be record on the address match wakeup frame.
+     * |        |          |1 = Read command be record on the address match wakeup frame.
+     * |[18]    |BUSHANG   |Bus Hang-up
+     * |        |          |This bit indicates bus hang-up status
+     * |        |          |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
+     * |        |          |The hang-up counter will count to overflow and set this bit when SDA is low
+     * |        |          |The counter will be reset by falling edge of SCL signal.
+     * |        |          |0 = The bus is normal status for transmission.
+     * |        |          |1 = The bus is hang-up status for transmission.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+     * |[19]    |ERRARBLO  |Error Arbitration Lost
+     * |        |          |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
+     * |        |          |The I2C can send start condition when ERRARBLO is set
+     * |        |          |Thus this bit doesn't be cared on slave mode.
+     * |        |          |0 = The bus is normal status for transmission.
+     * |        |          |1 = The bus is error arbitration lost status for transmission.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+     * @var UI2C_T::ADMAT
+     * Offset: 0x88  I2C Slave Match Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADMAT0    |USCI Address 0 Match Status Register
+     * |        |          |When address 0 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[1]     |ADMAT1    |USCI Address 1 Match Status Register
+     * |        |          |When address 1 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * @var UI2C_T::TMCTL
+     * Offset: 0x8C  I2C Timing Configure Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |STCTL     |Setup Time Configure Control Register
+     * |        |          |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
+     * |        |          |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
+     * |[24:16] |HTCTL     |Hold Time Configure Control Register
+     * |        |          |This field is used to generate the delay timing between SCL falling edge SDA edge in
+     * |        |          |transmission mode.
+     * |        |          |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __O  uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __I  uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DEVADDR0;              /*!< [0x0044] USCI Device Address Register 0                                   */
+    __IO uint32_t DEVADDR1;              /*!< [0x0048] USCI Device Address Register 1                                   */
+    __IO uint32_t ADDRMSK0;              /*!< [0x004c] USCI Device Address Mask Register 0                              */
+    __IO uint32_t ADDRMSK1;              /*!< [0x0050] USCI Device Address Mask Register 1                              */
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t ADMAT;                 /*!< [0x0088] I2C Slave Match Address Register                                 */
+    __IO uint32_t TMCTL;                 /*!< [0x008c] I2C Timing Configure Control Register                            */
+
+} UI2C_T;
+
+/**
+    @addtogroup UI2C_CONST UI2C Bit Field Definition
+    Constant Definitions for UI2C Controller
+@{ */
+
+#define UI2C_CTL_FUNMODE_Pos             (0)                                               /*!< UI2C_T::CTL: FUNMODE Position          */
+#define UI2C_CTL_FUNMODE_Msk             (0x7ul << UI2C_CTL_FUNMODE_Pos)                   /*!< UI2C_T::CTL: FUNMODE Mask              */
+
+#define UI2C_BRGEN_RCLKSEL_Pos           (0)                                               /*!< UI2C_T::BRGEN: RCLKSEL Position        */
+#define UI2C_BRGEN_RCLKSEL_Msk           (0x1ul << UI2C_BRGEN_RCLKSEL_Pos)                 /*!< UI2C_T::BRGEN: RCLKSEL Mask            */
+
+#define UI2C_BRGEN_PTCLKSEL_Pos          (1)                                               /*!< UI2C_T::BRGEN: PTCLKSEL Position       */
+#define UI2C_BRGEN_PTCLKSEL_Msk          (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos)                /*!< UI2C_T::BRGEN: PTCLKSEL Mask           */
+
+#define UI2C_BRGEN_SPCLKSEL_Pos          (2)                                               /*!< UI2C_T::BRGEN: SPCLKSEL Position       */
+#define UI2C_BRGEN_SPCLKSEL_Msk          (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos)                /*!< UI2C_T::BRGEN: SPCLKSEL Mask           */
+
+#define UI2C_BRGEN_TMCNTEN_Pos           (4)                                               /*!< UI2C_T::BRGEN: TMCNTEN Position        */
+#define UI2C_BRGEN_TMCNTEN_Msk           (0x1ul << UI2C_BRGEN_TMCNTEN_Pos)                 /*!< UI2C_T::BRGEN: TMCNTEN Mask            */
+
+#define UI2C_BRGEN_TMCNTSRC_Pos          (5)                                               /*!< UI2C_T::BRGEN: TMCNTSRC Position       */
+#define UI2C_BRGEN_TMCNTSRC_Msk          (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos)                /*!< UI2C_T::BRGEN: TMCNTSRC Mask           */
+
+#define UI2C_BRGEN_PDSCNT_Pos            (8)                                               /*!< UI2C_T::BRGEN: PDSCNT Position         */
+#define UI2C_BRGEN_PDSCNT_Msk            (0x3ul << UI2C_BRGEN_PDSCNT_Pos)                  /*!< UI2C_T::BRGEN: PDSCNT Mask             */
+
+#define UI2C_BRGEN_DSCNT_Pos             (10)                                              /*!< UI2C_T::BRGEN: DSCNT Position          */
+#define UI2C_BRGEN_DSCNT_Msk             (0x1ful << UI2C_BRGEN_DSCNT_Pos)                  /*!< UI2C_T::BRGEN: DSCNT Mask              */
+
+#define UI2C_BRGEN_CLKDIV_Pos            (16)                                              /*!< UI2C_T::BRGEN: CLKDIV Position         */
+#define UI2C_BRGEN_CLKDIV_Msk            (0x3fful << UI2C_BRGEN_CLKDIV_Pos)                /*!< UI2C_T::BRGEN: CLKDIV Mask             */
+
+#define UI2C_LINECTL_LSB_Pos             (0)                                               /*!< UI2C_T::LINECTL: LSB Position          */
+#define UI2C_LINECTL_LSB_Msk             (0x1ul << UI2C_LINECTL_LSB_Pos)                   /*!< UI2C_T::LINECTL: LSB Mask              */
+
+#define UI2C_LINECTL_DWIDTH_Pos          (8)                                               /*!< UI2C_T::LINECTL: DWIDTH Position       */
+#define UI2C_LINECTL_DWIDTH_Msk          (0xful << UI2C_LINECTL_DWIDTH_Pos)                /*!< UI2C_T::LINECTL: DWIDTH Mask           */
+
+#define UI2C_TXDAT_TXDAT_Pos             (0)                                               /*!< UI2C_T::TXDAT: TXDAT Position          */
+#define UI2C_TXDAT_TXDAT_Msk             (0xfffful << UI2C_TXDAT_TXDAT_Pos)                /*!< UI2C_T::TXDAT: TXDAT Mask              */
+
+#define UI2C_RXDAT_RXDAT_Pos             (0)                                               /*!< UI2C_T::RXDAT: RXDAT Position          */
+#define UI2C_RXDAT_RXDAT_Msk             (0xfffful << UI2C_RXDAT_RXDAT_Pos)                /*!< UI2C_T::RXDAT: RXDAT Mask              */
+
+#define UI2C_DEVADDR0_DEVADDR_Pos        (0)                                               /*!< UI2C_T::DEVADDR0: DEVADDR Position     */
+#define UI2C_DEVADDR0_DEVADDR_Msk        (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos)            /*!< UI2C_T::DEVADDR0: DEVADDR Mask         */
+
+#define UI2C_DEVADDR1_DEVADDR_Pos        (0)                                               /*!< UI2C_T::DEVADDR1: DEVADDR Position     */
+#define UI2C_DEVADDR1_DEVADDR_Msk        (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos)            /*!< UI2C_T::DEVADDR1: DEVADDR Mask         */
+
+#define UI2C_ADDRMSK0_ADDRMSK_Pos        (0)                                               /*!< UI2C_T::ADDRMSK0: ADDRMSK Position     */
+#define UI2C_ADDRMSK0_ADDRMSK_Msk        (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos)            /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask         */
+
+#define UI2C_ADDRMSK1_ADDRMSK_Pos        (0)                                               /*!< UI2C_T::ADDRMSK1: ADDRMSK Position     */
+#define UI2C_ADDRMSK1_ADDRMSK_Msk        (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos)            /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask         */
+
+#define UI2C_WKCTL_WKEN_Pos              (0)                                               /*!< UI2C_T::WKCTL: WKEN Position           */
+#define UI2C_WKCTL_WKEN_Msk              (0x1ul << UI2C_WKCTL_WKEN_Pos)                    /*!< UI2C_T::WKCTL: WKEN Mask               */
+
+#define UI2C_WKCTL_WKADDREN_Pos          (1)                                               /*!< UI2C_T::WKCTL: WKADDREN Position       */
+#define UI2C_WKCTL_WKADDREN_Msk          (0x1ul << UI2C_WKCTL_WKADDREN_Pos)                /*!< UI2C_T::WKCTL: WKADDREN Mask           */
+
+#define UI2C_WKSTS_WKF_Pos               (0)                                               /*!< UI2C_T::WKSTS: WKF Position            */
+#define UI2C_WKSTS_WKF_Msk               (0x1ul << UI2C_WKSTS_WKF_Pos)                     /*!< UI2C_T::WKSTS: WKF Mask                */
+
+#define UI2C_PROTCTL_GCFUNC_Pos          (0)                                               /*!< UI2C_T::PROTCTL: GCFUNC Position       */
+#define UI2C_PROTCTL_GCFUNC_Msk          (0x1ul << UI2C_PROTCTL_GCFUNC_Pos)                /*!< UI2C_T::PROTCTL: GCFUNC Mask           */
+
+#define UI2C_PROTCTL_AA_Pos              (1)                                               /*!< UI2C_T::PROTCTL: AA Position           */
+#define UI2C_PROTCTL_AA_Msk              (0x1ul << UI2C_PROTCTL_AA_Pos)                    /*!< UI2C_T::PROTCTL: AA Mask               */
+
+#define UI2C_PROTCTL_STO_Pos             (2)                                               /*!< UI2C_T::PROTCTL: STO Position          */
+#define UI2C_PROTCTL_STO_Msk             (0x1ul << UI2C_PROTCTL_STO_Pos)                   /*!< UI2C_T::PROTCTL: STO Mask              */
+
+#define UI2C_PROTCTL_STA_Pos             (3)                                               /*!< UI2C_T::PROTCTL: STA Position          */
+#define UI2C_PROTCTL_STA_Msk             (0x1ul << UI2C_PROTCTL_STA_Pos)                   /*!< UI2C_T::PROTCTL: STA Mask              */
+
+#define UI2C_PROTCTL_ADDR10EN_Pos        (4)                                               /*!< UI2C_T::PROTCTL: ADDR10EN Position     */
+#define UI2C_PROTCTL_ADDR10EN_Msk        (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos)              /*!< UI2C_T::PROTCTL: ADDR10EN Mask         */
+
+#define UI2C_PROTCTL_PTRG_Pos            (5)                                               /*!< UI2C_T::PROTCTL: PTRG Position         */
+#define UI2C_PROTCTL_PTRG_Msk            (0x1ul << UI2C_PROTCTL_PTRG_Pos)                  /*!< UI2C_T::PROTCTL: PTRG Mask             */
+
+#define UI2C_PROTCTL_SCLOUTEN_Pos        (8)                                               /*!< UI2C_T::PROTCTL: SCLOUTEN Position     */
+#define UI2C_PROTCTL_SCLOUTEN_Msk        (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos)              /*!< UI2C_T::PROTCTL: SCLOUTEN Mask         */
+
+#define UI2C_PROTCTL_MONEN_Pos           (9)                                               /*!< UI2C_T::PROTCTL: MONEN Position        */
+#define UI2C_PROTCTL_MONEN_Msk           (0x1ul << UI2C_PROTCTL_MONEN_Pos)                 /*!< UI2C_T::PROTCTL: MONEN Mask            */
+
+#define UI2C_PROTCTL_TOCNT_Pos           (16)                                              /*!< UI2C_T::PROTCTL: TOCNT Position        */
+#define UI2C_PROTCTL_TOCNT_Msk           (0x3fful << UI2C_PROTCTL_TOCNT_Pos)               /*!< UI2C_T::PROTCTL: TOCNT Mask            */
+
+#define UI2C_PROTCTL_PROTEN_Pos          (31)                                              /*!< UI2C_T::PROTCTL: PROTEN Position       */
+#define UI2C_PROTCTL_PROTEN_Msk          (0x1ul << UI2C_PROTCTL_PROTEN_Pos)                /*!< UI2C_T::PROTCTL: PROTEN Mask           */
+
+#define UI2C_PROTIEN_TOIEN_Pos           (0)                                               /*!< UI2C_T::PROTIEN: TOIEN Position        */
+#define UI2C_PROTIEN_TOIEN_Msk           (0x1ul << UI2C_PROTIEN_TOIEN_Pos)                 /*!< UI2C_T::PROTIEN: TOIEN Mask            */
+
+#define UI2C_PROTIEN_STARIEN_Pos         (1)                                               /*!< UI2C_T::PROTIEN: STARIEN Position      */
+#define UI2C_PROTIEN_STARIEN_Msk         (0x1ul << UI2C_PROTIEN_STARIEN_Pos)               /*!< UI2C_T::PROTIEN: STARIEN Mask          */
+
+#define UI2C_PROTIEN_STORIEN_Pos         (2)                                               /*!< UI2C_T::PROTIEN: STORIEN Position      */
+#define UI2C_PROTIEN_STORIEN_Msk         (0x1ul << UI2C_PROTIEN_STORIEN_Pos)               /*!< UI2C_T::PROTIEN: STORIEN Mask          */
+
+#define UI2C_PROTIEN_NACKIEN_Pos         (3)                                               /*!< UI2C_T::PROTIEN: NACKIEN Position      */
+#define UI2C_PROTIEN_NACKIEN_Msk         (0x1ul << UI2C_PROTIEN_NACKIEN_Pos)               /*!< UI2C_T::PROTIEN: NACKIEN Mask          */
+
+#define UI2C_PROTIEN_ARBLOIEN_Pos        (4)                                               /*!< UI2C_T::PROTIEN: ARBLOIEN Position     */
+#define UI2C_PROTIEN_ARBLOIEN_Msk        (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos)              /*!< UI2C_T::PROTIEN: ARBLOIEN Mask         */
+
+#define UI2C_PROTIEN_ERRIEN_Pos          (5)                                               /*!< UI2C_T::PROTIEN: ERRIEN Position       */
+#define UI2C_PROTIEN_ERRIEN_Msk          (0x1ul << UI2C_PROTIEN_ERRIEN_Pos)                /*!< UI2C_T::PROTIEN: ERRIEN Mask           */
+
+#define UI2C_PROTIEN_ACKIEN_Pos          (6)                                               /*!< UI2C_T::PROTIEN: ACKIEN Position       */
+#define UI2C_PROTIEN_ACKIEN_Msk          (0x1ul << UI2C_PROTIEN_ACKIEN_Pos)                /*!< UI2C_T::PROTIEN: ACKIEN Mask           */
+
+#define UI2C_PROTSTS_TOIF_Pos            (5)                                               /*!< UI2C_T::PROTSTS: TOIF Position         */
+#define UI2C_PROTSTS_TOIF_Msk            (0x1ul << UI2C_PROTSTS_TOIF_Pos)                  /*!< UI2C_T::PROTSTS: TOIF Mask             */
+
+#define UI2C_PROTSTS_ONBUSY_Pos          (6)                                               /*!< UI2C_T::PROTSTS: ONBUSY Position       */
+#define UI2C_PROTSTS_ONBUSY_Msk          (0x1ul << UI2C_PROTSTS_ONBUSY_Pos)                /*!< UI2C_T::PROTSTS: ONBUSY Mask           */
+
+#define UI2C_PROTSTS_STARIF_Pos          (8)                                               /*!< UI2C_T::PROTSTS: STARIF Position       */
+#define UI2C_PROTSTS_STARIF_Msk          (0x1ul << UI2C_PROTSTS_STARIF_Pos)                /*!< UI2C_T::PROTSTS: STARIF Mask           */
+
+#define UI2C_PROTSTS_STORIF_Pos          (9)                                               /*!< UI2C_T::PROTSTS: STORIF Position       */
+#define UI2C_PROTSTS_STORIF_Msk          (0x1ul << UI2C_PROTSTS_STORIF_Pos)                /*!< UI2C_T::PROTSTS: STORIF Mask           */
+
+#define UI2C_PROTSTS_NACKIF_Pos          (10)                                              /*!< UI2C_T::PROTSTS: NACKIF Position       */
+#define UI2C_PROTSTS_NACKIF_Msk          (0x1ul << UI2C_PROTSTS_NACKIF_Pos)                /*!< UI2C_T::PROTSTS: NACKIF Mask           */
+
+#define UI2C_PROTSTS_ARBLOIF_Pos         (11)                                              /*!< UI2C_T::PROTSTS: ARBLOIF Position      */
+#define UI2C_PROTSTS_ARBLOIF_Msk         (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos)               /*!< UI2C_T::PROTSTS: ARBLOIF Mask          */
+
+#define UI2C_PROTSTS_ERRIF_Pos           (12)                                              /*!< UI2C_T::PROTSTS: ERRIF Position        */
+#define UI2C_PROTSTS_ERRIF_Msk           (0x1ul << UI2C_PROTSTS_ERRIF_Pos)                 /*!< UI2C_T::PROTSTS: ERRIF Mask            */
+
+#define UI2C_PROTSTS_ACKIF_Pos           (13)                                              /*!< UI2C_T::PROTSTS: ACKIF Position        */
+#define UI2C_PROTSTS_ACKIF_Msk           (0x1ul << UI2C_PROTSTS_ACKIF_Pos)                 /*!< UI2C_T::PROTSTS: ACKIF Mask            */
+
+#define UI2C_PROTSTS_SLASEL_Pos          (14)                                              /*!< UI2C_T::PROTSTS: SLASEL Position       */
+#define UI2C_PROTSTS_SLASEL_Msk          (0x1ul << UI2C_PROTSTS_SLASEL_Pos)                /*!< UI2C_T::PROTSTS: SLASEL Mask           */
+
+#define UI2C_PROTSTS_SLAREAD_Pos         (15)                                              /*!< UI2C_T::PROTSTS: SLAREAD Position      */
+#define UI2C_PROTSTS_SLAREAD_Msk         (0x1ul << UI2C_PROTSTS_SLAREAD_Pos)               /*!< UI2C_T::PROTSTS: SLAREAD Mask          */
+
+#define UI2C_PROTSTS_WKAKDONE_Pos        (16)                                              /*!< UI2C_T::PROTSTS: WKAKDONE Position     */
+#define UI2C_PROTSTS_WKAKDONE_Msk        (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos)              /*!< UI2C_T::PROTSTS: WKAKDONE Mask         */
+
+#define UI2C_PROTSTS_WRSTSWK_Pos         (17)                                              /*!< UI2C_T::PROTSTS: WRSTSWK Position      */
+#define UI2C_PROTSTS_WRSTSWK_Msk         (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos)               /*!< UI2C_T::PROTSTS: WRSTSWK Mask          */
+
+#define UI2C_PROTSTS_BUSHANG_Pos         (18)                                              /*!< UI2C_T::PROTSTS: BUSHANG Position      */
+#define UI2C_PROTSTS_BUSHANG_Msk         (0x1ul << UI2C_PROTSTS_BUSHANG_Pos)               /*!< UI2C_T::PROTSTS: BUSHANG Mask          */
+
+#define UI2C_PROTSTS_ERRARBLO_Pos        (19)                                              /*!< UI2C_T::PROTSTS: ERRARBLO Position     */
+#define UI2C_PROTSTS_ERRARBLO_Msk        (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos)              /*!< UI2C_T::PROTSTS: ERRARBLO Mask         */
+
+#define UI2C_ADMAT_ADMAT0_Pos            (0)                                               /*!< UI2C_T::ADMAT: ADMAT0 Position         */
+#define UI2C_ADMAT_ADMAT0_Msk            (0x1ul << UI2C_ADMAT_ADMAT0_Pos)                  /*!< UI2C_T::ADMAT: ADMAT0 Mask             */
+
+#define UI2C_ADMAT_ADMAT1_Pos            (1)                                               /*!< UI2C_T::ADMAT: ADMAT1 Position         */
+#define UI2C_ADMAT_ADMAT1_Msk            (0x1ul << UI2C_ADMAT_ADMAT1_Pos)                  /*!< UI2C_T::ADMAT: ADMAT1 Mask             */
+
+#define UI2C_TMCTL_STCTL_Pos             (0)                                               /*!< UI2C_T::TMCTL: STCTL Position          */
+#define UI2C_TMCTL_STCTL_Msk             (0x1fful << UI2C_TMCTL_STCTL_Pos)                 /*!< UI2C_T::TMCTL: STCTL Mask              */
+
+#define UI2C_TMCTL_HTCTL_Pos             (16)                                              /*!< UI2C_T::TMCTL: HTCTL Position          */
+#define UI2C_TMCTL_HTCTL_Msk             (0x1fful << UI2C_TMCTL_HTCTL_Pos)                 /*!< UI2C_T::TMCTL: HTCTL Mask              */
+
+/**@}*/ /* UI2C_CONST */
+/**@}*/ /* end of UI2C register group */
+
+
+/*---------------------- Controller Area Network Controller -------------------------*/
+/**
+    @addtogroup CAN Controller Area Network Controller(CAN)
+    Memory Mapped Structure for CAN Controller
+@{ */
+
+
+typedef struct {
+
+    /**
+     * @var CAN_IF_T::CREQ
+     * Offset: 0x20, 0x80  IFn Command Request Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |MessageNumber|Message Number
+     * |        |          |0x01-0x20: Valid Message Number, the Message Object in the Message
+     * |        |          |RAM is selected for data transfer.
+     * |        |          |0x00: Not a valid Message Number, interpreted as 0x20.
+     * |        |          |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+     * |[15]    |Busy      |Busy Flag
+     * |        |          |0 = Read/write action has finished.
+     * |        |          |1 = Writing to the IFn Command Request Register is in progress
+     * |        |          |This bit can only be read by the software.
+     * @var CAN_IF_T::CMASK
+     * Offset: 0x24, 0x84  IFn Command Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DAT_B     |Access Data Bytes [7:4]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+     * |[1]     |DAT_A     |Access Data Bytes [3:0]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+     * |[2]     |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+     * |        |          |0 = TxRqst bit unchanged.
+     * |        |          |1 = Set TxRqst bit.
+     * |        |          |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+     * |        |          |Access New Data Bit when Read Operation.
+     * |        |          |0 = NewDat bit remains unchanged.
+     * |        |          |1 = Clear NewDat bit in the Message Object.
+     * |        |          |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat
+     * |        |          |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+     * |[3]     |ClrIntPnd |Clear Interrupt Pending Bit
+     * |        |          |Write Operation:
+     * |        |          |When writing to a Message Object, this bit is ignored.
+     * |        |          |Read Operation:
+     * |        |          |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+     * |        |          |1 = Clear IntPnd bit in the Message Object.
+     * |[4]     |Control   |Control Access Control Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to IFn Message Buffer Register.
+     * |[5]     |Arb       |Access Arbitration Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+     * |[6]     |Mask      |Access Mask Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+     * |[7]     |WR_RD     |Write / Read Mode
+     * |        |          |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+     * |        |          |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+     * @var CAN_IF_T::MASK1
+     * Offset: 0x28, 0x88  IFn Mask 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |Msk       |Identifier Mask 15-0
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * @var CAN_IF_T::MASK2
+     * Offset: 0x2C, 0x8C  IFn Mask 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |Msk       |Identifier Mask 28-16
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * |[14]    |MDir      |Mask Message Direction
+     * |        |          |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+     * |        |          |1 = The message direction bit (Dir) is used for acceptance filtering.
+     * |[15]    |MXtd      |Mask Extended Identifier
+     * |        |          |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+     * |        |          |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+     * |        |          |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])
+     * |        |          |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+     * @var CAN_IF_T::ARB1
+     * Offset: 0x30, 0x90  IFn Arbitration 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ID        |Message Identifier 15-0
+     * |        |          |ID28 - ID0, 29-bit Identifier (Extended Frame)
+     * |        |          |ID28 - ID18, 11-bit Identifier (Standard Frame)
+     * @var CAN_IF_T::ARB2
+     * Offset: 0x34, 0x94  IFn Arbitration 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |ID        |Message Identifier 28-16
+     * |        |          |ID28 - ID0, 29-bit Identifier (Extended Frame)
+     * |        |          |ID28 - ID18, 11-bit Identifier (Standard Frame)
+     * |[13]    |Dir       |Message Direction
+     * |        |          |0 = Direction is receive.
+     * |        |          |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted
+     * |        |          |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+     * |        |          |1 = Direction is transmit.
+     * |        |          |On TxRqst, the respective Message Object is transmitted as a Data Frame
+     * |        |          |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+     * |[14]    |Xtd       |Extended Identifier
+     * |        |          |0 = The 11-bit (standard) Identifier will be used for this Message Object.
+     * |        |          |1 = The 29-bit (extended) Identifier will be used for this Message Object.
+     * |[15]    |MsgVal    |Message Valid
+     * |        |          |0 = The Message Object is ignored by the Message Handler.
+     * |        |          |1 = The Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])
+     * |        |          |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+     * @var CAN_IF_T::MCON
+     * Offset: 0x38, 0x98  IFn Message Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DLC       |Data Length Code
+     * |        |          |0-8: Data Frame has 0-8 data bytes.
+     * |        |          |9-15: Data Frame has 8 data bytes
+     * |        |          |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes
+     * |        |          |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+     * |        |          |Data(0): 1st data byte of a CAN Data Frame
+     * |        |          |Data(1): 2nd data byte of a CAN Data Frame
+     * |        |          |Data(2): 3rd data byte of a CAN Data Frame
+     * |        |          |Data(3): 4th data byte of a CAN Data Frame
+     * |        |          |Data(4): 5th data byte of a CAN Data Frame
+     * |        |          |Data(5): 6th data byte of a CAN Data Frame
+     * |        |          |Data(6): 7th data byte of a CAN Data Frame
+     * |        |          |Data(7): 8th data byte of a CAN Data Frame
+     * |        |          |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last
+     * |        |          |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object
+     * |        |          |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+     * |[7]     |EoB       |End of Buffer
+     * |        |          |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+     * |        |          |1 = Single Message Object or last Message Object of a FIFO Buffer.
+     * |        |          |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer
+     * |        |          |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one
+     * |[8]     |TxRqst    |Transmit Request
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |[9]     |RmtEn     |Remote Enable Bit
+     * |        |          |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+     * |        |          |1 = At the reception of a Remote Frame, TxRqst is set.
+     * |[10]    |RxIE      |Receive Interrupt Enable Bit
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+     * |        |          |1 = IntPnd will be set after a successful reception of a frame.
+     * |[11]    |TxIE      |Transmit Interrupt Enable Bit
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+     * |        |          |1 = IntPnd will be set after a successful transmission of a frame.
+     * |[12]    |UMask     |Use Acceptance Mask
+     * |        |          |0 = Mask ignored.
+     * |        |          |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+     * |        |          |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
+     * |[13]    |IntPnd    |Interrupt Pending
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt
+     * |        |          |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+     * |[14]    |MsgLst    |Message Lost (only valid for Message Objects with direction = receive).
+     * |        |          |0 = No message lost since last time this bit was reset by the CPU.
+     * |        |          |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+     * |[15]    |NewDat    |New Data
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_IF_T::DAT_A1
+     * Offset: 0x3C, 0x9C  IFn Data A1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_0_   |Data Byte 0
+     * |        |          |1st data byte of a CAN Data Frame
+     * |[15:8]  |Data_1_   |Data Byte 1
+     * |        |          |2nd data byte of a CAN Data Frame
+     * @var CAN_IF_T::DAT_A2
+     * Offset: 0x40, 0xA0  IFn Data A2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_2_   |Data Byte 2
+     * |        |          |3rd data byte of CAN Data Frame
+     * |[15:8]  |Data_3_   |Data Byte 3
+     * |        |          |4th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B1
+     * Offset: 0x44, 0xA4  IFn Data B1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_4_   |Data Byte 4
+     * |        |          |5th data byte of CAN Data Frame
+     * |[15:8]  |Data_5_   |Data Byte 5
+     * |        |          |6th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B2
+     * Offset: 0x48, 0xA8  IFn Data B2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_6_   |Data Byte 6
+     * |        |          |7th data byte of CAN Data Frame.
+     * |[15:8]  |Data_7_   |Data Byte 7
+     * |        |          |8th data byte of CAN Data Frame.
+     */
+    __IO uint32_t CREQ;         /*!< [0x0020] IFn Command Request Register                                     */
+    __IO uint32_t CMASK;        /*!< [0x0024] IFn Command Mask Register                                        */
+    __IO uint32_t MASK1;        /*!< [0x0028] IFn Mask 1 Register                                              */
+    __IO uint32_t MASK2;        /*!< [0x002c] IFn Mask 2 Register                                              */
+    __IO uint32_t ARB1;         /*!< [0x0030] IFn Arbitration 1 Register                                       */
+    __IO uint32_t ARB2;         /*!< [0x0034] IFn Arbitration 2 Register                                       */
+    __IO uint32_t MCON;         /*!< [0x0038] IFn Message Control Register                                     */
+    __IO uint32_t DAT_A1;       /*!< [0x003c] IFn Data A1 Register                                             */
+    __IO uint32_t DAT_A2;       /*!< [0x0040] IFn Data A2 Register                                             */
+    __IO uint32_t DAT_B1;       /*!< [0x0044] IFn Data B1 Register                                             */
+    __IO uint32_t DAT_B2;       /*!< [0x0048] IFn Data B2 Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I uint32_t RESERVE0[13];
+    /// @endcond //HIDDEN_SYMBOLS
+} CAN_IF_T;
+
+
+typedef struct {
+
+
+    /**
+     * @var CAN_T::CON
+     * Offset: 0x00  Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |Init      |Init Initialization
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Initialization is started.
+     * |[1]     |IE        |Module Interrupt Enable Bit
+     * |        |          |0 = Function interrupt is Disabled.
+     * |        |          |1 = Function interrupt is Enabled.
+     * |[2]     |SIE       |Status Change Interrupt Enable Bit
+     * |        |          |0 = Disabled - No Status Change Interrupt will be generated.
+     * |        |          |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+     * |[3]     |EIE       |Error Interrupt Enable Bit
+     * |        |          |0 = Disabled - No Error Status Interrupt will be generated.
+     * |        |          |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+     * |[5]     |DAR       |Automatic Re-transmission Disable Bit
+     * |        |          |0 = Automatic Retransmission of disturbed messages Enabled.
+     * |        |          |1 = Automatic Retransmission Disabled.
+     * |[6]     |CCE       |Configuration Change Enable Bit
+     * |        |          |0 = No write access to the Bit Timing Register.
+     * |        |          |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+     * |[7]     |Test      |Test Mode Enable Bit
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Test Mode.
+     * @var CAN_T::STATUS
+     * Offset: 0x04  Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |LEC       |Last Error Code (Type of the Last Error to Occur on the CAN Bus)
+     * |        |          |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus
+     * |        |          |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error
+     * |        |          |The unused code '7' may be written by the CPU to check for updates
+     * |        |          |The Error! Reference source not found
+     * |        |          |describes the error code.
+     * |[3]     |TxOK      |Transmitted a Message Successfully
+     * |        |          |0 = Since this bit was reset by the CPU, no message has been successfully transmitted
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+     * |[4]     |RxOK      |Received a Message Successfully
+     * |        |          |0 = No message has been successfully received since this bit was last reset by the CPU
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+     * |[5]     |EPass     |Error Passive (Read Only)
+     * |        |          |0 = The CAN Core is error active.
+     * |        |          |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+     * |[6]     |EWarn     |Error Warning Status (Read Only)
+     * |        |          |0 = Both error counters are below the error warning limit of 96.
+     * |        |          |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+     * |[7]     |BOff      |Bus-off Status (Read Only)
+     * |        |          |0 = The CAN module is not in bus-off state.
+     * |        |          |1 = The CAN module is in bus-off state.
+     * @var CAN_T::ERR
+     * Offset: 0x08  Error Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TEC       |Transmit Error Counter
+     * |        |          |Actual state of the Transmit Error Counter. Values between 0 and 255.
+     * |[14:8]  |REC       |Receive Error Counter
+     * |        |          |Actual state of the Receive Error Counter. Values between 0 and 127.
+     * |[15]    |RP        |Receive Error Passive
+     * |        |          |0 = The Receive Error Counter is below the error passive level.
+     * |        |          |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+     * @var CAN_T::BTIME
+     * Offset: 0x0C  Bit Timing Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |BRP       |Baud Rate Prescaler
+     * |        |          |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta
+     * |        |          |The bit time is built up from a multiple of this quanta
+     * |        |          |Valid values for the Baud Rate Prescaler are [0...63]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[7:6]   |SJW       |(Re)Synchronization Jump Width
+     * |        |          |0x0-0x3: Valid programmed values are [0...3]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[11:8]  |TSeg1     |Time Segment Before the Sample Point Minus Sync_Seg
+     * |        |          |0x01-0x0F: valid values for TSeg1 are [1...15]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+     * |[14:12] |TSeg2     |Time Segment After Sample Point
+     * |        |          |0x0-0x7: Valid values for TSeg2 are [0...7]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * @var CAN_T::IIDR
+     * Offset: 0x10  Interrupt Identifier Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntId     |Interrupt Identifier (Indicates the Source of the Interrupt)
+     * |        |          |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order
+     * |        |          |An interrupt remains pending until the application software has cleared it
+     * |        |          |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active
+     * |        |          |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+     * |        |          |The Status Interrupt has the highest priority
+     * |        |          |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+     * |        |          |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13])
+     * |        |          |The Status Interrupt is cleared by reading the Status Register.
+     * @var CAN_T::TEST
+     * Offset: 0x14  Test Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |Basic     |Basic Mode
+     * |        |          |0 = Basic Mode Disabled.
+     * |        |          |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+     * |[3]     |Silent    |Silent Mode
+     * |        |          |0 = Normal operation.
+     * |        |          |1 = The module is in Silent Mode.
+     * |[4]     |LBack     |Loop Back Mode Enable Bit
+     * |        |          |0 = Loop Back Mode is Disabled.
+     * |        |          |1 = Loop Back Mode is Enabled.
+     * |[6:5]   |Tx        |Tx[1:0]: Control of CAN_TX Pin
+     * |        |          |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+     * |        |          |01 = Sample Point can be monitored at CAN_TX pin.
+     * |        |          |10 = CAN_TX pin drives a dominant ('0') value.
+     * |        |          |11 = CAN_TX pin drives a recessive ('1') value.
+     * |[7]     |Rx        |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)
+     * |        |          |0 = The CAN bus is dominant (CAN_RX = '0').
+     * |        |          |1 = The CAN bus is recessive (CAN_RX = '1').
+     * @var CAN_T::BRPE
+     * Offset: 0x18  Baud Rate Prescaler Extension Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |BRPE      |BRPE: Baud Rate Prescaler Extension
+     * |        |          |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023
+     * |        |          |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+     * @var CAN_T::TXREQ1
+     * Offset: 0x100  Transmission Request Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::TXREQ2
+     * Offset: 0x104  Transmission Request Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::NDAT1
+     * Offset: 0x120  New Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData16_1|New Data Bits 16-1 (of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::NDAT2
+     * Offset: 0x124  New Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData32_17|New Data Bits 32-17 (of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::IPND1
+     * Offset: 0x140  Interrupt Pending Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::IPND2
+     * Offset: 0x144  Interrupt Pending Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::MVLD1
+     * Offset: 0x160  Message Valid Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex
+     * |        |          |CAN_MVLD1[0] means Message object No.1 is valid or not
+     * |        |          |If CAN_MVLD1[0] is set, message object No.1 is configured.
+     * @var CAN_T::MVLD2
+     * Offset: 0x164  Message Valid Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not
+     * |        |          |If CAN_MVLD2[15] is set, message object No.32 is configured.
+     * @var CAN_T::WU_EN
+     * Offset: 0x168  Wake-up Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_EN  |Wake-up Enable Bit
+     * |        |          |0 = The wake-up function Disabled.
+     * |        |          |1 = The wake-up function Enabled.
+     * |        |          |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+     * @var CAN_T::WU_STATUS
+     * Offset: 0x16C  Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_STS |Wake-up Status
+     * |        |          |0 = No wake-up event occurred.
+     * |        |          |1 = Wake-up event occurred.
+     * |        |          |Note: This bit can be cleared by writing '0'.
+     */
+    __IO uint32_t CON;                   /*!< [0x0000] Control Register                                                 */
+    __IO uint32_t STATUS;                /*!< [0x0004] Status Register                                                  */
+    __I  uint32_t ERR;                   /*!< [0x0008] Error Counter Register                                           */
+    __IO uint32_t BTIME;                 /*!< [0x000c] Bit Timing Register                                              */
+    __I  uint32_t IIDR;                  /*!< [0x0010] Interrupt Identifier Register                                    */
+    __IO uint32_t TEST;                  /*!< [0x0014] Test Register                                                    */
+    __IO uint32_t BRPE;                  /*!< [0x0018] Baud Rate Prescaler Extension Register                           */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO CAN_IF_T IF[2];
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t TXREQ1;                /*!< [0x0100] Transmission Request Register 1                                  */
+    __I  uint32_t TXREQ2;                /*!< [0x0104] Transmission Request Register 2                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t NDAT1;                 /*!< [0x0120] New Data Register 1                                              */
+    __I  uint32_t NDAT2;                 /*!< [0x0124] New Data Register 2                                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t IPND1;                 /*!< [0x0140] Interrupt Pending Register 1                                     */
+    __I  uint32_t IPND2;                 /*!< [0x0144] Interrupt Pending Register 2                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t MVLD1;                 /*!< [0x0160] Message Valid Register 1                                         */
+    __I  uint32_t MVLD2;                 /*!< [0x0164] Message Valid Register 2                                         */
+    __IO uint32_t WU_EN;                 /*!< [0x0168] Wake-up Enable Control Register                                  */
+    __IO uint32_t WU_STATUS;             /*!< [0x016c] Wake-up Status Register                                          */
+
+} CAN_T;
+
+/**
+    @addtogroup CAN_CONST CAN Bit Field Definition
+    Constant Definitions for CAN Controller
+@{ */
+
+#define CAN_CON_INIT_Pos                 (0)                                               /*!< CAN_T::CON: Init Position              */
+#define CAN_CON_INIT_Msk                 (0x1ul << CAN_CON_INIT_Pos)                       /*!< CAN_T::CON: Init Mask                  */
+
+#define CAN_CON_IE_Pos                   (1)                                               /*!< CAN_T::CON: IE Position                */
+#define CAN_CON_IE_Msk                   (0x1ul << CAN_CON_IE_Pos)                         /*!< CAN_T::CON: IE Mask                    */
+
+#define CAN_CON_SIE_Pos                  (2)                                               /*!< CAN_T::CON: SIE Position               */
+#define CAN_CON_SIE_Msk                  (0x1ul << CAN_CON_SIE_Pos)                        /*!< CAN_T::CON: SIE Mask                   */
+
+#define CAN_CON_EIE_Pos                  (3)                                               /*!< CAN_T::CON: EIE Position               */
+#define CAN_CON_EIE_Msk                  (0x1ul << CAN_CON_EIE_Pos)                        /*!< CAN_T::CON: EIE Mask                   */
+
+#define CAN_CON_DAR_Pos                  (5)                                               /*!< CAN_T::CON: DAR Position               */
+#define CAN_CON_DAR_Msk                  (0x1ul << CAN_CON_DAR_Pos)                        /*!< CAN_T::CON: DAR Mask                   */
+
+#define CAN_CON_CCE_Pos                  (6)                                               /*!< CAN_T::CON: CCE Position               */
+#define CAN_CON_CCE_Msk                  (0x1ul << CAN_CON_CCE_Pos)                        /*!< CAN_T::CON: CCE Mask                   */
+
+#define CAN_CON_TEST_Pos                 (7)                                               /*!< CAN_T::CON: Test Position              */
+#define CAN_CON_TEST_Msk                 (0x1ul << CAN_CON_TEST_Pos)                       /*!< CAN_T::CON: Test Mask                  */
+
+#define CAN_STATUS_LEC_Pos               (0)                                               /*!< CAN_T::STATUS: LEC Position            */
+#define CAN_STATUS_LEC_Msk               (0x7ul << CAN_STATUS_LEC_Pos)                     /*!< CAN_T::STATUS: LEC Mask                */
+
+#define CAN_STATUS_TXOK_Pos              (3)                                               /*!< CAN_T::STATUS: TxOK Position           */
+#define CAN_STATUS_TXOK_Msk              (0x1ul << CAN_STATUS_TXOK_Pos)                    /*!< CAN_T::STATUS: TxOK Mask               */
+
+#define CAN_STATUS_RXOK_Pos              (4)                                               /*!< CAN_T::STATUS: RxOK Position           */
+#define CAN_STATUS_RXOK_Msk              (0x1ul << CAN_STATUS_RXOK_Pos)                    /*!< CAN_T::STATUS: RxOK Mask               */
+
+#define CAN_STATUS_EPASS_Pos             (5)                                               /*!< CAN_T::STATUS: EPass Position          */
+#define CAN_STATUS_EPASS_Msk             (0x1ul << CAN_STATUS_EPASS_Pos)                   /*!< CAN_T::STATUS: EPass Mask              */
+
+#define CAN_STATUS_EWARN_Pos             (6)                                               /*!< CAN_T::STATUS: EWarn Position          */
+#define CAN_STATUS_EWARN_Msk             (0x1ul << CAN_STATUS_EWARN_Pos)                   /*!< CAN_T::STATUS: EWarn Mask              */
+
+#define CAN_STATUS_BOFF_Pos              (7)                                               /*!< CAN_T::STATUS: BOff Position           */
+#define CAN_STATUS_BOFF_Msk              (0x1ul << CAN_STATUS_BOFF_Pos)                    /*!< CAN_T::STATUS: BOff Mask               */
+
+#define CAN_ERR_TEC_Pos                  (0)                                               /*!< CAN_T::ERR: TEC Position               */
+#define CAN_ERR_TEC_Msk                  (0xfful << CAN_ERR_TEC_Pos)                       /*!< CAN_T::ERR: TEC Mask                   */
+
+#define CAN_ERR_REC_Pos                  (8)                                               /*!< CAN_T::ERR: REC Position               */
+#define CAN_ERR_REC_Msk                  (0x7ful << CAN_ERR_REC_Pos)                       /*!< CAN_T::ERR: REC Mask                   */
+
+#define CAN_ERR_RP_Pos                   (15)                                              /*!< CAN_T::ERR: RP Position                */
+#define CAN_ERR_RP_Msk                   (0x1ul << CAN_ERR_RP_Pos)                         /*!< CAN_T::ERR: RP Mask                    */
+
+#define CAN_BTIME_BRP_Pos                (0)                                               /*!< CAN_T::BTIME: BRP Position             */
+#define CAN_BTIME_BRP_Msk                (0x3ful << CAN_BTIME_BRP_Pos)                     /*!< CAN_T::BTIME: BRP Mask                 */
+
+#define CAN_BTIME_SJW_Pos                (6)                                               /*!< CAN_T::BTIME: SJW Position             */
+#define CAN_BTIME_SJW_Msk                (0x3ul << CAN_BTIME_SJW_Pos)                      /*!< CAN_T::BTIME: SJW Mask                 */
+
+#define CAN_BTIME_TSEG1_Pos              (8)                                               /*!< CAN_T::BTIME: TSeg1 Position           */
+#define CAN_BTIME_TSEG1_Msk              (0xful << CAN_BTIME_TSEG1_Pos)                    /*!< CAN_T::BTIME: TSeg1 Mask               */
+
+#define CAN_BTIME_TSEG2_Pos              (12)                                              /*!< CAN_T::BTIME: TSeg2 Position           */
+#define CAN_BTIME_TSEG2_Msk              (0x7ul << CAN_BTIME_TSEG2_Pos)                    /*!< CAN_T::BTIME: TSeg2 Mask               */
+
+#define CAN_IIDR_IntId_Pos               (0)                                               /*!< CAN_T::IIDR: IntId Position            */
+#define CAN_IIDR_IntId_Msk               (0xfffful << CAN_IIDR_IntId_Pos)                  /*!< CAN_T::IIDR: IntId Mask                */
+
+#define CAN_TEST_BASIC_Pos               (2)                                               /*!< CAN_T::TEST: Basic Position            */
+#define CAN_TEST_BASIC_Msk               (0x1ul << CAN_TEST_BASIC_Pos)                     /*!< CAN_T::TEST: Basic Mask                */
+
+#define CAN_TEST_SILENT_Pos              (3)                                               /*!< CAN_T::TEST: Silent Position           */
+#define CAN_TEST_SILENT_Msk              (0x1ul << CAN_TEST_SILENT_Pos)                    /*!< CAN_T::TEST: Silent Mask               */
+
+#define CAN_TEST_LBACK_Pos               (4)                                               /*!< CAN_T::TEST: LBack Position            */
+#define CAN_TEST_LBACK_Msk               (0x1ul << CAN_TEST_LBACK_Pos)                     /*!< CAN_T::TEST: LBack Mask                */
+
+#define CAN_TEST_Tx_Pos                  (5)                                               /*!< CAN_T::TEST: Tx Position               */
+#define CAN_TEST_Tx_Msk                  (0x3ul << CAN_TEST_Tx_Pos)                        /*!< CAN_T::TEST: Tx Mask                   */
+
+#define CAN_TEST_Rx_Pos                  (7)                                               /*!< CAN_T::TEST: Rx Position               */
+#define CAN_TEST_Rx_Msk                  (0x1ul << CAN_TEST_Rx_Pos)                        /*!< CAN_T::TEST: Rx Mask                   */
+
+#define CAN_BRPE_BRPE_Pos                (0)                                               /*!< CAN_T::BRPE: BRPE Position             */
+#define CAN_BRPE_BRPE_Msk                (0xful << CAN_BRPE_BRPE_Pos)                      /*!< CAN_T::BRPE: BRPE Mask                 */
+
+#define CAN_IF_CREQ_MSGNUM_Pos   (0)                                               /*!< CAN_IF_T::CREQ: MessageNumber Position*/
+#define CAN_IF_CREQ_MSGNUM_Msk   (0x3ful << CAN_IF_CREQ_MSGNUM_Pos)        /*!< CAN_IF_T::CREQ: MessageNumber Mask    */
+
+#define CAN_IF_CREQ_BUSY_Pos            (15)                                              /*!< CAN_IF_T::CREQ: Busy Position         */
+#define CAN_IF_CREQ_BUSY_Msk            (0x1ul << CAN_IF_CREQ_BUSY_Pos)                   /*!< CAN_IF_T::CREQ: Busy Mask             */
+
+#define CAN_IF_CMASK_DATAB_Pos          (0)                                               /*!< CAN_IF_T::CMASK: DAT_B Position       */
+#define CAN_IF_CMASK_DATAB_Msk          (0x1ul << CAN_IF_CMASK_DATAB_Pos)                /*!< CAN_IF_T::CMASK: DAT_B Mask           */
+
+#define CAN_IF_CMASK_DATAA_Pos          (1)                                               /*!< CAN_IF_T::CMASK: DAT_A Position       */
+#define CAN_IF_CMASK_DATAA_Msk          (0x1ul << CAN_IF_CMASK_DATAA_Pos)                /*!< CAN_IF_T::CMASK: DAT_A Mask           */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos  (2)                                               /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk  (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)        /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask   */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos      (3)                                               /*!< CAN_IF_T::CMASK: ClrIntPnd Position   */
+#define CAN_IF_CMASK_CLRINTPND_Msk      (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos)            /*!< CAN_IF_T::CMASK: ClrIntPnd Mask       */
+
+#define CAN_IF_CMASK_CONTROL_Pos        (4)                                               /*!< CAN_IF_T::CMASK: Control Position     */
+#define CAN_IF_CMASK_CONTROL_Msk        (0x1ul << CAN_IF_CMASK_CONTROL_Pos)              /*!< CAN_IF_T::CMASK: Control Mask         */
+
+#define CAN_IF_CMASK_ARB_Pos            (5)                                               /*!< CAN_IF_T::CMASK: Arb Position         */
+#define CAN_IF_CMASK_ARB_Msk            (0x1ul << CAN_IF_CMASK_ARB_Pos)                  /*!< CAN_IF_T::CMASK: Arb Mask             */
+
+#define CAN_IF_CMASK_MASK_Pos           (6)                                               /*!< CAN_IF_T::CMASK: Mask Position        */
+#define CAN_IF_CMASK_MASK_Msk           (0x1ul << CAN_IF_CMASK_MASK_Pos)                 /*!< CAN_IF_T::CMASK: Mask Mask            */
+
+#define CAN_IF_CMASK_WRRD_Pos          (7)                                               /*!< CAN_IF_T::CMASK: WR_RD Position       */
+#define CAN_IF_CMASK_WRRD_Msk          (0x1ul << CAN_IF_CMASK_WRRD_Pos)                /*!< CAN_IF_T::CMASK: WR_RD Mask           */
+
+#define CAN_IF_MASK1_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK1: Msk Position         */
+#define CAN_IF_MASK1_Msk_Msk            (0xfffful << CAN_IF_MASK1_Msk_Pos)               /*!< CAN_IF_T::MASK1: Msk Mask             */
+
+#define CAN_IF_MASK2_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK2: Msk Position         */
+#define CAN_IF_MASK2_Msk_Msk            (0x1ffful << CAN_IF_MASK2_Msk_Pos)               /*!< CAN_IF_T::MASK2: Msk Mask             */
+
+#define CAN_IF_MASK2_MDIR_Pos           (14)                                              /*!< CAN_IF_T::MASK2: MDir Position        */
+#define CAN_IF_MASK2_MDIR_Msk           (0x1ul << CAN_IF_MASK2_MDIR_Pos)                 /*!< CAN_IF_T::MASK2: MDir Mask            */
+
+#define CAN_IF_MASK2_MXTD_Pos           (15)                                              /*!< CAN_IF_T::MASK2: MXtd Position        */
+#define CAN_IF_MASK2_MXTD_Msk           (0x1ul << CAN_IF_MASK2_MXTD_Pos)                 /*!< CAN_IF_T::MASK2: MXtd Mask            */
+
+#define CAN_IF_ARB1_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB1: ID Position           */
+#define CAN_IF_ARB1_ID_Msk              (0xfffful << CAN_IF_ARB1_ID_Pos)                 /*!< CAN_IF_T::ARB1: ID Mask               */
+
+#define CAN_IF_ARB2_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB2: ID Position           */
+#define CAN_IF_ARB2_ID_Msk              (0x1ffful << CAN_IF_ARB2_ID_Pos)                 /*!< CAN_IF_T::ARB2: ID Mask               */
+
+#define CAN_IF_ARB2_DIR_Pos             (13)                                              /*!< CAN_IF_T::ARB2: Dir Position          */
+#define CAN_IF_ARB2_DIR_Msk             (0x1ul << CAN_IF_ARB2_DIR_Pos)                   /*!< CAN_IF_T::ARB2: Dir Mask              */
+
+#define CAN_IF_ARB2_XTD_Pos             (14)                                              /*!< CAN_IF_T::ARB2: Xtd Position          */
+#define CAN_IF_ARB2_XTD_Msk             (0x1ul << CAN_IF_ARB2_XTD_Pos)                   /*!< CAN_IF_T::ARB2: Xtd Mask              */
+
+#define CAN_IF_ARB2_MSGVAL_Pos          (15)                                              /*!< CAN_IF_T::ARB2: MsgVal Position       */
+#define CAN_IF_ARB2_MSGVAL_Msk          (0x1ul << CAN_IF_ARB2_MSGVAL_Pos)                /*!< CAN_IF_T::ARB2: MsgVal Mask           */
+
+#define CAN_IF_MCON_DLC_Pos             (0)                                               /*!< CAN_IF_T::MCON: DLC Position          */
+#define CAN_IF_MCON_DLC_Msk             (0xful << CAN_IF_MCON_DLC_Pos)                   /*!< CAN_IF_T::MCON: DLC Mask              */
+
+#define CAN_IF_MCON_EOB_Pos             (7)                                               /*!< CAN_IF_T::MCON: EoB Position          */
+#define CAN_IF_MCON_EOB_Msk             (0x1ul << CAN_IF_MCON_EOB_Pos)                   /*!< CAN_IF_T::MCON: EoB Mask              */
+
+#define CAN_IF_MCON_TxRqst_Pos          (8)                                               /*!< CAN_IF_T::MCON: TxRqst Position       */
+#define CAN_IF_MCON_TxRqst_Msk          (0x1ul << CAN_IF_MCON_TxRqst_Pos)                /*!< CAN_IF_T::MCON: TxRqst Mask           */
+
+#define CAN_IF_MCON_RmtEn_Pos           (9)                                               /*!< CAN_IF_T::MCON: RmtEn Position        */
+#define CAN_IF_MCON_RmtEn_Msk           (0x1ul << CAN_IF_MCON_RmtEn_Pos)                 /*!< CAN_IF_T::MCON: RmtEn Mask            */
+
+#define CAN_IF_MCON_RXIE_Pos            (10)                                              /*!< CAN_IF_T::MCON: RxIE Position         */
+#define CAN_IF_MCON_RXIE_Msk            (0x1ul << CAN_IF_MCON_RXIE_Pos)                  /*!< CAN_IF_T::MCON: RxIE Mask             */
+
+#define CAN_IF_MCON_TXIE_Pos            (11)                                              /*!< CAN_IF_T::MCON: TxIE Position         */
+#define CAN_IF_MCON_TXIE_Msk            (0x1ul << CAN_IF_MCON_TXIE_Pos)                  /*!< CAN_IF_T::MCON: TxIE Mask             */
+
+#define CAN_IF_MCON_UMASK_Pos           (12)                                              /*!< CAN_IF_T::MCON: UMask Position        */
+#define CAN_IF_MCON_UMASK_Msk           (0x1ul << CAN_IF_MCON_UMASK_Pos)                 /*!< CAN_IF_T::MCON: UMask Mask            */
+
+#define CAN_IF_MCON_IntPnd_Pos          (13)                                              /*!< CAN_IF_T::MCON: IntPnd Position       */
+#define CAN_IF_MCON_IntPnd_Msk          (0x1ul << CAN_IF_MCON_IntPnd_Pos)                /*!< CAN_IF_T::MCON: IntPnd Mask           */
+
+#define CAN_IF_MCON_MsgLst_Pos          (14)                                              /*!< CAN_IF_T::MCON: MsgLst Position       */
+#define CAN_IF_MCON_MsgLst_Msk          (0x1ul << CAN_IF_MCON_MsgLst_Pos)                /*!< CAN_IF_T::MCON: MsgLst Mask           */
+
+#define CAN_IF_MCON_NEWDAT_Pos          (15)                                              /*!< CAN_IF_T::MCON: NewDat Position       */
+#define CAN_IF_MCON_NEWDAT_Msk          (0x1ul << CAN_IF_MCON_NEWDAT_Pos)                 /*!< CAN_IF_T::MCON: NewDat Mask           */
+
+#define CAN_IF_DAT_A1_DATA0_Pos       (0)                                               /*!< CAN_IF_T::DAT_A1: Data_0_ Position    */
+#define CAN_IF_DAT_A1_DATA0_Msk       (0xfful << CAN_IF_DAT_A1_DATA0_Pos)            /*!< CAN_IF_T::DAT_A1: Data_0_ Mask        */
+
+#define CAN_IF_DAT_A1_DATA1_Pos       (8)                                               /*!< CAN_IF_T::DAT_A1: Data_1_ Position    */
+#define CAN_IF_DAT_A1_DATA1_Msk       (0xfful << CAN_IF_DAT_A1_DATA1_Pos)            /*!< CAN_IF_T::DAT_A1: Data_1_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA2_Pos       (0)                                               /*!< CAN_IF_T::DAT_A2: Data_2_ Position    */
+#define CAN_IF_DAT_A2_DATA2_Msk       (0xfful << CAN_IF_DAT_A2_DATA2_Pos)            /*!< CAN_IF_T::DAT_A2: Data_2_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA3_Pos       (8)                                               /*!< CAN_IF_T::DAT_A2: Data_3_ Position    */
+#define CAN_IF_DAT_A2_DATA3_Msk       (0xfful << CAN_IF_DAT_A2_DATA3_Pos)            /*!< CAN_IF_T::DAT_A2: Data_3_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA4_Pos       (0)                                               /*!< CAN_IF_T::DAT_B1: Data_4_ Position    */
+#define CAN_IF_DAT_B1_DATA4_Msk       (0xfful << CAN_IF_DAT_B1_DATA4_Pos)            /*!< CAN_IF_T::DAT_B1: Data_4_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA5_Pos       (8)                                               /*!< CAN_IF_T::DAT_B1: Data_5_ Position    */
+#define CAN_IF_DAT_B1_DATA5_Msk       (0xfful << CAN_IF_DAT_B1_DATA5_Pos)            /*!< CAN_IF_T::DAT_B1: Data_5_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA6_Pos       (0)                                               /*!< CAN_IF_T::DAT_B2: Data_6_ Position    */
+#define CAN_IF_DAT_B2_DATA6_Msk       (0xfful << CAN_IF_DAT_B2_DATA6_Pos)            /*!< CAN_IF_T::DAT_B2: Data_6_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA7_Pos       (8)                                               /*!< CAN_IF_T::DAT_B2: Data_7_ Position    */
+#define CAN_IF_DAT_B2_DATA7_Msk       (0xfful << CAN_IF_DAT_B2_DATA7_Pos)            /*!< CAN_IF_T::DAT_B2: Data_7_ Mask        */
+
+#define CAN_TXREQ1_TXRQST16_1_Pos        (0)                                               /*!< CAN_T::TXREQ1: TxRqst16_1 Position     */
+#define CAN_TXREQ1_TXRQST16_1_Msk        (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos)           /*!< CAN_T::TXREQ1: TxRqst16_1 Mask         */
+
+#define CAN_TXREQ2_TXRQST32_17_Pos       (0)                                               /*!< CAN_T::TXREQ2: TxRqst32_17 Position    */
+#define CAN_TXREQ2_TXRQST32_17_Msk       (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos)          /*!< CAN_T::TXREQ2: TxRqst32_17 Mask        */
+
+#define CAN_NDAT1_NewData16_1_Pos        (0)                                               /*!< CAN_T::NDAT1: NewData16_1 Position     */
+#define CAN_NDAT1_NewData16_1_Msk        (0xfffful << CAN_NDAT1_NewData16_1_Pos)           /*!< CAN_T::NDAT1: NewData16_1 Mask         */
+
+#define CAN_NDAT2_NewData32_17_Pos       (0)                                               /*!< CAN_T::NDAT2: NewData32_17 Position    */
+#define CAN_NDAT2_NewData32_17_Msk       (0xfffful << CAN_NDAT2_NewData32_17_Pos)          /*!< CAN_T::NDAT2: NewData32_17 Mask        */
+
+#define CAN_IPND1_IntPnd16_1_Pos         (0)                                               /*!< CAN_T::IPND1: IntPnd16_1 Position      */
+#define CAN_IPND1_IntPnd16_1_Msk         (0xfffful << CAN_IPND1_IntPnd16_1_Pos)            /*!< CAN_T::IPND1: IntPnd16_1 Mask          */
+
+#define CAN_IPND2_IntPnd32_17_Pos        (0)                                               /*!< CAN_T::IPND2: IntPnd32_17 Position     */
+#define CAN_IPND2_IntPnd32_17_Msk        (0xfffful << CAN_IPND2_IntPnd32_17_Pos)           /*!< CAN_T::IPND2: IntPnd32_17 Mask         */
+
+#define CAN_MVLD1_MsgVal16_1_Pos         (0)                                               /*!< CAN_T::MVLD1: MsgVal16_1 Position      */
+#define CAN_MVLD1_MsgVal16_1_Msk         (0xfffful << CAN_MVLD1_MsgVal16_1_Pos)            /*!< CAN_T::MVLD1: MsgVal16_1 Mask          */
+
+#define CAN_MVLD2_MsgVal32_17_Pos        (0)                                               /*!< CAN_T::MVLD2: MsgVal32_17 Position     */
+#define CAN_MVLD2_MsgVal32_17_Msk        (0xfffful << CAN_MVLD2_MsgVal32_17_Pos)           /*!< CAN_T::MVLD2: MsgVal32_17 Mask         */
+
+#define CAN_WU_EN_WAKUP_EN_Pos           (0)                                               /*!< CAN_T::WU_EN: WAKUP_EN Position        */
+#define CAN_WU_EN_WAKUP_EN_Msk           (0x1ul << CAN_WU_EN_WAKUP_EN_Pos)                 /*!< CAN_T::WU_EN: WAKUP_EN Mask            */
+
+#define CAN_WU_STATUS_WAKUP_STS_Pos      (0)                                               /*!< CAN_T::WU_STATUS: WAKUP_STS Position   */
+#define CAN_WU_STATUS_WAKUP_STS_Msk      (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos)            /*!< CAN_T::WU_STATUS: WAKUP_STS Mask       */
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+
+
+
+/*---------------------- SD Card Host Interface -------------------------*/
+/**
+    @addtogroup SDH SD Card Host Interface(SDH)
+    Memory Mapped Structure for SDH Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var SDH_T::FB
+     * Offset: 0x00~0x7C  Shared Buffer (FIFO)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |BUFFER    |Shared Buffer
+     * |        |          |Buffer for DMA transfer
+     * @var SDH_T::DMACTL
+     * Offset: 0x400  DMA Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DMAEN     |DMA Engine Enable Bit
+     * |        |          |0 = DMA Disabled.
+     * |        |          |1 = DMA Enabled.
+     * |        |          |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
+     * |        |          |Note: If target abort is occurred, DMAEN will be cleared.
+     * |[1]     |DMARST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset internal state machine and pointers
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto be cleared after few clock cycles.
+     * |        |          |Note: The software reset DMA related registers.
+     * |[3]     |SGEN      |Scatter-gather Function Enable Bit
+     * |        |          |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
+     * |        |          |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
+     * |        |          |The format of these Pads' will be described later).
+     * |[9]     |DMABUSY   |DMA Transfer Is in Progress
+     * |        |          |This bit indicates if SD Host is granted and doing DMA transfer or not.
+     * |        |          |0 = DMA transfer is not in progress.
+     * |        |          |1 = DMA transfer is in progress.
+     * @var SDH_T::DMASA
+     * Offset: 0x408  DMA Transfer Starting Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ORDER     |Determined to the PAD Table Fetching Is in Order or Out of Order
+     * |        |          |0 = PAD table is fetched in order.
+     * |        |          |1 = PAD table is fetched out of order.
+     * |        |          |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
+     * |[31:1]  |DMASA     |DMA Transfer Starting Address
+     * |        |          |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
+     * |        |          |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
+     * |        |          |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
+     * @var SDH_T::DMABCNT
+     * Offset: 0x40C  DMA Transfer Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[25:0]  |BCNT      |DMA Transfer Byte Count (Read Only)
+     * |        |          |This field indicates the remained byte count of DMA transfer
+     * |        |          |The value of this field is valid only when DMA is busy; otherwise, it is 0.
+     * @var SDH_T::DMAINTEN
+     * Offset: 0x410  DMA Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIEN  |DMA Read/Write Target Abort Interrupt Enable Bit
+     * |        |          |0 = Target abort interrupt generation Disabled during DMA transfer.
+     * |        |          |1 = Target abort interrupt generation Enabled during DMA transfer.
+     * |[1]     |WEOTIEN   |Wrong EOT Encountered Interrupt Enable Bit
+     * |        |          |0 = Interrupt generation Disabled when wrong EOT is encountered.
+     * |        |          |1 = Interrupt generation Enabled when wrong EOT is encountered.
+     * @var SDH_T::DMAINTSTS
+     * Offset: 0x414  DMA Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIF   |DMA Read/Write Target Abort Interrupt Flag
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note1: This bit is read only, but can be cleared by writing '1' to it.
+     * |        |          |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
+     * |        |          |DMA will stop transfer and respond this event and then go to IDLE state
+     * |        |          |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
+     * |[1]     |WEOTIF    |Wrong EOT Encountered Interrupt Flag
+     * |        |          |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
+     * |        |          |0 = No EOT encountered before DMA transfer finished.
+     * |        |          |1 = EOT encountered before DMA transfer finished.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::GCTL
+     * Offset: 0x800  Global Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GCTLRST   |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset SD host
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto cleared after reset complete.
+     * |[1]     |SDEN      |Secure Digital Functionality Enable Bit
+     * |        |          |0 = SD functionality disabled.
+     * |        |          |1 = SD functionality enabled.
+     * @var SDH_T::GINTEN
+     * Offset: 0x804  Global Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIEN    |DMA READ/WRITE Target Abort Interrupt Enable Bit
+     * |        |          |0 = DMA READ/WRITE target abort interrupt generation disabled.
+     * |        |          |1 = DMA READ/WRITE target abort interrupt generation enabled.
+     * @var SDH_T::GINTSTS
+     * Offset: 0x808  Global Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIF     |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
+     * |        |          |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
+     * |        |          |When Target Abort is occurred, please reset all engine.
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::CTL
+     * Offset: 0x820  SD Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |COEN      |Command Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output a command to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[1]     |RIEN      |Response Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[2]     |DIEN      |Data Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[3]     |DOEN      |Data Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[4]     |R2EN      |Response R2 Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[5]     |CLK74OEN  |Initial 74 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 74 clock cycles to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[6]     |CLK8OEN   |Generating 8 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 8 clock cycles.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[7]     |CLKKEEP   |SD Clock Enable Control
+     * |        |          |0 = SD host decided when to output clock and when to disable clock output automatically.
+     * |        |          |1 = SD clock always keeps free running.
+     * |[13:8]  |CMDCODE   |SD Command Code
+     * |        |          |This register contains the SD command code (0x00 - 0x3F).
+     * |[14]    |CTLRST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the internal state machine and counters
+     * |        |          |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared)
+     * |        |          |This bit will be auto cleared after few clock cycles.
+     * |[15]    |DBW       |SD Data Bus Width (for 1-bit / 4-bit Selection)
+     * |        |          |0 = Data bus width is 1-bit.
+     * |        |          |1 = Data bus width is 4-bit.
+     * |[23:16] |BLKCNT    |Block Counts to Be Transferred or Received
+     * |        |          |This field contains the block counts for data-in and data-out transfer
+     * |        |          |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
+     * |        |          |Don't fill 0x0 to this field.
+     * |        |          |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
+     * |[27:24] |SDNWR     |NWR Parameter for Block Write Operation
+     * |        |          |This value indicates the NWR parameter for data block write operation in SD clock counts
+     * |        |          |The actual clock cycle will be SDNWR+1.
+     * @var SDH_T::CMDARG
+     * Offset: 0x824  SD Command Argument Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ARGUMENT  |SD Command Argument
+     * |        |          |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
+     * |        |          |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
+     * @var SDH_T::INTEN
+     * Offset: 0x828  SD Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIEN   |Block Transfer Done Interrupt Enable Bit
+     * |        |          |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable.
+     * |        |          |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
+     * |[1]     |CRCIEN    |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
+     * |        |          |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable.
+     * |        |          |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
+     * |[8]     |CDIEN     |SD Card Detection Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when card is inserted or removed.
+     * |        |          |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable.
+     * |        |          |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
+     * |[12]    |RTOIEN    |Response Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled.
+     * |        |          |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
+     * |[13]    |DITOIEN   |Data Input Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when data input time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled.
+     * |        |          |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
+     * |[14]    |WKIEN     |Wake-up Signal Generating Enable Bit
+     * |        |          |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
+     * |        |          |0 = SD Card interrupt to wake-up chip Disabled.
+     * |        |          |1 = SD Card interrupt to wake-up chip Enabled.
+     * |[30]    |CDSRC     |SD Card Detect Source Selection
+     * |        |          |0 = From SD card's DAT3 pin.
+     * |        |          |Host need clock to got data on pin DAT3
+     * |        |          |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
+     * |        |          |1 = From GPIO pin.
+     * @var SDH_T::INTSTS
+     * Offset: 0x82C  SD Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIF    |Block Transfer Done Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has finished all data-in or data-out block transfer
+     * |        |          |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
+     * |        |          |0 = Not finished yet.
+     * |        |          |1 = Done.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[1]     |CRCIF     |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
+     * |        |          |When CRC error is occurred, software should reset SD engine
+     * |        |          |Some response (ex
+     * |        |          |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
+     * |        |          |In this condition, software should ignore CRC error and clears this bit manually.
+     * |        |          |0 = No CRC error is occurred.
+     * |        |          |1 = CRC error is occurred.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[2]     |CRC7      |CRC7 Check Status (Read Only)
+     * |        |          |SD host will check CRC7 correctness during each response in
+     * |        |          |If that response does not contain CRC7 information (ex
+     * |        |          |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[3]     |CRC16     |CRC16 Check Status of Data-in Transfer (Read Only)
+     * |        |          |SD host will check CRC16 correctness after data-in transfer.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[6:4]   |CRCSTS    |CRC Status Value of Data-out Transfer (Read Only)
+     * |        |          |SD host will record CRC status of data-out transfer
+     * |        |          |Software could use this value to identify what type of error is during data-out transfer.
+     * |        |          |010 = Positive CRC status.
+     * |        |          |101 = Negative CRC status.
+     * |        |          |111 = SD card programming error occurs.
+     * |[7]     |DAT0STS   |DAT0 Pin Status of Current Selected SD Port (Read Only)
+     * |        |          |This bit is the DAT0 pin status of current selected SD port.
+     * |[8]     |CDIF      |SD Card Detection Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD card is inserted or removed
+     * |        |          |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.
+     * |        |          |0 = No card is inserted or removed.
+     * |        |          |1 = There is a card inserted in or removed from SD.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[12]    |RTOIF     |Response Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Response time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[13]    |DITOIF    |Data Input Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Data input time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[16]    |CDSTS     |Card Detect Status of SD (Read Only)
+     * |        |          |This bit indicates the card detect pin status of SD, and is used for card detection
+     * |        |          |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
+     * |        |          |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
+     * |        |          |0 = Card removed.
+     * |        |          |1 = Card inserted.
+     * |        |          |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
+     * |        |          |0 = Card inserted.
+     * |        |          |1 = Card removed.
+     * |[18]    |DAT1STS   |DAT1 Pin Status of SD Port (Read Only)
+     * |        |          |This bit indicates the DAT1 pin status of SD port.
+     * @var SDH_T::RESP0
+     * Offset: 0x830  SD Receiving Response Token Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RESPTK0   |SD Receiving Response Token 0
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This field contains response bit 47-16 of the response token.
+     * @var SDH_T::RESP1
+     * Offset: 0x834  SD Receiving Response Token Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |RESPTK1   |SD Receiving Response Token 1
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This register contains the bit 15-8 of the response token.
+     * @var SDH_T::BLEN
+     * Offset: 0x838  SD Block Length Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |BLKLEN    |SD BLOCK LENGTH in Byte Unit
+     * |        |          |An 11-bit value specifies the SD transfer byte count of a block
+     * |        |          |The actual byte count is equal to BLKLEN+1.
+     * |        |          |Note: The default SD block length is 512 bytes
+     * @var SDH_T::TOUT
+     * Offset: 0x83C  SD Response/Data-in Time-out Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |TOUT      |SD Response/Data-in Time-out Value
+     * |        |          |A 24-bit value specifies the time-out counts of response and data input
+     * |        |          |SD host controller will wait start bit of response or data-in until this value reached
+     * |        |          |The time period depends on SD engine clock frequency
+     * |        |          |Do not write a small number into this field, or you may never get response or data due to time-out.
+     * |        |          |Note: Filling 0x0 into this field will disable hardware time-out function.
+     */
+
+    __IO uint32_t FB[32];                /*!< Shared Buffer (FIFO)                                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[224];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DMACTL;                /*!< [0x0400] DMA Control and Status Register                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DMASA;                 /*!< [0x0408] DMA Transfer Starting Address Register                           */
+    __I  uint32_t DMABCNT;               /*!< [0x040c] DMA Transfer Byte Count Register                                 */
+    __IO uint32_t DMAINTEN;              /*!< [0x0410] DMA Interrupt Enable Control Register                            */
+    __IO uint32_t DMAINTSTS;             /*!< [0x0414] DMA Interrupt Status Register                                    */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[250];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t GCTL;                  /*!< [0x0800] Global Control and Status Register                               */
+    __IO uint32_t GINTEN;                /*!< [0x0804] Global Interrupt Control Register                                */
+    __I  uint32_t GINTSTS;               /*!< [0x0808] Global Interrupt Status Register                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL;                   /*!< [0x0820] SD Control and Status Register                                   */
+    __IO uint32_t CMDARG;                /*!< [0x0824] SD Command Argument Register                                     */
+    __IO uint32_t INTEN;                 /*!< [0x0828] SD Interrupt Control Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x082c] SD Interrupt Status Register                                     */
+    __I  uint32_t RESP0;                 /*!< [0x0830] SD Receiving Response Token Register 0                           */
+    __I  uint32_t RESP1;                 /*!< [0x0834] SD Receiving Response Token Register 1                           */
+    __IO uint32_t BLEN;                  /*!< [0x0838] SD Block Length Register                                         */
+    __IO uint32_t TOUT;                  /*!< [0x083c] SD Response/Data-in Time-out Register                            */
+
+} SDH_T;
+
+
+/**
+    @addtogroup SDH_CONST SDH Bit Field Definition
+    Constant Definitions for SDH Controller
+@{ */
+
+#define SDH_DMACTL_DMAEN_Pos             (0)                                               /*!< SDH_T::DMACTL: DMAEN Position          */
+#define SDH_DMACTL_DMAEN_Msk             (0x1ul << SDH_DMACTL_DMAEN_Pos)                   /*!< SDH_T::DMACTL: DMAEN Mask              */
+
+#define SDH_DMACTL_DMARST_Pos            (1)                                               /*!< SDH_T::DMACTL: DMARST Position         */
+#define SDH_DMACTL_DMARST_Msk            (0x1ul << SDH_DMACTL_DMARST_Pos)                  /*!< SDH_T::DMACTL: DMARST Mask             */
+
+#define SDH_DMACTL_SGEN_Pos              (3)                                               /*!< SDH_T::DMACTL: SGEN Position           */
+#define SDH_DMACTL_SGEN_Msk              (0x1ul << SDH_DMACTL_SGEN_Pos)                    /*!< SDH_T::DMACTL: SGEN Mask               */
+
+#define SDH_DMACTL_DMABUSY_Pos           (9)                                               /*!< SDH_T::DMACTL: DMABUSY Position        */
+#define SDH_DMACTL_DMABUSY_Msk           (0x1ul << SDH_DMACTL_DMABUSY_Pos)                 /*!< SDH_T::DMACTL: DMABUSY Mask            */
+
+#define SDH_DMASA_ORDER_Pos              (0)                                               /*!< SDH_T::DMASA: ORDER Position           */
+#define SDH_DMASA_ORDER_Msk              (0x1ul << SDH_DMASA_ORDER_Pos)                    /*!< SDH_T::DMASA: ORDER Mask               */
+
+#define SDH_DMASA_DMASA_Pos              (1)                                               /*!< SDH_T::DMASA: DMASA Position           */
+#define SDH_DMASA_DMASA_Msk              (0x7ffffffful << SDH_DMASA_DMASA_Pos)             /*!< SDH_T::DMASA: DMASA Mask               */
+
+#define SDH_DMABCNT_BCNT_Pos             (0)                                               /*!< SDH_T::DMABCNT: BCNT Position          */
+#define SDH_DMABCNT_BCNT_Msk             (0x3fffffful << SDH_DMABCNT_BCNT_Pos)             /*!< SDH_T::DMABCNT: BCNT Mask              */
+
+#define SDH_DMAINTEN_ABORTIEN_Pos        (0)                                               /*!< SDH_T::DMAINTEN: ABORTIEN Position     */
+#define SDH_DMAINTEN_ABORTIEN_Msk        (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos)              /*!< SDH_T::DMAINTEN: ABORTIEN Mask         */
+
+#define SDH_DMAINTEN_WEOTIEN_Pos         (1)                                               /*!< SDH_T::DMAINTEN: WEOTIEN Position      */
+#define SDH_DMAINTEN_WEOTIEN_Msk         (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos)               /*!< SDH_T::DMAINTEN: WEOTIEN Mask          */
+
+#define SDH_DMAINTSTS_ABORTIF_Pos        (0)                                               /*!< SDH_T::DMAINTSTS: ABORTIF Position     */
+#define SDH_DMAINTSTS_ABORTIF_Msk        (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos)              /*!< SDH_T::DMAINTSTS: ABORTIF Mask         */
+
+#define SDH_DMAINTSTS_WEOTIF_Pos         (1)                                               /*!< SDH_T::DMAINTSTS: WEOTIF Position      */
+#define SDH_DMAINTSTS_WEOTIF_Msk         (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos)               /*!< SDH_T::DMAINTSTS: WEOTIF Mask          */
+
+#define SDH_GCTL_GCTLRST_Pos             (0)                                               /*!< SDH_T::GCTL: GCTLRST Position          */
+#define SDH_GCTL_GCTLRST_Msk             (0x1ul << SDH_GCTL_GCTLRST_Pos)                   /*!< SDH_T::GCTL: GCTLRST Mask              */
+
+#define SDH_GCTL_SDEN_Pos                (1)                                               /*!< SDH_T::GCTL: SDEN Position             */
+#define SDH_GCTL_SDEN_Msk                (0x1ul << SDH_GCTL_SDEN_Pos)                      /*!< SDH_T::GCTL: SDEN Mask                 */
+
+#define SDH_GINTEN_DTAIEN_Pos            (0)                                               /*!< SDH_T::GINTEN: DTAIEN Position         */
+#define SDH_GINTEN_DTAIEN_Msk            (0x1ul << SDH_GINTEN_DTAIEN_Pos)                  /*!< SDH_T::GINTEN: DTAIEN Mask             */
+
+#define SDH_GINTSTS_DTAIF_Pos            (0)                                               /*!< SDH_T::GINTSTS: DTAIF Position         */
+#define SDH_GINTSTS_DTAIF_Msk            (0x1ul << SDH_GINTSTS_DTAIF_Pos)                  /*!< SDH_T::GINTSTS: DTAIF Mask             */
+
+#define SDH_CTL_COEN_Pos                 (0)                                               /*!< SDH_T::CTL: COEN Position              */
+#define SDH_CTL_COEN_Msk                 (0x1ul << SDH_CTL_COEN_Pos)                       /*!< SDH_T::CTL: COEN Mask                  */
+
+#define SDH_CTL_RIEN_Pos                 (1)                                               /*!< SDH_T::CTL: RIEN Position              */
+#define SDH_CTL_RIEN_Msk                 (0x1ul << SDH_CTL_RIEN_Pos)                       /*!< SDH_T::CTL: RIEN Mask                  */
+
+#define SDH_CTL_DIEN_Pos                 (2)                                               /*!< SDH_T::CTL: DIEN Position              */
+#define SDH_CTL_DIEN_Msk                 (0x1ul << SDH_CTL_DIEN_Pos)                       /*!< SDH_T::CTL: DIEN Mask                  */
+
+#define SDH_CTL_DOEN_Pos                 (3)                                               /*!< SDH_T::CTL: DOEN Position              */
+#define SDH_CTL_DOEN_Msk                 (0x1ul << SDH_CTL_DOEN_Pos)                       /*!< SDH_T::CTL: DOEN Mask                  */
+
+#define SDH_CTL_R2EN_Pos                 (4)                                               /*!< SDH_T::CTL: R2EN Position              */
+#define SDH_CTL_R2EN_Msk                 (0x1ul << SDH_CTL_R2EN_Pos)                       /*!< SDH_T::CTL: R2EN Mask                  */
+
+#define SDH_CTL_CLK74OEN_Pos             (5)                                               /*!< SDH_T::CTL: CLK74OEN Position          */
+#define SDH_CTL_CLK74OEN_Msk             (0x1ul << SDH_CTL_CLK74OEN_Pos)                   /*!< SDH_T::CTL: CLK74OEN Mask              */
+
+#define SDH_CTL_CLK8OEN_Pos              (6)                                               /*!< SDH_T::CTL: CLK8OEN Position           */
+#define SDH_CTL_CLK8OEN_Msk              (0x1ul << SDH_CTL_CLK8OEN_Pos)                    /*!< SDH_T::CTL: CLK8OEN Mask               */
+
+#define SDH_CTL_CLKKEEP_Pos              (7)                                               /*!< SDH_T::CTL: CLKKEEP Position          */
+#define SDH_CTL_CLKKEEP_Msk              (0x1ul << SDH_CTL_CLKKEEP_Pos)                    /*!< SDH_T::CTL: CLKKEEP Mask              */
+
+#define SDH_CTL_CMDCODE_Pos              (8)                                               /*!< SDH_T::CTL: CMDCODE Position           */
+#define SDH_CTL_CMDCODE_Msk              (0x3ful << SDH_CTL_CMDCODE_Pos)                   /*!< SDH_T::CTL: CMDCODE Mask               */
+
+#define SDH_CTL_CTLRST_Pos               (14)                                              /*!< SDH_T::CTL: CTLRST Position            */
+#define SDH_CTL_CTLRST_Msk               (0x1ul << SDH_CTL_CTLRST_Pos)                     /*!< SDH_T::CTL: CTLRST Mask                */
+
+#define SDH_CTL_DBW_Pos                  (15)                                              /*!< SDH_T::CTL: DBW Position               */
+#define SDH_CTL_DBW_Msk                  (0x1ul << SDH_CTL_DBW_Pos)                        /*!< SDH_T::CTL: DBW Mask                   */
+
+#define SDH_CTL_BLKCNT_Pos               (16)                                              /*!< SDH_T::CTL: BLKCNT Position            */
+#define SDH_CTL_BLKCNT_Msk               (0xfful << SDH_CTL_BLKCNT_Pos)                    /*!< SDH_T::CTL: BLKCNT Mask                */
+
+#define SDH_CTL_SDNWR_Pos                (24)                                              /*!< SDH_T::CTL: SDNWR Position             */
+#define SDH_CTL_SDNWR_Msk                (0xful << SDH_CTL_SDNWR_Pos)                      /*!< SDH_T::CTL: SDNWR Mask                 */
+
+#define SDH_CMDARG_ARGUMENT_Pos          (0)                                               /*!< SDH_T::CMDARG: ARGUMENT Position       */
+#define SDH_CMDARG_ARGUMENT_Msk          (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos)         /*!< SDH_T::CMDARG: ARGUMENT Mask           */
+
+#define SDH_INTEN_BLKDIEN_Pos            (0)                                               /*!< SDH_T::INTEN: BLKDIEN Position         */
+#define SDH_INTEN_BLKDIEN_Msk            (0x1ul << SDH_INTEN_BLKDIEN_Pos)                  /*!< SDH_T::INTEN: BLKDIEN Mask             */
+
+#define SDH_INTEN_CRCIEN_Pos             (1)                                               /*!< SDH_T::INTEN: CRCIEN Position          */
+#define SDH_INTEN_CRCIEN_Msk             (0x1ul << SDH_INTEN_CRCIEN_Pos)                   /*!< SDH_T::INTEN: CRCIEN Mask              */
+
+#define SDH_INTEN_CDIEN_Pos              (8)                                               /*!< SDH_T::INTEN: CDIEN Position          */
+#define SDH_INTEN_CDIEN_Msk              (0x1ul << SDH_INTEN_CDIEN_Pos)                    /*!< SDH_T::INTEN: CDIEN Mask              */
+
+#define SDH_INTEN_RTOIEN_Pos             (12)                                              /*!< SDH_T::INTEN: RTOIEN Position          */
+#define SDH_INTEN_RTOIEN_Msk             (0x1ul << SDH_INTEN_RTOIEN_Pos)                   /*!< SDH_T::INTEN: RTOIEN Mask              */
+
+#define SDH_INTEN_DITOIEN_Pos            (13)                                              /*!< SDH_T::INTEN: DITOIEN Position         */
+#define SDH_INTEN_DITOIEN_Msk            (0x1ul << SDH_INTEN_DITOIEN_Pos)                  /*!< SDH_T::INTEN: DITOIEN Mask             */
+
+#define SDH_INTEN_WKIEN_Pos              (14)                                              /*!< SDH_T::INTEN: WKIEN Position           */
+#define SDH_INTEN_WKIEN_Msk              (0x1ul << SDH_INTEN_WKIEN_Pos)                    /*!< SDH_T::INTEN: WKIEN Mask               */
+
+#define SDH_INTEN_CDSRC_Pos              (30)                                              /*!< SDH_T::INTEN: CDSRC Position          */
+#define SDH_INTEN_CDSRC_Msk              (0x1ul << SDH_INTEN_CDSRC_Pos)                    /*!< SDH_T::INTEN: CDSRC Mask              */
+
+#define SDH_INTSTS_BLKDIF_Pos            (0)                                               /*!< SDH_T::INTSTS: BLKDIF Position         */
+#define SDH_INTSTS_BLKDIF_Msk            (0x1ul << SDH_INTSTS_BLKDIF_Pos)                  /*!< SDH_T::INTSTS: BLKDIF Mask             */
+
+#define SDH_INTSTS_CRCIF_Pos             (1)                                               /*!< SDH_T::INTSTS: CRCIF Position          */
+#define SDH_INTSTS_CRCIF_Msk             (0x1ul << SDH_INTSTS_CRCIF_Pos)                   /*!< SDH_T::INTSTS: CRCIF Mask              */
+
+#define SDH_INTSTS_CRC7_Pos              (2)                                               /*!< SDH_T::INTSTS: CRC7 Position           */
+#define SDH_INTSTS_CRC7_Msk              (0x1ul << SDH_INTSTS_CRC7_Pos)                    /*!< SDH_T::INTSTS: CRC7 Mask               */
+
+#define SDH_INTSTS_CRC16_Pos             (3)                                               /*!< SDH_T::INTSTS: CRC16 Position          */
+#define SDH_INTSTS_CRC16_Msk             (0x1ul << SDH_INTSTS_CRC16_Pos)                   /*!< SDH_T::INTSTS: CRC16 Mask              */
+
+#define SDH_INTSTS_CRCSTS_Pos            (4)                                               /*!< SDH_T::INTSTS: CRCSTS Position         */
+#define SDH_INTSTS_CRCSTS_Msk            (0x7ul << SDH_INTSTS_CRCSTS_Pos)                  /*!< SDH_T::INTSTS: CRCSTS Mask             */
+
+#define SDH_INTSTS_DAT0STS_Pos           (7)                                               /*!< SDH_T::INTSTS: DAT0STS Position        */
+#define SDH_INTSTS_DAT0STS_Msk           (0x1ul << SDH_INTSTS_DAT0STS_Pos)                 /*!< SDH_T::INTSTS: DAT0STS Mask            */
+
+#define SDH_INTSTS_CDIF_Pos              (8)                                               /*!< SDH_T::INTSTS: CDIF Position          */
+#define SDH_INTSTS_CDIF_Msk              (0x1ul << SDH_INTSTS_CDIF_Pos)                    /*!< SDH_T::INTSTS: CDIF Mask              */
+
+#define SDH_INTSTS_RTOIF_Pos             (12)                                              /*!< SDH_T::INTSTS: RTOIF Position          */
+#define SDH_INTSTS_RTOIF_Msk             (0x1ul << SDH_INTSTS_RTOIF_Pos)                   /*!< SDH_T::INTSTS: RTOIF Mask              */
+
+#define SDH_INTSTS_DITOIF_Pos            (13)                                              /*!< SDH_T::INTSTS: DITOIF Position         */
+#define SDH_INTSTS_DITOIF_Msk            (0x1ul << SDH_INTSTS_DITOIF_Pos)                  /*!< SDH_T::INTSTS: DITOIF Mask             */
+
+#define SDH_INTSTS_CDSTS_Pos             (16)                                              /*!< SDH_T::INTSTS: CDSTS Position         */
+#define SDH_INTSTS_CDSTS_Msk             (0x1ul << SDH_INTSTS_CDSTS_Pos)                   /*!< SDH_T::INTSTS: CDSTS Mask             */
+
+#define SDH_INTSTS_DAT1STS_Pos           (18)                                              /*!< SDH_T::INTSTS: DAT1STS Position        */
+#define SDH_INTSTS_DAT1STS_Msk           (0x1ul << SDH_INTSTS_DAT1STS_Pos)                 /*!< SDH_T::INTSTS: DAT1STS Mask            */
+
+#define SDH_RESP0_RESPTK0_Pos            (0)                                               /*!< SDH_T::RESP0: RESPTK0 Position         */
+#define SDH_RESP0_RESPTK0_Msk            (0xfffffffful << SDH_RESP0_RESPTK0_Pos)           /*!< SDH_T::RESP0: RESPTK0 Mask             */
+
+#define SDH_RESP1_RESPTK1_Pos            (0)                                               /*!< SDH_T::RESP1: RESPTK1 Position         */
+#define SDH_RESP1_RESPTK1_Msk            (0xfful << SDH_RESP1_RESPTK1_Pos)                 /*!< SDH_T::RESP1: RESPTK1 Mask             */
+
+#define SDH_BLEN_BLKLEN_Pos              (0)                                               /*!< SDH_T::BLEN: BLKLEN Position           */
+#define SDH_BLEN_BLKLEN_Msk              (0x7fful << SDH_BLEN_BLKLEN_Pos)                  /*!< SDH_T::BLEN: BLKLEN Mask               */
+
+#define SDH_TOUT_TOUT_Pos                (0)                                               /*!< SDH_T::TOUT: TOUT Position             */
+#define SDH_TOUT_TOUT_Msk                (0xfffffful << SDH_TOUT_TOUT_Pos)                 /*!< SDH_T::TOUT: TOUT Mask                 */
+
+/**@}*/ /* SDH_CONST */
+/**@}*/ /* end of SDH register group */
+
+
+
+/*---------------------- External Bus Interface Controller -------------------------*/
+/**
+    @addtogroup EBI External Bus Interface Controller(EBI)
+    Memory Mapped Structure for EBI Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var EBI_T::CTL0
+     * Offset: 0x00  External Bus Interface Bank0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL0
+     * Offset: 0x04  External Bus Interface Bank0 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     * @var EBI_T::CTL1
+     * Offset: 0x10  External Bus Interface Bank1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL1
+     * Offset: 0x14  External Bus Interface Bank1 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     * @var EBI_T::CTL2
+     * Offset: 0x20  External Bus Interface Bank2 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL2
+     * Offset: 0x24  External Bus Interface Bank2 Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC +1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] External Bus Interface Bank0 Control Register                    */
+    __IO uint32_t TCTL0;                 /*!< [0x0004] External Bus Interface Bank0 Timing Control Register             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL1;                  /*!< [0x0010] External Bus Interface Bank1 Control Register                    */
+    __IO uint32_t TCTL1;                 /*!< [0x0014] External Bus Interface Bank1 Timing Control Register             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CTL2;                  /*!< [0x0020] External Bus Interface Bank2 Control Register                    */
+    __IO uint32_t TCTL2;                 /*!< [0x0024] External Bus Interface Bank2 Timing Control Register             */
+
+} EBI_T;
+
+/**
+    @addtogroup EBI_CONST EBI Bit Field Definition
+    Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_CTL_EN_Pos                   (0)                                               /*!< EBI_T::CTL: EN Position                */
+#define EBI_CTL_EN_Msk                   (0x1ul << EBI_CTL_EN_Pos)                         /*!< EBI_T::CTL: EN Mask                    */
+
+#define EBI_CTL_DW16_Pos                 (1)                                               /*!< EBI_T::CTL: DW16 Position              */
+#define EBI_CTL_DW16_Msk                 (0x1ul << EBI_CTL_DW16_Pos)                       /*!< EBI_T::CTL: DW16 Mask                  */
+
+#define EBI_CTL_CSPOLINV_Pos             (2)                                               /*!< EBI_T::CTL: CSPOLINV Position          */
+#define EBI_CTL_CSPOLINV_Msk             (0x1ul << EBI_CTL_CSPOLINV_Pos)                   /*!< EBI_T::CTL: CSPOLINV Mask              */
+
+#define EBI_CTL_ADSEPEN_Pos              (3)                                               /*!< EBI_T::CTL: ADSEPEN Position           */
+#define EBI_CTL_ADSEPEN_Msk              (0x1ul << EBI_CTL_ADSEPEN_Pos)                    /*!< EBI_T::CTL: ADSEPEN Mask               */
+
+#define EBI_CTL_CACCESS_Pos              (4)                                               /*!< EBI_T::CTL: CACCESS Position           */
+#define EBI_CTL_CACCESS_Msk              (0x1ul << EBI_CTL_CACCESS_Pos)                    /*!< EBI_T::CTL: CACCESS Mask               */
+
+#define EBI_CTL_MCLKDIV_Pos              (8)                                               /*!< EBI_T::CTL: MCLKDIV Position           */
+#define EBI_CTL_MCLKDIV_Msk              (0x7ul << EBI_CTL_MCLKDIV_Pos)                    /*!< EBI_T::CTL: MCLKDIV Mask               */
+
+#define EBI_CTL_TALE_Pos                 (16)                                              /*!< EBI_T::CTL: TALE Position              */
+#define EBI_CTL_TALE_Msk                 (0x7ul << EBI_CTL_TALE_Pos)                       /*!< EBI_T::CTL: TALE Mask                  */
+
+#define EBI_CTL_WBUFEN_Pos               (24)                                              /*!< EBI_T::CTL: WBUFEN Position            */
+#define EBI_CTL_WBUFEN_Msk               (0x1ul << EBI_CTL_WBUFEN_Pos)                     /*!< EBI_T::CTL: WBUFEN Mask                */
+
+#define EBI_TCTL_TACC_Pos                (3)                                               /*!< EBI_T::TCTL: TACC Position             */
+#define EBI_TCTL_TACC_Msk                (0x1ful << EBI_TCTL_TACC_Pos)                     /*!< EBI_T::TCTL: TACC Mask                 */
+
+#define EBI_TCTL_TAHD_Pos                (8)                                               /*!< EBI_T::TCTL: TAHD Position             */
+#define EBI_TCTL_TAHD_Msk                (0x7ul << EBI_TCTL_TAHD_Pos)                      /*!< EBI_T::TCTL: TAHD Mask                 */
+
+#define EBI_TCTL_W2X_Pos                 (12)                                              /*!< EBI_T::TCTL: W2X Position              */
+#define EBI_TCTL_W2X_Msk                 (0xful << EBI_TCTL_W2X_Pos)                       /*!< EBI_T::TCTL: W2X Mask                  */
+
+#define EBI_TCTL_RAHDOFF_Pos             (22)                                              /*!< EBI_T::TCTL: RAHDOFF Position          */
+#define EBI_TCTL_RAHDOFF_Msk             (0x1ul << EBI_TCTL_RAHDOFF_Pos)                   /*!< EBI_T::TCTL: RAHDOFF Mask              */
+
+#define EBI_TCTL_WAHDOFF_Pos             (23)                                              /*!< EBI_T::TCTL: WAHDOFF Position          */
+#define EBI_TCTL_WAHDOFF_Msk             (0x1ul << EBI_TCTL_WAHDOFF_Pos)                   /*!< EBI_T::TCTL: WAHDOFF Mask              */
+
+#define EBI_TCTL_R2R_Pos                 (24)                                              /*!< EBI_T::TCTL: R2R Position              */
+#define EBI_TCTL_R2R_Msk                 (0xful << EBI_TCTL_R2R_Pos)                       /*!< EBI_T::TCTL: R2R Mask                  */
+
+#define EBI_CTL0_EN_Pos                  (0)                                               /*!< EBI_T::CTL0: EN Position               */
+#define EBI_CTL0_EN_Msk                  (0x1ul << EBI_CTL0_EN_Pos)                        /*!< EBI_T::CTL0: EN Mask                   */
+
+#define EBI_CTL0_DW16_Pos                (1)                                               /*!< EBI_T::CTL0: DW16 Position             */
+#define EBI_CTL0_DW16_Msk                (0x1ul << EBI_CTL0_DW16_Pos)                      /*!< EBI_T::CTL0: DW16 Mask                 */
+
+#define EBI_CTL0_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL0: CSPOLINV Position         */
+#define EBI_CTL0_CSPOLINV_Msk            (0x1ul << EBI_CTL0_CSPOLINV_Pos)                  /*!< EBI_T::CTL0: CSPOLINV Mask             */
+
+#define EBI_CTL0_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL0: ADSEPEN Position          */
+#define EBI_CTL0_ADSEPEN_Msk             (0x1ul << EBI_CTL0_ADSEPEN_Pos)                   /*!< EBI_T::CTL0: ADSEPEN Mask              */
+
+#define EBI_CTL0_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL0: CACCESS Position          */
+#define EBI_CTL0_CACCESS_Msk             (0x1ul << EBI_CTL0_CACCESS_Pos)                   /*!< EBI_T::CTL0: CACCESS Mask              */
+
+#define EBI_CTL0_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL0: MCLKDIV Position          */
+#define EBI_CTL0_MCLKDIV_Msk             (0x7ul << EBI_CTL0_MCLKDIV_Pos)                   /*!< EBI_T::CTL0: MCLKDIV Mask              */
+
+#define EBI_CTL0_TALE_Pos                (16)                                              /*!< EBI_T::CTL0: TALE Position             */
+#define EBI_CTL0_TALE_Msk                (0x7ul << EBI_CTL0_TALE_Pos)                      /*!< EBI_T::CTL0: TALE Mask                 */
+
+#define EBI_CTL0_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL0: WBUFEN Position           */
+#define EBI_CTL0_WBUFEN_Msk              (0x1ul << EBI_CTL0_WBUFEN_Pos)                    /*!< EBI_T::CTL0: WBUFEN Mask               */
+
+#define EBI_TCTL0_TACC_Pos               (3)                                               /*!< EBI_T::TCTL0: TACC Position            */
+#define EBI_TCTL0_TACC_Msk               (0x1ful << EBI_TCTL0_TACC_Pos)                    /*!< EBI_T::TCTL0: TACC Mask                */
+
+#define EBI_TCTL0_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL0: TAHD Position            */
+#define EBI_TCTL0_TAHD_Msk               (0x7ul << EBI_TCTL0_TAHD_Pos)                     /*!< EBI_T::TCTL0: TAHD Mask                */
+
+#define EBI_TCTL0_W2X_Pos                (12)                                              /*!< EBI_T::TCTL0: W2X Position             */
+#define EBI_TCTL0_W2X_Msk                (0xful << EBI_TCTL0_W2X_Pos)                      /*!< EBI_T::TCTL0: W2X Mask                 */
+
+#define EBI_TCTL0_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL0: RAHDOFF Position         */
+#define EBI_TCTL0_RAHDOFF_Msk            (0x1ul << EBI_TCTL0_RAHDOFF_Pos)                  /*!< EBI_T::TCTL0: RAHDOFF Mask             */
+
+#define EBI_TCTL0_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL0: WAHDOFF Position         */
+#define EBI_TCTL0_WAHDOFF_Msk            (0x1ul << EBI_TCTL0_WAHDOFF_Pos)                  /*!< EBI_T::TCTL0: WAHDOFF Mask             */
+
+#define EBI_TCTL0_R2R_Pos                (24)                                              /*!< EBI_T::TCTL0: R2R Position             */
+#define EBI_TCTL0_R2R_Msk                (0xful << EBI_TCTL0_R2R_Pos)                      /*!< EBI_T::TCTL0: R2R Mask                 */
+
+#define EBI_CTL1_EN_Pos                  (0)                                               /*!< EBI_T::CTL1: EN Position               */
+#define EBI_CTL1_EN_Msk                  (0x1ul << EBI_CTL1_EN_Pos)                        /*!< EBI_T::CTL1: EN Mask                   */
+
+#define EBI_CTL1_DW16_Pos                (1)                                               /*!< EBI_T::CTL1: DW16 Position             */
+#define EBI_CTL1_DW16_Msk                (0x1ul << EBI_CTL1_DW16_Pos)                      /*!< EBI_T::CTL1: DW16 Mask                 */
+
+#define EBI_CTL1_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL1: CSPOLINV Position         */
+#define EBI_CTL1_CSPOLINV_Msk            (0x1ul << EBI_CTL1_CSPOLINV_Pos)                  /*!< EBI_T::CTL1: CSPOLINV Mask             */
+
+#define EBI_CTL1_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL1: ADSEPEN Position          */
+#define EBI_CTL1_ADSEPEN_Msk             (0x1ul << EBI_CTL1_ADSEPEN_Pos)                   /*!< EBI_T::CTL1: ADSEPEN Mask              */
+
+#define EBI_CTL1_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL1: CACCESS Position          */
+#define EBI_CTL1_CACCESS_Msk             (0x1ul << EBI_CTL1_CACCESS_Pos)                   /*!< EBI_T::CTL1: CACCESS Mask              */
+
+#define EBI_CTL1_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL1: MCLKDIV Position          */
+#define EBI_CTL1_MCLKDIV_Msk             (0x7ul << EBI_CTL1_MCLKDIV_Pos)                   /*!< EBI_T::CTL1: MCLKDIV Mask              */
+
+#define EBI_CTL1_TALE_Pos                (16)                                              /*!< EBI_T::CTL1: TALE Position             */
+#define EBI_CTL1_TALE_Msk                (0x7ul << EBI_CTL1_TALE_Pos)                      /*!< EBI_T::CTL1: TALE Mask                 */
+
+#define EBI_CTL1_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL1: WBUFEN Position           */
+#define EBI_CTL1_WBUFEN_Msk              (0x1ul << EBI_CTL1_WBUFEN_Pos)                    /*!< EBI_T::CTL1: WBUFEN Mask               */
+
+#define EBI_TCTL1_TACC_Pos               (3)                                               /*!< EBI_T::TCTL1: TACC Position            */
+#define EBI_TCTL1_TACC_Msk               (0x1ful << EBI_TCTL1_TACC_Pos)                    /*!< EBI_T::TCTL1: TACC Mask                */
+
+#define EBI_TCTL1_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL1: TAHD Position            */
+#define EBI_TCTL1_TAHD_Msk               (0x7ul << EBI_TCTL1_TAHD_Pos)                     /*!< EBI_T::TCTL1: TAHD Mask                */
+
+#define EBI_TCTL1_W2X_Pos                (12)                                              /*!< EBI_T::TCTL1: W2X Position             */
+#define EBI_TCTL1_W2X_Msk                (0xful << EBI_TCTL1_W2X_Pos)                      /*!< EBI_T::TCTL1: W2X Mask                 */
+
+#define EBI_TCTL1_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL1: RAHDOFF Position         */
+#define EBI_TCTL1_RAHDOFF_Msk            (0x1ul << EBI_TCTL1_RAHDOFF_Pos)                  /*!< EBI_T::TCTL1: RAHDOFF Mask             */
+
+#define EBI_TCTL1_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL1: WAHDOFF Position         */
+#define EBI_TCTL1_WAHDOFF_Msk            (0x1ul << EBI_TCTL1_WAHDOFF_Pos)                  /*!< EBI_T::TCTL1: WAHDOFF Mask             */
+
+#define EBI_TCTL1_R2R_Pos                (24)                                              /*!< EBI_T::TCTL1: R2R Position             */
+#define EBI_TCTL1_R2R_Msk                (0xful << EBI_TCTL1_R2R_Pos)                      /*!< EBI_T::TCTL1: R2R Mask                 */
+
+#define EBI_CTL2_EN_Pos                  (0)                                               /*!< EBI_T::CTL2: EN Position               */
+#define EBI_CTL2_EN_Msk                  (0x1ul << EBI_CTL2_EN_Pos)                        /*!< EBI_T::CTL2: EN Mask                   */
+
+#define EBI_CTL2_DW16_Pos                (1)                                               /*!< EBI_T::CTL2: DW16 Position             */
+#define EBI_CTL2_DW16_Msk                (0x1ul << EBI_CTL2_DW16_Pos)                      /*!< EBI_T::CTL2: DW16 Mask                 */
+
+#define EBI_CTL2_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL2: CSPOLINV Position         */
+#define EBI_CTL2_CSPOLINV_Msk            (0x1ul << EBI_CTL2_CSPOLINV_Pos)                  /*!< EBI_T::CTL2: CSPOLINV Mask             */
+
+#define EBI_CTL2_ADSEPEN_Pos             (3)                                               /*!< EBI_T::CTL2: ADSEPEN Position          */
+#define EBI_CTL2_ADSEPEN_Msk             (0x1ul << EBI_CTL2_ADSEPEN_Pos)                   /*!< EBI_T::CTL2: ADSEPEN Mask              */
+
+#define EBI_CTL2_CACCESS_Pos             (4)                                               /*!< EBI_T::CTL2: CACCESS Position          */
+#define EBI_CTL2_CACCESS_Msk             (0x1ul << EBI_CTL2_CACCESS_Pos)                   /*!< EBI_T::CTL2: CACCESS Mask              */
+
+#define EBI_CTL2_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL2: MCLKDIV Position          */
+#define EBI_CTL2_MCLKDIV_Msk             (0x7ul << EBI_CTL2_MCLKDIV_Pos)                   /*!< EBI_T::CTL2: MCLKDIV Mask              */
+
+#define EBI_CTL2_TALE_Pos                (16)                                              /*!< EBI_T::CTL2: TALE Position             */
+#define EBI_CTL2_TALE_Msk                (0x7ul << EBI_CTL2_TALE_Pos)                      /*!< EBI_T::CTL2: TALE Mask                 */
+
+#define EBI_CTL2_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL2: WBUFEN Position           */
+#define EBI_CTL2_WBUFEN_Msk              (0x1ul << EBI_CTL2_WBUFEN_Pos)                    /*!< EBI_T::CTL2: WBUFEN Mask               */
+
+#define EBI_TCTL2_TACC_Pos               (3)                                               /*!< EBI_T::TCTL2: TACC Position            */
+#define EBI_TCTL2_TACC_Msk               (0x1ful << EBI_TCTL2_TACC_Pos)                    /*!< EBI_T::TCTL2: TACC Mask                */
+
+#define EBI_TCTL2_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL2: TAHD Position            */
+#define EBI_TCTL2_TAHD_Msk               (0x7ul << EBI_TCTL2_TAHD_Pos)                     /*!< EBI_T::TCTL2: TAHD Mask                */
+
+#define EBI_TCTL2_W2X_Pos                (12)                                              /*!< EBI_T::TCTL2: W2X Position             */
+#define EBI_TCTL2_W2X_Msk                (0xful << EBI_TCTL2_W2X_Pos)                      /*!< EBI_T::TCTL2: W2X Mask                 */
+
+#define EBI_TCTL2_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL2: RAHDOFF Position         */
+#define EBI_TCTL2_RAHDOFF_Msk            (0x1ul << EBI_TCTL2_RAHDOFF_Pos)                  /*!< EBI_T::TCTL2: RAHDOFF Mask             */
+
+#define EBI_TCTL2_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL2: WAHDOFF Position         */
+#define EBI_TCTL2_WAHDOFF_Msk            (0x1ul << EBI_TCTL2_WAHDOFF_Pos)                  /*!< EBI_T::TCTL2: WAHDOFF Mask             */
+
+#define EBI_TCTL2_R2R_Pos                (24)                                              /*!< EBI_T::TCTL2: R2R Position             */
+#define EBI_TCTL2_R2R_Msk                (0xful << EBI_TCTL2_R2R_Pos)                      /*!< EBI_T::TCTL2: R2R Mask                 */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+
+
+
+/*---------------------- USB Device Controller -------------------------*/
+/**
+    @addtogroup USBD USB Device Controller(USBD)
+    Memory Mapped Structure for USBD Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var USBD_EP_T::BUFSEG
+     * Offset: 0x000  Endpoint n Buffer Segmentation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:3]   |BUFSEG    |Endpoint Buffer Segmentation
+     * |        |          |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
+     * |        |          |USBD_SRAM address + { BUFSEG, 3'b000}
+     * |        |          |Where the USBD_SRAM address = USBD_BA+0x100h.
+     * |        |          |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description.
+     * @var USBD_EP_T::MXPLD
+     * Offset: 0x004  Endpoint n Maximal Payload Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |MXPLD     |Maximal Payload
+     * |        |          |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
+     * |        |          |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+     * |        |          |(1) When the register is written by CPU,
+     * |        |          |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
+     * |        |          |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
+     * |        |          |(2) When the register is read by CPU,
+     * |        |          |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
+     * |        |          |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
+     * |        |          |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+     * @var USBD_EP_T::CFG
+     * Offset: 0x008  Endpoint n Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPNUM     |Endpoint Number
+     * |        |          |These bits are used to define the endpoint number of the current endpoint
+     * |[4]     |ISOCH     |Isochronous Endpoint
+     * |        |          |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+     * |        |          |0 = No Isochronous endpoint.
+     * |        |          |1 = Isochronous endpoint.
+     * |[6:5]   |STATE     |Endpoint STATE
+     * |        |          |00 = Endpoint is Disabled.
+     * |        |          |01 = Out endpoint.
+     * |        |          |10 = IN endpoint.
+     * |        |          |11 = Undefined.
+     * |[7]     |DSQSYNC   |Data Sequence Synchronization
+     * |        |          |0 = DATA0 PID.
+     * |        |          |1 = DATA1 PID.
+     * |        |          |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
+     * |        |          |hardware will toggle automatically in IN token base on the bit.
+     * |[9]     |CSTALL    |Clear STALL Response
+     * |        |          |0 = Disable the device to clear the STALL handshake in setup stage.
+     * |        |          |1 = Clear the device to response STALL handshake in setup stage.
+     * @var USBD_EP_T::CFGP
+     * Offset: 0x00C  Endpoint n Set Stall and Clear In/Out Ready Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CLRRDY    |Clear Ready
+     * |        |          |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
+     * |        |          |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
+     * |        |          |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
+     * |        |          |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
+     * |        |          |This bit is write 1 only and is always 0 when it is read back.
+     * |[1]     |SSTALL    |Set STALL
+     * |        |          |0 = Disable the device to response STALL.
+     * |        |          |1 = Set the device to respond STALL automatically.
+     */
+    __IO uint32_t BUFSEG;               /*!< [0x0000] Endpoint n Buffer Segmentation Register                          */
+    __IO uint32_t MXPLD;                /*!< [0x0004] Endpoint n Maximal Payload Register                              */
+    __IO uint32_t CFG;                  /*!< [0x0008] Endpoint n Configuration Register                                */
+    __IO uint32_t CFGP;                 /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register     */
+
+} USBD_EP_T;
+
+typedef struct {
+
+
+    /**
+     * @var USBD_T::INTEN
+     * Offset: 0x00  USB Device Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSIEN    |Bus Event Interrupt Enable Bit
+     * |        |          |0 = BUS event interrupt Disabled.
+     * |        |          |1 = BUS event interrupt Enabled.
+     * |[1]     |USBIEN    |USB Event Interrupt Enable Bit
+     * |        |          |0 = USB event interrupt Disabled.
+     * |        |          |1 = USB event interrupt Enabled.
+     * |[2]     |VBDETIEN  |VBUS Detection Interrupt Enable Bit
+     * |        |          |0 = VBUS detection Interrupt Disabled.
+     * |        |          |1 = VBUS detection Interrupt Enabled.
+     * |[3]     |NEVWKIEN  |USB No-event-wake-up Interrupt Enable Bit
+     * |        |          |0 = No-event-wake-up Interrupt Disabled.
+     * |        |          |1 = No-event-wake-up Interrupt Enabled.
+     * |[4]     |SOFIEN    |Start of Frame Interrupt Enable Bit
+     * |        |          |0 = SOF Interrupt Disabled.
+     * |        |          |1 = SOF Interrupt Enabled.
+     * |[8]     |WKEN      |Wake-up Function Enable Bit
+     * |        |          |0 = USB wake-up function Disabled.
+     * |        |          |1 = USB wake-up function Enabled.
+     * |[15]    |INNAKEN   |Active NAK Function and Its Status in IN Token
+     * |        |          |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
+     * |        |          |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
+     * @var USBD_T::INTSTS
+     * Offset: 0x04  USB Device Interrupt Event Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSIF     |BUS Interrupt Status
+     * |        |          |The BUS event means that there is one of the suspense or the resume function in the bus.
+     * |        |          |0 = No BUS event occurred.
+     * |        |          |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
+     * |[1]     |USBIF     |USB Event Interrupt Status
+     * |        |          |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
+     * |        |          |0 = No USB event occurred.
+     * |        |          |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
+     * |[2]     |VBDETIF   |VBUS Detection Interrupt Status
+     * |        |          |0 = There is not attached/detached event in the USB.
+     * |        |          |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
+     * |[3]     |NEVWKIF   |No-event-wake-up Interrupt Status
+     * |        |          |0 = NEVWK event does not occur.
+     * |        |          |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
+     * |[4]     |SOFIF     |Start of Frame Interrupt Status
+     * |        |          |0 = SOF event does not occur.
+     * |        |          |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
+     * |[16]    |EPEVT0    |Endpoint 0's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 0.
+     * |        |          |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
+     * |[17]    |EPEVT1    |Endpoint 1's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 1.
+     * |        |          |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
+     * |[18]    |EPEVT2    |Endpoint 2's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 2.
+     * |        |          |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
+     * |[19]    |EPEVT3    |Endpoint 3's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 3.
+     * |        |          |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
+     * |[20]    |EPEVT4    |Endpoint 4's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 4.
+     * |        |          |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
+     * |[21]    |EPEVT5    |Endpoint 5's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 5.
+     * |        |          |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
+     * |[22]    |EPEVT6    |Endpoint 6's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 6.
+     * |        |          |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
+     * |[23]    |EPEVT7    |Endpoint 7's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 7.
+     * |        |          |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
+     * |[24]    |EPEVT8    |Endpoint 8's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 8.
+     * |        |          |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
+     * |[25]    |EPEVT9    |Endpoint 9's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 9.
+     * |        |          |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
+     * |[26]    |EPEVT10   |Endpoint 10's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 10.
+     * |        |          |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
+     * |[27]    |EPEVT11   |Endpoint 11's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 11.
+     * |        |          |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
+     * |[31]    |SETUP     |Setup Event Status
+     * |        |          |0 = No Setup event.
+     * |        |          |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
+     * @var USBD_T::FADDR
+     * Offset: 0x08  USB Device Function Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |FADDR     |USB Device Function Address
+     * @var USBD_T::EPSTS
+     * Offset: 0x0C  USB Device Endpoint Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7]     |OV        |Overrun
+     * |        |          |It indicates that the received data is over the maximum payload number or not.
+     * |        |          |0 = No overrun.
+     * |        |          |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
+     * @var USBD_T::ATTR
+     * Offset: 0x10  USB Device Bus Status and Attribution Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBRST    |USB Reset Status
+     * |        |          |0 = Bus no reset.
+     * |        |          |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
+     * |        |          |Note: This bit is read only.
+     * |[1]     |SUSPEND   |Suspend Status
+     * |        |          |0 = Bus no suspend.
+     * |        |          |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
+     * |        |          |Note: This bit is read only.
+     * |[2]     |RESUME    |Resume Status
+     * |        |          |0 = No bus resume.
+     * |        |          |1 = Resume from suspend.
+     * |        |          |Note: This bit is read only.
+     * |[3]     |TOUT      |Time-out Status
+     * |        |          |0 = No time-out.
+     * |        |          |1 = No Bus response more than 18 bits time.
+     * |        |          |Note: This bit is read only.
+     * |[4]     |PHYEN     |PHY Transceiver Function Enable Bit
+     * |        |          |0 = PHY transceiver function Disabled.
+     * |        |          |1 = PHY transceiver function Enabled.
+     * |[5]     |RWAKEUP   |Remote Wake-up
+     * |        |          |0 = Release the USB bus from K state.
+     * |        |          |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
+     * |[7]     |USBEN     |USB Controller Enable Bit
+     * |        |          |0 = USB Controller Disabled.
+     * |        |          |1 = USB Controller Enabled.
+     * |[8]     |DPPUEN    |Pull-up Resistor on USB_DP Enable Bit
+     * |        |          |0 = Pull-up resistor in USB_D+ bus Disabled.
+     * |        |          |1 = Pull-up resistor in USB_D+ bus Active.
+     * |[10]    |BYTEM     |CPU Access USB SRAM Size Mode Selection
+     * |        |          |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
+     * |        |          |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
+     * |[11]    |LPMACK    |LPM Token Acknowledge Enable Bit
+     * |        |          |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
+     * |        |          |0= the valid LPM Token will be NYET.
+     * |        |          |1= the valid LPM Token will be ACK.
+     * |[12]    |L1SUSPEND |LPM L1 Suspend
+     * |        |          |0 = Bus no L1 state suspend.
+     * |        |          |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
+     * |        |          |Note: This bit is read only.
+     * |[13]    |L1RESUME  |LPM L1 Resume
+     * |        |          |0 = Bus no LPM L1 state resume.
+     * |        |          |1 = LPM L1 state Resume from LPM L1 state suspend.
+     * |        |          |Note: This bit is read only.
+     * @var USBD_T::VBUSDET
+     * Offset: 0x14  USB Device VBUS Detection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDET   |Device VBUS Detection
+     * |        |          |0 = Controller is not attached to the USB host.
+     * |        |          |1 = Controller is attached to the USB host.
+     * @var USBD_T::STBUFSEG
+     * Offset: 0x18  SETUP Token Buffer Segmentation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:3]   |STBUFSEG  |SETUP Token Buffer Segmentation
+     * |        |          |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
+     * |        |          |USBD_SRAM address + {STBUFSEG, 3'b000}
+     * |        |          |Where the USBD_SRAM address = USBD_BA+0x100h.
+     * |        |          |Note: It is used for SETUP token only.
+     * @var USBD_T::EPSTS0
+     * Offset: 0x20  USB Device Endpoint Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[03:00] |EPSTS0    |Endpoint 0 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[07:04] |EPSTS1    |Endpoint 1 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[11:08] |EPSTS2    |Endpoint 2 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[15:12] |EPSTS3    |Endpoint 3 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[19:16] |EPSTS4    |Endpoint 4 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[23:20] |EPSTS5    |Endpoint 5 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[27:24] |EPSTS6    |Endpoint 6 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[31:28] |EPSTS7    |Endpoint 7 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * @var USBD_T::EPSTS1
+     * Offset: 0x24  USB Device Endpoint Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPSTS8    |Endpoint 8 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[7:4]   |EPSTS9    |Endpoint 9 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[11:8]  |EPSTS10   |Endpoint 10 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[15:12] |EPSTS11   |Endpoint 11 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0011 = Setup ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * @var USBD_T::LPMATTR
+     * Offset: 0x88  USB LPM Attribution Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |LPMLINKSTS|LPM Link State
+     * |        |          |These bits contain the bLinkState received with last ACK LPM Token
+     * |[7:4]   |LPMBESL   |LPM Best Effort Service Latency
+     * |        |          |These bits contain the BESL value received with last ACK LPM Token
+     * |[8]     |LPMRWAKUP |LPM Remote Wakeup
+     * |        |          |This bit contains the bRemoteWake value received with last ACK LPM Token
+     * @var USBD_T::FN
+     * Offset: 0x8C  USB Frame number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |FN        |Frame Number
+     * |        |          |These bits contain the 11-bits frame number in the last received SOF packet.
+     * @var USBD_T::SE0
+     * Offset: 0x90  USB Device Drive SE0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SE0       |Drive Single Ended Zero in USB Bus
+     * |        |          |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
+     * |        |          |0 = Normal operation.
+     * |        |          |1 = Force USB PHY transceiver to drive SE0.
+     */
+
+    __IO uint32_t INTEN;                 /*!< [0x0000] USB Device Interrupt Enable Register                             */
+    __IO uint32_t INTSTS;                /*!< [0x0004] USB Device Interrupt Event Status Register                       */
+    __IO uint32_t FADDR;                 /*!< [0x0008] USB Device Function Address Register                             */
+    __I  uint32_t EPSTS;                 /*!< [0x000c] USB Device Endpoint Status Register                              */
+    __IO uint32_t ATTR;                  /*!< [0x0010] USB Device Bus Status and Attribution Register                   */
+    __I  uint32_t VBUSDET;               /*!< [0x0014] USB Device VBUS Detection Register                               */
+    __IO uint32_t STBUFSEG;              /*!< [0x0018] SETUP Token Buffer Segmentation Register                         */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t EPSTS0;                /*!< [0x0020] USB Device Endpoint Status Register 0                            */
+    __I  uint32_t EPSTS1;                /*!< [0x0024] USB Device Endpoint Status Register 1                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[24];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t LPMATTR;               /*!< [0x0088] USB LPM Attribution Register                                     */
+    __I  uint32_t FN;                    /*!< [0x008c] USB Frame number Register                                        */
+    __IO uint32_t SE0;                   /*!< [0x0090] USB Device Drive SE0 Control Register                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[283];
+    /// @endcond //HIDDEN_SYMBOLS
+    USBD_EP_T     EP[12];                /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register                 */
+
+} USBD_T;
+
+
+/**
+    @addtogroup USBD_CONST USBD Bit Field Definition
+    Constant Definitions for USBD Controller
+@{ */
+
+#define USBD_INTEN_BUSIEN_Pos            (0)                                               /*!< USBD_T::INTEN: BUSIEN Position         */
+#define USBD_INTEN_BUSIEN_Msk            (0x1ul << USBD_INTEN_BUSIEN_Pos)                  /*!< USBD_T::INTEN: BUSIEN Mask             */
+
+#define USBD_INTEN_USBIEN_Pos            (1)                                               /*!< USBD_T::INTEN: USBIEN Position         */
+#define USBD_INTEN_USBIEN_Msk            (0x1ul << USBD_INTEN_USBIEN_Pos)                  /*!< USBD_T::INTEN: USBIEN Mask             */
+
+#define USBD_INTEN_VBDETIEN_Pos          (2)                                               /*!< USBD_T::INTEN: VBDETIEN Position       */
+#define USBD_INTEN_VBDETIEN_Msk          (0x1ul << USBD_INTEN_VBDETIEN_Pos)                /*!< USBD_T::INTEN: VBDETIEN Mask           */
+
+#define USBD_INTEN_NEVWKIEN_Pos          (3)                                               /*!< USBD_T::INTEN: NEVWKIEN Position       */
+#define USBD_INTEN_NEVWKIEN_Msk          (0x1ul << USBD_INTEN_NEVWKIEN_Pos)                /*!< USBD_T::INTEN: NEVWKIEN Mask           */
+
+#define USBD_INTEN_SOFIEN_Pos            (4)                                               /*!< USBD_T::INTEN: SOFIEN Position         */
+#define USBD_INTEN_SOFIEN_Msk            (0x1ul << USBD_INTEN_SOFIEN_Pos)                  /*!< USBD_T::INTEN: SOFIEN Mask             */
+
+#define USBD_INTEN_WKEN_Pos              (8)                                               /*!< USBD_T::INTEN: WKEN Position           */
+#define USBD_INTEN_WKEN_Msk              (0x1ul << USBD_INTEN_WKEN_Pos)                    /*!< USBD_T::INTEN: WKEN Mask               */
+
+#define USBD_INTEN_INNAKEN_Pos           (15)                                              /*!< USBD_T::INTEN: INNAKEN Position        */
+#define USBD_INTEN_INNAKEN_Msk           (0x1ul << USBD_INTEN_INNAKEN_Pos)                 /*!< USBD_T::INTEN: INNAKEN Mask            */
+
+#define USBD_INTSTS_BUSIF_Pos            (0)                                               /*!< USBD_T::INTSTS: BUSIF Position         */
+#define USBD_INTSTS_BUSIF_Msk            (0x1ul << USBD_INTSTS_BUSIF_Pos)                  /*!< USBD_T::INTSTS: BUSIF Mask             */
+
+#define USBD_INTSTS_USBIF_Pos            (1)                                               /*!< USBD_T::INTSTS: USBIF Position         */
+#define USBD_INTSTS_USBIF_Msk            (0x1ul << USBD_INTSTS_USBIF_Pos)                  /*!< USBD_T::INTSTS: USBIF Mask             */
+
+#define USBD_INTSTS_VBDETIF_Pos          (2)                                               /*!< USBD_T::INTSTS: VBDETIF Position       */
+#define USBD_INTSTS_VBDETIF_Msk          (0x1ul << USBD_INTSTS_VBDETIF_Pos)                /*!< USBD_T::INTSTS: VBDETIF Mask           */
+
+#define USBD_INTSTS_NEVWKIF_Pos          (3)                                               /*!< USBD_T::INTSTS: NEVWKIF Position       */
+#define USBD_INTSTS_NEVWKIF_Msk          (0x1ul << USBD_INTSTS_NEVWKIF_Pos)                /*!< USBD_T::INTSTS: NEVWKIF Mask           */
+
+#define USBD_INTSTS_SOFIF_Pos            (4)                                               /*!< USBD_T::INTSTS: SOFIF Position         */
+#define USBD_INTSTS_SOFIF_Msk            (0x1ul << USBD_INTSTS_SOFIF_Pos)                  /*!< USBD_T::INTSTS: SOFIF Mask             */
+
+#define USBD_INTSTS_EPEVT0_Pos           (16)                                              /*!< USBD_T::INTSTS: EPEVT0 Position        */
+#define USBD_INTSTS_EPEVT0_Msk           (0x1ul << USBD_INTSTS_EPEVT0_Pos)                 /*!< USBD_T::INTSTS: EPEVT0 Mask            */
+
+#define USBD_INTSTS_EPEVT1_Pos           (17)                                              /*!< USBD_T::INTSTS: EPEVT1 Position        */
+#define USBD_INTSTS_EPEVT1_Msk           (0x1ul << USBD_INTSTS_EPEVT1_Pos)                 /*!< USBD_T::INTSTS: EPEVT1 Mask            */
+
+#define USBD_INTSTS_EPEVT2_Pos           (18)                                              /*!< USBD_T::INTSTS: EPEVT2 Position        */
+#define USBD_INTSTS_EPEVT2_Msk           (0x1ul << USBD_INTSTS_EPEVT2_Pos)                 /*!< USBD_T::INTSTS: EPEVT2 Mask            */
+
+#define USBD_INTSTS_EPEVT3_Pos           (19)                                              /*!< USBD_T::INTSTS: EPEVT3 Position        */
+#define USBD_INTSTS_EPEVT3_Msk           (0x1ul << USBD_INTSTS_EPEVT3_Pos)                 /*!< USBD_T::INTSTS: EPEVT3 Mask            */
+
+#define USBD_INTSTS_EPEVT4_Pos           (20)                                              /*!< USBD_T::INTSTS: EPEVT4 Position        */
+#define USBD_INTSTS_EPEVT4_Msk           (0x1ul << USBD_INTSTS_EPEVT4_Pos)                 /*!< USBD_T::INTSTS: EPEVT4 Mask            */
+
+#define USBD_INTSTS_EPEVT5_Pos           (21)                                              /*!< USBD_T::INTSTS: EPEVT5 Position        */
+#define USBD_INTSTS_EPEVT5_Msk           (0x1ul << USBD_INTSTS_EPEVT5_Pos)                 /*!< USBD_T::INTSTS: EPEVT5 Mask            */
+
+#define USBD_INTSTS_EPEVT6_Pos           (22)                                              /*!< USBD_T::INTSTS: EPEVT6 Position        */
+#define USBD_INTSTS_EPEVT6_Msk           (0x1ul << USBD_INTSTS_EPEVT6_Pos)                 /*!< USBD_T::INTSTS: EPEVT6 Mask            */
+
+#define USBD_INTSTS_EPEVT7_Pos           (23)                                              /*!< USBD_T::INTSTS: EPEVT7 Position        */
+#define USBD_INTSTS_EPEVT7_Msk           (0x1ul << USBD_INTSTS_EPEVT7_Pos)                 /*!< USBD_T::INTSTS: EPEVT7 Mask            */
+
+#define USBD_INTSTS_EPEVT8_Pos           (24)                                              /*!< USBD_T::INTSTS: EPEVT8 Position        */
+#define USBD_INTSTS_EPEVT8_Msk           (0x1ul << USBD_INTSTS_EPEVT8_Pos)                 /*!< USBD_T::INTSTS: EPEVT8 Mask            */
+
+#define USBD_INTSTS_EPEVT9_Pos           (25)                                              /*!< USBD_T::INTSTS: EPEVT9 Position        */
+#define USBD_INTSTS_EPEVT9_Msk           (0x1ul << USBD_INTSTS_EPEVT9_Pos)                 /*!< USBD_T::INTSTS: EPEVT9 Mask            */
+
+#define USBD_INTSTS_EPEVT10_Pos          (26)                                              /*!< USBD_T::INTSTS: EPEVT10 Position       */
+#define USBD_INTSTS_EPEVT10_Msk          (0x1ul << USBD_INTSTS_EPEVT10_Pos)                /*!< USBD_T::INTSTS: EPEVT10 Mask           */
+
+#define USBD_INTSTS_EPEVT11_Pos          (27)                                              /*!< USBD_T::INTSTS: EPEVT11 Position       */
+#define USBD_INTSTS_EPEVT11_Msk          (0x1ul << USBD_INTSTS_EPEVT11_Pos)                /*!< USBD_T::INTSTS: EPEVT11 Mask           */
+
+#define USBD_INTSTS_SETUP_Pos            (31)                                              /*!< USBD_T::INTSTS: SETUP Position         */
+#define USBD_INTSTS_SETUP_Msk            (0x1ul << USBD_INTSTS_SETUP_Pos)                  /*!< USBD_T::INTSTS: SETUP Mask             */
+
+#define USBD_FADDR_FADDR_Pos             (0)                                               /*!< USBD_T::FADDR: FADDR Position          */
+#define USBD_FADDR_FADDR_Msk             (0x7ful << USBD_FADDR_FADDR_Pos)                  /*!< USBD_T::FADDR: FADDR Mask              */
+
+#define USBD_EPSTS_OV_Pos                (7)                                               /*!< USBD_T::EPSTS: OV Position             */
+#define USBD_EPSTS_OV_Msk                (0x1ul << USBD_EPSTS_OV_Pos)                      /*!< USBD_T::EPSTS: OV Mask                 */
+
+#define USBD_ATTR_USBRST_Pos             (0)                                               /*!< USBD_T::ATTR: USBRST Position          */
+#define USBD_ATTR_USBRST_Msk             (0x1ul << USBD_ATTR_USBRST_Pos)                   /*!< USBD_T::ATTR: USBRST Mask              */
+
+#define USBD_ATTR_SUSPEND_Pos            (1)                                               /*!< USBD_T::ATTR: SUSPEND Position         */
+#define USBD_ATTR_SUSPEND_Msk            (0x1ul << USBD_ATTR_SUSPEND_Pos)                  /*!< USBD_T::ATTR: SUSPEND Mask             */
+
+#define USBD_ATTR_RESUME_Pos             (2)                                               /*!< USBD_T::ATTR: RESUME Position          */
+#define USBD_ATTR_RESUME_Msk             (0x1ul << USBD_ATTR_RESUME_Pos)                   /*!< USBD_T::ATTR: RESUME Mask              */
+
+#define USBD_ATTR_TOUT_Pos               (3)                                               /*!< USBD_T::ATTR: TOUT Position            */
+#define USBD_ATTR_TOUT_Msk               (0x1ul << USBD_ATTR_TOUT_Pos)                     /*!< USBD_T::ATTR: TOUT Mask                */
+
+#define USBD_ATTR_PHYEN_Pos              (4)                                               /*!< USBD_T::ATTR: PHYEN Position           */
+#define USBD_ATTR_PHYEN_Msk              (0x1ul << USBD_ATTR_PHYEN_Pos)                    /*!< USBD_T::ATTR: PHYEN Mask               */
+
+#define USBD_ATTR_RWAKEUP_Pos            (5)                                               /*!< USBD_T::ATTR: RWAKEUP Position         */
+#define USBD_ATTR_RWAKEUP_Msk            (0x1ul << USBD_ATTR_RWAKEUP_Pos)                  /*!< USBD_T::ATTR: RWAKEUP Mask             */
+
+#define USBD_ATTR_USBEN_Pos              (7)                                               /*!< USBD_T::ATTR: USBEN Position           */
+#define USBD_ATTR_USBEN_Msk              (0x1ul << USBD_ATTR_USBEN_Pos)                    /*!< USBD_T::ATTR: USBEN Mask               */
+
+#define USBD_ATTR_DPPUEN_Pos             (8)                                               /*!< USBD_T::ATTR: DPPUEN Position          */
+#define USBD_ATTR_DPPUEN_Msk             (0x1ul << USBD_ATTR_DPPUEN_Pos)                   /*!< USBD_T::ATTR: DPPUEN Mask              */
+
+#define USBD_ATTR_BYTEM_Pos              (10)                                              /*!< USBD_T::ATTR: BYTEM Position           */
+#define USBD_ATTR_BYTEM_Msk              (0x1ul << USBD_ATTR_BYTEM_Pos)                    /*!< USBD_T::ATTR: BYTEM Mask               */
+
+#define USBD_ATTR_LPMACK_Pos             (11)                                              /*!< USBD_T::ATTR: LPMACK Position          */
+#define USBD_ATTR_LPMACK_Msk             (0x1ul << USBD_ATTR_LPMACK_Pos)                   /*!< USBD_T::ATTR: LPMACK Mask              */
+
+#define USBD_ATTR_L1SUSPEND_Pos          (12)                                              /*!< USBD_T::ATTR: L1SUSPEND Position       */
+#define USBD_ATTR_L1SUSPEND_Msk          (0x1ul << USBD_ATTR_L1SUSPEND_Pos)                /*!< USBD_T::ATTR: L1SUSPEND Mask           */
+
+#define USBD_ATTR_L1RESUME_Pos           (13)                                              /*!< USBD_T::ATTR: L1RESUME Position        */
+#define USBD_ATTR_L1RESUME_Msk           (0x1ul << USBD_ATTR_L1RESUME_Pos)                 /*!< USBD_T::ATTR: L1RESUME Mask            */
+
+#define USBD_VBUSDET_VBUSDET_Pos         (0)                                               /*!< USBD_T::VBUSDET: VBUSDET Position      */
+#define USBD_VBUSDET_VBUSDET_Msk         (0x1ul << USBD_VBUSDET_VBUSDET_Pos)               /*!< USBD_T::VBUSDET: VBUSDET Mask          */
+
+#define USBD_STBUFSEG_STBUFSEG_Pos       (3)                                               /*!< USBD_T::STBUFSEG: STBUFSEG Position    */
+#define USBD_STBUFSEG_STBUFSEG_Msk       (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos)            /*!< USBD_T::STBUFSEG: STBUFSEG Mask        */
+
+#define USBD_EPSTS0_EPSTS5_Pos           (20)                                              /*!< USBD_T::EPSTS0: EPSTS5 Position        */
+#define USBD_EPSTS0_EPSTS5_Msk           (0xful << USBD_EPSTS0_EPSTS5_Pos)                 /*!< USBD_T::EPSTS0: EPSTS5 Mask            */
+
+#define USBD_EPSTS0_EPSTS6_Pos           (24)                                              /*!< USBD_T::EPSTS0: EPSTS6 Position        */
+#define USBD_EPSTS0_EPSTS6_Msk           (0xful << USBD_EPSTS0_EPSTS6_Pos)                 /*!< USBD_T::EPSTS0: EPSTS6 Mask            */
+
+#define USBD_EPSTS0_EPSTS7_Pos           (28)                                              /*!< USBD_T::EPSTS0: EPSTS7 Position        */
+#define USBD_EPSTS0_EPSTS7_Msk           (0xful << USBD_EPSTS0_EPSTS7_Pos)                 /*!< USBD_T::EPSTS0: EPSTS7 Mask            */
+
+#define USBD_EPSTS1_EPSTS8_Pos           (0)                                               /*!< USBD_T::EPSTS1: EPSTS8 Position        */
+#define USBD_EPSTS1_EPSTS8_Msk           (0xful << USBD_EPSTS1_EPSTS8_Pos)                 /*!< USBD_T::EPSTS1: EPSTS8 Mask            */
+
+#define USBD_EPSTS1_EPSTS9_Pos           (4)                                               /*!< USBD_T::EPSTS1: EPSTS9 Position        */
+#define USBD_EPSTS1_EPSTS9_Msk           (0xful << USBD_EPSTS1_EPSTS9_Pos)                 /*!< USBD_T::EPSTS1: EPSTS9 Mask            */
+
+#define USBD_EPSTS1_EPSTS10_Pos          (8)                                               /*!< USBD_T::EPSTS1: EPSTS10 Position       */
+#define USBD_EPSTS1_EPSTS10_Msk          (0xful << USBD_EPSTS1_EPSTS10_Pos)                /*!< USBD_T::EPSTS1: EPSTS10 Mask           */
+
+#define USBD_EPSTS1_EPSTS11_Pos          (12)                                              /*!< USBD_T::EPSTS1: EPSTS11 Position       */
+#define USBD_EPSTS1_EPSTS11_Msk          (0xful << USBD_EPSTS1_EPSTS11_Pos)                /*!< USBD_T::EPSTS1: EPSTS11 Mask           */
+
+#define USBD_LPMATTR_LPMLINKSTS_Pos      (0)                                               /*!< USBD_T::LPMATTR: LPMLINKSTS Position   */
+#define USBD_LPMATTR_LPMLINKSTS_Msk      (0xful << USBD_LPMATTR_LPMLINKSTS_Pos)            /*!< USBD_T::LPMATTR: LPMLINKSTS Mask       */
+
+#define USBD_LPMATTR_LPMBESL_Pos         (4)                                               /*!< USBD_T::LPMATTR: LPMBESL Position      */
+#define USBD_LPMATTR_LPMBESL_Msk         (0xful << USBD_LPMATTR_LPMBESL_Pos)               /*!< USBD_T::LPMATTR: LPMBESL Mask          */
+
+#define USBD_LPMATTR_LPMRWAKUP_Pos       (8)                                               /*!< USBD_T::LPMATTR: LPMRWAKUP Position    */
+#define USBD_LPMATTR_LPMRWAKUP_Msk       (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos)             /*!< USBD_T::LPMATTR: LPMRWAKUP Mask        */
+
+#define USBD_FN_FN_Pos                   (0)                                               /*!< USBD_T::FN: FN Position                */
+#define USBD_FN_FN_Msk                   (0x7fful << USBD_FN_FN_Pos)                       /*!< USBD_T::FN: FN Mask                    */
+
+#define USBD_SE0_SE0_Pos                 (0)                                               /*!< USBD_T::SE0: SE0 Position              */
+#define USBD_SE0_SE0_Msk                 (0x1ul << USBD_SE0_SE0_Pos)                       /*!< USBD_T::SE0: SE0 Mask                  */
+
+#define USBD_BUFSEG_BUFSEG_Pos           (3)                                               /*!< USBD_EP_T::BUFSEG: BUFSEG Position     */
+#define USBD_BUFSEG_BUFSEG_Msk           (0x3ful << USBD_BUFSEG_BUFSEG_Pos)                /*!< USBD_EP_T::BUFSEG: BUFSEG Mask         */
+
+#define USBD_MXPLD_MXPLD_Pos             (0)                                               /*!< USBD_EP_T::MXPLD: MXPLD Position       */
+#define USBD_MXPLD_MXPLD_Msk             (0x1fful << USBD_MXPLD_MXPLD_Pos)                 /*!< USBD_EP_T::MXPLD: MXPLD Mask           */
+
+#define USBD_CFG_EPNUM_Pos               (0)                                               /*!< USBD_EP_T::CFG: EPNUM Position         */
+#define USBD_CFG_EPNUM_Msk               (0xful << USBD_CFG_EPNUM_Pos)                     /*!< USBD_EP_T::CFG: EPNUM Mask             */
+
+#define USBD_CFG_ISOCH_Pos               (4)                                               /*!< USBD_EP_T::CFG: ISOCH Position         */
+#define USBD_CFG_ISOCH_Msk               (0x1ul << USBD_CFG_ISOCH_Pos)                     /*!< USBD_EP_T::CFG: ISOCH Mask             */
+
+#define USBD_CFG_STATE_Pos               (5)                                               /*!< USBD_EP_T::CFG: STATE Position         */
+#define USBD_CFG_STATE_Msk               (0x3ul << USBD_CFG_STATE_Pos)                     /*!< USBD_EP_T::CFG: STATE Mask             */
+
+#define USBD_CFG_DSQSYNC_Pos             (7)                                               /*!< USBD_EP_T::CFG: DSQSYNC Position       */
+#define USBD_CFG_DSQSYNC_Msk             (0x1ul << USBD_CFG_DSQSYNC_Pos)                   /*!< USBD_EP_T::CFG: DSQSYNC Mask           */
+
+#define USBD_CFG_CSTALL_Pos              (9)                                               /*!< USBD_EP_T::CFG: CSTALL Position        */
+#define USBD_CFG_CSTALL_Msk              (0x1ul << USBD_CFG_CSTALL_Pos)                    /*!< USBD_EP_T::CFG: CSTALL Mask            */
+
+#define USBD_CFGP_CLRRDY_Pos             (0)                                               /*!< USBD_EP_T::CFGP: CLRRDY Position       */
+#define USBD_CFGP_CLRRDY_Msk             (0x1ul << USBD_CFGP_CLRRDY_Pos)                   /*!< USBD_EP_T::CFGP: CLRRDY Mask           */
+
+#define USBD_CFGP_SSTALL_Pos             (1)                                               /*!< USBD_EP_T::CFGP: SSTALL Position       */
+#define USBD_CFGP_SSTALL_Msk             (0x1ul << USBD_CFGP_SSTALL_Pos)                   /*!< USBD_EP_T::CFGP: SSTALL Mask           */
+
+/**@}*/ /* USBD_CONST */
+/**@}*/ /* end of USBD register group */
+
+/*---------------------- High Speed USB 2.0 Device Controller -------------------------*/
+/**
+    @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD)
+    Memory Mapped Structure for HSUSBD Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var HSUSBD_EP_T::EPDAT
+     * Offset: 0x00  Endpoint n Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |EPDAT     |Endpoint A~L Data Register
+     * |        |          |Endpoint A~L data buffer for the buffer transaction (read or write).
+     * |        |          |Note: Only word access is supported.
+     * @var HSUSBD_EP_T::EPDAT_BYTE
+     * Offset: 0x00  Endpoint n Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |EPDAT     |Endpoint A~L Data Register
+     * |        |          |Endpoint A~L data buffer for the buffer transaction (read or write).
+     * |        |          |Note: Only byte access is supported.
+     * @var HSUSBD_EP_T::EPINTSTS
+     * Offset: 0x04  Endpoint n Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUFFULLIF |Buffer Full
+     * |        |          |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write)
+     * |        |          |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
+     * |        |          |0 = The endpoint packet buffer is not full.
+     * |        |          |1 = The endpoint packet buffer is full.
+     * |        |          |Note: This bit is read-only.
+     * |[1]     |BUFEMPTYIF|Buffer Empty
+     * |        |          |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
+     * |        |          |0 = The endpoint buffer is not empty.
+     * |        |          |1 = The endpoint buffer is empty.
+     * |        |          |For an OUT endpoint:
+     * |        |          |0 = The currently selected buffer has not a count of 0.
+     * |        |          |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
+     * |        |          |Note: This bit is read-only.
+     * |[2]     |SHORTTXIF |Short Packet Transferred Interrupt
+     * |        |          |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
+     * |        |          |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[3]     |TXPKIF    |Data Packet Transmitted Interrupt
+     * |        |          |0 = Not a data packet is transmitted from the endpoint to the host.
+     * |        |          |1 = A data packet is transmitted from the endpoint to the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |RXPKIF    |Data Packet Received Interrupt
+     * |        |          |0 = No data packet is received from the host by the endpoint.
+     * |        |          |1 = A data packet is received from the host by the endpoint.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |OUTTKIF   |Data OUT Token Interrupt
+     * |        |          |0 = A Data OUT token has not been received from the host.
+     * |        |          |1 = A Data OUT token has been received from the host
+     * |        |          |This bit also set by PING token (in high-speed only).
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[6]     |INTKIF    |Data IN Token Interrupt
+     * |        |          |0 = Not Data IN token has been received from the host.
+     * |        |          |1 = A Data IN token has been received from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[7]     |PINGIF    |PING Token Interrupt
+     * |        |          |0 = A Data PING token has not been received from the host.
+     * |        |          |1 = A Data PING token has been received from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[8]     |NAKIF     |USB NAK Sent
+     * |        |          |0 = The last USB IN packet could be provided, and was acknowledged with an ACK.
+     * |        |          |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |STALLIF   |USB STALL Sent
+     * |        |          |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+     * |        |          |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[10]    |NYETIF    |NYET Sent
+     * |        |          |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
+     * |        |          |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[11]    |ERRIF     |ERR Sent
+     * |        |          |0 = No any error in the transaction.
+     * |        |          |1 = There occurs any error in the transaction.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |SHORTRXIF |Bulk Out Short Packet Received
+     * |        |          |0 = No bulk out short packet is received.
+     * |        |          |1 = Received bulk out short packet (including zero length packet).
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * @var HSUSBD_EP_T::EPINTEN
+     * Offset: 0x08  Endpoint n Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUFFULLIEN|Buffer Full Interrupt
+     * |        |          |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
+     * |        |          |0 = Buffer full interrupt Disabled.
+     * |        |          |1 = Buffer full interrupt Enabled.
+     * |[1]     |BUFEMPTYIEN|Buffer Empty Interrupt
+     * |        |          |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
+     * |        |          |0 = Buffer empty interrupt Disabled.
+     * |        |          |1 = Buffer empty interrupt Enabled.
+     * |[2]     |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
+     * |        |          |0 = Short data packet interrupt Disabled.
+     * |        |          |1 = Short data packet interrupt Enabled.
+     * |[3]     |TXPKIEN   |Data Packet Transmitted Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
+     * |        |          |0 = Data packet has been received from the host interrupt Disabled.
+     * |        |          |1 = Data packet has been received from the host interrupt Enabled.
+     * |[4]     |RXPKIEN   |Data Packet Received Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
+     * |        |          |0 = Data packet has been transmitted to the host interrupt Disabled.
+     * |        |          |1 = Data packet has been transmitted to the host interrupt Enabled.
+     * |[5]     |OUTTKIEN  |Data OUT Token Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
+     * |        |          |0 = Data OUT token interrupt Disabled.
+     * |        |          |1 = Data OUT token interrupt Enabled.
+     * |[6]     |INTKIEN   |Data IN Token Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
+     * |        |          |0 = Data IN token interrupt Disabled.
+     * |        |          |1 = Data IN token interrupt Enabled.
+     * |[7]     |PINGIEN   |PING Token Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
+     * |        |          |0 = PING token interrupt Disabled.
+     * |        |          |1 = PING token interrupt Enabled.
+     * |[8]     |NAKIEN    |USB NAK Sent Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
+     * |        |          |0 = NAK token interrupt Disabled.
+     * |        |          |1 = NAK token interrupt Enabled.
+     * |[9]     |STALLIEN  |USB STALL Sent Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
+     * |        |          |0 = STALL token interrupt Disabled.
+     * |        |          |1 = STALL token interrupt Enabled.
+     * |[10]    |NYETIEN   |NYET Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
+     * |        |          |0 = NYET condition interrupt Disabled.
+     * |        |          |1 = NYET condition interrupt Enabled.
+     * |[11]    |ERRIEN    |ERR Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
+     * |        |          |0 = Error event interrupt Disabled.
+     * |        |          |1 = Error event interrupt Enabled.
+     * |[12]    |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
+     * |        |          |0 = Bulk out interrupt Disabled.
+     * |        |          |1 = Bulk out interrupt Enabled.
+     * @var HSUSBD_EP_T::EPDATCNT
+     * Offset: 0x0C  Endpoint n Data Available Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DATCNT    |Data Count
+     * |        |          |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.
+     * |        |          |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
+     * |[30:16] |DMALOOP   |DMA Loop
+     * |        |          |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
+     * @var HSUSBD_EP_T::EPRSPCTL
+     * Offset: 0x10  Endpoint n Response Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FLUSH     |Buffer Flush
+     * |        |          |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared
+     * |        |          |This bit is self-clearing
+     * |        |          |This bit should always be written after an configuration event.
+     * |        |          |0 = The packet buffer is not flushed.
+     * |        |          |1 = The packet buffer is flushed by user.
+     * |[2:1]   |MODE      |Mode Control
+     * |        |          |The two bits decide the operation mode of the in-endpoint.
+     * |        |          |00: Auto-Validate Mode
+     * |        |          |01: Manual-Validate Mode
+     * |        |          |10: Fly Mode
+     * |        |          |11: Reserved
+     * |        |          |These bits are not valid for an out-endpoint
+     * |        |          |The auto validate mode will be activated when the reserved mode is selected
+     * |[3]     |TOGGLE    |Endpoint Toggle
+     * |        |          |This bit is used to clear the endpoint data toggle bit
+     * |        |          |Reading this bit returns the current state of the endpoint data toggle bit.
+     * |        |          |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host
+     * |        |          |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
+     * |        |          |0 = Not clear the endpoint data toggle bit.
+     * |        |          |1 = Clear the endpoint data toggle bit.
+     * |[4]     |HALT      |Endpoint Halt
+     * |        |          |This bit is used to send a STALL handshake as response to the token from the host
+     * |        |          |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.
+     * |        |          |0 = Not send a STALL handshake as response to the token from the host.
+     * |        |          |1 = Send a STALL handshake as response to the token from the host.
+     * |[5]     |ZEROLEN   |Zero Length
+     * |        |          |This bit is used to send a zero-length packet response to an IN-token
+     * |        |          |When this bit is set, a zero packet is sent to the host on reception of an IN-token
+     * |        |          |This bit gets cleared once the zero length data packet is sent.
+     * |        |          |0 = A zero packet is not sent to the host on reception of an IN-token.
+     * |        |          |1 = A zero packet is sent to the host on reception of an IN-token.
+     * |[6]     |SHORTTXEN |Short Packet Transfer Enable
+     * |        |          |This bit is applicable only in case of Auto-Validate Method
+     * |        |          |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer
+     * |        |          |This bit gets cleared once the data packet is sent.
+     * |        |          |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+     * |        |          |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+     * |[7]     |DISBUF    |Buffer Disable Bit
+     * |        |          |This bit is used to receive unknown size OUT short packet
+     * |        |          |The received packet size is reference USBD_EPxDATCNT register.
+     * |        |          |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
+     * |        |          |1 = Buffer Disabled when Bulk-OUT short packet is received.
+     * @var HSUSBD_EP_T::EPMPS
+     * Offset: 0x14  Endpoint n Maximum Packet Size Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |EPMPS     |Endpoint Maximum Packet Size
+     * |        |          |This field determines the Maximum Packet Size of the Endpoint.
+     * @var HSUSBD_EP_T::EPTXCNT
+     * Offset: 0x18  Endpoint n Transfer Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |TXCNT     |Endpoint Transfer Count
+     * |        |          |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
+     * |        |          |For OUT endpoints, this field has no effect.
+     * @var HSUSBD_EP_T::EPCFG
+     * Offset: 0x1C  Endpoint n Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EPEN      |Endpoint Valid
+     * |        |          |When set, this bit enables this endpoint
+     * |        |          |This bit has no effect on Endpoint 0, which is always enabled.
+     * |        |          |0 = The endpoint Disabled.
+     * |        |          |1 = The endpoint Enabled.
+     * |[2:1]   |EPTYPE    |Endpoint Type
+     * |        |          |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
+     * |        |          |00 = Reserved.
+     * |        |          |01 = Bulk.
+     * |        |          |10 = Interrupt.
+     * |        |          |11 = Isochronous.
+     * |[3]     |EPDIR     |Endpoint Direction
+     * |        |          |0 = out-endpoint (Host OUT to Device).
+     * |        |          |1 = in-endpoint (Host IN to Device).
+     * |        |          |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
+     * |[7:4]   |EPNUM     |Endpoint Number
+     * |        |          |This field selects the number of the endpoint. Valid numbers 1 to 15.
+     * |        |          |Note: Do not support two endpoints have same endpoint number.
+     * @var HSUSBD_EP_T::EPBUFST
+     * Offset: 0x20  Endpoint n RAM Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |SADDR     |Endpoint Start Address
+     * |        |          |This is the start-address of the RAM space allocated for the endpoint A~L.
+     * @var HSUSBD_EP_T::EPBUFEND
+     * Offset: 0x24  Endpoint n RAM End Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |EADDR     |Endpoint End Address
+     * |        |          |This is the end-address of the RAM space allocated for the endpoint A~L.
+     */
+
+    union {
+        __IO uint32_t EPDAT;
+        __IO uint8_t  EPDAT_BYTE;
+
+    };                                  /*!< [0x0000] Endpoint n Data Register                                         */
+
+    __IO uint32_t EPINTSTS;             /*!< [0x0004] Endpoint n Interrupt Status Register                             */
+    __IO uint32_t EPINTEN;              /*!< [0x0008] Endpoint n Interrupt Enable Register                             */
+    __I  uint32_t EPDATCNT;             /*!< [0x000c] Endpoint n Data Available Count Register                         */
+    __IO uint32_t EPRSPCTL;             /*!< [0x0010] Endpoint n Response Control Register                             */
+    __IO uint32_t EPMPS;                /*!< [0x0014] Endpoint n Maximum Packet Size Register                          */
+    __IO uint32_t EPTXCNT;              /*!< [0x0018] Endpoint n Transfer Count Register                               */
+    __IO uint32_t EPCFG;                /*!< [0x001c] Endpoint n Configuration Register                                */
+    __IO uint32_t EPBUFST;              /*!< [0x0020] Endpoint n RAM Start Address Register                            */
+    __IO uint32_t EPBUFEND;             /*!< [0x0024] Endpoint n RAM End Address Register                              */
+
+} HSUSBD_EP_T;
+
+typedef struct {
+
+    /**
+     * @var HSUSBD_T::GINTSTS
+     * Offset: 0x00  Global Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBIF     |USB Interrupt
+     * |        |          |This bit conveys the interrupt status for USB specific events endpoint
+     * |        |          |When set, USB interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[1]     |CEPIF     |Control Endpoint Interrupt
+     * |        |          |This bit conveys the interrupt status for control endpoint
+     * |        |          |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[2]     |EPAIF     |Endpoint a Interrupt
+     * |        |          |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[3]     |EPBIF     |Endpoint B Interrupt
+     * |        |          |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[4]     |EPCIF     |Endpoint C Interrupt
+     * |        |          |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[5]     |EPDIF     |Endpoint D Interrupt
+     * |        |          |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[6]     |EPEIF     |Endpoint E Interrupt
+     * |        |          |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[7]     |EPFIF     |Endpoint F Interrupt
+     * |        |          |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[8]     |EPGIF     |Endpoint G Interrupt
+     * |        |          |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[9]     |EPHIF     |Endpoint H Interrupt
+     * |        |          |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[10]    |EPIIF     |Endpoint I Interrupt
+     * |        |          |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[11]    |EPJIF     |Endpoint J Interrupt
+     * |        |          |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[12]    |EPKIF     |Endpoint K Interrupt
+     * |        |          |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * |[13]    |EPLIF     |Endpoint L Interrupt
+     * |        |          |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
+     * |        |          |0 = No interrupt event occurred.
+     * |        |          |1 = The related interrupt event is occurred.
+     * @var HSUSBD_T::GINTEN
+     * Offset: 0x08  Global Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBIEN    |USB Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[1]     |CEPIEN    |Control Endpoint Interrupt Enable Bit
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[2]     |EPAIEN    |Interrupt Enable Control for Endpoint a
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[3]     |EPBIEN    |Interrupt Enable Control for Endpoint B
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[4]     |EPCIEN    |Interrupt Enable Control for Endpoint C
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[5]     |EPDIEN    |Interrupt Enable Control for Endpoint D
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[6]     |EPEIEN    |Interrupt Enable Control for Endpoint E
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[7]     |EPFIEN    |Interrupt Enable Control for Endpoint F
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[8]     |EPGIEN    |Interrupt Enable Control for Endpoint G
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[9]     |EPHIEN    |Interrupt Enable Control for Endpoint H
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[10]    |EPIIEN    |Interrupt Enable Control for Endpoint I
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[11]    |EPJIEN    |Interrupt Enable Control for Endpoint J
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[12]    |EPKIEN    |Interrupt Enable Control for Endpoint K
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * |[13]    |EPLIEN    |Interrupt Enable Control for Endpoint L
+     * |        |          |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
+     * |        |          |0 = The related interrupt Disabled.
+     * |        |          |1 = The related interrupt Enabled.
+     * @var HSUSBD_T::BUSINTSTS
+     * Offset: 0x10  USB Bus Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SOFIF     |SOF Receive Control
+     * |        |          |This bit indicates when a start-of-frame packet has been received.
+     * |        |          |0 = No start-of-frame packet has been received.
+     * |        |          |1 = Start-of-frame packet has been received.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |RSTIF     |Reset Status
+     * |        |          |When set, this bit indicates that either the USB root port reset is end.
+     * |        |          |0 = No USB root port reset is end.
+     * |        |          |1 = USB root port reset is end.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[2]     |RESUMEIF  |Resume
+     * |        |          |When set, this bit indicates that a device resume has occurred.
+     * |        |          |0 = No device resume has occurred.
+     * |        |          |1 = Device resume has occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[3]     |SUSPENDIF |Suspend Request
+     * |        |          |This bit is set as default and it has to be cleared by writing '1' before the USB reset
+     * |        |          |This bit is also set when a USB Suspend request is detected from the host.
+     * |        |          |0 = No USB Suspend request is detected from the host.
+     * |        |          |1= USB Suspend request is detected from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |HISPDIF   |High-speed Settle
+     * |        |          |0 = No valid high-speed reset protocol is detected.
+     * |        |          |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |DMADONEIF |DMA Completion Interrupt
+     * |        |          |0 = No DMA transfer over.
+     * |        |          |1 = DMA transfer is over.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[6]     |PHYCLKVLDIF|Usable Clock Interrupt
+     * |        |          |0 = Usable clock is not available.
+     * |        |          |1 = Usable clock is available from the transceiver.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[8]     |VBUSDETIF |VBUS Detection Interrupt Status
+     * |        |          |0 = No VBUS is plug-in.
+     * |        |          |1 = VBUS is plug-in.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * @var HSUSBD_T::BUSINTEN
+     * Offset: 0x14  USB Bus Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SOFIEN    |SOF Interrupt
+     * |        |          |This bit enables the SOF interrupt.
+     * |        |          |0 = SOF interrupt Disabled.
+     * |        |          |1 = SOF interrupt Enabled.
+     * |[1]     |RSTIEN    |Reset Status
+     * |        |          |This bit enables the USB-Reset interrupt.
+     * |        |          |0 = USB-Reset interrupt Disabled.
+     * |        |          |1 = USB-Reset interrupt Enabled.
+     * |[2]     |RESUMEIEN |Resume
+     * |        |          |This bit enables the Resume interrupt.
+     * |        |          |0 = Resume interrupt Disabled.
+     * |        |          |1 = Resume interrupt Enabled.
+     * |[3]     |SUSPENDIEN|Suspend Request
+     * |        |          |This bit enables the Suspend interrupt.
+     * |        |          |0 = Suspend interrupt Disabled.
+     * |        |          |1 = Suspend interrupt Enabled.
+     * |[4]     |HISPDIEN  |High-speed Settle
+     * |        |          |This bit enables the high-speed settle interrupt.
+     * |        |          |0 = High-speed settle interrupt Disabled.
+     * |        |          |1 = High-speed settle interrupt Enabled.
+     * |[5]     |DMADONEIEN|DMA Completion Interrupt
+     * |        |          |This bit enables the DMA completion interrupt
+     * |        |          |0 = DMA completion interrupt Disabled.
+     * |        |          |1 = DMA completion interrupt Enabled.
+     * |[6]     |PHYCLKVLDIEN|Usable Clock Interrupt
+     * |        |          |This bit enables the usable clock interrupt.
+     * |        |          |0 = Usable clock interrupt Disabled.
+     * |        |          |1 = Usable clock interrupt Enabled.
+     * |[8]     |VBUSDETIEN|VBUS Detection Interrupt Enable Bit
+     * |        |          |This bit enables the VBUS floating detection interrupt.
+     * |        |          |0 = VBUS floating detection interrupt Disabled.
+     * |        |          |1 = VBUS floating detection interrupt Enabled.
+     * @var HSUSBD_T::OPER
+     * Offset: 0x18  USB Operational Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RESUMEEN  |Generate Resume
+     * |        |          |0 = No Resume sequence to be initiated to the host.
+     * |        |          |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled
+     * |        |          |This bit is self-clearing.
+     * |[1]     |HISPDEN   |USB High-speed
+     * |        |          |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
+     * |        |          |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
+     * |[2]     |CURSPD    |USB Current Speed
+     * |        |          |0 = The device has settled in Full Speed.
+     * |        |          |1 = The USB device controller has settled in High-speed.
+     * @var HSUSBD_T::FRAMECNT
+     * Offset: 0x1C  USB Frame Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |MFRAMECNT |Micro-frame Counter
+     * |        |          |This field contains the micro-frame number for the frame number in the frame counter field.
+     * |[13:3]  |FRAMECNT  |Frame Counter
+     * |        |          |This field contains the frame count from the most recent start-of-frame packet.
+     * @var HSUSBD_T::FADDR
+     * Offset: 0x20  USB Function Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |FADDR     |USB Function Address
+     * |        |          |This field contains the current USB address of the device
+     * |        |          |This field is cleared when a root port reset is detected
+     * @var HSUSBD_T::TEST
+     * Offset: 0x24  USB Test Mode Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TESTMODE  |Test Mode Selection
+     * |        |          |000 = Normal Operation.
+     * |        |          |001 = Test_J.
+     * |        |          |010 = Test_K.
+     * |        |          |011 = Test_SE0_NAK.
+     * |        |          |100 = Test_Packet.
+     * |        |          |101 = Test_Force_Enable.
+     * |        |          |110 = Reserved.
+     * |        |          |111 = Reserved.
+     * |        |          |Note: This field is cleared when root port reset is detected.
+     * @var HSUSBD_T::CEPDAT
+     * Offset: 0x28  Control-Endpoint Data Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DAT       |Control-endpoint Data Buffer
+     * |        |          |Control endpoint data buffer for the buffer transaction (read or write).
+     * |        |          |Note: Only word access is supported.
+     * @var HSUSBD_T::CEPDAT_BYTE
+     * Offset: 0x28  Control-Endpoint Data Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |Control-endpoint Data Buffer
+     * |        |          |Control endpoint data buffer for the buffer transaction (read or write).
+     * |        |          |Note: Only byte access is supported.
+     * @var HSUSBD_T::CEPCTL
+     * Offset: 0x2C  Control-Endpoint Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |NAKCLR    |No Acknowledge Control
+     * |        |          |This bit plays a crucial role in any control transfer.
+     * |        |          |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase
+     * |        |          |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
+     * |        |          |1 = This bit is set to one by the USB device controller, whenever a setup token is received
+     * |        |          |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
+     * |        |          |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+     * |[1]     |STALLEN   |Stall Enable Bit
+     * |        |          |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter
+     * |        |          |This is typically used for response to invalid/unsupported requests
+     * |        |          |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL
+     * |        |          |It is automatically cleared on receipt of a next setup-token
+     * |        |          |So, the local CPU need not write again to clear this bit.
+     * |        |          |0 = No sends a stall handshake in response to any in or out token thereafter.
+     * |        |          |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
+     * |        |          |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+     * |[2]     |ZEROLEN   |Zero Packet Length
+     * |        |          |This bit is valid for Auto Validation mode only.
+     * |        |          |0 = No zero length packet to the host during Data stage to an IN token.
+     * |        |          |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token
+     * |        |          |This bit gets cleared once the zero length data packet is sent
+     * |        |          |So, the local CPU need not write again to clear this bit.
+     * |[3]     |FLUSH     |CEP-flush Bit
+     * |        |          |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
+     * |        |          |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
+     * |        |          |This bit is self-cleaning.
+     * @var HSUSBD_T::CEPINTEN
+     * Offset: 0x30  Control-Endpoint Interrupt Enable
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SETUPTKIEN|Setup Token Interrupt Enable Bit
+     * |        |          |0 = The SETUP token interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The SETUP token interrupt in Control Endpoint Enabled.
+     * |[1]     |SETUPPKIEN|Setup Packet Interrupt
+     * |        |          |0 = The SETUP packet interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The SETUP packet interrupt in Control Endpoint Enabled.
+     * |[2]     |OUTTKIEN  |Out Token Interrupt
+     * |        |          |0 = The OUT token interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The OUT token interrupt in Control Endpoint Enabled.
+     * |[3]     |INTKIEN   |In Token Interrupt
+     * |        |          |0 = The IN token interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The IN token interrupt in Control Endpoint Enabled.
+     * |[4]     |PINGIEN   |Ping Token Interrupt
+     * |        |          |0 = The ping token interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The ping token interrupt Control Endpoint Enabled.
+     * |[5]     |TXPKIEN   |Data Packet Transmitted Interrupt
+     * |        |          |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
+     * |[6]     |RXPKIEN   |Data Packet Received Interrupt
+     * |        |          |0 = The data received interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The data received interrupt in Control Endpoint Enabled.
+     * |[7]     |NAKIEN    |NAK Sent Interrupt
+     * |        |          |0 = The NAK sent interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The NAK sent interrupt in Control Endpoint Enabled.
+     * |[8]     |STALLIEN  |STALL Sent Interrupt
+     * |        |          |0 = The STALL sent interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The STALL sent interrupt in Control Endpoint Enabled.
+     * |[9]     |ERRIEN    |USB Error Interrupt
+     * |        |          |0 = The USB Error interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The USB Error interrupt in Control Endpoint Enabled.
+     * |[10]    |STSDONEIEN|Status Completion Interrupt
+     * |        |          |0 = The Status Completion interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The Status Completion interrupt in Control Endpoint Enabled.
+     * |[11]    |BUFFULLIEN|Buffer Full Interrupt
+     * |        |          |0 = The buffer full interrupt in Control Endpoint Disabled.
+     * |        |          |1 = The buffer full interrupt in Control Endpoint Enabled.
+     * |[12]    |BUFEMPTYIEN|Buffer Empty Interrupt
+     * |        |          |0 = The buffer empty interrupt in Control Endpoint Disabled.
+     * |        |          |1= The buffer empty interrupt in Control Endpoint Enabled.
+     * @var HSUSBD_T::CEPINTSTS
+     * Offset: 0x34  Control-Endpoint Interrupt Status
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SETUPTKIF |Setup Token Interrupt
+     * |        |          |0 = Not a Setup token is received.
+     * |        |          |1 = A Setup token is received. Writing 1 clears this status bit
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |SETUPPKIF |Setup Packet Interrupt
+     * |        |          |This bit must be cleared (by writing 1) before the next setup packet can be received
+     * |        |          |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
+     * |        |          |0 = Not a Setup packet has been received from the host.
+     * |        |          |1 = A Setup packet has been received from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[2]     |OUTTKIF   |Out Token Interrupt
+     * |        |          |0 = The control-endpoint does not received an OUT token from the host.
+     * |        |          |1 = The control-endpoint receives an OUT token from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[3]     |INTKIF    |in Token Interrupt
+     * |        |          |0 = The control-endpoint does not received an IN token from the host.
+     * |        |          |1 = The control-endpoint receives an IN token from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |PINGIF    |Ping Token Interrupt
+     * |        |          |0 = The control-endpoint does not received a ping token from the host.
+     * |        |          |1 = The control-endpoint receives a ping token from the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |TXPKIF    |Data Packet Transmitted Interrupt
+     * |        |          |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+     * |        |          |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[6]     |RXPKIF    |Data Packet Received Interrupt
+     * |        |          |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+     * |        |          |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[7]     |NAKIF     |NAK Sent Interrupt
+     * |        |          |0 = Not a NAK-token is sent in response to an IN/OUT token.
+     * |        |          |1 = A NAK-token is sent in response to an IN/OUT token.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[8]     |STALLIF   |STALL Sent Interrupt
+     * |        |          |0 = Not a stall-token is sent in response to an IN/OUT token.
+     * |        |          |1 = A stall-token is sent in response to an IN/OUT token.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |ERRIF     |USB Error Interrupt
+     * |        |          |0 = No error had occurred during the transaction.
+     * |        |          |1 = An error had occurred during the transaction.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[10]    |STSDONEIF |Status Completion Interrupt
+     * |        |          |0 = Not a USB transaction has completed successfully.
+     * |        |          |1 = The status stage of a USB transaction has completed successfully.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[11]    |BUFFULLIF |Buffer Full Interrupt
+     * |        |          |0 = The control-endpoint buffer is not full.
+     * |        |          |1 = The control-endpoint buffer is full.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |BUFEMPTYIF|Buffer Empty Interrupt
+     * |        |          |0 = The control-endpoint buffer is not empty.
+     * |        |          |1 = The control-endpoint buffer is empty.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * @var HSUSBD_T::CEPTXCNT
+     * Offset: 0x38  Control-Endpoint In-transfer Data Count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TXCNT     |In-transfer Data Count
+     * |        |          |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register
+     * |        |          |When zero is written into this field, a zero length packet is sent to the host
+     * |        |          |When the count written in the register is more than the MPS, the data sent will be of only MPS.
+     * @var HSUSBD_T::CEPRXCNT
+     * Offset: 0x3C  Control-Endpoint Out-transfer Data Count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |RXCNT     |Out-transfer Data Count
+     * |        |          |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
+     * @var HSUSBD_T::CEPDATCNT
+     * Offset: 0x40  Control-Endpoint data count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DATCNT    |Control-endpoint Data Count
+     * |        |          |The USB device controller maintains the count of the data of control-endpoint.
+     * @var HSUSBD_T::SETUP1_0
+     * Offset: 0x44  Setup1 & Setup0 bytes
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SETUP0    |Setup Byte 0[7:0]
+     * |        |          |This register provides byte 0 of the last setup packet received
+     * |        |          |For a Standard Device Request, the following bmRequestType information is returned.
+     * |        |          |Bit 7(Direction):
+     * |        |          | 0: Host to device
+     * |        |          | 1: Device to host
+     * |        |          |Bit 6-5 (Type):
+     * |        |          | 00: Standard
+     * |        |          | 01: Class
+     * |        |          | 10: Vendor
+     * |        |          | 11: Reserved
+     * |        |          |Bit 4-0 (Recipient)
+     * |        |          | 00000: Device
+     * |        |          | 00001: Interface
+     * |        |          | 00010: Endpoint
+     * |        |          | 00011: Other
+     * |        |          | Others: Reserved
+     * |[15:8]  |SETUP1    |Setup Byte 1[15:8]
+     * |        |          |This register provides byte 1 of the last setup packet received
+     * |        |          |For a Standard Device Request, the following bRequest Code information is returned.
+     * |        |          |00000000 = Get Status.
+     * |        |          |00000001 = Clear Feature.
+     * |        |          |00000010 = Reserved.
+     * |        |          |00000011 = Set Feature.
+     * |        |          |00000100 = Reserved.
+     * |        |          |00000101 = Set Address.
+     * |        |          |00000110 = Get Descriptor.
+     * |        |          |00000111 = Set Descriptor.
+     * |        |          |00001000 = Get Configuration.
+     * |        |          |00001001 = Set Configuration.
+     * |        |          |00001010 = Get Interface.
+     * |        |          |00001011 = Set Interface.
+     * |        |          |00001100 = Sync Frame.
+     * @var HSUSBD_T::SETUP3_2
+     * Offset: 0x48  Setup3 & Setup2 Bytes
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SETUP2    |Setup Byte 2 [7:0]
+     * |        |          |This register provides byte 2 of the last setup packet received
+     * |        |          |For a Standard Device Request, the least significant byte of the wValue field is returned
+     * |[15:8]  |SETUP3    |Setup Byte 3 [15:8]
+     * |        |          |This register provides byte 3 of the last setup packet received
+     * |        |          |For a Standard Device Request, the most significant byte of the wValue field is returned.
+     * @var HSUSBD_T::SETUP5_4
+     * Offset: 0x4C  Setup5 & Setup4 Bytes
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SETUP4    |Setup Byte 4[7:0]
+     * |        |          |This register provides byte 4 of the last setup packet received
+     * |        |          |For a Standard Device Request, the least significant byte of the wIndex is returned.
+     * |[15:8]  |SETUP5    |Setup Byte 5[15:8]
+     * |        |          |This register provides byte 5 of the last setup packet received
+     * |        |          |For a Standard Device Request, the most significant byte of the wIndex field is returned.
+     * @var HSUSBD_T::SETUP7_6
+     * Offset: 0x50  Setup7 & Setup6 Bytes
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SETUP6    |Setup Byte 6[7:0]
+     * |        |          |This register provides byte 6 of the last setup packet received
+     * |        |          |For a Standard Device Request, the least significant byte of the wLength field is returned.
+     * |[15:8]  |SETUP7    |Setup Byte 7[15:8]
+     * |        |          |This register provides byte 7 of the last setup packet received
+     * |        |          |For a Standard Device Request, the most significant byte of the wLength field is returned.
+     * @var HSUSBD_T::CEPBUFST
+     * Offset: 0x54  Control Endpoint RAM Start Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |SADDR     |Control-endpoint Start Address
+     * |        |          |This is the start-address of the RAM space allocated for the control-endpoint.
+     * @var HSUSBD_T::CEPBUFEND
+     * Offset: 0x58  Control Endpoint RAM End Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |EADDR     |Control-endpoint End Address
+     * |        |          |This is the end-address of the RAM space allocated for the control-endpoint.
+     * @var HSUSBD_T::DMACTL
+     * Offset: 0x5C  DMA Control Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPNUM     |DMA Endpoint Address Bits
+     * |        |          |Used to define the Endpoint Address
+     * |[4]     |DMARD     |DMA Operation
+     * |        |          |0 : The operation is a DMA write (read from USB buffer)
+     * |        |          |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation.
+     * |        |          |1 : The operation is a DMA read (write to USB buffer).
+     * |[5]     |DMAEN     |DMA Enable Bit
+     * |        |          |0 : DMA function Disabled.
+     * |        |          |1 : DMA function Enabled.
+     * |[6]     |SGEN      |Scatter Gather Function Enable Bit
+     * |        |          |0 : Scatter gather function Disabled.
+     * |        |          |1 : Scatter gather function Enabled.
+     * |[7]     |DMARST    |Reset DMA State Machine
+     * |        |          |0 : No reset the DMA state machine.
+     * |        |          |1 : Reset the DMA state machine.
+     * |[8]     |SVINEP    |Serve IN Endpoint
+     * |        |          |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint.
+     * |        |          |0: DMA serves OUT endpoint
+     * |        |          |1: DMA serves IN endpoint
+     * @var HSUSBD_T::DMACNT
+     * Offset: 0x60  DMA Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[19:0]  |DMACNT    |DMA Transfer Count
+     * |        |          |The transfer count of the DMA operation to be performed is written to this register.
+     * @var HSUSBD_T::DMAADDR
+     * Offset: 0x700  AHB DMA Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DMAADDR   |DMAADDR
+     * |        |          |The register specifies the address from which the DMA has to read / write
+     * |        |          |The address must WORD (32-bit) aligned.
+     * @var HSUSBD_T::PHYCTL
+     * Offset: 0x704  USB PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8]     |DPPUEN    |DP Pull-up
+     * |        |          |0 = Pull-up resistor on D+ Disabled.
+     * |        |          |1 = Pull-up resistor on D+ Enabled.
+     * |[9]     |PHYEN     |PHY Suspend Enable Bit
+     * |        |          |0 = The USB PHY is suspend.
+     * |        |          |1 = The USB PHY is not suspend.
+     * |[24]    |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = The wake-up function Disabled.
+     * |        |          |1 = The wake-up function Enabled.
+     * |[31]    |VBUSDET   |VBUS Status
+     * |        |          |0 = The VBUS is not detected yet.
+     * |        |          |1 = The VBUS is detected.
+     */
+
+    __I  uint32_t GINTSTS;               /*!< [0x0000] Global Interrupt Status Register                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t GINTEN;                /*!< [0x0008] Global Interrupt Enable Register                                 */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t BUSINTSTS;             /*!< [0x0010] USB Bus Interrupt Status Register                                */
+    __IO uint32_t BUSINTEN;              /*!< [0x0014] USB Bus Interrupt Enable Register                                */
+    __IO uint32_t OPER;                  /*!< [0x0018] USB Operational Register                                         */
+    __I  uint32_t FRAMECNT;              /*!< [0x001c] USB Frame Count Register                                         */
+    __IO uint32_t FADDR;                 /*!< [0x0020] USB Function Address Register                                    */
+    __IO uint32_t TEST;                  /*!< [0x0024] USB Test Mode Register                                           */
+
+    union {
+        __IO uint32_t CEPDAT;
+        __IO uint8_t  CEPDAT_BYTE;
+
+    };                                   /*!< [0x0028] Control-Endpoint Data Buffer                                     */
+
+    __IO uint32_t CEPCTL;                /*!< [0x002c] Control-Endpoint Control Register                                */
+    __IO uint32_t CEPINTEN;              /*!< [0x0030] Control-Endpoint Interrupt Enable                                */
+    __IO uint32_t CEPINTSTS;             /*!< [0x0034] Control-Endpoint Interrupt Status                                */
+    __IO uint32_t CEPTXCNT;              /*!< [0x0038] Control-Endpoint In-transfer Data Count                          */
+    __I  uint32_t CEPRXCNT;              /*!< [0x003c] Control-Endpoint Out-transfer Data Count                         */
+    __I  uint32_t CEPDATCNT;             /*!< [0x0040] Control-Endpoint data count                                      */
+    __I  uint32_t SETUP1_0;              /*!< [0x0044] Setup1 & Setup0 bytes                                            */
+    __I  uint32_t SETUP3_2;              /*!< [0x0048] Setup3 & Setup2 Bytes                                            */
+    __I  uint32_t SETUP5_4;              /*!< [0x004c] Setup5 & Setup4 Bytes                                            */
+    __I  uint32_t SETUP7_6;              /*!< [0x0050] Setup7 & Setup6 Bytes                                            */
+    __IO uint32_t CEPBUFST;              /*!< [0x0054] Control Endpoint RAM Start Address Register                      */
+    __IO uint32_t CEPBUFEND;             /*!< [0x0058] Control Endpoint RAM End Address Register                        */
+    __IO uint32_t DMACTL;                /*!< [0x005c] DMA Control Status Register                                      */
+    __IO uint32_t DMACNT;                /*!< [0x0060] DMA Count Register                                               */
+
+    HSUSBD_EP_T EP[12];
+
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[303];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t DMAADDR;               /*!< [0x0700] AHB DMA Address Register                                         */
+    __IO uint32_t PHYCTL;                /*!< [0x0704] USB PHY Control Register                                         */
+
+} HSUSBD_T;
+
+/**
+    @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition
+    Constant Definitions for HSUSBD Controller
+@{ */
+
+#define HSUSBD_GINTSTS_USBIF_Pos         (0)                                               /*!< HSUSBD_T::GINTSTS: USBIF Position      */
+#define HSUSBD_GINTSTS_USBIF_Msk         (0x1ul << HSUSBD_GINTSTS_USBIF_Pos)               /*!< HSUSBD_T::GINTSTS: USBIF Mask          */
+
+#define HSUSBD_GINTSTS_CEPIF_Pos         (1)                                               /*!< HSUSBD_T::GINTSTS: CEPIF Position      */
+#define HSUSBD_GINTSTS_CEPIF_Msk         (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos)               /*!< HSUSBD_T::GINTSTS: CEPIF Mask          */
+
+#define HSUSBD_GINTSTS_EPAIF_Pos         (2)                                               /*!< HSUSBD_T::GINTSTS: EPAIF Position      */
+#define HSUSBD_GINTSTS_EPAIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPAIF Mask          */
+
+#define HSUSBD_GINTSTS_EPBIF_Pos         (3)                                               /*!< HSUSBD_T::GINTSTS: EPBIF Position      */
+#define HSUSBD_GINTSTS_EPBIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPBIF Mask          */
+
+#define HSUSBD_GINTSTS_EPCIF_Pos         (4)                                               /*!< HSUSBD_T::GINTSTS: EPCIF Position      */
+#define HSUSBD_GINTSTS_EPCIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPCIF Mask          */
+
+#define HSUSBD_GINTSTS_EPDIF_Pos         (5)                                               /*!< HSUSBD_T::GINTSTS: EPDIF Position      */
+#define HSUSBD_GINTSTS_EPDIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPDIF Mask          */
+
+#define HSUSBD_GINTSTS_EPEIF_Pos         (6)                                               /*!< HSUSBD_T::GINTSTS: EPEIF Position      */
+#define HSUSBD_GINTSTS_EPEIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPEIF Mask          */
+
+#define HSUSBD_GINTSTS_EPFIF_Pos         (7)                                               /*!< HSUSBD_T::GINTSTS: EPFIF Position      */
+#define HSUSBD_GINTSTS_EPFIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPFIF Mask          */
+
+#define HSUSBD_GINTSTS_EPGIF_Pos         (8)                                               /*!< HSUSBD_T::GINTSTS: EPGIF Position      */
+#define HSUSBD_GINTSTS_EPGIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPGIF Mask          */
+
+#define HSUSBD_GINTSTS_EPHIF_Pos         (9)                                               /*!< HSUSBD_T::GINTSTS: EPHIF Position      */
+#define HSUSBD_GINTSTS_EPHIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPHIF Mask          */
+
+#define HSUSBD_GINTSTS_EPIIF_Pos         (10)                                              /*!< HSUSBD_T::GINTSTS: EPIIF Position      */
+#define HSUSBD_GINTSTS_EPIIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPIIF Mask          */
+
+#define HSUSBD_GINTSTS_EPJIF_Pos         (11)                                              /*!< HSUSBD_T::GINTSTS: EPJIF Position      */
+#define HSUSBD_GINTSTS_EPJIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPJIF Mask          */
+
+#define HSUSBD_GINTSTS_EPKIF_Pos         (12)                                              /*!< HSUSBD_T::GINTSTS: EPKIF Position      */
+#define HSUSBD_GINTSTS_EPKIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPKIF Mask          */
+
+#define HSUSBD_GINTSTS_EPLIF_Pos         (13)                                              /*!< HSUSBD_T::GINTSTS: EPLIF Position      */
+#define HSUSBD_GINTSTS_EPLIF_Msk         (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos)               /*!< HSUSBD_T::GINTSTS: EPLIF Mask          */
+
+#define HSUSBD_GINTEN_USBIEN_Pos         (0)                                               /*!< HSUSBD_T::GINTEN: USBIEN Position      */
+#define HSUSBD_GINTEN_USBIEN_Msk         (0x1ul << HSUSBD_GINTEN_USBIEN_Pos)               /*!< HSUSBD_T::GINTEN: USBIEN Mask          */
+
+#define HSUSBD_GINTEN_CEPIEN_Pos         (1)                                               /*!< HSUSBD_T::GINTEN: CEPIEN Position      */
+#define HSUSBD_GINTEN_CEPIEN_Msk         (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos)               /*!< HSUSBD_T::GINTEN: CEPIEN Mask          */
+
+#define HSUSBD_GINTEN_EPAIEN_Pos         (2)                                               /*!< HSUSBD_T::GINTEN: EPAIEN Position      */
+#define HSUSBD_GINTEN_EPAIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPAIEN Mask          */
+
+#define HSUSBD_GINTEN_EPBIEN_Pos         (3)                                               /*!< HSUSBD_T::GINTEN: EPBIEN Position      */
+#define HSUSBD_GINTEN_EPBIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPBIEN Mask          */
+
+#define HSUSBD_GINTEN_EPCIEN_Pos         (4)                                               /*!< HSUSBD_T::GINTEN: EPCIEN Position      */
+#define HSUSBD_GINTEN_EPCIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPCIEN Mask          */
+
+#define HSUSBD_GINTEN_EPDIEN_Pos         (5)                                               /*!< HSUSBD_T::GINTEN: EPDIEN Position      */
+#define HSUSBD_GINTEN_EPDIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPDIEN Mask          */
+
+#define HSUSBD_GINTEN_EPEIEN_Pos         (6)                                               /*!< HSUSBD_T::GINTEN: EPEIEN Position      */
+#define HSUSBD_GINTEN_EPEIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPEIEN Mask          */
+
+#define HSUSBD_GINTEN_EPFIEN_Pos         (7)                                               /*!< HSUSBD_T::GINTEN: EPFIEN Position      */
+#define HSUSBD_GINTEN_EPFIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPFIEN Mask          */
+
+#define HSUSBD_GINTEN_EPGIEN_Pos         (8)                                               /*!< HSUSBD_T::GINTEN: EPGIEN Position      */
+#define HSUSBD_GINTEN_EPGIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPGIEN Mask          */
+
+#define HSUSBD_GINTEN_EPHIEN_Pos         (9)                                               /*!< HSUSBD_T::GINTEN: EPHIEN Position      */
+#define HSUSBD_GINTEN_EPHIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPHIEN Mask          */
+
+#define HSUSBD_GINTEN_EPIIEN_Pos         (10)                                              /*!< HSUSBD_T::GINTEN: EPIIEN Position      */
+#define HSUSBD_GINTEN_EPIIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPIIEN Mask          */
+
+#define HSUSBD_GINTEN_EPJIEN_Pos         (11)                                              /*!< HSUSBD_T::GINTEN: EPJIEN Position      */
+#define HSUSBD_GINTEN_EPJIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPJIEN Mask          */
+
+#define HSUSBD_GINTEN_EPKIEN_Pos         (12)                                              /*!< HSUSBD_T::GINTEN: EPKIEN Position      */
+#define HSUSBD_GINTEN_EPKIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPKIEN Mask          */
+
+#define HSUSBD_GINTEN_EPLIEN_Pos         (13)                                              /*!< HSUSBD_T::GINTEN: EPLIEN Position      */
+#define HSUSBD_GINTEN_EPLIEN_Msk         (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos)               /*!< HSUSBD_T::GINTEN: EPLIEN Mask          */
+
+#define HSUSBD_BUSINTSTS_SOFIF_Pos       (0)                                               /*!< HSUSBD_T::BUSINTSTS: SOFIF Position    */
+#define HSUSBD_BUSINTSTS_SOFIF_Msk       (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos)             /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask        */
+
+#define HSUSBD_BUSINTSTS_RSTIF_Pos       (1)                                               /*!< HSUSBD_T::BUSINTSTS: RSTIF Position    */
+#define HSUSBD_BUSINTSTS_RSTIF_Msk       (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos)             /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask        */
+
+#define HSUSBD_BUSINTSTS_RESUMEIF_Pos    (2)                                               /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */
+#define HSUSBD_BUSINTSTS_RESUMEIF_Msk    (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos)          /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask     */
+
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos   (3)                                               /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk   (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos)         /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask    */
+
+#define HSUSBD_BUSINTSTS_HISPDIF_Pos     (4)                                               /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position  */
+#define HSUSBD_BUSINTSTS_HISPDIF_Msk     (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos)           /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask      */
+
+#define HSUSBD_BUSINTSTS_DMADONEIF_Pos   (5)                                               /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/
+#define HSUSBD_BUSINTSTS_DMADONEIF_Msk   (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos)         /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask    */
+
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6)                                               /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos)       /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask  */
+
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos   (8)                                               /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk   (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos)         /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask    */
+
+#define HSUSBD_BUSINTEN_SOFIEN_Pos       (0)                                               /*!< HSUSBD_T::BUSINTEN: SOFIEN Position    */
+#define HSUSBD_BUSINTEN_SOFIEN_Msk       (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos)             /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask        */
+
+#define HSUSBD_BUSINTEN_RSTIEN_Pos       (1)                                               /*!< HSUSBD_T::BUSINTEN: RSTIEN Position    */
+#define HSUSBD_BUSINTEN_RSTIEN_Msk       (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos)             /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask        */
+
+#define HSUSBD_BUSINTEN_RESUMEIEN_Pos    (2)                                               /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */
+#define HSUSBD_BUSINTEN_RESUMEIEN_Msk    (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos)          /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask     */
+
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos   (3)                                               /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk   (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos)         /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask    */
+
+#define HSUSBD_BUSINTEN_HISPDIEN_Pos     (4)                                               /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position  */
+#define HSUSBD_BUSINTEN_HISPDIEN_Msk     (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos)           /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask      */
+
+#define HSUSBD_BUSINTEN_DMADONEIEN_Pos   (5)                                               /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/
+#define HSUSBD_BUSINTEN_DMADONEIEN_Msk   (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos)         /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask    */
+
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6)                                               /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos)       /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask  */
+
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos   (8)                                               /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk   (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos)         /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask    */
+
+#define HSUSBD_OPER_RESUMEEN_Pos         (0)                                               /*!< HSUSBD_T::OPER: RESUMEEN Position      */
+#define HSUSBD_OPER_RESUMEEN_Msk         (0x1ul << HSUSBD_OPER_RESUMEEN_Pos)               /*!< HSUSBD_T::OPER: RESUMEEN Mask          */
+
+#define HSUSBD_OPER_HISPDEN_Pos          (1)                                               /*!< HSUSBD_T::OPER: HISPDEN Position       */
+#define HSUSBD_OPER_HISPDEN_Msk          (0x1ul << HSUSBD_OPER_HISPDEN_Pos)                /*!< HSUSBD_T::OPER: HISPDEN Mask           */
+
+#define HSUSBD_OPER_CURSPD_Pos           (2)                                               /*!< HSUSBD_T::OPER: CURSPD Position        */
+#define HSUSBD_OPER_CURSPD_Msk           (0x1ul << HSUSBD_OPER_CURSPD_Pos)                 /*!< HSUSBD_T::OPER: CURSPD Mask            */
+
+#define HSUSBD_FRAMECNT_MFRAMECNT_Pos    (0)                                               /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */
+#define HSUSBD_FRAMECNT_MFRAMECNT_Msk    (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos)          /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask     */
+
+#define HSUSBD_FRAMECNT_FRAMECNT_Pos     (3)                                               /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position  */
+#define HSUSBD_FRAMECNT_FRAMECNT_Msk     (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos)         /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask      */
+
+#define HSUSBD_FADDR_FADDR_Pos           (0)                                               /*!< HSUSBD_T::FADDR: FADDR Position        */
+#define HSUSBD_FADDR_FADDR_Msk           (0x7ful << HSUSBD_FADDR_FADDR_Pos)                /*!< HSUSBD_T::FADDR: FADDR Mask            */
+
+#define HSUSBD_TEST_TESTMODE_Pos         (0)                                               /*!< HSUSBD_T::TEST: TESTMODE Position      */
+#define HSUSBD_TEST_TESTMODE_Msk         (0x7ul << HSUSBD_TEST_TESTMODE_Pos)               /*!< HSUSBD_T::TEST: TESTMODE Mask          */
+
+#define HSUSBD_CEPDAT_DAT_Pos            (0)                                               /*!< HSUSBD_T::CEPDAT: DAT Position         */
+#define HSUSBD_CEPDAT_DAT_Msk            (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos)           /*!< HSUSBD_T::CEPDAT: DAT Mask             */
+
+#define HSUSBD_CEPCTL_NAKCLR_Pos         (0)                                               /*!< HSUSBD_T::CEPCTL: NAKCLR Position      */
+#define HSUSBD_CEPCTL_NAKCLR_Msk         (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos)               /*!< HSUSBD_T::CEPCTL: NAKCLR Mask          */
+
+#define HSUSBD_CEPCTL_STALLEN_Pos        (1)                                               /*!< HSUSBD_T::CEPCTL: STALLEN Position     */
+#define HSUSBD_CEPCTL_STALLEN_Msk        (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos)              /*!< HSUSBD_T::CEPCTL: STALLEN Mask         */
+
+#define HSUSBD_CEPCTL_ZEROLEN_Pos        (2)                                               /*!< HSUSBD_T::CEPCTL: ZEROLEN Position     */
+#define HSUSBD_CEPCTL_ZEROLEN_Msk        (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos)              /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask         */
+
+#define HSUSBD_CEPCTL_FLUSH_Pos          (3)                                               /*!< HSUSBD_T::CEPCTL: FLUSH Position       */
+#define HSUSBD_CEPCTL_FLUSH_Msk          (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos)                /*!< HSUSBD_T::CEPCTL: FLUSH Mask           */
+
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos   (0)                                               /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk   (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos)         /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask    */
+
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos   (1)                                               /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk   (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos)         /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask    */
+
+#define HSUSBD_CEPINTEN_OUTTKIEN_Pos     (2)                                               /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position  */
+#define HSUSBD_CEPINTEN_OUTTKIEN_Msk     (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos)           /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask      */
+
+#define HSUSBD_CEPINTEN_INTKIEN_Pos      (3)                                               /*!< HSUSBD_T::CEPINTEN: INTKIEN Position   */
+#define HSUSBD_CEPINTEN_INTKIEN_Msk      (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos)            /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask       */
+
+#define HSUSBD_CEPINTEN_PINGIEN_Pos      (4)                                               /*!< HSUSBD_T::CEPINTEN: PINGIEN Position   */
+#define HSUSBD_CEPINTEN_PINGIEN_Msk      (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos)            /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask       */
+
+#define HSUSBD_CEPINTEN_TXPKIEN_Pos      (5)                                               /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position   */
+#define HSUSBD_CEPINTEN_TXPKIEN_Msk      (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos)            /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask       */
+
+#define HSUSBD_CEPINTEN_RXPKIEN_Pos      (6)                                               /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position   */
+#define HSUSBD_CEPINTEN_RXPKIEN_Msk      (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos)            /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask       */
+
+#define HSUSBD_CEPINTEN_NAKIEN_Pos       (7)                                               /*!< HSUSBD_T::CEPINTEN: NAKIEN Position    */
+#define HSUSBD_CEPINTEN_NAKIEN_Msk       (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos)             /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask        */
+
+#define HSUSBD_CEPINTEN_STALLIEN_Pos     (8)                                               /*!< HSUSBD_T::CEPINTEN: STALLIEN Position  */
+#define HSUSBD_CEPINTEN_STALLIEN_Msk     (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos)           /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask      */
+
+#define HSUSBD_CEPINTEN_ERRIEN_Pos       (9)                                               /*!< HSUSBD_T::CEPINTEN: ERRIEN Position    */
+#define HSUSBD_CEPINTEN_ERRIEN_Msk       (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos)             /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask        */
+
+#define HSUSBD_CEPINTEN_STSDONEIEN_Pos   (10)                                              /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/
+#define HSUSBD_CEPINTEN_STSDONEIEN_Msk   (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos)         /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask    */
+
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos   (11)                                              /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk   (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos)         /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask    */
+
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos  (12)                                              /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk  (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos)        /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask   */
+
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos   (0)                                               /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk   (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos)         /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask    */
+
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos   (1)                                               /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk   (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos)         /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask    */
+
+#define HSUSBD_CEPINTSTS_OUTTKIF_Pos     (2)                                               /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position  */
+#define HSUSBD_CEPINTSTS_OUTTKIF_Msk     (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos)           /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask      */
+
+#define HSUSBD_CEPINTSTS_INTKIF_Pos      (3)                                               /*!< HSUSBD_T::CEPINTSTS: INTKIF Position   */
+#define HSUSBD_CEPINTSTS_INTKIF_Msk      (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos)            /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask       */
+
+#define HSUSBD_CEPINTSTS_PINGIF_Pos      (4)                                               /*!< HSUSBD_T::CEPINTSTS: PINGIF Position   */
+#define HSUSBD_CEPINTSTS_PINGIF_Msk      (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos)            /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask       */
+
+#define HSUSBD_CEPINTSTS_TXPKIF_Pos      (5)                                               /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position   */
+#define HSUSBD_CEPINTSTS_TXPKIF_Msk      (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos)            /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask       */
+
+#define HSUSBD_CEPINTSTS_RXPKIF_Pos      (6)                                               /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position   */
+#define HSUSBD_CEPINTSTS_RXPKIF_Msk      (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos)            /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask       */
+
+#define HSUSBD_CEPINTSTS_NAKIF_Pos       (7)                                               /*!< HSUSBD_T::CEPINTSTS: NAKIF Position    */
+#define HSUSBD_CEPINTSTS_NAKIF_Msk       (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos)             /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask        */
+
+#define HSUSBD_CEPINTSTS_STALLIF_Pos     (8)                                               /*!< HSUSBD_T::CEPINTSTS: STALLIF Position  */
+#define HSUSBD_CEPINTSTS_STALLIF_Msk     (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos)           /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask      */
+
+#define HSUSBD_CEPINTSTS_ERRIF_Pos       (9)                                               /*!< HSUSBD_T::CEPINTSTS: ERRIF Position    */
+#define HSUSBD_CEPINTSTS_ERRIF_Msk       (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos)             /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask        */
+
+#define HSUSBD_CEPINTSTS_STSDONEIF_Pos   (10)                                              /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/
+#define HSUSBD_CEPINTSTS_STSDONEIF_Msk   (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos)         /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask    */
+
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos   (11)                                              /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk   (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos)         /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask    */
+
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos  (12)                                              /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk  (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos)        /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask   */
+
+#define HSUSBD_CEPTXCNT_TXCNT_Pos        (0)                                               /*!< HSUSBD_T::CEPTXCNT: TXCNT Position     */
+#define HSUSBD_CEPTXCNT_TXCNT_Msk        (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos)             /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask         */
+
+#define HSUSBD_CEPRXCNT_RXCNT_Pos        (0)                                               /*!< HSUSBD_T::CEPRXCNT: RXCNT Position     */
+#define HSUSBD_CEPRXCNT_RXCNT_Msk        (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos)             /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask         */
+
+#define HSUSBD_CEPDATCNT_DATCNT_Pos      (0)                                               /*!< HSUSBD_T::CEPDATCNT: DATCNT Position   */
+#define HSUSBD_CEPDATCNT_DATCNT_Msk      (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos)         /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask       */
+
+#define HSUSBD_SETUP1_0_SETUP0_Pos       (0)                                               /*!< HSUSBD_T::SETUP1_0: SETUP0 Position    */
+#define HSUSBD_SETUP1_0_SETUP0_Msk       (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos)            /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask        */
+
+#define HSUSBD_SETUP1_0_SETUP1_Pos       (8)                                               /*!< HSUSBD_T::SETUP1_0: SETUP1 Position    */
+#define HSUSBD_SETUP1_0_SETUP1_Msk       (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos)            /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask        */
+
+#define HSUSBD_SETUP3_2_SETUP2_Pos       (0)                                               /*!< HSUSBD_T::SETUP3_2: SETUP2 Position    */
+#define HSUSBD_SETUP3_2_SETUP2_Msk       (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos)            /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask        */
+
+#define HSUSBD_SETUP3_2_SETUP3_Pos       (8)                                               /*!< HSUSBD_T::SETUP3_2: SETUP3 Position    */
+#define HSUSBD_SETUP3_2_SETUP3_Msk       (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos)            /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask        */
+
+#define HSUSBD_SETUP5_4_SETUP4_Pos       (0)                                               /*!< HSUSBD_T::SETUP5_4: SETUP4 Position    */
+#define HSUSBD_SETUP5_4_SETUP4_Msk       (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos)            /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask        */
+
+#define HSUSBD_SETUP5_4_SETUP5_Pos       (8)                                               /*!< HSUSBD_T::SETUP5_4: SETUP5 Position    */
+#define HSUSBD_SETUP5_4_SETUP5_Msk       (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos)            /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask        */
+
+#define HSUSBD_SETUP7_6_SETUP6_Pos       (0)                                               /*!< HSUSBD_T::SETUP7_6: SETUP6 Position    */
+#define HSUSBD_SETUP7_6_SETUP6_Msk       (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos)            /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask        */
+
+#define HSUSBD_SETUP7_6_SETUP7_Pos       (8)                                               /*!< HSUSBD_T::SETUP7_6: SETUP7 Position    */
+#define HSUSBD_SETUP7_6_SETUP7_Msk       (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos)            /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask        */
+
+#define HSUSBD_CEPBUFST_SADDR_Pos        (0)                                               /*!< HSUSBD_T::CEPBUFST: SADDR Position     */
+#define HSUSBD_CEPBUFST_SADDR_Msk        (0xffful << HSUSBD_CEPBUFST_SADDR_Pos)            /*!< HSUSBD_T::CEPBUFST: SADDR Mask         */
+
+#define HSUSBD_CEPBUFEND_EADDR_Pos       (0)                                               /*!< HSUSBD_T::CEPBUFEND: EADDR Position    */
+#define HSUSBD_CEPBUFEND_EADDR_Msk       (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos)           /*!< HSUSBD_T::CEPBUFEND: EADDR Mask        */
+
+#define HSUSBD_DMACTL_EPNUM_Pos          (0)                                               /*!< HSUSBD_T::DMACTL: EPNUM Position       */
+#define HSUSBD_DMACTL_EPNUM_Msk          (0xful << HSUSBD_DMACTL_EPNUM_Pos)                /*!< HSUSBD_T::DMACTL: EPNUM Mask           */
+
+#define HSUSBD_DMACTL_DMARD_Pos          (4)                                               /*!< HSUSBD_T::DMACTL: DMARD Position       */
+#define HSUSBD_DMACTL_DMARD_Msk          (0x1ul << HSUSBD_DMACTL_DMARD_Pos)                /*!< HSUSBD_T::DMACTL: DMARD Mask           */
+
+#define HSUSBD_DMACTL_DMAEN_Pos          (5)                                               /*!< HSUSBD_T::DMACTL: DMAEN Position       */
+#define HSUSBD_DMACTL_DMAEN_Msk          (0x1ul << HSUSBD_DMACTL_DMAEN_Pos)                /*!< HSUSBD_T::DMACTL: DMAEN Mask           */
+
+#define HSUSBD_DMACTL_SGEN_Pos           (6)                                               /*!< HSUSBD_T::DMACTL: SGEN Position        */
+#define HSUSBD_DMACTL_SGEN_Msk           (0x1ul << HSUSBD_DMACTL_SGEN_Pos)                 /*!< HSUSBD_T::DMACTL: SGEN Mask            */
+
+#define HSUSBD_DMACTL_DMARST_Pos         (7)                                               /*!< HSUSBD_T::DMACTL: DMARST Position      */
+#define HSUSBD_DMACTL_DMARST_Msk         (0x1ul << HSUSBD_DMACTL_DMARST_Pos)               /*!< HSUSBD_T::DMACTL: DMARST Mask          */
+
+#define HSUSBD_DMACTL_SVINEP_Pos         (8)                                               /*!< HSUSBD_T::DMACTL: SVINEP Position      */
+#define HSUSBD_DMACTL_SVINEP_Msk         (0x1ul << HSUSBD_DMACTL_SVINEP_Pos)               /*!< HSUSBD_T::DMACTL: SVINEP Mask          */
+
+#define HSUSBD_DMACNT_DMACNT_Pos         (0)                                               /*!< HSUSBD_T::DMACNT: DMACNT Position      */
+#define HSUSBD_DMACNT_DMACNT_Msk         (0xffffful << HSUSBD_DMACNT_DMACNT_Pos)           /*!< HSUSBD_T::DMACNT: DMACNT Mask          */
+
+#define HSUSBD_EPDAT_EPDAT_Pos           (0)                                               /*!< HSUSBD_T::EPDAT: EPDAT Position        */
+#define HSUSBD_EPDAT_EPDAT_Msk           (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos)          /*!< HSUSBD_T::EPDAT: EPDAT Mask            */
+
+#define HSUSBD_EPINTSTS_BUFFULLIF_Pos    (0)                                               /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */
+#define HSUSBD_EPINTSTS_BUFFULLIF_Msk    (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos)          /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask     */
+
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos   (1)                                               /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk   (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos)         /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask    */
+
+#define HSUSBD_EPINTSTS_SHORTTXIF_Pos    (2)                                               /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */
+#define HSUSBD_EPINTSTS_SHORTTXIF_Msk    (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos)          /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask     */
+
+#define HSUSBD_EPINTSTS_TXPKIF_Pos       (3)                                               /*!< HSUSBD_T::EPINTSTS: TXPKIF Position    */
+#define HSUSBD_EPINTSTS_TXPKIF_Msk       (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos)             /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask        */
+
+#define HSUSBD_EPINTSTS_RXPKIF_Pos       (4)                                               /*!< HSUSBD_T::EPINTSTS: RXPKIF Position    */
+#define HSUSBD_EPINTSTS_RXPKIF_Msk       (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos)             /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask        */
+
+#define HSUSBD_EPINTSTS_OUTTKIF_Pos      (5)                                               /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position   */
+#define HSUSBD_EPINTSTS_OUTTKIF_Msk      (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos)            /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask       */
+
+#define HSUSBD_EPINTSTS_INTKIF_Pos       (6)                                               /*!< HSUSBD_T::EPINTSTS: INTKIF Position    */
+#define HSUSBD_EPINTSTS_INTKIF_Msk       (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos)             /*!< HSUSBD_T::EPINTSTS: INTKIF Mask        */
+
+#define HSUSBD_EPINTSTS_PINGIF_Pos       (7)                                               /*!< HSUSBD_T::EPINTSTS: PINGIF Position    */
+#define HSUSBD_EPINTSTS_PINGIF_Msk       (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos)             /*!< HSUSBD_T::EPINTSTS: PINGIF Mask        */
+
+#define HSUSBD_EPINTSTS_NAKIF_Pos        (8)                                               /*!< HSUSBD_T::EPINTSTS: NAKIF Position     */
+#define HSUSBD_EPINTSTS_NAKIF_Msk        (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos)              /*!< HSUSBD_T::EPINTSTS: NAKIF Mask         */
+
+#define HSUSBD_EPINTSTS_STALLIF_Pos      (9)                                               /*!< HSUSBD_T::EPINTSTS: STALLIF Position   */
+#define HSUSBD_EPINTSTS_STALLIF_Msk      (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos)            /*!< HSUSBD_T::EPINTSTS: STALLIF Mask       */
+
+#define HSUSBD_EPINTSTS_NYETIF_Pos       (10)                                              /*!< HSUSBD_T::EPINTSTS: NYETIF Position    */
+#define HSUSBD_EPINTSTS_NYETIF_Msk       (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos)             /*!< HSUSBD_T::EPINTSTS: NYETIF Mask        */
+
+#define HSUSBD_EPINTSTS_ERRIF_Pos        (11)                                              /*!< HSUSBD_T::EPINTSTS: ERRIF Position     */
+#define HSUSBD_EPINTSTS_ERRIF_Msk        (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos)              /*!< HSUSBD_T::EPINTSTS: ERRIF Mask         */
+
+#define HSUSBD_EPINTSTS_SHORTRXIF_Pos    (12)                                              /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */
+#define HSUSBD_EPINTSTS_SHORTRXIF_Msk    (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos)          /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask     */
+
+#define HSUSBD_EPINTEN_BUFFULLIEN_Pos    (0)                                               /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */
+#define HSUSBD_EPINTEN_BUFFULLIEN_Msk    (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos)          /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask     */
+
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos   (1)                                               /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk   (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos)         /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask    */
+
+#define HSUSBD_EPINTEN_SHORTTXIEN_Pos    (2)                                               /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */
+#define HSUSBD_EPINTEN_SHORTTXIEN_Msk    (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos)          /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask     */
+
+#define HSUSBD_EPINTEN_TXPKIEN_Pos       (3)                                               /*!< HSUSBD_T::EPINTEN: TXPKIEN Position    */
+#define HSUSBD_EPINTEN_TXPKIEN_Msk       (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos)             /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask        */
+
+#define HSUSBD_EPINTEN_RXPKIEN_Pos       (4)                                               /*!< HSUSBD_T::EPINTEN: RXPKIEN Position    */
+#define HSUSBD_EPINTEN_RXPKIEN_Msk       (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos)             /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask        */
+
+#define HSUSBD_EPINTEN_OUTTKIEN_Pos      (5)                                               /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position   */
+#define HSUSBD_EPINTEN_OUTTKIEN_Msk      (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos)            /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask       */
+
+#define HSUSBD_EPINTEN_INTKIEN_Pos       (6)                                               /*!< HSUSBD_T::EPINTEN: INTKIEN Position    */
+#define HSUSBD_EPINTEN_INTKIEN_Msk       (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos)             /*!< HSUSBD_T::EPINTEN: INTKIEN Mask        */
+
+#define HSUSBD_EPINTEN_PINGIEN_Pos       (7)                                               /*!< HSUSBD_T::EPINTEN: PINGIEN Position    */
+#define HSUSBD_EPINTEN_PINGIEN_Msk       (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos)             /*!< HSUSBD_T::EPINTEN: PINGIEN Mask        */
+
+#define HSUSBD_EPINTEN_NAKIEN_Pos        (8)                                               /*!< HSUSBD_T::EPINTEN: NAKIEN Position     */
+#define HSUSBD_EPINTEN_NAKIEN_Msk        (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos)              /*!< HSUSBD_T::EPINTEN: NAKIEN Mask         */
+
+#define HSUSBD_EPINTEN_STALLIEN_Pos      (9)                                               /*!< HSUSBD_T::EPINTEN: STALLIEN Position   */
+#define HSUSBD_EPINTEN_STALLIEN_Msk      (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos)            /*!< HSUSBD_T::EPINTEN: STALLIEN Mask       */
+
+#define HSUSBD_EPINTEN_NYETIEN_Pos       (10)                                              /*!< HSUSBD_T::EPINTEN: NYETIEN Position    */
+#define HSUSBD_EPINTEN_NYETIEN_Msk       (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos)             /*!< HSUSBD_T::EPINTEN: NYETIEN Mask        */
+
+#define HSUSBD_EPINTEN_ERRIEN_Pos        (11)                                              /*!< HSUSBD_T::EPINTEN: ERRIEN Position     */
+#define HSUSBD_EPINTEN_ERRIEN_Msk        (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos)              /*!< HSUSBD_T::EPINTEN: ERRIEN Mask         */
+
+#define HSUSBD_EPINTEN_SHORTRXIEN_Pos    (12)                                              /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */
+#define HSUSBD_EPINTEN_SHORTRXIEN_Msk    (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos)          /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask     */
+
+#define HSUSBD_EPDATCNT_DATCNT_Pos       (0)                                               /*!< HSUSBD_T::EPDATCNT: DATCNT Position    */
+#define HSUSBD_EPDATCNT_DATCNT_Msk       (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos)          /*!< HSUSBD_T::EPDATCNT: DATCNT Mask        */
+
+#define HSUSBD_EPDATCNT_DMALOOP_Pos      (16)                                              /*!< HSUSBD_T::EPDATCNT: DMALOOP Position   */
+#define HSUSBD_EPDATCNT_DMALOOP_Msk      (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos)         /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask       */
+
+#define HSUSBD_EPRSPCTL_FLUSH_Pos        (0)                                               /*!< HSUSBD_T::EPRSPCTL: FLUSH Position     */
+#define HSUSBD_EPRSPCTL_FLUSH_Msk        (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos)              /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask         */
+
+#define HSUSBD_EPRSPCTL_MODE_Pos         (1)                                               /*!< HSUSBD_T::EPRSPCTL: MODE Position      */
+#define HSUSBD_EPRSPCTL_MODE_Msk         (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos)               /*!< HSUSBD_T::EPRSPCTL: MODE Mask          */
+
+#define HSUSBD_EPRSPCTL_TOGGLE_Pos       (3)                                               /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position    */
+#define HSUSBD_EPRSPCTL_TOGGLE_Msk       (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos)             /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask        */
+
+#define HSUSBD_EPRSPCTL_HALT_Pos         (4)                                               /*!< HSUSBD_T::EPRSPCTL: HALT Position      */
+#define HSUSBD_EPRSPCTL_HALT_Msk         (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos)               /*!< HSUSBD_T::EPRSPCTL: HALT Mask          */
+
+#define HSUSBD_EPRSPCTL_ZEROLEN_Pos      (5)                                               /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position   */
+#define HSUSBD_EPRSPCTL_ZEROLEN_Msk      (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos)            /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask       */
+
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos    (6)                                               /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk    (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos)          /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask     */
+
+#define HSUSBD_EPRSPCTL_DISBUF_Pos       (7)                                               /*!< HSUSBD_T::EPRSPCTL: DISBUF Position    */
+#define HSUSBD_EPRSPCTL_DISBUF_Msk       (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos)             /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask        */
+
+#define HSUSBD_EPMPS_EPMPS_Pos           (0)                                               /*!< HSUSBD_T::EPMPS: EPMPS Position        */
+#define HSUSBD_EPMPS_EPMPS_Msk           (0x7fful << HSUSBD_EPMPS_EPMPS_Pos)               /*!< HSUSBD_T::EPMPS: EPMPS Mask            */
+
+#define HSUSBD_EPTXCNT_TXCNT_Pos         (0)                                               /*!< HSUSBD_T::EPTXCNT: TXCNT Position      */
+#define HSUSBD_EPTXCNT_TXCNT_Msk         (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos)             /*!< HSUSBD_T::EPTXCNT: TXCNT Mask          */
+
+#define HSUSBD_EPCFG_EPEN_Pos            (0)                                               /*!< HSUSBD_T::EPCFG: EPEN Position         */
+#define HSUSBD_EPCFG_EPEN_Msk            (0x1ul << HSUSBD_EPCFG_EPEN_Pos)                  /*!< HSUSBD_T::EPCFG: EPEN Mask             */
+
+#define HSUSBD_EPCFG_EPTYPE_Pos          (1)                                               /*!< HSUSBD_T::EPCFG: EPTYPE Position       */
+#define HSUSBD_EPCFG_EPTYPE_Msk          (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos)                /*!< HSUSBD_T::EPCFG: EPTYPE Mask           */
+
+#define HSUSBD_EPCFG_EPDIR_Pos           (3)                                               /*!< HSUSBD_T::EPCFG: EPDIR Position        */
+#define HSUSBD_EPCFG_EPDIR_Msk           (0x1ul << HSUSBD_EPCFG_EPDIR_Pos)                 /*!< HSUSBD_T::EPCFG: EPDIR Mask            */
+
+#define HSUSBD_EPCFG_EPNUM_Pos           (4)                                               /*!< HSUSBD_T::EPCFG: EPNUM Position        */
+#define HSUSBD_EPCFG_EPNUM_Msk           (0xful << HSUSBD_EPCFG_EPNUM_Pos)                 /*!< HSUSBD_T::EPCFG: EPNUM Mask            */
+
+#define HSUSBD_EPBUFST_SADDR_Pos         (0)                                               /*!< HSUSBD_T::EPBUFST: SADDR Position      */
+#define HSUSBD_EPBUFST_SADDR_Msk         (0xffful << HSUSBD_EPBUFST_SADDR_Pos)             /*!< HSUSBD_T::EPBUFST: SADDR Mask          */
+
+#define HSUSBD_EPBUFEND_EADDR_Pos        (0)                                               /*!< HSUSBD_T::EPBUFEND: EADDR Position     */
+#define HSUSBD_EPBUFEND_EADDR_Msk        (0xffful << HSUSBD_EPBUFEND_EADDR_Pos)            /*!< HSUSBD_T::EPBUFEND: EADDR Mask         */
+
+#define HSUSBD_DMAADDR_DMAADDR_Pos       (0)                                               /*!< HSUSBD_T::DMAADDR: DMAADDR Position    */
+#define HSUSBD_DMAADDR_DMAADDR_Msk       (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos)      /*!< HSUSBD_T::DMAADDR: DMAADDR Mask        */
+
+#define HSUSBD_PHYCTL_DPPUEN_Pos         (8)                                               /*!< HSUSBD_T::PHYCTL: DPPUEN Position      */
+#define HSUSBD_PHYCTL_DPPUEN_Msk         (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos)               /*!< HSUSBD_T::PHYCTL: DPPUEN Mask          */
+
+#define HSUSBD_PHYCTL_PHYEN_Pos          (9)                                               /*!< HSUSBD_T::PHYCTL: PHYEN Position       */
+#define HSUSBD_PHYCTL_PHYEN_Msk          (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos)                /*!< HSUSBD_T::PHYCTL: PHYEN Mask           */
+
+#define HSUSBD_PHYCTL_WKEN_Pos           (24)                                              /*!< HSUSBD_T::PHYCTL: WKEN Position        */
+#define HSUSBD_PHYCTL_WKEN_Msk           (0x1ul << HSUSBD_PHYCTL_WKEN_Pos)                 /*!< HSUSBD_T::PHYCTL: WKEN Mask            */
+
+#define HSUSBD_PHYCTL_VBUSDET_Pos        (31)                                              /*!< HSUSBD_T::PHYCTL: VBUSDET Position     */
+#define HSUSBD_PHYCTL_VBUSDET_Msk        (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos)              /*!< HSUSBD_T::PHYCTL: VBUSDET Mask         */
+
+/**@}*/ /* HSUSBD_CONST */
+/**@}*/ /* end of HSUSBD register group */
+
+
+/*---------------------- USB Host Controller -------------------------*/
+/**
+    @addtogroup USBH USB Host Controller(USBH)
+    Memory Mapped Structure for USBH Controller
+@{ */
+
+typedef struct {
+
+    /**
+     * @var USBH_T::HcRevision
+     * Offset: 0x00  Host Controller Revision Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |REV       |Revision Number
+     * |        |          |Indicates the Open HCI Specification revision number implemented by the Hardware
+     * |        |          |Host Controller supports 1.1 specification.
+     * |        |          |(X.Y = XYh).
+     * @var USBH_T::HcControl
+     * Offset: 0x04  Host Controller Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CBSR      |Control Bulk Service Ratio
+     * |        |          |This specifies the service ratio between Control and Bulk EDs
+     * |        |          |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
+     * |        |          |The internal count will be retained when crossing the frame boundary
+     * |        |          |In case of reset, HCD is responsible for restoring this
+     * |        |          |Value.
+     * |        |          |00 = Number of Control EDs over Bulk EDs served is 1:1.
+     * |        |          |01 = Number of Control EDs over Bulk EDs served is 2:1.
+     * |        |          |10 = Number of Control EDs over Bulk EDs served is 3:1.
+     * |        |          |11 = Number of Control EDs over Bulk EDs served is 4:1.
+     * |[2]     |PLE       |Periodic List Enable Bit
+     * |        |          |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
+     * |        |          |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+     * |        |          |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
+     * |        |          |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+     * |[3]     |IE        |Isochronous List Enable Bit
+     * |        |          |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
+     * |        |          |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+     * |        |          |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
+     * |[4]     |CLE       |Control List Enable Bit
+     * |        |          |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Control list in the next frame Enabled.
+     * |[5]     |BLE       |Bulk List Enable Bit
+     * |        |          |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Bulk list in the next frame Enabled.
+     * |[7:6]   |HCFS      |Host Controller Functional State
+     * |        |          |This field sets the Host Controller state
+     * |        |          |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
+     * |        |          |States are:
+     * |        |          |00 = USBSUSPEND.
+     * |        |          |01 = USBOPERATIONAL.
+     * |        |          |10 = USBRESUME.
+     * |        |          |11 = USBRESET.
+     * @var USBH_T::HcCommandStatus
+     * Offset: 0x08  Host Controller Command Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HCR       |Host Controller Reset
+     * |        |          |This bit is set to initiate the software reset of Host Controller
+     * |        |          |This bit is cleared by the Host Controller, upon completed of the reset operation.
+     * |        |          |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+     * |        |          |0 = Host Controller is not in software reset state.
+     * |        |          |1 = Host Controller is in software reset state.
+     * |[1]     |CLF       |Control List Filled
+     * |        |          |Set high to indicate there is an active TD on the Control List
+     * |        |          |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Control list.
+     * |        |          |1 = An active TD added or found on the Control list.
+     * |[2]     |BLF       |Bulk List Filled
+     * |        |          |Set high to indicate there is an active TD on the Bulk list
+     * |        |          |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+     * |        |          |1 = An active TD added or found on the Bulk list.
+     * |[17:16] |SOC       |Schedule Overrun Count
+     * |        |          |These bits are incremented on each scheduling overrun error
+     * |        |          |It is initialized to 00b and wraps around at 11b
+     * |        |          |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
+     * @var USBH_T::HcInterruptStatus
+     * Offset: 0x0C  Host Controller Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun
+     * |        |          |Set when the List Processor determines a Schedule Overrun has occurred.
+     * |        |          |0 = Schedule Overrun didn't occur.
+     * |        |          |1 = Schedule Overrun has occurred.
+     * |[1]     |WDH       |Write Back Done Head
+     * |        |          |Set after the Host Controller has written HcDoneHead to HccaDoneHead
+     * |        |          |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+     * |        |          |0 =.Host Controller didn't update HccaDoneHead.
+     * |        |          |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
+     * |[2]     |SF        |Start of Frame
+     * |        |          |Set when the Frame Management functional block signals a 'Start of Frame' event
+     * |        |          |Host Control generates a SOF token at the same time.
+     * |        |          |0 =.Not the start of a frame.
+     * |        |          |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
+     * |[3]     |RD        |Resume Detected
+     * |        |          |Set when Host Controller detects resume signaling on a downstream port.
+     * |        |          |0 = No resume signaling detected on a downstream port.
+     * |        |          |1 = Resume signaling detected on a downstream port.
+     * |[5]     |FNO       |Frame Number Overflow
+     * |        |          |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |        |          |0 = The bit 15 of Frame Number didn't change.
+     * |        |          |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |[6]     |RHSC      |Root Hub Status Change
+     * |        |          |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * |        |          |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
+     * |        |          |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * @var USBH_T::HcInterruptEnable
+     * Offset: 0x10  Host Controller Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Enable Bit
+     * |        |          |This bit is a global interrupt enable
+     * |        |          |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcInterruptDisable
+     * Offset: 0x14  Host Controller Interrupt Disable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Disable Bit
+     * |        |          |Global interrupt disable. Writing '1' to disable all interrupts.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcHCCA
+     * Offset: 0x18  Host Controller Communication Area Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:8]  |HCCA      |Host Controller Communication Area
+     * |        |          |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
+     * @var USBH_T::HcPeriodCurrentED
+     * Offset: 0x1C  Host Controller Period Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |PCED      |Periodic Current ED
+     * |        |          |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+     * @var USBH_T::HcControlHeadED
+     * Offset: 0x20  Host Controller Control Head ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CHED      |Control Head ED
+     * |        |          |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcControlCurrentED
+     * Offset: 0x24  Host Controller Control Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CCED      |Control Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcBulkHeadED
+     * Offset: 0x28  Host Controller Bulk Head ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BHED      |Bulk Head ED
+     * |        |          |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+     * @var USBH_T::HcBulkCurrentED
+     * Offset: 0x2C  Host Controller Bulk Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BCED      |Bulk Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+     * @var USBH_T::HcDoneHead
+     * Offset: 0x30  Host Controller Done Head Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |DH        |Done Head
+     * |        |          |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+     * @var USBH_T::HcFmInterval
+     * Offset: 0x34  Host Controller Frame Interval Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FI        |Frame Interval
+     * |        |          |This field specifies the length of a frame as (bit times - 1)
+     * |        |          |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+     * |[30:16] |FSMPS     |FS Largest Data Packet
+     * |        |          |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+     * |[31]    |FIT       |Frame Interval Toggle
+     * |        |          |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
+     * |        |          |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
+     * |        |          |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
+     * @var USBH_T::HcFmRemaining
+     * Offset: 0x38  Host Controller Frame Remaining Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FR        |Frame Remaining
+     * |        |          |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
+     * |        |          |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
+     * |        |          |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+     * |[31]    |FRT       |Frame Remaining Toggle
+     * |        |          |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
+     * @var USBH_T::HcFmNumber
+     * Offset: 0x3C  Host Controller Frame Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FN        |Frame Number
+     * |        |          |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
+     * |        |          |The count rolls over from 'FFFFh' to '0h.'
+     * @var USBH_T::HcPeriodicStart
+     * Offset: 0x40  Host Controller Periodic Start Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |PS        |Periodic Start
+     * |        |          |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+     * @var USBH_T::HcLSThreshold
+     * Offset: 0x44  Host Controller Low-speed Threshold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |LST       |Low-speed Threshold
+     * |        |          |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
+     * |        |          |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
+     * |        |          |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+     * @var USBH_T::HcRhDescriptorA
+     * Offset: 0x48  Host Controller Root Hub Descriptor A Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |NDP       |Number Downstream Ports
+     * |        |          |USB host control supports two downstream ports and only one port is available in this series of chip.
+     * |[8]     |PSM       |Power Switching Mode
+     * |        |          |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+     * |        |          |0 = Global Switching.
+     * |        |          |1 = Individual Switching.
+     * |[11]    |OCPM      |over Current Protection Mode
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported
+     * |        |          |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
+     * |        |          |0 = Global Over current.
+     * |        |          |1 = Individual Over current.
+     * |[12]    |NOCP      |No over Current Protection
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported.
+     * |        |          |0 = Over current status is reported.
+     * |        |          |1 = Over current status is not reported.
+     * @var USBH_T::HcRhDescriptorB
+     * Offset: 0x4C  Host Controller Root Hub Descriptor B Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:16] |PPCM      |Port Power Control Mask
+     * |        |          |Global power switching
+     * |        |          |This field is only valid if PowerSwitchingMode is set (individual port switching)
+     * |        |          |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
+     * |        |          |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
+     * |        |          |0 = Port power controlled by global power switching.
+     * |        |          |1 = Port power controlled by port power switching.
+     * |        |          |Note: PPCM[15:2] and PPCM[0] are reserved.
+     * @var USBH_T::HcRhStatus
+     * Offset: 0x50  Host Controller Root Hub Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LPS       |Clear Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear global power.
+     * |[1]     |OCI       |over Current Indicator
+     * |        |          |This bit reflects the state of the over current status pin
+     * |        |          |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[15]    |DRWE      |Device Remote Wakeup Enable Bit
+     * |        |          |This bit controls if port's Connect Status Change as a remote wake-up event.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Connect Status Change as a remote wake-up event Disabled.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |[16]    |LPSC      |Set Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set global power.
+     * |[17]    |OCIC      |over Current Indicator Change
+     * |        |          |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = OCI (HcRhStatus[1]) didn't change.
+     * |        |          |1 = OCI (HcRhStatus[1]) change.
+     * |[31]    |CRWE      |Clear Remote Wake-up Enable Bit
+     * |        |          |This bit is use to clear DRWE (HcRhStatus[15]).
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear DRWE (HcRhStatus[15]).
+     * @var USBH_T::HcRhPortStatus[2]
+     * Offset: 0x54  Host Controller Root Hub Port Status
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCS       |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = No device connected.
+     * |        |          |1 = Device connected.
+     * |[1]     |PES       |Port Enable Status
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port Disabled.
+     * |        |          |1 = Port Enabled.
+     * |[2]     |PSS       |Port Suspend Status
+     * |        |          |This bit indicates the port is suspended
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port is not suspended.
+     * |        |          |1 = Port is selectively suspended.
+     * |[3]     |POCI      |Port over Current Indicator (Read) or Clear Port Suspend (Write)
+     * |        |          |This bit reflects the state of the over current status pin dedicated to this port
+     * |        |          |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
+     * |        |          |This bit is also used to initiate the selective result sequence for the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[4]     |PRS       |Port Reset Status
+     * |        |          |This bit reflects the reset state of the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port reset.
+     * |        |          |Read Operation
+     * |        |          |0 = Port reset signal is not active.
+     * |        |          |1 = Port reset signal is active.
+     * |[8]     |PPS       |Port Power Status
+     * |        |          |This bit reflects the power state of the port regardless of the power switching mode.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Port Power Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port power is Disabled.
+     * |        |          |1 = Port power is Enabled.
+     * |[9]     |LSDA      |Low Speed Device Attached (Read) or Clear Port Power (Write)
+     * |        |          |This bit defines the speed (and bud idle) of the attached device
+     * |        |          |It is only valid when CCS (HcRhPortStatus1[0]) is set.
+     * |        |          |This bit is also used to clear port power.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear PPS (HcRhPortStatus1[8]).
+     * |        |          |Read Operation:
+     * |        |          |0 = Full Speed device.
+     * |        |          |1 = Low-speed device.
+     * |[16]    |CSC       |Connect Status Change
+     * |        |          |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
+     * |        |          |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
+     * |[17]    |PESC      |Port Enable Status Change
+     * |        |          |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = PES (HcRhPortStatus1[1]) didn't change.
+     * |        |          |1 = PES (HcRhPortStatus1[1]) changed.
+     * |[18]    |PSSC      |Port Suspend Status Change
+     * |        |          |This bit indicates the completion of the selective resume sequence for the port.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port resume is not completed.
+     * |        |          |1 = Port resume completed.
+     * |[19]    |OCIC      |Port over Current Indicator Change
+     * |        |          |This bit is set when POCI (HcRhPortStatus1[3]) changes.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = POCI (HcRhPortStatus1[3]) didn't change.
+     * |        |          |1 = POCI (HcRhPortStatus1[3]) changes.
+     * |[20]    |PRSC      |Port Reset Status Change
+     * |        |          |This bit indicates that the port reset signal has completed.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port reset is not complete.
+     * |        |          |1 = Port reset is complete.
+     * @var USBH_T::HcPhyControl
+     * Offset: 0x200  Host Controller PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[27]    |STBYEN    |USB Transceiver Standby Enable Bit
+     * |        |          |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+     * |        |          |0 = The USB transceiver would never enter the standby mode.
+     * |        |          |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+     * @var USBH_T::HcMiscControl
+     * Offset: 0x204  Host Controller Miscellaneous Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |ABORT     |AHB Bus ERROR Response
+     * |        |          |This bit indicates there is an ERROR response received in AHB bus.
+     * |        |          |0 = No ERROR response received.
+     * |        |          |1 = ERROR response received.
+     * |[3]     |OCAL      |over Current Active Low
+     * |        |          |This bit controls the polarity of over current flag from external power IC.
+     * |        |          |0 = Over current flag is high active.
+     * |        |          |1 = Over current flag is low active.
+     * |[16]    |DPRT1     |Disable Port 1
+     * |        |          |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
+     * |        |          |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+     * |        |          |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+     * |        |          |0 = The connection between USB host controller and transceiver of port 1 Enabled.
+     * |        |          |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
+     */
+    __I  uint32_t HcRevision;            /*!< [0x0000] Host Controller Revision Register                                */
+    __IO uint32_t HcControl;             /*!< [0x0004] Host Controller Control Register                                 */
+    __IO uint32_t HcCommandStatus;       /*!< [0x0008] Host Controller Command Status Register                          */
+    __IO uint32_t HcInterruptStatus;     /*!< [0x000c] Host Controller Interrupt Status Register                        */
+    __IO uint32_t HcInterruptEnable;     /*!< [0x0010] Host Controller Interrupt Enable Register                        */
+    __IO uint32_t HcInterruptDisable;    /*!< [0x0014] Host Controller Interrupt Disable Register                       */
+    __IO uint32_t HcHCCA;                /*!< [0x0018] Host Controller Communication Area Register                      */
+    __IO uint32_t HcPeriodCurrentED;     /*!< [0x001c] Host Controller Period Current ED Register                       */
+    __IO uint32_t HcControlHeadED;       /*!< [0x0020] Host Controller Control Head ED Register                         */
+    __IO uint32_t HcControlCurrentED;    /*!< [0x0024] Host Controller Control Current ED Register                      */
+    __IO uint32_t HcBulkHeadED;          /*!< [0x0028] Host Controller Bulk Head ED Register                            */
+    __IO uint32_t HcBulkCurrentED;       /*!< [0x002c] Host Controller Bulk Current ED Register                         */
+    __IO uint32_t HcDoneHead;            /*!< [0x0030] Host Controller Done Head Register                               */
+    __IO uint32_t HcFmInterval;          /*!< [0x0034] Host Controller Frame Interval Register                          */
+    __I  uint32_t HcFmRemaining;         /*!< [0x0038] Host Controller Frame Remaining Register                         */
+    __I  uint32_t HcFmNumber;            /*!< [0x003c] Host Controller Frame Number Register                            */
+    __IO uint32_t HcPeriodicStart;       /*!< [0x0040] Host Controller Periodic Start Register                          */
+    __IO uint32_t HcLSThreshold;         /*!< [0x0044] Host Controller Low-speed Threshold Register                     */
+    __IO uint32_t HcRhDescriptorA;       /*!< [0x0048] Host Controller Root Hub Descriptor A Register                   */
+    __IO uint32_t HcRhDescriptorB;       /*!< [0x004c] Host Controller Root Hub Descriptor B Register                   */
+    __IO uint32_t HcRhStatus;            /*!< [0x0050] Host Controller Root Hub Status Register                         */
+    __IO uint32_t HcRhPortStatus[2];     /*!< [0x0054] Host Controller Root Hub Port Status [1]                         */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[105];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t HcPhyControl;          /*!< [0x0200] Host Controller PHY Control Register                             */
+    __IO uint32_t HcMiscControl;         /*!< [0x0204] Host Controller Miscellaneous Control Register                   */
+
+} USBH_T;
+
+/**
+    @addtogroup USBH_CONST USBH Bit Field Definition
+    Constant Definitions for USBH Controller
+@{ */
+
+#define USBH_HcRevision_REV_Pos          (0)                                               /*!< USBH_T::HcRevision: REV Position       */
+#define USBH_HcRevision_REV_Msk          (0xfful << USBH_HcRevision_REV_Pos)               /*!< USBH_T::HcRevision: REV Mask           */
+
+#define USBH_HcControl_CBSR_Pos          (0)                                               /*!< USBH_T::HcControl: CBSR Position       */
+#define USBH_HcControl_CBSR_Msk          (0x3ul << USBH_HcControl_CBSR_Pos)                /*!< USBH_T::HcControl: CBSR Mask           */
+
+#define USBH_HcControl_PLE_Pos           (2)                                               /*!< USBH_T::HcControl: PLE Position        */
+#define USBH_HcControl_PLE_Msk           (0x1ul << USBH_HcControl_PLE_Pos)                 /*!< USBH_T::HcControl: PLE Mask            */
+
+#define USBH_HcControl_IE_Pos            (3)                                               /*!< USBH_T::HcControl: IE Position         */
+#define USBH_HcControl_IE_Msk            (0x1ul << USBH_HcControl_IE_Pos)                  /*!< USBH_T::HcControl: IE Mask             */
+
+#define USBH_HcControl_CLE_Pos           (4)                                               /*!< USBH_T::HcControl: CLE Position        */
+#define USBH_HcControl_CLE_Msk           (0x1ul << USBH_HcControl_CLE_Pos)                 /*!< USBH_T::HcControl: CLE Mask            */
+
+#define USBH_HcControl_BLE_Pos           (5)                                               /*!< USBH_T::HcControl: BLE Position        */
+#define USBH_HcControl_BLE_Msk           (0x1ul << USBH_HcControl_BLE_Pos)                 /*!< USBH_T::HcControl: BLE Mask            */
+
+#define USBH_HcControl_HCFS_Pos          (6)                                               /*!< USBH_T::HcControl: HCFS Position       */
+#define USBH_HcControl_HCFS_Msk          (0x3ul << USBH_HcControl_HCFS_Pos)                /*!< USBH_T::HcControl: HCFS Mask           */
+
+#define USBH_HcCommandStatus_HCR_Pos     (0)                                               /*!< USBH_T::HcCommandStatus: HCR Position  */
+#define USBH_HcCommandStatus_HCR_Msk     (0x1ul << USBH_HcCommandStatus_HCR_Pos)           /*!< USBH_T::HcCommandStatus: HCR Mask      */
+
+#define USBH_HcCommandStatus_CLF_Pos     (1)                                               /*!< USBH_T::HcCommandStatus: CLF Position  */
+#define USBH_HcCommandStatus_CLF_Msk     (0x1ul << USBH_HcCommandStatus_CLF_Pos)           /*!< USBH_T::HcCommandStatus: CLF Mask      */
+
+#define USBH_HcCommandStatus_BLF_Pos     (2)                                               /*!< USBH_T::HcCommandStatus: BLF Position  */
+#define USBH_HcCommandStatus_BLF_Msk     (0x1ul << USBH_HcCommandStatus_BLF_Pos)           /*!< USBH_T::HcCommandStatus: BLF Mask      */
+
+#define USBH_HcCommandStatus_SOC_Pos     (16)                                              /*!< USBH_T::HcCommandStatus: SOC Position  */
+#define USBH_HcCommandStatus_SOC_Msk     (0x3ul << USBH_HcCommandStatus_SOC_Pos)           /*!< USBH_T::HcCommandStatus: SOC Mask      */
+
+#define USBH_HcInterruptStatus_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptStatus: SO Position */
+#define USBH_HcInterruptStatus_SO_Msk    (0x1ul << USBH_HcInterruptStatus_SO_Pos)          /*!< USBH_T::HcInterruptStatus: SO Mask     */
+
+#define USBH_HcInterruptStatus_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptStatus: WDH Position*/
+#define USBH_HcInterruptStatus_WDH_Msk   (0x1ul << USBH_HcInterruptStatus_WDH_Pos)         /*!< USBH_T::HcInterruptStatus: WDH Mask    */
+
+#define USBH_HcInterruptStatus_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptStatus: SF Position */
+#define USBH_HcInterruptStatus_SF_Msk    (0x1ul << USBH_HcInterruptStatus_SF_Pos)          /*!< USBH_T::HcInterruptStatus: SF Mask     */
+
+#define USBH_HcInterruptStatus_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptStatus: RD Position */
+#define USBH_HcInterruptStatus_RD_Msk    (0x1ul << USBH_HcInterruptStatus_RD_Pos)          /*!< USBH_T::HcInterruptStatus: RD Mask     */
+
+#define USBH_HcInterruptStatus_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptStatus: FNO Position*/
+#define USBH_HcInterruptStatus_FNO_Msk   (0x1ul << USBH_HcInterruptStatus_FNO_Pos)         /*!< USBH_T::HcInterruptStatus: FNO Mask    */
+
+#define USBH_HcInterruptStatus_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptStatus: RHSC Position*/
+#define USBH_HcInterruptStatus_RHSC_Msk  (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)        /*!< USBH_T::HcInterruptStatus: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptEnable: SO Position */
+#define USBH_HcInterruptEnable_SO_Msk    (0x1ul << USBH_HcInterruptEnable_SO_Pos)          /*!< USBH_T::HcInterruptEnable: SO Mask     */
+
+#define USBH_HcInterruptEnable_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptEnable: WDH Position*/
+#define USBH_HcInterruptEnable_WDH_Msk   (0x1ul << USBH_HcInterruptEnable_WDH_Pos)         /*!< USBH_T::HcInterruptEnable: WDH Mask    */
+
+#define USBH_HcInterruptEnable_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptEnable: SF Position */
+#define USBH_HcInterruptEnable_SF_Msk    (0x1ul << USBH_HcInterruptEnable_SF_Pos)          /*!< USBH_T::HcInterruptEnable: SF Mask     */
+
+#define USBH_HcInterruptEnable_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptEnable: RD Position */
+#define USBH_HcInterruptEnable_RD_Msk    (0x1ul << USBH_HcInterruptEnable_RD_Pos)          /*!< USBH_T::HcInterruptEnable: RD Mask     */
+
+#define USBH_HcInterruptEnable_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptEnable: FNO Position*/
+#define USBH_HcInterruptEnable_FNO_Msk   (0x1ul << USBH_HcInterruptEnable_FNO_Pos)         /*!< USBH_T::HcInterruptEnable: FNO Mask    */
+
+#define USBH_HcInterruptEnable_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptEnable: RHSC Position*/
+#define USBH_HcInterruptEnable_RHSC_Msk  (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)        /*!< USBH_T::HcInterruptEnable: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_MIE_Pos   (31)                                              /*!< USBH_T::HcInterruptEnable: MIE Position*/
+#define USBH_HcInterruptEnable_MIE_Msk   (0x1ul << USBH_HcInterruptEnable_MIE_Pos)         /*!< USBH_T::HcInterruptEnable: MIE Mask    */
+
+#define USBH_HcInterruptDisable_SO_Pos   (0)                                               /*!< USBH_T::HcInterruptDisable: SO Position*/
+#define USBH_HcInterruptDisable_SO_Msk   (0x1ul << USBH_HcInterruptDisable_SO_Pos)         /*!< USBH_T::HcInterruptDisable: SO Mask    */
+
+#define USBH_HcInterruptDisable_WDH_Pos  (1)                                               /*!< USBH_T::HcInterruptDisable: WDH Position*/
+#define USBH_HcInterruptDisable_WDH_Msk  (0x1ul << USBH_HcInterruptDisable_WDH_Pos)        /*!< USBH_T::HcInterruptDisable: WDH Mask   */
+
+#define USBH_HcInterruptDisable_SF_Pos   (2)                                               /*!< USBH_T::HcInterruptDisable: SF Position*/
+#define USBH_HcInterruptDisable_SF_Msk   (0x1ul << USBH_HcInterruptDisable_SF_Pos)         /*!< USBH_T::HcInterruptDisable: SF Mask    */
+
+#define USBH_HcInterruptDisable_RD_Pos   (3)                                               /*!< USBH_T::HcInterruptDisable: RD Position*/
+#define USBH_HcInterruptDisable_RD_Msk   (0x1ul << USBH_HcInterruptDisable_RD_Pos)         /*!< USBH_T::HcInterruptDisable: RD Mask    */
+
+#define USBH_HcInterruptDisable_FNO_Pos  (5)                                               /*!< USBH_T::HcInterruptDisable: FNO Position*/
+#define USBH_HcInterruptDisable_FNO_Msk  (0x1ul << USBH_HcInterruptDisable_FNO_Pos)        /*!< USBH_T::HcInterruptDisable: FNO Mask   */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6)                                               /*!< USBH_T::HcInterruptDisable: RHSC Position*/
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)       /*!< USBH_T::HcInterruptDisable: RHSC Mask  */
+
+#define USBH_HcInterruptDisable_MIE_Pos  (31)                                              /*!< USBH_T::HcInterruptDisable: MIE Position*/
+#define USBH_HcInterruptDisable_MIE_Msk  (0x1ul << USBH_HcInterruptDisable_MIE_Pos)        /*!< USBH_T::HcInterruptDisable: MIE Mask   */
+
+#define USBH_HcHCCA_HCCA_Pos             (8)                                               /*!< USBH_T::HcHCCA: HCCA Position          */
+#define USBH_HcHCCA_HCCA_Msk             (0xfffffful << USBH_HcHCCA_HCCA_Pos)              /*!< USBH_T::HcHCCA: HCCA Mask              */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos  (4)                                               /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
+#define USBH_HcPeriodCurrentED_PCED_Msk  (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)  /*!< USBH_T::HcPeriodCurrentED: PCED Mask   */
+
+#define USBH_HcControlHeadED_CHED_Pos    (4)                                               /*!< USBH_T::HcControlHeadED: CHED Position */
+#define USBH_HcControlHeadED_CHED_Msk    (0xffffffful << USBH_HcControlHeadED_CHED_Pos)    /*!< USBH_T::HcControlHeadED: CHED Mask     */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4)                                               /*!< USBH_T::HcControlCurrentED: CCED Position*/
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask  */
+
+#define USBH_HcBulkHeadED_BHED_Pos       (4)                                               /*!< USBH_T::HcBulkHeadED: BHED Position    */
+#define USBH_HcBulkHeadED_BHED_Msk       (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)       /*!< USBH_T::HcBulkHeadED: BHED Mask        */
+
+#define USBH_HcBulkCurrentED_BCED_Pos    (4)                                               /*!< USBH_T::HcBulkCurrentED: BCED Position */
+#define USBH_HcBulkCurrentED_BCED_Msk    (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)    /*!< USBH_T::HcBulkCurrentED: BCED Mask     */
+
+#define USBH_HcDoneHead_DH_Pos           (4)                                               /*!< USBH_T::HcDoneHead: DH Position        */
+#define USBH_HcDoneHead_DH_Msk           (0xffffffful << USBH_HcDoneHead_DH_Pos)           /*!< USBH_T::HcDoneHead: DH Mask            */
+
+#define USBH_HcFmInterval_FI_Pos         (0)                                               /*!< USBH_T::HcFmInterval: FI Position      */
+#define USBH_HcFmInterval_FI_Msk         (0x3ffful << USBH_HcFmInterval_FI_Pos)            /*!< USBH_T::HcFmInterval: FI Mask          */
+
+#define USBH_HcFmInterval_FSMPS_Pos      (16)                                              /*!< USBH_T::HcFmInterval: FSMPS Position   */
+#define USBH_HcFmInterval_FSMPS_Msk      (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)         /*!< USBH_T::HcFmInterval: FSMPS Mask       */
+
+#define USBH_HcFmInterval_FIT_Pos        (31)                                              /*!< USBH_T::HcFmInterval: FIT Position     */
+#define USBH_HcFmInterval_FIT_Msk        (0x1ul << USBH_HcFmInterval_FIT_Pos)              /*!< USBH_T::HcFmInterval: FIT Mask         */
+
+#define USBH_HcFmRemaining_FR_Pos        (0)                                               /*!< USBH_T::HcFmRemaining: FR Position     */
+#define USBH_HcFmRemaining_FR_Msk        (0x3ffful << USBH_HcFmRemaining_FR_Pos)           /*!< USBH_T::HcFmRemaining: FR Mask         */
+
+#define USBH_HcFmRemaining_FRT_Pos       (31)                                              /*!< USBH_T::HcFmRemaining: FRT Position    */
+#define USBH_HcFmRemaining_FRT_Msk       (0x1ul << USBH_HcFmRemaining_FRT_Pos)             /*!< USBH_T::HcFmRemaining: FRT Mask        */
+
+#define USBH_HcFmNumber_FN_Pos           (0)                                               /*!< USBH_T::HcFmNumber: FN Position        */
+#define USBH_HcFmNumber_FN_Msk           (0xfffful << USBH_HcFmNumber_FN_Pos)              /*!< USBH_T::HcFmNumber: FN Mask            */
+
+#define USBH_HcPeriodicStart_PS_Pos      (0)                                               /*!< USBH_T::HcPeriodicStart: PS Position   */
+#define USBH_HcPeriodicStart_PS_Msk      (0x3ffful << USBH_HcPeriodicStart_PS_Pos)         /*!< USBH_T::HcPeriodicStart: PS Mask       */
+
+#define USBH_HcLSThreshold_LST_Pos       (0)                                               /*!< USBH_T::HcLSThreshold: LST Position    */
+#define USBH_HcLSThreshold_LST_Msk       (0xffful << USBH_HcLSThreshold_LST_Pos)           /*!< USBH_T::HcLSThreshold: LST Mask        */
+
+#define USBH_HcRhDescriptorA_NDP_Pos     (0)                                               /*!< USBH_T::HcRhDescriptorA: NDP Position  */
+#define USBH_HcRhDescriptorA_NDP_Msk     (0xfful << USBH_HcRhDescriptorA_NDP_Pos)          /*!< USBH_T::HcRhDescriptorA: NDP Mask      */
+
+#define USBH_HcRhDescriptorA_PSM_Pos     (8)                                               /*!< USBH_T::HcRhDescriptorA: PSM Position  */
+#define USBH_HcRhDescriptorA_PSM_Msk     (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)           /*!< USBH_T::HcRhDescriptorA: PSM Mask      */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos    (11)                                              /*!< USBH_T::HcRhDescriptorA: OCPM Position */
+#define USBH_HcRhDescriptorA_OCPM_Msk    (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)          /*!< USBH_T::HcRhDescriptorA: OCPM Mask     */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos    (12)                                              /*!< USBH_T::HcRhDescriptorA: NOCP Position */
+#define USBH_HcRhDescriptorA_NOCP_Msk    (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)          /*!< USBH_T::HcRhDescriptorA: NOCP Mask     */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos    (16)                                              /*!< USBH_T::HcRhDescriptorB: PPCM Position */
+#define USBH_HcRhDescriptorB_PPCM_Msk    (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)       /*!< USBH_T::HcRhDescriptorB: PPCM Mask     */
+
+#define USBH_HcRhStatus_LPS_Pos          (0)                                               /*!< USBH_T::HcRhStatus: LPS Position       */
+#define USBH_HcRhStatus_LPS_Msk          (0x1ul << USBH_HcRhStatus_LPS_Pos)                /*!< USBH_T::HcRhStatus: LPS Mask           */
+
+#define USBH_HcRhStatus_OCI_Pos          (1)                                               /*!< USBH_T::HcRhStatus: OCI Position       */
+#define USBH_HcRhStatus_OCI_Msk          (0x1ul << USBH_HcRhStatus_OCI_Pos)                /*!< USBH_T::HcRhStatus: OCI Mask           */
+
+#define USBH_HcRhStatus_DRWE_Pos         (15)                                              /*!< USBH_T::HcRhStatus: DRWE Position      */
+#define USBH_HcRhStatus_DRWE_Msk         (0x1ul << USBH_HcRhStatus_DRWE_Pos)               /*!< USBH_T::HcRhStatus: DRWE Mask          */
+
+#define USBH_HcRhStatus_LPSC_Pos         (16)                                              /*!< USBH_T::HcRhStatus: LPSC Position      */
+#define USBH_HcRhStatus_LPSC_Msk         (0x1ul << USBH_HcRhStatus_LPSC_Pos)               /*!< USBH_T::HcRhStatus: LPSC Mask          */
+
+#define USBH_HcRhStatus_OCIC_Pos         (17)                                              /*!< USBH_T::HcRhStatus: OCIC Position      */
+#define USBH_HcRhStatus_OCIC_Msk         (0x1ul << USBH_HcRhStatus_OCIC_Pos)               /*!< USBH_T::HcRhStatus: OCIC Mask          */
+
+#define USBH_HcRhStatus_CRWE_Pos         (31)                                              /*!< USBH_T::HcRhStatus: CRWE Position      */
+#define USBH_HcRhStatus_CRWE_Msk         (0x1ul << USBH_HcRhStatus_CRWE_Pos)               /*!< USBH_T::HcRhStatus: CRWE Mask          */
+
+#define USBH_HcRhPortStatus_CCS_Pos      (0)                                               /*!< USBH_T::HcRhPortStatus1: CCS Position  */
+#define USBH_HcRhPortStatus_CCS_Msk      (0x1ul << USBH_HcRhPortStatus_CCS_Pos)            /*!< USBH_T::HcRhPortStatus1: CCS Mask      */
+
+#define USBH_HcRhPortStatus_PES_Pos      (1)                                               /*!< USBH_T::HcRhPortStatus1: PES Position  */
+#define USBH_HcRhPortStatus_PES_Msk      (0x1ul << USBH_HcRhPortStatus_PES_Pos)            /*!< USBH_T::HcRhPortStatus1: PES Mask      */
+
+#define USBH_HcRhPortStatus_PSS_Pos      (2)                                               /*!< USBH_T::HcRhPortStatus1: PSS Position  */
+#define USBH_HcRhPortStatus_PSS_Msk      (0x1ul << USBH_HcRhPortStatus_PSS_Pos)            /*!< USBH_T::HcRhPortStatus1: PSS Mask      */
+
+#define USBH_HcRhPortStatus_POCI_Pos     (3)                                               /*!< USBH_T::HcRhPortStatus1: POCI Position */
+#define USBH_HcRhPortStatus_POCI_Msk     (0x1ul << USBH_HcRhPortStatus_POCI_Pos)           /*!< USBH_T::HcRhPortStatus1: POCI Mask     */
+
+#define USBH_HcRhPortStatus_PRS_Pos      (4)                                               /*!< USBH_T::HcRhPortStatus1: PRS Position  */
+#define USBH_HcRhPortStatus_PRS_Msk      (0x1ul << USBH_HcRhPortStatus_PRS_Pos)            /*!< USBH_T::HcRhPortStatus1: PRS Mask      */
+
+#define USBH_HcRhPortStatus_PPS_Pos      (8)                                               /*!< USBH_T::HcRhPortStatus1: PPS Position  */
+#define USBH_HcRhPortStatus_PPS_Msk      (0x1ul << USBH_HcRhPortStatus_PPS_Pos)            /*!< USBH_T::HcRhPortStatus1: PPS Mask      */
+
+#define USBH_HcRhPortStatus_LSDA_Pos     (9)                                               /*!< USBH_T::HcRhPortStatus1: LSDA Position */
+#define USBH_HcRhPortStatus_LSDA_Msk     (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)           /*!< USBH_T::HcRhPortStatus1: LSDA Mask     */
+
+#define USBH_HcRhPortStatus_CSC_Pos      (16)                                              /*!< USBH_T::HcRhPortStatus1: CSC Position  */
+#define USBH_HcRhPortStatus_CSC_Msk      (0x1ul << USBH_HcRhPortStatus_CSC_Pos)            /*!< USBH_T::HcRhPortStatus1: CSC Mask      */
+
+#define USBH_HcRhPortStatus_PESC_Pos     (17)                                              /*!< USBH_T::HcRhPortStatus1: PESC Position */
+#define USBH_HcRhPortStatus_PESC_Msk     (0x1ul << USBH_HcRhPortStatus_PESC_Pos)           /*!< USBH_T::HcRhPortStatus1: PESC Mask     */
+
+#define USBH_HcRhPortStatus_PSSC_Pos     (18)                                              /*!< USBH_T::HcRhPortStatus1: PSSC Position */
+#define USBH_HcRhPortStatus_PSSC_Msk     (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)           /*!< USBH_T::HcRhPortStatus1: PSSC Mask     */
+
+#define USBH_HcRhPortStatus_OCIC_Pos     (19)                                              /*!< USBH_T::HcRhPortStatus1: OCIC Position */
+#define USBH_HcRhPortStatus_OCIC_Msk     (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)           /*!< USBH_T::HcRhPortStatus1: OCIC Mask     */
+
+#define USBH_HcRhPortStatus_PRSC_Pos     (20)                                              /*!< USBH_T::HcRhPortStatus1: PRSC Position */
+#define USBH_HcRhPortStatus_PRSC_Msk     (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)           /*!< USBH_T::HcRhPortStatus1: PRSC Mask     */
+
+#define USBH_HcPhyControl_STBYEN_Pos     (27)                                              /*!< USBH_T::HcPhyControl: STBYEN Position  */
+#define USBH_HcPhyControl_STBYEN_Msk     (0x1ul << USBH_HcPhyControl_STBYEN_Pos)           /*!< USBH_T::HcPhyControl: STBYEN Mask      */
+
+#define USBH_HcMiscControl_ABORT_Pos     (1)                                               /*!< USBH_T::HcMiscControl: ABORT Position  */
+#define USBH_HcMiscControl_ABORT_Msk     (0x1ul << USBH_HcMiscControl_ABORT_Pos)           /*!< USBH_T::HcMiscControl: ABORT Mask      */
+
+#define USBH_HcMiscControl_OCAL_Pos      (3)                                               /*!< USBH_T::HcMiscControl: OCAL Position   */
+#define USBH_HcMiscControl_OCAL_Msk      (0x1ul << USBH_HcMiscControl_OCAL_Pos)            /*!< USBH_T::HcMiscControl: OCAL Mask       */
+
+#define USBH_HcMiscControl_DPRT1_Pos     (16)                                              /*!< USBH_T::HcMiscControl: DPRT1 Position  */
+#define USBH_HcMiscControl_DPRT1_Msk     (0x1ul << USBH_HcMiscControl_DPRT1_Pos)           /*!< USBH_T::HcMiscControl: DPRT1 Mask      */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+
+
+/*---------------------- HSUSBH USB Host Controller -------------------------*/
+/**
+    @addtogroup HSUSBH Host Controller (UBH20)
+    Memory Mapped Structure for HSUSBH Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var HSUSBH_T::EHCVNR
+     * Offset: 0x00  EHCI Version Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CRLEN     |Capability Registers Length
+     * |        |          |This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
+     * |[31:16] |VERSION   |Host Controller Interface Version Number
+     * |        |          |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
+     * |        |          |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
+     * @var HSUSBH_T::EHCSPR
+     * Offset: 0x04  EHCI Structural Parameters Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |N_PORTS   |Number of Physical Downstream Ports
+     * |        |          |This field specifies the number of physical downstream ports implemented on this host controller
+     * |        |          |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8)
+     * |        |          |Valid values are in the range of 1H to FH.
+     * |        |          |A zero in this field is undefined.
+     * |[4]     |PPC       |Port Power Control
+     * |        |          |This field indicates whether the host controller implementation includes port power control
+     * |        |          |A one in this bit indicates the ports have port power switches
+     * |        |          |A zero in this bit indicates the port do not have port power stitches
+     * |        |          |The value of this field affects the functionality of the Port Power field in each port status and control register.
+     * |[11:8]  |N_PCC     |Number of Ports Per Companion Controller
+     * |        |          |This field indicates the number of ports supported per companion host controller
+     * |        |          |It is used to indicate the port routing configuration to system software.
+     * |        |          |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
+     * |        |          |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
+     * |        |          |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
+     * |        |          |The number in this field must be consistent with N_PORTS and N_CC.
+     * |[15:12] |N_CC      |Number of Companion Controller
+     * |        |          |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
+     * |        |          |A zero in this field indicates there are no companion host controllers
+     * |        |          |Port-ownership hand-off is not supported
+     * |        |          |Only high-speed devices are supported on the host controller root ports.
+     * |        |          |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
+     * |        |          |Port-ownership hand-offs are supported
+     * |        |          |High, Full- and Low-speed devices are supported on the host controller root ports.
+     * @var HSUSBH_T::EHCCPR
+     * Offset: 0x08  EHCI Capability Parameters Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AC64      |64-bit Addressing Capability
+     * |        |          |0 = Data structure using 32-bit address memory pointers.
+     * |[1]     |PFLF      |Programmable Frame List Flag
+     * |        |          |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
+     * |[2]     |ASPC      |Asynchronous Schedule Park Capability
+     * |        |          |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
+     * |[7:4]   |IST       |Isochronous Scheduling Threshold
+     * |        |          |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
+     * |        |          |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
+     * |[15:8]  |EECP      |EHCI Extended Capabilities Pointer (EECP)
+     * |        |          |0 = No extended capabilities are implemented.
+     * @var HSUSBH_T::UCMDR
+     * Offset: 0x20  USB Command Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RUN       |Run/Stop (R/W)
+     * |        |          |When set to a 1, the Host Controller proceeds with execution of the schedule
+     * |        |          |The Host Controller continues execution as long as this bit is set to a 1
+     * |        |          |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
+     * |        |          |The Host Controller must halt within 16 micro-frames after software clears the Run bit
+     * |        |          |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
+     * |        |          |Software must not write a one to this field unless the host controller is in the Halted state (i.e.
+     * |        |          |HCHalted in the USBSTS register is a one)
+     * |        |          |Doing so will yield undefined results.
+     * |        |          |0 = Stop.
+     * |        |          |1 = Run.
+     * |[1]     |HCRST     |Host Controller Reset (HCRESET) (R/W)
+     * |        |          |This control bit is used by software to reset the host controller
+     * |        |          |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
+     * |        |          |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
+     * |        |          |to their initial value
+     * |        |          |Any transaction currently in progress on USB is immediately terminated
+     * |        |          |A USB reset is not driven on downstream ports.
+     * |        |          |All operational registers, including port registers and port state machines are set to their initial values
+     * |        |          |Port ownership reverts to the companion host controller(s), with the side effects
+     * |        |          |Software must reinitialize the host controller in order to return the host controller to an operational state.
+     * |        |          |This bit is set to zero by the Host Controller when the reset process is complete
+     * |        |          |Software cannot terminate the reset process early by writing a zero to this register.
+     * |        |          |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
+     * |        |          |Attempting to reset an actively running host controller will result in undefined behavior.
+     * |[3:2]   |FLSZ      |Frame List Size (R/W or RO)
+     * |        |          |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
+     * |        |          |This field specifies the size of the frame list
+     * |        |          |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
+     * |        |          |Values mean:
+     * |        |          |00 = 1024 elements (4096 bytes) Default value.
+     * |        |          |01 = 512 elements (2048 bytes).
+     * |        |          |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment.
+     * |        |          |11 = Reserved.
+     * |[4]     |PSEN      |Periodic Schedule Enable (R/W)
+     * |        |          |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
+     * |        |          |0 = Do not process the Periodic Schedule.
+     * |        |          |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
+     * |[5]     |ASEN      |Asynchronous Schedule Enable (R/W)
+     * |        |          |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
+     * |        |          |0 = Do not process the Asynchronous Schedule.
+     * |        |          |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
+     * |[6]     |IAAD      |Interrupt on Asynchronous Advance Doorbell (R/W)
+     * |        |          |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
+     * |        |          |Software must write a 1 to this bit to ring the doorbell.
+     * |        |          |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
+     * |        |          |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
+     * |        |          |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
+     * |        |          |Software should not write a one to this bit when the asynchronous schedule is disabled
+     * |        |          |Doing so will yield undefined results.
+     * |[23:16] |ITC       |Interrupt Threshold Control (R/W)
+     * |        |          |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
+     * |        |          |The only valid values are defined below
+     * |        |          |If software writes an invalid value to this register, the results are undefined
+     * |        |          |Value Maximum Interrupt Interval
+     * |        |          |0x00 = Reserved.
+     * |        |          |0x01 = 1 micro-frame.
+     * |        |          |0x02 = 2 micro-frames.
+     * |        |          |0x04 = 4 micro-frames.
+     * |        |          |0x08 = 8 micro-frames (default, equates to 1 ms).
+     * |        |          |0x10 = 16 micro-frames (2 ms).
+     * |        |          |0x20 = 32 micro-frames (4 ms).
+     * |        |          |0x40 = 64 micro-frames (8 ms).
+     * |        |          |Any other value in this register yields undefined results.
+     * |        |          |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
+     * @var HSUSBH_T::USTSR
+     * Offset: 0x24  USB Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBINT    |USB Interrupt (USBINT) (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
+     * |        |          |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
+     * |[1]     |UERRINT   |USB Error Interrupt (USBERRINT) (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
+     * |        |          |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
+     * |[2]     |PCD       |Port Change Detect (R/WC)
+     * |        |          |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
+     * |        |          |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
+     * |        |          |This bit is allowed to be maintained in the Auxiliary power well
+     * |        |          |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
+     * |[3]     |FLR       |Frame List Rollover (R/WC)
+     * |        |          |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
+     * |        |          |The exact value at which the rollover occurs depends on the frame list size
+     * |        |          |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
+     * |        |          |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
+     * |[4]     |HSERR     |Host System Error (R/WC)
+     * |        |          |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
+     * |[5]     |IAA       |Interrupt on Asynchronous Advance (R/WC)
+     * |        |          |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
+     * |        |          |This status bit indicates the assertion of that interrupt source.
+     * |[12]    |HCHalted  |HCHalted (RO)
+     * |        |          |This bit is a zero whenever the Run/Stop bit is a one
+     * |        |          |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
+     * |        |          |internal error).
+     * |[13]    |RECLA     |Reclamation (RO)
+     * |        |          |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
+     * |[14]    |PSS       |Periodic Schedule Status (RO)
+     * |        |          |The bit reports the current real status of the Periodic Schedule
+     * |        |          |If this bit is a zero then the status of the Periodic Schedule is disabled
+     * |        |          |If this bit is a one then the status of the Periodic Schedule is enabled
+     * |        |          |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
+     * |        |          |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
+     * |[15]    |ASS       |Asynchronous Schedule Status (RO)
+     * |        |          |The bit reports the current real status of the Asynchronous Schedule
+     * |        |          |If this bit is a zero then the status of them Asynchronous Schedule is disabled
+     * |        |          |If this bit is a one then the status of the Asynchronous Schedule is enabled
+     * |        |          |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
+     * |        |          |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
+     * @var HSUSBH_T::UIENR
+     * Offset: 0x28  USB Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBIEN    |USB Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the USBINT bit.
+     * |        |          |0 = USB interrupt Disabled.
+     * |        |          |1 = USB interrupt Enabled.
+     * |[1]     |UERRIEN   |USB Error Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the USBERRINT bit.
+     * |        |          |0 = USB Error interrupt Disabled.
+     * |        |          |1 = USB Error interrupt Enabled.
+     * |[2]     |PCIEN     |Port Change Interrupt Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Port Change Detect bit.
+     * |        |          |0 = Port Change interrupt Disabled.
+     * |        |          |1 = Port Change interrupt Enabled.
+     * |[3]     |FLREN     |Frame List Rollover Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
+     * |        |          |0 = Frame List Rollover interrupt Disabled.
+     * |        |          |1 = Frame List Rollover interrupt Enabled.
+     * |[4]     |HSERREN   |Host System Error Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
+     * |        |          |The interrupt is acknowledged by software clearing the Host System Error bit.
+     * |        |          |0 = Host System Error interrupt Disabled.
+     * |        |          |1 = Host System Error interrupt Enabled.
+     * |[5]     |IAAEN     |Interrupt on Asynchronous Advance Enable or Disable Bit
+     * |        |          |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
+     * |        |          |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
+     * |        |          |0 = Interrupt on Asynchronous Advance Disabled.
+     * |        |          |1 = Interrupt on Asynchronous Advance Enabled.
+     * @var HSUSBH_T::UFINDR
+     * Offset: 0x2C  USB Frame Index Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FI        |Frame Index
+     * |        |          |The value in this register increment at the end of each time frame (e.g.
+     * |        |          |micro-frame)
+     * |        |          |Bits [N:3] are used for the Frame List current index
+     * |        |          |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
+     * |        |          |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
+     * |        |          |FLSZ (UCMDR[3:2] Number Elements N
+     * |        |          |0x0 1024 12
+     * |        |          |0x1 512 11
+     * |        |          |0x2 256 10
+     * |        |          |0x3 Reserved
+     * @var HSUSBH_T::UPFLBAR
+     * Offset: 0x34  USB Periodic Frame List Base Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:12] |BADDR     |Base Address
+     * |        |          |These bits correspond to memory address signals [31:12], respectively.
+     * @var HSUSBH_T::UCALAR
+     * Offset: 0x38  USB Current Asynchronous List Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:5]  |LPL       |Link Pointer Low (LPL)
+     * |        |          |These bits correspond to memory address signals [31:5], respectively
+     * |        |          |This field may only reference a Queue Head (QH).
+     * @var HSUSBH_T::UASSTR
+     * Offset: 0x3C  USB Asynchronous Schedule Sleep Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |ASSTMR    |Asynchronous Schedule Sleep Timer
+     * |        |          |This field defines the AsyncSchedSleepTime of EHCI spec.
+     * |        |          |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty.
+     * |        |          |The default value of this timer is 12'hBD6
+     * |        |          |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us.
+     * @var HSUSBH_T::UCFGR
+     * Offset: 0x60  USB Configure Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CF        |Configure Flag (CF)
+     * |        |          |Host software sets this bit as the last action in its process of configuring the Host Controller
+     * |        |          |This bit controls the default port-routing control logic
+     * |        |          |Bit values and side-effects are listed below.
+     * |        |          |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
+     * |        |          |1 = Port routing control logic default-routes all ports to this host controller.
+     * @var HSUSBH_T::UPSCR[2]
+     * Offset: 0x64~0x68  USB Port 0~1 Status and Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCS       |Current Connect Status (RO)
+     * |        |          |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No device is present.
+     * |        |          |1 = Device is present on port.
+     * |[1]     |CSC       |Connect Status Change (R/W)
+     * |        |          |Indicates a change has occurred in the port's Current Connect Status
+     * |        |          |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
+     * |        |          |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No change.
+     * |        |          |1 = Change in Current Connect Status.
+     * |[2]     |PE        |Port Enabled/Disabled (R/W)
+     * |        |          |Ports can only be enabled by the host controller as a part of the reset and enable
+     * |        |          |Software cannot enable a port by writing a one to this field
+     * |        |          |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
+     * |        |          |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
+     * |        |          |Note that the bit status does not change until the port state actually changes
+     * |        |          |There may be a delay in disabling or enabling a port due to other host controller and bus events.
+     * |        |          |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port Disabled.
+     * |        |          |1 = Port Enabled.
+     * |[3]     |PEC       |Port Enable/Disable Change (R/WC)
+     * |        |          |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
+     * |        |          |Software clears this bit by writing a 1 to it.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No change.
+     * |        |          |1 = Port enabled/disabled status has changed.
+     * |[4]     |OCA       |Over-current Active (RO)
+     * |        |          |This bit will automatically transition from a one to a zero when the over current condition is removed.
+     * |        |          |0 = This port does not have an over-current condition.
+     * |        |          |1 = This port currently has an over-current condition.
+     * |[5]     |OCC       |Over-current Change (R/WC)
+     * |        |          |1 = This bit gets set to a one when there is a change to Over-current Active
+     * |        |          |Software clears this bit by writing a one to this bit position.
+     * |[6]     |FPR       |Force Port Resume (R/W)
+     * |        |          |This functionality defined for manipulating this bit depends on the value of the Suspend bit
+     * |        |          |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
+     * |        |          |Software sets this bit to a 1 to drive resume signaling
+     * |        |          |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
+     * |        |          |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
+     * |        |          |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
+     * |        |          |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
+     * |        |          |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
+     * |        |          |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
+     * |        |          |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
+     * |        |          |This bit will remain a one until the port has switched to the high-speed idle
+     * |        |          |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = No resume (K-state) detected/driven on port.
+     * |        |          |1 = Resume detected/driven on port.
+     * |[7]     |SUSPEND   |Suspend (R/W)
+     * |        |          |Port Enabled Bit and Suspend bit of this register define the port states as follows:
+     * |        |          |Port enable is 0 and suspend is 0 = Disable.
+     * |        |          |Port enable is 0 and suspend is 1 = Disable.
+     * |        |          |Port enable is 1 and suspend is 0 = Enable.
+     * |        |          |Port enable is 1 and suspend is 1 = Suspend.
+     * |        |          |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
+     * |        |          |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
+     * |        |          |In the suspend state, the port is sensitive to resume detection
+     * |        |          |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
+     * |        |          |A write of zero to this bit is ignored by the host controller
+     * |        |          |The host controller will unconditionally set this bit to a zero when:
+     * |        |          |Software sets the Force Port Resume bit to a zero (from a one).
+     * |        |          |Software sets the Port Reset bit to a one (from a zero).
+     * |        |          |If host software sets this bit to a one when the port is not enabled (i.e.
+     * |        |          |Port enabled bit is a zero) the results are undefined.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port not in suspend state.
+     * |        |          |1 = Port in suspend state.
+     * |[8]     |PRST      |Port Reset (R/W)
+     * |        |          |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
+     * |        |          |Software writes a zero to this bit to terminate the bus reset sequence
+     * |        |          |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
+     * |        |          |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
+     * |        |          |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
+     * |        |          |The bit status will not read as a zero until after the reset has completed
+     * |        |          |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g.
+     * |        |          |set the Port Enable bit to a one)
+     * |        |          |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
+     * |        |          |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
+     * |        |          |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
+     * |        |          |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
+     * |        |          |This field is zero if Port Power is zero.
+     * |        |          |0 = Port is not in Reset.
+     * |        |          |1 = Port is in Reset.
+     * |[11:10] |LSTS      |Line Status (RO)
+     * |        |          |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
+     * |        |          |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
+     * |        |          |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
+     * |        |          |The encoding of the bits are:
+     * |        |          |Bits[11:10] USB State Interpretation
+     * |        |          |00 = SE0 Not Low-speed device, perform EHCI reset.
+     * |        |          |01 = K-state Low-speed device, release ownership of port.
+     * |        |          |10 = J-state Not Low-speed device, perform EHCI reset.
+     * |        |          |11 = Undefined Not Low-speed device, perform EHCI reset.
+     * |        |          |This value of this field is undefined if Port Power is zero.
+     * |[12]    |PP        |Port Power (PP)
+     * |        |          |Host controller has port power control switches
+     * |        |          |This bit represents the Current setting of the switch (0 = off, 1 = on)
+     * |        |          |When power is not available on a port (i.e.
+     * |        |          |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
+     * |        |          |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
+     * |[13]    |PO        |Port Owner (R/W)
+     * |        |          |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
+     * |        |          |This bit unconditionally goes to 1 whenever the Configured bit is zero.
+     * |        |          |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
+     * |        |          |Software writes a one to this bit when the attached device is not a high-speed device
+     * |        |          |A one in this bit means that a companion host controller owns and controls the port.
+     * |[19:16] |PTC       |Port Test Control (R/W)
+     * |        |          |When this field is zero, the port is NOT operating in a test mode
+     * |        |          |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
+     * |        |          |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
+     * |        |          |Bits Test Mode
+     * |        |          |0x0 = Test mode not enabled.
+     * |        |          |0x1 = Test J_STATE.
+     * |        |          |0x2 = Test K_STATE.
+     * |        |          |0x3 = Test SE0_NAK.
+     * |        |          |0x4 = Test Packet.
+     * |        |          |0x5 = Test FORCE_ENABLE.
+     * @var HSUSBH_T::USBPCR0
+     * Offset: 0xC4  USB PHY 0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8]     |SUSPEND   |Suspend Assertion
+     * |        |          |This bit controls the suspend mode of USB PHY 0.
+     * |        |          |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+     * |        |          |This bit is 1'b0 in default
+     * |        |          |This means the USB PHY 0 is suspended in default
+     * |        |          |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+     * |        |          |0 = USB PHY 0 was suspended.
+     * |        |          |1 = USB PHY 0 was not suspended.
+     * |[11]    |CLKVALID  |UTMI Clock Valid
+     * |        |          |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready
+     * |        |          |S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
+     * |        |          |0 = UTMI clock is not valid.
+     * |        |          |1 = UTMI clock is valid.
+     * @var HSUSBH_T::USBPCR1
+     * Offset: 0xC8  USB PHY 1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8]     |SUSPEND   |Suspend Assertion
+     * |        |          |This bit controls the suspend mode of USB PHY 1.
+     * |        |          |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
+     * |        |          |This bit is 1'b0 in default
+     * |        |          |This means the USB PHY 0 is suspended in default
+     * |        |          |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
+     * |        |          |0 = USB PHY 1 was suspended.
+     * |        |          |1 = USB PHY 1 was not suspended.
+     */
+    __I  uint32_t EHCVNR;                /*!< [0x0000] EHCI Version Number Register                                     */
+    __I  uint32_t EHCSPR;                /*!< [0x0004] EHCI Structural Parameters Register                              */
+    __I  uint32_t EHCCPR;                /*!< [0x0008] EHCI Capability Parameters Register                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t UCMDR;                 /*!< [0x0020] USB Command Register                                             */
+    __IO uint32_t USTSR;                 /*!< [0x0024] USB Status Register                                              */
+    __IO uint32_t UIENR;                 /*!< [0x0028] USB Interrupt Enable Register                                    */
+    __IO uint32_t UFINDR;                /*!< [0x002c] USB Frame Index Register                                         */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t UPFLBAR;               /*!< [0x0034] USB Periodic Frame List Base Address Register                    */
+    __IO uint32_t UCALAR;                /*!< [0x0038] USB Current Asynchronous List Address Register                   */
+    __IO uint32_t UASSTR;                /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register                   */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t UCFGR;                 /*!< [0x0060] USB Configure Flag Register                                      */
+    __IO uint32_t UPSCR[2];              /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register                           */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[22];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t USBPCR0;               /*!< [0x00c4] USB PHY 0 Control Register                                       */
+    __IO uint32_t USBPCR1;               /*!< [0x00c8] USB PHY 1 Control Register                                       */
+
+} HSUSBH_T;
+
+/**
+    @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
+    Constant Definitions for HSUSBH Controller
+@{ */
+
+#define HSUSBH_EHCVNR_CRLEN_Pos          (0)                                               /*!< HSUSBH_T::EHCVNR: CRLEN Position       */
+#define HSUSBH_EHCVNR_CRLEN_Msk          (0xfful << HSUSBH_EHCVNR_CRLEN_Pos)               /*!< HSUSBH_T::EHCVNR: CRLEN Mask           */
+
+#define HSUSBH_EHCVNR_VERSION_Pos        (16)                                              /*!< HSUSBH_T::EHCVNR: VERSION Position     */
+#define HSUSBH_EHCVNR_VERSION_Msk        (0xfffful << HSUSBH_EHCVNR_VERSION_Pos)           /*!< HSUSBH_T::EHCVNR: VERSION Mask         */
+
+#define HSUSBH_EHCSPR_N_PORTS_Pos        (0)                                               /*!< HSUSBH_T::EHCSPR: N_PORTS Position     */
+#define HSUSBH_EHCSPR_N_PORTS_Msk        (0xful << HSUSBH_EHCSPR_N_PORTS_Pos)              /*!< HSUSBH_T::EHCSPR: N_PORTS Mask         */
+
+#define HSUSBH_EHCSPR_PPC_Pos            (4)                                               /*!< HSUSBH_T::EHCSPR: PPC Position         */
+#define HSUSBH_EHCSPR_PPC_Msk            (0x1ul << HSUSBH_EHCSPR_PPC_Pos)                  /*!< HSUSBH_T::EHCSPR: PPC Mask             */
+
+#define HSUSBH_EHCSPR_N_PCC_Pos          (8)                                               /*!< HSUSBH_T::EHCSPR: N_PCC Position       */
+#define HSUSBH_EHCSPR_N_PCC_Msk          (0xful << HSUSBH_EHCSPR_N_PCC_Pos)                /*!< HSUSBH_T::EHCSPR: N_PCC Mask           */
+
+#define HSUSBH_EHCSPR_N_CC_Pos           (12)                                              /*!< HSUSBH_T::EHCSPR: N_CC Position        */
+#define HSUSBH_EHCSPR_N_CC_Msk           (0xful << HSUSBH_EHCSPR_N_CC_Pos)                 /*!< HSUSBH_T::EHCSPR: N_CC Mask            */
+
+#define HSUSBH_EHCCPR_AC64_Pos           (0)                                               /*!< HSUSBH_T::EHCCPR: AC64 Position        */
+#define HSUSBH_EHCCPR_AC64_Msk           (0x1ul << HSUSBH_EHCCPR_AC64_Pos)                 /*!< HSUSBH_T::EHCCPR: AC64 Mask            */
+
+#define HSUSBH_EHCCPR_PFLF_Pos           (1)                                               /*!< HSUSBH_T::EHCCPR: PFLF Position        */
+#define HSUSBH_EHCCPR_PFLF_Msk           (0x1ul << HSUSBH_EHCCPR_PFLF_Pos)                 /*!< HSUSBH_T::EHCCPR: PFLF Mask            */
+
+#define HSUSBH_EHCCPR_ASPC_Pos           (2)                                               /*!< HSUSBH_T::EHCCPR: ASPC Position        */
+#define HSUSBH_EHCCPR_ASPC_Msk           (0x1ul << HSUSBH_EHCCPR_ASPC_Pos)                 /*!< HSUSBH_T::EHCCPR: ASPC Mask            */
+
+#define HSUSBH_EHCCPR_IST_Pos            (4)                                               /*!< HSUSBH_T::EHCCPR: IST Position         */
+#define HSUSBH_EHCCPR_IST_Msk            (0xful << HSUSBH_EHCCPR_IST_Pos)                  /*!< HSUSBH_T::EHCCPR: IST Mask             */
+
+#define HSUSBH_EHCCPR_EECP_Pos           (8)                                               /*!< HSUSBH_T::EHCCPR: EECP Position        */
+#define HSUSBH_EHCCPR_EECP_Msk           (0xfful << HSUSBH_EHCCPR_EECP_Pos)                /*!< HSUSBH_T::EHCCPR: EECP Mask            */
+
+#define HSUSBH_UCMDR_RUN_Pos             (0)                                               /*!< HSUSBH_T::UCMDR: RUN Position          */
+#define HSUSBH_UCMDR_RUN_Msk             (0x1ul << HSUSBH_UCMDR_RUN_Pos)                   /*!< HSUSBH_T::UCMDR: RUN Mask              */
+
+#define HSUSBH_UCMDR_HCRST_Pos           (1)                                               /*!< HSUSBH_T::UCMDR: HCRST Position        */
+#define HSUSBH_UCMDR_HCRST_Msk           (0x1ul << HSUSBH_UCMDR_HCRST_Pos)                 /*!< HSUSBH_T::UCMDR: HCRST Mask            */
+
+#define HSUSBH_UCMDR_FLSZ_Pos            (2)                                               /*!< HSUSBH_T::UCMDR: FLSZ Position         */
+#define HSUSBH_UCMDR_FLSZ_Msk            (0x3ul << HSUSBH_UCMDR_FLSZ_Pos)                  /*!< HSUSBH_T::UCMDR: FLSZ Mask             */
+
+#define HSUSBH_UCMDR_PSEN_Pos            (4)                                               /*!< HSUSBH_T::UCMDR: PSEN Position         */
+#define HSUSBH_UCMDR_PSEN_Msk            (0x1ul << HSUSBH_UCMDR_PSEN_Pos)                  /*!< HSUSBH_T::UCMDR: PSEN Mask             */
+
+#define HSUSBH_UCMDR_ASEN_Pos            (5)                                               /*!< HSUSBH_T::UCMDR: ASEN Position         */
+#define HSUSBH_UCMDR_ASEN_Msk            (0x1ul << HSUSBH_UCMDR_ASEN_Pos)                  /*!< HSUSBH_T::UCMDR: ASEN Mask             */
+
+#define HSUSBH_UCMDR_IAAD_Pos            (6)                                               /*!< HSUSBH_T::UCMDR: IAAD Position         */
+#define HSUSBH_UCMDR_IAAD_Msk            (0x1ul << HSUSBH_UCMDR_IAAD_Pos)                  /*!< HSUSBH_T::UCMDR: IAAD Mask             */
+
+#define HSUSBH_UCMDR_ITC_Pos             (16)                                              /*!< HSUSBH_T::UCMDR: ITC Position          */
+#define HSUSBH_UCMDR_ITC_Msk             (0xfful << HSUSBH_UCMDR_ITC_Pos)                  /*!< HSUSBH_T::UCMDR: ITC Mask              */
+
+#define HSUSBH_USTSR_USBINT_Pos          (0)                                               /*!< HSUSBH_T::USTSR: USBINT Position       */
+#define HSUSBH_USTSR_USBINT_Msk          (0x1ul << HSUSBH_USTSR_USBINT_Pos)                /*!< HSUSBH_T::USTSR: USBINT Mask           */
+
+#define HSUSBH_USTSR_UERRINT_Pos         (1)                                               /*!< HSUSBH_T::USTSR: UERRINT Position      */
+#define HSUSBH_USTSR_UERRINT_Msk         (0x1ul << HSUSBH_USTSR_UERRINT_Pos)               /*!< HSUSBH_T::USTSR: UERRINT Mask          */
+
+#define HSUSBH_USTSR_PCD_Pos             (2)                                               /*!< HSUSBH_T::USTSR: PCD Position          */
+#define HSUSBH_USTSR_PCD_Msk             (0x1ul << HSUSBH_USTSR_PCD_Pos)                   /*!< HSUSBH_T::USTSR: PCD Mask              */
+
+#define HSUSBH_USTSR_FLR_Pos             (3)                                               /*!< HSUSBH_T::USTSR: FLR Position          */
+#define HSUSBH_USTSR_FLR_Msk             (0x1ul << HSUSBH_USTSR_FLR_Pos)                   /*!< HSUSBH_T::USTSR: FLR Mask              */
+
+#define HSUSBH_USTSR_HSERR_Pos           (4)                                               /*!< HSUSBH_T::USTSR: HSERR Position        */
+#define HSUSBH_USTSR_HSERR_Msk           (0x1ul << HSUSBH_USTSR_HSERR_Pos)                 /*!< HSUSBH_T::USTSR: HSERR Mask            */
+
+#define HSUSBH_USTSR_IAA_Pos             (5)                                               /*!< HSUSBH_T::USTSR: IAA Position          */
+#define HSUSBH_USTSR_IAA_Msk             (0x1ul << HSUSBH_USTSR_IAA_Pos)                   /*!< HSUSBH_T::USTSR: IAA Mask              */
+
+#define HSUSBH_USTSR_HCHalted_Pos        (12)                                              /*!< HSUSBH_T::USTSR: HCHalted Position     */
+#define HSUSBH_USTSR_HCHalted_Msk        (0x1ul << HSUSBH_USTSR_HCHalted_Pos)              /*!< HSUSBH_T::USTSR: HCHalted Mask         */
+
+#define HSUSBH_USTSR_RECLA_Pos           (13)                                              /*!< HSUSBH_T::USTSR: RECLA Position        */
+#define HSUSBH_USTSR_RECLA_Msk           (0x1ul << HSUSBH_USTSR_RECLA_Pos)                 /*!< HSUSBH_T::USTSR: RECLA Mask            */
+
+#define HSUSBH_USTSR_PSS_Pos             (14)                                              /*!< HSUSBH_T::USTSR: PSS Position          */
+#define HSUSBH_USTSR_PSS_Msk             (0x1ul << HSUSBH_USTSR_PSS_Pos)                   /*!< HSUSBH_T::USTSR: PSS Mask              */
+
+#define HSUSBH_USTSR_ASS_Pos             (15)                                              /*!< HSUSBH_T::USTSR: ASS Position          */
+#define HSUSBH_USTSR_ASS_Msk             (0x1ul << HSUSBH_USTSR_ASS_Pos)                   /*!< HSUSBH_T::USTSR: ASS Mask              */
+
+#define HSUSBH_UIENR_USBIEN_Pos          (0)                                               /*!< HSUSBH_T::UIENR: USBIEN Position       */
+#define HSUSBH_UIENR_USBIEN_Msk          (0x1ul << HSUSBH_UIENR_USBIEN_Pos)                /*!< HSUSBH_T::UIENR: USBIEN Mask           */
+
+#define HSUSBH_UIENR_UERRIEN_Pos         (1)                                               /*!< HSUSBH_T::UIENR: UERRIEN Position      */
+#define HSUSBH_UIENR_UERRIEN_Msk         (0x1ul << HSUSBH_UIENR_UERRIEN_Pos)               /*!< HSUSBH_T::UIENR: UERRIEN Mask          */
+
+#define HSUSBH_UIENR_PCIEN_Pos           (2)                                               /*!< HSUSBH_T::UIENR: PCIEN Position        */
+#define HSUSBH_UIENR_PCIEN_Msk           (0x1ul << HSUSBH_UIENR_PCIEN_Pos)                 /*!< HSUSBH_T::UIENR: PCIEN Mask            */
+
+#define HSUSBH_UIENR_FLREN_Pos           (3)                                               /*!< HSUSBH_T::UIENR: FLREN Position        */
+#define HSUSBH_UIENR_FLREN_Msk           (0x1ul << HSUSBH_UIENR_FLREN_Pos)                 /*!< HSUSBH_T::UIENR: FLREN Mask            */
+
+#define HSUSBH_UIENR_HSERREN_Pos         (4)                                               /*!< HSUSBH_T::UIENR: HSERREN Position      */
+#define HSUSBH_UIENR_HSERREN_Msk         (0x1ul << HSUSBH_UIENR_HSERREN_Pos)               /*!< HSUSBH_T::UIENR: HSERREN Mask          */
+
+#define HSUSBH_UIENR_IAAEN_Pos           (5)                                               /*!< HSUSBH_T::UIENR: IAAEN Position        */
+#define HSUSBH_UIENR_IAAEN_Msk           (0x1ul << HSUSBH_UIENR_IAAEN_Pos)                 /*!< HSUSBH_T::UIENR: IAAEN Mask            */
+
+#define HSUSBH_UFINDR_FI_Pos             (0)                                               /*!< HSUSBH_T::UFINDR: FI Position          */
+#define HSUSBH_UFINDR_FI_Msk             (0x3ffful << HSUSBH_UFINDR_FI_Pos)                /*!< HSUSBH_T::UFINDR: FI Mask              */
+
+#define HSUSBH_UPFLBAR_BADDR_Pos         (12)                                              /*!< HSUSBH_T::UPFLBAR: BADDR Position      */
+#define HSUSBH_UPFLBAR_BADDR_Msk         (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos)           /*!< HSUSBH_T::UPFLBAR: BADDR Mask          */
+
+#define HSUSBH_UCALAR_LPL_Pos            (5)                                               /*!< HSUSBH_T::UCALAR: LPL Position         */
+#define HSUSBH_UCALAR_LPL_Msk            (0x7fffffful << HSUSBH_UCALAR_LPL_Pos)            /*!< HSUSBH_T::UCALAR: LPL Mask             */
+
+#define HSUSBH_UASSTR_ASSTMR_Pos         (0)                                               /*!< HSUSBH_T::UASSTR: ASSTMR Position      */
+#define HSUSBH_UASSTR_ASSTMR_Msk         (0xffful << HSUSBH_UASSTR_ASSTMR_Pos)             /*!< HSUSBH_T::UASSTR: ASSTMR Mask          */
+
+#define HSUSBH_UCFGR_CF_Pos              (0)                                               /*!< HSUSBH_T::UCFGR: CF Position           */
+#define HSUSBH_UCFGR_CF_Msk              (0x1ul << HSUSBH_UCFGR_CF_Pos)                    /*!< HSUSBH_T::UCFGR: CF Mask               */
+
+#define HSUSBH_UPSCR_CCS_Pos             (0)                                               /*!< HSUSBH_T::UPSCR[2]: CCS Position       */
+#define HSUSBH_UPSCR_CCS_Msk             (0x1ul << HSUSBH_UPSCR_CCS_Pos)                   /*!< HSUSBH_T::UPSCR[2]: CCS Mask           */
+
+#define HSUSBH_UPSCR_CSC_Pos             (1)                                               /*!< HSUSBH_T::UPSCR[2]: CSC Position       */
+#define HSUSBH_UPSCR_CSC_Msk             (0x1ul << HSUSBH_UPSCR_CSC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: CSC Mask           */
+
+#define HSUSBH_UPSCR_PE_Pos              (2)                                               /*!< HSUSBH_T::UPSCR[2]: PE Position        */
+#define HSUSBH_UPSCR_PE_Msk              (0x1ul << HSUSBH_UPSCR_PE_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PE Mask            */
+
+#define HSUSBH_UPSCR_PEC_Pos             (3)                                               /*!< HSUSBH_T::UPSCR[2]: PEC Position       */
+#define HSUSBH_UPSCR_PEC_Msk             (0x1ul << HSUSBH_UPSCR_PEC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: PEC Mask           */
+
+#define HSUSBH_UPSCR_OCA_Pos             (4)                                               /*!< HSUSBH_T::UPSCR[2]: OCA Position       */
+#define HSUSBH_UPSCR_OCA_Msk             (0x1ul << HSUSBH_UPSCR_OCA_Pos)                   /*!< HSUSBH_T::UPSCR[2]: OCA Mask           */
+
+#define HSUSBH_UPSCR_OCC_Pos             (5)                                               /*!< HSUSBH_T::UPSCR[2]: OCC Position       */
+#define HSUSBH_UPSCR_OCC_Msk             (0x1ul << HSUSBH_UPSCR_OCC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: OCC Mask           */
+
+#define HSUSBH_UPSCR_FPR_Pos             (6)                                               /*!< HSUSBH_T::UPSCR[2]: FPR Position       */
+#define HSUSBH_UPSCR_FPR_Msk             (0x1ul << HSUSBH_UPSCR_FPR_Pos)                   /*!< HSUSBH_T::UPSCR[2]: FPR Mask           */
+
+#define HSUSBH_UPSCR_SUSPEND_Pos         (7)                                               /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position   */
+#define HSUSBH_UPSCR_SUSPEND_Msk         (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos)               /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask       */
+
+#define HSUSBH_UPSCR_PRST_Pos            (8)                                               /*!< HSUSBH_T::UPSCR[2]: PRST Position      */
+#define HSUSBH_UPSCR_PRST_Msk            (0x1ul << HSUSBH_UPSCR_PRST_Pos)                  /*!< HSUSBH_T::UPSCR[2]: PRST Mask          */
+
+#define HSUSBH_UPSCR_LSTS_Pos            (10)                                              /*!< HSUSBH_T::UPSCR[2]: LSTS Position      */
+#define HSUSBH_UPSCR_LSTS_Msk            (0x3ul << HSUSBH_UPSCR_LSTS_Pos)                  /*!< HSUSBH_T::UPSCR[2]: LSTS Mask          */
+
+#define HSUSBH_UPSCR_PP_Pos              (12)                                              /*!< HSUSBH_T::UPSCR[2]: PP Position        */
+#define HSUSBH_UPSCR_PP_Msk              (0x1ul << HSUSBH_UPSCR_PP_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PP Mask            */
+
+#define HSUSBH_UPSCR_PO_Pos              (13)                                              /*!< HSUSBH_T::UPSCR[2]: PO Position        */
+#define HSUSBH_UPSCR_PO_Msk              (0x1ul << HSUSBH_UPSCR_PO_Pos)                    /*!< HSUSBH_T::UPSCR[2]: PO Mask            */
+
+#define HSUSBH_UPSCR_PTC_Pos             (16)                                              /*!< HSUSBH_T::UPSCR[2]: PTC Position       */
+#define HSUSBH_UPSCR_PTC_Msk             (0xful << HSUSBH_UPSCR_PTC_Pos)                   /*!< HSUSBH_T::UPSCR[2]: PTC Mask           */
+
+#define HSUSBH_USBPCR0_SUSPEND_Pos       (8)                                               /*!< HSUSBH_T::USBPCR0: SUSPEND Position    */
+#define HSUSBH_USBPCR0_SUSPEND_Msk       (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos)             /*!< HSUSBH_T::USBPCR0: SUSPEND Mask        */
+
+#define HSUSBH_USBPCR0_CLKVALID_Pos      (11)                                              /*!< HSUSBH_T::USBPCR0: CLKVALID Position   */
+#define HSUSBH_USBPCR0_CLKVALID_Msk      (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos)            /*!< HSUSBH_T::USBPCR0: CLKVALID Mask       */
+
+#define HSUSBH_USBPCR1_SUSPEND_Pos       (8)                                               /*!< HSUSBH_T::USBPCR1: SUSPEND Position    */
+#define HSUSBH_USBPCR1_SUSPEND_Msk       (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos)             /*!< HSUSBH_T::USBPCR1: SUSPEND Mask        */
+
+/**@}*/ /* HSUSBH_CONST */
+/**@}*/ /* end of HSUSBH register group */
+
+
+/*---------------------- USB On-The-Go Controller -------------------------*/
+/**
+    @addtogroup OTG USB On-The-Go Controller(OTG)
+    Memory Mapped Structure for OTG Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var OTG_T::CTL
+     * Offset: 0x00  OTG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDROP  |Drop VBUS Control
+     * |        |          |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+     * |        |          |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+     * |        |          |0 = Not drop the VBUS.
+     * |        |          |1 = Drop the VBUS.
+     * |[1]     |BUSREQ    |OTG Bus Request
+     * |        |          |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+     * |        |          |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+     * |        |          |This bit will be cleared when A-device goes to A_wait_vfall state
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+     * |        |          |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+     * |        |          |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+     * |[2]     |HNPREQEN  |OTG HNP Request Enable Bit
+     * |        |          |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+     * |        |          |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+     * |        |          |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+     * |        |          |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+     * |        |          |0 = HNP request Disabled.
+     * |        |          |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+     * |        |          |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+     * |[4]     |OTGEN     |OTG Function Enable Bit
+     * |        |          |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+     * |        |          |When USB frame not configured as OTG device, this bit is must be low.
+     * |        |          |0= OTG function Disabled.
+     * |        |          |1 = OTG function Enabled.
+     * |[5]     |WKEN      |OTG ID Pin Wake-up Enable Bit
+     * |        |          |0 = OTG ID pin status change wake-up function Disabled.
+     * |        |          |1 = OTG ID pin status change wake-up function Enabled.
+     * @var OTG_T::PHYCTL
+     * Offset: 0x04  OTG PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OTGPHYEN  |OTG PHY Enable
+     * |        |          |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
+     * |        |          |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
+     * |        |          |0 = OTG PHY Disabled.
+     * |        |          |1 = OTG PHY Enabled.
+     * |[1]     |IDDETEN   |ID Detection Enable Bit
+     * |        |          |0 = Detect ID pin status Disabled.
+     * |        |          |1 = Detect ID pin status Enabled.
+     * |[4]     |VBENPOL   |Off-chip USB VBUS Power Switch Enable Polarity
+     * |        |          |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+     * |        |          |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+     * |        |          |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The off-chip USB VBUS power switch enable is active high.
+     * |        |          |1 = The off-chip USB VBUS power switch enable is active low.
+     * |[5]     |VBSTSPOL  |Off-chip USB VBUS Power Switch Status Polarity
+     * |        |          |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+     * |        |          |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+     * |        |          |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+     * @var OTG_T::INTEN
+     * Offset: 0x08  OTG Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[1]     |VBEIEN    |VBUS Error Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+     * |[2]     |SRPFIEN   |SRP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[3]     |HNPFIEN   |HNP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[4]     |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Going to idle state means going to a_idle or b_idle state
+     * |        |          |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+     * |[5]     |IDCHGIEN  |IDSTS Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[6]     |PDEVIEN   |Act As Peripheral Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+     * |        |          |0 = This device as a peripheral interrupt Disabled.
+     * |        |          |1 = This device as a peripheral interrupt Enabled.
+     * |[7]     |HOSTIEN   |Act As Host Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+     * |        |          |0 = This device as a host interrupt Disabled.
+     * |        |          |1 = This device as a host interrupt Enabled.
+     * |[8]     |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[9]     |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[10]    |VBCHGIEN  |VBUSVLD Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[11]    |SECHGIEN  |SESSEND Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[13]    |SRPDETIEN |SRP Detected Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * @var OTG_T::INTSTS
+     * Offset: 0x0C  OTG Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIF |OTG Role Change Interrupt Status
+     * |        |          |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+     * |        |          |0 = OTG device role not changed.
+     * |        |          |1 = OTG device role changed.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[1]     |VBEIF     |VBUS Error Interrupt Status
+     * |        |          |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+     * |        |          |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+     * |        |          |Note: Write 1 to clear this flag and recover from the VBUS error state.
+     * |[2]     |SRPFIF    |SRP Fail Interrupt Status
+     * |        |          |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+     * |        |          |This flag is set when the OTG B-device does not get VBUS high after this interval.
+     * |        |          |0 = OTG B-device gets VBUS high before this interval.
+     * |        |          |1 = OTG B-device does not get VBUS high before this interval.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[3]     |HNPFIF    |HNP Fail Interrupt Status
+     * |        |          |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+     * |        |          |0 = A-device connects to B-device before specified interval expires.
+     * |        |          |1 = A-device does not connect to B-device before specified interval expires.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[4]     |GOIDLEIF  |OTG Device Goes to IDLE Interrupt Status
+     * |        |          |Flag is set if the OTG device transfers from non-idle state to idle state
+     * |        |          |The OTG device will be neither a host nor a peripheral.
+     * |        |          |0 = OTG device does not go back to idle state (a_idle or b_idle).
+     * |        |          |1 = OTG device goes back to idle state(a_idle or b_idle).
+     * |        |          |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+     * |        |          |Note 2: Write 1 to clear this flag.
+     * |[5]     |IDCHGIF   |ID State Change Interrupt Status
+     * |        |          |0 = IDSTS (OTG_STATUS[1]) not toggled.
+     * |        |          |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[6]     |PDEVIF    |Act As Peripheral Interrupt Status
+     * |        |          |0= This device does not act as a peripheral.
+     * |        |          |1 = This device acts as a peripheral.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[7]     |HOSTIF    |Act As Host Interrupt Status
+     * |        |          |0= This device does not act as a host.
+     * |        |          |1 = This device acts as a host.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[8]     |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+     * |        |          |0 = BVLD (OTG_STATUS[3]) is not toggled.
+     * |        |          |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[9]     |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+     * |        |          |0 = AVLD (OTG_STATUS[4]) not toggled.
+     * |        |          |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[10]    |VBCHGIF   |VBUSVLD State Change Interrupt Status
+     * |        |          |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+     * |        |          |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[11]    |SECHGIF   |SESSEND State Change Interrupt Status
+     * |        |          |0 = SESSEND (OTG_STATUS[2]) not toggled.
+     * |        |          |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[13]    |SRPDETIF  |SRP Detected Interrupt Status
+     * |        |          |0 = SRP not detected.
+     * |        |          |1 = SRP detected.
+     * |        |          |Note: Write 1 to clear this status.
+     * @var OTG_T::STATUS
+     * Offset: 0x10  OTG Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OVERCUR   |over Current Condition
+     * |        |          |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS successfully.
+     * |        |          |1 = OTG A-device cannot drives VBUS high in this interval.
+     * |[1]     |IDSTS     |USB_ID Pin State of Mini-b/Micro-plug
+     * |        |          |0 = Mini-A/Micro-A plug is attached.
+     * |        |          |1 = Mini-B/Micro-B plug is attached.
+     * |[2]     |SESSEND   |Session End Status
+     * |        |          |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+     * |        |          |Session end means no meaningful power on VBUS.
+     * |        |          |0 = Session is not end.
+     * |        |          |1 = Session is end.
+     * |[3]     |BVLD      |B-device Session Valid Status
+     * |        |          |0 = B-device session is not valid.
+     * |        |          |1 = B-device session is valid.
+     * |[4]     |AVLD      |A-device Session Valid Status
+     * |        |          |0 = A-device session is not valid.
+     * |        |          |1 = A-device session is valid.
+     * |[5]     |VBUSVLD   |VBUS Valid Status
+     * |        |          |When VBUS is larger than 4.7V, this bit will be set to 1.
+     * |        |          |0 = VBUS is not valid.
+     * |        |          |1 = VBUS is valid.
+     * |[6]     |ASPERI    |As Peripheral Status
+     * |        |          |When OTG as peripheral, this bit is set.
+     * |        |          |0: OTG not as peripheral
+     * |        |          |1: OTG as peripheral
+     * |[7]     |ASHOST    |As Host Status
+     * |        |          |When OTG as Host, this bit is set.
+     * |        |          |0: OTG not as Host
+     * |        |          |1: OTG as Host
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] OTG Control Register                                             */
+    __IO uint32_t PHYCTL;                /*!< [0x0004] OTG PHY Control Register                                         */
+    __IO uint32_t INTEN;                 /*!< [0x0008] OTG Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x000c] OTG Interrupt Status Register                                    */
+    __I  uint32_t STATUS;                /*!< [0x0010] OTG Status Register                                              */
+
+} OTG_T;
+
+
+/**
+    @addtogroup OTG_CONST OTG Bit Field Definition
+    Constant Definitions for OTG Controller
+@{ */
+
+#define OTG_CTL_VBUSDROP_Pos             (0)                                               /*!< OTG_T::CTL: VBUSDROP Position          */
+#define OTG_CTL_VBUSDROP_Msk             (0x1ul << OTG_CTL_VBUSDROP_Pos)                   /*!< OTG_T::CTL: VBUSDROP Mask              */
+
+#define OTG_CTL_BUSREQ_Pos               (1)                                               /*!< OTG_T::CTL: BUSREQ Position            */
+#define OTG_CTL_BUSREQ_Msk               (0x1ul << OTG_CTL_BUSREQ_Pos)                     /*!< OTG_T::CTL: BUSREQ Mask                */
+
+#define OTG_CTL_HNPREQEN_Pos             (2)                                               /*!< OTG_T::CTL: HNPREQEN Position          */
+#define OTG_CTL_HNPREQEN_Msk             (0x1ul << OTG_CTL_HNPREQEN_Pos)                   /*!< OTG_T::CTL: HNPREQEN Mask              */
+
+#define OTG_CTL_OTGEN_Pos                (4)                                               /*!< OTG_T::CTL: OTGEN Position             */
+#define OTG_CTL_OTGEN_Msk                (0x1ul << OTG_CTL_OTGEN_Pos)                      /*!< OTG_T::CTL: OTGEN Mask                 */
+
+#define OTG_CTL_WKEN_Pos                 (5)                                               /*!< OTG_T::CTL: WKEN Position              */
+#define OTG_CTL_WKEN_Msk                 (0x1ul << OTG_CTL_WKEN_Pos)                       /*!< OTG_T::CTL: WKEN Mask                  */
+
+#define OTG_PHYCTL_OTGPHYEN_Pos          (0)                                               /*!< OTG_T::PHYCTL: OTGPHYEN Position       */
+#define OTG_PHYCTL_OTGPHYEN_Msk          (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos)                /*!< OTG_T::PHYCTL: OTGPHYEN Mask           */
+
+#define OTG_PHYCTL_IDDETEN_Pos           (1)                                               /*!< OTG_T::PHYCTL: IDDETEN Position        */
+#define OTG_PHYCTL_IDDETEN_Msk           (0x1ul << OTG_PHYCTL_IDDETEN_Pos)                 /*!< OTG_T::PHYCTL: IDDETEN Mask            */
+
+#define OTG_PHYCTL_VBENPOL_Pos           (4)                                               /*!< OTG_T::PHYCTL: VBENPOL Position        */
+#define OTG_PHYCTL_VBENPOL_Msk           (0x1ul << OTG_PHYCTL_VBENPOL_Pos)                 /*!< OTG_T::PHYCTL: VBENPOL Mask            */
+
+#define OTG_PHYCTL_VBSTSPOL_Pos          (5)                                               /*!< OTG_T::PHYCTL: VBSTSPOL Position       */
+#define OTG_PHYCTL_VBSTSPOL_Msk          (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos)                /*!< OTG_T::PHYCTL: VBSTSPOL Mask           */
+
+#define OTG_INTEN_ROLECHGIEN_Pos         (0)                                               /*!< OTG_T::INTEN: ROLECHGIEN Position      */
+#define OTG_INTEN_ROLECHGIEN_Msk         (0x1ul << OTG_INTEN_ROLECHGIEN_Pos)               /*!< OTG_T::INTEN: ROLECHGIEN Mask          */
+
+#define OTG_INTEN_VBEIEN_Pos             (1)                                               /*!< OTG_T::INTEN: VBEIEN Position          */
+#define OTG_INTEN_VBEIEN_Msk             (0x1ul << OTG_INTEN_VBEIEN_Pos)                   /*!< OTG_T::INTEN: VBEIEN Mask              */
+
+#define OTG_INTEN_SRPFIEN_Pos            (2)                                               /*!< OTG_T::INTEN: SRPFIEN Position         */
+#define OTG_INTEN_SRPFIEN_Msk            (0x1ul << OTG_INTEN_SRPFIEN_Pos)                  /*!< OTG_T::INTEN: SRPFIEN Mask             */
+
+#define OTG_INTEN_HNPFIEN_Pos            (3)                                               /*!< OTG_T::INTEN: HNPFIEN Position         */
+#define OTG_INTEN_HNPFIEN_Msk            (0x1ul << OTG_INTEN_HNPFIEN_Pos)                  /*!< OTG_T::INTEN: HNPFIEN Mask             */
+
+#define OTG_INTEN_GOIDLEIEN_Pos          (4)                                               /*!< OTG_T::INTEN: GOIDLEIEN Position       */
+#define OTG_INTEN_GOIDLEIEN_Msk          (0x1ul << OTG_INTEN_GOIDLEIEN_Pos)                /*!< OTG_T::INTEN: GOIDLEIEN Mask           */
+
+#define OTG_INTEN_IDCHGIEN_Pos           (5)                                               /*!< OTG_T::INTEN: IDCHGIEN Position        */
+#define OTG_INTEN_IDCHGIEN_Msk           (0x1ul << OTG_INTEN_IDCHGIEN_Pos)                 /*!< OTG_T::INTEN: IDCHGIEN Mask            */
+
+#define OTG_INTEN_PDEVIEN_Pos            (6)                                               /*!< OTG_T::INTEN: PDEVIEN Position         */
+#define OTG_INTEN_PDEVIEN_Msk            (0x1ul << OTG_INTEN_PDEVIEN_Pos)                  /*!< OTG_T::INTEN: PDEVIEN Mask             */
+
+#define OTG_INTEN_HOSTIEN_Pos            (7)                                               /*!< OTG_T::INTEN: HOSTIEN Position         */
+#define OTG_INTEN_HOSTIEN_Msk            (0x1ul << OTG_INTEN_HOSTIEN_Pos)                  /*!< OTG_T::INTEN: HOSTIEN Mask             */
+
+#define OTG_INTEN_BVLDCHGIEN_Pos         (8)                                               /*!< OTG_T::INTEN: BVLDCHGIEN Position      */
+#define OTG_INTEN_BVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: BVLDCHGIEN Mask          */
+
+#define OTG_INTEN_AVLDCHGIEN_Pos         (9)                                               /*!< OTG_T::INTEN: AVLDCHGIEN Position      */
+#define OTG_INTEN_AVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: AVLDCHGIEN Mask          */
+
+#define OTG_INTEN_VBCHGIEN_Pos           (10)                                              /*!< OTG_T::INTEN: VBCHGIEN Position        */
+#define OTG_INTEN_VBCHGIEN_Msk           (0x1ul << OTG_INTEN_VBCHGIEN_Pos)                 /*!< OTG_T::INTEN: VBCHGIEN Mask            */
+
+#define OTG_INTEN_SECHGIEN_Pos           (11)                                              /*!< OTG_T::INTEN: SECHGIEN Position        */
+#define OTG_INTEN_SECHGIEN_Msk           (0x1ul << OTG_INTEN_SECHGIEN_Pos)                 /*!< OTG_T::INTEN: SECHGIEN Mask            */
+
+#define OTG_INTEN_SRPDETIEN_Pos          (13)                                              /*!< OTG_T::INTEN: SRPDETIEN Position       */
+#define OTG_INTEN_SRPDETIEN_Msk          (0x1ul << OTG_INTEN_SRPDETIEN_Pos)                /*!< OTG_T::INTEN: SRPDETIEN Mask           */
+
+#define OTG_INTSTS_ROLECHGIF_Pos         (0)                                               /*!< OTG_T::INTSTS: ROLECHGIF Position      */
+#define OTG_INTSTS_ROLECHGIF_Msk         (0x1ul << OTG_INTSTS_ROLECHGIF_Pos)               /*!< OTG_T::INTSTS: ROLECHGIF Mask          */
+
+#define OTG_INTSTS_VBEIF_Pos             (1)                                               /*!< OTG_T::INTSTS: VBEIF Position          */
+#define OTG_INTSTS_VBEIF_Msk             (0x1ul << OTG_INTSTS_VBEIF_Pos)                   /*!< OTG_T::INTSTS: VBEIF Mask              */
+
+#define OTG_INTSTS_SRPFIF_Pos            (2)                                               /*!< OTG_T::INTSTS: SRPFIF Position         */
+#define OTG_INTSTS_SRPFIF_Msk            (0x1ul << OTG_INTSTS_SRPFIF_Pos)                  /*!< OTG_T::INTSTS: SRPFIF Mask             */
+
+#define OTG_INTSTS_HNPFIF_Pos            (3)                                               /*!< OTG_T::INTSTS: HNPFIF Position         */
+#define OTG_INTSTS_HNPFIF_Msk            (0x1ul << OTG_INTSTS_HNPFIF_Pos)                  /*!< OTG_T::INTSTS: HNPFIF Mask             */
+
+#define OTG_INTSTS_GOIDLEIF_Pos          (4)                                               /*!< OTG_T::INTSTS: GOIDLEIF Position       */
+#define OTG_INTSTS_GOIDLEIF_Msk          (0x1ul << OTG_INTSTS_GOIDLEIF_Pos)                /*!< OTG_T::INTSTS: GOIDLEIF Mask           */
+
+#define OTG_INTSTS_IDCHGIF_Pos           (5)                                               /*!< OTG_T::INTSTS: IDCHGIF Position        */
+#define OTG_INTSTS_IDCHGIF_Msk           (0x1ul << OTG_INTSTS_IDCHGIF_Pos)                 /*!< OTG_T::INTSTS: IDCHGIF Mask            */
+
+#define OTG_INTSTS_PDEVIF_Pos            (6)                                               /*!< OTG_T::INTSTS: PDEVIF Position         */
+#define OTG_INTSTS_PDEVIF_Msk            (0x1ul << OTG_INTSTS_PDEVIF_Pos)                  /*!< OTG_T::INTSTS: PDEVIF Mask             */
+
+#define OTG_INTSTS_HOSTIF_Pos            (7)                                               /*!< OTG_T::INTSTS: HOSTIF Position         */
+#define OTG_INTSTS_HOSTIF_Msk            (0x1ul << OTG_INTSTS_HOSTIF_Pos)                  /*!< OTG_T::INTSTS: HOSTIF Mask             */
+
+#define OTG_INTSTS_BVLDCHGIF_Pos         (8)                                               /*!< OTG_T::INTSTS: BVLDCHGIF Position      */
+#define OTG_INTSTS_BVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: BVLDCHGIF Mask          */
+
+#define OTG_INTSTS_AVLDCHGIF_Pos         (9)                                               /*!< OTG_T::INTSTS: AVLDCHGIF Position      */
+#define OTG_INTSTS_AVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: AVLDCHGIF Mask          */
+
+#define OTG_INTSTS_VBCHGIF_Pos           (10)                                              /*!< OTG_T::INTSTS: VBCHGIF Position        */
+#define OTG_INTSTS_VBCHGIF_Msk           (0x1ul << OTG_INTSTS_VBCHGIF_Pos)                 /*!< OTG_T::INTSTS: VBCHGIF Mask            */
+
+#define OTG_INTSTS_SECHGIF_Pos           (11)                                              /*!< OTG_T::INTSTS: SECHGIF Position        */
+#define OTG_INTSTS_SECHGIF_Msk           (0x1ul << OTG_INTSTS_SECHGIF_Pos)                 /*!< OTG_T::INTSTS: SECHGIF Mask            */
+
+#define OTG_INTSTS_SRPDETIF_Pos          (13)                                              /*!< OTG_T::INTSTS: SRPDETIF Position       */
+#define OTG_INTSTS_SRPDETIF_Msk          (0x1ul << OTG_INTSTS_SRPDETIF_Pos)                /*!< OTG_T::INTSTS: SRPDETIF Mask           */
+
+#define OTG_STATUS_OVERCUR_Pos           (0)                                               /*!< OTG_T::STATUS: OVERCUR Position        */
+#define OTG_STATUS_OVERCUR_Msk           (0x1ul << OTG_STATUS_OVERCUR_Pos)                 /*!< OTG_T::STATUS: OVERCUR Mask            */
+
+#define OTG_STATUS_IDSTS_Pos             (1)                                               /*!< OTG_T::STATUS: IDSTS Position          */
+#define OTG_STATUS_IDSTS_Msk             (0x1ul << OTG_STATUS_IDSTS_Pos)                   /*!< OTG_T::STATUS: IDSTS Mask              */
+
+#define OTG_STATUS_SESSEND_Pos           (2)                                               /*!< OTG_T::STATUS: SESSEND Position        */
+#define OTG_STATUS_SESSEND_Msk           (0x1ul << OTG_STATUS_SESSEND_Pos)                 /*!< OTG_T::STATUS: SESSEND Mask            */
+
+#define OTG_STATUS_BVLD_Pos              (3)                                               /*!< OTG_T::STATUS: BVLD Position           */
+#define OTG_STATUS_BVLD_Msk              (0x1ul << OTG_STATUS_BVLD_Pos)                    /*!< OTG_T::STATUS: BVLD Mask               */
+
+#define OTG_STATUS_AVLD_Pos              (4)                                               /*!< OTG_T::STATUS: AVLD Position           */
+#define OTG_STATUS_AVLD_Msk              (0x1ul << OTG_STATUS_AVLD_Pos)                    /*!< OTG_T::STATUS: AVLD Mask               */
+
+#define OTG_STATUS_VBUSVLD_Pos           (5)                                               /*!< OTG_T::STATUS: VBUSVLD Position        */
+#define OTG_STATUS_VBUSVLD_Msk           (0x1ul << OTG_STATUS_VBUSVLD_Pos)                 /*!< OTG_T::STATUS: VBUSVLD Mask            */
+
+#define OTG_STATUS_ASPERI_Pos            (6)                                               /*!< OTG_T::STATUS: ASPERI Position         */
+#define OTG_STATUS_ASPERI_Msk            (0x1ul << OTG_STATUS_ASPERI_Pos)                  /*!< OTG_T::STATUS: ASPERI Mask             */
+
+#define OTG_STATUS_ASHOST_Pos            (7)                                               /*!< OTG_T::STATUS: ASHOST Position         */
+#define OTG_STATUS_ASHOST_Msk            (0x1ul << OTG_STATUS_ASHOST_Pos)                  /*!< OTG_T::STATUS: ASHOST Mask             */
+
+/**@}*/ /* OTG_CONST */
+/**@}*/ /* end of OTG register group */
+
+
+
+
+/*---------------------- USB High Speed On-The-Go Controller -------------------------*/
+/**
+    @addtogroup HSOTG USB On-The-Go Controller(HSOTG)
+    Memory Mapped Structure for HSOTG Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var HSOTG_T::CTL
+     * Offset: 0x00  HSOTG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDROP  |Drop VBUS Control
+     * |        |          |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+     * |        |          |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+     * |        |          |0 = Not drop the VBUS.
+     * |        |          |1 = Drop the VBUS.
+     * |[1]     |BUSREQ    |OTG Bus Request
+     * |        |          |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+     * |        |          |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+     * |        |          |This bit will be cleared when A-device goes to A_wait_vfall state
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+     * |        |          |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+     * |        |          |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+     * |[2]     |HNPREQEN  |OTG HNP Request Enable Bit
+     * |        |          |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+     * |        |          |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+     * |        |          |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+     * |        |          |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+     * |        |          |0 = HNP request Disabled.
+     * |        |          |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+     * |        |          |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+     * |[4]     |OTGEN     |OTG Function Enable Bit
+     * |        |          |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+     * |        |          |When USB frame not configured as OTG device, this bit is must be low.
+     * |        |          |0= OTG function Disabled.
+     * |        |          |1 = OTG function Enabled.
+     * |[5]     |WKEN      |OTG ID Pin Wake-up Enable Bit
+     * |        |          |0 = OTG ID pin status change wake-up function Disabled.
+     * |        |          |1 = OTG ID pin status change wake-up function Enabled.
+     * @var HSOTG_T::PHYCTL
+     * Offset: 0x04  HSOTG PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OTGPHYEN  |OTG PHY Enable
+     * |        |          |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
+     * |        |          |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care".
+     * |        |          |0 = OTG PHY Disabled.
+     * |        |          |1 = OTG PHY Enabled.
+     * |[1]     |IDDETEN   |ID Detection Enable Bit
+     * |        |          |0 = Detect ID pin status Disabled.
+     * |        |          |1 = Detect ID pin status Enabled.
+     * |[4]     |VBENPOL   |Off-chip USB VBUS Power Switch Enable Polarity
+     * |        |          |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+     * |        |          |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+     * |        |          |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The off-chip USB VBUS power switch enable is active high.
+     * |        |          |1 = The off-chip USB VBUS power switch enable is active low.
+     * |[5]     |VBSTSPOL  |Off-chip USB VBUS Power Switch Status Polarity
+     * |        |          |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+     * |        |          |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+     * |        |          |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+     * @var HSOTG_T::INTEN
+     * Offset: 0x08  HSOTG Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[1]     |VBEIEN    |VBUS Error Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+     * |[2]     |SRPFIEN   |SRP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[3]     |HNPFIEN   |HNP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[4]     |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Going to idle state means going to a_idle or b_idle state
+     * |        |          |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+     * |[5]     |IDCHGIEN  |IDSTS Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[6]     |PDEVIEN   |Act As Peripheral Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+     * |        |          |0 = This device as a peripheral interrupt Disabled.
+     * |        |          |1 = This device as a peripheral interrupt Enabled.
+     * |[7]     |HOSTIEN   |Act As Host Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+     * |        |          |0 = This device as a host interrupt Disabled.
+     * |        |          |1 = This device as a host interrupt Enabled.
+     * |[8]     |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[9]     |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[10]    |VBCHGIEN  |VBUSVLD Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[11]    |SECHGIEN  |SESSEND Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[13]    |SRPDETIEN |SRP Detected Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * @var HSOTG_T::INTSTS
+     * Offset: 0x0C  HSOTG Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIF |OTG Role Change Interrupt Status
+     * |        |          |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+     * |        |          |0 = OTG device role not changed.
+     * |        |          |1 = OTG device role changed.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[1]     |VBEIF     |VBUS Error Interrupt Status
+     * |        |          |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+     * |        |          |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+     * |        |          |Note: Write 1 to clear this flag and recover from the VBUS error state.
+     * |[2]     |SRPFIF    |SRP Fail Interrupt Status
+     * |        |          |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+     * |        |          |This flag is set when the OTG B-device does not get VBUS high after this interval.
+     * |        |          |0 = OTG B-device gets VBUS high before this interval.
+     * |        |          |1 = OTG B-device does not get VBUS high before this interval.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[3]     |HNPFIF    |HNP Fail Interrupt Status
+     * |        |          |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+     * |        |          |0 = A-device connects to B-device before specified interval expires.
+     * |        |          |1 = A-device does not connect to B-device before specified interval expires.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[4]     |GOIDLEIF  |OTG Device Goes to IDLE Interrupt Status
+     * |        |          |Flag is set if the OTG device transfers from non-idle state to idle state
+     * |        |          |The OTG device will be neither a host nor a peripheral.
+     * |        |          |0 = OTG device does not go back to idle state (a_idle or b_idle).
+     * |        |          |1 = OTG device goes back to idle state(a_idle or b_idle).
+     * |        |          |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+     * |        |          |Note 2: Write 1 to clear this flag.
+     * |[5]     |IDCHGIF   |ID State Change Interrupt Status
+     * |        |          |0 = IDSTS (OTG_STATUS[1]) not toggled.
+     * |        |          |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[6]     |PDEVIF    |Act As Peripheral Interrupt Status
+     * |        |          |0= This device does not act as a peripheral.
+     * |        |          |1 = This device acts as a peripheral.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[7]     |HOSTIF    |Act As Host Interrupt Status
+     * |        |          |0= This device does not act as a host.
+     * |        |          |1 = This device acts as a host.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[8]     |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+     * |        |          |0 = BVLD (OTG_STATUS[3]) is not toggled.
+     * |        |          |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[9]     |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+     * |        |          |0 = AVLD (OTG_STATUS[4]) not toggled.
+     * |        |          |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[10]    |VBCHGIF   |VBUSVLD State Change Interrupt Status
+     * |        |          |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+     * |        |          |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[11]    |SECHGIF   |SESSEND State Change Interrupt Status
+     * |        |          |0 = SESSEND (OTG_STATUS[2]) not toggled.
+     * |        |          |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[13]    |SRPDETIF  |SRP Detected Interrupt Status
+     * |        |          |0 = SRP not detected.
+     * |        |          |1 = SRP detected.
+     * |        |          |Note: Write 1 to clear this status.
+     * @var HSOTG_T::STATUS
+     * Offset: 0x10  HSOTG Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OVERCUR   |over Current Condition
+     * |        |          |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS successfully.
+     * |        |          |1 = OTG A-device cannot drives VBUS high in this interval.
+     * |[1]     |IDSTS     |USB_ID Pin State of Mini-b/Micro-plug
+     * |        |          |0 = Mini-A/Micro-A plug is attached.
+     * |        |          |1 = Mini-B/Micro-B plug is attached.
+     * |[2]     |SESSEND   |Session End Status
+     * |        |          |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+     * |        |          |Session end means no meaningful power on VBUS.
+     * |        |          |0 = Session is not end.
+     * |        |          |1 = Session is end.
+     * |[3]     |BVLD      |B-device Session Valid Status
+     * |        |          |0 = B-device session is not valid.
+     * |        |          |1 = B-device session is valid.
+     * |[4]     |AVLD      |A-device Session Valid Status
+     * |        |          |0 = A-device session is not valid.
+     * |        |          |1 = A-device session is valid.
+     * |[5]     |VBUSVLD   |VBUS Valid Status
+     * |        |          |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1.
+     * |        |          |0 = VBUS is not valid.
+     * |        |          |1 = VBUS is valid.
+     * |[6]     |ASPERI    |As Peripheral Status
+     * |        |          |When OTG as peripheral, this bit is set.
+     * |        |          |0: OTG not as peripheral
+     * |        |          |1: OTG as peripheral
+     * |[7]     |ASHOST    |As Host Status
+     * |        |          |When OTG as Host, this bit is set.
+     * |        |          |0: OTG not as Host
+     * |        |          |1: OTG as Host
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] HSOTG Control Register                                           */
+    __IO uint32_t PHYCTL;                /*!< [0x0004] HSOTG PHY Control Register                                       */
+    __IO uint32_t INTEN;                 /*!< [0x0008] HSOTG Interrupt Enable Register                                  */
+    __IO uint32_t INTSTS;                /*!< [0x000c] HSOTG Interrupt Status Register                                  */
+    __I  uint32_t STATUS;                /*!< [0x0010] HSOTG Status Register                                            */
+
+} HSOTG_T;
+
+/**
+    @addtogroup HSOTG_CONST HSOTG Bit Field Definition
+    Constant Definitions for HSOTG Controller
+@{ */
+
+#define HSOTG_CTL_VBUSDROP_Pos           (0)                                               /*!< HSOTG_T::CTL: VBUSDROP Position        */
+#define HSOTG_CTL_VBUSDROP_Msk           (0x1ul << HSOTG_CTL_VBUSDROP_Pos)                 /*!< HSOTG_T::CTL: VBUSDROP Mask            */
+
+#define HSOTG_CTL_BUSREQ_Pos             (1)                                               /*!< HSOTG_T::CTL: BUSREQ Position          */
+#define HSOTG_CTL_BUSREQ_Msk             (0x1ul << HSOTG_CTL_BUSREQ_Pos)                   /*!< HSOTG_T::CTL: BUSREQ Mask              */
+
+#define HSOTG_CTL_HNPREQEN_Pos           (2)                                               /*!< HSOTG_T::CTL: HNPREQEN Position        */
+#define HSOTG_CTL_HNPREQEN_Msk           (0x1ul << HSOTG_CTL_HNPREQEN_Pos)                 /*!< HSOTG_T::CTL: HNPREQEN Mask            */
+
+#define HSOTG_CTL_OTGEN_Pos              (4)                                               /*!< HSOTG_T::CTL: OTGEN Position           */
+#define HSOTG_CTL_OTGEN_Msk              (0x1ul << HSOTG_CTL_OTGEN_Pos)                    /*!< HSOTG_T::CTL: OTGEN Mask               */
+
+#define HSOTG_CTL_WKEN_Pos               (5)                                               /*!< HSOTG_T::CTL: WKEN Position            */
+#define HSOTG_CTL_WKEN_Msk               (0x1ul << HSOTG_CTL_WKEN_Pos)                     /*!< HSOTG_T::CTL: WKEN Mask                */
+
+#define HSOTG_PHYCTL_OTGPHYEN_Pos        (0)                                               /*!< HSOTG_T::PHYCTL: OTGPHYEN Position     */
+#define HSOTG_PHYCTL_OTGPHYEN_Msk        (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos)              /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask         */
+
+#define HSOTG_PHYCTL_IDDETEN_Pos         (1)                                               /*!< HSOTG_T::PHYCTL: IDDETEN Position      */
+#define HSOTG_PHYCTL_IDDETEN_Msk         (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos)               /*!< HSOTG_T::PHYCTL: IDDETEN Mask          */
+
+#define HSOTG_PHYCTL_VBENPOL_Pos         (4)                                               /*!< HSOTG_T::PHYCTL: VBENPOL Position      */
+#define HSOTG_PHYCTL_VBENPOL_Msk         (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos)               /*!< HSOTG_T::PHYCTL: VBENPOL Mask          */
+
+#define HSOTG_PHYCTL_VBSTSPOL_Pos        (5)                                               /*!< HSOTG_T::PHYCTL: VBSTSPOL Position     */
+#define HSOTG_PHYCTL_VBSTSPOL_Msk        (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos)              /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask         */
+
+#define HSOTG_INTEN_ROLECHGIEN_Pos       (0)                                               /*!< HSOTG_T::INTEN: ROLECHGIEN Position    */
+#define HSOTG_INTEN_ROLECHGIEN_Msk       (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos)             /*!< HSOTG_T::INTEN: ROLECHGIEN Mask        */
+
+#define HSOTG_INTEN_VBEIEN_Pos           (1)                                               /*!< HSOTG_T::INTEN: VBEIEN Position        */
+#define HSOTG_INTEN_VBEIEN_Msk           (0x1ul << HSOTG_INTEN_VBEIEN_Pos)                 /*!< HSOTG_T::INTEN: VBEIEN Mask            */
+
+#define HSOTG_INTEN_SRPFIEN_Pos          (2)                                               /*!< HSOTG_T::INTEN: SRPFIEN Position       */
+#define HSOTG_INTEN_SRPFIEN_Msk          (0x1ul << HSOTG_INTEN_SRPFIEN_Pos)                /*!< HSOTG_T::INTEN: SRPFIEN Mask           */
+
+#define HSOTG_INTEN_HNPFIEN_Pos          (3)                                               /*!< HSOTG_T::INTEN: HNPFIEN Position       */
+#define HSOTG_INTEN_HNPFIEN_Msk          (0x1ul << HSOTG_INTEN_HNPFIEN_Pos)                /*!< HSOTG_T::INTEN: HNPFIEN Mask           */
+
+#define HSOTG_INTEN_GOIDLEIEN_Pos        (4)                                               /*!< HSOTG_T::INTEN: GOIDLEIEN Position     */
+#define HSOTG_INTEN_GOIDLEIEN_Msk        (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos)              /*!< HSOTG_T::INTEN: GOIDLEIEN Mask         */
+
+#define HSOTG_INTEN_IDCHGIEN_Pos         (5)                                               /*!< HSOTG_T::INTEN: IDCHGIEN Position      */
+#define HSOTG_INTEN_IDCHGIEN_Msk         (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos)               /*!< HSOTG_T::INTEN: IDCHGIEN Mask          */
+
+#define HSOTG_INTEN_PDEVIEN_Pos          (6)                                               /*!< HSOTG_T::INTEN: PDEVIEN Position       */
+#define HSOTG_INTEN_PDEVIEN_Msk          (0x1ul << HSOTG_INTEN_PDEVIEN_Pos)                /*!< HSOTG_T::INTEN: PDEVIEN Mask           */
+
+#define HSOTG_INTEN_HOSTIEN_Pos          (7)                                               /*!< HSOTG_T::INTEN: HOSTIEN Position       */
+#define HSOTG_INTEN_HOSTIEN_Msk          (0x1ul << HSOTG_INTEN_HOSTIEN_Pos)                /*!< HSOTG_T::INTEN: HOSTIEN Mask           */
+
+#define HSOTG_INTEN_BVLDCHGIEN_Pos       (8)                                               /*!< HSOTG_T::INTEN: BVLDCHGIEN Position    */
+#define HSOTG_INTEN_BVLDCHGIEN_Msk       (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos)             /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask        */
+
+#define HSOTG_INTEN_AVLDCHGIEN_Pos       (9)                                               /*!< HSOTG_T::INTEN: AVLDCHGIEN Position    */
+#define HSOTG_INTEN_AVLDCHGIEN_Msk       (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos)             /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask        */
+
+#define HSOTG_INTEN_VBCHGIEN_Pos         (10)                                              /*!< HSOTG_T::INTEN: VBCHGIEN Position      */
+#define HSOTG_INTEN_VBCHGIEN_Msk         (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos)               /*!< HSOTG_T::INTEN: VBCHGIEN Mask          */
+
+#define HSOTG_INTEN_SECHGIEN_Pos         (11)                                              /*!< HSOTG_T::INTEN: SECHGIEN Position      */
+#define HSOTG_INTEN_SECHGIEN_Msk         (0x1ul << HSOTG_INTEN_SECHGIEN_Pos)               /*!< HSOTG_T::INTEN: SECHGIEN Mask          */
+
+#define HSOTG_INTEN_SRPDETIEN_Pos        (13)                                              /*!< HSOTG_T::INTEN: SRPDETIEN Position     */
+#define HSOTG_INTEN_SRPDETIEN_Msk        (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos)              /*!< HSOTG_T::INTEN: SRPDETIEN Mask         */
+
+#define HSOTG_INTSTS_ROLECHGIF_Pos       (0)                                               /*!< HSOTG_T::INTSTS: ROLECHGIF Position    */
+#define HSOTG_INTSTS_ROLECHGIF_Msk       (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos)             /*!< HSOTG_T::INTSTS: ROLECHGIF Mask        */
+
+#define HSOTG_INTSTS_VBEIF_Pos           (1)                                               /*!< HSOTG_T::INTSTS: VBEIF Position        */
+#define HSOTG_INTSTS_VBEIF_Msk           (0x1ul << HSOTG_INTSTS_VBEIF_Pos)                 /*!< HSOTG_T::INTSTS: VBEIF Mask            */
+
+#define HSOTG_INTSTS_SRPFIF_Pos          (2)                                               /*!< HSOTG_T::INTSTS: SRPFIF Position       */
+#define HSOTG_INTSTS_SRPFIF_Msk          (0x1ul << HSOTG_INTSTS_SRPFIF_Pos)                /*!< HSOTG_T::INTSTS: SRPFIF Mask           */
+
+#define HSOTG_INTSTS_HNPFIF_Pos          (3)                                               /*!< HSOTG_T::INTSTS: HNPFIF Position       */
+#define HSOTG_INTSTS_HNPFIF_Msk          (0x1ul << HSOTG_INTSTS_HNPFIF_Pos)                /*!< HSOTG_T::INTSTS: HNPFIF Mask           */
+
+#define HSOTG_INTSTS_GOIDLEIF_Pos        (4)                                               /*!< HSOTG_T::INTSTS: GOIDLEIF Position     */
+#define HSOTG_INTSTS_GOIDLEIF_Msk        (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos)              /*!< HSOTG_T::INTSTS: GOIDLEIF Mask         */
+
+#define HSOTG_INTSTS_IDCHGIF_Pos         (5)                                               /*!< HSOTG_T::INTSTS: IDCHGIF Position      */
+#define HSOTG_INTSTS_IDCHGIF_Msk         (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos)               /*!< HSOTG_T::INTSTS: IDCHGIF Mask          */
+
+#define HSOTG_INTSTS_PDEVIF_Pos          (6)                                               /*!< HSOTG_T::INTSTS: PDEVIF Position       */
+#define HSOTG_INTSTS_PDEVIF_Msk          (0x1ul << HSOTG_INTSTS_PDEVIF_Pos)                /*!< HSOTG_T::INTSTS: PDEVIF Mask           */
+
+#define HSOTG_INTSTS_HOSTIF_Pos          (7)                                               /*!< HSOTG_T::INTSTS: HOSTIF Position       */
+#define HSOTG_INTSTS_HOSTIF_Msk          (0x1ul << HSOTG_INTSTS_HOSTIF_Pos)                /*!< HSOTG_T::INTSTS: HOSTIF Mask           */
+
+#define HSOTG_INTSTS_BVLDCHGIF_Pos       (8)                                               /*!< HSOTG_T::INTSTS: BVLDCHGIF Position    */
+#define HSOTG_INTSTS_BVLDCHGIF_Msk       (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos)             /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask        */
+
+#define HSOTG_INTSTS_AVLDCHGIF_Pos       (9)                                               /*!< HSOTG_T::INTSTS: AVLDCHGIF Position    */
+#define HSOTG_INTSTS_AVLDCHGIF_Msk       (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos)             /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask        */
+
+#define HSOTG_INTSTS_VBCHGIF_Pos         (10)                                              /*!< HSOTG_T::INTSTS: VBCHGIF Position      */
+#define HSOTG_INTSTS_VBCHGIF_Msk         (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos)               /*!< HSOTG_T::INTSTS: VBCHGIF Mask          */
+
+#define HSOTG_INTSTS_SECHGIF_Pos         (11)                                              /*!< HSOTG_T::INTSTS: SECHGIF Position      */
+#define HSOTG_INTSTS_SECHGIF_Msk         (0x1ul << HSOTG_INTSTS_SECHGIF_Pos)               /*!< HSOTG_T::INTSTS: SECHGIF Mask          */
+
+#define HSOTG_INTSTS_SRPDETIF_Pos        (13)                                              /*!< HSOTG_T::INTSTS: SRPDETIF Position     */
+#define HSOTG_INTSTS_SRPDETIF_Msk        (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos)              /*!< HSOTG_T::INTSTS: SRPDETIF Mask         */
+
+#define HSOTG_STATUS_OVERCUR_Pos         (0)                                               /*!< HSOTG_T::STATUS: OVERCUR Position      */
+#define HSOTG_STATUS_OVERCUR_Msk         (0x1ul << HSOTG_STATUS_OVERCUR_Pos)               /*!< HSOTG_T::STATUS: OVERCUR Mask          */
+
+#define HSOTG_STATUS_IDSTS_Pos           (1)                                               /*!< HSOTG_T::STATUS: IDSTS Position        */
+#define HSOTG_STATUS_IDSTS_Msk           (0x1ul << HSOTG_STATUS_IDSTS_Pos)                 /*!< HSOTG_T::STATUS: IDSTS Mask            */
+
+#define HSOTG_STATUS_SESSEND_Pos         (2)                                               /*!< HSOTG_T::STATUS: SESSEND Position      */
+#define HSOTG_STATUS_SESSEND_Msk         (0x1ul << HSOTG_STATUS_SESSEND_Pos)               /*!< HSOTG_T::STATUS: SESSEND Mask          */
+
+#define HSOTG_STATUS_BVLD_Pos            (3)                                               /*!< HSOTG_T::STATUS: BVLD Position         */
+#define HSOTG_STATUS_BVLD_Msk            (0x1ul << HSOTG_STATUS_BVLD_Pos)                  /*!< HSOTG_T::STATUS: BVLD Mask             */
+
+#define HSOTG_STATUS_AVLD_Pos            (4)                                               /*!< HSOTG_T::STATUS: AVLD Position         */
+#define HSOTG_STATUS_AVLD_Msk            (0x1ul << HSOTG_STATUS_AVLD_Pos)                  /*!< HSOTG_T::STATUS: AVLD Mask             */
+
+#define HSOTG_STATUS_VBUSVLD_Pos         (5)                                               /*!< HSOTG_T::STATUS: VBUSVLD Position      */
+#define HSOTG_STATUS_VBUSVLD_Msk         (0x1ul << HSOTG_STATUS_VBUSVLD_Pos)               /*!< HSOTG_T::STATUS: VBUSVLD Mask          */
+
+#define HSOTG_STATUS_ASPERI_Pos          (6)                                               /*!< HSOTG_T::STATUS: ASPERI Position       */
+#define HSOTG_STATUS_ASPERI_Msk          (0x1ul << HSOTG_STATUS_ASPERI_Pos)                /*!< HSOTG_T::STATUS: ASPERI Mask           */
+
+#define HSOTG_STATUS_ASHOST_Pos          (7)                                               /*!< HSOTG_T::STATUS: ASHOST Position       */
+#define HSOTG_STATUS_ASHOST_Msk          (0x1ul << HSOTG_STATUS_ASHOST_Pos)                /*!< HSOTG_T::STATUS: ASHOST Mask           */
+
+/**@}*/ /* HSOTG_CONST */
+/**@}*/ /* end of HSOTG register group */
+
+
+
+/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var CRC_T::CTL
+     * Offset: 0x00  CRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRCEN     |CRC Channel Enable Bit
+     * |        |          |0 = No effect.
+     * |        |          |1 = CRC operation Enabled.
+     * |[1]     |CHKSINIT  |Checksum Initialization
+     * |        |          |0 = No effect.
+     * |        |          |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
+     * |        |          |Note: This bit will be cleared automatically.
+     * |[24]    |DATREV    |Write Data Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
+     * |        |          |0 = Bit order reversed for CRC write data in Disabled.
+     * |        |          |1 = Bit order reversed for CRC write data in Enabled (per byte).
+     * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+     * |[25]    |CHKSREV   |Checksum Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = Bit order reverse for CRC checksum Disabled.
+     * |        |          |1 = Bit order reverse for CRC checksum Enabled.
+     * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+     * |[26]    |DATFMT    |Write Data 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+     * |        |          |0 = 1's complement for CRC writes data in Disabled.
+     * |        |          |1 = 1's complement for CRC writes data in Enabled.
+     * |[27]    |CHKSFMT   |Checksum 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = 1's complement for CRC checksum Disabled.
+     * |        |          |1 = 1's complement for CRC checksum Enabled.
+     * |[29:28] |DATLEN    |CPU Write Data Length
+     * |        |          |This field indicates the write data length.
+     * |        |          |00 = Data length is 8-bit mode.
+     * |        |          |01 = Data length is 16-bit mode.
+     * |        |          |1x = Data length is 32-bit mode.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+     * |[31:30] |CRCMODE   |CRC Polynomial Mode
+     * |        |          |This field indicates the CRC operation polynomial mode.
+     * |        |          |00 = CRC-CCITT Polynomial mode.
+     * |        |          |01 = CRC-8 Polynomial mode.
+     * |        |          |10 = CRC-16 Polynomial mode.
+     * |        |          |11 = CRC-32 Polynomial mode.
+     * @var CRC_T::DAT
+     * Offset: 0x04  CRC Write Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATA      |CRC Write Data Bits
+     * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+     * @var CRC_T::SEED
+     * Offset: 0x08  CRC Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |CRC Seed Value
+     * |        |          |This field indicates the CRC seed value.
+     * |        |          |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
+     * @var CRC_T::CHECKSUM
+     * Offset: 0x0C  CRC Checksum Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CHECKSUM  |CRC Checksum Results
+     * |        |          |This field indicates the CRC checksum result.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] CRC Control Register                                             */
+    __IO uint32_t DAT;                   /*!< [0x0004] CRC Write Data Register                                          */
+    __IO uint32_t SEED;                  /*!< [0x0008] CRC Seed Register                                                */
+    __I  uint32_t CHECKSUM;              /*!< [0x000c] CRC Checksum Register                                            */
+
+} CRC_T;
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position             */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                 */
+
+#define CRC_CTL_CHKSINIT_Pos             (1)                                               /*!< CRC_T::CTL: CHKSINIT Position          */
+#define CRC_CTL_CHKSINIT_Msk             (0x1ul << CRC_CTL_CHKSINIT_Pos)                   /*!< CRC_T::CTL: CHKSINIT Mask              */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position            */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position           */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask               */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position            */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position           */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask               */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position            */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position           */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask               */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position              */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                  */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position             */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                 */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position     */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask         */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+
+
+/*---------------------- Cryptographic Accelerator -------------------------*/
+/**
+    @addtogroup CRPT Cryptographic Accelerator(CRPT)
+    Memory Mapped Structure for Cryptographic Accelerator
+@{ */
+
+typedef struct {
+
+    /**
+     * @var CRPT_T::INTEN
+     * Offset: 0x00  Crypto Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIEN    |AES Interrupt Enable Control
+     * |        |          |0 = AES interrupt Disabled.
+     * |        |          |1 = AES interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
+     * |[1]     |AESEIEN   |AES Error Flag Enable Control
+     * |        |          |0 = AES error interrupt flag Disabled.
+     * |        |          |1 = AES error interrupt flag Enabled.
+     * |[8]     |TDESIEN   |TDES/DES Interrupt Enable Control
+     * |        |          |0 = TDES/DES interrupt Disabled.
+     * |        |          |1 = TDES/DES interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
+     * |[9]     |TDESEIEN  |TDES/DES Error Flag Enable Control
+     * |        |          |0 = TDES/DES error interrupt flag Disabled.
+     * |        |          |1 = TDES/DES error interrupt flag Enabled.
+     * |[16]    |PRNGIEN   |PRNG Interrupt Enable Control
+     * |        |          |0 = PRNG interrupt Disabled.
+     * |        |          |1 = PRNG interrupt Enabled.
+     * |[22]    |ECCIEN    |ECC Interrupt Enable Control
+     * |        |          |0 = ECC interrupt Disabled.
+     * |        |          |1 = ECC interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
+     * |[23]    |ECCEIEN   |ECC Error Interrupt Enable Control
+     * |        |          |0 = ECC error interrupt flag Disabled.
+     * |        |          |1 = ECC error interrupt flag Enabled.
+     * |[24]    |HMACIEN   |SHA/HMAC Interrupt Enable Control
+     * |        |          |0 = SHA/HMAC interrupt Disabled.
+     * |        |          |1 = SHA/HMAC interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
+     * |[25]    |HMACEIEN  |SHA/HMAC Error Interrupt Enable Control
+     * |        |          |0 = SHA/HMAC error interrupt flag Disabled.
+     * |        |          |1 = SHA/HMAC error interrupt flag Enabled.
+     * @var CRPT_T::INTSTS
+     * Offset: 0x04  Crypto Interrupt Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIF     |AES Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No AES interrupt.
+     * |        |          |= AES encryption/decryption done interrupt.
+     * |[1]     |AESEIF    |AES Error Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No AES error.
+     * |        |          |1 = AES encryption/decryption done interrupt.
+     * |[8]     |TDESIF    |TDES/DES Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No TDES/DES interrupt.
+     * |        |          |1 = TDES/DES encryption/decryption done interrupt.
+     * |[9]     |TDESEIF   |TDES/DES Error Flag
+     * |        |          |This bit includes the operating and setting error
+     * |        |          |The detailed flag is shown in the CRPT_TDES_STS register
+     * |        |          |This includes operating and setting error.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No TDES/DES error.
+     * |        |          |1 = TDES/DES encryption/decryption error interrupt.
+     * |[16]    |PRNGIF    |PRNG Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No PRNG interrupt.
+     * |        |          |1 = PRNG key generation done interrupt.
+     * |[22]    |ECCIF     |ECC Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No ECC interrupt.
+     * |        |          |1 = ECC operation done interrupt.
+     * |[23]    |ECCEIF    |ECC Error Flag
+     * |        |          |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No ECC error.
+     * |        |          |1 = ECC error interrupt.
+     * |[24]    |HMACIF    |SHA/HMAC Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No SHA/HMAC interrupt.
+     * |        |          |1 = SHA/HMAC operation done interrupt.
+     * |[25]    |HMACEIF   |SHA/HMAC Error Flag
+     * |        |          |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No SHA/HMAC error.
+     * |        |          |1 = SHA/HMAC error interrupt.
+     * @var CRPT_T::PRNG_CTL
+     * Offset: 0x08  PRNG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |Start PRNG Engine
+     * |        |          |0 = Stop PRNG engine.
+     * |        |          |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
+     * |[1]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |[3:2]   |KEYSZ     |PRNG Generate Key Size
+     * |        |          |00 = 64 bits.
+     * |        |          |01 = 128 bits.
+     * |        |          |10 = 192 bits.
+     * |        |          |11 = 256 bits.
+     * |[8]     |BUSY      |PRNG Busy (Read Only)
+     * |        |          |0 = PRNG engine is idle.
+     * |        |          |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
+     * @var CRPT_T::PRNG_SEED
+     * Offset: 0x0C  Seed for PRNG
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed for PRNG (Write Only)
+     * |        |          |The bits store the seed for PRNG engine.
+     * @var CRPT_T::PRNG_KEY[8]
+     * Offset: 0x10 ~ 0x2C  PRNG Generated Key0 ~ Key7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |Store PRNG Generated Key (Read Only)
+     * |        |          |The bits store the key that is generated by PRNG.
+     * @var CRPT_T::AES_FDBCK[4]
+     * Offset: 0x50 ~ 0x5C  AES Engine Output Feedback Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |AES Feedback Information
+     * |        |          |The feedback value is 128 bits in size.
+     * |        |          |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.
+     * |        |          |The AES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
+     * @var CRPT_T::TDES_FDBCKH
+     * Offset: 0x60  TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |TDES/DES Feedback
+     * |        |          |The feedback value is 64 bits in size.
+     * |        |          |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+     * |        |          |The feedback register is for CBC, CFB, and OFB mode.
+     * |        |          |TDES/DES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation
+     * |        |          |Then can continue the operation with the original setting.
+     * @var CRPT_T::TDES_FDBCKL
+     * Offset: 0x64  TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |TDES/DES Feedback
+     * |        |          |The feedback value is 64 bits in size.
+     * |        |          |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+     * |        |          |The feedback register is for CBC, CFB, and OFB mode.
+     * |        |          |TDES/DES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation
+     * |        |          |Then can continue the operation with the original setting.
+     * @var CRPT_T::AES_CTL
+     * Offset: 0x100  AES Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |AES Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start AES engine. BUSY flag will be set.
+     * |        |          |Note: This bit is always 0 when it's read back.
+     * |[1]     |STOP      |AES Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop AES engine.
+     * |        |          |Note: This bit is always 0 when it's read back.
+     * |[3:2]   |KEYSZ     |AES Key Size
+     * |        |          |This bit defines three different key size for AES operation.
+     * |        |          |2'b00 = 128 bits key.
+     * |        |          |2'b01 = 192 bits key.
+     * |        |          |2'b10 = 256 bits key.
+     * |        |          |2'b11 = Reserved.
+     * |        |          |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
+     * |[5]     |DMALAST   |AES Last Block
+     * |        |          |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+     * |        |          |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
+     * |        |          |This bit is always 0 when it's read back. Must be written again once START is triggered.
+     * |[6]     |DMACSCAD  |AES Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |AES Engine DMA Enable Control
+     * |        |          |0 = AES DMA engine Disabled.
+     * |        |          |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
+     * |        |          |1 = AES_DMA engine Enabled.
+     * |        |          |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[15:8]  |OPMODE    |AES Engine Operation Modes
+     * |        |          |0x00 = ECB (Electronic Codebook Mode)  0x01 = CBC (Cipher Block Chaining Mode).
+     * |        |          |0x02 = CFB (Cipher Feedback Mode).
+     * |        |          |0x03 = OFB (Output Feedback Mode).
+     * |        |          |0x04 = CTR (Counter Mode).
+     * |        |          |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
+     * |        |          |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
+     * |        |          |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
+     * |[16]    |ENCRPT    |AES Encryption/Decryption
+     * |        |          |0 = AES engine executes decryption operation.
+     * |        |          |1 = AES engine executes encryption operation.
+     * |[22]    |OUTSWAP   |AES Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |AES Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[25:24] |CHANNEL   |AES Engine Working Channel
+     * |        |          |00 = Current control register setting is for channel 0.
+     * |        |          |01 = Current control register setting is for channel 1.
+     * |        |          |10 = Current control register setting is for channel 2.
+     * |        |          |11 = Current control register setting is for channel 3.
+     * |[30:26] |KEYUNPRT  |Unprotect Key
+     * |        |          |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key.
+     * |        |          |The KEYUNPRT can be read and written
+     * |        |          |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+     * |[31]    |KEYPRT    |Protect Key
+     * |        |          |Read as a flag to reflect KEYPRT.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Protect the content of the AES key from reading
+     * |        |          |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx
+     * |        |          |Once it is set, it can be cleared by asserting KEYUNPRT
+     * |        |          |And the key content would be cleared as well.
+     * @var CRPT_T::AES_STS
+     * Offset: 0x104  AES Engine Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |AES Engine Busy
+     * |        |          |0 = The AES engine is idle or finished.
+     * |        |          |1 = The AES engine is under processing.
+     * |[8]     |INBUFEMPTY|AES Input Buffer Empty
+     * |        |          |0 = There are some data in input buffer waiting for the AES engine to process.
+     * |        |          |1 = AES input buffer is empty
+     * |        |          |Software needs to feed data to the AES engine
+     * |        |          |Otherwise, the AES engine will be pending to wait for input data.
+     * |[9]     |INBUFFULL |AES Input Buffer Full Flag
+     * |        |          |0 = AES input buffer is not full. Software can feed the data into the AES engine.
+     * |        |          |1 = AES input buffer is full
+     * |        |          |Software cannot feed data to the AES engine
+     * |        |          |Otherwise, the flag INBUFERR will be set to 1.
+     * |[10]    |INBUFERR  |AES Input Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during feeding data to the AES engine.
+     * |[12]    |CNTERR    |CRPT_AESn_CNT Setting Error
+     * |        |          |0 = No error in CRPT_AESn_CNT setting.
+     * |        |          |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
+     * |[16]    |OUTBUFEMPTY|AES Out Buffer Empty
+     * |        |          |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
+     * |        |          |1 = AES output buffer is empty
+     * |        |          |Software cannot get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
+     * |[17]    |OUTBUFFULL|AES Out Buffer Full Flag
+     * |        |          |0 = AES output buffer is not full.
+     * |        |          |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the AES engine will be pending since the output buffer is full.
+     * |[18]    |OUTBUFERR |AES Out Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during getting the result from AES engine.
+     * |[20]    |BUSERR    |AES DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and AES engine.
+     * @var CRPT_T::AES_DATIN
+     * Offset: 0x108  AES Engine Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |AES Engine Input Port
+     * |        |          |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
+     * @var CRPT_T::AES_DATOUT
+     * Offset: 0x10C  AES Engine Data Output Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATOUT    |AES Engine Output Port
+     * |        |          |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
+     * |        |          |Get data as OUTBUFEMPTY is 0.
+     * @var CRPT_T::AES0_KEY[8]
+     * Offset: 0x110 ~ 0x12C  AES Key Word 0 ~ 7 Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES0_IV[4]
+     * Offset: 0x130 ~ 0x13C  AES Initial Vector Word 0 ~ 3 Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES0_SADDR
+     * Offset: 0x140  AES DMA Source Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES0_DADDR
+     * Offset: 0x144  AES DMA Destination Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES0_CNT
+     * Offset: 0x148  AES Byte Count Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES1_KEY[8]
+     * Offset: 0x14C ~ 0x168  AES Key Word 0 ~ 7 Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES1_IV[4]
+     * Offset: 0x16C ~ 0x178  AES Initial Vector Word 0 ~ 3 Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES1_SADDR
+     * Offset: 0x17C  AES DMA Source Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES1_DADDR
+     * Offset: 0x180  AES DMA Destination Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES1_CNT
+     * Offset: 0x184  AES Byte Count Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES2_KEY[8]
+     * Offset: 0x188 ~ 0x1A4  AES Key Word 0 ~ 7 Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES2_IV[4]
+     * Offset: 0x1A8 ~ 0x1B4  AES Initial Vector Word 0 ~ 3 Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES2_SADDR
+     * Offset: 0x1B8  AES DMA Source Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES2_DADDR
+     * Offset: 0x1BC  AES DMA Destination Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES2_CNT
+     * Offset: 0x1C0  AES Byte Count Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES3_KEY[8]
+     * Offset: 0x1C4 ~ 0x1E0  AES Key Word 0 ~ 7 Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES3_IV[4]
+     * Offset: 0x1E4 ~ 0x1F0  AES Initial Vector Word 0 ~ 3 Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES3_SADDR
+     * Offset: 0x1F4  AES DMA Source Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES3_DADDR
+     * Offset: 0x1F8  AES DMA Destination Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES3_CNT
+     * Offset: 0x1FC  AES Byte Count Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::TDES_CTL
+     * Offset: 0x200  TDES/DES Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |TDES/DES Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start TDES/DES engine. The flag BUSY would be set.
+     * |        |          |Note: The bit is always 0 when it's read back.
+     * |[1]     |STOP      |TDES/DES Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop TDES/DES engine.
+     * |        |          |Note: The bit is always 0 when it's read back.
+     * |[2]     |TMODE     |TDES/DES Engine Operating Mode
+     * |        |          |0 = Set DES mode for TDES/DES engine.
+     * |        |          |1 = Set Triple DES mode for TDES/DES engine.
+     * |[3]     |3KEYS     |TDES/DES Key Number
+     * |        |          |0 = Select KEY1 and KEY2 in TDES/DES engine.
+     * |        |          |1 = Triple keys in TDES/DES engine Enabled.
+     * |[5]     |DMALAST   |TDES/DES Engine Start for the Last Block
+     * |        |          |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+     * |        |          |In Non-DMA mode, this bit must be set as feeding in last block of data.
+     * |[6]     |DMACSCAD  |TDES/DES Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |TDES/DES Engine DMA Enable Control
+     * |        |          |0 = TDES_DMA engine Disabled.
+     * |        |          |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
+     * |        |          |1 = TDES_DMA engine Enabled.
+     * |        |          |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[10:8]  |OPMODE    |TDES/DES Engine Operation Mode
+     * |        |          |0x00 = ECB (Electronic Codebook Mode).
+     * |        |          |0x01 = CBC (Cipher Block Chaining Mode).
+     * |        |          |0x02 = CFB (Cipher Feedback Mode).
+     * |        |          |0x03 = OFB (Output Feedback Mode).
+     * |        |          |0x04 = CTR (Counter Mode).
+     * |        |          |Others = CTR (Counter Mode).
+     * |[16]    |ENCRPT    |TDES/DES Encryption/Decryption
+     * |        |          |0 = TDES engine executes decryption operation.
+     * |        |          |1 = TDES engine executes encryption operation.
+     * |[21]    |BLKSWAP   |TDES/DES Engine Block Double Word Endian Swap
+     * |        |          |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
+     * |        |          |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
+     * |[22]    |OUTSWAP   |TDES/DES Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |TDES/DES Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[25:24] |CHANNEL   |TDES/DES Engine Working Channel
+     * |        |          |00 = Current control register setting is for channel 0.
+     * |        |          |01 = Current control register setting is for channel 1.
+     * |        |          |10 = Current control register setting is for channel 2.
+     * |        |          |11 = Current control register setting is for channel 3.
+     * |[30:26] |KEYUNPRT  |Unprotect Key
+     * |        |          |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
+     * |        |          |The KEYUNPRT can be read and written
+     * |        |          |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+     * |[31]    |KEYPRT    |Protect Key
+     * |        |          |Read as a flag to reflect KEYPRT.
+     * |        |          |0 = No effect.
+     * |        |          |1 = This bit is to protect the content of TDES key from reading
+     * |        |          |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L
+     * |        |          |Once it is set, it can be cleared by asserting KEYUNPRT
+     * |        |          |The key content would be cleared as well.
+     * @var CRPT_T::TDES_STS
+     * Offset: 0x204  TDES/DES Engine Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |TDES/DES Engine Busy
+     * |        |          |0 = TDES/DES engine is idle or finished.
+     * |        |          |1 = TDES/DES engine is under processing.
+     * |[8]     |INBUFEMPTY|TDES/DES in Buffer Empty
+     * |        |          |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
+     * |        |          |1 = TDES/DES input buffer is empty
+     * |        |          |Software needs to feed data to the TDES/DES engine
+     * |        |          |Otherwise, the TDES/DES engine will be pending to wait for input data.
+     * |[9]     |INBUFFULL |TDES/DES in Buffer Full Flag
+     * |        |          |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
+     * |        |          |1 = TDES input buffer is full
+     * |        |          |Software cannot feed data to the TDES/DES engine
+     * |        |          |Otherwise, the flag INBUFERR will be set to 1.
+     * |[10]    |INBUFERR  |TDES/DES in Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during feeding data to the TDES/DES engine.
+     * |[16]    |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
+     * |        |          |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
+     * |        |          |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT
+     * |        |          |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
+     * |[17]    |OUTBUFFULL|TDES/DES Output Buffer Full Flag
+     * |        |          |0 = TDES/DES output buffer is not full.
+     * |        |          |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT
+     * |        |          |Otherwise, the TDES/DES engine will be pending since output buffer is full.
+     * |[18]    |OUTBUFERR |TDES/DES Out Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during getting test result from TDES/DES engine.
+     * |[20]    |BUSERR    |TDES/DES DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and TDES/DES engine.
+     * @var CRPT_T::TDES0_KEY1H
+     * Offset: 0x208  TDES/DES Key 1 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY1L
+     * Offset: 0x20C  TDES/DES Key 1 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY2H
+     * Offset: 0x210  TDES Key 2 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY2L
+     * Offset: 0x214  TDES Key 2 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY3H
+     * Offset: 0x218  TDES Key 3 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY3L
+     * Offset: 0x21C  TDES Key 3 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_IVH
+     * Offset: 0x220  TDES/DES Initial Vector High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES0_IVL
+     * Offset: 0x224  TDES/DES Initial Vector Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES0_SA
+     * Offset: 0x228  TDES/DES DMA Source Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES0_DA
+     * Offset: 0x22C  TDES/DES DMA Destination Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES0_CNT
+     * Offset: 0x230  TDES/DES Byte Count Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES_DATIN
+     * Offset: 0x234  TDES/DES Engine Input data Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |TDES/DES Engine Input Port
+     * |        |          |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS
+     * |        |          |Feed data as INBUFFULL is 0.
+     * @var CRPT_T::TDES_DATOUT
+     * Offset: 0x238  TDES/DES Engine Output data Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATOUT    |TDES/DES Engine Output Port
+     * |        |          |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS
+     * |        |          |Get data as OUTBUFEMPTY is 0.
+     * @var CRPT_T::TDES1_KEY1H
+     * Offset: 0x248  TDES/DES Key 1 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY1L
+     * Offset: 0x24C  TDES/DES Key 1 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY2H
+     * Offset: 0x250  TDES Key 2 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY2L
+     * Offset: 0x254  TDES Key 2 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY3H
+     * Offset: 0x258  TDES Key 3 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY3L
+     * Offset: 0x25C  TDES Key 3 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_IVH
+     * Offset: 0x260  TDES/DES Initial Vector High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES1_IVL
+     * Offset: 0x264  TDES/DES Initial Vector Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES1_SA
+     * Offset: 0x268  TDES/DES DMA Source Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES1_DA
+     * Offset: 0x26C  TDES/DES DMA Destination Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES1_CNT
+     * Offset: 0x270  TDES/DES Byte Count Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES2_KEY1H
+     * Offset: 0x288  TDES/DES Key 1 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY1L
+     * Offset: 0x28C  TDES/DES Key 1 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY2H
+     * Offset: 0x290  TDES Key 2 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY2L
+     * Offset: 0x294  TDES Key 2 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY3H
+     * Offset: 0x298  TDES Key 3 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY3L
+     * Offset: 0x29C  TDES Key 3 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_IVH
+     * Offset: 0x2A0  TDES/DES Initial Vector High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES2_IVL
+     * Offset: 0x2A4  TDES/DES Initial Vector Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES2_SA
+     * Offset: 0x2A8  TDES/DES DMA Source Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES2_DA
+     * Offset: 0x2AC  TDES/DES DMA Destination Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES2_CNT
+     * Offset: 0x2B0  TDES/DES Byte Count Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES3_KEY1H
+     * Offset: 0x2C8  TDES/DES Key 1 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY1L
+     * Offset: 0x2CC  TDES/DES Key 1 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY2H
+     * Offset: 0x2D0  TDES Key 2 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY2L
+     * Offset: 0x2D4  TDES Key 2 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY3H
+     * Offset: 0x2D8  TDES Key 3 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY3L
+     * Offset: 0x2DC  TDES Key 3 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_IVH
+     * Offset: 0x2E0  TDES/DES Initial Vector High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES3_IVL
+     * Offset: 0x2E4  TDES/DES Initial Vector Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES3_SA
+     * Offset: 0x2E8  TDES/DES DMA Source Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES3_DA
+     * Offset: 0x2EC  TDES/DES DMA Destination Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES3_CNT
+     * Offset: 0x2F0  TDES/DES Byte Count Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::HMAC_CTL
+     * Offset: 0x300  SHA/HMAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |SHA/HMAC Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start SHA/HMAC engine. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it's read back.
+     * |[1]     |STOP      |SHA/HMAC Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop SHA/HMAC engine.
+     * |        |          |This bit is always 0 when it's read back.
+     * |[4]     |HMACEN    |HMAC_SHA Engine Operating Mode
+     * |        |          |0 = execute SHA function.
+     * |        |          |1 = execute HMAC function.
+     * |[5]     |DMALAST   |SHA/HMAC Last Block
+     * |        |          |This bit must be set as feeding in last byte of data.
+     * |[7]     |DMAEN     |SHA/HMAC Engine DMA Enable Control
+     * |        |          |0 = SHA/HMAC DMA engine Disabled.
+     * |        |          |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.
+     * |        |          |1 = SHA/HMAC DMA engine Enabled.
+     * |        |          |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[10:8]  |OPMODE    |SHA/HMAC Engine Operation Modes
+     * |        |          |0x0xx: SHA160
+     * |        |          |0x100: SHA256
+     * |        |          |0x101: SHA224
+     * |        |          |0x110: SHA512
+     * |        |          |0x111: SHA384
+     * |        |          |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
+     * |[22]    |OUTSWAP   |SHA/HMAC Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |SHA/HMAC Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * @var CRPT_T::HMAC_STS
+     * Offset: 0x304  SHA/HMAC Status Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |SHA/HMAC Engine Busy
+     * |        |          |0 = SHA/HMAC engine is idle or finished.
+     * |        |          |1 = SHA/HMAC engine is busy.
+     * |[1]     |DMABUSY   |SHA/HMAC Engine DMA Busy Flag
+     * |        |          |0 = SHA/HMAC DMA engine is idle or finished.
+     * |        |          |1 = SHA/HMAC DMA engine is busy.
+     * |[8]     |DMAERR    |SHA/HMAC Engine DMA Error Flag
+     * |        |          |0 = Show the SHA/HMAC engine access normal.
+     * |        |          |1 = Show the SHA/HMAC engine access error.
+     * |[16]    |DATINREQ  |SHA/HMAC Non-DMA Mode Data Input Request
+     * |        |          |0 = No effect.
+     * |        |          |1 = Request SHA/HMAC Non-DMA mode data input.
+     * @var CRPT_T::HMAC_DGST[16]
+     * Offset: 0x308 ~ 0x344  SHA/HMAC Digest Message 0 ~ 15
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DGST      |SHA/HMAC Digest Message Output Register
+     * |        |          |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
+     * |        |          |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
+     * |        |          |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
+     * |        |          |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
+     * |        |          |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
+     * @var CRPT_T::HMAC_KEYCNT
+     * Offset: 0x348  SHA/HMAC Key Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEYCNT    |SHA/HMAC Key Byte Count
+     * |        |          |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
+     * |        |          |The register is 32-bit and the maximum byte count is 4G bytes
+     * |        |          |It can be read and written.
+     * |        |          |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_SHA _KEYCNT will be updated later on
+     * |        |          |Consequently, software can prepare the key count for the next SHA/HMAC operation.
+     * @var CRPT_T::HMAC_SADDR
+     * Offset: 0x34C  SHA/HMAC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |SHA/HMAC DMA Source Address
+     * |        |          |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
+     * |        |          |CRPT_HMAC_SADDR can be read and written
+     * |        |          |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
+     * |        |          |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
+     * |        |          |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
+     * @var CRPT_T::HMAC_DMACNT
+     * Offset: 0x350  SHA/HMAC Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DMACNT    |SHA/HMAC Operation Byte Count
+     * |        |          |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
+     * |        |          |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_HMAC_DMACNT can be read and written
+     * |        |          |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_DMACNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
+     * |        |          |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
+     * @var CRPT_T::HMAC_DATIN
+     * Offset: 0x354  SHA/HMAC Engine Non-DMA Mode Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |SHA/HMAC Engine Input Port
+     * |        |          |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
+     * |        |          |Feed data as DATINREQ is 1.
+     * @var CRPT_T::ECC_CTL
+     * Offset: 0x800  ECC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |ECC Accelerator Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start ECC accelerator. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it's read back.
+     * |        |          |ECC accelerator will ignore this START signal when BUSY flag is 1.
+     * |[1]     |STOP      |ECC Accelerator Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Abort ECC accelerator and make it into idle state.
+     * |        |          |This bit is always 0 when it's read back.
+     * |        |          |Remember to clear ECC interrupt flag after stopping ECC accelerator.
+     * |[7]     |DMAEN     |ECC Accelerator DMA Enable Control
+     * |        |          |0 = ECC DMA engine Disabled.
+     * |        |          |1 = ECC DMA engine Enabled.
+     * |        |          |Only when START and DMAEN are 1, ECC DMA engine will be active
+     * |[8]     |FSEL      |Field Selection
+     * |        |          |0 = Binary Field (GF(2^m)).
+     * |        |          |1 = Prime Field (GF(p)).
+     * |[10:9]  |ECCOP     |Point Operation for BF and PF
+     * |        |          |00 = Point multiplication :.
+     * |        |          |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
+     * |        |          |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
+     * |        |          |10 = Point addition :.
+     * |        |          |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
+     * |        |          |(POINTX2, POINTY2)
+     * |        |          |11 = Point doubling :.
+     * |        |          |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
+     * |        |          |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
+     * |[12:11] |MODOP     |Modulus Operation for PF
+     * |        |          |00 = Division :.
+     * |        |          |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
+     * |        |          |01 = Multiplication :.
+     * |        |          |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
+     * |        |          |10 = Addition :.
+     * |        |          |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
+     * |        |          |11 = Subtraction :.
+     * |        |          |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
+     * |        |          |MODOP is active only when ECCOP = 01.
+     * |[16]    |LDP1      |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
+     * |        |          |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
+     * |[17]    |LDP2      |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
+     * |        |          |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
+     * |[18]    |LDA       |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
+     * |        |          |0 = The register for CURVEA is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEA is modified by DMA or user.
+     * |[19]    |LDB       |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
+     * |        |          |0 = The register for CURVEB is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEB is modified by DMA or user.
+     * |[20]    |LDN       |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
+     * |        |          |0 = The register for CURVEN is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEN is modified by DMA or user.
+     * |[21]    |LDK       |The Control Signal of Register for SCALARK
+     * |        |          |0 = The register for SCALARK is not modified by DMA or user.
+     * |        |          |1 = The register for SCALARK is modified by DMA or user.
+     * |[31:22] |CURVEM    |The key length of elliptic curve.
+     * @var CRPT_T::ECC_STS
+     * Offset: 0x804  ECC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |ECC Accelerator Busy Flag
+     * |        |          |0 = The ECC accelerator is idle or finished.
+     * |        |          |1 = The ECC accelerator is under processing and protects all registers.
+     * |        |          |Remember to clear ECC interrupt flag after ECC accelerator finished
+     * |[1]     |DMABUSY   |ECC DMA Busy Flag
+     * |        |          |0 = ECC DMA is idle or finished.
+     * |        |          |1 = ECC DMA is busy.
+     * |[16]    |BUSERR    |ECC DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and ECC accelerator.
+     * @var CRPT_T::ECC_X1[18]
+     * Offset: 0x808 ~ 0x84C  ECC The X-coordinate word 0 ~ 17 of the first point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX1   |ECC the x-coordinate Value of the First Point (POINTX1)
+     * |        |          |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
+     * |        |          |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
+     * |        |          |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
+     * |        |          |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
+     * |        |          |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
+     * |        |          |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
+     * @var CRPT_T::ECC_Y1[18]
+     * Offset: 0x850 ~ 0x894  ECC The Y-coordinate word 0 ~ 17 of the first point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY1   |ECC the Y-coordinate Value of the First Point (POINTY1)
+     * |        |          |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
+     * |        |          |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
+     * |        |          |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
+     * |        |          |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
+     * |        |          |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
+     * |        |          |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
+     * @var CRPT_T::ECC_X2[18]
+     * Offset: 0x898 ~ 0x8DC  ECC The X-coordinate word 0 ~ 17 of the second point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX2   |ECC the x-coordinate Value of the Second Point (POINTX2)
+     * |        |          |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
+     * |        |          |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
+     * |        |          |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
+     * |        |          |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
+     * |        |          |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
+     * |        |          |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
+     * @var CRPT_T::ECC_Y2[18]
+     * Offset: 0x8E0 ~ 0x924  ECC The Y-coordinate word 0 ~ 17 of the second point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY2   |ECC the Y-coordinate Value of the Second Point (POINTY2)
+     * |        |          |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
+     * |        |          |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
+     * |        |          |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
+     * |        |          |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
+     * |        |          |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
+     * |        |          |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
+     * @var CRPT_T::ECC_A[18]
+     * Offset: 0x928 ~ 0x96C  ECC The parameter CURVEA word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEA    |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+     * |        |          |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
+     * |        |          |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
+     * |        |          |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
+     * |        |          |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
+     * |        |          |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
+     * |        |          |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
+     * @var CRPT_T::ECC_B[18]
+     * Offset: 0x970 ~ 0x9B4  ECC The parameter CURVEB word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEB    |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+     * |        |          |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
+     * |        |          |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
+     * |        |          |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
+     * |        |          |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
+     * |        |          |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
+     * |        |          |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
+     * @var CRPT_T::ECC_N[18]
+     * Offset: 0x9B8 ~ 0x9FC  ECC The parameter CURVEN word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEN    |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)
+     * |        |          |In GF(p), CURVEN is the prime p.
+     * |        |          |In GF(2^m), CURVEN is the irreducible polynomial.
+     * |        |          |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+     * |        |          |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+     * |        |          |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08
+     * |        |          |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12
+     * |        |          |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17
+     * |        |          |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+     * |        |          |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06
+     * |        |          |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+     * |        |          |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11
+     * |        |          |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16
+     * @var CRPT_T::ECC_K[18]
+     * Offset: 0xA00 ~ 0xA44  ECC The scalar SCALARK word0 of point multiplication
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SCALARK   |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)
+     * |        |          |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
+     * |        |          |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+     * |        |          |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+     * |        |          |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08
+     * |        |          |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12
+     * |        |          |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17
+     * |        |          |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+     * |        |          |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06
+     * |        |          |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+     * |        |          |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11
+     * |        |          |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16
+     * @var CRPT_T::ECC_SADDR
+     * Offset: 0xA48  ECC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |ECC DMA Source Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
+     * |        |          |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
+     * |        |          |buffer where the source text is stored. Based on the source address, the ECC accelerator
+     * |        |          |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
+     * |        |          |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
+     * |        |          |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
+     * |        |          |before triggering START.
+     * @var CRPT_T::ECC_DADDR
+     * Offset: 0xA4C  ECC DMA Destination Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |ECC DMA Destination Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator
+     * |        |          |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
+     * |        |          |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |That is, bit 1 and 0 of DADDR are ignored
+     * |        |          |DADDR can be read and written
+     * |        |          |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
+     * @var CRPT_T::ECC_STARTREG
+     * Offset: 0xA50  ECC Starting Address of Updated Registers
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |STARTREG  |ECC Starting Address of Updated Registers
+     * |        |          |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
+     * |        |          |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG
+     * |        |          |For example, we want to updated input data from register CRPT_ECC POINTX1
+     * |        |          |Thus, the value of STARTREG is 0x808.
+     * @var CRPT_T::ECC_WORDCNT
+     * Offset: 0xA54  ECC DMA Word Count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |WORDCNT   |ECC DMA Word Count
+     * |        |          |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
+     * |        |          |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words
+     * |        |          |CRPT_ECC_WORDCNT can be read and written
+     */
+    __IO uint32_t INTEN;                 /*!< [0x0000] Crypto Interrupt Enable Control Register                         */
+    __IO uint32_t INTSTS;                /*!< [0x0004] Crypto Interrupt Flag                                            */
+    __IO uint32_t PRNG_CTL;              /*!< [0x0008] PRNG Control Register                                            */
+    __O  uint32_t PRNG_SEED;             /*!< [0x000c] Seed for PRNG                                                    */
+    __I  uint32_t PRNG_KEY[8];           /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t AES_FDBCK[4];          /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation     */
+    __I  uint32_t TDES_FDBCKH;           /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
+    __I  uint32_t TDES_FDBCKL;           /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[38];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t AES_CTL;               /*!< [0x0100] AES Control Register                                             */
+    __I  uint32_t AES_STS;               /*!< [0x0104] AES Engine Flag                                                  */
+    __IO uint32_t AES_DATIN;             /*!< [0x0108] AES Engine Data Input Port Register                              */
+    __I  uint32_t AES_DATOUT;            /*!< [0x010c] AES Engine Data Output Port Register                             */
+    __IO uint32_t AES0_KEY[8];           /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0               */
+    __IO uint32_t AES0_IV[4];            /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0  */
+    __IO uint32_t AES0_SADDR;            /*!< [0x0140] AES DMA Source Address Register for Channel 0                    */
+    __IO uint32_t AES0_DADDR;            /*!< [0x0144] AES DMA Destination Address Register for Channel 0               */
+    __IO uint32_t AES0_CNT;              /*!< [0x0148] AES Byte Count Register for Channel 0                            */
+    __IO uint32_t AES1_KEY[8];           /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1               */
+    __IO uint32_t AES1_IV[4];            /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1    */
+    __IO uint32_t AES1_SADDR;            /*!< [0x017c] AES DMA Source Address Register for Channel 1                    */
+    __IO uint32_t AES1_DADDR;            /*!< [0x0180] AES DMA Destination Address Register for Channel 1               */
+    __IO uint32_t AES1_CNT;              /*!< [0x0184] AES Byte Count Register for Channel 1                            */
+    __IO uint32_t AES2_KEY[8];           /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2               */
+    __IO uint32_t AES2_IV[4];            /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2    */
+    __IO uint32_t AES2_SADDR;            /*!< [0x01b8] AES DMA Source Address Register for Channel 2                    */
+    __IO uint32_t AES2_DADDR;            /*!< [0x01bc] AES DMA Destination Address Register for Channel 2               */
+    __IO uint32_t AES2_CNT;              /*!< [0x01c0] AES Byte Count Register for Channel 2                            */
+    __IO uint32_t AES3_KEY[8];           /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3               */
+    __IO uint32_t AES3_IV[4];            /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3    */
+    __IO uint32_t AES3_SADDR;            /*!< [0x01f4] AES DMA Source Address Register for Channel 3                    */
+    __IO uint32_t AES3_DADDR;            /*!< [0x01f8] AES DMA Destination Address Register for Channel 3               */
+    __IO uint32_t AES3_CNT;              /*!< [0x01fc] AES Byte Count Register for Channel 3                            */
+    __IO uint32_t TDES_CTL;              /*!< [0x0200] TDES/DES Control Register                                        */
+    __I  uint32_t TDES_STS;              /*!< [0x0204] TDES/DES Engine Flag                                             */
+    __IO uint32_t TDES0_KEY1H;           /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0                  */
+    __IO uint32_t TDES0_KEY1L;           /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0                   */
+    __IO uint32_t TDES0_KEY2H;           /*!< [0x0210] TDES Key 2 High Word Register for Channel 0                      */
+    __IO uint32_t TDES0_KEY2L;           /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0                       */
+    __IO uint32_t TDES0_KEY3H;           /*!< [0x0218] TDES Key 3 High Word Register for Channel 0                      */
+    __IO uint32_t TDES0_KEY3L;           /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0                       */
+    __IO uint32_t TDES0_IVH;             /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0         */
+    __IO uint32_t TDES0_IVL;             /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0          */
+    __IO uint32_t TDES0_SA;              /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0               */
+    __IO uint32_t TDES0_DA;              /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0          */
+    __IO uint32_t TDES0_CNT;             /*!< [0x0230] TDES/DES Byte Count Register for Channel 0                       */
+    __IO uint32_t TDES_DATIN;            /*!< [0x0234] TDES/DES Engine Input data Word Register                         */
+    __I  uint32_t TDES_DATOUT;           /*!< [0x0238] TDES/DES Engine Output data Word Register                        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES1_KEY1H;           /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1                  */
+    __IO uint32_t TDES1_KEY1L;           /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1                   */
+    __IO uint32_t TDES1_KEY2H;           /*!< [0x0250] TDES Key 2 High Word Register for Channel 1                      */
+    __IO uint32_t TDES1_KEY2L;           /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1                       */
+    __IO uint32_t TDES1_KEY3H;           /*!< [0x0258] TDES Key 3 High Word Register for Channel 1                      */
+    __IO uint32_t TDES1_KEY3L;           /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1                       */
+    __IO uint32_t TDES1_IVH;             /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1         */
+    __IO uint32_t TDES1_IVL;             /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1          */
+    __IO uint32_t TDES1_SA;              /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1               */
+    __IO uint32_t TDES1_DA;              /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1          */
+    __IO uint32_t TDES1_CNT;             /*!< [0x0270] TDES/DES Byte Count Register for Channel 1                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES2_KEY1H;           /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2                  */
+    __IO uint32_t TDES2_KEY1L;           /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2                   */
+    __IO uint32_t TDES2_KEY2H;           /*!< [0x0290] TDES Key 2 High Word Register for Channel 2                      */
+    __IO uint32_t TDES2_KEY2L;           /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2                       */
+    __IO uint32_t TDES2_KEY3H;           /*!< [0x0298] TDES Key 3 High Word Register for Channel 2                      */
+    __IO uint32_t TDES2_KEY3L;           /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2                       */
+    __IO uint32_t TDES2_IVH;             /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2         */
+    __IO uint32_t TDES2_IVL;             /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2          */
+    __IO uint32_t TDES2_SA;              /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2               */
+    __IO uint32_t TDES2_DA;              /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2          */
+    __IO uint32_t TDES2_CNT;             /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES3_KEY1H;           /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3                  */
+    __IO uint32_t TDES3_KEY1L;           /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3                   */
+    __IO uint32_t TDES3_KEY2H;           /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3                      */
+    __IO uint32_t TDES3_KEY2L;           /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3                       */
+    __IO uint32_t TDES3_KEY3H;           /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3                      */
+    __IO uint32_t TDES3_KEY3L;           /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3                       */
+    __IO uint32_t TDES3_IVH;             /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3         */
+    __IO uint32_t TDES3_IVL;             /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3          */
+    __IO uint32_t TDES3_SA;              /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3               */
+    __IO uint32_t TDES3_DA;              /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3          */
+    __IO uint32_t TDES3_CNT;             /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t HMAC_CTL;              /*!< [0x0300] SHA/HMAC Control Register                                        */
+    __I  uint32_t HMAC_STS;              /*!< [0x0304] SHA/HMAC Status Flag                                             */
+    __I  uint32_t HMAC_DGST[16];         /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15                          */
+    __IO uint32_t HMAC_KEYCNT;           /*!< [0x0348] SHA/HMAC Key Byte Count Register                                 */
+    __IO uint32_t HMAC_SADDR;            /*!< [0x034c] SHA/HMAC DMA Source Address Register                             */
+    __IO uint32_t HMAC_DMACNT;           /*!< [0x0350] SHA/HMAC Byte Count Register                                     */
+    __IO uint32_t HMAC_DATIN;            /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE6[298];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t ECC_CTL;               /*!< [0x0800] ECC Control Register                                             */
+    __I  uint32_t ECC_STS;               /*!< [0x0804] ECC Status Register                                              */
+    __IO uint32_t ECC_X1[18];            /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point     */
+    __IO uint32_t ECC_Y1[18];            /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point     */
+    __IO uint32_t ECC_X2[18];            /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_Y2[18];            /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_A[18];             /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_B[18];             /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_N[18];             /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve  */
+    __O  uint32_t ECC_K[18];             /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
+    __IO uint32_t ECC_SADDR;             /*!< [0x0a48] ECC DMA Source Address Register                                  */
+    __IO uint32_t ECC_DADDR;             /*!< [0x0a4c] ECC DMA Destination Address Register                             */
+    __IO uint32_t ECC_STARTREG;          /*!< [0x0a50] ECC Starting Address of Updated Registers                        */
+    __IO uint32_t ECC_WORDCNT;           /*!< [0x0a54] ECC DMA Word Count                                               */
+
+} CRPT_T;
+
+/**
+    @addtogroup CRPT_CONST CRPT Bit Field Definition
+    Constant Definitions for CRPT Controller
+@{ */
+
+#define CRPT_INTEN_AESIEN_Pos            (0)                                               /*!< CRPT_T::INTEN: AESIEN Position         */
+#define CRPT_INTEN_AESIEN_Msk            (0x1ul << CRPT_INTEN_AESIEN_Pos)                  /*!< CRPT_T::INTEN: AESIEN Mask             */
+
+#define CRPT_INTEN_AESEIEN_Pos           (1)                                               /*!< CRPT_T::INTEN: AESEIEN Position        */
+#define CRPT_INTEN_AESEIEN_Msk           (0x1ul << CRPT_INTEN_AESEIEN_Pos)                 /*!< CRPT_T::INTEN: AESEIEN Mask            */
+
+#define CRPT_INTEN_TDESIEN_Pos           (8)                                               /*!< CRPT_T::INTEN: TDESIEN Position        */
+#define CRPT_INTEN_TDESIEN_Msk           (0x1ul << CRPT_INTEN_TDESIEN_Pos)                 /*!< CRPT_T::INTEN: TDESIEN Mask            */
+
+#define CRPT_INTEN_TDESEIEN_Pos          (9)                                               /*!< CRPT_T::INTEN: TDESEIEN Position       */
+#define CRPT_INTEN_TDESEIEN_Msk          (0x1ul << CRPT_INTEN_TDESEIEN_Pos)                /*!< CRPT_T::INTEN: TDESEIEN Mask           */
+
+#define CRPT_INTEN_PRNGIEN_Pos           (16)                                              /*!< CRPT_T::INTEN: PRNGIEN Position        */
+#define CRPT_INTEN_PRNGIEN_Msk           (0x1ul << CRPT_INTEN_PRNGIEN_Pos)                 /*!< CRPT_T::INTEN: PRNGIEN Mask            */
+
+#define CRPT_INTEN_ECCIEN_Pos            (22)                                              /*!< CRPT_T::INTEN: ECCIEN Position         */
+#define CRPT_INTEN_ECCIEN_Msk            (0x1ul << CRPT_INTEN_ECCIEN_Pos)                  /*!< CRPT_T::INTEN: ECCIEN Mask             */
+
+#define CRPT_INTEN_ECCEIEN_Pos           (23)                                              /*!< CRPT_T::INTEN: ECCEIEN Position        */
+#define CRPT_INTEN_ECCEIEN_Msk           (0x1ul << CRPT_INTEN_ECCEIEN_Pos)                 /*!< CRPT_T::INTEN: ECCEIEN Mask            */
+
+#define CRPT_INTEN_HMACIEN_Pos           (24)                                              /*!< CRPT_T::INTEN: HMACIEN Position        */
+#define CRPT_INTEN_HMACIEN_Msk           (0x1ul << CRPT_INTEN_HMACIEN_Pos)                 /*!< CRPT_T::INTEN: HMACIEN Mask            */
+
+#define CRPT_INTEN_HMACEIEN_Pos          (25)                                              /*!< CRPT_T::INTEN: HMACEIEN Position       */
+#define CRPT_INTEN_HMACEIEN_Msk          (0x1ul << CRPT_INTEN_HMACEIEN_Pos)                /*!< CRPT_T::INTEN: HMACEIEN Mask           */
+
+#define CRPT_INTSTS_AESIF_Pos            (0)                                               /*!< CRPT_T::INTSTS: AESIF Position         */
+#define CRPT_INTSTS_AESIF_Msk            (0x1ul << CRPT_INTSTS_AESIF_Pos)                  /*!< CRPT_T::INTSTS: AESIF Mask             */
+
+#define CRPT_INTSTS_AESEIF_Pos           (1)                                               /*!< CRPT_T::INTSTS: AESEIF Position        */
+#define CRPT_INTSTS_AESEIF_Msk           (0x1ul << CRPT_INTSTS_AESEIF_Pos)                 /*!< CRPT_T::INTSTS: AESEIF Mask            */
+
+#define CRPT_INTSTS_TDESIF_Pos           (8)                                               /*!< CRPT_T::INTSTS: TDESIF Position        */
+#define CRPT_INTSTS_TDESIF_Msk           (0x1ul << CRPT_INTSTS_TDESIF_Pos)                 /*!< CRPT_T::INTSTS: TDESIF Mask            */
+
+#define CRPT_INTSTS_TDESEIF_Pos          (9)                                               /*!< CRPT_T::INTSTS: TDESEIF Position       */
+#define CRPT_INTSTS_TDESEIF_Msk          (0x1ul << CRPT_INTSTS_TDESEIF_Pos)                /*!< CRPT_T::INTSTS: TDESEIF Mask           */
+
+#define CRPT_INTSTS_PRNGIF_Pos           (16)                                              /*!< CRPT_T::INTSTS: PRNGIF Position        */
+#define CRPT_INTSTS_PRNGIF_Msk           (0x1ul << CRPT_INTSTS_PRNGIF_Pos)                 /*!< CRPT_T::INTSTS: PRNGIF Mask            */
+
+#define CRPT_INTSTS_ECCIF_Pos            (22)                                              /*!< CRPT_T::INTSTS: ECCIF Position         */
+#define CRPT_INTSTS_ECCIF_Msk            (0x1ul << CRPT_INTSTS_ECCIF_Pos)                  /*!< CRPT_T::INTSTS: ECCIF Mask             */
+
+#define CRPT_INTSTS_ECCEIF_Pos           (23)                                              /*!< CRPT_T::INTSTS: ECCEIF Position        */
+#define CRPT_INTSTS_ECCEIF_Msk           (0x1ul << CRPT_INTSTS_ECCEIF_Pos)                 /*!< CRPT_T::INTSTS: ECCEIF Mask            */
+
+#define CRPT_INTSTS_HMACIF_Pos           (24)                                              /*!< CRPT_T::INTSTS: HMACIF Position        */
+#define CRPT_INTSTS_HMACIF_Msk           (0x1ul << CRPT_INTSTS_HMACIF_Pos)                 /*!< CRPT_T::INTSTS: HMACIF Mask            */
+
+#define CRPT_INTSTS_HMACEIF_Pos          (25)                                              /*!< CRPT_T::INTSTS: HMACEIF Position       */
+#define CRPT_INTSTS_HMACEIF_Msk          (0x1ul << CRPT_INTSTS_HMACEIF_Pos)                /*!< CRPT_T::INTSTS: HMACEIF Mask           */
+
+#define CRPT_PRNG_CTL_START_Pos          (0)                                               /*!< CRPT_T::PRNG_CTL: START Position       */
+#define CRPT_PRNG_CTL_START_Msk          (0x1ul << CRPT_PRNG_CTL_START_Pos)                /*!< CRPT_T::PRNG_CTL: START Mask           */
+
+#define CRPT_PRNG_CTL_SEEDRLD_Pos        (1)                                               /*!< CRPT_T::PRNG_CTL: SEEDRLD Position     */
+#define CRPT_PRNG_CTL_SEEDRLD_Msk        (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)              /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask         */
+
+#define CRPT_PRNG_CTL_KEYSZ_Pos          (2)                                               /*!< CRPT_T::PRNG_CTL: KEYSZ Position       */
+#define CRPT_PRNG_CTL_KEYSZ_Msk          (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos)                /*!< CRPT_T::PRNG_CTL: KEYSZ Mask           */
+
+#define CRPT_PRNG_CTL_BUSY_Pos           (8)                                               /*!< CRPT_T::PRNG_CTL: BUSY Position        */
+#define CRPT_PRNG_CTL_BUSY_Msk           (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)                 /*!< CRPT_T::PRNG_CTL: BUSY Mask            */
+
+#define CRPT_PRNG_SEED_SEED_Pos          (0)                                               /*!< CRPT_T::PRNG_SEED: SEED Position       */
+#define CRPT_PRNG_SEED_SEED_Msk          (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos)         /*!< CRPT_T::PRNG_SEED: SEED Mask           */
+
+#define CRPT_PRNG_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::PRNG_KEY[8]: KEY Position      */
+#define CRPT_PRNG_KEYx_KEY_Msk           (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos)          /*!< CRPT_T::PRNG_KEY[8]: KEY Mask          */
+
+#define CRPT_AES_FDBCKx_FDBCK_Pos        (0)                                               /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position   */
+#define CRPT_AES_FDBCKx_FDBCK_Msk        (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos)       /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask       */
+
+#define CRPT_TDES_FDBCKH_FDBCK_Pos       (0)                                               /*!< CRPT_T::TDES_FDBCKH: FDBCK Position    */
+#define CRPT_TDES_FDBCKH_FDBCK_Msk       (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos)      /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask        */
+
+#define CRPT_TDES_FDBCKL_FDBCK_Pos       (0)                                               /*!< CRPT_T::TDES_FDBCKL: FDBCK Position    */
+#define CRPT_TDES_FDBCKL_FDBCK_Msk       (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos)      /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask        */
+
+#define CRPT_AES_CTL_START_Pos           (0)                                               /*!< CRPT_T::AES_CTL: START Position        */
+#define CRPT_AES_CTL_START_Msk           (0x1ul << CRPT_AES_CTL_START_Pos)                 /*!< CRPT_T::AES_CTL: START Mask            */
+
+#define CRPT_AES_CTL_STOP_Pos            (1)                                               /*!< CRPT_T::AES_CTL: STOP Position         */
+#define CRPT_AES_CTL_STOP_Msk            (0x1ul << CRPT_AES_CTL_STOP_Pos)                  /*!< CRPT_T::AES_CTL: STOP Mask             */
+
+#define CRPT_AES_CTL_KEYSZ_Pos           (2)                                               /*!< CRPT_T::AES_CTL: KEYSZ Position        */
+#define CRPT_AES_CTL_KEYSZ_Msk           (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)                 /*!< CRPT_T::AES_CTL: KEYSZ Mask            */
+
+#define CRPT_AES_CTL_DMALAST_Pos         (5)                                               /*!< CRPT_T::AES_CTL: DMALAST Position      */
+#define CRPT_AES_CTL_DMALAST_Msk         (0x1ul << CRPT_AES_CTL_DMALAST_Pos)               /*!< CRPT_T::AES_CTL: DMALAST Mask          */
+
+#define CRPT_AES_CTL_DMACSCAD_Pos        (6)                                               /*!< CRPT_T::AES_CTL: DMACSCAD Position     */
+#define CRPT_AES_CTL_DMACSCAD_Msk        (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)              /*!< CRPT_T::AES_CTL: DMACSCAD Mask         */
+
+#define CRPT_AES_CTL_DMAEN_Pos           (7)                                               /*!< CRPT_T::AES_CTL: DMAEN Position        */
+#define CRPT_AES_CTL_DMAEN_Msk           (0x1ul << CRPT_AES_CTL_DMAEN_Pos)                 /*!< CRPT_T::AES_CTL: DMAEN Mask            */
+
+#define CRPT_AES_CTL_OPMODE_Pos          (8)                                               /*!< CRPT_T::AES_CTL: OPMODE Position       */
+#define CRPT_AES_CTL_OPMODE_Msk          (0xfful << CRPT_AES_CTL_OPMODE_Pos)               /*!< CRPT_T::AES_CTL: OPMODE Mask           */
+
+#define CRPT_AES_CTL_ENCRPT_Pos          (16)                                              /*!< CRPT_T::AES_CTL: ENCRPT Position       */
+#define CRPT_AES_CTL_ENCRPT_Msk          (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)                /*!< CRPT_T::AES_CTL: ENCRPT Mask           */
+
+#define CRPT_AES_CTL_OUTSWAP_Pos         (22)                                              /*!< CRPT_T::AES_CTL: OUTSWAP Position      */
+#define CRPT_AES_CTL_OUTSWAP_Msk         (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)               /*!< CRPT_T::AES_CTL: OUTSWAP Mask          */
+
+#define CRPT_AES_CTL_INSWAP_Pos          (23)                                              /*!< CRPT_T::AES_CTL: INSWAP Position       */
+#define CRPT_AES_CTL_INSWAP_Msk          (0x1ul << CRPT_AES_CTL_INSWAP_Pos)                /*!< CRPT_T::AES_CTL: INSWAP Mask           */
+
+#define CRPT_AES_CTL_CHANNEL_Pos         (24)                                              /*!< CRPT_T::AES_CTL: CHANNEL Position      */
+#define CRPT_AES_CTL_CHANNEL_Msk         (0x3ul << CRPT_AES_CTL_CHANNEL_Pos)               /*!< CRPT_T::AES_CTL: CHANNEL Mask          */
+
+#define CRPT_AES_CTL_KEYUNPRT_Pos        (26)                                              /*!< CRPT_T::AES_CTL: KEYUNPRT Position     */
+#define CRPT_AES_CTL_KEYUNPRT_Msk        (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)             /*!< CRPT_T::AES_CTL: KEYUNPRT Mask         */
+
+#define CRPT_AES_CTL_KEYPRT_Pos          (31)                                              /*!< CRPT_T::AES_CTL: KEYPRT Position       */
+#define CRPT_AES_CTL_KEYPRT_Msk          (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)                /*!< CRPT_T::AES_CTL: KEYPRT Mask           */
+
+#define CRPT_AES_STS_BUSY_Pos            (0)                                               /*!< CRPT_T::AES_STS: BUSY Position         */
+#define CRPT_AES_STS_BUSY_Msk            (0x1ul << CRPT_AES_STS_BUSY_Pos)                  /*!< CRPT_T::AES_STS: BUSY Mask             */
+
+#define CRPT_AES_STS_INBUFEMPTY_Pos      (8)                                               /*!< CRPT_T::AES_STS: INBUFEMPTY Position   */
+#define CRPT_AES_STS_INBUFEMPTY_Msk      (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)            /*!< CRPT_T::AES_STS: INBUFEMPTY Mask       */
+
+#define CRPT_AES_STS_INBUFFULL_Pos       (9)                                               /*!< CRPT_T::AES_STS: INBUFFULL Position    */
+#define CRPT_AES_STS_INBUFFULL_Msk       (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)             /*!< CRPT_T::AES_STS: INBUFFULL Mask        */
+
+#define CRPT_AES_STS_INBUFERR_Pos        (10)                                              /*!< CRPT_T::AES_STS: INBUFERR Position     */
+#define CRPT_AES_STS_INBUFERR_Msk        (0x1ul << CRPT_AES_STS_INBUFERR_Pos)              /*!< CRPT_T::AES_STS: INBUFERR Mask         */
+
+#define CRPT_AES_STS_CNTERR_Pos          (12)                                              /*!< CRPT_T::AES_STS: CNTERR Position       */
+#define CRPT_AES_STS_CNTERR_Msk          (0x1ul << CRPT_AES_STS_CNTERR_Pos)                /*!< CRPT_T::AES_STS: CNTERR Mask           */
+
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos     (16)                                              /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position  */
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk     (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)           /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask      */
+
+#define CRPT_AES_STS_OUTBUFFULL_Pos      (17)                                              /*!< CRPT_T::AES_STS: OUTBUFFULL Position   */
+#define CRPT_AES_STS_OUTBUFFULL_Msk      (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)            /*!< CRPT_T::AES_STS: OUTBUFFULL Mask       */
+
+#define CRPT_AES_STS_OUTBUFERR_Pos       (18)                                              /*!< CRPT_T::AES_STS: OUTBUFERR Position    */
+#define CRPT_AES_STS_OUTBUFERR_Msk       (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)             /*!< CRPT_T::AES_STS: OUTBUFERR Mask        */
+
+#define CRPT_AES_STS_BUSERR_Pos          (20)                                              /*!< CRPT_T::AES_STS: BUSERR Position       */
+#define CRPT_AES_STS_BUSERR_Msk          (0x1ul << CRPT_AES_STS_BUSERR_Pos)                /*!< CRPT_T::AES_STS: BUSERR Mask           */
+
+#define CRPT_AES_DATIN_DATIN_Pos         (0)                                               /*!< CRPT_T::AES_DATIN: DATIN Position      */
+#define CRPT_AES_DATIN_DATIN_Msk         (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos)        /*!< CRPT_T::AES_DATIN: DATIN Mask          */
+
+#define CRPT_AES_DATOUT_DATOUT_Pos       (0)                                               /*!< CRPT_T::AES_DATOUT: DATOUT Position    */
+#define CRPT_AES_DATOUT_DATOUT_Msk       (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos)      /*!< CRPT_T::AES_DATOUT: DATOUT Mask        */
+
+#define CRPT_AES0_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES0_KEY[8]: KEY Position      */
+#define CRPT_AES0_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos)          /*!< CRPT_T::AES0_KEY[8]: KEY Mask          */
+
+#define CRPT_AES0_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES0_IV[4]: IV Position        */
+#define CRPT_AES0_IVx_IV_Msk             (0xfffffffful << CRPT_AES0_IVx_IV_Pos)            /*!< CRPT_T::AES0_IV[4]: IV Mask            */
+
+#define CRPT_AES0_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES0_SADDR: SADDR Position     */
+#define CRPT_AES0_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos)       /*!< CRPT_T::AES0_SADDR: SADDR Mask         */
+
+#define CRPT_AES0_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES0_DADDR: DADDR Position     */
+#define CRPT_AES0_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos)       /*!< CRPT_T::AES0_DADDR: DADDR Mask         */
+
+#define CRPT_AES0_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES0_CNT: CNT Position         */
+#define CRPT_AES0_CNT_CNT_Msk            (0xfffffffful << CRPT_AES0_CNT_CNT_Pos)           /*!< CRPT_T::AES0_CNT: CNT Mask             */
+
+#define CRPT_AES1_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES1_KEY[8]: KEY Position      */
+#define CRPT_AES1_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos)          /*!< CRPT_T::AES1_KEY[8]: KEY Mask          */
+
+#define CRPT_AES1_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES1_IV[4]: IV Position        */
+#define CRPT_AES1_IVx_IV_Msk             (0xfffffffful << CRPT_AES1_IVx_IV_Pos)            /*!< CRPT_T::AES1_IV[4]: IV Mask            */
+
+#define CRPT_AES1_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES1_SADDR: SADDR Position     */
+#define CRPT_AES1_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos)       /*!< CRPT_T::AES1_SADDR: SADDR Mask         */
+
+#define CRPT_AES1_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES1_DADDR: DADDR Position     */
+#define CRPT_AES1_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos)       /*!< CRPT_T::AES1_DADDR: DADDR Mask         */
+
+#define CRPT_AES1_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES1_CNT: CNT Position         */
+#define CRPT_AES1_CNT_CNT_Msk            (0xfffffffful << CRPT_AES1_CNT_CNT_Pos)           /*!< CRPT_T::AES1_CNT: CNT Mask             */
+
+#define CRPT_AES2_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES2_KEY[8]: KEY Position      */
+#define CRPT_AES2_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos)          /*!< CRPT_T::AES2_KEY[8]: KEY Mask          */
+
+#define CRPT_AES2_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES2_IV[4]: IV Position        */
+#define CRPT_AES2_IVx_IV_Msk             (0xfffffffful << CRPT_AES2_IVx_IV_Pos)            /*!< CRPT_T::AES2_IV[4]: IV Mask            */
+
+#define CRPT_AES2_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES2_SADDR: SADDR Position     */
+#define CRPT_AES2_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos)       /*!< CRPT_T::AES2_SADDR: SADDR Mask         */
+
+#define CRPT_AES2_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES2_DADDR: DADDR Position     */
+#define CRPT_AES2_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos)       /*!< CRPT_T::AES2_DADDR: DADDR Mask         */
+
+#define CRPT_AES2_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES2_CNT: CNT Position         */
+#define CRPT_AES2_CNT_CNT_Msk            (0xfffffffful << CRPT_AES2_CNT_CNT_Pos)           /*!< CRPT_T::AES2_CNT: CNT Mask             */
+
+#define CRPT_AES3_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES3_KEY[8]: KEY Position      */
+#define CRPT_AES3_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos)          /*!< CRPT_T::AES3_KEY[8]: KEY Mask          */
+
+#define CRPT_AES3_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES3_IV[4]: IV Position        */
+#define CRPT_AES3_IVx_IV_Msk             (0xfffffffful << CRPT_AES3_IVx_IV_Pos)            /*!< CRPT_T::AES3_IV[4]: IV Mask            */
+
+#define CRPT_AES3_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES3_SADDR: SADDR Position     */
+#define CRPT_AES3_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos)       /*!< CRPT_T::AES3_SADDR: SADDR Mask         */
+
+#define CRPT_AES3_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES3_DADDR: DADDR Position     */
+#define CRPT_AES3_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos)       /*!< CRPT_T::AES3_DADDR: DADDR Mask         */
+
+#define CRPT_AES3_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES3_CNT: CNT Position         */
+#define CRPT_AES3_CNT_CNT_Msk            (0xfffffffful << CRPT_AES3_CNT_CNT_Pos)           /*!< CRPT_T::AES3_CNT: CNT Mask             */
+
+#define CRPT_TDES_CTL_START_Pos          (0)                                               /*!< CRPT_T::TDES_CTL: START Position       */
+#define CRPT_TDES_CTL_START_Msk          (0x1ul << CRPT_TDES_CTL_START_Pos)                /*!< CRPT_T::TDES_CTL: START Mask           */
+
+#define CRPT_TDES_CTL_STOP_Pos           (1)                                               /*!< CRPT_T::TDES_CTL: STOP Position        */
+#define CRPT_TDES_CTL_STOP_Msk           (0x1ul << CRPT_TDES_CTL_STOP_Pos)                 /*!< CRPT_T::TDES_CTL: STOP Mask            */
+
+#define CRPT_TDES_CTL_TMODE_Pos          (2)                                               /*!< CRPT_T::TDES_CTL: TMODE Position       */
+#define CRPT_TDES_CTL_TMODE_Msk          (0x1ul << CRPT_TDES_CTL_TMODE_Pos)                /*!< CRPT_T::TDES_CTL: TMODE Mask           */
+
+#define CRPT_TDES_CTL_3KEYS_Pos          (3)                                               /*!< CRPT_T::TDES_CTL: 3KEYS Position       */
+#define CRPT_TDES_CTL_3KEYS_Msk          (0x1ul << CRPT_TDES_CTL_3KEYS_Pos)                /*!< CRPT_T::TDES_CTL: 3KEYS Mask           */
+
+#define CRPT_TDES_CTL_DMALAST_Pos        (5)                                               /*!< CRPT_T::TDES_CTL: DMALAST Position     */
+#define CRPT_TDES_CTL_DMALAST_Msk        (0x1ul << CRPT_TDES_CTL_DMALAST_Pos)              /*!< CRPT_T::TDES_CTL: DMALAST Mask         */
+
+#define CRPT_TDES_CTL_DMACSCAD_Pos       (6)                                               /*!< CRPT_T::TDES_CTL: DMACSCAD Position    */
+#define CRPT_TDES_CTL_DMACSCAD_Msk       (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos)             /*!< CRPT_T::TDES_CTL: DMACSCAD Mask        */
+
+#define CRPT_TDES_CTL_DMAEN_Pos          (7)                                               /*!< CRPT_T::TDES_CTL: DMAEN Position       */
+#define CRPT_TDES_CTL_DMAEN_Msk          (0x1ul << CRPT_TDES_CTL_DMAEN_Pos)                /*!< CRPT_T::TDES_CTL: DMAEN Mask           */
+
+#define CRPT_TDES_CTL_OPMODE_Pos         (8)                                               /*!< CRPT_T::TDES_CTL: OPMODE Position      */
+#define CRPT_TDES_CTL_OPMODE_Msk         (0x7ul << CRPT_TDES_CTL_OPMODE_Pos)               /*!< CRPT_T::TDES_CTL: OPMODE Mask          */
+
+#define CRPT_TDES_CTL_ENCRPT_Pos         (16)                                              /*!< CRPT_T::TDES_CTL: ENCRPT Position      */
+#define CRPT_TDES_CTL_ENCRPT_Msk         (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos)               /*!< CRPT_T::TDES_CTL: ENCRPT Mask          */
+
+#define CRPT_TDES_CTL_BLKSWAP_Pos        (21)                                              /*!< CRPT_T::TDES_CTL: BLKSWAP Position     */
+#define CRPT_TDES_CTL_BLKSWAP_Msk        (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos)              /*!< CRPT_T::TDES_CTL: BLKSWAP Mask         */
+
+#define CRPT_TDES_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT_T::TDES_CTL: OUTSWAP Position     */
+#define CRPT_TDES_CTL_OUTSWAP_Msk        (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos)              /*!< CRPT_T::TDES_CTL: OUTSWAP Mask         */
+
+#define CRPT_TDES_CTL_INSWAP_Pos         (23)                                              /*!< CRPT_T::TDES_CTL: INSWAP Position      */
+#define CRPT_TDES_CTL_INSWAP_Msk         (0x1ul << CRPT_TDES_CTL_INSWAP_Pos)               /*!< CRPT_T::TDES_CTL: INSWAP Mask          */
+
+#define CRPT_TDES_CTL_CHANNEL_Pos        (24)                                              /*!< CRPT_T::TDES_CTL: CHANNEL Position     */
+#define CRPT_TDES_CTL_CHANNEL_Msk        (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos)              /*!< CRPT_T::TDES_CTL: CHANNEL Mask         */
+
+#define CRPT_TDES_CTL_KEYUNPRT_Pos       (26)                                              /*!< CRPT_T::TDES_CTL: KEYUNPRT Position    */
+#define CRPT_TDES_CTL_KEYUNPRT_Msk       (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos)            /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask        */
+
+#define CRPT_TDES_CTL_KEYPRT_Pos         (31)                                              /*!< CRPT_T::TDES_CTL: KEYPRT Position      */
+#define CRPT_TDES_CTL_KEYPRT_Msk         (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos)               /*!< CRPT_T::TDES_CTL: KEYPRT Mask          */
+
+#define CRPT_TDES_STS_BUSY_Pos           (0)                                               /*!< CRPT_T::TDES_STS: BUSY Position        */
+#define CRPT_TDES_STS_BUSY_Msk           (0x1ul << CRPT_TDES_STS_BUSY_Pos)                 /*!< CRPT_T::TDES_STS: BUSY Mask            */
+
+#define CRPT_TDES_STS_INBUFEMPTY_Pos     (8)                                               /*!< CRPT_T::TDES_STS: INBUFEMPTY Position  */
+#define CRPT_TDES_STS_INBUFEMPTY_Msk     (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos)           /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask      */
+
+#define CRPT_TDES_STS_INBUFFULL_Pos      (9)                                               /*!< CRPT_T::TDES_STS: INBUFFULL Position   */
+#define CRPT_TDES_STS_INBUFFULL_Msk      (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos)            /*!< CRPT_T::TDES_STS: INBUFFULL Mask       */
+
+#define CRPT_TDES_STS_INBUFERR_Pos       (10)                                              /*!< CRPT_T::TDES_STS: INBUFERR Position    */
+#define CRPT_TDES_STS_INBUFERR_Msk       (0x1ul << CRPT_TDES_STS_INBUFERR_Pos)             /*!< CRPT_T::TDES_STS: INBUFERR Mask        */
+
+#define CRPT_TDES_STS_OUTBUFEMPTY_Pos    (16)                                              /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */
+#define CRPT_TDES_STS_OUTBUFEMPTY_Msk    (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos)          /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask     */
+
+#define CRPT_TDES_STS_OUTBUFFULL_Pos     (17)                                              /*!< CRPT_T::TDES_STS: OUTBUFFULL Position  */
+#define CRPT_TDES_STS_OUTBUFFULL_Msk     (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos)           /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask      */
+
+#define CRPT_TDES_STS_OUTBUFERR_Pos      (18)                                              /*!< CRPT_T::TDES_STS: OUTBUFERR Position   */
+#define CRPT_TDES_STS_OUTBUFERR_Msk      (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos)            /*!< CRPT_T::TDES_STS: OUTBUFERR Mask       */
+
+#define CRPT_TDES_STS_BUSERR_Pos         (20)                                              /*!< CRPT_T::TDES_STS: BUSERR Position      */
+#define CRPT_TDES_STS_BUSERR_Msk         (0x1ul << CRPT_TDES_STS_BUSERR_Pos)               /*!< CRPT_T::TDES_STS: BUSERR Mask          */
+
+#define CRPT_TDES0_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES0_KEYxH: KEY Position      */
+#define CRPT_TDES0_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES0_KEYxH: KEY Mask          */
+
+#define CRPT_TDES0_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES0_KEYxL: KEY Position      */
+#define CRPT_TDES0_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES0_KEYxL: KEY Mask          */
+
+#define CRPT_TDES0_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES0_IVH: IV Position         */
+#define CRPT_TDES0_IVH_IV_Msk            (0xfffffffful << CRPT_TDES0_IVH_IV_Pos)           /*!< CRPT_T::TDES0_IVH: IV Mask             */
+
+#define CRPT_TDES0_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES0_IVL: IV Position         */
+#define CRPT_TDES0_IVL_IV_Msk            (0xfffffffful << CRPT_TDES0_IVL_IV_Pos)           /*!< CRPT_T::TDES0_IVL: IV Mask             */
+
+#define CRPT_TDES0_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES0_SADDR: SADDR Position    */
+#define CRPT_TDES0_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES0_SADDR: SADDR Mask        */
+
+#define CRPT_TDES0_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES0_DADDR: DADDR Position    */
+#define CRPT_TDES0_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES0_DADDR: DADDR Mask        */
+
+#define CRPT_TDES0_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES0_CNT: CNT Position        */
+#define CRPT_TDES0_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos)          /*!< CRPT_T::TDES0_CNT: CNT Mask            */
+
+#define CRPT_TDES_DATIN_DATIN_Pos        (0)                                               /*!< CRPT_T::TDES_DATIN: DATIN Position     */
+#define CRPT_TDES_DATIN_DATIN_Msk        (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos)       /*!< CRPT_T::TDES_DATIN: DATIN Mask         */
+
+#define CRPT_TDES_DATOUT_DATOUT_Pos      (0)                                               /*!< CRPT_T::TDES_DATOUT: DATOUT Position   */
+#define CRPT_TDES_DATOUT_DATOUT_Msk      (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos)     /*!< CRPT_T::TDES_DATOUT: DATOUT Mask       */
+
+#define CRPT_TDES1_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES1_KEYxH: KEY Position      */
+#define CRPT_TDES1_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES1_KEYxH: KEY Mask          */
+
+#define CRPT_TDES1_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES1_KEYxL: KEY Position      */
+#define CRPT_TDES1_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos)        /*!< CRPT_T::TDES1_KEYxL: KEY Mask          */
+
+#define CRPT_TDES1_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES1_IVH: IV Position         */
+#define CRPT_TDES1_IVH_IV_Msk            (0xfffffffful << CRPT_TDES1_IVH_IV_Pos)           /*!< CRPT_T::TDES1_IVH: IV Mask             */
+
+#define CRPT_TDES1_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES1_IVL: IV Position         */
+#define CRPT_TDES1_IVL_IV_Msk            (0xfffffffful << CRPT_TDES1_IVL_IV_Pos)           /*!< CRPT_T::TDES1_IVL: IV Mask             */
+
+#define CRPT_TDES1_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES1_SADDR: SADDR Position    */
+#define CRPT_TDES1_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES1_SADDR: SADDR Mask        */
+
+#define CRPT_TDES1_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES1_DADDR: DADDR Position    */
+#define CRPT_TDES1_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES1_DADDR: DADDR Mask        */
+
+#define CRPT_TDES1_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES1_CNT: CNT Position        */
+#define CRPT_TDES1_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos)          /*!< CRPT_T::TDES1_CNT: CNT Mask            */
+
+#define CRPT_TDES2_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES2_KEYxH: KEY Position      */
+#define CRPT_TDES2_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES2_KEYxH: KEY Mask          */
+
+#define CRPT_TDES2_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES2_KEYxL: KEY Position      */
+#define CRPT_TDES2_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES2_KEYxL: KEY Mask          */
+
+#define CRPT_TDES2_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES2_IVH: IV Position         */
+#define CRPT_TDES2_IVH_IV_Msk            (0xfffffffful << CRPT_TDES2_IVH_IV_Pos)           /*!< CRPT_T::TDES2_IVH: IV Mask             */
+
+#define CRPT_TDES2_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES2_IVL: IV Position         */
+#define CRPT_TDES2_IVL_IV_Msk            (0xfffffffful << CRPT_TDES2_IVL_IV_Pos)           /*!< CRPT_T::TDES2_IVL: IV Mask             */
+
+#define CRPT_TDES2_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES2_SADDR: SADDR Position    */
+#define CRPT_TDES2_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES2_SADDR: SADDR Mask        */
+
+#define CRPT_TDES2_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES2_DADDR: DADDR Position    */
+#define CRPT_TDES2_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES2_DADDR: DADDR Mask        */
+
+#define CRPT_TDES2_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES2_CNT: CNT Position        */
+#define CRPT_TDES2_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos)          /*!< CRPT_T::TDES2_CNT: CNT Mask            */
+
+#define CRPT_TDES3_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES3_KEYxH: KEY Position      */
+#define CRPT_TDES3_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES3_KEYxH: KEY Mask          */
+
+#define CRPT_TDES3_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES3_KEYxL: KEY Position      */
+#define CRPT_TDES3_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES3_KEYxL: KEY Mask          */
+
+#define CRPT_TDES3_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES3_IVH: IV Position         */
+#define CRPT_TDES3_IVH_IV_Msk            (0xfffffffful << CRPT_TDES3_IVH_IV_Pos)           /*!< CRPT_T::TDES3_IVH: IV Mask             */
+
+#define CRPT_TDES3_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES3_IVL: IV Position         */
+#define CRPT_TDES3_IVL_IV_Msk            (0xfffffffful << CRPT_TDES3_IVL_IV_Pos)           /*!< CRPT_T::TDES3_IVL: IV Mask             */
+
+#define CRPT_TDES3_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES3_SADDR: SADDR Position    */
+#define CRPT_TDES3_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES3_SADDR: SADDR Mask        */
+
+#define CRPT_TDES3_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES3_DADDR: DADDR Position    */
+#define CRPT_TDES3_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES3_DADDR: DADDR Mask        */
+
+#define CRPT_TDES3_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES3_CNT: CNT Position        */
+#define CRPT_TDES3_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos)          /*!< CRPT_T::TDES3_CNT: CNT Mask            */
+
+#define CRPT_HMAC_CTL_START_Pos          (0)                                               /*!< CRPT_T::HMAC_CTL: START Position       */
+#define CRPT_HMAC_CTL_START_Msk          (0x1ul << CRPT_HMAC_CTL_START_Pos)                /*!< CRPT_T::HMAC_CTL: START Mask           */
+
+#define CRPT_HMAC_CTL_STOP_Pos           (1)                                               /*!< CRPT_T::HMAC_CTL: STOP Position        */
+#define CRPT_HMAC_CTL_STOP_Msk           (0x1ul << CRPT_HMAC_CTL_STOP_Pos)                 /*!< CRPT_T::HMAC_CTL: STOP Mask            */
+
+#define CRPT_HMAC_CTL_HMACEN_Pos         (4)                                               /*!< CRPT_T::HMAC_CTL: HMACEN Position      */
+#define CRPT_HMAC_CTL_HMACEN_Msk         (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos)               /*!< CRPT_T::HMAC_CTL: HMACEN Mask          */
+
+#define CRPT_HMAC_CTL_DMALAST_Pos        (5)                                               /*!< CRPT_T::HMAC_CTL: DMALAST Position     */
+#define CRPT_HMAC_CTL_DMALAST_Msk        (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos)              /*!< CRPT_T::HMAC_CTL: DMALAST Mask         */
+
+#define CRPT_HMAC_CTL_DMAEN_Pos          (7)                                               /*!< CRPT_T::HMAC_CTL: DMAEN Position       */
+#define CRPT_HMAC_CTL_DMAEN_Msk          (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos)                /*!< CRPT_T::HMAC_CTL: DMAEN Mask           */
+
+#define CRPT_HMAC_CTL_OPMODE_Pos         (8)                                               /*!< CRPT_T::HMAC_CTL: OPMODE Position      */
+#define CRPT_HMAC_CTL_OPMODE_Msk         (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos)               /*!< CRPT_T::HMAC_CTL: OPMODE Mask          */
+
+#define CRPT_HMAC_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT_T::HMAC_CTL: OUTSWAP Position     */
+#define CRPT_HMAC_CTL_OUTSWAP_Msk        (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos)              /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask         */
+
+#define CRPT_HMAC_CTL_INSWAP_Pos         (23)                                              /*!< CRPT_T::HMAC_CTL: INSWAP Position      */
+#define CRPT_HMAC_CTL_INSWAP_Msk         (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos)               /*!< CRPT_T::HMAC_CTL: INSWAP Mask          */
+
+#define CRPT_HMAC_STS_BUSY_Pos           (0)                                               /*!< CRPT_T::HMAC_STS: BUSY Position        */
+#define CRPT_HMAC_STS_BUSY_Msk           (0x1ul << CRPT_HMAC_STS_BUSY_Pos)                 /*!< CRPT_T::HMAC_STS: BUSY Mask            */
+
+#define CRPT_HMAC_STS_DMABUSY_Pos        (1)                                               /*!< CRPT_T::HMAC_STS: DMABUSY Position     */
+#define CRPT_HMAC_STS_DMABUSY_Msk        (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos)              /*!< CRPT_T::HMAC_STS: DMABUSY Mask         */
+
+#define CRPT_HMAC_STS_DMAERR_Pos         (8)                                               /*!< CRPT_T::HMAC_STS: DMAERR Position      */
+#define CRPT_HMAC_STS_DMAERR_Msk         (0x1ul << CRPT_HMAC_STS_DMAERR_Pos)               /*!< CRPT_T::HMAC_STS: DMAERR Mask          */
+
+#define CRPT_HMAC_STS_DATINREQ_Pos       (16)                                              /*!< CRPT_T::HMAC_STS: DATINREQ Position    */
+#define CRPT_HMAC_STS_DATINREQ_Msk       (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos)             /*!< CRPT_T::HMAC_STS: DATINREQ Mask        */
+
+#define CRPT_HMAC_DGSTx_DGST_Pos         (0)                                               /*!< CRPT_T::HMAC_DGST[16]: DGST Position   */
+#define CRPT_HMAC_DGSTx_DGST_Msk         (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos)        /*!< CRPT_T::HMAC_DGST[16]: DGST Mask       */
+
+#define CRPT_HMAC_KEYCNT_KEYCNT_Pos      (0)                                               /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position   */
+#define CRPT_HMAC_KEYCNT_KEYCNT_Msk      (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos)     /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask       */
+
+#define CRPT_HMAC_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::HMAC_SADDR: SADDR Position     */
+#define CRPT_HMAC_SADDR_SADDR_Msk        (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos)       /*!< CRPT_T::HMAC_SADDR: SADDR Mask         */
+
+#define CRPT_HMAC_DMACNT_DMACNT_Pos      (0)                                               /*!< CRPT_T::HMAC_DMACNT: DMACNT Position   */
+#define CRPT_HMAC_DMACNT_DMACNT_Msk      (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos)     /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask       */
+
+#define CRPT_HMAC_DATIN_DATIN_Pos        (0)                                               /*!< CRPT_T::HMAC_DATIN: DATIN Position     */
+#define CRPT_HMAC_DATIN_DATIN_Msk        (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos)       /*!< CRPT_T::HMAC_DATIN: DATIN Mask         */
+
+#define CRPT_ECC_CTL_START_Pos           (0)                                               /*!< CRPT_T::ECC_CTL: START Position        */
+#define CRPT_ECC_CTL_START_Msk           (0x1ul << CRPT_ECC_CTL_START_Pos)                 /*!< CRPT_T::ECC_CTL: START Mask            */
+
+#define CRPT_ECC_CTL_STOP_Pos            (1)                                               /*!< CRPT_T::ECC_CTL: STOP Position         */
+#define CRPT_ECC_CTL_STOP_Msk            (0x1ul << CRPT_ECC_CTL_STOP_Pos)                  /*!< CRPT_T::ECC_CTL: STOP Mask             */
+
+#define CRPT_ECC_CTL_DMAEN_Pos           (7)                                               /*!< CRPT_T::ECC_CTL: DMAEN Position        */
+#define CRPT_ECC_CTL_DMAEN_Msk           (0x1ul << CRPT_ECC_CTL_DMAEN_Pos)                 /*!< CRPT_T::ECC_CTL: DMAEN Mask            */
+
+#define CRPT_ECC_CTL_FSEL_Pos            (8)                                               /*!< CRPT_T::ECC_CTL: FSEL Position         */
+#define CRPT_ECC_CTL_FSEL_Msk            (0x1ul << CRPT_ECC_CTL_FSEL_Pos)                  /*!< CRPT_T::ECC_CTL: FSEL Mask             */
+
+#define CRPT_ECC_CTL_ECCOP_Pos           (9)                                               /*!< CRPT_T::ECC_CTL: ECCOP Position        */
+#define CRPT_ECC_CTL_ECCOP_Msk           (0x3ul << CRPT_ECC_CTL_ECCOP_Pos)                 /*!< CRPT_T::ECC_CTL: ECCOP Mask            */
+
+#define CRPT_ECC_CTL_MODOP_Pos           (11)                                              /*!< CRPT_T::ECC_CTL: MODOP Position        */
+#define CRPT_ECC_CTL_MODOP_Msk           (0x3ul << CRPT_ECC_CTL_MODOP_Pos)                 /*!< CRPT_T::ECC_CTL: MODOP Mask            */
+
+#define CRPT_ECC_CTL_LDP1_Pos            (16)                                              /*!< CRPT_T::ECC_CTL: LDP1 Position         */
+#define CRPT_ECC_CTL_LDP1_Msk            (0x1ul << CRPT_ECC_CTL_LDP1_Pos)                  /*!< CRPT_T::ECC_CTL: LDP1 Mask             */
+
+#define CRPT_ECC_CTL_LDP2_Pos            (17)                                              /*!< CRPT_T::ECC_CTL: LDP2 Position         */
+#define CRPT_ECC_CTL_LDP2_Msk            (0x1ul << CRPT_ECC_CTL_LDP2_Pos)                  /*!< CRPT_T::ECC_CTL: LDP2 Mask             */
+
+#define CRPT_ECC_CTL_LDA_Pos             (18)                                              /*!< CRPT_T::ECC_CTL: LDA Position          */
+#define CRPT_ECC_CTL_LDA_Msk             (0x1ul << CRPT_ECC_CTL_LDA_Pos)                   /*!< CRPT_T::ECC_CTL: LDA Mask              */
+
+#define CRPT_ECC_CTL_LDB_Pos             (19)                                              /*!< CRPT_T::ECC_CTL: LDB Position          */
+#define CRPT_ECC_CTL_LDB_Msk             (0x1ul << CRPT_ECC_CTL_LDB_Pos)                   /*!< CRPT_T::ECC_CTL: LDB Mask              */
+
+#define CRPT_ECC_CTL_LDN_Pos             (20)                                              /*!< CRPT_T::ECC_CTL: LDN Position          */
+#define CRPT_ECC_CTL_LDN_Msk             (0x1ul << CRPT_ECC_CTL_LDN_Pos)                   /*!< CRPT_T::ECC_CTL: LDN Mask              */
+
+#define CRPT_ECC_CTL_LDK_Pos             (21)                                              /*!< CRPT_T::ECC_CTL: LDK Position          */
+#define CRPT_ECC_CTL_LDK_Msk             (0x1ul << CRPT_ECC_CTL_LDK_Pos)                   /*!< CRPT_T::ECC_CTL: LDK Mask              */
+
+#define CRPT_ECC_CTL_CURVEM_Pos          (22)                                              /*!< CRPT_T::ECC_CTL: CURVEM Position       */
+#define CRPT_ECC_CTL_CURVEM_Msk          (0x3fful << CRPT_ECC_CTL_CURVEM_Pos)              /*!< CRPT_T::ECC_CTL: CURVEM Mask           */
+
+#define CRPT_ECC_STS_BUSY_Pos            (0)                                               /*!< CRPT_T::ECC_STS: BUSY Position         */
+#define CRPT_ECC_STS_BUSY_Msk            (0x1ul << CRPT_ECC_STS_BUSY_Pos)                  /*!< CRPT_T::ECC_STS: BUSY Mask             */
+
+#define CRPT_ECC_STS_DMABUSY_Pos         (1)                                               /*!< CRPT_T::ECC_STS: DMABUSY Position      */
+#define CRPT_ECC_STS_DMABUSY_Msk         (0x1ul << CRPT_ECC_STS_DMABUSY_Pos)               /*!< CRPT_T::ECC_STS: DMABUSY Mask          */
+
+#define CRPT_ECC_STS_BUSERR_Pos          (16)                                              /*!< CRPT_T::ECC_STS: BUSERR Position       */
+#define CRPT_ECC_STS_BUSERR_Msk          (0x1ul << CRPT_ECC_STS_BUSERR_Pos)                /*!< CRPT_T::ECC_STS: BUSERR Mask           */
+
+#define CRPT_ECC_X1_POINTX1_Pos          (0)                                               /*!< CRPT_T::ECC_X1[18]:  POINTX1 Position  */
+#define CRPT_ECC_X1_POINTX1_Msk          (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos)         /*!< CRPT_T::ECC_X1[18]:  POINTX1 Mask      */
+
+#define CRPT_ECC_Y1_POINTY1_Pos          (0)                                               /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position   */
+#define CRPT_ECC_Y1_POINTY1_Msk          (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos)         /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask       */
+
+#define CRPT_ECC_X2_POINTX2_Pos          (0)                                               /*!< CRPT_T::ECC_X2[18]: POINTX2 Position   */
+#define CRPT_ECC_X2_POINTX2_Msk          (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos)         /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask       */
+
+#define CRPT_ECC_Y2_POINTY2_Pos          (0)                                               /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position   */
+#define CRPT_ECC_Y2_POINTY2_Msk          (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos)         /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask       */
+
+#define CRPT_ECC_A_CURVEA_Pos            (0)                                               /*!< CRPT_T::ECC_A[18]: CURVEA Position     */
+#define CRPT_ECC_A_CURVEA_Msk            (0xfffffffful << CRPT_ECC_A_CURVEA_Pos)           /*!< CRPT_T::ECC_A[18]: CURVEA Mask         */
+
+#define CRPT_ECC_B_CURVEB_Pos            (0)                                               /*!< CRPT_T::ECC_B[18]: CURVEB Position     */
+#define CRPT_ECC_B_CURVEB_Msk            (0xfffffffful << CRPT_ECC_B_CURVEB_Pos)           /*!< CRPT_T::ECC_B[18]: CURVEB Mask         */
+
+#define CRPT_ECC_N_CURVEN_Pos            (0)                                               /*!< CRPT_T::ECC_N[18]: CURVEN Position     */
+#define CRPT_ECC_N_CURVEN_Msk            (0xfffffffful << CRPT_ECC_N_CURVEN_Pos)           /*!< CRPT_T::ECC_N[18]: CURVEN Mask         */
+
+#define CRPT_ECC_K_SCALARK_Pos           (0)                                               /*!< CRPT_T::ECC_K[18]: SCALARK Position    */
+#define CRPT_ECC_K_SCALARK_Msk           (0xfffffffful << CRPT_ECC_K_SCALARK_Pos)          /*!< CRPT_T::ECC_K[18]: SCALARK Mask        */
+
+#define CRPT_ECC_DADDR_DADDR_Pos         (0)                                               /*!< CRPT_T::ECC_DADDR: DADDR Position      */
+#define CRPT_ECC_DADDR_DADDR_Msk         (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos)        /*!< CRPT_T::ECC_DADDR: DADDR Mask          */
+
+#define CRPT_ECC_STARTREG_STARTREG_Pos   (0)                                               /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
+#define CRPT_ECC_STARTREG_STARTREG_Msk   (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos)  /*!< CRPT_T::ECC_STARTREG: STARTREG Mask    */
+
+#define CRPT_ECC_WORDCNT_WORDCNT_Pos     (0)                                               /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position  */
+#define CRPT_ECC_WORDCNT_WORDCNT_Msk     (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos)    /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask      */
+
+/**@}*/ /* CRPT_CONST CRYPTO */
+/**@}*/ /* end of CRYPTO register group */
+
+
+
+/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
+/**
+    @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
+    Memory Mapped Structure for EADC Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var EADC_T::DAT[19]
+     * Offset: 0x00  ADC Data Register 0~18 for Sample Module 0~18
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RESULT    |ADC Conversion Result
+     * |        |          |This field contains 12 bits conversion result.
+     * |        |          |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
+     * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
+     * |[16]    |OV        |Overrun Flag
+     * |        |          |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+     * |        |          |0 = Data in RESULT[11:0] is recent conversion result.
+     * |        |          |1 = Data in RESULT[11:0] is overwrite.
+     * |        |          |Note: It is cleared by hardware after EADC_DAT register is read.
+     * |[17]    |VALID     |Valid Flag
+     * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
+     * |        |          |0 = Data in RESULT[11:0] bits is not valid.
+     * |        |          |1 = Data in RESULT[11:0] bits is valid.
+     * @var EADC_T::CURDAT
+     * Offset: 0x4C  ADC PDMA Current Transfer Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[17:0]  |CURDAT    |ADC PDMA Current Transfer Data Register
+     * |        |          |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
+     * |        |          |This is a read only register.
+     * @var EADC_T::CTL
+     * Offset: 0x50  ADC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADCEN     |ADC Converter Enable Bit
+     * |        |          |0 = Disabled EADC.
+     * |        |          |1 = Enabled EADC.
+     * |        |          |Note: Before starting ADC conversion function, this bit should be set to 1
+     * |        |          |Clear it to 0 to disable ADC converter analog circuit power consumption.
+     * |[1]     |ADCRST    |ADC Converter Control Circuits Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
+     * |        |          |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+     * |[2]     |ADCIEN0   |Specific Sample Module ADC ADINT0 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT0 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT0 interrupt function Enabled.
+     * |[3]     |ADCIEN1   |Specific Sample Module ADC ADINT1 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT1 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT1 interrupt function Enabled.
+     * |[4]     |ADCIEN2   |Specific Sample Module ADC ADINT2 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT2 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT2 interrupt function Enabled.
+     * |[5]     |ADCIEN3   |Specific Sample Module ADC ADINT3 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT3 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT3 interrupt function Enabled.
+     * |[7:6]   |RESSEL    |Resolution Selection
+     * |        |          |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).
+     * |        |          |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).
+     * |        |          |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).
+     * |        |          |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).
+     * |[8]     |DIFFEN    |Differential Analog Input Mode Enable Bit
+     * |        |          |0 = Single-end analog input mode.
+     * |        |          |1 = Differential analog input mode.
+     * |[9]     |DMOF      |ADC Differential Input Mode Output Format
+     * |        |          |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
+     * |        |          |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
+     * |[11]    |PDMAEN    |PDMA Transfer Enable Bit
+     * |        |          |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
+     * |        |          |0 = PDMA data transfer Disabled.
+     * |        |          |1 = PDMA data transfer Enabled.
+     * |        |          |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+     * @var EADC_T::SWTRG
+     * Offset: 0x54  ADC Sample Module Software Start Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |SWTRG     |ADC Sample Module 0~18 Software Force to Start ADC Conversion
+     * |        |          |0 = No effect.
+     * |        |          |1 = Cause an ADC conversion when the priority is given to sample module.
+     * |        |          |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
+     * |        |          |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+     * @var EADC_T::PENDSTS
+     * Offset: 0x58  ADC Start of Conversion Pending Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |STPF      |ADC Sample Module 0~18 Start of Conversion Pending Flag
+     * |        |          |Read:
+     * |        |          |0 = There is no pending conversion for sample module.
+     * |        |          |1 = Sample module ADC start of conversion is pending.
+     * |        |          |Write:
+     * |        |          |1 = clear pending flag & cancel the conversion for sample module.
+     * |        |          |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
+     * @var EADC_T::OVSTS
+     * Offset: 0x5C  ADC Sample Module Start of Conversion Overrun Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |SPOVF     |ADC SAMPLE0~18 Overrun Flag
+     * |        |          |0 = No sample module event overrun.
+     * |        |          |1 = Indicates a new sample module event is generated while an old one event is pending.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var EADC_T::SCTL[19]
+     * Offset: 0x80  ADC Sample Module 0~18 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CHSEL     |ADC Sample Module Channel Selection
+     * |        |          |00H = EADC_CH0 (slow channel).
+     * |        |          |01H = EADC_CH1 (slow channel).
+     * |        |          |02H = EADC_CH2 (slow channel).
+     * |        |          |03H = EADC_CH3 (slow channel).
+     * |        |          |04H = EADC_CH4 (slow channel).
+     * |        |          |05H = EADC_CH5 (slow channel).
+     * |        |          |06H = EADC_CH6 (slow channel).
+     * |        |          |07H = EADC_CH7 (slow channel).
+     * |        |          |08H = EADC_CH8 (slow channel).
+     * |        |          |09H = EADC_CH9 (slow channel).
+     * |        |          |0AH = EADC_CH10 (fast channel).
+     * |        |          |0BH = EADC_CH11 (fast channel).
+     * |        |          |0CH = EADC_CH12 (fast channel).
+     * |        |          |0DH = EADC_CH13 (fast channel).
+     * |        |          |0EH = EADC_CH14 (fast channel).
+     * |        |          |0FH = EADC_CH15 (fast channel).
+     * |[4]     |EXTREN    |ADC External Trigger Rising Edge Enable Bit
+     * |        |          |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.
+     * |        |          |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.
+     * |[5]     |EXTFEN    |ADC External Trigger Falling Edge Enable Bit
+     * |        |          |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.
+     * |        |          |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.
+     * |[7:6]   |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
+     * |        |          |Trigger delay clock frequency:
+     * |        |          |00 = ADC_CLK/1.
+     * |        |          |01 = ADC_CLK/2.
+     * |        |          |10 = ADC_CLK/4.
+     * |        |          |11 = ADC_CLK/16.
+     * |[15:8]  |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time
+     * |        |          |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+     * |[20:16] |TRGSEL    |ADC Sample Module Start of Conversion Trigger Source Selection
+     * |        |          |0H = Disable trigger.
+     * |        |          |1H = External trigger from EADC0_ST pin input.
+     * |        |          |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
+     * |        |          |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
+     * |        |          |4H = Timer0 overflow pulse trigger.
+     * |        |          |5H = Timer1 overflow pulse trigger.
+     * |        |          |6H = Timer2 overflow pulse trigger.
+     * |        |          |7H = Timer3 overflow pulse trigger.
+     * |        |          |8H = EPWM0TG0.
+     * |        |          |9H = EPWM0TG1.
+     * |        |          |AH = EPWM0TG2.
+     * |        |          |BH = EPWM0TG3.
+     * |        |          |CH = EPWM0TG4.
+     * |        |          |DH = EPWM0TG5.
+     * |        |          |EH = EPWM1TG0.
+     * |        |          |FH = EPWM1TG1.
+     * |        |          |10H = EPWM1TG2.
+     * |        |          |11H = EPWM1TG3.
+     * |        |          |12H = EPWM1TG4.
+     * |        |          |13H = EPWM1TG5.
+     * |        |          |14H = BPWM0TG.
+     * |        |          |15H = BPWM1TG.
+     * |        |          |other = Reserved.
+     * |[22]    |INTPOS    |Interrupt Flag Position Select
+     * |        |          |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.
+     * |        |          |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.
+     * |[23]    |DBMEN     |Double Buffer Mode Enable Bit
+     * |        |          |0 = Sample has one sample result register. (default).
+     * |        |          |1 = Sample has two sample result registers.
+     * |[31:24] |EXTSMPT   |ADC Sampling Time Extend
+     * |        |          |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
+     * |        |          |The range of start delay time is from 0~255 ADC clock.
+     * @var EADC_T::INTSRC[4]
+     * Offset: 0xD0  ADC interrupt 0~3 Source Enable Control Register.
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPLIE0    |Sample Module 0 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 0 interrupt Disabled.
+     * |        |          |1 = Sample Module 0 interrupt Enabled.
+     * |[1]     |SPLIE1    |Sample Module 1 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 1 interrupt Disabled.
+     * |        |          |1 = Sample Module 1 interrupt Enabled.
+     * |[2]     |SPLIE2    |Sample Module 2 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 2 interrupt Disabled.
+     * |        |          |1 = Sample Module 2 interrupt Enabled.
+     * |[3]     |SPLIE3    |Sample Module 3 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 3 interrupt Disabled.
+     * |        |          |1 = Sample Module 3 interrupt Enabled.
+     * |[4]     |SPLIE4    |Sample Module 4 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 4 interrupt Disabled.
+     * |        |          |1 = Sample Module 4 interrupt Enabled.
+     * |[5]     |SPLIE5    |Sample Module 5 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 5 interrupt Disabled.
+     * |        |          |1 = Sample Module 5 interrupt Enabled.
+     * |[6]     |SPLIE6    |Sample Module 6 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 6 interrupt Disabled.
+     * |        |          |1 = Sample Module 6 interrupt Enabled.
+     * |[7]     |SPLIE7    |Sample Module 7 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 7 interrupt Disabled.
+     * |        |          |1 = Sample Module 7 interrupt Enabled.
+     * |[8]     |SPLIE8    |Sample Module 8 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 8 interrupt Disabled.
+     * |        |          |1 = Sample Module 8 interrupt Enabled.
+     * |[9]     |SPLIE9    |Sample Module 9 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 9 interrupt Disabled.
+     * |        |          |1 = Sample Module 9 interrupt Enabled.
+     * |[10]    |SPLIE10   |Sample Module 10 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 10 interrupt Disabled.
+     * |        |          |1 = Sample Module 10 interrupt Enabled.
+     * |[11]    |SPLIE11   |Sample Module 11 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 11 interrupt Disabled.
+     * |        |          |1 = Sample Module 11 interrupt Enabled.
+     * |[12]    |SPLIE12   |Sample Module 12 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 12 interrupt Disabled.
+     * |        |          |1 = Sample Module 12 interrupt Enabled.
+     * |[13]    |SPLIE13   |Sample Module 13 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 13 interrupt Disabled.
+     * |        |          |1 = Sample Module 13 interrupt Enabled.
+     * |[14]    |SPLIE14   |Sample Module 14 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 14 interrupt Disabled.
+     * |        |          |1 = Sample Module 14 interrupt Enabled.
+     * |[15]    |SPLIE15   |Sample Module 15 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 15 interrupt Disabled.
+     * |        |          |1 = Sample Module 15 interrupt Enabled.
+     * |[16]    |SPLIE16   |Sample Module 16 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 16 interrupt Disabled.
+     * |        |          |1 = Sample Module 16 interrupt Enabled.
+     * |[17]    |SPLIE17   |Sample Module 17 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 17 interrupt Disabled.
+     * |        |          |1 = Sample Module 17 interrupt Enabled.
+     * |[18]    |SPLIE18   |Sample Module 18 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 18 interrupt Disabled.
+     * |        |          |1 = Sample Module 18 interrupt Enabled.
+     * @var EADC_T::CMP[4]
+     * Offset: 0xE0  ADC Result Compare Register 0~3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADCMPEN   |ADC Result Compare Enable Bit
+     * |        |          |0 = Compare Disabled.
+     * |        |          |1 = Compare Enabled.
+     * |        |          |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
+     * |[1]     |ADCMPIE   |ADC Result Compare Interrupt Enable Bit
+     * |        |          |0 = Compare function interrupt Disabled.
+     * |        |          |1 = Compare function interrupt Enabled.
+     * |        |          |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
+     * |[2]     |CMPCOND   |Compare Condition
+     * |        |          |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+     * |        |          |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+     * |        |          |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
+     * |[7:3]   |CMPSPL    |Compare Sample Module Selection
+     * |        |          |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
+     * |        |          |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
+     * |        |          |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
+     * |        |          |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
+     * |        |          |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
+     * |        |          |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
+     * |        |          |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
+     * |        |          |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
+     * |        |          |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
+     * |        |          |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
+     * |        |          |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
+     * |        |          |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
+     * |        |          |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
+     * |        |          |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
+     * |        |          |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
+     * |        |          |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
+     * |        |          |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
+     * |        |          |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
+     * |        |          |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
+     * |[11:8]  |CMPMCNT   |Compare Match Count
+     * |        |          |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
+     * |        |          |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
+     * |        |          |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
+     * |[15]    |CMPWEN    |Compare Window Mode Enable Bit
+     * |        |          |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
+     * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
+     * |        |          |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
+     * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+     * |        |          |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
+     * |[27:16] |CMPDAT    |Comparison Data
+     * |        |          |The 12 bits data is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
+     * @var EADC_T::STATUS0
+     * Offset: 0xF0  ADC Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |VALID     |EADC_DAT0~15 Data Valid Flag
+     * |        |          |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * |[31:16] |OV        |EADC_DAT0~15 Overrun Flag
+     * |        |          |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * @var EADC_T::STATUS1
+     * Offset: 0xF4  ADC Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |VALID     |EADC_DAT16~18 Data Valid Flag
+     * |        |          |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * |[18:16] |OV        |EADC_DAT16~18 Overrun Flag
+     * |        |          |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * @var EADC_T::STATUS2
+     * Offset: 0xF8  ADC Status Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADIF0     |ADC ADINT0 Interrupt Flag
+     * |        |          |0 = No ADINT0 interrupt pulse received.
+     * |        |          |1 = ADINT0 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[1]     |ADIF1     |ADC ADINT1 Interrupt Flag
+     * |        |          |0 = No ADINT1 interrupt pulse received.
+     * |        |          |1 = ADINT1 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[2]     |ADIF2     |ADC ADINT2 Interrupt Flag
+     * |        |          |0 = No ADINT2 interrupt pulse received.
+     * |        |          |1 = ADINT2 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[3]     |ADIF3     |ADC ADINT3 Interrupt Flag
+     * |        |          |0 = No ADINT3 interrupt pulse received.
+     * |        |          |1 = ADINT3 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[4]     |ADCMPF0   |ADC Compare 0 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[5]     |ADCMPF1   |ADC Compare 1 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[6]     |ADCMPF2   |ADC Compare 2 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[7]     |ADCMPF3   |ADC Compare 3 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[8]     |ADOVIF0   |ADC ADINT0 Interrupt Flag Overrun
+     * |        |          |0 = ADINT0 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT0 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[9]     |ADOVIF1   |ADC ADINT1 Interrupt Flag Overrun
+     * |        |          |0 = ADINT1 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT1 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[10]    |ADOVIF2   |ADC ADINT2 Interrupt Flag Overrun
+     * |        |          |0 = ADINT2 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT2 interrupt flag is s overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[11]    |ADOVIF3   |ADC ADINT3 Interrupt Flag Overrun
+     * |        |          |0 = ADINT3 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT3 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[12]    |ADCMPO0   |ADC Compare 0 Output Status (Read Only)
+     * |        |          |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
+     * |[13]    |ADCMPO1   |ADC Compare 1 Output Status (Read Only)
+     * |        |          |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
+     * |[14]    |ADCMPO2   |ADC Compare 2 Output Status (Read Only)
+     * |        |          |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
+     * |[15]    |ADCMPO3   |ADC Compare 3 Output Status (Read Only)
+     * |        |          |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
+     * |[20:16] |CHANNEL   |Current Conversion Channel (Read Only)
+     * |        |          |This filed reflects ADC current conversion channel when BUSY=1.
+     * |        |          |It is read only.
+     * |        |          |00H = EADC_CH0.
+     * |        |          |01H = EADC_CH1.
+     * |        |          |02H = EADC_CH2.
+     * |        |          |03H = EADC_CH3.
+     * |        |          |04H = EADC_CH4.
+     * |        |          |05H = EADC_CH5.
+     * |        |          |06H = EADC_CH6.
+     * |        |          |07H = EADC_CH7.
+     * |        |          |08H = EADC_CH8.
+     * |        |          |09H = EADC_CH9.
+     * |        |          |0AH = EADC_CH10.
+     * |        |          |0BH = EADC_CH11.
+     * |        |          |0CH = EADC_CH12.
+     * |        |          |0DH = EADC_CH13.
+     * |        |          |0EH = EADC_CH14.
+     * |        |          |0FH = EADC_CH15.
+     * |        |          |10H = VBG.
+     * |        |          |11H = VTEMP.
+     * |        |          |12H = VBAT/4.
+     * |[23]    |BUSY      |Busy/Idle (Read Only)
+     * |        |          |0 = EADC is in idle state.
+     * |        |          |1 = EADC is busy at conversion.
+     * |[24]    |ADOVIF    |All ADC Interrupt Flag Overrun Bits Check (Read Only)
+     * |        |          |n=0~3.
+     * |        |          |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+     * |        |          |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+     * |        |          |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
+     * |[25]    |STOVF     |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+     * |        |          |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
+     * |[26]    |AVALID    |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+     * |        |          |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
+     * |[27]    |AOV       |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+     * |        |          |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any OVn Flag is equal to 1.
+     * @var EADC_T::STATUS3
+     * Offset: 0xFC  ADC Status Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |CURSPL    |ADC Current Sample Module
+     * |        |          |This register show the current ADC is controlled by which sample module control logic modules.
+     * |        |          |If the ADC is Idle, this bit filed will set to 0x1F.
+     * |        |          |This is a read only register.
+     * @var EADC_T::DDAT[4]
+     * Offset: 0x100  ADC Double Data Register 0 for Sample Module 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RESULT    |ADC Conversion Results
+     * |        |          |This field contains 12 bits conversion results.
+     * |        |          |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
+     * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
+     * |[16]    |OV        |Overrun Flag
+     * |        |          |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
+     * |        |          |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
+     * |        |          |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1
+     * |        |          |It is cleared by hardware after EADC_DDAT register is read.
+     * |[17]    |VALID     |Valid Flag
+     * |        |          |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
+     * |        |          |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
+     * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read
+     * |        |          |(n=0~3).
+     * @var EADC_T::PWRM
+     * Offset: 0x110  ADC Power Management Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PWUPRDY   |ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
+     * |        |          |0 = ADC is not ready for conversion may be in power down state or in the progress of start up.
+     * |        |          |1 = ADC is ready for conversion.
+     * |[1]     |PWUCALEN  |Power Up Calibration Function Enable Control
+     * |        |          |0 = Disable the function of calibration at power up.
+     * |        |          |1 = Enable the function of calibration at power up.
+     * |        |          |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following
+     * |        |          |{PWUCALEN, CALSEL } Description:
+     * |        |          |PWUCALEN is 0 and CALSEL is 0: No need to calibrate.
+     * |        |          |PWUCALEN is 0 and CALSEL is 1: No need to calibrate.
+     * |        |          |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.
+     * |        |          |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
+     * |[3:2]   |PWDMOD    |ADC Power-down Mode
+     * |        |          |Set this bit fields to select ADC power down mode when system power-down.
+     * |        |          |00 = ADC Deep power down mode.
+     * |        |          |01 = ADC Power down.
+     * |        |          |10 = ADC Standby mode.
+     * |        |          |11 = ADC Deep power down mode.
+     * |        |          |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up
+     * |[19:8]  |LDOSUT    |ADC Internal LDO Start-up Time
+     * |        |          |Set this bit fields to control LDO start-up time
+     * |        |          |The minimum required LDO start-up time is 20us
+     * |        |          |LDO start-up time = (1/ADC_CLK) x LDOSUT.
+     * @var EADC_T::CALCTL
+     * Offset: 0x114  ADC Calibration Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |CALSTART  |Calibration Functional Block Start
+     * |        |          |0 = Stops calibration functional block.
+     * |        |          |1 = Starts calibration functional block.
+     * |        |          |Note: This bit is set by SW and clear by HW after re-calibration finish
+     * |[2]     |CALDONE   |Calibration Functional Block Complete (Read Only)
+     * |        |          |0 = During a calibration.
+     * |        |          |1 = Calibration is completed.
+     * |[3]     |CALSEL    |Select Calibration Functional Block
+     * |        |          |0 = Load calibration word when calibration functional block is active.
+     * |        |          |1 = Execute calibration when calibration functional block is active.
+     * @var EADC_T::CALDWRD
+     * Offset: 0x118  ADC Calibration Load Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |CALWORD   |Calibration Word Bits
+     * |        |          |Write to this register with the previous calibration word before load calibration action.
+     * |        |          |Read this register after calibration done.
+     * |        |          |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
+     */
+    __I  uint32_t DAT[19];               /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18                    */
+    __I  uint32_t CURDAT;                /*!< [0x004c] ADC PDMA Current Transfer Data Register                          */
+    __IO uint32_t CTL;                   /*!< [0x0050] ADC Control Register                                             */
+    __O  uint32_t SWTRG;                 /*!< [0x0054] ADC Sample Module Software Start Register                        */
+    __IO uint32_t PENDSTS;               /*!< [0x0058] ADC Start of Conversion Pending Flag Register                    */
+    __IO uint32_t OVSTS;                 /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t SCTL[19];              /*!< [0x0080] ADC Sample Module 0~18 Control Register                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t INTSRC[4];             /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register.                */
+    __IO uint32_t CMP[4];                /*!< [0x00e0] ADC Result Compare Register 0~3                                  */
+    __I  uint32_t STATUS0;               /*!< [0x00f0] ADC Status Register 0                                            */
+    __I  uint32_t STATUS1;               /*!< [0x00f4] ADC Status Register 1                                            */
+    __IO uint32_t STATUS2;               /*!< [0x00f8] ADC Status Register 2                                            */
+    __I  uint32_t STATUS3;               /*!< [0x00fc] ADC Status Register 3                                            */
+    __I  uint32_t DDAT[4];               /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3               */
+    __IO uint32_t PWRM;                  /*!< [0x0110] ADC Power Management Register                                    */
+    __IO uint32_t CALCTL;                /*!< [0x0114] ADC Calibration Control Register                                 */
+    __IO uint32_t CALDWRD;               /*!< [0x0118] ADC Calibration Load Word Register                               */
+
+} EADC_T;
+
+/**
+    @addtogroup EADC_CONST EADC Bit Field Definition
+    Constant Definitions for EADC Controller
+@{ */
+
+#define EADC_DAT_RESULT_Pos              (0)                                                /*!< EADC_T::DAT: RESULT Position          */
+#define EADC_DAT_RESULT_Msk              (0xfffful << EADC_DAT_RESULT_Pos)                  /*!< EADC_T::DAT: RESULT Mask              */
+
+#define EADC_DAT_OV_Pos                  (16)                                               /*!< EADC_T::DAT: OV Position              */
+#define EADC_DAT_OV_Msk                  (0x1ul << EADC_DAT_OV_Pos)                         /*!< EADC_T::DAT: OV Mask                  */
+
+#define EADC_DAT_VALID_Pos               (17)                                               /*!< EADC_T::DAT: VALID Position           */
+#define EADC_DAT_VALID_Msk               (0x1ul << EADC_DAT_VALID_Pos)                      /*!< EADC_T::DAT: VALID Mask               */
+
+#define EADC_DAT0_RESULT_Pos             (0)                                               /*!< EADC_T::DAT0: RESULT Position          */
+#define EADC_DAT0_RESULT_Msk             (0xfffful << EADC_DAT0_RESULT_Pos)                /*!< EADC_T::DAT0: RESULT Mask              */
+
+#define EADC_DAT0_OV_Pos                 (16)                                              /*!< EADC_T::DAT0: OV Position              */
+#define EADC_DAT0_OV_Msk                 (0x1ul << EADC_DAT0_OV_Pos)                       /*!< EADC_T::DAT0: OV Mask                  */
+
+#define EADC_DAT0_VALID_Pos              (17)                                              /*!< EADC_T::DAT0: VALID Position           */
+#define EADC_DAT0_VALID_Msk              (0x1ul << EADC_DAT0_VALID_Pos)                    /*!< EADC_T::DAT0: VALID Mask               */
+
+#define EADC_DAT1_RESULT_Pos             (0)                                               /*!< EADC_T::DAT1: RESULT Position          */
+#define EADC_DAT1_RESULT_Msk             (0xfffful << EADC_DAT1_RESULT_Pos)                /*!< EADC_T::DAT1: RESULT Mask              */
+
+#define EADC_DAT1_OV_Pos                 (16)                                              /*!< EADC_T::DAT1: OV Position              */
+#define EADC_DAT1_OV_Msk                 (0x1ul << EADC_DAT1_OV_Pos)                       /*!< EADC_T::DAT1: OV Mask                  */
+
+#define EADC_DAT1_VALID_Pos              (17)                                              /*!< EADC_T::DAT1: VALID Position           */
+#define EADC_DAT1_VALID_Msk              (0x1ul << EADC_DAT1_VALID_Pos)                    /*!< EADC_T::DAT1: VALID Mask               */
+
+#define EADC_DAT2_RESULT_Pos             (0)                                               /*!< EADC_T::DAT2: RESULT Position          */
+#define EADC_DAT2_RESULT_Msk             (0xfffful << EADC_DAT2_RESULT_Pos)                /*!< EADC_T::DAT2: RESULT Mask              */
+
+#define EADC_DAT2_OV_Pos                 (16)                                              /*!< EADC_T::DAT2: OV Position              */
+#define EADC_DAT2_OV_Msk                 (0x1ul << EADC_DAT2_OV_Pos)                       /*!< EADC_T::DAT2: OV Mask                  */
+
+#define EADC_DAT2_VALID_Pos              (17)                                              /*!< EADC_T::DAT2: VALID Position           */
+#define EADC_DAT2_VALID_Msk              (0x1ul << EADC_DAT2_VALID_Pos)                    /*!< EADC_T::DAT2: VALID Mask               */
+
+#define EADC_DAT3_RESULT_Pos             (0)                                               /*!< EADC_T::DAT3: RESULT Position          */
+#define EADC_DAT3_RESULT_Msk             (0xfffful << EADC_DAT3_RESULT_Pos)                /*!< EADC_T::DAT3: RESULT Mask              */
+
+#define EADC_DAT3_OV_Pos                 (16)                                              /*!< EADC_T::DAT3: OV Position              */
+#define EADC_DAT3_OV_Msk                 (0x1ul << EADC_DAT3_OV_Pos)                       /*!< EADC_T::DAT3: OV Mask                  */
+
+#define EADC_DAT3_VALID_Pos              (17)                                              /*!< EADC_T::DAT3: VALID Position           */
+#define EADC_DAT3_VALID_Msk              (0x1ul << EADC_DAT3_VALID_Pos)                    /*!< EADC_T::DAT3: VALID Mask               */
+
+#define EADC_DAT4_RESULT_Pos             (0)                                               /*!< EADC_T::DAT4: RESULT Position          */
+#define EADC_DAT4_RESULT_Msk             (0xfffful << EADC_DAT4_RESULT_Pos)                /*!< EADC_T::DAT4: RESULT Mask              */
+
+#define EADC_DAT4_OV_Pos                 (16)                                              /*!< EADC_T::DAT4: OV Position              */
+#define EADC_DAT4_OV_Msk                 (0x1ul << EADC_DAT4_OV_Pos)                       /*!< EADC_T::DAT4: OV Mask                  */
+
+#define EADC_DAT4_VALID_Pos              (17)                                              /*!< EADC_T::DAT4: VALID Position           */
+#define EADC_DAT4_VALID_Msk              (0x1ul << EADC_DAT4_VALID_Pos)                    /*!< EADC_T::DAT4: VALID Mask               */
+
+#define EADC_DAT5_RESULT_Pos             (0)                                               /*!< EADC_T::DAT5: RESULT Position          */
+#define EADC_DAT5_RESULT_Msk             (0xfffful << EADC_DAT5_RESULT_Pos)                /*!< EADC_T::DAT5: RESULT Mask              */
+
+#define EADC_DAT5_OV_Pos                 (16)                                              /*!< EADC_T::DAT5: OV Position              */
+#define EADC_DAT5_OV_Msk                 (0x1ul << EADC_DAT5_OV_Pos)                       /*!< EADC_T::DAT5: OV Mask                  */
+
+#define EADC_DAT5_VALID_Pos              (17)                                              /*!< EADC_T::DAT5: VALID Position           */
+#define EADC_DAT5_VALID_Msk              (0x1ul << EADC_DAT5_VALID_Pos)                    /*!< EADC_T::DAT5: VALID Mask               */
+
+#define EADC_DAT6_RESULT_Pos             (0)                                               /*!< EADC_T::DAT6: RESULT Position          */
+#define EADC_DAT6_RESULT_Msk             (0xfffful << EADC_DAT6_RESULT_Pos)                /*!< EADC_T::DAT6: RESULT Mask              */
+
+#define EADC_DAT6_OV_Pos                 (16)                                              /*!< EADC_T::DAT6: OV Position              */
+#define EADC_DAT6_OV_Msk                 (0x1ul << EADC_DAT6_OV_Pos)                       /*!< EADC_T::DAT6: OV Mask                  */
+
+#define EADC_DAT6_VALID_Pos              (17)                                              /*!< EADC_T::DAT6: VALID Position           */
+#define EADC_DAT6_VALID_Msk              (0x1ul << EADC_DAT6_VALID_Pos)                    /*!< EADC_T::DAT6: VALID Mask               */
+
+#define EADC_DAT7_RESULT_Pos             (0)                                               /*!< EADC_T::DAT7: RESULT Position          */
+#define EADC_DAT7_RESULT_Msk             (0xfffful << EADC_DAT7_RESULT_Pos)                /*!< EADC_T::DAT7: RESULT Mask              */
+
+#define EADC_DAT7_OV_Pos                 (16)                                              /*!< EADC_T::DAT7: OV Position              */
+#define EADC_DAT7_OV_Msk                 (0x1ul << EADC_DAT7_OV_Pos)                       /*!< EADC_T::DAT7: OV Mask                  */
+
+#define EADC_DAT7_VALID_Pos              (17)                                              /*!< EADC_T::DAT7: VALID Position           */
+#define EADC_DAT7_VALID_Msk              (0x1ul << EADC_DAT7_VALID_Pos)                    /*!< EADC_T::DAT7: VALID Mask               */
+
+#define EADC_DAT8_RESULT_Pos             (0)                                               /*!< EADC_T::DAT8: RESULT Position          */
+#define EADC_DAT8_RESULT_Msk             (0xfffful << EADC_DAT8_RESULT_Pos)                /*!< EADC_T::DAT8: RESULT Mask              */
+
+#define EADC_DAT8_OV_Pos                 (16)                                              /*!< EADC_T::DAT8: OV Position              */
+#define EADC_DAT8_OV_Msk                 (0x1ul << EADC_DAT8_OV_Pos)                       /*!< EADC_T::DAT8: OV Mask                  */
+
+#define EADC_DAT8_VALID_Pos              (17)                                              /*!< EADC_T::DAT8: VALID Position           */
+#define EADC_DAT8_VALID_Msk              (0x1ul << EADC_DAT8_VALID_Pos)                    /*!< EADC_T::DAT8: VALID Mask               */
+
+#define EADC_DAT9_RESULT_Pos             (0)                                               /*!< EADC_T::DAT9: RESULT Position          */
+#define EADC_DAT9_RESULT_Msk             (0xfffful << EADC_DAT9_RESULT_Pos)                /*!< EADC_T::DAT9: RESULT Mask              */
+
+#define EADC_DAT9_OV_Pos                 (16)                                              /*!< EADC_T::DAT9: OV Position              */
+#define EADC_DAT9_OV_Msk                 (0x1ul << EADC_DAT9_OV_Pos)                       /*!< EADC_T::DAT9: OV Mask                  */
+
+#define EADC_DAT9_VALID_Pos              (17)                                              /*!< EADC_T::DAT9: VALID Position           */
+#define EADC_DAT9_VALID_Msk              (0x1ul << EADC_DAT9_VALID_Pos)                    /*!< EADC_T::DAT9: VALID Mask               */
+
+#define EADC_DAT10_RESULT_Pos            (0)                                               /*!< EADC_T::DAT10: RESULT Position         */
+#define EADC_DAT10_RESULT_Msk            (0xfffful << EADC_DAT10_RESULT_Pos)               /*!< EADC_T::DAT10: RESULT Mask             */
+
+#define EADC_DAT10_OV_Pos                (16)                                              /*!< EADC_T::DAT10: OV Position             */
+#define EADC_DAT10_OV_Msk                (0x1ul << EADC_DAT10_OV_Pos)                      /*!< EADC_T::DAT10: OV Mask                 */
+
+#define EADC_DAT10_VALID_Pos             (17)                                              /*!< EADC_T::DAT10: VALID Position          */
+#define EADC_DAT10_VALID_Msk             (0x1ul << EADC_DAT10_VALID_Pos)                   /*!< EADC_T::DAT10: VALID Mask              */
+
+#define EADC_DAT11_RESULT_Pos            (0)                                               /*!< EADC_T::DAT11: RESULT Position         */
+#define EADC_DAT11_RESULT_Msk            (0xfffful << EADC_DAT11_RESULT_Pos)               /*!< EADC_T::DAT11: RESULT Mask             */
+
+#define EADC_DAT11_OV_Pos                (16)                                              /*!< EADC_T::DAT11: OV Position             */
+#define EADC_DAT11_OV_Msk                (0x1ul << EADC_DAT11_OV_Pos)                      /*!< EADC_T::DAT11: OV Mask                 */
+
+#define EADC_DAT11_VALID_Pos             (17)                                              /*!< EADC_T::DAT11: VALID Position          */
+#define EADC_DAT11_VALID_Msk             (0x1ul << EADC_DAT11_VALID_Pos)                   /*!< EADC_T::DAT11: VALID Mask              */
+
+#define EADC_DAT12_RESULT_Pos            (0)                                               /*!< EADC_T::DAT12: RESULT Position         */
+#define EADC_DAT12_RESULT_Msk            (0xfffful << EADC_DAT12_RESULT_Pos)               /*!< EADC_T::DAT12: RESULT Mask             */
+
+#define EADC_DAT12_OV_Pos                (16)                                              /*!< EADC_T::DAT12: OV Position             */
+#define EADC_DAT12_OV_Msk                (0x1ul << EADC_DAT12_OV_Pos)                      /*!< EADC_T::DAT12: OV Mask                 */
+
+#define EADC_DAT12_VALID_Pos             (17)                                              /*!< EADC_T::DAT12: VALID Position          */
+#define EADC_DAT12_VALID_Msk             (0x1ul << EADC_DAT12_VALID_Pos)                   /*!< EADC_T::DAT12: VALID Mask              */
+
+#define EADC_DAT13_RESULT_Pos            (0)                                               /*!< EADC_T::DAT13: RESULT Position         */
+#define EADC_DAT13_RESULT_Msk            (0xfffful << EADC_DAT13_RESULT_Pos)               /*!< EADC_T::DAT13: RESULT Mask             */
+
+#define EADC_DAT13_OV_Pos                (16)                                              /*!< EADC_T::DAT13: OV Position             */
+#define EADC_DAT13_OV_Msk                (0x1ul << EADC_DAT13_OV_Pos)                      /*!< EADC_T::DAT13: OV Mask                 */
+
+#define EADC_DAT13_VALID_Pos             (17)                                              /*!< EADC_T::DAT13: VALID Position          */
+#define EADC_DAT13_VALID_Msk             (0x1ul << EADC_DAT13_VALID_Pos)                   /*!< EADC_T::DAT13: VALID Mask              */
+
+#define EADC_DAT14_RESULT_Pos            (0)                                               /*!< EADC_T::DAT14: RESULT Position         */
+#define EADC_DAT14_RESULT_Msk            (0xfffful << EADC_DAT14_RESULT_Pos)               /*!< EADC_T::DAT14: RESULT Mask             */
+
+#define EADC_DAT14_OV_Pos                (16)                                              /*!< EADC_T::DAT14: OV Position             */
+#define EADC_DAT14_OV_Msk                (0x1ul << EADC_DAT14_OV_Pos)                      /*!< EADC_T::DAT14: OV Mask                 */
+
+#define EADC_DAT14_VALID_Pos             (17)                                              /*!< EADC_T::DAT14: VALID Position          */
+#define EADC_DAT14_VALID_Msk             (0x1ul << EADC_DAT14_VALID_Pos)                   /*!< EADC_T::DAT14: VALID Mask              */
+
+#define EADC_DAT15_RESULT_Pos            (0)                                               /*!< EADC_T::DAT15: RESULT Position         */
+#define EADC_DAT15_RESULT_Msk            (0xfffful << EADC_DAT15_RESULT_Pos)               /*!< EADC_T::DAT15: RESULT Mask             */
+
+#define EADC_DAT15_OV_Pos                (16)                                              /*!< EADC_T::DAT15: OV Position             */
+#define EADC_DAT15_OV_Msk                (0x1ul << EADC_DAT15_OV_Pos)                      /*!< EADC_T::DAT15: OV Mask                 */
+
+#define EADC_DAT15_VALID_Pos             (17)                                              /*!< EADC_T::DAT15: VALID Position          */
+#define EADC_DAT15_VALID_Msk             (0x1ul << EADC_DAT15_VALID_Pos)                   /*!< EADC_T::DAT15: VALID Mask              */
+
+#define EADC_DAT16_RESULT_Pos            (0)                                               /*!< EADC_T::DAT16: RESULT Position         */
+#define EADC_DAT16_RESULT_Msk            (0xfffful << EADC_DAT16_RESULT_Pos)               /*!< EADC_T::DAT16: RESULT Mask             */
+
+#define EADC_DAT16_OV_Pos                (16)                                              /*!< EADC_T::DAT16: OV Position             */
+#define EADC_DAT16_OV_Msk                (0x1ul << EADC_DAT16_OV_Pos)                      /*!< EADC_T::DAT16: OV Mask                 */
+
+#define EADC_DAT16_VALID_Pos             (17)                                              /*!< EADC_T::DAT16: VALID Position          */
+#define EADC_DAT16_VALID_Msk             (0x1ul << EADC_DAT16_VALID_Pos)                   /*!< EADC_T::DAT16: VALID Mask              */
+
+#define EADC_DAT17_RESULT_Pos            (0)                                               /*!< EADC_T::DAT17: RESULT Position         */
+#define EADC_DAT17_RESULT_Msk            (0xfffful << EADC_DAT17_RESULT_Pos)               /*!< EADC_T::DAT17: RESULT Mask             */
+
+#define EADC_DAT17_OV_Pos                (16)                                              /*!< EADC_T::DAT17: OV Position             */
+#define EADC_DAT17_OV_Msk                (0x1ul << EADC_DAT17_OV_Pos)                      /*!< EADC_T::DAT17: OV Mask                 */
+
+#define EADC_DAT17_VALID_Pos             (17)                                              /*!< EADC_T::DAT17: VALID Position          */
+#define EADC_DAT17_VALID_Msk             (0x1ul << EADC_DAT17_VALID_Pos)                   /*!< EADC_T::DAT17: VALID Mask              */
+
+#define EADC_DAT18_RESULT_Pos            (0)                                               /*!< EADC_T::DAT18: RESULT Position         */
+#define EADC_DAT18_RESULT_Msk            (0xfffful << EADC_DAT18_RESULT_Pos)               /*!< EADC_T::DAT18: RESULT Mask             */
+
+#define EADC_DAT18_OV_Pos                (16)                                              /*!< EADC_T::DAT18: OV Position             */
+#define EADC_DAT18_OV_Msk                (0x1ul << EADC_DAT18_OV_Pos)                      /*!< EADC_T::DAT18: OV Mask                 */
+
+#define EADC_DAT18_VALID_Pos             (17)                                              /*!< EADC_T::DAT18: VALID Position          */
+#define EADC_DAT18_VALID_Msk             (0x1ul << EADC_DAT18_VALID_Pos)                   /*!< EADC_T::DAT18: VALID Mask              */
+
+#define EADC_CURDAT_CURDAT_Pos           (0)                                               /*!< EADC_T::CURDAT: CURDAT Position        */
+#define EADC_CURDAT_CURDAT_Msk           (0x3fffful << EADC_CURDAT_CURDAT_Pos)             /*!< EADC_T::CURDAT: CURDAT Mask            */
+
+#define EADC_CTL_ADCEN_Pos               (0)                                               /*!< EADC_T::CTL: ADCEN Position            */
+#define EADC_CTL_ADCEN_Msk               (0x1ul << EADC_CTL_ADCEN_Pos)                     /*!< EADC_T::CTL: ADCEN Mask                */
+
+#define EADC_CTL_ADCRST_Pos              (1)                                               /*!< EADC_T::CTL: ADCRST Position           */
+#define EADC_CTL_ADCRST_Msk              (0x1ul << EADC_CTL_ADCRST_Pos)                    /*!< EADC_T::CTL: ADCRST Mask               */
+
+#define EADC_CTL_ADCIEN0_Pos             (2)                                               /*!< EADC_T::CTL: ADCIEN0 Position          */
+#define EADC_CTL_ADCIEN0_Msk             (0x1ul << EADC_CTL_ADCIEN0_Pos)                   /*!< EADC_T::CTL: ADCIEN0 Mask              */
+
+#define EADC_CTL_ADCIEN1_Pos             (3)                                               /*!< EADC_T::CTL: ADCIEN1 Position          */
+#define EADC_CTL_ADCIEN1_Msk             (0x1ul << EADC_CTL_ADCIEN1_Pos)                   /*!< EADC_T::CTL: ADCIEN1 Mask              */
+
+#define EADC_CTL_ADCIEN2_Pos             (4)                                               /*!< EADC_T::CTL: ADCIEN2 Position          */
+#define EADC_CTL_ADCIEN2_Msk             (0x1ul << EADC_CTL_ADCIEN2_Pos)                   /*!< EADC_T::CTL: ADCIEN2 Mask              */
+
+#define EADC_CTL_ADCIEN3_Pos             (5)                                               /*!< EADC_T::CTL: ADCIEN3 Position          */
+#define EADC_CTL_ADCIEN3_Msk             (0x1ul << EADC_CTL_ADCIEN3_Pos)                   /*!< EADC_T::CTL: ADCIEN3 Mask              */
+
+#define EADC_CTL_RESSEL_Pos              (6)                                               /*!< EADC_T::CTL: RESSEL Position           */
+#define EADC_CTL_RESSEL_Msk              (0x3ul << EADC_CTL_RESSEL_Pos)                    /*!< EADC_T::CTL: RESSEL Mask               */
+
+#define EADC_CTL_DIFFEN_Pos              (8)                                               /*!< EADC_T::CTL: DIFFEN Position           */
+#define EADC_CTL_DIFFEN_Msk              (0x1ul << EADC_CTL_DIFFEN_Pos)                    /*!< EADC_T::CTL: DIFFEN Mask               */
+
+#define EADC_CTL_DMOF_Pos                (9)                                               /*!< EADC_T::CTL: DMOF Position             */
+#define EADC_CTL_DMOF_Msk                (0x1ul << EADC_CTL_DMOF_Pos)                      /*!< EADC_T::CTL: DMOF Mask                 */
+
+#define EADC_CTL_PDMAEN_Pos              (11)                                              /*!< EADC_T::CTL: PDMAEN Position           */
+#define EADC_CTL_PDMAEN_Msk              (0x1ul << EADC_CTL_PDMAEN_Pos)                    /*!< EADC_T::CTL: PDMAEN Mask               */
+
+#define EADC_SWTRG_SWTRG_Pos             (0)                                               /*!< EADC_T::SWTRG: SWTRG Position          */
+#define EADC_SWTRG_SWTRG_Msk             (0x7fffful << EADC_SWTRG_SWTRG_Pos)               /*!< EADC_T::SWTRG: SWTRG Mask              */
+
+#define EADC_PENDSTS_STPF_Pos            (0)                                               /*!< EADC_T::PENDSTS: STPF Position         */
+#define EADC_PENDSTS_STPF_Msk            (0x7fffful << EADC_PENDSTS_STPF_Pos)              /*!< EADC_T::PENDSTS: STPF Mask             */
+
+#define EADC_OVSTS_SPOVF_Pos             (0)                                               /*!< EADC_T::OVSTS: SPOVF Position          */
+#define EADC_OVSTS_SPOVF_Msk             (0x7fffful << EADC_OVSTS_SPOVF_Pos)               /*!< EADC_T::OVSTS: SPOVF Mask              */
+
+#define EADC_SCTL_CHSEL_Pos              (0)                                               /*!< EADC_T::SCTL: CHSEL Position           */
+#define EADC_SCTL_CHSEL_Msk              (0xful << EADC_SCTL_CHSEL_Pos)                    /*!< EADC_T::SCTL: CHSEL Mask               */
+
+#define EADC_SCTL_EXTREN_Pos             (4)                                               /*!< EADC_T::SCTL: EXTREN Position          */
+#define EADC_SCTL_EXTREN_Msk             (0x1ul << EADC_SCTL_EXTREN_Pos)                   /*!< EADC_T::SCTL: EXTREN Mask              */
+
+#define EADC_SCTL_EXTFEN_Pos             (5)                                               /*!< EADC_T::SCTL: EXTFEN Position          */
+#define EADC_SCTL_EXTFEN_Msk             (0x1ul << EADC_SCTL_EXTFEN_Pos)                   /*!< EADC_T::SCTL: EXTFEN Mask              */
+
+#define EADC_SCTL_TRGDLYDIV_Pos          (6)                                               /*!< EADC_T::SCTL: TRGDLYDIV Position       */
+#define EADC_SCTL_TRGDLYDIV_Msk          (0x3ul << EADC_SCTL_TRGDLYDIV_Pos)                /*!< EADC_T::SCTL: TRGDLYDIV Mask           */
+
+#define EADC_SCTL_TRGDLYCNT_Pos          (8)                                               /*!< EADC_T::SCTL: TRGDLYCNT Position       */
+#define EADC_SCTL_TRGDLYCNT_Msk          (0xfful << EADC_SCTL_TRGDLYCNT_Pos)               /*!< EADC_T::SCTL: TRGDLYCNT Mask           */
+
+#define EADC_SCTL_TRGSEL_Pos             (16)                                              /*!< EADC_T::SCTL: TRGSEL Position          */
+#define EADC_SCTL_TRGSEL_Msk             (0x1ful << EADC_SCTL_TRGSEL_Pos)                  /*!< EADC_T::SCTL: TRGSEL Mask              */
+
+#define EADC_SCTL_INTPOS_Pos             (22)                                              /*!< EADC_T::SCTL: INTPOS Position          */
+#define EADC_SCTL_INTPOS_Msk             (0x1ul << EADC_SCTL_INTPOS_Pos)                   /*!< EADC_T::SCTL: INTPOS Mask              */
+
+#define EADC_SCTL_DBMEN_Pos              (23)                                              /*!< EADC_T::SCTL: DBMEN Position           */
+#define EADC_SCTL_DBMEN_Msk              (0x1ul << EADC_SCTL_DBMEN_Pos)                    /*!< EADC_T::SCTL: DBMEN Mask               */
+
+#define EADC_SCTL_EXTSMPT_Pos            (24)                                              /*!< EADC_T::SCTL: EXTSMPT Position         */
+#define EADC_SCTL_EXTSMPT_Msk            (0xfful << EADC_SCTL_EXTSMPT_Pos)                 /*!< EADC_T::SCTL: EXTSMPT Mask             */
+
+#define EADC_SCTL0_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL0: CHSEL Position          */
+#define EADC_SCTL0_CHSEL_Msk             (0xful << EADC_SCTL0_CHSEL_Pos)                   /*!< EADC_T::SCTL0: CHSEL Mask              */
+
+#define EADC_SCTL0_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL0: EXTREN Position         */
+#define EADC_SCTL0_EXTREN_Msk            (0x1ul << EADC_SCTL0_EXTREN_Pos)                  /*!< EADC_T::SCTL0: EXTREN Mask             */
+
+#define EADC_SCTL0_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL0: EXTFEN Position         */
+#define EADC_SCTL0_EXTFEN_Msk            (0x1ul << EADC_SCTL0_EXTFEN_Pos)                  /*!< EADC_T::SCTL0: EXTFEN Mask             */
+
+#define EADC_SCTL0_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL0: TRGDLYDIV Position      */
+#define EADC_SCTL0_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL0: TRGDLYDIV Mask          */
+
+#define EADC_SCTL0_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL0: TRGDLYCNT Position      */
+#define EADC_SCTL0_TRGDLYCNT_Msk         (0xfful << EADC_SCTL0_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL0: TRGDLYCNT Mask          */
+
+#define EADC_SCTL0_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL0: TRGSEL Position         */
+#define EADC_SCTL0_TRGSEL_Msk            (0x1ful << EADC_SCTL0_TRGSEL_Pos)                 /*!< EADC_T::SCTL0: TRGSEL Mask             */
+
+#define EADC_SCTL0_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL0: INTPOS Position         */
+#define EADC_SCTL0_INTPOS_Msk            (0x1ul << EADC_SCTL0_INTPOS_Pos)                  /*!< EADC_T::SCTL0: INTPOS Mask             */
+
+#define EADC_SCTL0_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL0: DBMEN Position          */
+#define EADC_SCTL0_DBMEN_Msk             (0x1ul << EADC_SCTL0_DBMEN_Pos)                   /*!< EADC_T::SCTL0: DBMEN Mask              */
+
+#define EADC_SCTL0_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL0: EXTSMPT Position        */
+#define EADC_SCTL0_EXTSMPT_Msk           (0xfful << EADC_SCTL0_EXTSMPT_Pos)                /*!< EADC_T::SCTL0: EXTSMPT Mask            */
+
+#define EADC_SCTL1_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL1: CHSEL Position          */
+#define EADC_SCTL1_CHSEL_Msk             (0xful << EADC_SCTL1_CHSEL_Pos)                   /*!< EADC_T::SCTL1: CHSEL Mask              */
+
+#define EADC_SCTL1_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL1: EXTREN Position         */
+#define EADC_SCTL1_EXTREN_Msk            (0x1ul << EADC_SCTL1_EXTREN_Pos)                  /*!< EADC_T::SCTL1: EXTREN Mask             */
+
+#define EADC_SCTL1_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL1: EXTFEN Position         */
+#define EADC_SCTL1_EXTFEN_Msk            (0x1ul << EADC_SCTL1_EXTFEN_Pos)                  /*!< EADC_T::SCTL1: EXTFEN Mask             */
+
+#define EADC_SCTL1_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL1: TRGDLYDIV Position      */
+#define EADC_SCTL1_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL1: TRGDLYDIV Mask          */
+
+#define EADC_SCTL1_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL1: TRGDLYCNT Position      */
+#define EADC_SCTL1_TRGDLYCNT_Msk         (0xfful << EADC_SCTL1_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL1: TRGDLYCNT Mask          */
+
+#define EADC_SCTL1_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL1: TRGSEL Position         */
+#define EADC_SCTL1_TRGSEL_Msk            (0x1ful << EADC_SCTL1_TRGSEL_Pos)                 /*!< EADC_T::SCTL1: TRGSEL Mask             */
+
+#define EADC_SCTL1_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL1: INTPOS Position         */
+#define EADC_SCTL1_INTPOS_Msk            (0x1ul << EADC_SCTL1_INTPOS_Pos)                  /*!< EADC_T::SCTL1: INTPOS Mask             */
+
+#define EADC_SCTL1_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL1: DBMEN Position          */
+#define EADC_SCTL1_DBMEN_Msk             (0x1ul << EADC_SCTL1_DBMEN_Pos)                   /*!< EADC_T::SCTL1: DBMEN Mask              */
+
+#define EADC_SCTL1_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL1: EXTSMPT Position        */
+#define EADC_SCTL1_EXTSMPT_Msk           (0xfful << EADC_SCTL1_EXTSMPT_Pos)                /*!< EADC_T::SCTL1: EXTSMPT Mask            */
+
+#define EADC_SCTL2_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL2: CHSEL Position          */
+#define EADC_SCTL2_CHSEL_Msk             (0xful << EADC_SCTL2_CHSEL_Pos)                   /*!< EADC_T::SCTL2: CHSEL Mask              */
+
+#define EADC_SCTL2_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL2: EXTREN Position         */
+#define EADC_SCTL2_EXTREN_Msk            (0x1ul << EADC_SCTL2_EXTREN_Pos)                  /*!< EADC_T::SCTL2: EXTREN Mask             */
+
+#define EADC_SCTL2_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL2: EXTFEN Position         */
+#define EADC_SCTL2_EXTFEN_Msk            (0x1ul << EADC_SCTL2_EXTFEN_Pos)                  /*!< EADC_T::SCTL2: EXTFEN Mask             */
+
+#define EADC_SCTL2_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL2: TRGDLYDIV Position      */
+#define EADC_SCTL2_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL2: TRGDLYDIV Mask          */
+
+#define EADC_SCTL2_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL2: TRGDLYCNT Position      */
+#define EADC_SCTL2_TRGDLYCNT_Msk         (0xfful << EADC_SCTL2_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL2: TRGDLYCNT Mask          */
+
+#define EADC_SCTL2_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL2: TRGSEL Position         */
+#define EADC_SCTL2_TRGSEL_Msk            (0x1ful << EADC_SCTL2_TRGSEL_Pos)                 /*!< EADC_T::SCTL2: TRGSEL Mask             */
+
+#define EADC_SCTL2_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL2: INTPOS Position         */
+#define EADC_SCTL2_INTPOS_Msk            (0x1ul << EADC_SCTL2_INTPOS_Pos)                  /*!< EADC_T::SCTL2: INTPOS Mask             */
+
+#define EADC_SCTL2_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL2: DBMEN Position          */
+#define EADC_SCTL2_DBMEN_Msk             (0x1ul << EADC_SCTL2_DBMEN_Pos)                   /*!< EADC_T::SCTL2: DBMEN Mask              */
+
+#define EADC_SCTL2_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL2: EXTSMPT Position        */
+#define EADC_SCTL2_EXTSMPT_Msk           (0xfful << EADC_SCTL2_EXTSMPT_Pos)                /*!< EADC_T::SCTL2: EXTSMPT Mask            */
+
+#define EADC_SCTL3_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL3: CHSEL Position          */
+#define EADC_SCTL3_CHSEL_Msk             (0xful << EADC_SCTL3_CHSEL_Pos)                   /*!< EADC_T::SCTL3: CHSEL Mask              */
+
+#define EADC_SCTL3_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL3: EXTREN Position         */
+#define EADC_SCTL3_EXTREN_Msk            (0x1ul << EADC_SCTL3_EXTREN_Pos)                  /*!< EADC_T::SCTL3: EXTREN Mask             */
+
+#define EADC_SCTL3_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL3: EXTFEN Position         */
+#define EADC_SCTL3_EXTFEN_Msk            (0x1ul << EADC_SCTL3_EXTFEN_Pos)                  /*!< EADC_T::SCTL3: EXTFEN Mask             */
+
+#define EADC_SCTL3_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL3: TRGDLYDIV Position      */
+#define EADC_SCTL3_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL3: TRGDLYDIV Mask          */
+
+#define EADC_SCTL3_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL3: TRGDLYCNT Position      */
+#define EADC_SCTL3_TRGDLYCNT_Msk         (0xfful << EADC_SCTL3_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL3: TRGDLYCNT Mask          */
+
+#define EADC_SCTL3_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL3: TRGSEL Position         */
+#define EADC_SCTL3_TRGSEL_Msk            (0x1ful << EADC_SCTL3_TRGSEL_Pos)                 /*!< EADC_T::SCTL3: TRGSEL Mask             */
+
+#define EADC_SCTL3_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL3: INTPOS Position         */
+#define EADC_SCTL3_INTPOS_Msk            (0x1ul << EADC_SCTL3_INTPOS_Pos)                  /*!< EADC_T::SCTL3: INTPOS Mask             */
+
+#define EADC_SCTL3_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL3: DBMEN Position          */
+#define EADC_SCTL3_DBMEN_Msk             (0x1ul << EADC_SCTL3_DBMEN_Pos)                   /*!< EADC_T::SCTL3: DBMEN Mask              */
+
+#define EADC_SCTL3_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL3: EXTSMPT Position        */
+#define EADC_SCTL3_EXTSMPT_Msk           (0xfful << EADC_SCTL3_EXTSMPT_Pos)                /*!< EADC_T::SCTL3: EXTSMPT Mask            */
+
+#define EADC_SCTL4_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL4: CHSEL Position          */
+#define EADC_SCTL4_CHSEL_Msk             (0xful << EADC_SCTL4_CHSEL_Pos)                   /*!< EADC_T::SCTL4: CHSEL Mask              */
+
+#define EADC_SCTL4_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL4: EXTREN Position         */
+#define EADC_SCTL4_EXTREN_Msk            (0x1ul << EADC_SCTL4_EXTREN_Pos)                  /*!< EADC_T::SCTL4: EXTREN Mask             */
+
+#define EADC_SCTL4_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL4: EXTFEN Position         */
+#define EADC_SCTL4_EXTFEN_Msk            (0x1ul << EADC_SCTL4_EXTFEN_Pos)                  /*!< EADC_T::SCTL4: EXTFEN Mask             */
+
+#define EADC_SCTL4_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL4: TRGDLYDIV Position      */
+#define EADC_SCTL4_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL4: TRGDLYDIV Mask          */
+
+#define EADC_SCTL4_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL4: TRGDLYCNT Position      */
+#define EADC_SCTL4_TRGDLYCNT_Msk         (0xfful << EADC_SCTL4_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL4: TRGDLYCNT Mask          */
+
+#define EADC_SCTL4_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL4: TRGSEL Position         */
+#define EADC_SCTL4_TRGSEL_Msk            (0x1ful << EADC_SCTL4_TRGSEL_Pos)                 /*!< EADC_T::SCTL4: TRGSEL Mask             */
+
+#define EADC_SCTL4_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL4: INTPOS Position         */
+#define EADC_SCTL4_INTPOS_Msk            (0x1ul << EADC_SCTL4_INTPOS_Pos)                  /*!< EADC_T::SCTL4: INTPOS Mask             */
+
+#define EADC_SCTL4_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL4: EXTSMPT Position        */
+#define EADC_SCTL4_EXTSMPT_Msk           (0xfful << EADC_SCTL4_EXTSMPT_Pos)                /*!< EADC_T::SCTL4: EXTSMPT Mask            */
+
+#define EADC_SCTL5_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL5: CHSEL Position          */
+#define EADC_SCTL5_CHSEL_Msk             (0xful << EADC_SCTL5_CHSEL_Pos)                   /*!< EADC_T::SCTL5: CHSEL Mask              */
+
+#define EADC_SCTL5_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL5: EXTREN Position         */
+#define EADC_SCTL5_EXTREN_Msk            (0x1ul << EADC_SCTL5_EXTREN_Pos)                  /*!< EADC_T::SCTL5: EXTREN Mask             */
+
+#define EADC_SCTL5_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL5: EXTFEN Position         */
+#define EADC_SCTL5_EXTFEN_Msk            (0x1ul << EADC_SCTL5_EXTFEN_Pos)                  /*!< EADC_T::SCTL5: EXTFEN Mask             */
+
+#define EADC_SCTL5_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL5: TRGDLYDIV Position      */
+#define EADC_SCTL5_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL5: TRGDLYDIV Mask          */
+
+#define EADC_SCTL5_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL5: TRGDLYCNT Position      */
+#define EADC_SCTL5_TRGDLYCNT_Msk         (0xfful << EADC_SCTL5_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL5: TRGDLYCNT Mask          */
+
+#define EADC_SCTL5_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL5: TRGSEL Position         */
+#define EADC_SCTL5_TRGSEL_Msk            (0x1ful << EADC_SCTL5_TRGSEL_Pos)                 /*!< EADC_T::SCTL5: TRGSEL Mask             */
+
+#define EADC_SCTL5_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL5: INTPOS Position         */
+#define EADC_SCTL5_INTPOS_Msk            (0x1ul << EADC_SCTL5_INTPOS_Pos)                  /*!< EADC_T::SCTL5: INTPOS Mask             */
+
+#define EADC_SCTL5_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL5: EXTSMPT Position        */
+#define EADC_SCTL5_EXTSMPT_Msk           (0xfful << EADC_SCTL5_EXTSMPT_Pos)                /*!< EADC_T::SCTL5: EXTSMPT Mask            */
+
+#define EADC_SCTL6_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL6: CHSEL Position          */
+#define EADC_SCTL6_CHSEL_Msk             (0xful << EADC_SCTL6_CHSEL_Pos)                   /*!< EADC_T::SCTL6: CHSEL Mask              */
+
+#define EADC_SCTL6_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL6: EXTREN Position         */
+#define EADC_SCTL6_EXTREN_Msk            (0x1ul << EADC_SCTL6_EXTREN_Pos)                  /*!< EADC_T::SCTL6: EXTREN Mask             */
+
+#define EADC_SCTL6_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL6: EXTFEN Position         */
+#define EADC_SCTL6_EXTFEN_Msk            (0x1ul << EADC_SCTL6_EXTFEN_Pos)                  /*!< EADC_T::SCTL6: EXTFEN Mask             */
+
+#define EADC_SCTL6_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL6: TRGDLYDIV Position      */
+#define EADC_SCTL6_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL6: TRGDLYDIV Mask          */
+
+#define EADC_SCTL6_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL6: TRGDLYCNT Position      */
+#define EADC_SCTL6_TRGDLYCNT_Msk         (0xfful << EADC_SCTL6_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL6: TRGDLYCNT Mask          */
+
+#define EADC_SCTL6_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL6: TRGSEL Position         */
+#define EADC_SCTL6_TRGSEL_Msk            (0x1ful << EADC_SCTL6_TRGSEL_Pos)                 /*!< EADC_T::SCTL6: TRGSEL Mask             */
+
+#define EADC_SCTL6_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL6: INTPOS Position         */
+#define EADC_SCTL6_INTPOS_Msk            (0x1ul << EADC_SCTL6_INTPOS_Pos)                  /*!< EADC_T::SCTL6: INTPOS Mask             */
+
+#define EADC_SCTL6_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL6: EXTSMPT Position        */
+#define EADC_SCTL6_EXTSMPT_Msk           (0xfful << EADC_SCTL6_EXTSMPT_Pos)                /*!< EADC_T::SCTL6: EXTSMPT Mask            */
+
+#define EADC_SCTL7_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL7: CHSEL Position          */
+#define EADC_SCTL7_CHSEL_Msk             (0xful << EADC_SCTL7_CHSEL_Pos)                   /*!< EADC_T::SCTL7: CHSEL Mask              */
+
+#define EADC_SCTL7_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL7: EXTREN Position         */
+#define EADC_SCTL7_EXTREN_Msk            (0x1ul << EADC_SCTL7_EXTREN_Pos)                  /*!< EADC_T::SCTL7: EXTREN Mask             */
+
+#define EADC_SCTL7_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL7: EXTFEN Position         */
+#define EADC_SCTL7_EXTFEN_Msk            (0x1ul << EADC_SCTL7_EXTFEN_Pos)                  /*!< EADC_T::SCTL7: EXTFEN Mask             */
+
+#define EADC_SCTL7_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL7: TRGDLYDIV Position      */
+#define EADC_SCTL7_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL7: TRGDLYDIV Mask          */
+
+#define EADC_SCTL7_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL7: TRGDLYCNT Position      */
+#define EADC_SCTL7_TRGDLYCNT_Msk         (0xfful << EADC_SCTL7_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL7: TRGDLYCNT Mask          */
+
+#define EADC_SCTL7_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL7: TRGSEL Position         */
+#define EADC_SCTL7_TRGSEL_Msk            (0x1ful << EADC_SCTL7_TRGSEL_Pos)                 /*!< EADC_T::SCTL7: TRGSEL Mask             */
+
+#define EADC_SCTL7_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL7: INTPOS Position         */
+#define EADC_SCTL7_INTPOS_Msk            (0x1ul << EADC_SCTL7_INTPOS_Pos)                  /*!< EADC_T::SCTL7: INTPOS Mask             */
+
+#define EADC_SCTL7_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL7: EXTSMPT Position        */
+#define EADC_SCTL7_EXTSMPT_Msk           (0xfful << EADC_SCTL7_EXTSMPT_Pos)                /*!< EADC_T::SCTL7: EXTSMPT Mask            */
+
+#define EADC_SCTL8_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL8: CHSEL Position          */
+#define EADC_SCTL8_CHSEL_Msk             (0xful << EADC_SCTL8_CHSEL_Pos)                   /*!< EADC_T::SCTL8: CHSEL Mask              */
+
+#define EADC_SCTL8_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL8: EXTREN Position         */
+#define EADC_SCTL8_EXTREN_Msk            (0x1ul << EADC_SCTL8_EXTREN_Pos)                  /*!< EADC_T::SCTL8: EXTREN Mask             */
+
+#define EADC_SCTL8_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL8: EXTFEN Position         */
+#define EADC_SCTL8_EXTFEN_Msk            (0x1ul << EADC_SCTL8_EXTFEN_Pos)                  /*!< EADC_T::SCTL8: EXTFEN Mask             */
+
+#define EADC_SCTL8_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL8: TRGDLYDIV Position      */
+#define EADC_SCTL8_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL8: TRGDLYDIV Mask          */
+
+#define EADC_SCTL8_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL8: TRGDLYCNT Position      */
+#define EADC_SCTL8_TRGDLYCNT_Msk         (0xfful << EADC_SCTL8_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL8: TRGDLYCNT Mask          */
+
+#define EADC_SCTL8_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL8: TRGSEL Position         */
+#define EADC_SCTL8_TRGSEL_Msk            (0x1ful << EADC_SCTL8_TRGSEL_Pos)                 /*!< EADC_T::SCTL8: TRGSEL Mask             */
+
+#define EADC_SCTL8_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL8: INTPOS Position         */
+#define EADC_SCTL8_INTPOS_Msk            (0x1ul << EADC_SCTL8_INTPOS_Pos)                  /*!< EADC_T::SCTL8: INTPOS Mask             */
+
+#define EADC_SCTL8_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL8: EXTSMPT Position        */
+#define EADC_SCTL8_EXTSMPT_Msk           (0xfful << EADC_SCTL8_EXTSMPT_Pos)                /*!< EADC_T::SCTL8: EXTSMPT Mask            */
+
+#define EADC_SCTL9_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL9: CHSEL Position          */
+#define EADC_SCTL9_CHSEL_Msk             (0xful << EADC_SCTL9_CHSEL_Pos)                   /*!< EADC_T::SCTL9: CHSEL Mask              */
+
+#define EADC_SCTL9_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL9: EXTREN Position         */
+#define EADC_SCTL9_EXTREN_Msk            (0x1ul << EADC_SCTL9_EXTREN_Pos)                  /*!< EADC_T::SCTL9: EXTREN Mask             */
+
+#define EADC_SCTL9_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL9: EXTFEN Position         */
+#define EADC_SCTL9_EXTFEN_Msk            (0x1ul << EADC_SCTL9_EXTFEN_Pos)                  /*!< EADC_T::SCTL9: EXTFEN Mask             */
+
+#define EADC_SCTL9_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL9: TRGDLYDIV Position      */
+#define EADC_SCTL9_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL9: TRGDLYDIV Mask          */
+
+#define EADC_SCTL9_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL9: TRGDLYCNT Position      */
+#define EADC_SCTL9_TRGDLYCNT_Msk         (0xfful << EADC_SCTL9_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL9: TRGDLYCNT Mask          */
+
+#define EADC_SCTL9_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL9: TRGSEL Position         */
+#define EADC_SCTL9_TRGSEL_Msk            (0x1ful << EADC_SCTL9_TRGSEL_Pos)                 /*!< EADC_T::SCTL9: TRGSEL Mask             */
+
+#define EADC_SCTL9_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL9: INTPOS Position         */
+#define EADC_SCTL9_INTPOS_Msk            (0x1ul << EADC_SCTL9_INTPOS_Pos)                  /*!< EADC_T::SCTL9: INTPOS Mask             */
+
+#define EADC_SCTL9_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL9: EXTSMPT Position        */
+#define EADC_SCTL9_EXTSMPT_Msk           (0xfful << EADC_SCTL9_EXTSMPT_Pos)                /*!< EADC_T::SCTL9: EXTSMPT Mask            */
+
+#define EADC_SCTL10_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL10: CHSEL Position         */
+#define EADC_SCTL10_CHSEL_Msk            (0xful << EADC_SCTL10_CHSEL_Pos)                  /*!< EADC_T::SCTL10: CHSEL Mask             */
+
+#define EADC_SCTL10_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL10: EXTREN Position        */
+#define EADC_SCTL10_EXTREN_Msk           (0x1ul << EADC_SCTL10_EXTREN_Pos)                 /*!< EADC_T::SCTL10: EXTREN Mask            */
+
+#define EADC_SCTL10_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL10: EXTFEN Position        */
+#define EADC_SCTL10_EXTFEN_Msk           (0x1ul << EADC_SCTL10_EXTFEN_Pos)                 /*!< EADC_T::SCTL10: EXTFEN Mask            */
+
+#define EADC_SCTL10_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL10: TRGDLYDIV Position     */
+#define EADC_SCTL10_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL10: TRGDLYDIV Mask         */
+
+#define EADC_SCTL10_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL10: TRGDLYCNT Position     */
+#define EADC_SCTL10_TRGDLYCNT_Msk        (0xfful << EADC_SCTL10_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL10: TRGDLYCNT Mask         */
+
+#define EADC_SCTL10_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL10: TRGSEL Position        */
+#define EADC_SCTL10_TRGSEL_Msk           (0x1ful << EADC_SCTL10_TRGSEL_Pos)                /*!< EADC_T::SCTL10: TRGSEL Mask            */
+
+#define EADC_SCTL10_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL10: INTPOS Position        */
+#define EADC_SCTL10_INTPOS_Msk           (0x1ul << EADC_SCTL10_INTPOS_Pos)                 /*!< EADC_T::SCTL10: INTPOS Mask            */
+
+#define EADC_SCTL10_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL10: EXTSMPT Position       */
+#define EADC_SCTL10_EXTSMPT_Msk          (0xfful << EADC_SCTL10_EXTSMPT_Pos)               /*!< EADC_T::SCTL10: EXTSMPT Mask           */
+
+#define EADC_SCTL11_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL11: CHSEL Position         */
+#define EADC_SCTL11_CHSEL_Msk            (0xful << EADC_SCTL11_CHSEL_Pos)                  /*!< EADC_T::SCTL11: CHSEL Mask             */
+
+#define EADC_SCTL11_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL11: EXTREN Position        */
+#define EADC_SCTL11_EXTREN_Msk           (0x1ul << EADC_SCTL11_EXTREN_Pos)                 /*!< EADC_T::SCTL11: EXTREN Mask            */
+
+#define EADC_SCTL11_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL11: EXTFEN Position        */
+#define EADC_SCTL11_EXTFEN_Msk           (0x1ul << EADC_SCTL11_EXTFEN_Pos)                 /*!< EADC_T::SCTL11: EXTFEN Mask            */
+
+#define EADC_SCTL11_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL11: TRGDLYDIV Position     */
+#define EADC_SCTL11_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL11: TRGDLYDIV Mask         */
+
+#define EADC_SCTL11_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL11: TRGDLYCNT Position     */
+#define EADC_SCTL11_TRGDLYCNT_Msk        (0xfful << EADC_SCTL11_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL11: TRGDLYCNT Mask         */
+
+#define EADC_SCTL11_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL11: TRGSEL Position        */
+#define EADC_SCTL11_TRGSEL_Msk           (0x1ful << EADC_SCTL11_TRGSEL_Pos)                /*!< EADC_T::SCTL11: TRGSEL Mask            */
+
+#define EADC_SCTL11_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL11: INTPOS Position        */
+#define EADC_SCTL11_INTPOS_Msk           (0x1ul << EADC_SCTL11_INTPOS_Pos)                 /*!< EADC_T::SCTL11: INTPOS Mask            */
+
+#define EADC_SCTL11_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL11: EXTSMPT Position       */
+#define EADC_SCTL11_EXTSMPT_Msk          (0xfful << EADC_SCTL11_EXTSMPT_Pos)               /*!< EADC_T::SCTL11: EXTSMPT Mask           */
+
+#define EADC_SCTL12_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL12: CHSEL Position         */
+#define EADC_SCTL12_CHSEL_Msk            (0xful << EADC_SCTL12_CHSEL_Pos)                  /*!< EADC_T::SCTL12: CHSEL Mask             */
+
+#define EADC_SCTL12_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL12: EXTREN Position        */
+#define EADC_SCTL12_EXTREN_Msk           (0x1ul << EADC_SCTL12_EXTREN_Pos)                 /*!< EADC_T::SCTL12: EXTREN Mask            */
+
+#define EADC_SCTL12_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL12: EXTFEN Position        */
+#define EADC_SCTL12_EXTFEN_Msk           (0x1ul << EADC_SCTL12_EXTFEN_Pos)                 /*!< EADC_T::SCTL12: EXTFEN Mask            */
+
+#define EADC_SCTL12_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL12: TRGDLYDIV Position     */
+#define EADC_SCTL12_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL12: TRGDLYDIV Mask         */
+
+#define EADC_SCTL12_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL12: TRGDLYCNT Position     */
+#define EADC_SCTL12_TRGDLYCNT_Msk        (0xfful << EADC_SCTL12_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL12: TRGDLYCNT Mask         */
+
+#define EADC_SCTL12_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL12: TRGSEL Position        */
+#define EADC_SCTL12_TRGSEL_Msk           (0x1ful << EADC_SCTL12_TRGSEL_Pos)                /*!< EADC_T::SCTL12: TRGSEL Mask            */
+
+#define EADC_SCTL12_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL12: INTPOS Position        */
+#define EADC_SCTL12_INTPOS_Msk           (0x1ul << EADC_SCTL12_INTPOS_Pos)                 /*!< EADC_T::SCTL12: INTPOS Mask            */
+
+#define EADC_SCTL12_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL12: EXTSMPT Position       */
+#define EADC_SCTL12_EXTSMPT_Msk          (0xfful << EADC_SCTL12_EXTSMPT_Pos)               /*!< EADC_T::SCTL12: EXTSMPT Mask           */
+
+#define EADC_SCTL13_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL13: CHSEL Position         */
+#define EADC_SCTL13_CHSEL_Msk            (0xful << EADC_SCTL13_CHSEL_Pos)                  /*!< EADC_T::SCTL13: CHSEL Mask             */
+
+#define EADC_SCTL13_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL13: EXTREN Position        */
+#define EADC_SCTL13_EXTREN_Msk           (0x1ul << EADC_SCTL13_EXTREN_Pos)                 /*!< EADC_T::SCTL13: EXTREN Mask            */
+
+#define EADC_SCTL13_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL13: EXTFEN Position        */
+#define EADC_SCTL13_EXTFEN_Msk           (0x1ul << EADC_SCTL13_EXTFEN_Pos)                 /*!< EADC_T::SCTL13: EXTFEN Mask            */
+
+#define EADC_SCTL13_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL13: TRGDLYDIV Position     */
+#define EADC_SCTL13_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL13: TRGDLYDIV Mask         */
+
+#define EADC_SCTL13_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL13: TRGDLYCNT Position     */
+#define EADC_SCTL13_TRGDLYCNT_Msk        (0xfful << EADC_SCTL13_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL13: TRGDLYCNT Mask         */
+
+#define EADC_SCTL13_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL13: TRGSEL Position        */
+#define EADC_SCTL13_TRGSEL_Msk           (0x1ful << EADC_SCTL13_TRGSEL_Pos)                /*!< EADC_T::SCTL13: TRGSEL Mask            */
+
+#define EADC_SCTL13_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL13: INTPOS Position        */
+#define EADC_SCTL13_INTPOS_Msk           (0x1ul << EADC_SCTL13_INTPOS_Pos)                 /*!< EADC_T::SCTL13: INTPOS Mask            */
+
+#define EADC_SCTL13_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL13: EXTSMPT Position       */
+#define EADC_SCTL13_EXTSMPT_Msk          (0xfful << EADC_SCTL13_EXTSMPT_Pos)               /*!< EADC_T::SCTL13: EXTSMPT Mask           */
+
+#define EADC_SCTL14_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL14: CHSEL Position         */
+#define EADC_SCTL14_CHSEL_Msk            (0xful << EADC_SCTL14_CHSEL_Pos)                  /*!< EADC_T::SCTL14: CHSEL Mask             */
+
+#define EADC_SCTL14_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL14: EXTREN Position        */
+#define EADC_SCTL14_EXTREN_Msk           (0x1ul << EADC_SCTL14_EXTREN_Pos)                 /*!< EADC_T::SCTL14: EXTREN Mask            */
+
+#define EADC_SCTL14_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL14: EXTFEN Position        */
+#define EADC_SCTL14_EXTFEN_Msk           (0x1ul << EADC_SCTL14_EXTFEN_Pos)                 /*!< EADC_T::SCTL14: EXTFEN Mask            */
+
+#define EADC_SCTL14_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL14: TRGDLYDIV Position     */
+#define EADC_SCTL14_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL14: TRGDLYDIV Mask         */
+
+#define EADC_SCTL14_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL14: TRGDLYCNT Position     */
+#define EADC_SCTL14_TRGDLYCNT_Msk        (0xfful << EADC_SCTL14_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL14: TRGDLYCNT Mask         */
+
+#define EADC_SCTL14_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL14: TRGSEL Position        */
+#define EADC_SCTL14_TRGSEL_Msk           (0x1ful << EADC_SCTL14_TRGSEL_Pos)                /*!< EADC_T::SCTL14: TRGSEL Mask            */
+
+#define EADC_SCTL14_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL14: INTPOS Position        */
+#define EADC_SCTL14_INTPOS_Msk           (0x1ul << EADC_SCTL14_INTPOS_Pos)                 /*!< EADC_T::SCTL14: INTPOS Mask            */
+
+#define EADC_SCTL14_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL14: EXTSMPT Position       */
+#define EADC_SCTL14_EXTSMPT_Msk          (0xfful << EADC_SCTL14_EXTSMPT_Pos)               /*!< EADC_T::SCTL14: EXTSMPT Mask           */
+
+#define EADC_SCTL15_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL15: CHSEL Position         */
+#define EADC_SCTL15_CHSEL_Msk            (0xful << EADC_SCTL15_CHSEL_Pos)                  /*!< EADC_T::SCTL15: CHSEL Mask             */
+
+#define EADC_SCTL15_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL15: EXTREN Position        */
+#define EADC_SCTL15_EXTREN_Msk           (0x1ul << EADC_SCTL15_EXTREN_Pos)                 /*!< EADC_T::SCTL15: EXTREN Mask            */
+
+#define EADC_SCTL15_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL15: EXTFEN Position        */
+#define EADC_SCTL15_EXTFEN_Msk           (0x1ul << EADC_SCTL15_EXTFEN_Pos)                 /*!< EADC_T::SCTL15: EXTFEN Mask            */
+
+#define EADC_SCTL15_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL15: TRGDLYDIV Position     */
+#define EADC_SCTL15_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL15: TRGDLYDIV Mask         */
+
+#define EADC_SCTL15_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL15: TRGDLYCNT Position     */
+#define EADC_SCTL15_TRGDLYCNT_Msk        (0xfful << EADC_SCTL15_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL15: TRGDLYCNT Mask         */
+
+#define EADC_SCTL15_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL15: TRGSEL Position        */
+#define EADC_SCTL15_TRGSEL_Msk           (0x1ful << EADC_SCTL15_TRGSEL_Pos)                /*!< EADC_T::SCTL15: TRGSEL Mask            */
+
+#define EADC_SCTL15_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL15: INTPOS Position        */
+#define EADC_SCTL15_INTPOS_Msk           (0x1ul << EADC_SCTL15_INTPOS_Pos)                 /*!< EADC_T::SCTL15: INTPOS Mask            */
+
+#define EADC_SCTL15_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL15: EXTSMPT Position       */
+#define EADC_SCTL15_EXTSMPT_Msk          (0xfful << EADC_SCTL15_EXTSMPT_Pos)               /*!< EADC_T::SCTL15: EXTSMPT Mask           */
+
+#define EADC_SCTL16_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL16: EXTSMPT Position       */
+#define EADC_SCTL16_EXTSMPT_Msk          (0xfful << EADC_SCTL16_EXTSMPT_Pos)               /*!< EADC_T::SCTL16: EXTSMPT Mask           */
+
+#define EADC_SCTL17_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL17: EXTSMPT Position       */
+#define EADC_SCTL17_EXTSMPT_Msk          (0xfful << EADC_SCTL17_EXTSMPT_Pos)               /*!< EADC_T::SCTL17: EXTSMPT Mask           */
+
+#define EADC_SCTL18_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL18: EXTSMPT Position       */
+#define EADC_SCTL18_EXTSMPT_Msk          (0xfful << EADC_SCTL18_EXTSMPT_Pos)               /*!< EADC_T::SCTL18: EXTSMPT Mask           */
+
+#define EADC_INTSRC0_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC0: SPLIE0 Position       */
+#define EADC_INTSRC0_SPLIE0_Msk          (0x1ul << EADC_INTSRC0_SPLIE0_Pos)                /*!< EADC_T::INTSRC0: SPLIE0 Mask           */
+
+#define EADC_INTSRC0_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC0: SPLIE1 Position       */
+#define EADC_INTSRC0_SPLIE1_Msk          (0x1ul << EADC_INTSRC0_SPLIE1_Pos)                /*!< EADC_T::INTSRC0: SPLIE1 Mask           */
+
+#define EADC_INTSRC0_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC0: SPLIE2 Position       */
+#define EADC_INTSRC0_SPLIE2_Msk          (0x1ul << EADC_INTSRC0_SPLIE2_Pos)                /*!< EADC_T::INTSRC0: SPLIE2 Mask           */
+
+#define EADC_INTSRC0_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC0: SPLIE3 Position       */
+#define EADC_INTSRC0_SPLIE3_Msk          (0x1ul << EADC_INTSRC0_SPLIE3_Pos)                /*!< EADC_T::INTSRC0: SPLIE3 Mask           */
+
+#define EADC_INTSRC0_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC0: SPLIE4 Position       */
+#define EADC_INTSRC0_SPLIE4_Msk          (0x1ul << EADC_INTSRC0_SPLIE4_Pos)                /*!< EADC_T::INTSRC0: SPLIE4 Mask           */
+
+#define EADC_INTSRC0_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC0: SPLIE5 Position       */
+#define EADC_INTSRC0_SPLIE5_Msk          (0x1ul << EADC_INTSRC0_SPLIE5_Pos)                /*!< EADC_T::INTSRC0: SPLIE5 Mask           */
+
+#define EADC_INTSRC0_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC0: SPLIE6 Position       */
+#define EADC_INTSRC0_SPLIE6_Msk          (0x1ul << EADC_INTSRC0_SPLIE6_Pos)                /*!< EADC_T::INTSRC0: SPLIE6 Mask           */
+
+#define EADC_INTSRC0_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC0: SPLIE7 Position       */
+#define EADC_INTSRC0_SPLIE7_Msk          (0x1ul << EADC_INTSRC0_SPLIE7_Pos)                /*!< EADC_T::INTSRC0: SPLIE7 Mask           */
+
+#define EADC_INTSRC0_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC0: SPLIE8 Position       */
+#define EADC_INTSRC0_SPLIE8_Msk          (0x1ul << EADC_INTSRC0_SPLIE8_Pos)                /*!< EADC_T::INTSRC0: SPLIE8 Mask           */
+
+#define EADC_INTSRC0_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC0: SPLIE9 Position       */
+#define EADC_INTSRC0_SPLIE9_Msk          (0x1ul << EADC_INTSRC0_SPLIE9_Pos)                /*!< EADC_T::INTSRC0: SPLIE9 Mask           */
+
+#define EADC_INTSRC0_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC0: SPLIE10 Position      */
+#define EADC_INTSRC0_SPLIE10_Msk         (0x1ul << EADC_INTSRC0_SPLIE10_Pos)               /*!< EADC_T::INTSRC0: SPLIE10 Mask          */
+
+#define EADC_INTSRC0_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC0: SPLIE11 Position      */
+#define EADC_INTSRC0_SPLIE11_Msk         (0x1ul << EADC_INTSRC0_SPLIE11_Pos)               /*!< EADC_T::INTSRC0: SPLIE11 Mask          */
+
+#define EADC_INTSRC0_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC0: SPLIE12 Position      */
+#define EADC_INTSRC0_SPLIE12_Msk         (0x1ul << EADC_INTSRC0_SPLIE12_Pos)               /*!< EADC_T::INTSRC0: SPLIE12 Mask          */
+
+#define EADC_INTSRC0_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC0: SPLIE13 Position      */
+#define EADC_INTSRC0_SPLIE13_Msk         (0x1ul << EADC_INTSRC0_SPLIE13_Pos)               /*!< EADC_T::INTSRC0: SPLIE13 Mask          */
+
+#define EADC_INTSRC0_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC0: SPLIE14 Position      */
+#define EADC_INTSRC0_SPLIE14_Msk         (0x1ul << EADC_INTSRC0_SPLIE14_Pos)               /*!< EADC_T::INTSRC0: SPLIE14 Mask          */
+
+#define EADC_INTSRC0_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC0: SPLIE15 Position      */
+#define EADC_INTSRC0_SPLIE15_Msk         (0x1ul << EADC_INTSRC0_SPLIE15_Pos)               /*!< EADC_T::INTSRC0: SPLIE15 Mask          */
+
+#define EADC_INTSRC0_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC0: SPLIE16 Position      */
+#define EADC_INTSRC0_SPLIE16_Msk         (0x1ul << EADC_INTSRC0_SPLIE16_Pos)               /*!< EADC_T::INTSRC0: SPLIE16 Mask          */
+
+#define EADC_INTSRC0_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC0: SPLIE17 Position      */
+#define EADC_INTSRC0_SPLIE17_Msk         (0x1ul << EADC_INTSRC0_SPLIE17_Pos)               /*!< EADC_T::INTSRC0: SPLIE17 Mask          */
+
+#define EADC_INTSRC0_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC0: SPLIE18 Position      */
+#define EADC_INTSRC0_SPLIE18_Msk         (0x1ul << EADC_INTSRC0_SPLIE18_Pos)               /*!< EADC_T::INTSRC0: SPLIE18 Mask          */
+
+#define EADC_INTSRC1_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC1: SPLIE0 Position       */
+#define EADC_INTSRC1_SPLIE0_Msk          (0x1ul << EADC_INTSRC1_SPLIE0_Pos)                /*!< EADC_T::INTSRC1: SPLIE0 Mask           */
+
+#define EADC_INTSRC1_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC1: SPLIE1 Position       */
+#define EADC_INTSRC1_SPLIE1_Msk          (0x1ul << EADC_INTSRC1_SPLIE1_Pos)                /*!< EADC_T::INTSRC1: SPLIE1 Mask           */
+
+#define EADC_INTSRC1_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC1: SPLIE2 Position       */
+#define EADC_INTSRC1_SPLIE2_Msk          (0x1ul << EADC_INTSRC1_SPLIE2_Pos)                /*!< EADC_T::INTSRC1: SPLIE2 Mask           */
+
+#define EADC_INTSRC1_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC1: SPLIE3 Position       */
+#define EADC_INTSRC1_SPLIE3_Msk          (0x1ul << EADC_INTSRC1_SPLIE3_Pos)                /*!< EADC_T::INTSRC1: SPLIE3 Mask           */
+
+#define EADC_INTSRC1_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC1: SPLIE4 Position       */
+#define EADC_INTSRC1_SPLIE4_Msk          (0x1ul << EADC_INTSRC1_SPLIE4_Pos)                /*!< EADC_T::INTSRC1: SPLIE4 Mask           */
+
+#define EADC_INTSRC1_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC1: SPLIE5 Position       */
+#define EADC_INTSRC1_SPLIE5_Msk          (0x1ul << EADC_INTSRC1_SPLIE5_Pos)                /*!< EADC_T::INTSRC1: SPLIE5 Mask           */
+
+#define EADC_INTSRC1_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC1: SPLIE6 Position       */
+#define EADC_INTSRC1_SPLIE6_Msk          (0x1ul << EADC_INTSRC1_SPLIE6_Pos)                /*!< EADC_T::INTSRC1: SPLIE6 Mask           */
+
+#define EADC_INTSRC1_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC1: SPLIE7 Position       */
+#define EADC_INTSRC1_SPLIE7_Msk          (0x1ul << EADC_INTSRC1_SPLIE7_Pos)                /*!< EADC_T::INTSRC1: SPLIE7 Mask           */
+
+#define EADC_INTSRC1_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC1: SPLIE8 Position       */
+#define EADC_INTSRC1_SPLIE8_Msk          (0x1ul << EADC_INTSRC1_SPLIE8_Pos)                /*!< EADC_T::INTSRC1: SPLIE8 Mask           */
+
+#define EADC_INTSRC1_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC1: SPLIE9 Position       */
+#define EADC_INTSRC1_SPLIE9_Msk          (0x1ul << EADC_INTSRC1_SPLIE9_Pos)                /*!< EADC_T::INTSRC1: SPLIE9 Mask           */
+
+#define EADC_INTSRC1_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC1: SPLIE10 Position      */
+#define EADC_INTSRC1_SPLIE10_Msk         (0x1ul << EADC_INTSRC1_SPLIE10_Pos)               /*!< EADC_T::INTSRC1: SPLIE10 Mask          */
+
+#define EADC_INTSRC1_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC1: SPLIE11 Position      */
+#define EADC_INTSRC1_SPLIE11_Msk         (0x1ul << EADC_INTSRC1_SPLIE11_Pos)               /*!< EADC_T::INTSRC1: SPLIE11 Mask          */
+
+#define EADC_INTSRC1_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC1: SPLIE12 Position      */
+#define EADC_INTSRC1_SPLIE12_Msk         (0x1ul << EADC_INTSRC1_SPLIE12_Pos)               /*!< EADC_T::INTSRC1: SPLIE12 Mask          */
+
+#define EADC_INTSRC1_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC1: SPLIE13 Position      */
+#define EADC_INTSRC1_SPLIE13_Msk         (0x1ul << EADC_INTSRC1_SPLIE13_Pos)               /*!< EADC_T::INTSRC1: SPLIE13 Mask          */
+
+#define EADC_INTSRC1_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC1: SPLIE14 Position      */
+#define EADC_INTSRC1_SPLIE14_Msk         (0x1ul << EADC_INTSRC1_SPLIE14_Pos)               /*!< EADC_T::INTSRC1: SPLIE14 Mask          */
+
+#define EADC_INTSRC1_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC1: SPLIE15 Position      */
+#define EADC_INTSRC1_SPLIE15_Msk         (0x1ul << EADC_INTSRC1_SPLIE15_Pos)               /*!< EADC_T::INTSRC1: SPLIE15 Mask          */
+
+#define EADC_INTSRC1_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC1: SPLIE16 Position      */
+#define EADC_INTSRC1_SPLIE16_Msk         (0x1ul << EADC_INTSRC1_SPLIE16_Pos)               /*!< EADC_T::INTSRC1: SPLIE16 Mask          */
+
+#define EADC_INTSRC1_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC1: SPLIE17 Position      */
+#define EADC_INTSRC1_SPLIE17_Msk         (0x1ul << EADC_INTSRC1_SPLIE17_Pos)               /*!< EADC_T::INTSRC1: SPLIE17 Mask          */
+
+#define EADC_INTSRC1_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC1: SPLIE18 Position      */
+#define EADC_INTSRC1_SPLIE18_Msk         (0x1ul << EADC_INTSRC1_SPLIE18_Pos)               /*!< EADC_T::INTSRC1: SPLIE18 Mask          */
+
+#define EADC_INTSRC2_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC2: SPLIE0 Position       */
+#define EADC_INTSRC2_SPLIE0_Msk          (0x1ul << EADC_INTSRC2_SPLIE0_Pos)                /*!< EADC_T::INTSRC2: SPLIE0 Mask           */
+
+#define EADC_INTSRC2_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC2: SPLIE1 Position       */
+#define EADC_INTSRC2_SPLIE1_Msk          (0x1ul << EADC_INTSRC2_SPLIE1_Pos)                /*!< EADC_T::INTSRC2: SPLIE1 Mask           */
+
+#define EADC_INTSRC2_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC2: SPLIE2 Position       */
+#define EADC_INTSRC2_SPLIE2_Msk          (0x1ul << EADC_INTSRC2_SPLIE2_Pos)                /*!< EADC_T::INTSRC2: SPLIE2 Mask           */
+
+#define EADC_INTSRC2_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC2: SPLIE3 Position       */
+#define EADC_INTSRC2_SPLIE3_Msk          (0x1ul << EADC_INTSRC2_SPLIE3_Pos)                /*!< EADC_T::INTSRC2: SPLIE3 Mask           */
+
+#define EADC_INTSRC2_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC2: SPLIE4 Position       */
+#define EADC_INTSRC2_SPLIE4_Msk          (0x1ul << EADC_INTSRC2_SPLIE4_Pos)                /*!< EADC_T::INTSRC2: SPLIE4 Mask           */
+
+#define EADC_INTSRC2_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC2: SPLIE5 Position       */
+#define EADC_INTSRC2_SPLIE5_Msk          (0x1ul << EADC_INTSRC2_SPLIE5_Pos)                /*!< EADC_T::INTSRC2: SPLIE5 Mask           */
+
+#define EADC_INTSRC2_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC2: SPLIE6 Position       */
+#define EADC_INTSRC2_SPLIE6_Msk          (0x1ul << EADC_INTSRC2_SPLIE6_Pos)                /*!< EADC_T::INTSRC2: SPLIE6 Mask           */
+
+#define EADC_INTSRC2_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC2: SPLIE7 Position       */
+#define EADC_INTSRC2_SPLIE7_Msk          (0x1ul << EADC_INTSRC2_SPLIE7_Pos)                /*!< EADC_T::INTSRC2: SPLIE7 Mask           */
+
+#define EADC_INTSRC2_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC2: SPLIE8 Position       */
+#define EADC_INTSRC2_SPLIE8_Msk          (0x1ul << EADC_INTSRC2_SPLIE8_Pos)                /*!< EADC_T::INTSRC2: SPLIE8 Mask           */
+
+#define EADC_INTSRC2_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC2: SPLIE9 Position       */
+#define EADC_INTSRC2_SPLIE9_Msk          (0x1ul << EADC_INTSRC2_SPLIE9_Pos)                /*!< EADC_T::INTSRC2: SPLIE9 Mask           */
+
+#define EADC_INTSRC2_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC2: SPLIE10 Position      */
+#define EADC_INTSRC2_SPLIE10_Msk         (0x1ul << EADC_INTSRC2_SPLIE10_Pos)               /*!< EADC_T::INTSRC2: SPLIE10 Mask          */
+
+#define EADC_INTSRC2_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC2: SPLIE11 Position      */
+#define EADC_INTSRC2_SPLIE11_Msk         (0x1ul << EADC_INTSRC2_SPLIE11_Pos)               /*!< EADC_T::INTSRC2: SPLIE11 Mask          */
+
+#define EADC_INTSRC2_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC2: SPLIE12 Position      */
+#define EADC_INTSRC2_SPLIE12_Msk         (0x1ul << EADC_INTSRC2_SPLIE12_Pos)               /*!< EADC_T::INTSRC2: SPLIE12 Mask          */
+
+#define EADC_INTSRC2_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC2: SPLIE13 Position      */
+#define EADC_INTSRC2_SPLIE13_Msk         (0x1ul << EADC_INTSRC2_SPLIE13_Pos)               /*!< EADC_T::INTSRC2: SPLIE13 Mask          */
+
+#define EADC_INTSRC2_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC2: SPLIE14 Position      */
+#define EADC_INTSRC2_SPLIE14_Msk         (0x1ul << EADC_INTSRC2_SPLIE14_Pos)               /*!< EADC_T::INTSRC2: SPLIE14 Mask          */
+
+#define EADC_INTSRC2_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC2: SPLIE15 Position      */
+#define EADC_INTSRC2_SPLIE15_Msk         (0x1ul << EADC_INTSRC2_SPLIE15_Pos)               /*!< EADC_T::INTSRC2: SPLIE15 Mask          */
+
+#define EADC_INTSRC2_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC2: SPLIE16 Position      */
+#define EADC_INTSRC2_SPLIE16_Msk         (0x1ul << EADC_INTSRC2_SPLIE16_Pos)               /*!< EADC_T::INTSRC2: SPLIE16 Mask          */
+
+#define EADC_INTSRC2_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC2: SPLIE17 Position      */
+#define EADC_INTSRC2_SPLIE17_Msk         (0x1ul << EADC_INTSRC2_SPLIE17_Pos)               /*!< EADC_T::INTSRC2: SPLIE17 Mask          */
+
+#define EADC_INTSRC2_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC2: SPLIE18 Position      */
+#define EADC_INTSRC2_SPLIE18_Msk         (0x1ul << EADC_INTSRC2_SPLIE18_Pos)               /*!< EADC_T::INTSRC2: SPLIE18 Mask          */
+
+#define EADC_INTSRC3_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC3: SPLIE0 Position       */
+#define EADC_INTSRC3_SPLIE0_Msk          (0x1ul << EADC_INTSRC3_SPLIE0_Pos)                /*!< EADC_T::INTSRC3: SPLIE0 Mask           */
+
+#define EADC_INTSRC3_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC3: SPLIE1 Position       */
+#define EADC_INTSRC3_SPLIE1_Msk          (0x1ul << EADC_INTSRC3_SPLIE1_Pos)                /*!< EADC_T::INTSRC3: SPLIE1 Mask           */
+
+#define EADC_INTSRC3_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC3: SPLIE2 Position       */
+#define EADC_INTSRC3_SPLIE2_Msk          (0x1ul << EADC_INTSRC3_SPLIE2_Pos)                /*!< EADC_T::INTSRC3: SPLIE2 Mask           */
+
+#define EADC_INTSRC3_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC3: SPLIE3 Position       */
+#define EADC_INTSRC3_SPLIE3_Msk          (0x1ul << EADC_INTSRC3_SPLIE3_Pos)                /*!< EADC_T::INTSRC3: SPLIE3 Mask           */
+
+#define EADC_INTSRC3_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC3: SPLIE4 Position       */
+#define EADC_INTSRC3_SPLIE4_Msk          (0x1ul << EADC_INTSRC3_SPLIE4_Pos)                /*!< EADC_T::INTSRC3: SPLIE4 Mask           */
+
+#define EADC_INTSRC3_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC3: SPLIE5 Position       */
+#define EADC_INTSRC3_SPLIE5_Msk          (0x1ul << EADC_INTSRC3_SPLIE5_Pos)                /*!< EADC_T::INTSRC3: SPLIE5 Mask           */
+
+#define EADC_INTSRC3_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC3: SPLIE6 Position       */
+#define EADC_INTSRC3_SPLIE6_Msk          (0x1ul << EADC_INTSRC3_SPLIE6_Pos)                /*!< EADC_T::INTSRC3: SPLIE6 Mask           */
+
+#define EADC_INTSRC3_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC3: SPLIE7 Position       */
+#define EADC_INTSRC3_SPLIE7_Msk          (0x1ul << EADC_INTSRC3_SPLIE7_Pos)                /*!< EADC_T::INTSRC3: SPLIE7 Mask           */
+
+#define EADC_INTSRC3_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC3: SPLIE8 Position       */
+#define EADC_INTSRC3_SPLIE8_Msk          (0x1ul << EADC_INTSRC3_SPLIE8_Pos)                /*!< EADC_T::INTSRC3: SPLIE8 Mask           */
+
+#define EADC_INTSRC3_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC3: SPLIE9 Position       */
+#define EADC_INTSRC3_SPLIE9_Msk          (0x1ul << EADC_INTSRC3_SPLIE9_Pos)                /*!< EADC_T::INTSRC3: SPLIE9 Mask           */
+
+#define EADC_INTSRC3_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC3: SPLIE10 Position      */
+#define EADC_INTSRC3_SPLIE10_Msk         (0x1ul << EADC_INTSRC3_SPLIE10_Pos)               /*!< EADC_T::INTSRC3: SPLIE10 Mask          */
+
+#define EADC_INTSRC3_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC3: SPLIE11 Position      */
+#define EADC_INTSRC3_SPLIE11_Msk         (0x1ul << EADC_INTSRC3_SPLIE11_Pos)               /*!< EADC_T::INTSRC3: SPLIE11 Mask          */
+
+#define EADC_INTSRC3_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC3: SPLIE12 Position      */
+#define EADC_INTSRC3_SPLIE12_Msk         (0x1ul << EADC_INTSRC3_SPLIE12_Pos)               /*!< EADC_T::INTSRC3: SPLIE12 Mask          */
+
+#define EADC_INTSRC3_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC3: SPLIE13 Position      */
+#define EADC_INTSRC3_SPLIE13_Msk         (0x1ul << EADC_INTSRC3_SPLIE13_Pos)               /*!< EADC_T::INTSRC3: SPLIE13 Mask          */
+
+#define EADC_INTSRC3_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC3: SPLIE14 Position      */
+#define EADC_INTSRC3_SPLIE14_Msk         (0x1ul << EADC_INTSRC3_SPLIE14_Pos)               /*!< EADC_T::INTSRC3: SPLIE14 Mask          */
+
+#define EADC_INTSRC3_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC3: SPLIE15 Position      */
+#define EADC_INTSRC3_SPLIE15_Msk         (0x1ul << EADC_INTSRC3_SPLIE15_Pos)               /*!< EADC_T::INTSRC3: SPLIE15 Mask          */
+
+#define EADC_INTSRC3_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC3: SPLIE16 Position      */
+#define EADC_INTSRC3_SPLIE16_Msk         (0x1ul << EADC_INTSRC3_SPLIE16_Pos)               /*!< EADC_T::INTSRC3: SPLIE16 Mask          */
+
+#define EADC_INTSRC3_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC3: SPLIE17 Position      */
+#define EADC_INTSRC3_SPLIE17_Msk         (0x1ul << EADC_INTSRC3_SPLIE17_Pos)               /*!< EADC_T::INTSRC3: SPLIE17 Mask          */
+
+#define EADC_INTSRC3_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC3: SPLIE18 Position      */
+#define EADC_INTSRC3_SPLIE18_Msk         (0x1ul << EADC_INTSRC3_SPLIE18_Pos)               /*!< EADC_T::INTSRC3: SPLIE18 Mask          */
+
+#define EADC_CMP_ADCMPEN_Pos             (0)                                               /*!< EADC_T::CMP: ADCMPEN Position          */
+#define EADC_CMP_ADCMPEN_Msk             (0x1ul << EADC_CMP_ADCMPEN_Pos)                   /*!< EADC_T::CMP: ADCMPEN Mask              */
+
+#define EADC_CMP_ADCMPIE_Pos             (1)                                               /*!< EADC_T::CMP: ADCMPIE Position          */
+#define EADC_CMP_ADCMPIE_Msk             (0x1ul << EADC_CMP_ADCMPIE_Pos)                   /*!< EADC_T::CMP: ADCMPIE Mask              */
+
+#define EADC_CMP_CMPCOND_Pos             (2)                                               /*!< EADC_T::CMP: CMPCOND Position          */
+#define EADC_CMP_CMPCOND_Msk             (0x1ul << EADC_CMP_CMPCOND_Pos)                   /*!< EADC_T::CMP: CMPCOND Mask              */
+
+#define EADC_CMP_CMPSPL_Pos              (3)                                               /*!< EADC_T::CMP: CMPSPL Position           */
+#define EADC_CMP_CMPSPL_Msk              (0x1ful << EADC_CMP_CMPSPL_Pos)                   /*!< EADC_T::CMP: CMPSPL Mask               */
+
+#define EADC_CMP_CMPMCNT_Pos             (8)                                               /*!< EADC_T::CMP: CMPMCNT Position          */
+#define EADC_CMP_CMPMCNT_Msk             (0xful << EADC_CMP_CMPMCNT_Pos)                   /*!< EADC_T::CMP: CMPMCNT Mask              */
+
+#define EADC_CMP_CMPWEN_Pos              (15)                                              /*!< EADC_T::CMP: CMPWEN Position           */
+#define EADC_CMP_CMPWEN_Msk              (0x1ul << EADC_CMP_CMPWEN_Pos)                    /*!< EADC_T::CMP: CMPWEN Mask               */
+
+#define EADC_CMP_CMPDAT_Pos              (16)                                              /*!< EADC_T::CMP: CMPDAT Position           */
+#define EADC_CMP_CMPDAT_Msk              (0xffful << EADC_CMP_CMPDAT_Pos)                  /*!< EADC_T::CMP: CMPDAT Mask               */
+
+#define EADC_CMP0_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP0: ADCMPEN Position         */
+#define EADC_CMP0_ADCMPEN_Msk            (0x1ul << EADC_CMP0_ADCMPEN_Pos)                  /*!< EADC_T::CMP0: ADCMPEN Mask             */
+
+#define EADC_CMP0_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP0: ADCMPIE Position         */
+#define EADC_CMP0_ADCMPIE_Msk            (0x1ul << EADC_CMP0_ADCMPIE_Pos)                  /*!< EADC_T::CMP0: ADCMPIE Mask             */
+
+#define EADC_CMP0_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP0: CMPCOND Position         */
+#define EADC_CMP0_CMPCOND_Msk            (0x1ul << EADC_CMP0_CMPCOND_Pos)                  /*!< EADC_T::CMP0: CMPCOND Mask             */
+
+#define EADC_CMP0_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP0: CMPSPL Position          */
+#define EADC_CMP0_CMPSPL_Msk             (0x1ful << EADC_CMP0_CMPSPL_Pos)                  /*!< EADC_T::CMP0: CMPSPL Mask              */
+
+#define EADC_CMP0_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP0: CMPMCNT Position         */
+#define EADC_CMP0_CMPMCNT_Msk            (0xful << EADC_CMP0_CMPMCNT_Pos)                  /*!< EADC_T::CMP0: CMPMCNT Mask             */
+
+#define EADC_CMP0_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP0: CMPWEN Position          */
+#define EADC_CMP0_CMPWEN_Msk             (0x1ul << EADC_CMP0_CMPWEN_Pos)                   /*!< EADC_T::CMP0: CMPWEN Mask              */
+
+#define EADC_CMP0_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP0: CMPDAT Position          */
+#define EADC_CMP0_CMPDAT_Msk             (0xffful << EADC_CMP0_CMPDAT_Pos)                 /*!< EADC_T::CMP0: CMPDAT Mask              */
+
+#define EADC_CMP1_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP1: ADCMPEN Position         */
+#define EADC_CMP1_ADCMPEN_Msk            (0x1ul << EADC_CMP1_ADCMPEN_Pos)                  /*!< EADC_T::CMP1: ADCMPEN Mask             */
+
+#define EADC_CMP1_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP1: ADCMPIE Position         */
+#define EADC_CMP1_ADCMPIE_Msk            (0x1ul << EADC_CMP1_ADCMPIE_Pos)                  /*!< EADC_T::CMP1: ADCMPIE Mask             */
+
+#define EADC_CMP1_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP1: CMPCOND Position         */
+#define EADC_CMP1_CMPCOND_Msk            (0x1ul << EADC_CMP1_CMPCOND_Pos)                  /*!< EADC_T::CMP1: CMPCOND Mask             */
+
+#define EADC_CMP1_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP1: CMPSPL Position          */
+#define EADC_CMP1_CMPSPL_Msk             (0x1ful << EADC_CMP1_CMPSPL_Pos)                  /*!< EADC_T::CMP1: CMPSPL Mask              */
+
+#define EADC_CMP1_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP1: CMPMCNT Position         */
+#define EADC_CMP1_CMPMCNT_Msk            (0xful << EADC_CMP1_CMPMCNT_Pos)                  /*!< EADC_T::CMP1: CMPMCNT Mask             */
+
+#define EADC_CMP1_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP1: CMPWEN Position          */
+#define EADC_CMP1_CMPWEN_Msk             (0x1ul << EADC_CMP1_CMPWEN_Pos)                   /*!< EADC_T::CMP1: CMPWEN Mask              */
+
+#define EADC_CMP1_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP1: CMPDAT Position          */
+#define EADC_CMP1_CMPDAT_Msk             (0xffful << EADC_CMP1_CMPDAT_Pos)                 /*!< EADC_T::CMP1: CMPDAT Mask              */
+
+#define EADC_CMP2_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP2: ADCMPEN Position         */
+#define EADC_CMP2_ADCMPEN_Msk            (0x1ul << EADC_CMP2_ADCMPEN_Pos)                  /*!< EADC_T::CMP2: ADCMPEN Mask             */
+
+#define EADC_CMP2_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP2: ADCMPIE Position         */
+#define EADC_CMP2_ADCMPIE_Msk            (0x1ul << EADC_CMP2_ADCMPIE_Pos)                  /*!< EADC_T::CMP2: ADCMPIE Mask             */
+
+#define EADC_CMP2_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP2: CMPCOND Position         */
+#define EADC_CMP2_CMPCOND_Msk            (0x1ul << EADC_CMP2_CMPCOND_Pos)                  /*!< EADC_T::CMP2: CMPCOND Mask             */
+
+#define EADC_CMP2_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP2: CMPSPL Position          */
+#define EADC_CMP2_CMPSPL_Msk             (0x1ful << EADC_CMP2_CMPSPL_Pos)                  /*!< EADC_T::CMP2: CMPSPL Mask              */
+
+#define EADC_CMP2_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP2: CMPMCNT Position         */
+#define EADC_CMP2_CMPMCNT_Msk            (0xful << EADC_CMP2_CMPMCNT_Pos)                  /*!< EADC_T::CMP2: CMPMCNT Mask             */
+
+#define EADC_CMP2_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP2: CMPWEN Position          */
+#define EADC_CMP2_CMPWEN_Msk             (0x1ul << EADC_CMP2_CMPWEN_Pos)                   /*!< EADC_T::CMP2: CMPWEN Mask              */
+
+#define EADC_CMP2_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP2: CMPDAT Position          */
+#define EADC_CMP2_CMPDAT_Msk             (0xffful << EADC_CMP2_CMPDAT_Pos)                 /*!< EADC_T::CMP2: CMPDAT Mask              */
+
+#define EADC_CMP3_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP3: ADCMPEN Position         */
+#define EADC_CMP3_ADCMPEN_Msk            (0x1ul << EADC_CMP3_ADCMPEN_Pos)                  /*!< EADC_T::CMP3: ADCMPEN Mask             */
+
+#define EADC_CMP3_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP3: ADCMPIE Position         */
+#define EADC_CMP3_ADCMPIE_Msk            (0x1ul << EADC_CMP3_ADCMPIE_Pos)                  /*!< EADC_T::CMP3: ADCMPIE Mask             */
+
+#define EADC_CMP3_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP3: CMPCOND Position         */
+#define EADC_CMP3_CMPCOND_Msk            (0x1ul << EADC_CMP3_CMPCOND_Pos)                  /*!< EADC_T::CMP3: CMPCOND Mask             */
+
+#define EADC_CMP3_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP3: CMPSPL Position          */
+#define EADC_CMP3_CMPSPL_Msk             (0x1ful << EADC_CMP3_CMPSPL_Pos)                  /*!< EADC_T::CMP3: CMPSPL Mask              */
+
+#define EADC_CMP3_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP3: CMPMCNT Position         */
+#define EADC_CMP3_CMPMCNT_Msk            (0xful << EADC_CMP3_CMPMCNT_Pos)                  /*!< EADC_T::CMP3: CMPMCNT Mask             */
+
+#define EADC_CMP3_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP3: CMPWEN Position          */
+#define EADC_CMP3_CMPWEN_Msk             (0x1ul << EADC_CMP3_CMPWEN_Pos)                   /*!< EADC_T::CMP3: CMPWEN Mask              */
+
+#define EADC_CMP3_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP3: CMPDAT Position          */
+#define EADC_CMP3_CMPDAT_Msk             (0xffful << EADC_CMP3_CMPDAT_Pos)                 /*!< EADC_T::CMP3: CMPDAT Mask              */
+
+#define EADC_STATUS0_VALID_Pos           (0)                                               /*!< EADC_T::STATUS0: VALID Position        */
+#define EADC_STATUS0_VALID_Msk           (0xfffful << EADC_STATUS0_VALID_Pos)              /*!< EADC_T::STATUS0: VALID Mask            */
+
+#define EADC_STATUS0_OV_Pos              (16)                                              /*!< EADC_T::STATUS0: OV Position           */
+#define EADC_STATUS0_OV_Msk              (0xfffful << EADC_STATUS0_OV_Pos)                 /*!< EADC_T::STATUS0: OV Mask               */
+
+#define EADC_STATUS1_VALID_Pos           (0)                                               /*!< EADC_T::STATUS1: VALID Position        */
+#define EADC_STATUS1_VALID_Msk           (0x7ul << EADC_STATUS1_VALID_Pos)                 /*!< EADC_T::STATUS1: VALID Mask            */
+
+#define EADC_STATUS1_OV_Pos              (16)                                              /*!< EADC_T::STATUS1: OV Position           */
+#define EADC_STATUS1_OV_Msk              (0x7ul << EADC_STATUS1_OV_Pos)                    /*!< EADC_T::STATUS1: OV Mask               */
+
+#define EADC_STATUS2_ADIF0_Pos           (0)                                               /*!< EADC_T::STATUS2: ADIF0 Position        */
+#define EADC_STATUS2_ADIF0_Msk           (0x1ul << EADC_STATUS2_ADIF0_Pos)                 /*!< EADC_T::STATUS2: ADIF0 Mask            */
+
+#define EADC_STATUS2_ADIF1_Pos           (1)                                               /*!< EADC_T::STATUS2: ADIF1 Position        */
+#define EADC_STATUS2_ADIF1_Msk           (0x1ul << EADC_STATUS2_ADIF1_Pos)                 /*!< EADC_T::STATUS2: ADIF1 Mask            */
+
+#define EADC_STATUS2_ADIF2_Pos           (2)                                               /*!< EADC_T::STATUS2: ADIF2 Position        */
+#define EADC_STATUS2_ADIF2_Msk           (0x1ul << EADC_STATUS2_ADIF2_Pos)                 /*!< EADC_T::STATUS2: ADIF2 Mask            */
+
+#define EADC_STATUS2_ADIF3_Pos           (3)                                               /*!< EADC_T::STATUS2: ADIF3 Position        */
+#define EADC_STATUS2_ADIF3_Msk           (0x1ul << EADC_STATUS2_ADIF3_Pos)                 /*!< EADC_T::STATUS2: ADIF3 Mask            */
+
+#define EADC_STATUS2_ADCMPF0_Pos         (4)                                               /*!< EADC_T::STATUS2: ADCMPF0 Position      */
+#define EADC_STATUS2_ADCMPF0_Msk         (0x1ul << EADC_STATUS2_ADCMPF0_Pos)               /*!< EADC_T::STATUS2: ADCMPF0 Mask          */
+
+#define EADC_STATUS2_ADCMPF1_Pos         (5)                                               /*!< EADC_T::STATUS2: ADCMPF1 Position      */
+#define EADC_STATUS2_ADCMPF1_Msk         (0x1ul << EADC_STATUS2_ADCMPF1_Pos)               /*!< EADC_T::STATUS2: ADCMPF1 Mask          */
+
+#define EADC_STATUS2_ADCMPF2_Pos         (6)                                               /*!< EADC_T::STATUS2: ADCMPF2 Position      */
+#define EADC_STATUS2_ADCMPF2_Msk         (0x1ul << EADC_STATUS2_ADCMPF2_Pos)               /*!< EADC_T::STATUS2: ADCMPF2 Mask          */
+
+#define EADC_STATUS2_ADCMPF3_Pos         (7)                                               /*!< EADC_T::STATUS2: ADCMPF3 Position      */
+#define EADC_STATUS2_ADCMPF3_Msk         (0x1ul << EADC_STATUS2_ADCMPF3_Pos)               /*!< EADC_T::STATUS2: ADCMPF3 Mask          */
+
+#define EADC_STATUS2_ADOVIF0_Pos         (8)                                               /*!< EADC_T::STATUS2: ADOVIF0 Position      */
+#define EADC_STATUS2_ADOVIF0_Msk         (0x1ul << EADC_STATUS2_ADOVIF0_Pos)               /*!< EADC_T::STATUS2: ADOVIF0 Mask          */
+
+#define EADC_STATUS2_ADOVIF1_Pos         (9)                                               /*!< EADC_T::STATUS2: ADOVIF1 Position      */
+#define EADC_STATUS2_ADOVIF1_Msk         (0x1ul << EADC_STATUS2_ADOVIF1_Pos)               /*!< EADC_T::STATUS2: ADOVIF1 Mask          */
+
+#define EADC_STATUS2_ADOVIF2_Pos         (10)                                              /*!< EADC_T::STATUS2: ADOVIF2 Position      */
+#define EADC_STATUS2_ADOVIF2_Msk         (0x1ul << EADC_STATUS2_ADOVIF2_Pos)               /*!< EADC_T::STATUS2: ADOVIF2 Mask          */
+
+#define EADC_STATUS2_ADOVIF3_Pos         (11)                                              /*!< EADC_T::STATUS2: ADOVIF3 Position      */
+#define EADC_STATUS2_ADOVIF3_Msk         (0x1ul << EADC_STATUS2_ADOVIF3_Pos)               /*!< EADC_T::STATUS2: ADOVIF3 Mask          */
+
+#define EADC_STATUS2_ADCMPO0_Pos         (12)                                              /*!< EADC_T::STATUS2: ADCMPO0 Position      */
+#define EADC_STATUS2_ADCMPO0_Msk         (0x1ul << EADC_STATUS2_ADCMPO0_Pos)               /*!< EADC_T::STATUS2: ADCMPO0 Mask          */
+
+#define EADC_STATUS2_ADCMPO1_Pos         (13)                                              /*!< EADC_T::STATUS2: ADCMPO1 Position      */
+#define EADC_STATUS2_ADCMPO1_Msk         (0x1ul << EADC_STATUS2_ADCMPO1_Pos)               /*!< EADC_T::STATUS2: ADCMPO1 Mask          */
+
+#define EADC_STATUS2_ADCMPO2_Pos         (14)                                              /*!< EADC_T::STATUS2: ADCMPO2 Position      */
+#define EADC_STATUS2_ADCMPO2_Msk         (0x1ul << EADC_STATUS2_ADCMPO2_Pos)               /*!< EADC_T::STATUS2: ADCMPO2 Mask          */
+
+#define EADC_STATUS2_ADCMPO3_Pos         (15)                                              /*!< EADC_T::STATUS2: ADCMPO3 Position      */
+#define EADC_STATUS2_ADCMPO3_Msk         (0x1ul << EADC_STATUS2_ADCMPO3_Pos)               /*!< EADC_T::STATUS2: ADCMPO3 Mask          */
+
+#define EADC_STATUS2_CHANNEL_Pos         (16)                                              /*!< EADC_T::STATUS2: CHANNEL Position      */
+#define EADC_STATUS2_CHANNEL_Msk         (0x1ful << EADC_STATUS2_CHANNEL_Pos)              /*!< EADC_T::STATUS2: CHANNEL Mask          */
+
+#define EADC_STATUS2_BUSY_Pos            (23)                                              /*!< EADC_T::STATUS2: BUSY Position         */
+#define EADC_STATUS2_BUSY_Msk            (0x1ul << EADC_STATUS2_BUSY_Pos)                  /*!< EADC_T::STATUS2: BUSY Mask             */
+
+#define EADC_STATUS2_ADOVIF_Pos          (24)                                              /*!< EADC_T::STATUS2: ADOVIF Position       */
+#define EADC_STATUS2_ADOVIF_Msk          (0x1ul << EADC_STATUS2_ADOVIF_Pos)                /*!< EADC_T::STATUS2: ADOVIF Mask           */
+
+#define EADC_STATUS2_STOVF_Pos           (25)                                              /*!< EADC_T::STATUS2: STOVF Position        */
+#define EADC_STATUS2_STOVF_Msk           (0x1ul << EADC_STATUS2_STOVF_Pos)                 /*!< EADC_T::STATUS2: STOVF Mask            */
+
+#define EADC_STATUS2_AVALID_Pos          (26)                                              /*!< EADC_T::STATUS2: AVALID Position       */
+#define EADC_STATUS2_AVALID_Msk          (0x1ul << EADC_STATUS2_AVALID_Pos)                /*!< EADC_T::STATUS2: AVALID Mask           */
+
+#define EADC_STATUS2_AOV_Pos             (27)                                              /*!< EADC_T::STATUS2: AOV Position          */
+#define EADC_STATUS2_AOV_Msk             (0x1ul << EADC_STATUS2_AOV_Pos)                   /*!< EADC_T::STATUS2: AOV Mask              */
+
+#define EADC_STATUS3_CURSPL_Pos          (0)                                               /*!< EADC_T::STATUS3: CURSPL Position       */
+#define EADC_STATUS3_CURSPL_Msk          (0x1ful << EADC_STATUS3_CURSPL_Pos)               /*!< EADC_T::STATUS3: CURSPL Mask           */
+
+#define EADC_DDAT0_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT0: RESULT Position         */
+#define EADC_DDAT0_RESULT_Msk            (0xfffful << EADC_DDAT0_RESULT_Pos)               /*!< EADC_T::DDAT0: RESULT Mask             */
+
+#define EADC_DDAT0_OV_Pos                (16)                                              /*!< EADC_T::DDAT0: OV Position             */
+#define EADC_DDAT0_OV_Msk                (0x1ul << EADC_DDAT0_OV_Pos)                      /*!< EADC_T::DDAT0: OV Mask                 */
+
+#define EADC_DDAT0_VALID_Pos             (17)                                              /*!< EADC_T::DDAT0: VALID Position          */
+#define EADC_DDAT0_VALID_Msk             (0x1ul << EADC_DDAT0_VALID_Pos)                   /*!< EADC_T::DDAT0: VALID Mask              */
+
+#define EADC_DDAT1_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT1: RESULT Position         */
+#define EADC_DDAT1_RESULT_Msk            (0xfffful << EADC_DDAT1_RESULT_Pos)               /*!< EADC_T::DDAT1: RESULT Mask             */
+
+#define EADC_DDAT1_OV_Pos                (16)                                              /*!< EADC_T::DDAT1: OV Position             */
+#define EADC_DDAT1_OV_Msk                (0x1ul << EADC_DDAT1_OV_Pos)                      /*!< EADC_T::DDAT1: OV Mask                 */
+
+#define EADC_DDAT1_VALID_Pos             (17)                                              /*!< EADC_T::DDAT1: VALID Position          */
+#define EADC_DDAT1_VALID_Msk             (0x1ul << EADC_DDAT1_VALID_Pos)                   /*!< EADC_T::DDAT1: VALID Mask              */
+
+#define EADC_DDAT2_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT2: RESULT Position         */
+#define EADC_DDAT2_RESULT_Msk            (0xfffful << EADC_DDAT2_RESULT_Pos)               /*!< EADC_T::DDAT2: RESULT Mask             */
+
+#define EADC_DDAT2_OV_Pos                (16)                                              /*!< EADC_T::DDAT2: OV Position             */
+#define EADC_DDAT2_OV_Msk                (0x1ul << EADC_DDAT2_OV_Pos)                      /*!< EADC_T::DDAT2: OV Mask                 */
+
+#define EADC_DDAT2_VALID_Pos             (17)                                              /*!< EADC_T::DDAT2: VALID Position          */
+#define EADC_DDAT2_VALID_Msk             (0x1ul << EADC_DDAT2_VALID_Pos)                   /*!< EADC_T::DDAT2: VALID Mask              */
+
+#define EADC_DDAT3_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT3: RESULT Position         */
+#define EADC_DDAT3_RESULT_Msk            (0xfffful << EADC_DDAT3_RESULT_Pos)               /*!< EADC_T::DDAT3: RESULT Mask             */
+
+#define EADC_DDAT3_OV_Pos                (16)                                              /*!< EADC_T::DDAT3: OV Position             */
+#define EADC_DDAT3_OV_Msk                (0x1ul << EADC_DDAT3_OV_Pos)                      /*!< EADC_T::DDAT3: OV Mask                 */
+
+#define EADC_DDAT3_VALID_Pos             (17)                                              /*!< EADC_T::DDAT3: VALID Position          */
+#define EADC_DDAT3_VALID_Msk             (0x1ul << EADC_DDAT3_VALID_Pos)                   /*!< EADC_T::DDAT3: VALID Mask              */
+
+#define EADC_PWRM_PWUPRDY_Pos            (0)                                               /*!< EADC_T::PWRM: PWUPRDY Position         */
+#define EADC_PWRM_PWUPRDY_Msk            (0x1ul << EADC_PWRM_PWUPRDY_Pos)                  /*!< EADC_T::PWRM: PWUPRDY Mask             */
+
+#define EADC_PWRM_PWUCALEN_Pos           (1)                                               /*!< EADC_T::PWRM: PWUCALEN Position        */
+#define EADC_PWRM_PWUCALEN_Msk           (0x1ul << EADC_PWRM_PWUCALEN_Pos)                 /*!< EADC_T::PWRM: PWUCALEN Mask            */
+
+#define EADC_PWRM_PWDMOD_Pos             (2)                                               /*!< EADC_T::PWRM: PWDMOD Position          */
+#define EADC_PWRM_PWDMOD_Msk             (0x3ul << EADC_PWRM_PWDMOD_Pos)                   /*!< EADC_T::PWRM: PWDMOD Mask              */
+
+#define EADC_PWRM_LDOSUT_Pos             (8)                                               /*!< EADC_T::PWRM: LDOSUT Position          */
+#define EADC_PWRM_LDOSUT_Msk             (0xffful << EADC_PWRM_LDOSUT_Pos)                 /*!< EADC_T::PWRM: LDOSUT Mask              */
+
+#define EADC_CALCTL_CALSTART_Pos         (1)                                               /*!< EADC_T::CALCTL: CALSTART Position      */
+#define EADC_CALCTL_CALSTART_Msk         (0x1ul << EADC_CALCTL_CALSTART_Pos)               /*!< EADC_T::CALCTL: CALSTART Mask          */
+
+#define EADC_CALCTL_CALDONE_Pos          (2)                                               /*!< EADC_T::CALCTL: CALDONE Position       */
+#define EADC_CALCTL_CALDONE_Msk          (0x1ul << EADC_CALCTL_CALDONE_Pos)                /*!< EADC_T::CALCTL: CALDONE Mask           */
+
+#define EADC_CALCTL_CALSEL_Pos           (3)                                               /*!< EADC_T::CALCTL: CALSEL Position        */
+#define EADC_CALCTL_CALSEL_Msk           (0x1ul << EADC_CALCTL_CALSEL_Pos)                 /*!< EADC_T::CALCTL: CALSEL Mask            */
+
+#define EADC_CALDWRD_CALWORD_Pos         (0)                                               /*!< EADC_T::CALDWRD: CALWORD Position      */
+#define EADC_CALDWRD_CALWORD_Msk         (0x7ful << EADC_CALDWRD_CALWORD_Pos)              /*!< EADC_T::CALDWRD: CALWORD Mask          */
+
+/**@}*/ /* EADC_CONST */
+/**@}*/ /* end of EADC register group */
+
+
+/*---------------------- Digital to Analog Converter -------------------------*/
+/**
+    @addtogroup DAC Digital to Analog Converter(DAC)
+    Memory Mapped Structure for DAC Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var DAC_T::CTL
+     * Offset: 0x00  DAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DACEN     |DAC Enable Bit
+     * |        |          |0 = DAC is Disabled.
+     * |        |          |1 = DAC is Enabled.
+     * |[1]     |DACIEN    |DAC Interrupt Enable Bit
+     * |        |          |0 = Interrupt is Disabled.
+     * |        |          |1 = Interrupt is Enabled.
+     * |[2]     |DMAEN     |DMA Mode Enable Bit
+     * |        |          |0 = DMA mode Disabled.
+     * |        |          |1 = DMA mode Enabled.
+     * |[3]     |DMAURIEN  |DMA Under-run Interrupt Enable Bit
+     * |        |          |0 = DMA under-run interrupt Disabled.
+     * |        |          |1 = DMA under-run interrupt Enabled.
+     * |[4]     |TRGEN     |Trigger Mode Enable Bit
+     * |        |          |0 = DAC event trigger mode Disabled.
+     * |        |          |1 = DAC event trigger mode Enabled.
+     * |[7:5]   |TRGSEL    |Trigger Source Selection
+     * |        |          |000 = Software trigger.
+     * |        |          |001 = External pin DAC0_ST trigger.
+     * |        |          |010 = Timer 0 trigger.
+     * |        |          |011 = Timer 1 trigger.
+     * |        |          |100 = Timer 2 trigger.
+     * |        |          |101 = Timer 3 trigger.
+     * |        |          |110 = EPWM0 trigger.
+     * |        |          |111 = EPWM1 trigger.
+     * |[8]     |BYPASS    |Bypass Buffer Mode
+     * |        |          |0 = Output voltage buffer Enabled.
+     * |        |          |1 = Output voltage buffer Disabled.
+     * |[10]    |LALIGN    |DAC Data Left-aligned Enabled Control
+     * |        |          |0 = Right alignment.
+     * |        |          |1 = Left alignment.
+     * |[13:12] |ETRGSEL   |External Pin Trigger Selection
+     * |        |          |00 = Low level trigger.
+     * |        |          |01 = High level trigger.
+     * |        |          |10 = Falling edge trigger.
+     * |        |          |11 = Rising edge trigger.
+     * |[15:14] |BWSEL     |DAC Data Bit-width Selection
+     * |        |          |00 = data is 12 bits.
+     * |        |          |01 = data is 8 bits.
+     * |        |          |Others = reserved.
+     * |[16]    |GRPEN     |DAC Group Mode Enable Bit
+     * |        |          |0 = DAC0 and DAC1 are not grouped.
+     * |        |          |1 = DAC0 and DAC1 are grouped.
+     * @var DAC_T::SWTRG
+     * Offset: 0x04  DAC Software Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SWTRG     |Software Trigger
+     * |        |          |0 = Software trigger Disabled.
+     * |        |          |1 = Software trigger Enabled.
+     * |        |          |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+     * @var DAC_T::DAT
+     * Offset: 0x08  DAC Data Holding Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DACDAT    |DAC 12-bit Holding Data
+     * |        |          |These bits are written by user software which specifies 12-bit conversion data for DAC output
+     * |        |          |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+     * |        |          |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+     * |        |          |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+     * @var DAC_T::DATOUT
+     * Offset: 0x0C  DAC Data Output Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DATOUT    |DAC 12-bit Output Data
+     * |        |          |These bits are current digital data for DAC output conversion.
+     * |        |          |It is loaded from DAC_DAT register and user cannot write it directly.
+     * @var DAC_T::STATUS
+     * Offset: 0x10  DAC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FINISH    |DAC Conversion Complete Finish Flag
+     * |        |          |0 = DAC is in conversion state.
+     * |        |          |1 = DAC conversion finish.
+     * |        |          |This bit set to 1 when conversion time counter counts to SETTLET
+     * |        |          |It is cleared to 0 when DAC starts a new conversion
+     * |        |          |User writes 1 to clear this bit to 0.
+     * |[1]     |DMAUDR    |DMA Under-run Interrupt Flag
+     * |        |          |0 = No DMA under-run error condition occurred.
+     * |        |          |1 = DMA under-run error condition occurred.
+     * |        |          |User writes 1 to clear this bit.
+     * |[8]     |BUSY      |DAC Busy Flag (Read Only)
+     * |        |          |0 = DAC is ready for next conversion.
+     * |        |          |1 = DAC is busy in conversion.
+     * |        |          |This is read only bit.
+     * @var DAC_T::TCTL
+     * Offset: 0x14  DAC Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |SETTLET   |DAC Output Settling Time
+     * |        |          |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+     * |        |          |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
+     * |        |          |SELTTLET = DAC controller clock speed x settling time.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] DAC Control Register                                             */
+    __IO uint32_t SWTRG;                 /*!< [0x0004] DAC Software Trigger Control Register                            */
+    __IO uint32_t DAT;                   /*!< [0x0008] DAC Data Holding Register                                        */
+    __I  uint32_t DATOUT;                /*!< [0x000c] DAC Data Output Register                                         */
+    __IO uint32_t STATUS;                /*!< [0x0010] DAC Status Register                                              */
+    __IO uint32_t TCTL;                  /*!< [0x0014] DAC Timing Control Register                                      */
+
+} DAC_T;
+
+/**
+    @addtogroup DAC_CONST DAC Bit Field Definition
+    Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos                (0)                                               /*!< DAC_T::CTL: DACEN Position             */
+#define DAC_CTL_DACEN_Msk                (0x1ul << DAC_CTL_DACEN_Pos)                      /*!< DAC_T::CTL: DACEN Mask                 */
+
+#define DAC_CTL_DACIEN_Pos               (1)                                               /*!< DAC_T::CTL: DACIEN Position            */
+#define DAC_CTL_DACIEN_Msk               (0x1ul << DAC_CTL_DACIEN_Pos)                     /*!< DAC_T::CTL: DACIEN Mask                */
+
+#define DAC_CTL_DMAEN_Pos                (2)                                               /*!< DAC_T::CTL: DMAEN Position             */
+#define DAC_CTL_DMAEN_Msk                (0x1ul << DAC_CTL_DMAEN_Pos)                      /*!< DAC_T::CTL: DMAEN Mask                 */
+
+#define DAC_CTL_DMAURIEN_Pos             (3)                                               /*!< DAC_T::CTL: DMAURIEN Position          */
+#define DAC_CTL_DMAURIEN_Msk             (0x1ul << DAC_CTL_DMAURIEN_Pos)                   /*!< DAC_T::CTL: DMAURIEN Mask              */
+
+#define DAC_CTL_TRGEN_Pos                (4)                                               /*!< DAC_T::CTL: TRGEN Position             */
+#define DAC_CTL_TRGEN_Msk                (0x1ul << DAC_CTL_TRGEN_Pos)                      /*!< DAC_T::CTL: TRGEN Mask                 */
+
+#define DAC_CTL_TRGSEL_Pos               (5)                                               /*!< DAC_T::CTL: TRGSEL Position            */
+#define DAC_CTL_TRGSEL_Msk               (0x7ul << DAC_CTL_TRGSEL_Pos)                     /*!< DAC_T::CTL: TRGSEL Mask                */
+
+#define DAC_CTL_BYPASS_Pos               (8)                                               /*!< DAC_T::CTL: BYPASS Position            */
+#define DAC_CTL_BYPASS_Msk               (0x1ul << DAC_CTL_BYPASS_Pos)                     /*!< DAC_T::CTL: BYPASS Mask                */
+
+#define DAC_CTL_LALIGN_Pos               (10)                                              /*!< DAC_T::CTL: LALIGN Position            */
+#define DAC_CTL_LALIGN_Msk               (0x1ul << DAC_CTL_LALIGN_Pos)                     /*!< DAC_T::CTL: LALIGN Mask                */
+
+#define DAC_CTL_ETRGSEL_Pos              (12)                                              /*!< DAC_T::CTL: ETRGSEL Position           */
+#define DAC_CTL_ETRGSEL_Msk              (0x3ul << DAC_CTL_ETRGSEL_Pos)                    /*!< DAC_T::CTL: ETRGSEL Mask               */
+
+#define DAC_CTL_BWSEL_Pos                (14)                                              /*!< DAC_T::CTL: BWSEL Position             */
+#define DAC_CTL_BWSEL_Msk                (0x3ul << DAC_CTL_BWSEL_Pos)                      /*!< DAC_T::CTL: BWSEL Mask                 */
+
+#define DAC_CTL_GRPEN_Pos                (16)                                              /*!< DAC_T::CTL: GRPEN Position             */
+#define DAC_CTL_GRPEN_Msk                (0x1ul << DAC_CTL_GRPEN_Pos)                      /*!< DAC_T::CTL: GRPEN Mask                 */
+
+#define DAC_SWTRG_SWTRG_Pos              (0)                                               /*!< DAC_T::SWTRG: SWTRG Position           */
+#define DAC_SWTRG_SWTRG_Msk              (0x1ul << DAC_SWTRG_SWTRG_Pos)                    /*!< DAC_T::SWTRG: SWTRG Mask               */
+
+#define DAC_DAT_DACDAT_Pos               (0)                                               /*!< DAC_T::DAT: DACDAT Position            */
+#define DAC_DAT_DACDAT_Msk               (0xfffful << DAC_DAT_DACDAT_Pos)                  /*!< DAC_T::DAT: DACDAT Mask                */
+
+#define DAC_DATOUT_DATOUT_Pos            (0)                                               /*!< DAC_T::DATOUT: DATOUT Position         */
+#define DAC_DATOUT_DATOUT_Msk            (0xffful << DAC_DATOUT_DATOUT_Pos)                /*!< DAC_T::DATOUT: DATOUT Mask             */
+
+#define DAC_STATUS_FINISH_Pos            (0)                                               /*!< DAC_T::STATUS: FINISH Position         */
+#define DAC_STATUS_FINISH_Msk            (0x1ul << DAC_STATUS_FINISH_Pos)                  /*!< DAC_T::STATUS: FINISH Mask             */
+
+#define DAC_STATUS_DMAUDR_Pos            (1)                                               /*!< DAC_T::STATUS: DMAUDR Position         */
+#define DAC_STATUS_DMAUDR_Msk            (0x1ul << DAC_STATUS_DMAUDR_Pos)                  /*!< DAC_T::STATUS: DMAUDR Mask             */
+
+#define DAC_STATUS_BUSY_Pos              (8)                                               /*!< DAC_T::STATUS: BUSY Position           */
+#define DAC_STATUS_BUSY_Msk              (0x1ul << DAC_STATUS_BUSY_Pos)                    /*!< DAC_T::STATUS: BUSY Mask               */
+
+#define DAC_TCTL_SETTLET_Pos             (0)                                               /*!< DAC_T::TCTL: SETTLET Position          */
+#define DAC_TCTL_SETTLET_Msk             (0x3fful << DAC_TCTL_SETTLET_Pos)                 /*!< DAC_T::TCTL: SETTLET Mask              */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+
+
+/*---------------------- Analog Comparator Controller -------------------------*/
+/**
+    @addtogroup ACMP Analog Comparator Controller(ACMP)
+    Memory Mapped Structure for ACMP Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var ACMP_T::CTL
+     * Offset: 0x00~0x04  Analog Comparator 0/1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPEN    |Comparator Enable Bit
+     * |        |          |0 = Comparator x Disabled.
+     * |        |          |1 = Comparator x Enabled.
+     * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+     * |        |          |0 = Comparator x interrupt Disabled.
+     * |        |          |1 = Comparator x interrupt Enabled
+     * |        |          |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+     * |[3]     |ACMPOINV  |Comparator Output Inverse
+     * |        |          |0 = Comparator x output inverse Disabled.
+     * |        |          |1 = Comparator x output inverse Enabled.
+     * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+     * |        |          |00 = ACMPx_N pin.
+     * |        |          |01 = Internal comparator reference voltage (CRV).
+     * |        |          |10 = Band-gap voltage.
+     * |        |          |11 = DAC output.
+     * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+     * |        |          |00 = Input from ACMPx_P0.
+     * |        |          |01 = Input from ACMPx_P1.
+     * |        |          |10 = Input from ACMPx_P2.
+     * |        |          |11 = Input from ACMPx_P3.
+     * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+     * |        |          |ACMPIFx will be set to 1 when comparator output edge condition is detected.
+     * |        |          |00 = Rising edge or falling edge.
+     * |        |          |01 = Rising edge.
+     * |        |          |10 = Falling edge.
+     * |        |          |11 = Reserved.
+     * |[12]    |OUTSEL    |Comparator Output Select
+     * |        |          |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
+     * |        |          |1 = Comparator x output to ACMPx_O pin is from filter output.
+     * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+     * |        |          |000 = Filter function is Disabled.
+     * |        |          |001 = ACMPx output is sampled 1 consecutive PCLK.
+     * |        |          |010 = ACMPx output is sampled 2 consecutive PCLKs.
+     * |        |          |011 = ACMPx output is sampled 4 consecutive PCLKs.
+     * |        |          |100 = ACMPx output is sampled 8 consecutive PCLKs.
+     * |        |          |101 = ACMPx output is sampled 16 consecutive PCLKs.
+     * |        |          |110 = ACMPx output is sampled 32 consecutive PCLKs.
+     * |        |          |111 = ACMPx output is sampled 64 consecutive PCLKs.
+     * |[16]    |WKEN      |Power-down Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[17]    |WLATEN    |Window Latch Mode Enable Bit
+     * |        |          |0 = Window Latch Mode Disabled.
+     * |        |          |1 = Window Latch Mode Enabled.
+     * |[18]    |WCMPSEL   |Window Compare Mode Selection
+     * |        |          |0 = Window Compare Mode Disabled.
+     * |        |          |1 = Window Compare Mode is Selected.
+     * |[25:24] |HYSSEL    |Hysteresis Mode Selection
+     * |        |          |00 = Hysteresis is 0mV.
+     * |        |          |01 = Hysteresis is 10mV.
+     * |        |          |10 = Hysteresis is 20mV.
+     * |        |          |11 = Hysteresis is 30mV.
+     * |[29:28] |MODESEL   |Propagation Delay Mode Selection
+     * |        |          |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
+     * |        |          |01 = Max propagation delay is 2uS, operation current is 3uA.
+     * |        |          |10 = Max propagation delay is 600nS, operation current is 10uA.
+     * |        |          |11 = Max propagation delay is 200nS, operation current is 75uA.
+     * @var ACMP_T::STATUS
+     * Offset: 0x08  Analog Comparator Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPIF0   |Comparator 0 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8])
+     * |        |          |is detected on comparator 0 output.
+     * |        |          |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |ACMPIF1   |Comparator 1 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8])
+     * |        |          |is detected on comparator 1 output.
+     * |        |          |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |ACMPO0    |Comparator 0 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[5]     |ACMPO1    |Comparator 1 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software.
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[8]     |WKIF0     |Comparator 0 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |WKIF1     |Comparator 1 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |ACMPS0    |Comparator 0 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[13]    |ACMPS1    |Comparator 1 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[16]    |ACMPWO    |Comparator Window Output
+     * |        |          |This bit shows the output status of window compare mode
+     * |        |          |0 = The positive input voltage is outside the window.
+     * |        |          |1 = The positive input voltage is in the window.
+     * @var ACMP_T::VREF
+     * Offset: 0x0C  Analog Comparator Reference Voltage Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CRVCTL    |Comparator Reference Voltage Setting
+     * |        |          |CRV = CRV source voltage * (1/6+CRVCTL/24).
+     * |[6]     |CRVSSEL   |CRV Source Voltage Selection
+     * |        |          |0 = VDDA is selected as CRV source voltage.
+     * |        |          |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+     */
+    __IO uint32_t CTL[2];                /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register                    */
+    __IO uint32_t STATUS;                /*!< [0x0008] Analog Comparator Status Register                                */
+    __IO uint32_t VREF;                  /*!< [0x000c] Analog Comparator Reference Voltage Control Register             */
+
+} ACMP_T;
+
+/**
+    @addtogroup ACMP_CONST ACMP Bit Field Definition
+    Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos              (0)                                               /*!< ACMP_T::CTL: ACMPEN Position           */
+#define ACMP_CTL_ACMPEN_Msk              (0x1ul << ACMP_CTL_ACMPEN_Pos)                    /*!< ACMP_T::CTL: ACMPEN Mask               */
+
+#define ACMP_CTL_ACMPIE_Pos              (1)                                               /*!< ACMP_T::CTL: ACMPIE Position           */
+#define ACMP_CTL_ACMPIE_Msk              (0x1ul << ACMP_CTL_ACMPIE_Pos)                    /*!< ACMP_T::CTL: ACMPIE Mask               */
+
+#define ACMP_CTL_ACMPOINV_Pos            (3)                                               /*!< ACMP_T::CTL: ACMPOINV Position         */
+#define ACMP_CTL_ACMPOINV_Msk            (0x1ul << ACMP_CTL_ACMPOINV_Pos)                  /*!< ACMP_T::CTL: ACMPOINV Mask             */
+
+#define ACMP_CTL_NEGSEL_Pos              (4)                                               /*!< ACMP_T::CTL: NEGSEL Position           */
+#define ACMP_CTL_NEGSEL_Msk              (0x3ul << ACMP_CTL_NEGSEL_Pos)                    /*!< ACMP_T::CTL: NEGSEL Mask               */
+
+#define ACMP_CTL_POSSEL_Pos              (6)                                               /*!< ACMP_T::CTL: POSSEL Position           */
+#define ACMP_CTL_POSSEL_Msk              (0x3ul << ACMP_CTL_POSSEL_Pos)                    /*!< ACMP_T::CTL: POSSEL Mask               */
+
+#define ACMP_CTL_INTPOL_Pos              (8)                                               /*!< ACMP_T::CTL: INTPOL Position           */
+#define ACMP_CTL_INTPOL_Msk              (0x3ul << ACMP_CTL_INTPOL_Pos)                    /*!< ACMP_T::CTL: INTPOL Mask               */
+
+#define ACMP_CTL_OUTSEL_Pos              (12)                                              /*!< ACMP_T::CTL: OUTSEL Position           */
+#define ACMP_CTL_OUTSEL_Msk              (0x1ul << ACMP_CTL_OUTSEL_Pos)                    /*!< ACMP_T::CTL: OUTSEL Mask               */
+
+#define ACMP_CTL_FILTSEL_Pos             (13)                                              /*!< ACMP_T::CTL: FILTSEL Position          */
+#define ACMP_CTL_FILTSEL_Msk             (0x7ul << ACMP_CTL_FILTSEL_Pos)                   /*!< ACMP_T::CTL: FILTSEL Mask              */
+
+#define ACMP_CTL_WKEN_Pos                (16)                                              /*!< ACMP_T::CTL: WKEN Position             */
+#define ACMP_CTL_WKEN_Msk                (0x1ul << ACMP_CTL_WKEN_Pos)                      /*!< ACMP_T::CTL: WKEN Mask                 */
+
+#define ACMP_CTL_WLATEN_Pos              (17)                                              /*!< ACMP_T::CTL: WLATEN Position           */
+#define ACMP_CTL_WLATEN_Msk              (0x1ul << ACMP_CTL_WLATEN_Pos)                    /*!< ACMP_T::CTL: WLATEN Mask               */
+
+#define ACMP_CTL_WCMPSEL_Pos             (18)                                              /*!< ACMP_T::CTL: WCMPSEL Position          */
+#define ACMP_CTL_WCMPSEL_Msk             (0x1ul << ACMP_CTL_WCMPSEL_Pos)                   /*!< ACMP_T::CTL: WCMPSEL Mask              */
+
+#define ACMP_CTL_HYSSEL_Pos              (24)                                              /*!< ACMP_T::CTL: HYSSEL Position           */
+#define ACMP_CTL_HYSSEL_Msk              (0x3ul << ACMP_CTL_HYSSEL_Pos)                    /*!< ACMP_T::CTL: HYSSEL Mask               */
+
+#define ACMP_CTL_MODESEL_Pos             (28)                                              /*!< ACMP_T::CTL: MODESEL Position          */
+#define ACMP_CTL_MODESEL_Msk             (0x3ul << ACMP_CTL_MODESEL_Pos)                   /*!< ACMP_T::CTL: MODESEL Mask              */
+
+#define ACMP_STATUS_ACMPIF0_Pos          (0)                                               /*!< ACMP_T::STATUS: ACMPIF0 Position       */
+#define ACMP_STATUS_ACMPIF0_Msk          (0x1ul << ACMP_STATUS_ACMPIF0_Pos)                /*!< ACMP_T::STATUS: ACMPIF0 Mask           */
+
+#define ACMP_STATUS_ACMPIF1_Pos          (1)                                               /*!< ACMP_T::STATUS: ACMPIF1 Position       */
+#define ACMP_STATUS_ACMPIF1_Msk          (0x1ul << ACMP_STATUS_ACMPIF1_Pos)                /*!< ACMP_T::STATUS: ACMPIF1 Mask           */
+
+#define ACMP_STATUS_ACMPO0_Pos           (4)                                               /*!< ACMP_T::STATUS: ACMPO0 Position        */
+#define ACMP_STATUS_ACMPO0_Msk           (0x1ul << ACMP_STATUS_ACMPO0_Pos)                 /*!< ACMP_T::STATUS: ACMPO0 Mask            */
+
+#define ACMP_STATUS_ACMPO1_Pos           (5)                                               /*!< ACMP_T::STATUS: ACMPO1 Position        */
+#define ACMP_STATUS_ACMPO1_Msk           (0x1ul << ACMP_STATUS_ACMPO1_Pos)                 /*!< ACMP_T::STATUS: ACMPO1 Mask            */
+
+#define ACMP_STATUS_WKIF0_Pos            (8)                                               /*!< ACMP_T::STATUS: WKIF0 Position         */
+#define ACMP_STATUS_WKIF0_Msk            (0x1ul << ACMP_STATUS_WKIF0_Pos)                  /*!< ACMP_T::STATUS: WKIF0 Mask             */
+
+#define ACMP_STATUS_WKIF1_Pos            (9)                                               /*!< ACMP_T::STATUS: WKIF1 Position         */
+#define ACMP_STATUS_WKIF1_Msk            (0x1ul << ACMP_STATUS_WKIF1_Pos)                  /*!< ACMP_T::STATUS: WKIF1 Mask             */
+
+#define ACMP_STATUS_ACMPS0_Pos           (12)                                              /*!< ACMP_T::STATUS: ACMPS0 Position        */
+#define ACMP_STATUS_ACMPS0_Msk           (0x1ul << ACMP_STATUS_ACMPS0_Pos)                 /*!< ACMP_T::STATUS: ACMPS0 Mask            */
+
+#define ACMP_STATUS_ACMPS1_Pos           (13)                                              /*!< ACMP_T::STATUS: ACMPS1 Position        */
+#define ACMP_STATUS_ACMPS1_Msk           (0x1ul << ACMP_STATUS_ACMPS1_Pos)                 /*!< ACMP_T::STATUS: ACMPS1 Mask            */
+
+#define ACMP_STATUS_ACMPWO_Pos           (16)                                              /*!< ACMP_T::STATUS: ACMPWO Position        */
+#define ACMP_STATUS_ACMPWO_Msk           (0x1ul << ACMP_STATUS_ACMPWO_Pos)                 /*!< ACMP_T::STATUS: ACMPWO Mask            */
+
+#define ACMP_VREF_CRVCTL_Pos             (0)                                               /*!< ACMP_T::VREF: CRVCTL Position          */
+#define ACMP_VREF_CRVCTL_Msk             (0xful << ACMP_VREF_CRVCTL_Pos)                   /*!< ACMP_T::VREF: CRVCTL Mask              */
+
+#define ACMP_VREF_CRVSSEL_Pos            (6)                                               /*!< ACMP_T::VREF: CRVSSEL Position         */
+#define ACMP_VREF_CRVSSEL_Msk            (0x1ul << ACMP_VREF_CRVSSEL_Pos)                  /*!< ACMP_T::VREF: CRVSSEL Mask             */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+
+
+/*---------------------- OP Amplifier -------------------------*/
+/**
+    @addtogroup OPA OP Amplifier(OPA)
+    Memory Mapped Structure for OPA Controller
+@{ */
+
+typedef struct {
+
+
+    /**
+     * @var OPA_T::CTL
+     * Offset: 0x00  OP Amplifier Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OPEN0     |OP Amplifier 0 Enable Bit
+     * |        |          |0 = OP amplifier0 Disabled.
+     * |        |          |1 = OP amplifier0 Enabled.
+     * |        |          |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set.
+     * |[1]     |OPEN1     |OP Amplifier 1 Enable Bit
+     * |        |          |0 = OP amplifier1 Disabled.
+     * |        |          |1 = OP amplifier1 Enabled.
+     * |        |          |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set.
+     * |[2]     |OPEN2     |OP Amplifier 2 Enable Bit
+     * |        |          |0 = OP amplifier2 Disabled.
+     * |        |          |1 = OP amplifier2 Enabled.
+     * |        |          |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set.
+     * |[4]     |OPDOEN0   |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
+     * |        |          |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled.
+     * |        |          |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled.
+     * |[5]     |OPDOEN1   |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit
+     * |        |          |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled.
+     * |        |          |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled.
+     * |[6]     |OPDOEN2   |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit
+     * |        |          |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled.
+     * |        |          |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled.
+     * |[8]     |OPDOIEN0  |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit
+     * |        |          |0 = OP Amplifier 0 digital output interrupt function Disabled.
+     * |        |          |1 = OP Amplifier 0 digital output interrupt function Enabled.
+     * |        |          |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
+     * |[9]     |OPDOIEN1  |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit
+     * |        |          |0 = OP Amplifier 1 digital output interrupt function Disabled.
+     * |        |          |1 = OP Amplifier 1 digital output interrupt function Enabled.
+     * |        |          |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated.
+     * |[10]    |OPDOIEN2  |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit
+     * |        |          |0 = OP Amplifier 2 digital output interrupt function Disabled.
+     * |        |          |1 = OP Amplifier 2 digital output interrupt function Enabled.
+     * |        |          |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated.
+     * @var OPA_T::STATUS
+     * Offset: 0x04  OP Amplifier Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OPDO0     |OP Amplifier 0 Digital Output
+     * |        |          |Synchronized to the APB clock to allow reading by software
+     * |        |          |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0)
+     * |[1]     |OPDO1     |OP Amplifier 1 Digital Output
+     * |        |          |Synchronized to the APB clock to allow reading by software
+     * |        |          |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0)
+     * |[2]     |OPDO2     |OP Amplifier 2 Digital Output
+     * |        |          |Synchronized to the APB clock to allow reading by software
+     * |        |          |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0)
+     * |[4]     |OPDOIF0   |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
+     * |        |          |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state
+     * |        |          |This bit is cleared by writing 1 to it.
+     * |[5]     |OPDOIF1   |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
+     * |        |          |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state
+     * |        |          |This bit is cleared by writing 1 to it.
+     * |[6]     |OPDOIF2   |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag
+     * |        |          |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state
+     * |        |          |This bit is cleared by writing 1 to it.
+     * @var OPA_T::CALCTL
+     * Offset: 0x08  OP Amplifier Calibration Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CALTRG0   |OP Amplifier 0 Calibration Trigger Bit
+     * |        |          |0 = Stop, hardware auto clear.
+     * |        |          |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance.
+     * |[1]     |CALTRG1   |OP Amplifier 1 Calibration Trigger Bit
+     * |        |          |0 = Stop, hardware auto clear.
+     * |        |          |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance.
+     * |[2]     |CALTRG2   |OP Amplifier 2 Calibration Trigger Bit
+     * |        |          |0 = Stop, hardware auto clear.
+     * |        |          |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance.
+     * |[16]    |CALRVS0   |OPA0 Calibration Reference Voltage Selection
+     * |        |          |0 = VREF is AVDD.
+     * |        |          |1 = VREF from high vcm to low vcm.
+     * |[17]    |CALRVS1   |OPA1 Calibration Reference Voltage Selection
+     * |        |          |0 = VREF is AVDD.
+     * |        |          |1 = VREF from high vcm to low vcm.
+     * |[18]    |CALRVS2   |OPA2 Calibration Reference Voltage Selection
+     * |        |          |0 = VREF is AVDD.
+     * |        |          |1 = VREF from high vcm to low vcm.
+     * @var OPA_T::CALST
+     * Offset: 0x0C  OP Amplifier Calibration Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DONE0     |OP Amplifier 0 Calibration Done Status
+     * |        |          |0 = Calibrating.
+     * |        |          |1 = Calibration Done.
+     * |[1]     |CALNS0    |OP Amplifier 0 Calibration Result Status for NMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     * |[2]     |CALPS0    |OP Amplifier 0 Calibration Result Status for PMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     * |[4]     |DONE1     |OP Amplifier 1 Calibration Done Status
+     * |        |          |0 = Calibrating.
+     * |        |          |1 = Calibration Done.
+     * |[5]     |CALNS1    |OP Amplifier 1 Calibration Result Status for NMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     * |[6]     |CALPS1    |OP Amplifier 1 Calibration Result Status for PMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     * |[8]     |DONE2     |OP Amplifier 2 Calibration Done Status
+     * |        |          |0 = Calibrating.
+     * |        |          |1 = Calibration Done.
+     * |[9]     |CALNS2    |OP Amplifier 2 Calibration Result Status for NMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     * |[10]    |CALPS2    |OP Amplifier 2 Calibration Result Status for PMOS
+     * |        |          |0 = Pass.
+     * |        |          |1 = Fail.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] OP Amplifier Control Register                                    */
+    __IO uint32_t STATUS;                /*!< [0x0004] OP Amplifier Status Register                                     */
+    __IO uint32_t CALCTL;                /*!< [0x0008] OP Amplifier Calibration Control Register                        */
+    __I  uint32_t CALST;                 /*!< [0x000c] OP Amplifier Calibration Status Register                         */
+
+} OPA_T;
+
+/**
+    @addtogroup OPA_CONST OPA Bit Field Definition
+    Constant Definitions for OPA Controller
+@{ */
+
+#define OPA_CTL_OPEN0_Pos                (0)                                               /*!< OPA_T::CTL: OPEN0 Position             */
+#define OPA_CTL_OPEN0_Msk                (0x1ul << OPA_CTL_OPEN0_Pos)                      /*!< OPA_T::CTL: OPEN0 Mask                 */
+
+#define OPA_CTL_OPEN1_Pos                (1)                                               /*!< OPA_T::CTL: OPEN1 Position             */
+#define OPA_CTL_OPEN1_Msk                (0x1ul << OPA_CTL_OPEN1_Pos)                      /*!< OPA_T::CTL: OPEN1 Mask                 */
+
+#define OPA_CTL_OPEN2_Pos                (2)                                               /*!< OPA_T::CTL: OPEN2 Position             */
+#define OPA_CTL_OPEN2_Msk                (0x1ul << OPA_CTL_OPEN2_Pos)                      /*!< OPA_T::CTL: OPEN2 Mask                 */
+
+#define OPA_CTL_OPDOEN0_Pos              (4)                                               /*!< OPA_T::CTL: OPDOEN0 Position           */
+#define OPA_CTL_OPDOEN0_Msk              (0x1ul << OPA_CTL_OPDOEN0_Pos)                    /*!< OPA_T::CTL: OPDOEN0 Mask               */
+
+#define OPA_CTL_OPDOEN1_Pos              (5)                                               /*!< OPA_T::CTL: OPDOEN1 Position           */
+#define OPA_CTL_OPDOEN1_Msk              (0x1ul << OPA_CTL_OPDOEN1_Pos)                    /*!< OPA_T::CTL: OPDOEN1 Mask               */
+
+#define OPA_CTL_OPDOEN2_Pos              (6)                                               /*!< OPA_T::CTL: OPDOEN2 Position           */
+#define OPA_CTL_OPDOEN2_Msk              (0x1ul << OPA_CTL_OPDOEN2_Pos)                    /*!< OPA_T::CTL: OPDOEN2 Mask               */
+
+#define OPA_CTL_OPDOIEN0_Pos             (8)                                               /*!< OPA_T::CTL: OPDOIEN0 Position          */
+#define OPA_CTL_OPDOIEN0_Msk             (0x1ul << OPA_CTL_OPDOIEN0_Pos)                   /*!< OPA_T::CTL: OPDOIEN0 Mask              */
+
+#define OPA_CTL_OPDOIEN1_Pos             (9)                                               /*!< OPA_T::CTL: OPDOIEN1 Position          */
+#define OPA_CTL_OPDOIEN1_Msk             (0x1ul << OPA_CTL_OPDOIEN1_Pos)                   /*!< OPA_T::CTL: OPDOIEN1 Mask              */
+
+#define OPA_CTL_OPDOIEN2_Pos             (10)                                              /*!< OPA_T::CTL: OPDOIEN2 Position          */
+#define OPA_CTL_OPDOIEN2_Msk             (0x1ul << OPA_CTL_OPDOIEN2_Pos)                   /*!< OPA_T::CTL: OPDOIEN2 Mask              */
+
+#define OPA_STATUS_OPDO0_Pos             (0)                                               /*!< OPA_T::STATUS: OPDO0 Position          */
+#define OPA_STATUS_OPDO0_Msk             (0x1ul << OPA_STATUS_OPDO0_Pos)                   /*!< OPA_T::STATUS: OPDO0 Mask              */
+
+#define OPA_STATUS_OPDO1_Pos             (1)                                               /*!< OPA_T::STATUS: OPDO1 Position          */
+#define OPA_STATUS_OPDO1_Msk             (0x1ul << OPA_STATUS_OPDO1_Pos)                   /*!< OPA_T::STATUS: OPDO1 Mask              */
+
+#define OPA_STATUS_OPDO2_Pos             (2)                                               /*!< OPA_T::STATUS: OPDO2 Position          */
+#define OPA_STATUS_OPDO2_Msk             (0x1ul << OPA_STATUS_OPDO2_Pos)                   /*!< OPA_T::STATUS: OPDO2 Mask              */
+
+#define OPA_STATUS_OPDOIF0_Pos           (4)                                               /*!< OPA_T::STATUS: OPDOIF0 Position        */
+#define OPA_STATUS_OPDOIF0_Msk           (0x1ul << OPA_STATUS_OPDOIF0_Pos)                 /*!< OPA_T::STATUS: OPDOIF0 Mask            */
+
+#define OPA_STATUS_OPDOIF1_Pos           (5)                                               /*!< OPA_T::STATUS: OPDOIF1 Position        */
+#define OPA_STATUS_OPDOIF1_Msk           (0x1ul << OPA_STATUS_OPDOIF1_Pos)                 /*!< OPA_T::STATUS: OPDOIF1 Mask            */
+
+#define OPA_STATUS_OPDOIF2_Pos           (6)                                               /*!< OPA_T::STATUS: OPDOIF2 Position        */
+#define OPA_STATUS_OPDOIF2_Msk           (0x1ul << OPA_STATUS_OPDOIF2_Pos)                 /*!< OPA_T::STATUS: OPDOIF2 Mask            */
+
+#define OPA_CALCTL_CALTRG0_Pos           (0)                                               /*!< OPA_T::CALCTL: CALTRG0 Position        */
+#define OPA_CALCTL_CALTRG0_Msk           (0x1ul << OPA_CALCTL_CALTRG0_Pos)                 /*!< OPA_T::CALCTL: CALTRG0 Mask            */
+
+#define OPA_CALCTL_CALTRG1_Pos           (1)                                               /*!< OPA_T::CALCTL: CALTRG1 Position        */
+#define OPA_CALCTL_CALTRG1_Msk           (0x1ul << OPA_CALCTL_CALTRG1_Pos)                 /*!< OPA_T::CALCTL: CALTRG1 Mask            */
+
+#define OPA_CALCTL_CALTRG2_Pos           (2)                                               /*!< OPA_T::CALCTL: CALTRG2 Position        */
+#define OPA_CALCTL_CALTRG2_Msk           (0x1ul << OPA_CALCTL_CALTRG2_Pos)                 /*!< OPA_T::CALCTL: CALTRG2 Mask            */
+
+#define OPA_CALCTL_CALCLK0_Pos           (4)                                               /*!< OPA_T::CALCTL: CALCLK0 Position        */
+#define OPA_CALCTL_CALCLK0_Msk           (0x3ul << OPA_CALCTL_CALCLK0_Pos)                 /*!< OPA_T::CALCTL: CALCLK0 Mask            */
+
+#define OPA_CALCTL_CALCLK1_Pos           (6)                                               /*!< OPA_T::CALCTL: CALCLK1 Position        */
+#define OPA_CALCTL_CALCLK1_Msk           (0x3ul << OPA_CALCTL_CALCLK1_Pos)                 /*!< OPA_T::CALCTL: CALCLK1 Mask            */
+
+#define OPA_CALCTL_CALCLK2_Pos           (8)                                               /*!< OPA_T::CALCTL: CALCLK2 Position        */
+#define OPA_CALCTL_CALCLK2_Msk           (0x3ul << OPA_CALCTL_CALCLK2_Pos)                 /*!< OPA_T::CALCTL: CALCLK2 Mask            */
+
+#define OPA_CALCTL_CALRVS0_Pos           (16)                                              /*!< OPA_T::CALCTL: CALRVS0 Position        */
+#define OPA_CALCTL_CALRVS0_Msk           (0x1ul << OPA_CALCTL_CALRVS0_Pos)                 /*!< OPA_T::CALCTL: CALRVS0 Mask            */
+
+#define OPA_CALCTL_CALRVS1_Pos           (17)                                              /*!< OPA_T::CALCTL: CALRVS1 Position        */
+#define OPA_CALCTL_CALRVS1_Msk           (0x1ul << OPA_CALCTL_CALRVS1_Pos)                 /*!< OPA_T::CALCTL: CALRVS1 Mask            */
+
+#define OPA_CALCTL_CALRVS2_Pos           (18)                                              /*!< OPA_T::CALCTL: CALRVS2 Position        */
+#define OPA_CALCTL_CALRVS2_Msk           (0x1ul << OPA_CALCTL_CALRVS2_Pos)                 /*!< OPA_T::CALCTL: CALRVS2 Mask            */
+
+#define OPA_CALST_DONE0_Pos              (0)                                               /*!< OPA_T::CALST: DONE0 Position           */
+#define OPA_CALST_DONE0_Msk              (0x1ul << OPA_CALST_DONE0_Pos)                    /*!< OPA_T::CALST: DONE0 Mask               */
+
+#define OPA_CALST_CALNS0_Pos             (1)                                               /*!< OPA_T::CALST: CALNS0 Position          */
+#define OPA_CALST_CALNS0_Msk             (0x1ul << OPA_CALST_CALNS0_Pos)                   /*!< OPA_T::CALST: CALNS0 Mask              */
+
+#define OPA_CALST_CALPS0_Pos             (2)                                               /*!< OPA_T::CALST: CALPS0 Position          */
+#define OPA_CALST_CALPS0_Msk             (0x1ul << OPA_CALST_CALPS0_Pos)                   /*!< OPA_T::CALST: CALPS0 Mask              */
+
+#define OPA_CALST_DONE1_Pos              (4)                                               /*!< OPA_T::CALST: DONE1 Position           */
+#define OPA_CALST_DONE1_Msk              (0x1ul << OPA_CALST_DONE1_Pos)                    /*!< OPA_T::CALST: DONE1 Mask               */
+
+#define OPA_CALST_CALNS1_Pos             (5)                                               /*!< OPA_T::CALST: CALNS1 Position          */
+#define OPA_CALST_CALNS1_Msk             (0x1ul << OPA_CALST_CALNS1_Pos)                   /*!< OPA_T::CALST: CALNS1 Mask              */
+
+#define OPA_CALST_CALPS1_Pos             (6)                                               /*!< OPA_T::CALST: CALPS1 Position          */
+#define OPA_CALST_CALPS1_Msk             (0x1ul << OPA_CALST_CALPS1_Pos)                   /*!< OPA_T::CALST: CALPS1 Mask              */
+
+#define OPA_CALST_DONE2_Pos              (8)                                               /*!< OPA_T::CALST: DONE2 Position           */
+#define OPA_CALST_DONE2_Msk              (0x1ul << OPA_CALST_DONE2_Pos)                    /*!< OPA_T::CALST: DONE2 Mask               */
+
+#define OPA_CALST_CALNS2_Pos             (9)                                               /*!< OPA_T::CALST: CALNS2 Position          */
+#define OPA_CALST_CALNS2_Msk             (0x1ul << OPA_CALST_CALNS2_Pos)                   /*!< OPA_T::CALST: CALNS2 Mask              */
+
+#define OPA_CALST_CALPS2_Pos             (10)                                              /*!< OPA_T::CALST: CALPS2 Position          */
+#define OPA_CALST_CALPS2_Msk             (0x1ul << OPA_CALST_CALPS2_Pos)                   /*!< OPA_T::CALST: CALPS2 Mask              */
+
+/**@}*/ /* OPA_CONST */
+/**@}*/ /* end of OPA register group */
+
+/**@}*/ /* end of REGISTER group */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+
+/*@}*/ /* end of group M480_Peripherals */
+
+/** @addtogroup M480_PERIPHERAL_MEM_MAP M480 Peripheral Memory Base
+  Memory Mapped Structure for M480 Peripheral
+  @{
+ */
+/* Peripheral and SRAM base address */
+#define FLASH_BASE           ((uint32_t)0x00000000)      /*!< Flash base address      */
+#define SRAM_BASE            ((uint32_t)0x20000000)      /*!< SRAM Base Address       */
+#define PERIPH_BASE          ((uint32_t)0x40000000)      /*!< Peripheral Base Address */
+#define AHBPERIPH_BASE       PERIPH_BASE                 /*!< AHB Base Address */
+#define APBPERIPH_BASE       (PERIPH_BASE + (uint32_t)0x00040000)  /*!< APB Base Address */
+
+/*!< AHB peripherals */
+#define SYS_BASE               (AHBPERIPH_BASE + 0x00000UL)
+#define CLK_BASE               (AHBPERIPH_BASE + 0x00200UL)
+#define GPIOA_BASE             (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOB_BASE             (AHBPERIPH_BASE + 0x04040UL)
+#define GPIOC_BASE             (AHBPERIPH_BASE + 0x04080UL)
+#define GPIOD_BASE             (AHBPERIPH_BASE + 0x040C0UL)
+#define GPIOE_BASE             (AHBPERIPH_BASE + 0x04100UL)
+#define GPIOF_BASE             (AHBPERIPH_BASE + 0x04140UL)
+#define GPIOG_BASE             (AHBPERIPH_BASE + 0x04180UL)
+#define GPIOH_BASE             (AHBPERIPH_BASE + 0x041C0UL)
+#define GPIOI_BASE             (AHBPERIPH_BASE + 0x04200UL)
+#define GPIO_DBCTL_BASE        (AHBPERIPH_BASE + 0x04440UL)
+#define GPIO_PIN_DATA_BASE     (AHBPERIPH_BASE + 0x04800UL)
+#define PDMA_BASE              (AHBPERIPH_BASE + 0x08000UL)
+#define USBH_BASE              (AHBPERIPH_BASE + 0x09000UL)
+#define HSUSBH_BASE            (AHBPERIPH_BASE + 0x1A000UL)
+#define EMAC_BASE              (AHBPERIPH_BASE + 0x0B000UL)
+#define FMC_BASE               (AHBPERIPH_BASE + 0x0C000UL)
+#define SDH0_BASE              (AHBPERIPH_BASE + 0x0D000UL)
+#define SDH1_BASE              (AHBPERIPH_BASE + 0x0E000UL)
+#define EBI_BASE               (AHBPERIPH_BASE + 0x10000UL)
+#define HSUSBD_BASE            (AHBPERIPH_BASE + 0x19000UL)
+#define CRC_BASE               (AHBPERIPH_BASE + 0x31000UL)
+#define TAMPER_BASE            (AHBPERIPH_BASE + 0xE1000UL)
+
+/*!< APB2 peripherals */
+#define WDT_BASE              (APBPERIPH_BASE + 0x00000UL)
+#define WWDT_BASE             (APBPERIPH_BASE + 0x00100UL)
+#define OPA_BASE              (APBPERIPH_BASE + 0x06000UL)
+#define I2S_BASE              (APBPERIPH_BASE + 0x08000UL)
+#define TIMER0_BASE           (APBPERIPH_BASE + 0x10000UL)
+#define TIMER1_BASE           (APBPERIPH_BASE + 0x10100UL)
+#define EPWM0_BASE            (APBPERIPH_BASE + 0x18000UL)
+#define BPWM0_BASE            (APBPERIPH_BASE + 0x1A000UL)
+#define SPI0_BASE             (APBPERIPH_BASE + 0x20000UL)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x22000UL)
+#define SPI4_BASE             (APBPERIPH_BASE + 0x24000UL)
+#define UART0_BASE            (APBPERIPH_BASE + 0x30000UL)
+#define UART2_BASE            (APBPERIPH_BASE + 0x32000UL)
+#define UART4_BASE            (APBPERIPH_BASE + 0x34000UL)
+#define I2C0_BASE             (APBPERIPH_BASE + 0x40000UL)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x42000UL)
+#define CAN0_BASE             (APBPERIPH_BASE + 0x60000UL)
+#define QEI0_BASE             (APBPERIPH_BASE + 0x70000UL)
+#define ECAP0_BASE            (APBPERIPH_BASE + 0x74000UL)
+#define USCI0_BASE            (APBPERIPH_BASE + 0x90000UL)
+
+
+/*!< APB1 peripherals */
+#define RTC_BASE              (APBPERIPH_BASE + 0x01000UL)
+#define EADC_BASE             (APBPERIPH_BASE + 0x03000UL)
+#define ACMP_BASE             (APBPERIPH_BASE + 0x05000UL)
+#define USBD_BASE             (APBPERIPH_BASE + 0x80000UL)
+#define OTG_BASE              (APBPERIPH_BASE + 0x0D000UL)
+#define HSOTG_BASE            (APBPERIPH_BASE + 0x0F000UL)
+#define TIMER2_BASE           (APBPERIPH_BASE + 0x11000UL)
+#define TIMER3_BASE           (APBPERIPH_BASE + 0x11100UL)
+#define EPWM1_BASE            (APBPERIPH_BASE + 0x19000UL)
+#define BPWM1_BASE            (APBPERIPH_BASE + 0x1B000UL)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x21000UL)
+#define SPI3_BASE             (APBPERIPH_BASE + 0x23000UL)
+#define UART1_BASE            (APBPERIPH_BASE + 0x31000UL)
+#define UART3_BASE            (APBPERIPH_BASE + 0x33000UL)
+#define UART5_BASE            (APBPERIPH_BASE + 0x35000UL)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x41000UL)
+#define CAN1_BASE             (APBPERIPH_BASE + 0x61000UL)
+#define QEI1_BASE             (APBPERIPH_BASE + 0x71000UL)
+#define ECAP1_BASE            (APBPERIPH_BASE + 0x75000UL)
+#define USCI1_BASE            (APBPERIPH_BASE + 0x91000UL)
+#define CRPT_BASE             (0x50080000UL)
+#define SPIM_BASE             (0x40007000UL)
+
+#define SC0_BASE             (APBPERIPH_BASE + 0x50000UL)
+#define SC1_BASE             (APBPERIPH_BASE + 0x51000UL)
+#define SC2_BASE             (APBPERIPH_BASE + 0x52000UL)
+#define DAC0_BASE            (APBPERIPH_BASE + 0x07000UL)
+#define DAC1_BASE            (APBPERIPH_BASE + 0x07040UL)
+#define DACDBG_BASE          (APBPERIPH_BASE + 0x07FECUL)
+#define OPA0_BASE            (APBPERIPH_BASE + 0x06000UL)
+
+/*@}*/ /* end of group M480_PERIPHERAL_MEM_MAP */
+
+
+/** @addtogroup M480_PERIPHERAL_DECLARATION M480 Peripheral Pointer
+  The Declaration of M480 Peripheral
+  @{
+ */
+
+#define SYS                  ((SYS_T *)   SYS_BASE)
+#define CLK                  ((CLK_T *)   CLK_BASE)
+#define PA                   ((GPIO_T *)  GPIOA_BASE)
+#define PB                   ((GPIO_T *)  GPIOB_BASE)
+#define PC                   ((GPIO_T *)  GPIOC_BASE)
+#define PD                   ((GPIO_T *)  GPIOD_BASE)
+#define PE                   ((GPIO_T *)  GPIOE_BASE)
+#define PF                   ((GPIO_T *)  GPIOF_BASE)
+#define PG                   ((GPIO_T *)  GPIOG_BASE)
+#define PH                   ((GPIO_T *)  GPIOH_BASE)
+#define GPA                  ((GPIO_T *)  GPIOA_BASE)
+#define GPB                  ((GPIO_T *)  GPIOB_BASE)
+#define GPC                  ((GPIO_T *)  GPIOC_BASE)
+#define GPD                  ((GPIO_T *)  GPIOD_BASE)
+#define GPE                  ((GPIO_T *)  GPIOE_BASE)
+#define GPF                  ((GPIO_T *)  GPIOF_BASE)
+#define GPG                  ((GPIO_T *)  GPIOG_BASE)
+#define GPH                  ((GPIO_T *)  GPIOH_BASE)
+#define GPIO                 ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA                 ((PDMA_T *)  PDMA_BASE)
+#define USBH                 ((USBH_T *)  USBH_BASE)
+#define HSUSBH               ((HSUSBH_T *)  HSUSBH_BASE)
+#define EMAC                 ((EMAC_T *)  EMAC_BASE)
+#define FMC                  ((FMC_T *)   FMC_BASE)
+#define SDH0                 ((SDH_T *)   SDH0_BASE)
+#define SDH1                 ((SDH_T *)   SDH1_BASE)
+#define EBI                  ((EBI_T *)   EBI_BASE)
+#define CRC                  ((CRC_T *)   CRC_BASE)
+#define TAMPER               ((TAMPER_T *) TAMPER_BASE)
+
+#define WDT                  ((WDT_T *)   WDT_BASE)
+#define WWDT                 ((WWDT_T *)  WWDT_BASE)
+#define RTC                  ((RTC_T *)   RTC_BASE)
+#define EADC                 ((EADC_T *)  EADC_BASE)
+#define ACMP                 ((ACMP_T *)  ACMP_BASE)
+
+#define I2S0                 ((I2S_T *)   I2S_BASE)
+#define USBD                 ((USBD_T *)  USBD_BASE)
+#define OTG                  ((OTG_T *)   OTG_BASE)
+#define HSUSBD               ((HSUSBD_T *)HSUSBD_BASE)
+#define HSOTG                ((HSOTG_T *) HSOTG_BASE)
+#define TIMER0               ((TIMER_T *) TIMER0_BASE)
+#define TIMER1               ((TIMER_T *) TIMER1_BASE)
+#define TIMER2               ((TIMER_T *) TIMER2_BASE)
+#define TIMER3               ((TIMER_T *) TIMER3_BASE)
+#define EPWM0                ((EPWM_T *)  EPWM0_BASE)
+#define EPWM1                ((EPWM_T *)  EPWM1_BASE)
+#define BPWM0                ((BPWM_T *)  BPWM0_BASE)
+#define BPWM1                ((BPWM_T *)  BPWM1_BASE)
+#define ECAP0                ((ECAP_T *)  ECAP0_BASE)
+#define ECAP1                ((ECAP_T *)  ECAP1_BASE)
+#define QEI0                 ((QEI_T *)   QEI0_BASE)
+#define QEI1                 ((QEI_T *)   QEI1_BASE)
+#define SPI0                 ((SPI_T *)   SPI0_BASE)
+#define SPI1                 ((SPI_T *)   SPI1_BASE)
+#define SPI2                 ((SPI_T *)   SPI2_BASE)
+#define SPI3                 ((SPI_T *)   SPI3_BASE)
+#define SPI4                 ((SPI_T *)   SPI4_BASE)
+#define UART0                ((UART_T *)  UART0_BASE)
+#define UART1                ((UART_T *)  UART1_BASE)
+#define UART2                ((UART_T *)  UART2_BASE)
+#define UART3                ((UART_T *)  UART3_BASE)
+#define UART4                ((UART_T *)  UART4_BASE)
+#define UART5                ((UART_T *)  UART5_BASE)
+#define I2C0                 ((I2C_T *)   I2C0_BASE)
+#define I2C1                 ((I2C_T *)   I2C1_BASE)
+#define I2C2                 ((I2C_T *)   I2C2_BASE)
+#define SC0                  ((SC_T *)    SC0_BASE)
+#define SC1                  ((SC_T *)    SC1_BASE)
+#define SC2                  ((SC_T *)    SC2_BASE)
+#define CAN0                 ((CAN_T *)   CAN0_BASE)
+#define CAN1                 ((CAN_T *)   CAN1_BASE)
+#define CRPT                 ((CRPT_T *)  CRPT_BASE)
+#define SPIM                 ((volatile SPIM_T *)  SPIM_BASE)
+#define DAC0                 ((DAC_T *)   DAC0_BASE)
+#define DAC1                 ((DAC_T *)   DAC1_BASE)
+#define USPI0               ((USPI_T *) USCI0_BASE)                     /*!< USPI0 Configuration Struct                       */
+#define USPI1               ((USPI_T *) USCI1_BASE)                     /*!< USPI1 Configuration Struct                       */
+#define OPA                   ((OPA_T *) OPA_BASE)
+#define UI2C0               ((UI2C_T *) USCI0_BASE)                     /*!< UI2C0 Configuration Struct                       */
+#define UI2C1               ((UI2C_T *) USCI1_BASE)                     /*!< UI2C1 Configuration Struct                       */
+#define UUART0              ((UUART_T *) USCI0_BASE)                    /*!< UUART0 Configuration Struct                      */
+#define UUART1              ((UUART_T *) USCI1_BASE)                    /*!< UUART1 Configuration Struct                      */
+
+/*@}*/ /* end of group M480_PERIPHERAL_DECLARATION */
+
+/** @addtogroup M480_IO_ROUTINE M480 I/O Routines
+  The Declaration of M480 I/O Routines
+  @{
+ */
+
+typedef volatile unsigned char  vu8;        ///< Define 8-bit unsigned volatile data type
+typedef volatile unsigned short vu16;       ///< Define 16-bit unsigned volatile data type
+typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile data type
+
+/**
+  * @brief Get a 8-bit unsigned value from specified address
+  * @param[in] addr Address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified address
+  */
+#define M8(addr)  (*((vu8  *) (addr)))
+
+/**
+  * @brief Get a 16-bit unsigned value from specified address
+  * @param[in] addr Address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified address
+  * @note The input address must be 16-bit aligned
+  */
+#define M16(addr) (*((vu16 *) (addr)))
+
+/**
+  * @brief Get a 32-bit unsigned value from specified address
+  * @param[in] addr Address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified address
+  * @note The input address must be 32-bit aligned
+  */
+#define M32(addr) (*((vu32 *) (addr)))
+
+/**
+  * @brief Set a 32-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 32-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 32-bit aligned
+  */
+#define outpw(port,value)     *((volatile unsigned int *)(port)) = (value)
+
+/**
+  * @brief Get a 32-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified I/O port
+  * @note The input port must be 32-bit aligned
+  */
+#define inpw(port)            (*((volatile unsigned int *)(port)))
+
+/**
+  * @brief Set a 16-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 16-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 16-bit aligned
+  */
+#define outps(port,value)     *((volatile unsigned short *)(port)) = (value)
+
+/**
+  * @brief Get a 16-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified I/O port
+  * @note The input port must be 16-bit aligned
+  */
+#define inps(port)            (*((volatile unsigned short *)(port)))
+
+/**
+  * @brief Set a 8-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 8-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  */
+#define outpb(port,value)     *((volatile unsigned char *)(port)) = (value)
+
+/**
+  * @brief Get a 8-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified I/O port
+  */
+#define inpb(port)            (*((volatile unsigned char *)(port)))
+
+/**
+  * @brief Set a 32-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 32-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 32-bit aligned
+  */
+#define outp32(port,value)    *((volatile unsigned int *)(port)) = (value)
+
+/**
+  * @brief Get a 32-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified I/O port
+  * @note The input port must be 32-bit aligned
+  */
+#define inp32(port)           (*((volatile unsigned int *)(port)))
+
+/**
+  * @brief Set a 16-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 16-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 16-bit aligned
+  */
+#define outp16(port,value)    *((volatile unsigned short *)(port)) = (value)
+
+/**
+  * @brief Get a 16-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified I/O port
+  * @note The input port must be 16-bit aligned
+  */
+#define inp16(port)           (*((volatile unsigned short *)(port)))
+
+/**
+  * @brief Set a 8-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 8-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  */
+#define outp8(port,value)     *((volatile unsigned char *)(port)) = (value)
+
+/**
+  * @brief Get a 8-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified I/O port
+  */
+#define inp8(port)            (*((volatile unsigned char *)(port)))
+
+
+/*@}*/ /* end of group M480_IO_ROUTINE */
+
+/******************************************************************************/
+/*                Legacy Constants                                            */
+/******************************************************************************/
+/** @addtogroup M480_legacy_Constants M480 Legacy Constants
+  M480 Legacy Constants
+  @{
+*/
+
+#ifndef NULL
+#define NULL           (0)      ///< NULL pointer
+#endif
+
+#define TRUE           (1UL)      ///< Boolean true, define to use in API parameters or return value
+#define FALSE          (0UL)      ///< Boolean false, define to use in API parameters or return value
+
+#define ENABLE         (1UL)      ///< Enable, define to use in API parameters
+#define DISABLE        (0UL)      ///< Disable, define to use in API parameters
+
+/* Define one bit mask */
+#define BIT0     (0x00000001UL)       ///< Bit 0 mask of an 32 bit integer
+#define BIT1     (0x00000002UL)       ///< Bit 1 mask of an 32 bit integer
+#define BIT2     (0x00000004UL)       ///< Bit 2 mask of an 32 bit integer
+#define BIT3     (0x00000008UL)       ///< Bit 3 mask of an 32 bit integer
+#define BIT4     (0x00000010UL)       ///< Bit 4 mask of an 32 bit integer
+#define BIT5     (0x00000020UL)       ///< Bit 5 mask of an 32 bit integer
+#define BIT6     (0x00000040UL)       ///< Bit 6 mask of an 32 bit integer
+#define BIT7     (0x00000080UL)       ///< Bit 7 mask of an 32 bit integer
+#define BIT8     (0x00000100UL)       ///< Bit 8 mask of an 32 bit integer
+#define BIT9     (0x00000200UL)       ///< Bit 9 mask of an 32 bit integer
+#define BIT10    (0x00000400UL)       ///< Bit 10 mask of an 32 bit integer
+#define BIT11    (0x00000800UL)       ///< Bit 11 mask of an 32 bit integer
+#define BIT12    (0x00001000UL)       ///< Bit 12 mask of an 32 bit integer
+#define BIT13    (0x00002000UL)       ///< Bit 13 mask of an 32 bit integer
+#define BIT14    (0x00004000UL)       ///< Bit 14 mask of an 32 bit integer
+#define BIT15    (0x00008000UL)       ///< Bit 15 mask of an 32 bit integer
+#define BIT16    (0x00010000UL)       ///< Bit 16 mask of an 32 bit integer
+#define BIT17    (0x00020000UL)       ///< Bit 17 mask of an 32 bit integer
+#define BIT18    (0x00040000UL)       ///< Bit 18 mask of an 32 bit integer
+#define BIT19    (0x00080000UL)       ///< Bit 19 mask of an 32 bit integer
+#define BIT20    (0x00100000UL)       ///< Bit 20 mask of an 32 bit integer
+#define BIT21    (0x00200000UL)       ///< Bit 21 mask of an 32 bit integer
+#define BIT22    (0x00400000UL)       ///< Bit 22 mask of an 32 bit integer
+#define BIT23    (0x00800000UL)       ///< Bit 23 mask of an 32 bit integer
+#define BIT24    (0x01000000UL)       ///< Bit 24 mask of an 32 bit integer
+#define BIT25    (0x02000000UL)       ///< Bit 25 mask of an 32 bit integer
+#define BIT26    (0x04000000UL)       ///< Bit 26 mask of an 32 bit integer
+#define BIT27    (0x08000000UL)       ///< Bit 27 mask of an 32 bit integer
+#define BIT28    (0x10000000UL)       ///< Bit 28 mask of an 32 bit integer
+#define BIT29    (0x20000000UL)       ///< Bit 29 mask of an 32 bit integer
+#define BIT30    (0x40000000UL)       ///< Bit 30 mask of an 32 bit integer
+#define BIT31    (0x80000000UL)       ///< Bit 31 mask of an 32 bit integer
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk              (0x000000FFUL)         ///< Mask to get bit0~bit7 from a 32 bit integer
+#define BYTE1_Msk              (0x0000FF00UL)         ///< Mask to get bit8~bit15 from a 32 bit integer
+#define BYTE2_Msk              (0x00FF0000UL)         ///< Mask to get bit16~bit23 from a 32 bit integer
+#define BYTE3_Msk              (0xFF000000UL)         ///< Mask to get bit24~bit31 from a 32 bit integer
+
+#define GET_BYTE0(u32Param)    (((u32Param) & BYTE0_Msk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
+#define GET_BYTE1(u32Param)    (((u32Param) & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
+#define GET_BYTE2(u32Param)    (((u32Param) & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define GET_BYTE3(u32Param)    (((u32Param) & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+/*@}*/ /* end of group M480_legacy_Constants */
+
+
+/******************************************************************************/
+/*                         Peripheral header files                            */
+/******************************************************************************/
+#include "m480_sys.h"
+#include "m480_clk.h"
+
+#include "m480_acmp.h"
+#include "m480_dac.h"
+#include "m480_emac.h"
+#include "m480_uart.h"
+#include "m480_usci_spi.h"
+#include "m480_gpio.h"
+#include "m480_ecap.h"
+#include "m480_qei.h"
+#include "m480_timer.h"
+#include "m480_timer_pwm.h"
+#include "m480_pdma.h"
+#include "m480_crypto.h"
+#include "m480_fmc.h"
+#include "m480_spim.h"
+#include "m480_i2c.h"
+#include "m480_i2s.h"
+#include "m480_epwm.h"
+#include "m480_eadc.h"
+#include "m480_bpwm.h"
+#include "m480_wdt.h"
+#include "m480_wwdt.h"
+#include "m480_opa.h"
+#include "m480_crc.h"
+#include "m480_ebi.h"
+#include "m480_usci_i2c.h"
+#include "m480_scuart.h"
+#include "m480_sc.h"
+#include "m480_spi.h"
+#include "m480_can.h"
+#include "m480_rtc.h"
+#include "m480_usci_uart.h"
+#include "m480_sdh.h"
+#include "m480_usbd.h"
+#include "m480_hsusbd.h"
+#include "m480_otg.h"
+#include "m480_hsotg.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __M480_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_acmp.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,74 @@
+/**************************************************************************//**
+ * @file     acmp.c
+ * @version  V1.00
+ * @brief    M480 series Analog Comparator(ACMP) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup M480_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Configure the specified ACMP module
+  *
+  * @param[in]  acmp The pointer of the specified ACMP module
+  * @param[in]  u32ChNum Comparator number.
+  * @param[in]  u32NegSrc Comparator negative input selection.  Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @param[in]  u32HysSel The hysteresis function option. Including:
+  *                  - \ref ACMP_CTL_HYSTERESIS_30MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_20MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_10MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_DISABLE
+  *
+  * @return     None
+  *
+  * @details    Configure hysteresis function, select the source of negative input and enable analog comparator.
+  */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
+{
+    acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
+}
+
+/**
+  * @brief  Close analog comparator
+  *
+  * @param[in]  acmp The pointer of the specified ACMP module
+  * @param[in]  u32ChNum Comparator number.
+  *
+  * @return     None
+  *
+  * @details  This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  */
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
+{
+    acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
+}
+
+
+
+/*@}*/ /* end of group M480_ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_ACMP_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_acmp.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,414 @@
+/**************************************************************************//**
+ * @file     ACMP.h
+ * @version  V1.00
+ * @brief    M480 Series ACMP Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __ACMP_H__
+#define __ACMP_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+
+/** @addtogroup M480_ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup M480_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CTL constant definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CTL_FILTSEL_OFF         (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */
+#define ACMP_CTL_FILTSEL_1PCLK       (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_2PCLK       (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_4PCLK       (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_8PCLK       (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_16PCLK      (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_32PCLK      (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_FILTSEL_64PCLK      (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */
+#define ACMP_CTL_INTPOL_RF           (0UL << ACMP_CTL_INTPOL_Pos)  /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_INTPOL_R            (1UL << ACMP_CTL_INTPOL_Pos)  /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_INTPOL_F            (2UL << ACMP_CTL_INTPOL_Pos)  /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */
+#define ACMP_CTL_POSSEL_P0           (0UL << ACMP_CTL_POSSEL_Pos)  /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P1           (1UL << ACMP_CTL_POSSEL_Pos)  /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P2           (2UL << ACMP_CTL_POSSEL_Pos)  /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_POSSEL_P3           (3UL << ACMP_CTL_POSSEL_Pos)  /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */
+#define ACMP_CTL_NEGSEL_PIN          (0UL << ACMP_CTL_NEGSEL_Pos)  /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_CRV          (1UL << ACMP_CTL_NEGSEL_Pos)  /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_VBG          (2UL << ACMP_CTL_NEGSEL_Pos)  /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_NEGSEL_DAC          (3UL << ACMP_CTL_NEGSEL_Pos)  /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_30MV     (3UL << ACMP_CTL_HYSSEL_Pos)  /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_20MV     (2UL << ACMP_CTL_HYSSEL_Pos)  /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_10MV     (1UL << ACMP_CTL_HYSSEL_Pos)  /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */
+#define ACMP_CTL_HYSTERESIS_DISABLE  (0UL << ACMP_CTL_HYSSEL_Pos)  /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_VREF constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_VREF_CRVSSEL_VDDA       (0UL << ACMP_VREF_CRVSSEL_Pos)  /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */
+#define ACMP_VREF_CRVSSEL_INTVREF    (1UL << ACMP_VREF_CRVSSEL_Pos)  /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */
+
+
+/*@}*/ /* end of group M480_ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to disable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to select ACMP negative input source
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Src is comparator negative input selection. Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @return None
+  * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
+  * \hideinitializer
+  */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
+
+/**
+  * @brief This macro is used to disable hysteresis function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
+
+/**
+  * @brief This macro is used to select hysteresis level
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32HysSel The hysteresis function option. Including:
+  *                  - \ref ACMP_CTL_HYSTERESIS_30MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_20MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_10MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_DISABLE
+  * \hideinitializer
+  * @return None
+  */
+#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
+
+/**
+  * @brief This macro is used to enable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
+  *          If wake-up function is enabled, the wake-up interrupt will be enabled as well.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to disable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to enable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to get ACMP output value
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return  ACMP output value
+  * @details This macro will return the ACMP output value.
+  * \hideinitializer
+  */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
+
+/**
+  * @brief This macro is used to get ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   ACMP interrupt occurred (1) or not (0)
+  * @details This macro will return the ACMP interrupt flag.
+  * \hideinitializer
+  */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
+
+/**
+  * @brief This macro is used to clear ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
+  * \hideinitializer
+  */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
+
+/**
+  * @brief This macro is used to clear ACMP wake-up interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
+  * \hideinitializer
+  */
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
+
+/**
+  * @brief This macro is used to enable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to select ACMP positive input pin
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Pin Comparator positive pin selection. Including:
+  *                  - \ref ACMP_CTL_POSSEL_P0
+  *                  - \ref ACMP_CTL_POSSEL_P1
+  *                  - \ref ACMP_CTL_POSSEL_P2
+  *                  - \ref ACMP_CTL_POSSEL_P3
+  * @return None
+  * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
+  * \hideinitializer
+  */
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
+
+/**
+  * @brief This macro is used to enable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to set ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cnt is comparator filter count setting.
+  *                  - \ref ACMP_CTL_FILTSEL_OFF
+  *                  - \ref ACMP_CTL_FILTSEL_1PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_2PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_4PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_8PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_16PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_32PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_64PCLK
+  * @return None
+  * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
+  * \hideinitializer
+  */
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
+
+/**
+  * @brief This macro is used to select comparator reference voltage
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32Level  The comparator reference voltage setting.
+  *             The formula is:
+  *                       comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
+  *             The range of u32Level is 0 ~ 15.
+  * @return   None
+  * @details  When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
+  * \hideinitializer
+  */
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
+
+/**
+  * @brief This macro is used to select the source of CRV
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32Src is the source of CRV. Including:
+  *                  - \ref ACMP_VREF_CRVSSEL_VDDA
+  *                  - \ref ACMP_VREF_CRVSSEL_INTVREF
+  * @return None
+  * @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
+  * \hideinitializer
+  */
+#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to select ACMP interrupt condition
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cond Comparator interrupt condition selection. Including:
+  *                  - \ref ACMP_CTL_INTPOL_RF
+  *                  - \ref ACMP_CTL_INTPOL_R
+  *                  - \ref ACMP_CTL_INTPOL_F
+  * @return None
+  * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
+  * \hideinitializer
+  */
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
+
+/**
+  * @brief This macro is used to enable ACMP window latch mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
+  *          When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
+  *          block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
+  *          WLATOUT, is frozen.
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP window latch mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
+
+/**
+  * @brief This macro is used to enable ACMP window compare mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
+  *          When window compare mode is enabled, user can connect the specific analog voltage
+  *          source to either the positive inputs of both comparators or the negative inputs of
+  *          both comparators. The upper bound and lower bound of the designated range are
+  *          determined by the voltages applied to the other inputs of both comparators. If the
+  *          output of a comparator is low and the other comparator outputs high, which means two
+  *          comparators implies the upper and lower bound. User can directly monitor a specific
+  *          analog voltage source via ACMPWO (ACMP_STATUS[16]).
+  * \hideinitializer
+  */
+#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP window compare mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
+  * \hideinitializer
+  */
+#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
+
+
+
+
+/* Function prototype declaration */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
+
+
+
+/*@}*/ /* end of group M480_ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_ACMP_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __ACMP_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_bpwm.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,703 @@
+/**************************************************************************//**
+ * @file     bpwm.c
+ * @version  V1.00
+ * @brief    M480 series BPWM driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_BPWM_Driver BPWM Driver
+  @{
+*/
+
+
+/** @addtogroup M480_BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Configure BPWM capture and get the nearest unit time.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure BPWM capture and get the nearest unit time.
+ */
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+    uint32_t u32Src;
+    uint32_t u32PWMClockSrc;
+    uint32_t u32NearestUnitTimeNsec;
+    uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU;
+
+    if(bpwm == BPWM0) {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+    } else { /* (bpwm == BPWM1) */
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+    }
+
+    if(u32Src == 0U) {
+        /* clock source is from PLL clock */
+        u32PWMClockSrc = CLK_GetPLLClockFreq();
+    } else {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if(bpwm == BPWM0) {
+            u32PWMClockSrc = CLK_GetPCLK0Freq();
+        } else {/* (bpwm == BPWM1) */
+            u32PWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+
+    u32PWMClockSrc /= 1000UL;
+    for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) {
+        uint32_t u32Exit = 0U;
+        u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc;
+        if(u32NearestUnitTimeNsec < u32UnitTimeNsec) {
+            if (u16Prescale == 0x1000U) { /* limit to the maximum unit time(nano second) */
+                u32Exit = 1U;
+            } else {
+                u32Exit = 0U;
+            }
+            if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) {
+                u32Exit = 1U;
+            } else {
+                u32Exit = 0U;
+            }
+        } else {
+            u32Exit = 1U;
+        }
+        if (u32Exit == 1U) {
+            break;
+        } else {}
+    }
+
+    /* convert to real register value */
+    /* all channels share a prescaler */
+    u16Prescale -= 1U;
+    BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale);
+
+    /* set BPWM to down count type(edge aligned) */
+    (bpwm)->CTL1 = (1UL);
+
+    BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
+
+    return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
+ *       existing frequency of other channel.
+ */
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    uint32_t u32Src;
+    uint32_t u32PWMClockSrc;
+    uint32_t i;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+    if(bpwm == BPWM0) {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+    } else { /* (bpwm == BPWM1) */
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+    }
+
+    if(u32Src == 0U) {
+        /* clock source is from PLL clock */
+        u32PWMClockSrc = CLK_GetPLLClockFreq();
+    } else {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if(bpwm == BPWM0) {
+            u32PWMClockSrc = CLK_GetPCLK0Freq();
+        } else { /* (bpwm == BPWM1) */
+            u32PWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+
+    for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) { /* prescale could be 0~0xFFF */
+        i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
+        /* If target value is larger than CNR, need to use a larger prescaler */
+        if(i < (0x10000U)) {
+            u32CNR = i;
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
+    i = u32PWMClockSrc / (u32Prescale * u32CNR);
+
+    /* convert to real register value */
+    /* all channels share a prescaler */
+    u32Prescale -= 1U;
+    BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
+    /* set BPWM to down count type(edge aligned) */
+    (bpwm)->CTL1 = (1UL);
+
+    u32CNR -= 1U;
+    BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
+    if(u32DutyCycle) {
+        BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL);
+        (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U));
+        (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTLn_Pos));
+        (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U));
+        (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos));
+    } else {
+        BPWM_SET_CMR(bpwm, u32ChannelNum, 0U);
+        (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U));
+        (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTLn_Pos));
+        (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U));
+        (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos));
+    }
+
+    return(i);
+}
+
+/**
+ * @brief Start BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to start BPWM module.
+ * @note All channels share one counter.
+ */
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Stop BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM module.
+ * @note All channels share one period.
+ */
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->PERIOD = 0U;
+}
+
+/**
+ * @brief Stop BPWM generation immediately by clear channel enable bit
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM generation immediately by clear channel enable bit.
+ * @note All channels share one counter.
+ */
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Enable selected channel to trigger EADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger EADC. Combination of following conditions:
+ *                  - \ref BPWM_TRIGGER_EADC_EVEN_ZERO_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_EVEN_PERIOD_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_EVEN_ZERO_OR_PERIOD_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_EVEN_CMP_UP_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_EVEN_CMP_DOWN_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_ODD_CMP_UP_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_EADC_ODD_CMP_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger EADC
+ */
+void BPWM_EnableEADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    if(u32ChannelNum < 4U) {
+        (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U));
+        (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U));
+    } else {
+        (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U));
+        (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U));
+    }
+}
+
+/**
+ * @brief Disable selected channel to trigger EADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable selected channel to trigger EADC
+ */
+void BPWM_DisableEADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    if(u32ChannelNum < 4U) {
+        (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U));
+    } else {
+        (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U));
+    }
+}
+
+/**
+ * @brief Clear selected channel trigger EADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger EADC flag
+ */
+void BPWM_ClearEADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (bpwm)->STATUS = (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger EADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger EADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger EADC to start of conversion flag is set
+ * @details This function is used to get BPWM trigger EADC to start of conversion flag for specified channel
+ */
+uint32_t BPWM_GetEADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s)
+ */
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CAPINEN |= u32ChannelMask;
+    (bpwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s)
+ */
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CAPINEN &= ~u32ChannelMask;
+    (bpwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enables BPWM output generation of selected channel(s)
+ */
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disables BPWM output generation of selected channel(s)
+ */
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIFn_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
+            (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIFn_Msk << u32ChannelNum)) ? 1UL : 0UL));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ *              - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ *              - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+    (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel
+ */
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+
+    (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel
+ */
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIFn_Msk | BPWM_INTSTS_CMPDIFn_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel
+ */
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIFn_Msk | BPWM_INTSTS_CMPUIFn_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
+{
+    (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return zero interrupt flag of specified channel
+ * @retval 0 zero interrupt did not occur
+ * @retval 1 zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode BPWM counter loading mode.
+ *              - \ref BPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ *              - \ref BPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Enable BPWM SYNC input pin inverse function
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32ClkSrcSel BPWM external clock source.
+ *              - \ref BPWM_CLKSRC_BPWM_CLK
+ *              - \ref BPWM_CLKSRC_TIMER0
+ *              - \ref BPWM_CLKSRC_TIMER1
+ *              - \ref BPWM_CLKSRC_TIMER2
+ *              - \ref BPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to enable BPWM SYNC input pin inverse function.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+    (bpwm)->CLKSRC = (u32ClkSrcSel);
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
+}
+
+
+/*@}*/ /* end of group M480_BPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_BPWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_bpwm.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,319 @@
+/**************************************************************************//**
+ * @file     bpwm.h
+ * @version  V1.00
+ * @brief    M480 series PWM driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __BPWM_H__
+#define __BPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_BPWM_Driver BPWM Driver
+  @{
+*/
+
+/** @addtogroup M480_BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
+  @{
+*/
+#define BPWM_CHANNEL_NUM                          (6)        /*!< BPWM channel number \hideinitializer */
+#define BPWM_CH_0_MASK                            (0x1UL)    /*!< BPWM channel 0 mask \hideinitializer */
+#define BPWM_CH_1_MASK                            (0x2UL)    /*!< BPWM channel 1 mask \hideinitializer */
+#define BPWM_CH_2_MASK                            (0x4UL)    /*!< BPWM channel 2 mask \hideinitializer */
+#define BPWM_CH_3_MASK                            (0x8UL)    /*!< BPWM channel 3 mask \hideinitializer */
+#define BPWM_CH_4_MASK                            (0x10UL)   /*!< BPWM channel 4 mask \hideinitializer */
+#define BPWM_CH_5_MASK                            (0x20UL)   /*!< BPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_UP_COUNTER                           (0UL)      /*!< Up counter type \hideinitializer */
+#define BPWM_DOWN_COUNTER                         (1UL)      /*!< Down counter type \hideinitializer */
+#define BPWM_UP_DOWN_COUNTER                      (2UL)      /*!< Up-Down counter type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Aligned Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_EDGE_ALIGNED                         (1UL)      /*!< BPWM working in edge aligned type(down count) \hideinitializer */
+#define BPWM_CENTER_ALIGNED                       (2UL)      /*!< BPWM working in center aligned type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_OUTPUT_NOTHING                       (0UL)      /*!< BPWM output nothing \hideinitializer */
+#define BPWM_OUTPUT_LOW                           (1UL)      /*!< BPWM output low \hideinitializer */
+#define BPWM_OUTPUT_HIGH                          (2UL)      /*!< BPWM output high \hideinitializer */
+#define BPWM_OUTPUT_TOGGLE                        (3UL)      /*!< BPWM output toggle \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Trigger Source Select Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_TRIGGER_EADC_EVEN_ZERO_POINT                     (0UL)     /*!< BPWM trigger EADC while counter of even channel matches zero point \hideinitializer */
+#define BPWM_TRIGGER_EADC_EVEN_PERIOD_POINT                   (1UL)     /*!< BPWM trigger EADC while counter of even channel matches period point \hideinitializer */
+#define BPWM_TRIGGER_EADC_EVEN_ZERO_OR_PERIOD_POINT           (2UL)     /*!< BPWM trigger EADC while counter of even channel matches zero or period point \hideinitializer */
+#define BPWM_TRIGGER_EADC_EVEN_CMP_UP_COUNT_POINT             (3UL)     /*!< BPWM trigger EADC while counter of even channel matches up count to comparator point \hideinitializer */
+#define BPWM_TRIGGER_EADC_EVEN_CMP_DOWN_COUNT_POINT           (4UL)     /*!< BPWM trigger EADC while counter of even channel matches down count to comparator point \hideinitializer */
+#define BPWM_TRIGGER_EADC_ODD_CMP_UP_COUNT_POINT              (8UL)     /*!< BPWM trigger EADC while counter of odd channel matches up count to comparator point \hideinitializer */
+#define BPWM_TRIGGER_EADC_ODD_CMP_DOWN_COUNT_POINT            (9UL)     /*!< BPWM trigger EADC while counter of odd channel matches down count to comparator point \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Capture Control Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_CAPTURE_INT_RISING_LATCH             (1UL)        /*!< BPWM capture interrupt if channel has rising transition \hideinitializer */
+#define BPWM_CAPTURE_INT_FALLING_LATCH            (0x100UL)    /*!< BPWM capture interrupt if channel has falling transition \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Duty Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP        (1 << BPWM_INTEN_CMPDIENn_Pos)   /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */
+#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP          (1 << BPWM_INTEN_CMPUIENn_Pos)   /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Load Mode Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_LOAD_MODE_IMMEDIATE                  (1 << BPWM_CTL0_IMMLDENn_Pos)    /*!< BPWM immediately load mode \hideinitializer */
+#define BPWM_LOAD_MODE_CENTER                     (1 << BPWM_CTL0_CTRLDn_Pos)      /*!< BPWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Clock Source Select Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_CLKSRC_BPWM_CLK                      (0UL)    /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK \hideinitializer */
+#define BPWM_CLKSRC_TIMER0                        (1UL)    /*!< BPWM Clock source selects to TIMER0 overflow \hideinitializer */
+#define BPWM_CLKSRC_TIMER1                        (2UL)    /*!< BPWM Clock source selects to TIMER1 overflow \hideinitializer */
+#define BPWM_CLKSRC_TIMER2                        (3UL)    /*!< BPWM Clock source selects to TIMER2 overflow \hideinitializer */
+#define BPWM_CLKSRC_TIMER3                        (4UL)    /*!< BPWM Clock source selects to TIMER3 overflow \hideinitializer */
+
+/*@}*/ /* end of group M480_BPWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Enable timer synchronous mode of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to enable timer synchronous mode of specified channel(s).
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL |= BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief Disable timer synchronous mode of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to disable timer synchronous mode of specified channel(s).
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) (*(__IO uint32_t *) (&((bpwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) (*(__IO uint32_t *) (&((bpwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
+    { \
+        (bpwm)->MSKEN = (u32ChannelMask); \
+        (bpwm)->MSK = (u32LevelMask); \
+    }
+
+/**
+ * @brief This macro set the prescaler of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
+
+/**
+ * @brief This macro set the duty of the selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * \hideinitializer
+ */
+#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
+
+/**
+ * @brief This macro set the period of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * @note BPWM counter will stop if period length set to 0
+ * \hideinitializer
+ */
+#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
+
+/**
+ * @brief This macro set the BPWM aligned type
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @param[in] u32AlignedType BPWM aligned type, valid values are:
+ *              - \ref BPWM_EDGE_ALIGNED
+ *              - \ref BPWM_CENTER_ALIGNED
+ * @return None
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
+
+/**
+ * @brief Clear counter of channel 0
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to clear counter of channel 0
+ * \hideinitializer
+ */
+#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * \hideinitializer
+ */
+#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+   do{ \
+        int i; \
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) { \
+                (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
+                (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
+                (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
+                (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
+            } \
+        } \
+    }while(0)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define BPWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableEADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void BPWM_DisableEADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearEADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t BPWM_GetEADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType);
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+
+
+/*@}*/ /* end of group M480_BPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_BPWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BPWM_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_can.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1126 @@
+/**************************************************************************//**
+ * @file     can.c
+ * @version  V2.00
+ * @brief    M480 series CAN driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup M480_CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+#if defined(CAN1)
+static uint8_t gu8LockCanIf[2ul][2ul] = {0ul};    /* The chip has two CANs. */
+#elif defined(CAN0) || defined(CAN)
+static uint8_t gu8LockCanIf[1ul][2ul] = {0ul};    /* The chip only has one CAN. */
+#endif
+
+#define RETRY_COUNTS    (0x10000000ul)
+
+#define TSEG1_MIN 2ul
+#define TSEG1_MAX 16ul
+#define TSEG2_MIN 1ul
+#define TSEG2_MAX 8ul
+#define BRP_MIN   1ul
+#define BRP_MAX   1024ul  /* 6-bit BRP field + 4-bit BRPE field*/
+#define SJW_MAX   4ul
+#define BRP_INC   1ul
+
+/* #define DEBUG_PRINTF printf */
+#define DEBUG_PRINTF(...)
+
+static uint32_t LockIF(CAN_T *tCAN);
+static uint32_t LockIF_TL(CAN_T *tCAN);
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+void CAN_WaitMsg(CAN_T *tCAN);
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg);
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2);
+
+/**
+  * @brief Check if any interface is available then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If a interface is
+  *          available, set a flag to lock the interface.
+  */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+    uint32_t u32CanNo;
+    uint32_t u32FreeIfNo;
+    uint32_t u32IntMask;
+
+#if defined(CAN1)
+    u32CanNo = (tCAN == CAN1) ? 1ul : 0ul;
+#else /* defined(CAN0) || defined(CAN) */
+    u32CanNo = 0ul;
+#endif
+
+    u32FreeIfNo = 2ul;
+
+    /* Disable CAN interrupt */
+    u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+    tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+    /* Check interface 1 is available or not */
+    if((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) {
+        if(gu8LockCanIf[u32CanNo][0ul] == 0ul) {
+            gu8LockCanIf[u32CanNo][0ul] = 1u;
+            u32FreeIfNo = 0ul;
+        } else {
+        }
+    } else {
+    }
+
+    /* Or check interface 2 is available or not */
+    if(u32FreeIfNo == 2ul) {
+        if((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) {
+            if(gu8LockCanIf[u32CanNo][1ul] == 0ul) {
+                gu8LockCanIf[u32CanNo][1ul] = 1u;
+                u32FreeIfNo = 1ul;
+            } else {
+            }
+        } else {
+        }
+    } else {
+    }
+
+    /* Enable CAN interrupt */
+    tCAN->CON |= u32IntMask;
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Check if any interface is available in a time limitation then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If no interface is
+  *          it will try again until time out. If a interface is available,  set a flag to
+  *          lock the interface.
+  */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+    uint32_t u32Count;
+    uint32_t u32FreeIfNo;
+
+    for(u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++) {
+        if((u32FreeIfNo = LockIF(tCAN)) != 2ul) {
+            break;
+        } else {
+        }
+    }
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Release locked interface.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Info The interface number, 0 or 1.
+  * @return none
+  * @details Release the locked interface.
+  */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+    uint32_t u32IntMask;
+    uint32_t u32CanNo;
+
+    if(u32IfNo >= 2ul) {
+    } else {
+#if defined(CAN1)
+        u32CanNo = (tCAN == CAN1) ? 1ul : 0ul;
+#else /* defined(CAN0) || defined(CAN) */
+        u32CanNo = 0ul;
+#endif
+
+        /* Disable CAN interrupt */
+        u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+        tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+        gu8LockCanIf[u32CanNo][u32IfNo] = 0u;
+
+        /* Enable CAN interrupt */
+        tCAN->CON |= u32IntMask;
+    }
+}
+
+/**
+  * @brief Enter initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] Following values can be used.
+  *            \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+  *            \ref CAN_CON_EIE_Msk Enable error interrupt.
+  *            \ref CAN_CON_SIE_Msk Enable status interrupt.
+  *            \ref CAN_CON_IE_Msk CAN interrupt.
+  * @return None
+  * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+  *          register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+  *          to leave initialization mode and lock bit timing register to let new configuration
+  *          take effect.
+  */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+    tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+  * @brief Leave initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to set CAN to leave initialization mode to let
+  *          bit timing configuration take effect after configuration ready.
+  */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+    tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+    while(tCAN->CON & CAN_CON_INIT_Msk) {
+        /* Check INIT bit is released */
+    }
+}
+
+/**
+  * @brief Wait message into message buffer in basic mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to wait message into message buffer in basic mode. Please notice the
+  *          function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+  */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+    tCAN->STATUS = 0x0ul; /* clr status */
+
+    while(1) {
+        if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) { /* check new data */
+            /* New Data IN */
+            break;
+        } else {
+        }
+
+        if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) {
+            /* Rx OK */
+        } else {
+        }
+
+        if(tCAN->STATUS & CAN_STATUS_LEC_Msk) {
+            /* Error */
+        } else {
+        }
+    }
+}
+
+/**
+  * @brief Get current bit rate
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return Current Bit-Rate (kilo bit per second)
+  * @details Return current CAN bit rate according to the user bit-timing parameter settings
+  */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+    uint32_t u32Tseg1, u32Tseg2;
+    uint32_t u32Bpr;
+
+    u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
+    u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
+    u32Bpr   = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul);
+
+    return (SystemCoreClock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul));
+}
+
+/**
+  * @brief Switch the CAN into test mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8TestMask Specifies the configuration in test modes
+  *                       \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+  *                       \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+  *                       \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+  *                       \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field
+  * @return None
+  * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+  *          LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+  *          must call CAN_LeaveInitMode() to let the setting take effect.
+  */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST = u8TestMask;
+}
+
+
+/**
+  * @brief Leave the test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return   None
+  * @details  This function is used to Leave the test mode (switch into normal mode).
+  */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+    tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+  * @brief Get the waiting status of a received message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @retval non-zero The corresponding message object has a new data bit is set.
+  * @retval 0 No message object has new data.
+  * @details This function is used to get the waiting status of a received message.
+  */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+    return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul)));
+}
+
+
+/**
+  * @brief Send CAN message in BASIC mode of test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+  * @return TRUE:  Transmission OK
+  *         FALSE: Check busy flag of interface 0 is timeout
+  * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+  *          the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+  *          basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+  */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+    uint32_t i = 0ul;
+    int32_t rev = 1l;
+
+    while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    if(pCanMsg->IdType == CAN_STD_ID) {
+        /* standard ID*/
+        tCAN->IF[0].ARB1 = 0ul;
+        tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ;
+    } else {
+        /* extended ID*/
+        tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+        tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul  | CAN_IF_ARB2_XTD_Msk;
+
+    }
+
+    if(pCanMsg->FrameType) {
+        tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+    } else {
+        tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+    }
+
+    tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+    tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]);
+    tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]);
+    tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]);
+    tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]);
+
+    /* request transmission*/
+    tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+    if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {
+        /* Cannot clear busy for sending ...*/
+        rev = 0l; /* return FALSE */
+    } else {
+        tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk;  /* sending */
+
+        for(i = 0ul; i < 0xFFFFFul; i++) {
+            if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) {
+                break;
+            } else {
+            }
+        }
+
+        if(i >= 0xFFFFFul) {
+            /* Cannot send out... */
+            rev = 0l; /* return FALSE */
+        } else {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Get a message information in BASIC mode.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @return FALSE No any message received.
+  *         TRUE Receive a message success.
+  *
+  */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+    int32_t rev = 1l;
+
+    if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul) {
+        /* In basic mode, receive data always save in IF2 */
+        rev = 0; /* return FALSE */
+    } else {
+
+        tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+        tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+                            | CAN_IF_CMASK_CONTROL_Msk
+                            | CAN_IF_CMASK_DATAA_Msk
+                            | CAN_IF_CMASK_DATAB_Msk;
+
+        if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) {
+            /* standard ID*/
+            pCanMsg->IdType = CAN_STD_ID;
+            pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul;
+
+        } else {
+            /* extended ID*/
+            pCanMsg->IdType = CAN_EXT_ID;
+            pCanMsg->Id  = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16;
+            pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+        }
+
+        pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul;
+
+        pCanMsg->DLC     = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk);
+        pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+        pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+        pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+        pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+        pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+        pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+        pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+        pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set Rx message object, include ID mask.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+        rev = 0; /* return FALSE */
+    } else {
+        /* Command Setting */
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+        if(u8idType == CAN_STD_ID) {  /* According STD/EXT ID format,Configure Mask and Arbitration register */
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+        } else {
+            tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+        }
+
+        tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul);
+        tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul;
+
+        /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+        tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+        if(u8singleOrFifoLast) {
+            tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+        } else {
+            tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_A2  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B2  = 0ul;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set Rx message object
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+        rev = 0; /* return FALSE */
+    } else {
+        /* Command Setting */
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+        if(u8idType == CAN_STD_ID) {  /* According STD/EXT ID format,Configure Mask and Arbitration register */
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2;
+        } else {
+            tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16;
+        }
+
+        /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */
+        tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+        if(u8singleOrFifoLast) {
+            tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+        } else {
+            tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_A2  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B1  = 0ul;
+        tCAN->IF[u32MsgIfNum].DAT_B2  = 0ul;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Gets the message
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8Release Specifies the message release indicator.
+  *                      This parameter can be one of the following values:
+  *                      TRUE: the message object is released when getting the data.
+  *                      FALSE:the message object is not released.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  * @retval TRUE Success
+  * @retval FALSE No any message received
+  * @details Gets the message, if received.
+  */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) {
+        rev = 0; /* return FALSE */
+    } else {
+        /* Get and lock a free interface */
+        if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+            rev = 0; /* return FALSE */
+        } else {
+            tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+            /* read the message contents*/
+            tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+                                          | CAN_IF_CMASK_ARB_Msk
+                                          | CAN_IF_CMASK_CONTROL_Msk
+                                          | CAN_IF_CMASK_CLRINTPND_Msk
+                                          | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul)
+                                          | CAN_IF_CMASK_DATAA_Msk
+                                          | CAN_IF_CMASK_DATAB_Msk;
+
+            tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj;
+
+            while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) {
+                /*Wait*/
+            }
+
+            if((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) {
+                /* standard ID*/
+                pCanMsg->IdType = CAN_STD_ID;
+                pCanMsg->Id     = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul;
+            } else {
+                /* extended ID*/
+                pCanMsg->IdType = CAN_EXT_ID;
+                pCanMsg->Id  = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1;
+            }
+
+            pCanMsg->DLC     = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk);
+            pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+            pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+            pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+            pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+            pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+            pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+            pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+            pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+
+            ReleaseIF(tCAN, u32MsgIfNum);
+        }
+    }
+
+    return rev;
+}
+
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)
+{
+    *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
+    if (*tseg2 < ((int) TSEG2_MIN)) {
+        *tseg2 = TSEG2_MIN;
+    } else {
+    }
+
+    if (*tseg2 > ((int) TSEG2_MAX)) {
+        *tseg2 = TSEG2_MAX;
+    } else {
+    }
+
+    *tseg1 = tseg - *tseg2;
+    if (*tseg1 > ((int) TSEG1_MAX)) {
+        *tseg1 = TSEG1_MAX;
+        *tseg2 = tseg - *tseg1;
+    } else {
+    }
+
+    return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief Set bus baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  *
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+  */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+    long rate;
+    long best_error = 1000000000, error = 0;
+    int best_tseg = 0, best_brp = 0, brp = 0;
+    int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
+    int spt_error = 1000, spt = 0, sampl_pt;
+    uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1;
+    uint32_t sjw = (uint32_t)1;
+
+    CAN_EnterInitMode(tCAN, (uint8_t)0);
+
+    SystemCoreClockUpdate();
+    if(tCAN == CAN0) {
+        u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk);
+        u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
+    } else if(tCAN == CAN1) {
+        u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos);
+        u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
+    }
+
+    clock_freq = SystemCoreClock / u64PCLK_DIV;
+
+    if(u32BaudRate >= (uint32_t)1000000) {
+        u32BaudRate = (uint32_t)1000000;
+    }
+
+    /* Use CIA recommended sample points */
+    if (u32BaudRate > (uint32_t)800000) {
+        sampl_pt = (int)750;
+    } else if (u32BaudRate > (uint32_t)500000) {
+        sampl_pt = (int)800;
+    } else {
+        sampl_pt = (int)875;
+    }
+
+    /* tseg even = round down, odd = round up */
+    for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (int) ((TSEG1_MIN + TSEG2_MIN) * 2ul); tseg--) {
+        tsegall = 1ul + tseg / 2ul;
+        /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
+        brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2;
+        /* chose brp step which is possible in system */
+        brp = (brp / BRP_INC) * BRP_INC;
+
+        if ((brp < ((int) BRP_MIN)) || (brp > ((int) BRP_MAX))) {
+            continue;
+        }
+        rate = clock_freq / (brp * tsegall);
+
+        error = u32BaudRate - rate;
+
+        /* tseg brp biterror */
+        if (error < 0) {
+            error = -error;
+        }
+        if (error > best_error) {
+            continue;
+        }
+        best_error = error;
+        if (error == 0) {
+            spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2);
+            error = sampl_pt - spt;
+            if (error < 0) {
+                error = -error;
+            }
+            if (error > spt_error) {
+                continue;
+            }
+            spt_error = error;
+        }
+        best_tseg = tseg / 2;
+        best_brp = brp;
+
+        if (error == 0) {
+            break;
+        }
+    }
+
+    spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2);
+
+    /* check for sjw user settings */
+    /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */
+    if (sjw > SJW_MAX) {
+        sjw = SJW_MAX;
+    }
+    /* bt->sjw must not be higher than tseg2 */
+    if (tseg2 < ((int) sjw)) {
+        sjw = tseg2;
+    }
+
+    /* real bit-rate */
+    u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1));
+
+    tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) |
+                  ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos);
+    tCAN->BRPE  = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful;
+
+    /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */
+
+    CAN_LeaveInitMode(tCAN);
+
+    return u32BaudRate;
+}
+
+/**
+  * @brief The function is used to disable all CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  *
+  * @return None
+  *
+  * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+  */
+void CAN_Close(CAN_T *tCAN)
+{
+    CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Set CAN operation mode and target baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  * @param[in] u32Mode The CAN operation mode. Valid values are:
+  *                    - \ref CAN_NORMAL_MODE Normal operation.
+  *                    - \ref CAN_BASIC_MODE Basic mode.
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details Set bus timing parameter according current clock and target baud-rate.
+  *          In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+  */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+    uint32_t u32CurrentBitRate;
+
+    u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+    if(u32Mode == CAN_BASIC_MODE) {
+        CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk);
+    } else {
+    }
+
+    return u32CurrentBitRate;
+}
+
+/**
+  * @brief The function is used to configure a transmit object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Config message object success.
+  *
+  * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+  *          They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+  */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+        rev = 0; /* return FALSE */
+    } else {
+        /* update the contents needed for transmission*/
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                      CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk  | CAN_IF_CMASK_DATAB_Msk;
+
+        if(pCanMsg->IdType == CAN_STD_ID) {
+            /* standard ID*/
+            tCAN->IF[u32MsgIfNum].ARB1 = 0ul;
+            tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+        } else {
+            /* extended ID*/
+            tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul;
+            tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 |
+                                         CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+        }
+
+        if(pCanMsg->FrameType) {
+            tCAN->IF[u32MsgIfNum].ARB2 |=   CAN_IF_ARB2_DIR_Msk;
+        } else {
+            tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+        }
+
+        tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]);
+        tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]);
+        tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]);
+        tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]);
+
+        tCAN->IF[u32MsgIfNum].MCON   =  CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+        tCAN->IF[u32MsgIfNum].CREQ   = 1ul + u32MsgNum;
+
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Set transmit request bit.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return TRUE: Start transmit message.
+  *
+  * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+  */
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum)
+{
+    int32_t rev = 1l;
+    uint32_t u32MsgIfNum;
+
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+        rev = 0; /* return FALSE */
+    } else {
+        tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+        /* read the message contents*/
+        tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+                                      | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+        tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+        while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) {
+            /*Wait*/
+        }
+        tCAN->IF[u32MsgIfNum].CMASK  = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+        tCAN->IF[u32MsgIfNum].CREQ  = 1ul + u32MsgNum;
+
+        ReleaseIF(tCAN, u32MsgIfNum);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Enable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. Valid values are:
+  *                    - \ref CAN_CON_IE_Msk Module interrupt enable.
+  *                    - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+  *                    - \ref CAN_CON_EIE_Msk Error interrupt enable.
+  *
+  * @return None
+  *
+  * @details The application software has two possibilities to follow the source of a message interrupt.
+  *          First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+  */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+                (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Disable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+  *
+  * @return None
+  *
+  * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+  */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32TimeOutCount = 0ul;
+
+    while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) {
+        if(++u32TimeOutCount >= RETRY_COUNTS) {
+            rev = (int32_t)(FALSE); /* return FALSE */
+            break;
+        } else {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+    int32_t  rev = (int32_t)TRUE;
+    uint32_t u32TimeOutCount = 0ul;
+
+    while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) {
+        if(++u32TimeOutCount >= RETRY_COUNTS) {
+            rev = (int32_t)FALSE;
+            break;
+        } else {
+        }
+    }
+
+    return rev;
+}
+
+/**
+  * @brief The function is used to configure several receive message objects.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+  * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure receive message objects success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+    int32_t  rev = (int32_t)TRUE;
+    uint32_t i = 0ul;
+    uint32_t u32TimeOutCount;
+    uint32_t u32EOB_Flag = 0ul;
+
+    for(i = 1ul; i < u32MsgCount; i++) {
+        u32TimeOutCount = 0ul;
+
+        u32MsgNum += (i - 1ul);
+
+        if(i == u32MsgCount) {
+            u32EOB_Flag = 1ul;
+        } else {
+        }
+
+        while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) {
+            if(++u32TimeOutCount >= RETRY_COUNTS) {
+                rev = (int32_t)FALSE;
+                break;
+            } else {
+            }
+        }
+    }
+
+    return rev;
+}
+
+
+/**
+  * @brief Send CAN message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+  *               2. When operation in normal mode: No useful interface. \n
+  * @retval TRUE Transmit Message success.
+  *
+  * @details The receive/transmit priority for the Message Objects is attached to the message number.
+  *          Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+  */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32Tmp;
+
+    u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+    if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) {
+        rev = CAN_BasicSendMsg(tCAN, pCanMsg);
+    } else {
+        if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE) {
+            rev = (int32_t)FALSE;
+        } else {
+            CAN_TriggerTxMsg(tCAN, u32MsgNum);
+        }
+    }
+
+    return rev;
+}
+
+
+/**
+  * @brief Gets the message, if received.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No any message received.
+  * @retval TRUE Receive Message success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    int32_t rev = (int32_t)TRUE;
+    uint32_t u32Tmp;
+
+    u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk);
+
+    if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) {
+        rev = CAN_BasicReceiveMsg(tCAN, pCanMsg);
+    } else {
+        rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg);
+    }
+
+    return rev;
+}
+
+/**
+  * @brief Clear interrupt pending bit.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return None
+  *
+  * @details An interrupt remains pending until the application software has cleared it.
+  */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+    uint32_t u32MsgIfNum;
+
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) {
+        u32MsgIfNum = 0ul;
+    } else {
+    }
+
+    tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum;
+
+    ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+
+/*@}*/ /* end of group M480_CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CAN_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_can.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file     can.h
+ * @version  V2.00
+ * @brief    M480 Series CAN Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "M480.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup M480_CAN_EXPORTED_CONSTANTS CAN Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_NORMAL_MODE   0ul    /*!< CAN select normal mode \hideinitializer */
+#define    CAN_BASIC_MODE    1ul    /*!< CAN select basic mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_STD_ID    0ul    /*!< CAN select standard ID \hideinitializer */
+#define    CAN_EXT_ID    1ul    /*!< CAN select extended ID \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_REMOTE_FRAME    0ul    /*!< CAN frame select remote frame \hideinitializer */
+#define    CAN_DATA_FRAME    1ul      /*!< CAN frame select data frame \hideinitializer */
+
+/*@}*/ /* end of group M480_CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_CAN_EXPORTED_STRUCTS CAN Exported Structs
+  @{
+*/
+/**
+  * @details    CAN message structure
+  */
+typedef struct {
+    uint32_t  IdType;       /*!< ID type */
+    uint32_t  FrameType;    /*!< Frame type */
+    uint32_t  Id;           /*!< Message ID */
+    uint8_t   DLC;          /*!< Data length */
+    uint8_t   Data[8];      /*!< Data */
+} STR_CANMSG_T;
+
+/**
+  * @details    CAN mask message structure
+  */
+typedef struct {
+    uint8_t   u8Xtd;      /*!< Extended ID */
+    uint8_t   u8Dir;      /*!< Direction */
+    uint32_t  u32Id;      /*!< Message ID */
+    uint8_t   u8IdType;   /*!< ID type*/
+} STR_CANMASK_T;
+
+/*@}*/ /* end of group M480_CAN_EXPORTED_STRUCTS */
+
+/** @cond HIDDEN_SYMBOLS */
+#define MSG(id)  (id)
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ *          EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ *          with the highest priority, disregarding their chronological order.
+ *  \hideinitializer
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details  The macro is used to disable wake-up function.
+ * \hideinitializer
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * \hideinitializer
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ *          or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ * \hideinitializer
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+
+
+/*@}*/ /* end of group M480_CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CAN_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CAN_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_clk.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1002 @@
+/**************************************************************************//**
+ * @file     clk.c
+ * @version  V3.00
+ * @brief    M480 series CLK driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CLK_Driver CLK Driver
+  @{
+*/
+
+/** @addtogroup M480_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Disable clock divider output function
+  * @param      None
+  * @return     None
+  * @details    This function disable clock divider output function.
+  */
+void CLK_DisableCKO(void)
+{
+    /* Disable CKO clock source */
+    CLK_DisableModuleClock(CLKO_MODULE);
+}
+
+/**
+  * @brief      This function enable clock divider output module clock,
+  *             enable clock divider output function and set frequency selection.
+  * @param[in]  u32ClkSrc is frequency divider function clock source. Including :
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_LXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+  * @param[in]  u32ClkDiv is divider output frequency selection. It could be 0~15.
+  * @param[in]  u32ClkDivBy1En is clock divided by one enabled.
+  * @return     None
+  * @details    Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
+  *             The formula is: \n
+  *                 CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
+  *             This function is just used to set CKO clock.
+  *             User must enable I/O for CKO clock output pin by themselves. \n
+  */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+    /* CKO = clock source / 2^(u32ClkDiv + 1) */
+    CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+
+    /* Enable CKO clock source */
+    CLK_EnableModuleClock(CLKO_MODULE);
+
+    /* Select CKO clock source */
+    CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
+}
+
+/**
+  * @brief      Enter to Power-down mode
+  * @param      None
+  * @return     None
+  * @details    This function is used to let system enter to Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_PowerDown(void)
+{
+    /* Set the processor uses deep sleep as its low power mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set system Power-down enabled and Power-down entry condition */
+    CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
+
+    /* Chip enter Power-down mode after CPU run WFI instruction */
+    __WFI();
+}
+
+/**
+  * @brief      Enter to Idle mode
+  * @param      None
+  * @return     None
+  * @details    This function let system enter to Idle mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_Idle(void)
+{
+    /* Set the processor uses sleep as its low power mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set chip in idle mode because of WFI command */
+    CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+
+    /* Chip enter idle mode after CPU run WFI instruction */
+    __WFI();
+}
+
+/**
+  * @brief      Get external high speed crystal clock frequency
+  * @param      None
+  * @return     External high frequency crystal frequency
+  * @details    This function get external high frequency crystal frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetHXTFreq(void)
+{
+    uint32_t u32Freq;
+
+    if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
+        u32Freq = __HXT;
+    } else {
+        u32Freq = 0UL;
+    }
+
+    return u32Freq;
+}
+
+
+/**
+  * @brief      Get external low speed crystal clock frequency
+  * @param      None
+  * @return     External low speed crystal clock frequency
+  * @details    This function get external low frequency crystal frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetLXTFreq(void)
+{
+    uint32_t u32Freq;
+    if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) {
+        u32Freq = __LXT;
+    } else {
+        u32Freq = 0UL;
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief      Get PCLK0 frequency
+  * @param      None
+  * @return     PCLK0 frequency
+  * @details    This function get PCLK0 frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetPCLK0Freq(void)
+{
+    uint32_t u32Freq;
+    SystemCoreClockUpdate();
+
+#if(1)
+    if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV1) {
+        u32Freq = SystemCoreClock;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV2) {
+        u32Freq = SystemCoreClock / 2UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV4) {
+        u32Freq = SystemCoreClock / 4UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV8) {
+        u32Freq = SystemCoreClock / 8UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV16) {
+        u32Freq = SystemCoreClock / 16UL;
+    } else {
+        u32Freq = SystemCoreClock;
+    }
+
+
+#else
+    if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV1) {
+        u32Freq =  SystemCoreClock;
+    } else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV2) {
+        u32Freq =  SystemCoreClock / 2UL;
+    } else {
+        u32Freq =  SystemCoreClock;
+    }
+#endif
+
+    return u32Freq;
+}
+
+
+/**
+  * @brief      Get PCLK1 frequency
+  * @param      None
+  * @return     PCLK1 frequency
+  * @details    This function get PCLK1 frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetPCLK1Freq(void)
+{
+    uint32_t u32Freq;
+    SystemCoreClockUpdate();
+
+#if(1)
+    if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV1) {
+        u32Freq = SystemCoreClock;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV2) {
+        u32Freq = SystemCoreClock / 2UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV4) {
+        u32Freq = SystemCoreClock / 4UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV8) {
+        u32Freq = SystemCoreClock / 8UL;
+    } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV16) {
+        u32Freq = SystemCoreClock / 16UL;
+    } else {
+        u32Freq = SystemCoreClock;
+    }
+
+
+#else
+    if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV1) {
+        u32Freq =  SystemCoreClock;
+    } else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV2) {
+        u32Freq =  SystemCoreClock / 2UL;
+    } else {
+        u32Freq =  SystemCoreClock;
+    }
+#endif
+
+    return u32Freq;
+}
+
+
+/**
+  * @brief      Get HCLK frequency
+  * @param      None
+  * @return     HCLK frequency
+  * @details    This function get HCLK frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetHCLKFreq(void)
+{
+    SystemCoreClockUpdate();
+    return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Get CPU frequency
+  * @param      None
+  * @return     CPU frequency
+  * @details    This function get CPU frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetCPUFreq(void)
+{
+    SystemCoreClockUpdate();
+    return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Set HCLK frequency
+  * @param[in]  u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz.
+  * @return     HCLK frequency
+  * @details    This function is used to set HCLK frequency. The frequency unit is Hz. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* The range of u32Hclk is running up to 192 MHz */
+    if(u32Hclk > FREQ_192MHZ) {
+        u32Hclk = FREQ_192MHZ;
+    }
+
+    /* Switch HCLK clock source to HIRC clock for safe */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+    CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+    /* Configure PLL setting if HXT clock is enabled */
+    if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
+    }
+    /* Configure PLL setting if HXT clock is not enabled */
+    else {
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
+
+        /* Read HIRC clock source stable flag */
+        u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+    }
+
+    /* Select HCLK clock source to PLL,
+       and update system core clock
+    */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
+
+    /* Disable HIRC if HIRC is disabled before setting core clock */
+    if(u32HIRCSTB == 0UL) {
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+    }
+
+    /* Return actually HCLK frequency is PLL frequency divide 1 */
+    return u32Hclk;
+}
+
+/**
+  * @brief      This function set HCLK clock source and HCLK clock divider
+  * @param[in]  u32ClkSrc is HCLK clock source. Including :
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_PLL
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+  * @param[in]  u32ClkDiv is HCLK clock divider. Including :
+  *             - \ref CLK_CLKDIV0_HCLK(x)
+  * @return     None
+  * @details    This function set HCLK clock source and HCLK clock divider. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
+
+    /* Apply new Divider */
+    CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+
+    /* Switch HCLK to new HCLK source */
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+
+    /* Update System Core Clock */
+    SystemCoreClockUpdate();
+
+    /* Disable HIRC if HIRC is disabled before switching HCLK source */
+    if(u32HIRCSTB == 0UL) {
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+    }
+}
+
+/**
+  * @brief      This function set selected module clock source and module clock divider
+  * @param[in]  u32ModuleIdx is module index.
+  * @param[in]  u32ClkSrc is module clock source.
+  * @param[in]  u32ClkDiv is module clock divider.
+  * @return     None
+  * @details    Valid parameter combinations listed in following table:
+  *
+  * |Module index        |Clock source                           |Divider                        |
+  * | :----------------  | :-----------------------------------  | :--------------------------   |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HXT           |\ref CLK_CLKDIV0_SDH0(x)       |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_PLL           |\ref CLK_CLKDIV0_SDH0(x)       |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HIRC          |\ref CLK_CLKDIV0_SDH0(x)       |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HCLK          |\ref CLK_CLKDIV0_SDH0(x)       |
+  * |\ref SDH1_MODULE    |\ref CLK_CLKSEL0_SDH1SEL_HXT           |\ref CLK_CLKDIV3_SDH1(x)       |
+  * |\ref SDH1_MODULE    |\ref CLK_CLKSEL0_SDH1SEL_PLL           |\ref CLK_CLKDIV3_SDH1(x)       |
+  * |\ref SDH1_MODULE    |\ref CLK_CLKSEL0_SDH1SEL_HIRC          |\ref CLK_CLKDIV3_SDH1(x)       |
+  * |\ref SDH1_MODULE    |\ref CLK_CLKSEL0_SDH1SEL_HCLK          |\ref CLK_CLKDIV3_SDH1(x)       |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LXT            | x                             |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LIRC           | x                             |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HXT           | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LXT           | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LIRC          | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HIRC          | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_PCLK0         | x                             |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_EXT           | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HXT           | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LXT           | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LIRC          | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HIRC          | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_PCLK0         | x                             |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_EXT           | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HXT           | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LXT           | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LIRC          | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HIRC          | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_PCLK1         | x                             |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_EXT           | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HXT           | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LXT           | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LIRC          | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HIRC          | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_PCLK1         | x                             |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_EXT           | x                             |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UART0SEL_HXT          |\ref CLK_CLKDIV0_UART0(x)      |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UART0SEL_LXT          |\ref CLK_CLKDIV0_UART0(x)      |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UART0SEL_PLL          |\ref CLK_CLKDIV0_UART0(x)      |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UART0SEL_HIRC         |\ref CLK_CLKDIV0_UART0(x)      |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UART1SEL_HXT          |\ref CLK_CLKDIV0_UART1(x)      |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UART1SEL_LXT          |\ref CLK_CLKDIV0_UART1(x)      |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UART1SEL_PLL          |\ref CLK_CLKDIV0_UART1(x)      |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UART1SEL_HIRC         |\ref CLK_CLKDIV0_UART1(x)      |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HXT           | x                             |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_LXT           | x                             |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HIRC          | x                             |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HCLK          | x                             |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_LIRC          | x                             |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048  | x                             |
+  * |\ref EPWM0_MODULE   |\ref CLK_CLKSEL2_EPWM0SEL_PLL          | x                             |
+  * |\ref EPWM0_MODULE   |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0        | x                             |
+  * |\ref EPWM1_MODULE   |\ref CLK_CLKSEL2_EPWM1SEL_PLL          | x                             |
+  * |\ref EPWM1_MODULE   |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1        | x                             |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HXT           | x                             |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PLL           | x                             |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HIRC          | x                             |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PCLK0         | x                             |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HXT           | x                             |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PLL           | x                             |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HIRC          | x                             |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PCLK1         | x                             |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HXT           | x                             |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PLL           | x                             |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HIRC          | x                             |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PCLK0         | x                             |
+  * |\ref BPWM0_MODULE   |\ref CLK_CLKSEL2_BPWM0SEL_PLL          | x                             |
+  * |\ref BPWM0_MODULE   |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0        | x                             |
+  * |\ref BPWM1_MODULE   |\ref CLK_CLKSEL2_BPWM1SEL_PLL          | x                             |
+  * |\ref BPWM1_MODULE   |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1        | x                             |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_HXT           | x                             |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_PLL           | x                             |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_HIRC          | x                             |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_PCLK1         | x                             |
+  * |\ref SPI4_MODULE    |\ref CLK_CLKSEL2_SPI4SEL_HXT           | x                             |
+  * |\ref SPI4_MODULE    |\ref CLK_CLKSEL2_SPI4SEL_PLL           | x                             |
+  * |\ref SPI4_MODULE    |\ref CLK_CLKSEL2_SPI4SEL_HIRC          | x                             |
+  * |\ref SPI4_MODULE    |\ref CLK_CLKSEL2_SPI4SEL_PCLK0         | x                             |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HXT            |\ref CLK_CLKDIV1_SC0(x)        |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PLL            |\ref CLK_CLKDIV1_SC0(x)        |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HIRC           |\ref CLK_CLKDIV1_SC0(x)        |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PCLK0          |\ref CLK_CLKDIV1_SC0(x)        |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_HXT            |\ref CLK_CLKDIV1_SC1(x)        |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_PLL            |\ref CLK_CLKDIV1_SC1(x)        |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_HIRC           |\ref CLK_CLKDIV1_SC1(x)        |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_PCLK1          |\ref CLK_CLKDIV1_SC1(x)        |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_HXT            |\ref CLK_CLKDIV1_SC2(x)        |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_PLL            |\ref CLK_CLKDIV1_SC2(x)        |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_HIRC           |\ref CLK_CLKDIV1_SC2(x)        |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_PCLK0          |\ref CLK_CLKDIV1_SC2(x)        |
+  * |\ref RTC_MODULE     |\ref CLK_CLKSEL3_RTCSEL_LXT            | x                             |
+  * |\ref RTC_MODULE     |\ref CLK_CLKSEL3_RTCSEL_LIRC           | x                             |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_HXT           | x                             |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_PLL           | x                             |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_HIRC          | x                             |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL3_UART2SEL_HXT          |\ref CLK_CLKDIV4_UART2(x)      |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL3_UART2SEL_LXT          |\ref CLK_CLKDIV4_UART2(x)      |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL3_UART2SEL_PLL          |\ref CLK_CLKDIV4_UART2(x)      |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL3_UART2SEL_HIRC         |\ref CLK_CLKDIV4_UART2(x)      |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL3_UART3SEL_HXT          |\ref CLK_CLKDIV4_UART3(x)      |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL3_UART3SEL_LXT          |\ref CLK_CLKDIV4_UART3(x)      |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL3_UART3SEL_PLL          |\ref CLK_CLKDIV4_UART3(x)      |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL3_UART3SEL_HIRC         |\ref CLK_CLKDIV4_UART3(x)      |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_HXT          |\ref CLK_CLKDIV4_UART4(x)      |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_LXT          |\ref CLK_CLKDIV4_UART4(x)      |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_PLL          |\ref CLK_CLKDIV4_UART4(x)      |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_HIRC         |\ref CLK_CLKDIV4_UART4(x)      |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_HXT          |\ref CLK_CLKDIV4_UART5(x)      |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_LXT          |\ref CLK_CLKDIV4_UART5(x)      |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_PLL          |\ref CLK_CLKDIV4_UART5(x)      |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_HIRC         |\ref CLK_CLKDIV4_UART5(x)      |
+  *
+  */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32sel = 0U, u32div = 0U;
+
+    if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+        /* Get clock divider control register address */
+        if(MODULE_CLKDIV(u32ModuleIdx) == 2U) {
+            u32div = (uint32_t)&CLK->CLKDIV3;
+        } else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) {
+            u32div = (uint32_t)&CLK->CLKDIV4;
+        } else {
+            u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
+        }
+
+        /* Apply new divider */
+        M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+    }
+
+    if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+        /* Get clock select control register address */
+        u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
+        /* Set new clock selection setting */
+        M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+    }
+}
+
+/**
+  * @brief      Set SysTick clock source
+  * @param[in]  u32ClkSrc is module clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  * @return     None
+  * @details    This function set SysTick clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+
+}
+
+/**
+  * @brief      Enable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  * @return     None
+  * @details    This function enable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+  * @brief      Disable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  * @return     None
+  * @details    This function disable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+  * @brief      Enable module clock
+  * @param[in]  u32ModuleIdx is module index. Including :
+  *             - \ref PDMA_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref EMAC_MODULE
+  *             - \ref SDH0_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref HSUSBD_MODULE
+  *             - \ref CRPT_MODULE
+  *             - \ref SPIM_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref SDH1_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref I2C2_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref SPI3_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref CAN1_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref I2S0_MODULE
+  *             - \ref HSOTG_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref SPI4_MODULE
+  *             - \ref USCI0_MODULE
+  *             - \ref USCI1_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref EPWM0_MODULE
+  *             - \ref EPWM1_MODULE
+  *             - \ref BPWM0_MODULE
+  *             - \ref BPWM1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref QEI1_MODULE
+  *             - \ref ECAP0_MODULE
+  *             - \ref ECAP1_MODULE
+  *             - \ref OPA_MODULE
+  * @return     None
+  * @details    This function is used to enable module clock.
+  */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+    uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+    u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+    u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+    u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+    *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
+}
+
+/**
+  * @brief      Disable module clock
+  * @param[in]  u32ModuleIdx is module index. Including :
+  *             - \ref PDMA_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref EMAC_MODULE
+  *             - \ref SDH0_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref HSUSBD_MODULE
+  *             - \ref CRPT_MODULE
+  *             - \ref SPIM_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref SDH1_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref I2C2_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref SPI3_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref CAN1_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref I2S0_MODULE
+  *             - \ref HSOTG_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref SPI4_MODULE
+  *             - \ref USCI0_MODULE
+  *             - \ref USCI1_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref EPWM0_MODULE
+  *             - \ref EPWM1_MODULE
+  *             - \ref BPWM0_MODULE
+  *             - \ref BPWM1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref QEI1_MODULE
+  *             - \ref ECAP0_MODULE
+  *             - \ref ECAP1_MODULE
+  *             - \ref OPA_MODULE
+  * @return     None
+  * @details    This function is used to disable module clock.
+  */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+    uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+    u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+    u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+    u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+    *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+
+/**
+  * @brief      Set PLL frequency
+  * @param[in]  u32PllClkSrc is PLL clock source. Including :
+  *             - \ref CLK_PLLCTL_PLLSRC_HXT
+  *             - \ref CLK_PLLCTL_PLLSRC_HIRC
+  * @param[in]  u32PllFreq is PLL frequency.
+  * @return     PLL frequency
+  * @details    This function is used to configure PLLCTL register to set specified PLL frequency. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+    uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
+    uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
+
+    /* Disable PLL first to avoid unstable when setting PLL */
+    CLK_DisablePLL();
+
+    /* PLL source clock is from HXT */
+    if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
+        /* Enable HXT clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+
+        /* Wait for HXT clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+        /* Select PLL source clock from HXT */
+        u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
+        u32PllSrcClk = __HXT;
+
+        /* u32NR start from 2 */
+        u32NR = 2UL;
+    }
+
+    /* PLL source clock is from HIRC */
+    else {
+        /* Enable HIRC clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+
+        /* Wait for HIRC clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+        /* Select PLL source clock from HIRC */
+        u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
+        u32PllSrcClk = __HIRC;
+
+        /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
+        u32NR = 4UL;
+    }
+
+    if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) {
+
+        /* Find best solution */
+        u32Min = (uint32_t) - 1;
+        u32MinNR = 0UL;
+        u32MinNF = 0UL;
+        u32MinNO = 0UL;
+        u32basFreq = u32PllFreq;
+
+        for(u32NO = 1UL; u32NO <= 4UL; u32NO++) {
+            /* Break when get good results */
+            if (u32Min == 0UL) {
+                break;
+            }
+
+            if (u32NO != 3UL) {
+
+                if(u32NO == 4UL) {
+                    u32PllFreq = u32basFreq << 2;
+                } else if(u32NO == 2UL) {
+                    u32PllFreq = u32basFreq << 1;
+                } else {
+                }
+
+                for(u32NR = 2UL; u32NR <= 32UL; u32NR++) {
+                    /* Break when get good results */
+                    if (u32Min == 0UL) {
+                        break;
+                    }
+
+                    u32Tmp = u32PllSrcClk / u32NR;
+                    if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) {
+                        for(u32NF = 2UL; u32NF <= 513UL; u32NF++) {
+                            /* u32Tmp2 is shifted 2 bits to avoid overflow */
+                            u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
+
+                            if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) {
+                                u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
+                                if(u32Tmp3 < u32Min) {
+                                    u32Min = u32Tmp3;
+                                    u32MinNR = u32NR;
+                                    u32MinNF = u32NF;
+                                    u32MinNO = u32NO;
+
+                                    /* Break when get good results */
+                                    if(u32Min == 0UL) {
+                                        break;
+                                    }
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        /* Enable and apply new PLL setting. */
+        CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
+
+        /* Wait for PLL clock stable */
+        CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+        /* Actual PLL output clock frequency */
+        u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
+    } else {
+        /* Wrong frequency request. Just return default setting. */
+        /* Apply default PLL setting and return */
+        if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
+            CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
+        } else {
+            CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
+        }
+
+        /* Wait for PLL clock stable */
+        CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+        /* Actual PLL output clock frequency */
+        u32PllClk = CLK_GetPLLClockFreq();
+    }
+
+    return u32PllClk;
+}
+
+/**
+  * @brief      Disable PLL
+  * @param      None
+  * @return     None
+  * @details    This function set PLL in Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisablePLL(void)
+{
+    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+
+/**
+  * @brief      This function check selected clock source status
+  * @param[in]  u32ClkMask is selected clock source. Including :
+  *             - \ref CLK_STATUS_HXTSTB_Msk
+  *             - \ref CLK_STATUS_LXTSTB_Msk
+  *             - \ref CLK_STATUS_HIRCSTB_Msk
+  *             - \ref CLK_STATUS_LIRCSTB_Msk
+  *             - \ref CLK_STATUS_PLLSTB_Msk
+  * @retval     0  clock is not stable
+  * @retval     1  clock is stable
+  * @details    To wait for clock ready by specified clock source stable flag or timeout (~300ms)
+  */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+    int32_t i32TimeOutCnt = 2160000;
+    uint32_t u32Ret = 1U;
+
+    while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
+        if(i32TimeOutCnt-- <= 0) {
+            u32Ret = 0U;
+            break;
+        }
+    }
+    return u32Ret;
+}
+
+/**
+  * @brief      Enable System Tick counter
+  * @param[in]  u32ClkSrc is System Tick clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+  * @param[in]  u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+  * @return     None
+  * @details    This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+    /* Set System Tick counter disabled */
+    SysTick->CTRL = 0UL;
+
+    /* Set System Tick clock source */
+    if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) {
+        SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+    } else {
+        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+    }
+
+    /* Set System Tick reload value */
+    SysTick->LOAD = u32Count;
+
+    /* Clear System Tick current value and counter flag */
+    SysTick->VAL = 0UL;
+
+    /* Set System Tick interrupt enabled and counter enabled */
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+  * @brief      Disable System Tick counter
+  * @param      None
+  * @return     None
+  * @details    This function disable System Tick counter.
+  */
+void CLK_DisableSysTick(void)
+{
+    /* Set System Tick counter disabled */
+    SysTick->CTRL = 0UL;
+}
+
+
+/**
+  * @brief      Power-down mode selected
+  * @param[in]  u32PDMode is power down mode index. Including :
+  *             - \ref CLK_PMUCTL_PDMSEL_PD
+  *             - \ref CLK_PMUCTL_PDMSEL_LLPD
+  *             - \ref CLK_PMUCTL_PDMSEL_FWPD
+  *             - \ref CLK_PMUCTL_PDMSEL_SPD0
+  *             - \ref CLK_PMUCTL_PDMSEL_SPD1
+  *             - \ref CLK_PMUCTL_PDMSEL_DPD
+  * @return     None
+  * @details    This function is used to set power-down mode.
+  * @note       Must enable LIRC clock before entering to Standby Power-down Mode
+  */
+
+void CLK_SetPowerDownMode(uint32_t u32PDMode)
+{
+    /* Enable LIRC clock before entering to Standby Power-down Mode */
+    if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) {
+        /* Enable LIRC clock */
+        CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
+
+        /* Wait for LIRC clock stable */
+        CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+    }
+
+    CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
+}
+
+/**
+ * @brief       Set Wake-up pin trigger type at Deep Power down mode
+ *
+ * @param[in]   u32TriggerType
+ *              - \ref CLK_DPDWKPIN_RISING
+ *              - \ref CLK_DPDWKPIN_FALLING
+ *              - \ref CLK_DPDWKPIN_BOTHEDGE
+ * @return      None
+ *
+ * @details     This function is used to enable Wake-up pin trigger type.
+ */
+
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
+{
+    CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
+}
+
+/**
+ * @brief      Get power manager wake up source
+ *
+ * @param[in]   None
+ * @return      None
+ *
+ * @details     This function get power manager wake up source.
+ */
+
+uint32_t CLK_GetPMUWKSrc(void)
+{
+    return (CLK->PMUSTS);
+}
+
+/**
+ * @brief       Set specified GPIO as wake up source at Stand-by Power down mode
+ *
+ * @param[in]   u32Port GPIO port. It could be 0~3.
+ * @param[in]   u32Pin  The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in]   u32TriggerType
+ *              - \ref CLK_SPDWKPIN_RISING
+ *              - \ref CLK_SPDWKPIN_FALLING
+ * @param[in]   u32DebounceEn
+ *              - \ref CLK_SPDWKPIN_DEBOUNCEEN
+ *              - \ref CLK_SPDWKPIN_DEBOUNCEDIS
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO as wake up source
+ *              at Stand-by Power down mode.
+ */
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
+{
+    uint32_t u32tmpAddr = 0UL;
+    uint32_t u32tmpVal = 0UL;
+
+    /* GPx Stand-by Power-down Wake-up Pin Select */
+    u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
+    u32tmpAddr += (0x4UL * u32Port);
+
+    u32tmpVal = inpw((uint32_t *)u32tmpAddr);
+    u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
+                (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
+    outpw((uint32_t *)u32tmpAddr, u32tmpVal);
+}
+
+/*@}*/ /* end of group M480_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CLK_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_clk.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,612 @@
+/**************************************************************************//**
+ * @file     CLK.h
+ * @version  V1.0
+ * @brief    M480 Series CLK Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CLK_Driver CLK Driver
+  @{
+*/
+
+/** @addtogroup M480_CLK_EXPORTED_CONSTANTS CLK Exported Constants
+  @{
+*/
+
+
+#define FREQ_25MHZ         25000000UL   /*!< 25 MHz \hideinitializer */
+#define FREQ_50MHZ         50000000UL   /*!< 50 MHz \hideinitializer */
+#define FREQ_72MHZ         72000000UL   /*!< 72 MHz \hideinitializer */
+#define FREQ_80MHZ         80000000UL   /*!< 80 MHz \hideinitializer */
+#define FREQ_100MHZ        100000000UL  /*!< 100 MHz \hideinitializer */
+#define FREQ_125MHZ        125000000UL  /*!< 125 MHz \hideinitializer */
+#define FREQ_160MHZ        160000000UL  /*!< 160 MHz \hideinitializer */
+#define FREQ_192MHZ        192000000UL  /*!< 192 MHz \hideinitializer */
+#define FREQ_200MHZ        200000000UL  /*!< 200 MHz \hideinitializer */
+#define FREQ_250MHZ        250000000UL  /*!< 250 MHz \hideinitializer */
+#define FREQ_500MHZ        500000000UL  /*!< 500 MHz \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL0 constant definitions.  (Write-protection)                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT          (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LXT          (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_PLL          (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LIRC         (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_HIRC         (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL0_STCLKSEL_HXT         (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_LXT         (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2    (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HXT/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK        (0x01UL << SysTick_CTRL_CLKSOURCE_Pos)     /*!< Select SysTick clock source from HCLK \hideinitializer */
+
+#if(0)
+#define CLK_CLKSEL0_PCLK0DIV1            (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos)        /*!< Select PCLK0 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK0DIV2            (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos)        /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_PCLK1DIV1            (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos)        /*!< Select PCLK1 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK1DIV2            (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos)        /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */
+#endif
+
+#define CLK_CLKSEL0_SDH0SEL_HXT          (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_PLL          (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HIRC         (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HCLK         (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_SDH1SEL_HXT          (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_PLL          (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HIRC         (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HCLK         (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from HCLK \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL1 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL1_WDTSEL_LXT           (0x1UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_LIRC          (0x3UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048  (0x2UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
+
+#define CLK_CLKSEL1_TMR0SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_PCLK0        (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR1SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_PCLK0        (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR2SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_PCLK1        (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR3SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_PCLK1        (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_UART0SEL_HXT         (0x0UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_LXT         (0x2UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_PLL         (0x1UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_HIRC        (0x3UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_UART1SEL_HXT         (0x0UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_LXT         (0x2UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_PLL         (0x1UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_HIRC        (0x3UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_CLKOSEL_HXT          (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_LXT          (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HIRC         (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HCLK         (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL1_WWDTSEL_LIRC         (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos)         /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos)         /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL2 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL2_SPI0SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PLL          (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PCLK0        (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI1SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PLL          (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PCLK1        (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI2SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos)         /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PLL          (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos)         /*!< Select SPI2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos)         /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PCLK0        (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos)         /*!< Select SPI2 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM0SEL_PLL         (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos)        /*!< Select EPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM0SEL_PCLK0       (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos)        /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM1SEL_PLL         (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos)        /*!< Select EPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM1SEL_PCLK1       (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos)        /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM0SEL_PLL         (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos)        /*!< Select BPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM0SEL_PCLK0       (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos)        /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM1SEL_PLL         (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos)        /*!< Select BPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM1SEL_PCLK1       (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos)        /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI3SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos)         /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PLL          (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos)         /*!< Select SPI3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos)         /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PCLK1        (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos)         /*!< Select SPI3 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI4SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI4SEL_Pos)         /*!< Select SPI4 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI4SEL_PLL          (0x1UL << CLK_CLKSEL2_SPI4SEL_Pos)         /*!< Select SPI4 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI4SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI4SEL_Pos)         /*!< Select SPI4 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI4SEL_PCLK0        (0x2UL << CLK_CLKSEL2_SPI4SEL_Pos)         /*!< Select SPI4 clock source from PCLK0 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL3 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL3_SC0SEL_HXT           (0x0UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PLL           (0x1UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PCLK0         (0x2UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_SC1SEL_HXT           (0x0UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PLL           (0x1UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PCLK1         (0x2UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL3_SC2SEL_HXT           (0x0UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PLL           (0x1UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PCLK0         (0x2UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_RTCSEL_LXT           (0x0UL << CLK_CLKSEL3_RTCSEL_Pos)          /*!< Select RTC clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_RTCSEL_LIRC          (0x1UL << CLK_CLKSEL3_RTCSEL_Pos)          /*!< Select RTC clock source from low speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_I2S0SEL_HXT          (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PLL          (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_HIRC         (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PCLK0        (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_UART2SEL_HXT         (0x0UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_LXT         (0x2UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_PLL         (0x1UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART3SEL_HXT         (0x0UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_LXT         (0x2UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_PLL         (0x1UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART4SEL_HXT         (0x0UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_LXT         (0x2UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_PLL         (0x1UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART5SEL_HXT         (0x0UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_LXT         (0x2UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_PLL         (0x1UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV0 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV0_HCLK(x)              (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos)   /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_USB(x)               (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos)    /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_SDH0(x)              (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos)   /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV0_UART0(x)             (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos)  /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_UART1(x)             (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos)  /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_EADC(x)              (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos)   /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV1 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV1_SC0(x)               (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos)    /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC1(x)               (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos)    /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC2(x)               (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos)    /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV3 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV3_EMAC(x)              (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos)   /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV3_SDH1(x)              (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos)   /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV4 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV4_UART2(x)             (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos)  /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART3(x)             (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos)  /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART4(x)             (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos)  /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART5(x)             (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos)  /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  PCLKDIV constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#if(1)
+#define CLK_PCLKDIV_PCLK0DIV1            (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV2            (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV4            (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV8            (0x3UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV16           (0x4UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV1            (0x0UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV2            (0x1UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV4            (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV8            (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV16           (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
+#endif
+/*---------------------------------------------------------------------------------------------------------*/
+/*  PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PLLCTL_PLLSRC_HXT   0x00000000UL    /*!< For PLL clock source is HXT.  4MHz < FIN/NR < 8MHz \hideinitializer */
+#define CLK_PLLCTL_PLLSRC_HIRC  0x00080000UL    /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NF(x)        (((x)-2UL))       /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
+#define CLK_PLLCTL_NR(x)        (((x)-1UL)<<9)    /*!< x must be constant and 1 <= x <= 32.  4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NO_1         0x0000UL        /*!< For output divider is 1 \hideinitializer */
+#define CLK_PLLCTL_NO_2         0x4000UL        /*!< For output divider is 2 \hideinitializer */
+#define CLK_PLLCTL_NO_4         0xC000UL        /*!< For output divider is 4 \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HXT    (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HXT    (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  MODULE constant definitions.                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
+
+#define MODULE_APBCLK(x)        (((x) >>30) & 0x3UL)    /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL(x)        (((x) >>28) & 0x3UL)    /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk(x)    (((x) >>25) & 0x7UL)    /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos(x)    (((x) >>20) & 0x1fUL)   /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV(x)        (((x) >>18) & 0x3UL)    /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk(x)    (((x) >>10) & 0xffUL)   /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos(x)    (((x) >>5 ) & 0x1fUL)   /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos(x)     (((x) >>0 ) & 0x1fUL)   /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
+#define MODULE_NoMsk            0x0UL                   /*!< Not mask on MODULE index \hideinitializer */
+#define NA                      MODULE_NoMsk            /*!< Not Available \hideinitializer */
+
+#define MODULE_APBCLK_ENC(x)        (((x) & 0x03UL) << 30)   /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL_ENC(x)        (((x) & 0x03UL) << 28)   /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk_ENC(x)    (((x) & 0x07UL) << 25)   /*!< CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos_ENC(x)    (((x) & 0x1fUL) << 20)   /*!< CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_ENC(x)        (((x) & 0x03UL) << 18)   /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk_ENC(x)    (((x) & 0xffUL) << 10)   /*!< CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos_ENC(x)    (((x) & 0x1fUL) <<  5)   /*!< CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos_ENC(x)     (((x) & 0x1fUL) <<  0)   /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
+
+#define PDMA_MODULE      ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0))  /*!< PDMA Module \hideinitializer */
+#define ISP_MODULE       ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0))  /*!< ISP Module \hideinitializer */
+#define EBI_MODULE       ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0))  /*!< EBI Module \hideinitializer */
+#define USBH_MODULE      ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */
+#define EMAC_MODULE      ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18)         |(0xFFUL<<10)      |(16UL<<5)        |(5UL<<0))  /*!< EMAC Module \hideinitializer */
+#define SDH0_MODULE      ((0UL<<30)|(0UL<<28)         |(0x3UL<<25)       |(20UL<<20)        |(0UL<<18)         |(0xFFUL<<10)      |(24UL<<5)        |(6UL<<0))  /*!< SDH0 Module \hideinitializer */
+#define CRC_MODULE       ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0))  /*!< CRC Module \hideinitializer */
+#define HSUSBD_MODULE    ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */
+#define CRPT_MODULE      ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */
+#define SPIM_MODULE      ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */
+#define SDH1_MODULE      ((0UL<<30)|(0UL<<28)         |(0x3UL<<25)       |(22UL<<20)        |(2UL<<18)         |(0xFFUL<<10)      |(24UL<<5)        |(17UL<<0)) /*!< SDH1 Module \hideinitializer */
+#define WDT_MODULE       ((1UL<<30)|(1UL<<28)         |(0x3UL<<25)       |(0UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0))  /*!< WDT Module \hideinitializer */
+#define RTC_MODULE       ((1UL<<30)|(3UL<<28)         |(0x1UL<<25)       |(8UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0))  /*!< RTC Module \hideinitializer */
+#define TMR0_MODULE      ((1UL<<30)|(1UL<<28)         |(0x7UL<<25)       |(8UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0))  /*!< TMR0 Module \hideinitializer */
+#define TMR1_MODULE      ((1UL<<30)|(1UL<<28)         |(0x7UL<<25)       |(12UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0))  /*!< TMR1 Module \hideinitializer */
+#define TMR2_MODULE      ((1UL<<30)|(1UL<<28)         |(0x7UL<<25)       |(16UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0))  /*!< TMR2 Module \hideinitializer */
+#define TMR3_MODULE      ((1UL<<30)|(1UL<<28)         |(0x7UL<<25)       |(20UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0))  /*!< TMR3 Module \hideinitializer */
+#define CLKO_MODULE      ((1UL<<30)|(1UL<<28)         |(0x3UL<<25)       |(28UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0))  /*!< CLKO Module \hideinitializer */
+#define WWDT_MODULE      ((1UL<<30)|(1UL<<28)         |(0x3UL<<25)       |(30UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0))  /*!< WWDT Module \hideinitializer */
+#define ACMP01_MODULE    ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0))  /*!< ACMP01 Module \hideinitializer */
+#define I2C0_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0))  /*!< I2C0 Module \hideinitializer */
+#define I2C1_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0))  /*!< I2C1 Module \hideinitializer */
+#define I2C2_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */
+#define SPI0_MODULE      ((1UL<<30)|(2UL<<28)         |(0x3UL<<25)       |(2UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< SPI0 Module \hideinitializer */
+#define SPI1_MODULE      ((1UL<<30)|(2UL<<28)         |(0x3UL<<25)       |(4UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI1 Module \hideinitializer */
+#define SPI2_MODULE      ((1UL<<30)|(2UL<<28)         |(0x3UL<<25)       |(6UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI2 Module \hideinitializer */
+#define SPI3_MODULE      ((1UL<<30)|(2UL<<28)         |(0x3UL<<25)       |(10UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI3 Module \hideinitializer */
+#define UART0_MODULE     ((1UL<<30)|(1UL<<28)         |(0x3UL<<25)       |(24UL<<20)        |(0UL<<18)         |(0xFUL<<10)       |(8UL<<5)         |(16UL<<0)) /*!< UART0 Module \hideinitializer */
+#define UART1_MODULE     ((1UL<<30)|(1UL<<28)         |(0x3UL<<25)       |(26UL<<20)        |(0UL<<18)         |(0xFUL<<10)       |(12UL<<5)        |(17UL<<0)) /*!< UART1 Module \hideinitializer */
+#define UART2_MODULE     ((1UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(24UL<<20)        |(3UL<<18)         |(0xFUL<<10)       |(0UL<<5)         |(18UL<<0)) /*!< UART2 Module \hideinitializer */
+#define UART3_MODULE     ((1UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(26UL<<20)        |(3UL<<18)         |(0xFUL<<10)       |(4UL<<5)         |(19UL<<0)) /*!< UART3 Module \hideinitializer */
+#define UART4_MODULE     ((1UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(28UL<<20)        |(3UL<<18)         |(0xFUL<<10)       |(8UL<<5)         |(20UL<<0)) /*!< UART4 Module \hideinitializer */
+#define UART5_MODULE     ((1UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(30UL<<20)        |(3UL<<18)         |(0xFUL<<10)       |(12UL<<5)        |(21UL<<0)) /*!< UART5 Module \hideinitializer */
+#define CAN0_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */
+#define CAN1_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */
+#define OTG_MODULE       ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */
+#define USBD_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */
+#define EADC_MODULE      ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18)         |(0xFFUL<<10)      |(16UL<<5)        |(28UL<<0)) /*!< EADC Module \hideinitializer */
+#define I2S0_MODULE      ((1UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(16UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< I2S0 Module \hideinitializer */
+#define HSOTG_MODULE     ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */
+#define SC0_MODULE       ((2UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(0UL<<20)         |(1UL<<18)         |(0xFFUL<<10)      |(0UL<<5)         |(0UL<<0))  /*!< SC0 Module \hideinitializer */
+#define SC1_MODULE       ((2UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(2UL<<20)         |(1UL<<18)         |(0xFFUL<<10)      |(8UL<<5)         |(1UL<<0))  /*!< SC1 Module \hideinitializer */
+#define SC2_MODULE       ((2UL<<30)|(3UL<<28)         |(0x3UL<<25)       |(4UL<<20)         |(1UL<<18)         |(0xFFUL<<10)      |(16UL<<5)        |(2UL<<0))  /*!< SC2 Module \hideinitializer */
+#define SPI4_MODULE      ((2UL<<30)|(2UL<<28)         |(0x3UL<<25)       |(12UL<<20)        |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0))  /*!< SPI4 Module \hideinitializer */
+#define USCI0_MODULE     ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0))  /*!< USCI0 Module \hideinitializer */
+#define USCI1_MODULE     ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0))  /*!< USCI1 Module \hideinitializer */
+#define DAC_MODULE       ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */
+#define EPWM0_MODULE     ((2UL<<30)|(2UL<<28)         |(0x1UL<<25)       |(0UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */
+#define EPWM1_MODULE     ((2UL<<30)|(2UL<<28)         |(0x1UL<<25)       |(1UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */
+#define BPWM0_MODULE     ((2UL<<30)|(2UL<<28)         |(0x1UL<<25)       |(8UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */
+#define BPWM1_MODULE     ((2UL<<30)|(2UL<<28)         |(0x1UL<<25)       |(9UL<<20)         |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */
+#define QEI0_MODULE      ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */
+#define QEI1_MODULE      ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */
+#define ECAP0_MODULE     ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */
+#define ECAP1_MODULE     ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */
+#define OPA_MODULE       ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  PDMSEL constant definitions.                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_PDMSEL_PD          (0x0UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_LLPD        (0x1UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Low leakage Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_FWPD        (0x2UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Fast wake-up Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD0        (0x4UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Standby Power-down mode 0 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD1        (0x5UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Standby Power-down mode 1 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_DPD         (0x6UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mdoe is Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WKTMRIS constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_WKTMRIS_128          (0x0UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_256          (0x1UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_512          (0x2UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_1024         (0x3UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_4096         (0x4UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_8192         (0x5UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_16384        (0x6UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_65536        (0x7UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  SWKDBCLKSEL constant definitions.                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SWKDBCTL_SWKDBCLKSEL_1          (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2          (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4          (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8          (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16         (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32         (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64         (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128        (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_256        (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256      (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256      (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256      (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256     (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256     (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256     (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256    (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_DPDWKPIN_DISABLE     (0x0UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_RISING      (0x1UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_FALLING     (0x2UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_BOTHEDGE    (0x3UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  SPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SPDWKPIN_ENABLE         (0x1UL << 0)     /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
+#define CLK_SPDWKPIN_RISING         (0x1UL << 1)     /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
+#define CLK_SPDWKPIN_FALLING        (0x1UL << 2)     /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEEN     (0x1UL << 8)     /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEDIS    (0x0UL << 8)     /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
+
+#define CLK_DISABLE_WKTMR(void)       (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk)    /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_WKTMR(void)        (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk)     /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN(void)    (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk)    /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_SPDACMP(void)     (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk)   /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_ENABLE_SPDACMP(void)      (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk)    /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_DISABLE_RTCWK(void)       (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk)    /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_RTCWK(void)        (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk)     /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+
+/*@}*/ /* end of group M480_CLK_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set Wake-up Timer Time-out Interval
+ *
+ * @param[in]   u32Interval   The de-bounce sampling cycle selection. It could be
+ *                             - \ref CLK_PMUCTL_WKTMRIS_128
+ *                             - \ref CLK_PMUCTL_WKTMRIS_256
+ *                             - \ref CLK_PMUCTL_WKTMRIS_512
+ *                             - \ref CLK_PMUCTL_WKTMRIS_1024
+ *                             - \ref CLK_PMUCTL_WKTMRIS_4096
+ *                             - \ref CLK_PMUCTL_WKTMRIS_8192
+ *                             - \ref CLK_PMUCTL_WKTMRIS_16384
+ *                             - \ref CLK_PMUCTL_WKTMRIS_65536
+ *
+ * @return      None
+ *
+ * @details     This function set Wake-up Timer Time-out Interval.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_WKTMR_INTERVAL(u32Interval)   (CLK->PMUCTL |= (u32Interval))
+
+/**
+ * @brief       Set De-bounce Sampling Cycle Time
+ *
+ * @param[in]   u32CycleSel   The de-bounce sampling cycle selection. It could be
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
+ *
+ * @return      None
+ *
+ * @details     This function set Set De-bounce Sampling Cycle Time.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel)    (CLK->SWKDBCTL = (u32CycleSel))
+
+
+
+
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE uint32_t CLK_GetPLLClockFreq(void);
+static __INLINE void CLK_SysTickDelay(uint32_t us);
+
+/**
+  * @brief      Get PLL clock frequency
+  * @param      None
+  * @return     PLL frequency
+  * @details    This function get PLL frequency. The frequency unit is Hz.
+  */
+__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
+{
+    uint32_t u32PllFreq = 0UL, u32PllReg;
+    uint32_t u32FIN, u32NF, u32NR, u32NO;
+    uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
+
+    u32PllReg = CLK->PLLCTL;
+
+    if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) {		
+        u32PllFreq = 0UL;           /* PLL is in power down mode or fix low */
+    } else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) {
+        if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
+            u32FIN = __HIRC;    /* PLL source clock from HIRC */
+        } else {
+            u32FIN = __HXT;     /* PLL source clock from HXT */
+        }
+
+        u32PllFreq = u32FIN;
+    } else {
+        if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
+            u32FIN = __HIRC;    /* PLL source clock from HIRC */
+        } else {
+            u32FIN = __HXT;     /* PLL source clock from HXT */
+        }
+        /* PLL is output enabled in normal work mode */
+        u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+        u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
+        u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
+
+        /* u32FIN is shifted 2 bits to avoid overflow */
+        u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
+    }
+
+    return u32PllFreq;
+}
+
+/**
+  * @brief      This function execute delay function.
+  * @param      us  Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+  *                             72MHz => 233016us, 50MHz => 335544us,
+  *                             48MHz => 349525us, 28MHz => 699050us ...
+  * @return     None
+  * @details    Use the SysTick to generate the delay time and the unit is in us.
+  *             The SysTick clock source is from HCLK, i.e the same as system core clock.
+  */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+    SysTick->LOAD = us * CyclesPerUs;
+    SysTick->VAL  = 0x0UL;
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+    /* Waiting for down-count to zero */
+    while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) {
+    }
+
+    /* Disable SysTick counter */
+    SysTick->CTRL = 0UL;
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+void CLK_SetPowerDownMode(uint32_t u32PDMode);
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
+uint32_t CLK_GetPMUWKSrc(void);
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
+void CLK_SetUSBModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+
+/*@}*/ /* end of group M480_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CLK_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __CLK_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,93 @@
+/**************************************************************************//**
+ * @file     crc.c
+ * @version  V1.00
+ * @brief     M480 CRC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include  "M480.h"
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup M480_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      CRC Open
+  *
+  * @param[in]  u32Mode         CRC operation polynomial mode. Valid values are:
+  *                             - \ref CRC_CCITT
+  *                             - \ref CRC_8
+  *                             - \ref CRC_16
+  *                             - \ref CRC_32
+  * @param[in]  u32Attribute    CRC operation data attribute. Valid values are combined with:
+  *                             - \ref CRC_CHECKSUM_COM
+  *                             - \ref CRC_CHECKSUM_RVS
+  *                             - \ref CRC_WDATA_COM
+  *                             - \ref CRC_WDATA_RVS
+  * @param[in]  u32Seed         Seed value.
+  * @param[in]  u32DataLen      CPU Write Data Length. Valid values are:
+  *                             - \ref CRC_CPU_WDATA_8
+  *                             - \ref CRC_CPU_WDATA_16
+  *                             - \ref CRC_CPU_WDATA_32
+  *
+  * @return     None
+  *
+  * @details    This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
+  *             After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
+  */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+    CRC->SEED = u32Seed;
+    CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
+
+    /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */
+    CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
+}
+
+/**
+  * @brief      Get CRC Checksum
+  *
+  * @param[in]  None
+  *
+  * @return     Checksum Result
+  *
+  * @details    This macro gets the CRC checksum result by current CRC polynomial mode.
+  */
+uint32_t CRC_GetChecksum(void)
+{
+    uint32_t ret;
+
+    switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) {
+    case CRC_CCITT:
+    case CRC_16:
+        ret = (CRC->CHECKSUM & 0xFFFFU);
+        break;
+    case CRC_32:
+        ret = (CRC->CHECKSUM);
+        break;
+    case CRC_8:
+        ret = (CRC->CHECKSUM & 0xFFU);
+        break;
+    default:
+        ret = 0U;
+        break;
+    }
+
+    return ret;
+}
+
+/*@}*/ /* end of group M480_CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CRC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,112 @@
+/**************************************************************************//**
+ * @file     crc.h
+ * @version  V1.00
+ * @brief    M480 series CRC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup M480_CRC_EXPORTED_CONSTANTS CRC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CRC Polynomial Mode Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT           (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
+#define CRC_8               (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
+#define CRC_16              (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
+#define CRC_32              (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Checksum, Write data Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CHECKSUM_COM    (CRC_CTL_CHKSFMT_Msk)       /*!<CRC Checksum Complement \hideinitializer */
+#define CRC_CHECKSUM_RVS    (CRC_CTL_CHKSREV_Msk)       /*!<CRC Checksum Reverse \hideinitializer */
+#define CRC_WDATA_COM       (CRC_CTL_DATFMT_Msk)        /*!<CRC Write Data Complement \hideinitializer */
+#define CRC_WDATA_RVS       (CRC_CTL_DATREV_Msk)        /*!<CRC Write Data Reverse \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CPU Write Data Length Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CPU_WDATA_8     (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 8-bit \hideinitializer */
+#define CRC_CPU_WDATA_16    (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 16-bit \hideinitializer */
+#define CRC_CPU_WDATA_32    (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 32-bit \hideinitializer */
+
+/*@}*/ /* end of group M480_CRC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set CRC Seed Value
+  *
+  * @param[in]  u32Seed     Seed value
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set CRC seed value.
+  *
+  * @note       User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
+  *             to CRC controller.
+  * \hideinitializer
+  */
+#define CRC_SET_SEED(u32Seed)   do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
+
+/**
+ * @brief       Get CRC Seed Value
+ *
+  * @param      None
+ *
+ * @return      CRC seed value
+ *
+ * @details     This macro gets the current CRC seed value.
+ * \hideinitializer
+ */
+#define CRC_GET_SEED()          (CRC->SEED)
+
+/**
+ * @brief       CRC Write Data
+ *
+ * @param[in]   u32Data     Write data
+ *
+ * @return      None
+ *
+ * @details    User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ * \hideinitializer
+ */
+#define CRC_WRITE_DATA(u32Data)   (CRC->DAT = (u32Data))
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/*@}*/ /* end of group M480_CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CRC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crypto.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1641 @@
+/**************************************************************************//**
+ * @file     crypto.c
+ * @version  V1.10
+ * @brief  Cryptographic Accelerator driver source file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include "M480.h"
+
+/** @cond HIDDEN_SYMBOLS */
+
+#define ENABLE_DEBUG    0
+
+#if ENABLE_DEBUG
+#define CRPT_DBGMSG   printf
+#else
+#define CRPT_DBGMSG(...)   do { } while (0)       /* disable debug */
+#endif
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+
+/** @addtogroup M480_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+static uint32_t g_AES_CTL[4];
+static uint32_t g_TDES_CTL[4];
+
+static char  hex_char_tbl[] = "0123456789abcdef";
+
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count);
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx);
+static void Hex2Reg(char input[], uint32_t volatile reg[]);
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift);
+static char ch2hex(char ch);
+static int  get_nibble_value(char c);
+
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief  Open PRNG function
+  * @param[in]  u32KeySize is PRNG key size, including:
+  *         - \ref PRNG_KEY_SIZE_64
+  *         - \ref PRNG_KEY_SIZE_128
+  *         - \ref PRNG_KEY_SIZE_192
+  *         - \ref PRNG_KEY_SIZE_256
+  * @param[in]  u32SeedReload is PRNG seed reload or not, including:
+  *         - \ref PRNG_SEED_CONT
+  *         - \ref PRNG_SEED_RELOAD
+  * @param[in]  u32Seed  The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
+  * @return None
+  */
+void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
+{
+    if (u32SeedReload) {
+        CRPT->PRNG_SEED = u32Seed;
+    }
+
+    CRPT->PRNG_CTL =  (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                      (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
+}
+
+/**
+  * @brief  Start to generate one PRNG key.
+  * @return None
+  */
+void PRNG_Start(void)
+{
+    CRPT->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
+}
+
+/**
+  * @brief  Read the PRNG key.
+  * @param[out]  u32RandKey  The key buffer to store newly generated PRNG key.
+  * @return None
+  */
+void PRNG_Read(uint32_t u32RandKey[])
+{
+    uint32_t  i, wcnt;
+
+    wcnt = (((CRPT->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;
+
+    for (i = 0U; i < wcnt; i++) {
+        u32RandKey[i] = CRPT->PRNG_KEY[i];
+    }
+
+    CRPT->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;
+}
+
+
+/**
+  * @brief  Open AES encrypt/decrypt function.
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32EncDec    1: AES encode;  0: AES decode
+  * @param[in]  u32OpMode    AES operation mode, including:
+  *         - \ref AES_MODE_ECB
+  *         - \ref AES_MODE_CBC
+  *         - \ref AES_MODE_CFB
+  *         - \ref AES_MODE_OFB
+  *         - \ref AES_MODE_CTR
+  *         - \ref AES_MODE_CBC_CS1
+  *         - \ref AES_MODE_CBC_CS2
+  *         - \ref AES_MODE_CBC_CS3
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @param[in]  u32SwapType is AES input/output data swap control, including:
+  *         - \ref AES_NO_SWAP
+  *         - \ref AES_OUT_SWAP
+  *         - \ref AES_IN_SWAP
+  *         - \ref AES_IN_OUT_SWAP
+  * @return None
+  */
+void AES_Open(uint32_t u32Channel, uint32_t u32EncDec,
+              uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
+{
+    CRPT->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) |
+                    (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |
+                    (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
+                    (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
+                    (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
+    g_AES_CTL[u32Channel] = CRPT->AES_CTL;
+}
+
+/**
+  * @brief  Start AES encrypt/decrypt
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  u32DMAMode  AES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last AES encrypt/decrypt of a series of AES_Start.
+  * @return None
+  */
+void AES_Start(int32_t u32Channel, uint32_t u32DMAMode)
+{
+    CRPT->AES_CTL = g_AES_CTL[u32Channel];
+    CRPT->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set AES keys
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32Keys    An word array contains AES keys.
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @return None
+  */
+void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
+{
+    uint32_t  i, wcnt, key_reg_addr;
+
+    key_reg_addr = (uint32_t)&CRPT->AES0_KEY[0] + (u32Channel * 0x3CUL);
+    wcnt = 4UL + u32KeySize*2UL;
+
+    for (i = 0U; i < wcnt; i++) {
+        outpw(key_reg_addr, au32Keys[i]);
+        key_reg_addr += 4UL;
+    }
+}
+
+/**
+  * @brief  Set AES initial vectors
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32IV      A four entry word array contains AES initial vectors.
+  * @return None
+  */
+void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[])
+{
+    uint32_t  i, key_reg_addr;
+
+    key_reg_addr = (uint32_t)&CRPT->AES0_IV[0] + (u32Channel * 0x3CUL);
+
+    for (i = 0U; i < 4U; i++) {
+        outpw(key_reg_addr, au32IV[i]);
+        key_reg_addr += 4UL;
+    }
+}
+
+/**
+  * @brief  Set AES DMA transfer configuration.
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32SrcAddr   AES DMA source address
+  * @param[in]  u32DstAddr   AES DMA destination address
+  * @param[in]  u32TransCnt  AES DMA transfer byte count
+  * @return None
+  */
+void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
+                        uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32SrcAddr);
+
+    reg_addr = (uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32DstAddr);
+
+    reg_addr = (uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3CUL);
+    outpw(reg_addr, u32TransCnt);
+}
+
+/**
+  * @brief  Open TDES encrypt/decrypt function.
+  * @param[in]  u32Channel   TDES channel. Must be 0~3.
+  * @param[in]  u32EncDec    1: TDES encode; 0: TDES decode
+  * @param[in]  Is3DES       1: TDES; 0: DES
+  * @param[in]  Is3Key       1: TDES 3 key mode; 0: TDES 2 key mode
+  * @param[in]  u32OpMode    TDES operation mode, including:
+  *         - \ref TDES_MODE_ECB
+  *         - \ref TDES_MODE_CBC
+  *         - \ref TDES_MODE_CFB
+  *         - \ref TDES_MODE_OFB
+  *         - \ref TDES_MODE_CTR
+  * @param[in]  u32SwapType is TDES input/output data swap control and word swap control, including:
+  *         - \ref TDES_NO_SWAP
+  *         - \ref TDES_WHL_SWAP
+  *         - \ref TDES_OUT_SWAP
+  *         - \ref TDES_OUT_WHL_SWAP
+  *         - \ref TDES_IN_SWAP
+  *         - \ref TDES_IN_WHL_SWAP
+  *         - \ref TDES_IN_OUT_SWAP
+  *         - \ref TDES_IN_OUT_WHL_SWAP
+  * @return None
+  */
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key,
+               uint32_t u32OpMode, uint32_t u32SwapType)
+{
+    g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |
+                             (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |
+                             u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
+    if (Is3DES) {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk;
+    }
+    if (Is3Key) {
+        g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk;
+    }
+}
+
+/**
+  * @brief  Start TDES encrypt/decrypt
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  u32DMAMode  TDES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop TDES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous TDES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last TDES encrypt/decrypt of a series of TDES_Start.
+  * @return None
+  */
+void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode)
+{
+    g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos);
+    CRPT->TDES_CTL = g_TDES_CTL[u32Channel];
+}
+
+/**
+  * @brief  Set TDES keys
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  au32Keys    The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word.
+  * @return None
+  */
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2])
+{
+    uint32_t   i, reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_KEY1H + (0x40UL * u32Channel);
+
+    for (i = 0U; i < 3U; i++) {
+        outpw(reg_addr, au32Keys[i][0]);   /* TDESn_KEYxH */
+        reg_addr += 4UL;
+        outpw(reg_addr, au32Keys[i][1]);   /* TDESn_KEYxL */
+        reg_addr += 4UL;
+    }
+}
+
+/**
+  * @brief  Set TDES initial vectors
+  * @param[in]  u32Channel  TDES channel. Must be 0~3.
+  * @param[in]  u32IVH      TDES initial vector high word.
+  * @param[in]  u32IVL      TDES initial vector low word.
+  * @return None
+  */
+void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)
+{
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_IVH + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32IVH);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_IVL + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32IVL);
+}
+
+/**
+  * @brief  Set TDES DMA transfer configuration.
+  * @param[in]  u32Channel   TDES channel. Must be 0~3.
+  * @param[in]  u32SrcAddr   TDES DMA source address
+  * @param[in]  u32DstAddr   TDES DMA destination address
+  * @param[in]  u32TransCnt  TDES DMA transfer byte count
+  * @return None
+  */
+void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
+                         uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+    uint32_t  reg_addr;
+
+    reg_addr = (uint32_t)&CRPT->TDES0_SA + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32SrcAddr);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_DA + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32DstAddr);
+
+    reg_addr = (uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40UL);
+    outpw(reg_addr, u32TransCnt);
+}
+
+/**
+  * @brief  Open SHA encrypt function.
+  * @param[in]  u32OpMode   SHA operation mode, including:
+  *         - \ref SHA_MODE_SHA1
+  *         - \ref SHA_MODE_SHA224
+  *         - \ref SHA_MODE_SHA256
+  *         - \ref SHA_MODE_SHA384
+  *         - \ref SHA_MODE_SHA512
+  * @param[in]  u32SwapType is SHA input/output data swap control, including:
+  *         - \ref SHA_NO_SWAP
+  *         - \ref SHA_OUT_SWAP
+  *         - \ref SHA_IN_SWAP
+  *         - \ref SHA_IN_OUT_SWAP
+  * @param[in]  hmac_key_len   HMAC key byte count
+  * @return None
+  */
+void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len)
+{
+    CRPT->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) |
+                     (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos);
+
+    if (hmac_key_len != 0UL) {
+        CRPT->HMAC_KEYCNT = hmac_key_len;
+        CRPT->HMAC_CTL |= CRPT_HMAC_CTL_HMACEN_Msk;
+    }
+}
+
+/**
+  * @brief  Start SHA encrypt
+  * @param[in]  u32DMAMode  TDES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop SHA encrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous SHA encrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last SHA encrypt of a series of SHA_Start.
+  * @return None
+  */
+void SHA_Start(uint32_t u32DMAMode)
+{
+    CRPT->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos);
+    CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set SHA DMA transfer
+  * @param[in]  u32SrcAddr   SHA DMA source address
+  * @param[in]  u32TransCnt  SHA DMA transfer byte count
+  * @return None
+  */
+void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt)
+{
+    CRPT->HMAC_SADDR = u32SrcAddr;
+    CRPT->HMAC_DMACNT = u32TransCnt;
+}
+
+/**
+  * @brief  Read the SHA digest.
+  * @param[out]  u32Digest  The SHA encrypt output digest.
+  * @return None
+  */
+void SHA_Read(uint32_t u32Digest[])
+{
+    uint32_t  i, wcnt, reg_addr;
+
+    i = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;
+
+    if (i == SHA_MODE_SHA1) {
+        wcnt = 5UL;
+    } else if (i == SHA_MODE_SHA224) {
+        wcnt = 7UL;
+    } else if (i == SHA_MODE_SHA256) {
+        wcnt = 8UL;
+    } else if (i == SHA_MODE_SHA384) {
+        wcnt = 12UL;
+    } else {     /* SHA_MODE_SHA512 */
+        wcnt = 16UL;
+    }
+
+    reg_addr = (uint32_t)&(CRPT->HMAC_DGST[0]);
+    for (i = 0UL; i < wcnt; i++) {
+        u32Digest[i] = inpw(reg_addr);
+        reg_addr += 4UL;
+    }
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+/*-----------------------------------------------------------------------------------------------*/
+/*                                                                                               */
+/*    ECC                                                                                        */
+/*                                                                                               */
+/*-----------------------------------------------------------------------------------------------*/
+
+#define ECCOP_POINT_MUL     (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_MODULE        (0x1UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_ADD     (0x2UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_DOUBLE  (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+
+#define MODOP_DIV           (0x0UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_MUL           (0x1UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_ADD           (0x2UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_SUB           (0x3UL << CRPT_ECC_CTL_MODOP_Pos)
+
+enum {
+    CURVE_GF_P,
+    CURVE_GF_2M,
+};
+
+/*-----------------------------------------------------*/
+/*  Define elliptic curve (EC):                        */
+/*-----------------------------------------------------*/
+
+typedef struct e_curve_t {
+    E_ECC_CURVE  curve_id;
+    int32_t   Echar;
+    char  Ea[144];
+    char  Eb[144];
+    char  Px[144];
+    char  Py[144];
+    int32_t   Epl;
+    char  Pp[176];
+    int32_t   Eol;
+    char  Eorder[176];
+    int32_t   key_len;
+    int32_t   irreducible_k1;
+    int32_t   irreducible_k2;
+    int32_t   irreducible_k3;
+    int32_t   GF;
+}  ECC_CURVE;
+
+const ECC_CURVE _Curve[] = {
+    {
+        /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_192,
+        48,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC",   /* "000000000000000000000000000000000000000000000003" */
+        "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1",
+        "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012",
+        "07192b95ffc8da78631011ed6b24cdd573f977a11e794811",
+        58,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF",   /* "6277101735386680763835789423207666416083908700390324961279" */
+        58,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831",   /* "6277101735386680763835789423176059013767194773182842284081" */
+        192,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_224,
+        56,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE",  /* "00000000000000000000000000000000000000000000000000000003" */
+        "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4",
+        "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21",
+        "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34",
+        70,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "0026959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D",  /* "0026959946667150639794667015087019625940457807714424391721682722368061" */
+        224,    /* key_len */
+        9,
+        8,
+        3,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_256,
+        64,     /* Echar */
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC",  /* "0000000000000000000000000000000000000000000000000000000000000003" */
+        "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b",
+        "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296",
+        "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5",
+        78,     /* Epl */
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF",  /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */
+        78,     /* Eol */
+        "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551",  /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */
+        256,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_384,
+        96,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC",  /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+        "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef",
+        "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7",
+        "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f",
+        116,    /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF",  /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */
+        116,    /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973",  /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */
+        384,    /* key_len */
+        12,
+        3,
+        2,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/
+        CURVE_P_521,
+        131,    /* Echar */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",  /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+        "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00",
+        "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66",
+        "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650",
+        157,    /* Epl */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",  /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */
+        157,    /* Eol */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409",  /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */
+        521,    /* key_len */
+        32,
+        32,
+        32,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_163,
+        41,     /* Echar */
+        "00000000000000000000000000000000000000001",
+        "20a601907b8c953ca1481eb10512f78744a3205fd",
+        "3f0eba16286a2d57ea0991168d4994637e8343e36",
+        "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        49,     /* Eol */
+        "40000000000000000000292FE77E70C12A4234C33",   /* "5846006549323611672814742442876390689256843201587" */
+        163,    /* key_len */
+        7,
+        6,
+        3,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_233,
+        59,     /* Echar 59 */
+        "00000000000000000000000000000000000000000000000000000000001",
+        "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad",
+        "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b",
+        "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7",  /* "6901746346790563787434755862277025555839812737345013555379383634485463" */
+        233,    /* key_len */
+        74,
+        74,
+        74,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_283,
+        71,     /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000001",
+        "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5",
+        "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053",
+        "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        85,     /* Eol */
+        "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307",  /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */
+        283,    /* key_len */
+        12,
+        7,
+        5,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_409,
+        103,    /* Echar */
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f",
+        "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7",
+        "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        123,    /* Eol */
+        "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173",  /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */
+        409,    /* key_len */
+        87,
+        87,
+        87,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_571,
+        143,    /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a",
+        "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19",
+        "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        172,    /* Eol */
+        "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47",  /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */
+        571,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_163,
+        41,     /* Echar */
+        "00000000000000000000000000000000000000001",
+        "00000000000000000000000000000000000000001",
+        "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8",
+        "289070fb05d38ff58321f2e800536d538ccdaa3d9",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        49,     /* Eol */
+        "4000000000000000000020108A2E0CC0D99F8A5EF",  /* "5846006549323611672814741753598448348329118574063" */
+        163,    /* key_len */
+        7,
+        6,
+        3,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_233,
+        59,     /* Echar 59 */
+        "00000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000001",
+        "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126",
+        "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",    /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF",  /* "3450873173395281893717377931138512760570940988862252126328087024741343" */
+        233,    /* key_len */
+        74,
+        74,
+        74,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_283,
+        71,     /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000000000000000001",
+        "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836",
+        "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        85,     /* Eol */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61",  /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */
+        283,    /* key_len */
+        12,
+        7,
+        5,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_409,
+        103,    /* Echar */
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746",
+        "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        123,    /* Eol */
+        "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF",  /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */
+        409,    /* key_len */
+        87,
+        87,
+        87,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_571,
+        143,    /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972",
+        "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        172,    /* Eol */
+        "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001",  /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */
+        571,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_2M
+    },
+};
+
+static ECC_CURVE  *pCurve;
+static ECC_CURVE  Curve_Copy;
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
+static int32_t ecc_init_curve(E_ECC_CURVE ecc_curve);
+static void run_ecc_codec(uint32_t mode);
+
+static char  temp_hex_str[160];
+
+
+#if ENABLE_DEBUG
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)
+{
+    int32_t  i;
+
+    printf("%s => ", str);
+    for (i = 0; i < count; i++) {
+        printf("0x%08x ", regs[i]);
+    }
+    printf("\n");
+}
+#else
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) { }
+#endif
+
+static char  ch2hex(char ch)
+{
+    if (ch <= '9') {
+        ch = ch - '0';
+    } else if ((ch <= 'z') && (ch >= 'a')) {
+        ch = ch - 'a' + 10U;
+    } else {
+        ch = ch - 'A' + 10U;
+    }
+    return ch;
+}
+
+static void Hex2Reg(char input[], uint32_t volatile reg[])
+{
+    char      hex;
+    int       si, ri;
+    uint32_t  i, val32;
+
+    si = (int)strlen(input) - 1;
+    ri = 0;
+
+    while (si >= 0) {
+        val32 = 0UL;
+        for (i = 0UL; (i < 8UL) && (si >= 0); i++) {
+            hex = ch2hex(input[si]);
+            val32 |= (uint32_t)hex << (i * 4UL);
+            si--;
+        }
+        reg[ri++] = val32;
+    }
+}
+
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
+{
+    uint32_t  hex, carry;
+    int       si, ri;
+    uint32_t  i, val32;
+
+    si = (int)strlen(input) - 1;
+    ri = 0L;
+    carry = 0UL;
+    while (si >= 0) {
+        val32 = 0UL;
+        for (i = 0UL; (i < 8UL) && (si >= 0L); i++) {
+            hex = (uint32_t)ch2hex(input[si]);
+            hex <<= shift;
+
+            val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL);
+            carry = (hex >> 4UL) & 0xFUL;
+            si--;
+        }
+        reg[ri++] = val32;
+    }
+    if (carry != 0UL) {
+        reg[ri] = carry;
+    }
+}
+
+/**
+  * @brief  Extract specified nibble from an unsigned word in character format.
+  *         For example:
+  *                Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'.
+  * @param[in]  val32   The input unsigned word
+  * @param[in]  idx     The Nth nibble to be extracted.
+  * @return  The nibble in character format.
+  */
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
+{
+    return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ];
+}
+
+
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
+{
+    int32_t    idx, ri;
+    uint32_t   i;
+
+    output[count] = 0U;
+    idx = count - 1;
+
+    for (ri = 0; idx >= 0; ri++) {
+        for (i = 0UL; (i < 8UL) && (idx >= 0); i++) {
+            output[idx] = get_Nth_nibble_char(reg[ri], i);
+            idx--;
+        }
+    }
+}
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
+{
+    uint32_t   i;
+    ECC_CURVE  *ret = NULL;
+
+    for (i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) {
+        if (ecc_curve == _Curve[i].curve_id) {
+            memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE));
+            ret = &Curve_Copy;   /* (ECC_CURVE *)&_Curve[i]; */
+        }
+        if (ret != NULL) {
+            break;
+        }
+    }
+    return ret;
+}
+
+static int32_t ecc_init_curve(E_ECC_CURVE ecc_curve)
+{
+    int32_t  i, ret = 0;
+
+    pCurve = get_curve(ecc_curve);
+    if (pCurve == NULL) {
+        CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve);
+        ret = -1;
+    }
+
+    if (ret == 0) {
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_A[i] = 0UL;
+            CRPT->ECC_B[i] = 0UL;
+            CRPT->ECC_X1[i] = 0UL;
+            CRPT->ECC_Y1[i] = 0UL;
+            CRPT->ECC_N[i] = 0UL;
+        }
+
+        Hex2Reg(pCurve->Ea, CRPT->ECC_A);
+        Hex2Reg(pCurve->Eb, CRPT->ECC_B);
+        Hex2Reg(pCurve->Px, CRPT->ECC_X1);
+        Hex2Reg(pCurve->Py, CRPT->ECC_Y1);
+
+        CRPT_DBGMSG("Key length = %d\n", pCurve->key_len);
+        dump_ecc_reg("CRPT_ECC_CURVE_A", CRPT->ECC_A, 10);
+        dump_ecc_reg("CRPT_ECC_CURVE_B", CRPT->ECC_B, 10);
+        dump_ecc_reg("CRPT_ECC_POINT_X1", CRPT->ECC_X1, 10);
+        dump_ecc_reg("CRPT_ECC_POINT_Y1", CRPT->ECC_Y1, 10);
+
+        if (pCurve->GF == (int)CURVE_GF_2M) {
+            CRPT->ECC_N[0] = 0x1UL;
+            CRPT->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32));
+            CRPT->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32));
+            CRPT->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32));
+            CRPT->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32));
+        } else {
+            Hex2Reg(pCurve->Pp, CRPT->ECC_N);
+        }
+    }
+    dump_ecc_reg("CRPT_ECC_CURVE_N", CRPT->ECC_N, 10);
+    return ret;
+}
+
+static int  get_nibble_value(char c)
+{
+    if ((c >= '0') && (c <= '9')) {
+        c = c - '0';
+    }
+
+    if ((c >= 'a') && (c <= 'f')) {
+        c = c - 'a' - (char)10;
+    }
+
+    if ((c >= 'A') && (c <= 'F')) {
+        c = c - 'A' - (char)10;
+    }
+    return (int)c;
+}
+
+volatile uint32_t g_ECC_done, g_ECCERR_done;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief  ECC interrupt service routine. User application must invoke this function in
+  *         his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done.
+  * @return   none
+  */
+void ECC_DriverISR(void)
+{
+    if (CRPT->INTSTS & CRPT_INTSTS_ECCIF_Msk) {
+        g_ECC_done = 1UL;
+        CRPT->INTSTS = CRPT_INTSTS_ECCIF_Msk;
+        /* printf("ECC done IRQ.\n"); */
+    }
+
+    if (CRPT->INTSTS & CRPT_INTSTS_ECCEIF_Msk) {
+        g_ECCERR_done = 1UL;
+        CRPT->INTSTS = CRPT_INTSTS_ECCEIF_Msk;
+        /* printf("ECCERRIF is set!!\n"); */
+    }
+}
+
+/**
+  * @brief  Check if the private key is located in valid range of curve.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  private_k   The input private key.
+  * @return  1    Is valid.
+  * @return  0    Is not valid.
+  * @return  -1   Invalid curve.
+  */
+int ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve, char private_k[])
+{
+    uint32_t  i;
+    int       ret = -1;
+
+    pCurve = get_curve(ecc_curve);
+    if (pCurve == NULL) {
+        ret = -1;
+    }
+
+    if (strlen(private_k) < strlen(pCurve->Eorder)) {
+        ret = 1;
+    }
+
+    if (strlen(private_k) > strlen(pCurve->Eorder)) {
+        ret = 0;
+    }
+
+    for (i = 0UL; i < strlen(private_k); i++) {
+        if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) {
+            ret = 1;
+            break;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief  Given a private key and curve to generate the public key pair.
+  * @param[in]  private_k   The input private key.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[out] public_k1   The output public key 1.
+  * @param[out] public_k2   The output public key 2.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GeneratePublicKey(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[])
+{
+    int32_t  i, ret = 0;
+
+    if (ecc_init_curve(ecc_curve) != 0) {
+        ret = -1;
+    }
+
+    if (ret == 0) {
+
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_K[i] = 0UL;
+        }
+        Hex2Reg(private_k, CRPT->ECC_K);
+
+        /* set FSEL (Field selection) */
+        if (pCurve->GF == (int)CURVE_GF_2M) {
+            CRPT->ECC_CTL = 0UL;
+        } else {       /*  CURVE_GF_P */
+            CRPT->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+
+        g_ECC_done = g_ECCERR_done = 0UL;
+        CRPT->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        while ((g_ECC_done | g_ECCERR_done) == 0UL) { }
+
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, public_k1);
+        Reg2Hex(pCurve->Echar, CRPT->ECC_Y1, public_k2);
+    }
+
+    return ret;
+}
+
+/**
+  * @brief  Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  private_k   One's own private key.
+  * @param[in]  public_k1   The other party's publick key 1.
+  * @param[in]  public_k2   The other party's publick key 2.
+  * @param[out] secret_z    The ECC CDH secret Z.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GenerateSecretZ(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[])
+{
+    int32_t  i, ret = 0;
+
+    if (ecc_init_curve(ecc_curve) != 0) {
+        ret = -1;
+    }
+
+    if (ret == 0) {
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_K[i] = 0UL;
+            CRPT->ECC_X1[i] = 0UL;
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+
+        if ((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) ||
+                (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) {
+            Hex2RegEx(private_k, CRPT->ECC_K, 1);
+        } else if ((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) ||
+                   (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) {
+            Hex2RegEx(private_k, CRPT->ECC_K, 2);
+        } else {
+            Hex2Reg(private_k, CRPT->ECC_K);
+        }
+
+        Hex2Reg(public_k1, CRPT->ECC_X1);
+        Hex2Reg(public_k2, CRPT->ECC_Y1);
+
+        /* set FSEL (Field selection) */
+        if (pCurve->GF == (int)CURVE_GF_2M) {
+            CRPT->ECC_CTL = 0UL;
+        } else {       /*  CURVE_GF_P */
+            CRPT->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+        g_ECC_done = g_ECCERR_done = 0UL;
+        CRPT->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        while ((g_ECC_done | g_ECCERR_done) == 0UL) { }
+
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, secret_z);
+    }
+
+    return ret;
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+static void run_ecc_codec(uint32_t mode)
+{
+    if ((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE) {
+        CRPT->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+    } else {
+        if (pCurve->GF == (int)CURVE_GF_2M) {
+            /* point */
+            CRPT->ECC_CTL = 0UL;
+        } else {
+            /* CURVE_GF_P */
+            CRPT->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+    }
+
+    g_ECC_done = g_ECCERR_done = 0UL;
+    CRPT->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk;
+    while ((g_ECC_done | g_ECCERR_done) == 0UL) { }
+
+    while (CRPT->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { }
+}
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief  ECDSA digital signature generation.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  d           The private key.
+  * @param[in]  k           The selected random integer.
+  * @param[out] R           R of the (R,S) pair digital signature
+  * @param[out] S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GenerateSignature(E_ECC_CURVE ecc_curve, char *message,
+                               char *d, char *k, char *R, char *S)
+{
+    uint32_t volatile temp_result1[18], temp_result2[18];
+    int32_t  i, ret = 0;
+
+    if (ecc_init_curve(ecc_curve) != 0) {
+        ret = -1;
+    }
+
+    if (ret == 0) {
+
+        /*
+         *   1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1)
+         *      (1) Use SHA to calculate e
+         */
+
+        /*   2. Select a random integer k form [1, n-1]
+         *      (1) Notice that n is order, not prime modulus or irreducible polynomial function
+         */
+
+        /*
+         *   3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2
+         *      (1) Write the curve parameter A, B, and curve length M to corresponding registers
+         *      (2) Write the prime modulus or irreducible polynomial function to N registers according
+         *      (3) Write the point G(x, y) to X1, Y1 registers
+         *      (4) Write the random integer k to K register
+         *      (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+         *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (9) Write the curve order and curve length to N ,M registers according
+         *      (10) Write 0x0 to Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1         *
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Read X1 registers to get r
+         */
+
+        /* 3-(4) Write the random integer k to K register */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_K[i] = 0UL;
+        }
+        Hex2Reg(k, CRPT->ECC_K);
+
+        run_ecc_codec(ECCOP_POINT_MUL);
+
+        /*  3-(9) Write the curve order to N registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /* 3-(10) Write 0x0 to Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_ADD);
+
+        /* 3-(15) Read X1 registers to get r */
+        for (i = 0; i < 18; i++) {
+            temp_result1[i] = CRPT->ECC_X1[i];
+        }
+
+        Reg2Hex(pCurve->Echar, temp_result1, R);
+
+        /*
+         *   4. Compute s = k ? 1 ¡Ñ (e + d ¡Ñ r)(mod n). If s = 0, go to step 2
+         *      (1) Write the curve order to N registers according
+         *      (2) Write 0x1 to Y1 registers
+         *      (3) Write the random integer k to X1 registers according
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+         *      (6) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (8) Read X1 registers to get k^-1
+         *      (9) Write the curve order and curve length to N ,M registers
+         *      (10) Write r, d to X1, Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Write the curve order to N registers
+         *      (16) Write e to Y1 registers
+         *      (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (19) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (21) Write the curve order and curve length to N ,M registers
+         *      (22) Write k^-1 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get s
+         */
+
+        /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */
+
+        /*  4-(1) Write the curve order to N registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*  4-(2) Write 0x1 to Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+        CRPT->ECC_Y1[0] = 0x1UL;
+
+        /*  4-(3) Write the random integer k to X1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(k, CRPT->ECC_X1);
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_DIV);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(7) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(8) Read X1 registers to get k^-1 */
+
+        for (i = 0; i < 18; i++) {
+            temp_result2[i] = CRPT->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(9) Write the curve order and curve length to N ,M registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*  4-(10) Write r, d to X1, Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = temp_result1[i];
+        }
+
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+        Hex2Reg(d, CRPT->ECC_Y1);
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_MUL);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(14) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(15) Write the curve order to N registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*  4-(16) Write e to Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+        Hex2Reg(message, CRPT->ECC_Y1);
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_ADD);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(20) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(21) Write the curve order and curve length to N ,M registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*  4-(22) Write k^-1 to Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(27) Read X1 registers to get s */
+        for (i = 0; i < 18; i++) {
+            temp_result2[i] = CRPT->ECC_X1[i];
+        }
+
+        Reg2Hex(pCurve->Echar, temp_result2, S);
+
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+/**
+  * @brief  ECDSA dogotal signature verification.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  public_k1   The public key 1.
+  * @param[in]  public_k2   The public key 2.
+  * @param[in]  R           R of the (R,S) pair digital signature
+  * @param[in]  S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  * @return  -2   Verification failed.
+  */
+int32_t  ECC_VerifySignature(E_ECC_CURVE ecc_curve, char *message,
+                             char *public_k1, char *public_k2, char *R, char *S)
+{
+    uint32_t  temp_result1[18], temp_result2[18];
+    uint32_t  temp_x[18], temp_y[18];
+    int32_t   i, ret = 0;
+
+    /*
+     *   1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid
+     *   2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation
+     *      (1) Use SHA to calculate e
+     */
+
+    /*
+     *   3. Compute w = s^-1 (mod n)
+     *      (1) Write the curve order to N registers
+     *      (2) Write 0x1 to Y1 registers
+     *      (3) Write s to X1 registers
+     *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+     *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+     *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+     *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+     *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+     *      (9) Read X1 registers to get w
+     */
+
+    if (ecc_init_curve(ecc_curve) != 0) {
+        ret = -1;
+    }
+
+    if (ret == 0) {
+
+        /*  3-(1) Write the curve order to N registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*  3-(2) Write 0x1 to Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+        CRPT->ECC_Y1[0] = 0x1UL;
+
+        /*  3-(3) Write s to X1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(S, CRPT->ECC_X1);
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_DIV);
+
+        /*  3-(9) Read X1 registers to get w */
+        for (i = 0; i < 18; i++) {
+            temp_result2[i] = CRPT->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        CRPT_DBGMSG("e = %s\n", message);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("w = %s\n", temp_hex_str);
+        CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder);
+#endif
+
+        /*
+         *   4. Compute u1 = e ¡Ñ w (mod n) and u2 = r ¡Ñ w (mod n)
+         *      (1) Write the curve order and curve length to N ,M registers
+         *      (2) Write e, w to X1, Y1 registers
+         *      (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1 registers to get u1
+         *      (8) Write the curve order and curve length to N ,M registers
+         *      (9) Write r, w to X1, Y1 registers
+         *      (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Read X1 registers to get u2
+         */
+
+        /*  4-(1) Write the curve order and curve length to N ,M registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /* 4-(2) Write e, w to X1, Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(message, CRPT->ECC_X1);
+
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(7) Read X1 registers to get u1 */
+        for (i = 0; i < 18; i++) {
+            temp_result1[i] = CRPT->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("u1 = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(8) Write the curve order and curve length to N ,M registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /* 4-(9) Write r, w to X1, Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(R, CRPT->ECC_X1);
+
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(14) Read X1 registers to get u2 */
+        for (i = 0; i < 18; i++) {
+            temp_result2[i] = CRPT->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("u2 = %s\n", temp_hex_str);
+#endif
+
+        /*
+         *   5. Compute X¡¦ (x1¡¦, y1¡¦) = u1 * G + u2 * Q
+         *      (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (2) Write the point G(x, y) to X1, Y1 registers
+         *      (3) Write u1 to K registers
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1, Y1 registers to get u1*G
+         *      (8) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (9) Write the public key Q(x,y) to X1, Y1 registers
+         *      (10) Write u2 to K registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (15) Write the result data u1*G to X2, Y2 registers
+         *      (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
+         *      (17) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦)
+         *      (20) Write the curve order and curve length to N ,M registers
+         *      (21) Write x1¡¦ to X1 registers
+         *      (22) Write 0x0 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get x1¡¦ (mod n)
+         *
+         *   6. The signature is valid if x1¡¦ = r, otherwise it is invalid
+         */
+
+        /*
+         *  (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *  (2) Write the point G(x, y) to X1, Y1 registers
+         */
+        ecc_init_curve(ecc_curve);
+
+        /* (3) Write u1 to K registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_K[i] = temp_result1[i];
+        }
+
+        run_ecc_codec(ECCOP_POINT_MUL);
+
+        /* (7) Read X1, Y1 registers to get u1*G */
+        for (i = 0; i < 18; i++) {
+            temp_x[i] = CRPT->ECC_X1[i];
+            temp_y[i] = CRPT->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str);
+#endif
+
+        /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(ecc_curve);
+
+        /* (9) Write the public key Q(x,y) to X1, Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = 0UL;
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+
+        Hex2Reg(public_k1, CRPT->ECC_X1);
+        Hex2Reg(public_k2, CRPT->ECC_Y1);
+
+        /* (10) Write u2 to K registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_K[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(ECCOP_POINT_MUL);
+
+        for (i = 0; i < 18; i++) {
+            temp_result1[i] = CRPT->ECC_X1[i];
+            temp_result2[i] = CRPT->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str);
+#endif
+
+        /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(ecc_curve);
+
+        /* Write the result data u2*Q to X1, Y1 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = temp_result1[i];
+            CRPT->ECC_Y1[i] = temp_result2[i];
+        }
+
+        /* (15) Write the result data u1*G to X2, Y2 registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X2[i] = temp_x[i];
+            CRPT->ECC_Y2[i] = temp_y[i];
+        }
+
+        run_ecc_codec(ECCOP_POINT_ADD);
+
+        /* (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) */
+        for (i = 0; i < 18; i++) {
+            temp_x[i] = CRPT->ECC_X1[i];
+            temp_y[i] = CRPT->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str);
+#endif
+
+        /*  (20) Write the curve order and curve length to N ,M registers */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, CRPT->ECC_N);
+
+        /*
+         *  (21) Write x1¡¦ to X1 registers
+         *  (22) Write 0x0 to Y1 registers
+         */
+        for (i = 0; i < 18; i++) {
+            CRPT->ECC_X1[i] = temp_x[i];
+            CRPT->ECC_Y1[i] = 0UL;
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, CRPT->ECC_Y1, temp_hex_str);
+        CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str);
+#endif
+
+        run_ecc_codec(ECCOP_MODULE | MODOP_ADD);
+
+        /*  (27) Read X1 registers to get x1¡¦ (mod n) */
+        Reg2Hex(pCurve->Echar, CRPT->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
+
+        /* 6. The signature is valid if x1¡¦ = r, otherwise it is invalid */
+
+        /* Compare with test pattern to check if r is correct or not */
+        if (strcmp(temp_hex_str, R) != 0) {
+            CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n");
+            CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R);
+            ret = -2;
+        }
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+/*@}*/ /* end of group M480_CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CRYPTO_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crypto.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,338 @@
+/**************************************************************************//**
+ * @file     crypto.h
+ * @version  V1.10
+ * @brief    Cryptographic Accelerator driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CRYPTO_H__
+#define __CRYPTO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+
+/** @addtogroup M480_CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
+  @{
+*/
+
+#define PRNG_KEY_SIZE_64        0UL     /*!< Select to generate 64-bit random key    \hideinitializer */
+#define PRNG_KEY_SIZE_128       1UL     /*!< Select to generate 128-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_192       2UL     /*!< Select to generate 192-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_256       3UL     /*!< Select to generate 256-bit random key   \hideinitializer */
+
+#define PRNG_SEED_CONT          0UL     /*!< PRNG using current seed                 \hideinitializer */
+#define PRNG_SEED_RELOAD        1UL     /*!< PRNG reload new seed                    \hideinitializer */
+
+#define AES_KEY_SIZE_128        0UL     /*!< AES select 128-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_192        1UL     /*!< AES select 192-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_256        2UL     /*!< AES select 256-bit key length           \hideinitializer */
+
+#define AES_MODE_ECB            0UL     /*!< AES select ECB mode                     \hideinitializer */
+#define AES_MODE_CBC            1UL     /*!< AES select CBC mode                     \hideinitializer */
+#define AES_MODE_CFB            2UL     /*!< AES select CFB mode                     \hideinitializer */
+#define AES_MODE_OFB            3UL     /*!< AES select OFB mode                     \hideinitializer */
+#define AES_MODE_CTR            4UL     /*!< AES select CTR mode                     \hideinitializer */
+#define AES_MODE_CBC_CS1        0x10UL  /*!< AES select CBC CS1 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS2        0x11UL  /*!< AES select CBC CS2 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS3        0x12UL  /*!< AES select CBC CS3 mode                 \hideinitializer */
+
+#define AES_NO_SWAP             0UL     /*!< AES do not swap input and output data   \hideinitializer */
+#define AES_OUT_SWAP            1UL     /*!< AES swap output data                    \hideinitializer */
+#define AES_IN_SWAP             2UL     /*!< AES swap input data                     \hideinitializer */
+#define AES_IN_OUT_SWAP         3UL     /*!< AES swap both input and output data     \hideinitializer */
+
+#define DES_MODE_ECB            0x000UL /*!< DES select ECB mode                     \hideinitializer */
+#define DES_MODE_CBC            0x100UL /*!< DES select CBC mode                     \hideinitializer */
+#define DES_MODE_CFB            0x200UL /*!< DES select CFB mode                     \hideinitializer */
+#define DES_MODE_OFB            0x300UL /*!< DES select OFB mode                     \hideinitializer */
+#define DES_MODE_CTR            0x400UL /*!< DES select CTR mode                     \hideinitializer */
+#define TDES_MODE_ECB           0x004UL /*!< TDES select ECB mode                    \hideinitializer */
+#define TDES_MODE_CBC           0x104UL /*!< TDES select CBC mode                    \hideinitializer */
+#define TDES_MODE_CFB           0x204UL /*!< TDES select CFB mode                    \hideinitializer */
+#define TDES_MODE_OFB           0x304UL /*!< TDES select OFB mode                    \hideinitializer */
+#define TDES_MODE_CTR           0x404UL /*!< TDES select CTR mode                    \hideinitializer */
+
+#define TDES_NO_SWAP            0UL     /*!< TDES do not swap data                       \hideinitializer */
+#define TDES_WHL_SWAP           1UL     /*!< TDES swap high-low word                     \hideinitializer */
+#define TDES_OUT_SWAP           2UL     /*!< TDES swap output data                       \hideinitializer */
+#define TDES_OUT_WHL_SWAP       3UL     /*!< TDES swap output data and high-low word     \hideinitializer */
+#define TDES_IN_SWAP            4UL     /*!< TDES swap input data                        \hideinitializer */
+#define TDES_IN_WHL_SWAP        5UL     /*!< TDES swap input data and high-low word      \hideinitializer */
+#define TDES_IN_OUT_SWAP        6UL     /*!< TDES swap both input and output data        \hideinitializer */
+#define TDES_IN_OUT_WHL_SWAP    7UL     /*!< TDES swap input, output and high-low word   \hideinitializer */
+
+#define SHA_MODE_SHA1           0UL     /*!< SHA select SHA-1 160-bit                \hideinitializer */
+#define SHA_MODE_SHA224         5UL     /*!< SHA select SHA-224 224-bit              \hideinitializer */
+#define SHA_MODE_SHA256         4UL     /*!< SHA select SHA-256 256-bit              \hideinitializer */
+#define SHA_MODE_SHA384         7UL     /*!< SHA select SHA-384 384-bit              \hideinitializer */
+#define SHA_MODE_SHA512         6UL     /*!< SHA select SHA-512 512-bit              \hideinitializer */
+
+#define SHA_NO_SWAP             0UL     /*!< SHA do not swap input and output data   \hideinitializer */
+#define SHA_OUT_SWAP            1UL     /*!< SHA swap output data                    \hideinitializer */
+#define SHA_IN_SWAP             2UL     /*!< SHA swap input data                     \hideinitializer */
+#define SHA_IN_OUT_SWAP         3UL     /*!< SHA swap both input and output data     \hideinitializer */
+
+#define CRYPTO_DMA_FIRST        0x4UL   /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_ONE_SHOT     0x5UL   /*!< Do one shot encrypt/decrypt with DMA      \hideinitializer */
+#define CRYPTO_DMA_CONTINUE     0x6UL   /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_LAST         0x7UL   /*!< Do last encrypt/decrypt in DMA cascade          \hideinitializer */
+
+typedef enum {                          /*!< ECC curve                \hideinitializer */
+    CURVE_P_192,                        /*!< ECC curve P-192          \hideinitializer */
+    CURVE_P_224,                        /*!< ECC curve P-224          \hideinitializer */
+    CURVE_P_256,                        /*!< ECC curve P-256          \hideinitializer */
+    CURVE_P_384,                        /*!< ECC curve P-384          \hideinitializer */
+    CURVE_P_521,                        /*!< ECC curve P-521          \hideinitializer */
+    CURVE_K_163,                        /*!< ECC curve K-163          \hideinitializer */
+    CURVE_K_233,                        /*!< ECC curve K-233          \hideinitializer */
+    CURVE_K_283,                        /*!< ECC curve K-283          \hideinitializer */
+    CURVE_K_409,                        /*!< ECC curve K-409          \hideinitializer */
+    CURVE_K_571,                        /*!< ECC curve K-571          \hideinitializer */
+    CURVE_B_163,                        /*!< ECC curve B-163          \hideinitializer */
+    CURVE_B_233,                        /*!< ECC curve B-233          \hideinitializer */
+    CURVE_B_283,                        /*!< ECC curve B-283          \hideinitializer */
+    CURVE_B_409,                        /*!< ECC curve B-409          \hideinitializer */
+    CURVE_B_571                         /*!< ECC curve K-571          \hideinitializer */
+}
+E_ECC_CURVE;                            /*!< ECC curve                \hideinitializer */
+
+
+/*@}*/ /* end of group M480_CRYPTO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/*----------------------------------------------------------------------------------------------*/
+/*  Macros                                                                                      */
+/*----------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief This macro enables PRNG interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_ENABLE_INT()       (CRPT->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro disables PRNG interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_DISABLE_INT()      (CRPT->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro gets PRNG interrupt flag.
+  * @return PRNG interrupt flag.
+  * \hideinitializer
+  */
+#define PRNG_GET_INT_FLAG()     (CRPT->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro clears PRNG interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_CLR_INT_FLAG()     (CRPT->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro enables AES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+  * @brief This macro disables AES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+  * @brief This macro gets AES interrupt flag.
+  * @return AES interrupt flag.
+  * \hideinitializer
+  */
+#define AES_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+  * @brief This macro clears AES interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+  * @brief This macro enables AES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_KEY_PROTECT()  (CRPT->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables AES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_KEY_PROTECT() (CRPT->AES_CTL = (CRPT->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_AES_CTL_KEYUNPRT_Pos)); \
+                                  (CRPT->AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro enables TDES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_INT()       (CRPT->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+  * @brief This macro disables TDES interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_INT()      (CRPT->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+  * @brief This macro gets TDES interrupt flag.
+  * @return TDES interrupt flag.
+  * \hideinitializer
+  */
+#define TDES_GET_INT_FLAG()     (CRPT->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+  * @brief This macro clears TDES interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_CLR_INT_FLAG()     (CRPT->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+  * @brief This macro enables TDES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_KEY_PROTECT()  (CRPT->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables TDES key protection.
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_KEY_PROTECT() (CRPT->TDES_CTL = (CRPT->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_TDES_CTL_KEYUNPRT_Pos)); \
+                                   (CRPT->TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro enables SHA interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+  * @brief This macro disables SHA interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+  * @brief This macro gets SHA interrupt flag.
+  * @return SHA interrupt flag.
+  * \hideinitializer
+  */
+#define SHA_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+  * @brief This macro clears SHA interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+  * @brief This macro enables ECC interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+  * @brief This macro disables ECC interrupt.
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+  * @brief This macro gets ECC interrupt flag.
+  * @return ECC interrupt flag.
+  * \hideinitializer
+  */
+#define ECC_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+/**
+  * @brief This macro clears ECC interrupt flag.
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Functions                                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+
+void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
+void PRNG_Start(void);
+void PRNG_Read(uint32_t u32RandKey[]);
+void AES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
+void AES_Start(int32_t u32Channel, uint32_t u32DMAMode);
+void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
+void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]);
+void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
+void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode);
+void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]);
+void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
+void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
+void SHA_Start(uint32_t u32DMAMode);
+void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt);
+void SHA_Read(uint32_t u32Digest[]);
+void ECC_DriverISR(void);
+int  ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve,  char private_k[]);
+int32_t  ECC_GeneratePublicKey(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
+int32_t  ECC_GenerateSecretZ(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
+int32_t  ECC_GenerateSignature(E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
+int32_t  ECC_VerifySignature(E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
+
+
+/*@}*/ /* end of group M480_CRYPTO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_CRYPTO_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __CRYPTO_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_dac.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,89 @@
+/**************************************************************************//**
+ * @file     dac.c
+ * @version  V1.00
+ * @brief    M480 series DAC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_DAC_Driver DAC Driver
+  @{
+*/
+
+/** @addtogroup M480_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make DAC module be ready to convert.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
+  *                      - \ref DAC_WRITE_DAT_TRIGGER             :Write DAC_DAT trigger
+  *                      - \ref DAC_SOFTWARE_TRIGGER              :Software trigger
+  *                      - \ref DAC_LOW_LEVEL_TRIGGER             :STDAC pin low level trigger
+  *                      - \ref DAC_HIGH_LEVEL_TRIGGER            :STDAC pin high level trigger
+  *                      - \ref DAC_FALLING_EDGE_TRIGGER          :STDAC pin falling edge trigger
+  *                      - \ref DAC_RISING_EDGE_TRIGGER           :STDAC pin rising edge trigger
+  *                      - \ref DAC_TIMER0_TRIGGER                :Timer 0 trigger
+  *                      - \ref DAC_TIMER1_TRIGGER                :Timer 1 trigger
+  *                      - \ref DAC_TIMER2_TRIGGER                :Timer 2 trigger
+  *                      - \ref DAC_TIMER3_TRIGGER                :Timer 3 trigger
+  *                      - \ref DAC_EPWM0_TRIGGER                 :EPWM0 trigger
+  *                      - \ref DAC_EPWM1_TRIGGER                 :EPWM1 trigger
+  * @return None
+  * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
+  *         When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
+  *         When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
+  *         external STDAC pin, timer event, or EPWM event.
+  */
+void DAC_Open(DAC_T *dac,
+              uint32_t u32Ch,
+              uint32_t u32TrgSrc)
+{
+    dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
+    dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Disable DAC analog power.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @return None
+  * @details Disable DAC analog power for saving power consumption.
+  */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+    dac->CTL &= (~DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Set delay time for DAC to become stable.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
+  * @return Real DAC conversion settling time (micro second).
+  * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0.
+  * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
+  */
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+
+    dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
+
+    return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
+}
+
+
+
+/*@}*/ /* end of group M480_DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_DAC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_dac.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file     dac.h
+ * @version V1.00
+ * @brief    M480 series DAC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __DAC_H__
+#define __DAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_DAC_Driver DAC Driver
+  @{
+*/
+
+
+/** @addtogroup M480_DAC_EXPORTED_CONSTANTS DAC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DAC_CTL Constant Definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define DAC_CTL_LALIGN_RIGHT_ALIGN   (0UL<<DAC_CTL_LALIGN_Pos)   /*!< Right alignment. \hideinitializer */
+#define DAC_CTL_LALIGN_LEFT_ALIGN    (1UL<<DAC_CTL_LALIGN_Pos)   /*!< Left alignment \hideinitializer */
+
+#define DAC_WRITE_DAT_TRIGGER      (0UL)    /*!< Write DAC_DAT trigger \hideinitializer */
+#define DAC_SOFTWARE_TRIGGER       (0UL|DAC_CTL_TRGEN_Msk)    /*!< Software trigger \hideinitializer */
+#define DAC_LOW_LEVEL_TRIGGER      ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin low level trigger \hideinitializer */
+#define DAC_HIGH_LEVEL_TRIGGER     ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin high level trigger \hideinitializer */
+#define DAC_FALLING_EDGE_TRIGGER   ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin falling edge trigger \hideinitializer */
+#define DAC_RISING_EDGE_TRIGGER    ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin rising edge trigger \hideinitializer */
+#define DAC_TIMER0_TRIGGER         ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 0 trigger \hideinitializer */
+#define DAC_TIMER1_TRIGGER         ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 1 trigger \hideinitializer */
+#define DAC_TIMER2_TRIGGER         ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 2 trigger \hideinitializer */
+#define DAC_TIMER3_TRIGGER         ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 3 trigger \hideinitializer */
+#define DAC_EPWM0_TRIGGER          ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< EPWM0 trigger \hideinitializer */
+#define DAC_EPWM1_TRIGGER          ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< EPWM1 trigger \hideinitializer */
+
+#define DAC_TRIGGER_MODE_DISABLE   (0UL<<DAC_CTL_TRGEN_Pos)   /*!< Trigger mode disable \hideinitializer */
+#define DAC_TRIGGER_MODE_ENABLE    (1UL<<DAC_CTL_TRGEN_Pos)   /*!< Trigger mode enable \hideinitializer */
+
+
+/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+  @{
+*/
+
+/**
+  * @brief Start the D/A conversion.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
+  * \hideinitializer
+  */
+#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
+
+/**
+  * @brief Enable DAC data left-aligned.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable DAC data right-aligned.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable output voltage buffer.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
+  *         drive external loads directly without having to add an external operational amplifier.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Disable output voltage buffer.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable output voltage buffer.
+  * \hideinitializer
+  */
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @return None
+  * @details This macro is used to enable DAC interrupt.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @return None
+  * @details This macro is used to disable DAC interrupt.
+  * \hideinitializer
+  */
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Enable DMA under-run interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to enable DMA under-run interrupt.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Disable DMA under-run interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable DMA under-run interrupt.
+  * \hideinitializer
+  */
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Enable PDMA mode.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Disable PDMA mode.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable DMA mode.
+  * \hideinitializer
+  */
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Write data for conversion.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+  * @return None
+  * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+  *         12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+  * \hideinitializer
+  */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
+
+/**
+  * @brief Read DAC 12-bit holding data.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @return Return DAC 12-bit holding data.
+  * @details This macro is used to read DAC_DAT register.
+  * \hideinitializer
+  */
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
+
+/**
+  * @brief Get the busy state of DAC.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
+  * \hideinitializer
+  */
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
+
+/**
+  * @brief Get the interrupt flag.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @retval 0 DAC is in conversion state.
+  * @retval 1 DAC conversion finish.
+  * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
+  * \hideinitializer
+  */
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief Get the DMA under-run flag.
+  * @param[in] dac Base address of DAC module.
+  * @retval 0 No DMA under-run error condition occurred.
+  * @retval 1 DMA under-run error condition occurred.
+  * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
+  * \hideinitializer
+  */
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
+
+/**
+  * @brief This macro clear the interrupt status bit.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M480 DAC.
+  * @return None
+  * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
+  * \hideinitializer
+  */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief This macro clear the  DMA under-run flag.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
+  * \hideinitializer
+  */
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
+
+
+/**
+  * @brief Enable DAC group mode
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * \hideinitializer
+  */
+#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk)
+
+/**
+  * @brief Disable DAC group mode
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * \hideinitializer
+  */
+#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
+
+/*@}*/ /* end of group M480_DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_DAC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_eadc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file     eadc.c
+ * @version  V2.00
+ * @brief    M480 series EADC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make EADC_module be ready to convert.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32InputMode Decides the input mode.
+  *                       - \ref EADC_CTL_DIFFEN_SINGLE_END      :Single end input mode.
+  *                       - \ref EADC_CTL_DIFFEN_DIFFERENTIAL    :Differential input type.
+  * @return None
+  * @details This function is used to set analog input mode and enable A/D Converter.
+  *         Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
+  * @note
+  */
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
+{
+    eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
+
+    eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
+    while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {}
+}
+
+/**
+  * @brief Disable EADC_module.
+  * @param[in] eadc The pointer of the specified EADC module..
+  * @return None
+  * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
+  */
+void EADC_Close(EADC_T *eadc)
+{
+    eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
+}
+
+/**
+  * @brief Configure the sample control logic module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
+  *                            - \ref EADC_SOFTWARE_TRIGGER              : Disable trigger
+  *                            - \ref EADC_FALLING_EDGE_TRIGGER          : STADC pin falling edge trigger
+  *                            - \ref EADC_RISING_EDGE_TRIGGER           : STADC pin rising edge trigger
+  *                            - \ref EADC_FALLING_RISING_EDGE_TRIGGER   : STADC pin both falling and rising edge trigger
+  *                            - \ref EADC_ADINT0_TRIGGER                : ADC ADINT0 interrupt EOC pulse trigger
+  *                            - \ref EADC_ADINT1_TRIGGER                : ADC ADINT1 interrupt EOC pulse trigger
+  *                            - \ref EADC_TIMER0_TRIGGER                : Timer0 overflow pulse trigger
+  *                            - \ref EADC_TIMER1_TRIGGER                : Timer1 overflow pulse trigger
+  *                            - \ref EADC_TIMER2_TRIGGER                : Timer2 overflow pulse trigger
+  *                            - \ref EADC_TIMER3_TRIGGER                : Timer3 overflow pulse trigger
+  *                            - \ref EADC_PWM0TG0_TRIGGER               : PWM0TG0 trigger
+  *                            - \ref EADC_PWM0TG1_TRIGGER               : PWM0TG1 trigger
+  *                            - \ref EADC_PWM0TG2_TRIGGER               : PWM0TG2 trigger
+  *                            - \ref EADC_PWM0TG3_TRIGGER               : PWM0TG3 trigger
+  *                            - \ref EADC_PWM0TG4_TRIGGER               : PWM0TG4 trigger
+  *                            - \ref EADC_PWM0TG5_TRIGGER               : PWM0TG5 trigger
+  *                            - \ref EADC_PWM1TG0_TRIGGER               : PWM1TG0 trigger
+  *                            - \ref EADC_PWM1TG1_TRIGGER               : PWM1TG1 trigger
+  *                            - \ref EADC_PWM1TG2_TRIGGER               : PWM1TG2 trigger
+  *                            - \ref EADC_PWM1TG3_TRIGGER               : PWM1TG3 trigger
+  *                            - \ref EADC_PWM1TG4_TRIGGER               : PWM1TG4 trigger
+  *                            - \ref EADC_PWM1TG5_TRIGGER               : PWM1TG5 trigger
+  * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
+  * @return None
+  * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
+  *         sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
+  */
+void EADC_ConfigSampleModule(EADC_T *eadc, \
+                             uint32_t u32ModuleNum, \
+                             uint32_t u32TriggerSrc, \
+                             uint32_t u32Channel)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
+    eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
+}
+
+
+/**
+  * @brief Set trigger delay time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
+  * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1    : Trigger delay clock frequency is ADC_CLK/1
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2    : Trigger delay clock frequency is ADC_CLK/2
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4    : Trigger delay clock frequency is ADC_CLK/4
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16   : Trigger delay clock frequency is ADC_CLK/16
+  * @return None
+  * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
+  *         Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
+  */
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \
+                              uint32_t u32ModuleNum, \
+                              uint32_t u32TriggerDelayTime, \
+                              uint32_t u32DelayClockDivider)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
+    eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
+}
+
+/**
+  * @brief Set ADC extend sample time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
+  * @return None
+  * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
+  *         user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+  */
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
+{
+    eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
+
+    eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
+
+}
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_eadc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,596 @@
+/**************************************************************************//**
+ * @file     eadc.h
+ * @version  V0.10
+ * @brief    M480 series EADC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __EADC_H__
+#define __EADC_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M480.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EADC_CTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CTL_DIFFEN_SINGLE_END          (0UL<<EADC_CTL_DIFFEN_Pos)   /*!< Single-end input mode      \hideinitializer */
+#define EADC_CTL_DIFFEN_DIFFERENTIAL        (1UL<<EADC_CTL_DIFFEN_Pos)   /*!< Differential input mode    \hideinitializer */
+
+#define EADC_CTL_DMOF_STRAIGHT_BINARY       (0UL<<EADC_CTL_DMOF_Pos)     /*!< Select the straight binary format as the output format of the conversion result   \hideinitializer */
+#define EADC_CTL_DMOF_TWOS_COMPLEMENT       (1UL<<EADC_CTL_DMOF_Pos)     /*!< Select the 2's complement format as the output format of the conversion result    \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_SCTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_SCTL_CHSEL(x)                  ((x) << EADC_SCTL_CHSEL_Pos)       /*!< A/D sample module channel selection \hideinitializer */
+#define EADC_SCTL_TRGDLYDIV(x)              ((x) << EADC_SCTL_TRGDLYDIV_Pos)   /*!< A/D sample module start of conversion trigger delay clock divider selection \hideinitializer */
+#define EADC_SCTL_TRGDLYCNT(x)              ((x) << EADC_SCTL_TRGDLYCNT_Pos)   /*!< A/D sample module start of conversion trigger delay time \hideinitializer */
+
+#define EADC_SOFTWARE_TRIGGER               (0UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Software trigger \hideinitializer */
+#define EADC_FALLING_EDGE_TRIGGER           (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))       /*!< STADC pin falling edge trigger \hideinitializer */
+#define EADC_RISING_EDGE_TRIGGER            (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))       /*!< STADC pin rising edge trigger \hideinitializer */
+#define EADC_FALLING_RISING_EDGE_TRIGGER    (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger \hideinitializer */
+#define EADC_ADINT0_TRIGGER                 (2UL<<EADC_SCTL_TRGSEL_Pos)      /*!< ADC ADINT0 interrupt EOC pulse trigger \hideinitializer */
+#define EADC_ADINT1_TRIGGER                 (3UL<<EADC_SCTL_TRGSEL_Pos)      /*!< ADC ADINT1 interrupt EOC pulse trigger \hideinitializer */
+#define EADC_TIMER0_TRIGGER                 (4UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer0 overflow pulse trigger \hideinitializer */
+#define EADC_TIMER1_TRIGGER                 (5UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer1 overflow pulse trigger \hideinitializer */
+#define EADC_TIMER2_TRIGGER                 (6UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer2 overflow pulse trigger \hideinitializer */
+#define EADC_TIMER3_TRIGGER                 (7UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer3 overflow pulse trigger \hideinitializer */
+#define EADC_PWM0TG0_TRIGGER                (8UL<<EADC_SCTL_TRGSEL_Pos)      /*!< PWM0TG0 trigger \hideinitializer */
+#define EADC_PWM0TG1_TRIGGER                (9UL<<EADC_SCTL_TRGSEL_Pos)      /*!< PWM0TG1 trigger \hideinitializer */
+#define EADC_PWM0TG2_TRIGGER                (0xAUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG2 trigger \hideinitializer */
+#define EADC_PWM0TG3_TRIGGER                (0xBUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG3 trigger \hideinitializer */
+#define EADC_PWM0TG4_TRIGGER                (0xCUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG4 trigger \hideinitializer */
+#define EADC_PWM0TG5_TRIGGER                (0xDUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG5 trigger \hideinitializer */
+#define EADC_PWM1TG0_TRIGGER                (0xEUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM1TG0 trigger \hideinitializer */
+#define EADC_PWM1TG1_TRIGGER                (0xFUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM1TG1 trigger \hideinitializer */
+#define EADC_PWM1TG2_TRIGGER                (0x10UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG2 trigger \hideinitializer */
+#define EADC_PWM1TG3_TRIGGER                (0x11UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG3 trigger \hideinitializer */
+#define EADC_PWM1TG4_TRIGGER                (0x12UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG4 trigger \hideinitializer */
+#define EADC_PWM1TG5_TRIGGER                (0x13UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG5 trigger \hideinitializer */
+
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_1       (0<<EADC_SCTL_TRGDLYDIV_Pos)           /*!< Trigger delay clock frequency is ADC_CLK/1 \hideinitializer */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_2       (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/2 \hideinitializer */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_4       (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/4 \hideinitializer */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_16      (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/16 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_CMP Constant Definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CMP_CMPCOND_LESS_THAN          (0UL<<EADC_CMP_CMPCOND_Pos)   /*!< The compare condition is "less than" \hideinitializer */
+#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL   (1UL<<EADC_CMP_CMPCOND_Pos)   /*!< The compare condition is "greater than or equal to" \hideinitializer */
+#define EADC_CMP_CMPWEN_ENABLE              (EADC_CMP_CMPWEN_Msk)    /*!< Compare window mode enable \hideinitializer */
+#define EADC_CMP_CMPWEN_DISABLE             (~EADC_CMP_CMPWEN_Msk)   /*!< Compare window mode disable \hideinitializer */
+#define EADC_CMP_ADCMPIE_ENABLE             (EADC_CMP_ADCMPIE_Msk)   /*!< A/D result compare interrupt enable \hideinitializer */
+#define EADC_CMP_ADCMPIE_DISABLE            (~EADC_CMP_ADCMPIE_Msk)  /*!< A/D result compare interrupt disable \hideinitializer */
+
+/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EADC Macro Definitions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief A/D Converter Control Circuits Reset.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+  * \hideinitializer
+  */
+#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
+
+/**
+  * @brief Enable PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+  *         user can enable this bit to generate a PDMA data transfer request.
+  * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
+
+/**
+  * @brief Disable PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable PDMA transfer.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
+
+/**
+  * @brief Enable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details The ADC controller supports a double buffer mode in sample module 0~3.
+  *         If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Disable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details Sample has one sample result register.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Set ADIFn at A/D end of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Set ADIFn at A/D start of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
+  *         If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
+  * \hideinitializer
+  */
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details Specific sample module A/D ADINT0 interrupt function Disabled.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Enable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
+
+/**
+  * @brief Disable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
+
+/**
+  * @brief Set the input mode output format.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Format Decides the output format. Valid values are:
+  *                       - EADC_CTL_DMOF_STRAIGHT_BINARY      :Select the straight binary format as the output format of the conversion result.
+  *                       - EADC_CTL_DMOF_TWOS_COMPLEMENT      :Select the 2's complement format as the output format of the conversion result.
+  * @return None
+  * @details The macro is used to set A/D input mode output format.
+  * \hideinitializer
+  */
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
+
+/**
+  * @brief Start the A/D conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
+  * @return None
+  * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
+  * \hideinitializer
+  */
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
+
+/**
+  * @brief Cancel the conversion for sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
+  * @return None
+  * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+  * \hideinitializer
+  */
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
+
+/**
+  * @brief Get the conversion pending flag.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return Return the conversion pending sample module.
+  * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
+  *         the STPFn (n=0~18) bit is automatically cleared to 0.
+  * \hideinitializer
+  */
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
+
+/**
+  * @brief Get the conversion data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the conversion data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
+  * \hideinitializer
+  */
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
+
+/**
+  * @brief Get the data overrun flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the data overrun flag of the user-specified sample module.
+  * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
+  * \hideinitializer
+  */
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
+
+/**
+  * @brief Get the data valid flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
+  * @return Return the data valid flag of the user-specified sample module.
+  * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.
+  * \hideinitializer
+  */
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
+
+/**
+  * @brief Get the double data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the double data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
+  * \hideinitializer
+  */
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
+
+/**
+  * @brief Get the user-specified interrupt flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return Return the user-specified interrupt flags.
+  * @details This macro is used to get the user-specified interrupt flags.
+  * \hideinitializer
+  */
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
+
+/**
+  * @brief Get the user-specified sample module overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the user-specified sample module overrun flags.
+  * @details This macro is used to get the user-specified sample module overrun flags.
+  * \hideinitializer
+  */
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
+
+/**
+  * @brief Clear the selected interrupt status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return None
+  * @details This macro is used to clear clear the selected interrupt status bits.
+  * \hideinitializer
+  */
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
+
+/**
+  * @brief Clear the selected sample module overrun status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
+  *                      Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
+  * @return None
+  * @details This macro is used to clear the selected sample module overrun status bits.
+  * \hideinitializer
+  */
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
+
+/**
+  * @brief Check all sample module A/D result data register overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register overrun flag is set to 1.
+  * @retval 1 Any one of sample module data register overrun flag is set to 1.
+  * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+  * \hideinitializer
+  */
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
+
+/**
+  * @brief Check all sample module A/D result data register valid flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register valid flag is set to 1.
+  * @retval 1 Any one of sample module data register valid flag is set to 1.
+  * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+  * \hideinitializer
+  */
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
+
+/**
+  * @brief Check all A/D sample module start of conversion overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module event overrun flag is set to 1.
+  * @retval 1 Any one of sample module event overrun flag is set to 1.
+  * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+  * \hideinitializer
+  */
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
+
+/**
+  * @brief Check all A/D interrupt flag overrun bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of ADINT interrupt flag is overwritten to 1.
+  * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
+  * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+  * \hideinitializer
+  */
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
+
+/**
+  * @brief Get the busy state of EADC.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
+  * \hideinitializer
+  */
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
+
+/**
+  * @brief Configure the comparator 0 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP0(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 1 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP1(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 2 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP2(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 3 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP3(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Enable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Disable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Enable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
+  *         and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
+  *         if ADCMPIE is set to 1, a compare interrupt request is generated.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details This macro is used to disable the compare interrupt.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable comparator 0.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 0.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
+
+/**
+  * @brief Disable comparator 1.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 1.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
+
+/**
+  * @brief Disable comparator 2.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 2.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
+
+/**
+  * @brief Disable comparator 3.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 3.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EADC functions prototype                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
+void EADC_Close(EADC_T *eadc);
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EADC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_ebi.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,190 @@
+/**************************************************************************//**
+ * @file     ebi.c
+ * @version  V3.00
+ * @brief    M480 series External Bus Interface(EBI) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_EBI_Driver EBI Driver
+  @{
+*/
+
+
+/** @addtogroup M480_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize EBI for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  *                                     - \ref EBI_BANK2
+  * @param[in]  u32DataWidth        Data bus width. Valid values are:
+  *                                     - \ref EBI_BUSWIDTH_8BIT
+  *                                     - \ref EBI_BUSWIDTH_16BIT
+  * @param[in]  u32TimingClass      Default timing configuration. Valid values are:
+  *                                     - \ref EBI_TIMING_FASTEST
+  *                                     - \ref EBI_TIMING_VERYFAST
+  *                                     - \ref EBI_TIMING_FAST
+  *                                     - \ref EBI_TIMING_NORMAL
+  *                                     - \ref EBI_TIMING_SLOW
+  *                                     - \ref EBI_TIMING_VERYSLOW
+  *                                     - \ref EBI_TIMING_SLOWEST
+  * @param[in]  u32BusMode          Set EBI bus operate mode. Valid values are:
+  *                                     - \ref EBI_OPMODE_NORMAL
+  *                                     - \ref EBI_OPMODE_CACCESS
+  *                                     - \ref EBI_OPMODE_ADSEPARATE
+  * @param[in]  u32CSActiveLevel    CS is active High/Low. Valid values are:
+  *                                     - \ref EBI_CS_ACTIVE_HIGH
+  *                                     - \ref EBI_CS_ACTIVE_LOW
+  *
+  * @return     None
+  *
+  * @details    This function is used to open specify EBI bank with different bus width, timing setting and \n
+  *             active level of CS pin to access EBI device.
+  * @note       Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
+  */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+    uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
+    uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
+    volatile uint32_t *pu32EBICTL  = (uint32_t *)( u32Index0 );
+    volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 );
+
+    if(u32DataWidth == EBI_BUSWIDTH_8BIT) {
+        *pu32EBICTL &= ~EBI_CTL_DW16_Msk;
+    } else {
+        *pu32EBICTL |= EBI_CTL_DW16_Msk;
+    }
+
+    *pu32EBICTL |= u32BusMode;
+
+    switch(u32TimingClass) {
+    case EBI_TIMING_FASTEST:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+        *pu32EBITCTL = 0x0U;
+        break;
+
+    case EBI_TIMING_VERYFAST:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                      (0x3U << EBI_CTL_TALE_Pos) ;
+        *pu32EBITCTL = 0x03003318U;
+        break;
+
+    case EBI_TIMING_FAST:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+        *pu32EBITCTL = 0x0U;
+        break;
+
+    case EBI_TIMING_NORMAL:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                      (0x3U << EBI_CTL_TALE_Pos) ;
+        *pu32EBITCTL = 0x03003318U;
+        break;
+
+    case EBI_TIMING_SLOW:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                      (0x7U << EBI_CTL_TALE_Pos) ;
+        *pu32EBITCTL = 0x07007738U;
+        break;
+
+    case EBI_TIMING_VERYSLOW:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                      (0x7U << EBI_CTL_TALE_Pos) ;
+        *pu32EBITCTL = 0x07007738U;
+        break;
+
+    case EBI_TIMING_SLOWEST:
+        *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                      (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
+                      (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                      (0x7U << EBI_CTL_TALE_Pos) ;
+        *pu32EBITCTL = 0x07007738U;
+        break;
+
+    default:
+        *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+        break;
+    }
+}
+
+/**
+  * @brief      Disable EBI on specify Bank
+  *
+  * @param[in]  u32Bank     Bank number for EBI. Valid values are:
+  *                             - \ref EBI_BANK0
+  *                             - \ref EBI_BANK1
+  *                             - \ref EBI_BANK2
+  *
+  * @return     None
+  *
+  * @details    This function is used to close specify EBI function.
+  */
+void EBI_Close(uint32_t u32Bank)
+{
+    uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U;
+    volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index );
+
+    *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+}
+
+/**
+  * @brief      Set EBI Bus Timing for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  *                                     - \ref EBI_BANK2
+  * @param[in]  u32TimingConfig     Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
+  * @param[in]  u32MclkDiv          Divider for MCLK. Valid values are:
+  *                                     - \ref EBI_MCLKDIV_1
+  *                                     - \ref EBI_MCLKDIV_2
+  *                                     - \ref EBI_MCLKDIV_4
+  *                                     - \ref EBI_MCLKDIV_8
+  *                                     - \ref EBI_MCLKDIV_16
+  *                                     - \ref EBI_MCLKDIV_32
+  *                                     - \ref EBI_MCLKDIV_64
+  *                                     - \ref EBI_MCLKDIV_128
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure specify EBI bus timing for access EBI device.
+  */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+    uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
+    uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
+    volatile uint32_t *pu32EBICTL  = (uint32_t *)( u32Index0 );
+    volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 );
+
+    *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
+    *pu32EBITCTL = u32TimingConfig;
+}
+
+/*@}*/ /* end of group M480_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_EBI_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_ebi.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,351 @@
+/**************************************************************************//**
+ * @file     ebi.h
+ * @version  V3.00
+ * @brief    M480 series External Bus Interface(EBI) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_H__
+#define __EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_EBI_Driver EBI Driver
+  @{
+*/
+
+/** @addtogroup M480_EBI_EXPORTED_CONSTANTS EBI Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Miscellaneous Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0_BASE_ADDR     0x60000000UL /*!< EBI bank0 base address \hideinitializer */
+#define EBI_BANK1_BASE_ADDR     0x60100000UL /*!< EBI bank1 base address \hideinitializer */
+#define EBI_BANK2_BASE_ADDR     0x60200000UL /*!< EBI bank2 base address \hideinitializer */
+#define EBI_MAX_SIZE            0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI bank number                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0               0UL    /*!< EBI bank 0 \hideinitializer */
+#define EBI_BANK1               1UL    /*!< EBI bank 1 \hideinitializer */
+#define EBI_BANK2               2UL    /*!< EBI bank 2 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI data bus width                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT       8UL   /*!< EBI bus width is 8-bit \hideinitializer */
+#define EBI_BUSWIDTH_16BIT      16UL  /*!< EBI bus width is 16-bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI CS Active Level                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_CS_ACTIVE_LOW       0UL    /*!< EBI CS active level is low \hideinitializer */
+#define EBI_CS_ACTIVE_HIGH      1UL    /*!< EBI CS active level is high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI MCLK divider and Timing                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1           0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
+#define EBI_MCLKDIV_2           0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
+#define EBI_MCLKDIV_4           0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
+#define EBI_MCLKDIV_8           0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
+#define EBI_MCLKDIV_16          0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
+#define EBI_MCLKDIV_32          0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
+#define EBI_MCLKDIV_64          0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
+#define EBI_MCLKDIV_128         0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
+
+#define EBI_TIMING_FASTEST      0x0UL /*!< EBI timing is the fastest \hideinitializer */
+#define EBI_TIMING_VERYFAST     0x1UL /*!< EBI timing is very fast \hideinitializer */
+#define EBI_TIMING_FAST         0x2UL /*!< EBI timing is fast \hideinitializer */
+#define EBI_TIMING_NORMAL       0x3UL /*!< EBI timing is normal  \hideinitializer */
+#define EBI_TIMING_SLOW         0x4UL /*!< EBI timing is slow \hideinitializer */
+#define EBI_TIMING_VERYSLOW     0x5UL /*!< EBI timing is very slow \hideinitializer */
+#define EBI_TIMING_SLOWEST      0x6UL /*!< EBI timing is the slowest \hideinitializer */
+
+#define EBI_OPMODE_NORMAL       0x0UL                 /*!< EBI bus operate in normal mode \hideinitializer */
+#define EBI_OPMODE_CACCESS      (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
+#define EBI_OPMODE_ADSEPARATE   (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */
+
+/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Read 8-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA8(u32Addr)            (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA8(u32Addr, u32Data)  (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA16(u32Addr)           (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA32(u32Addr)           (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 8-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA8(u32Addr)            (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA8(u32Addr, u32Data)  (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA16(u32Addr)           (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA32(u32Addr)           (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 8-bit data on EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_READ_DATA8(u32Addr)            (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA8(u32Addr, u32Data)  (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_READ_DATA16(u32Addr)           (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_READ_DATA32(u32Addr)           (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank2
+  *
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief       Enable EBI Write Buffer
+  *
+  * @param       None
+  *
+  * @return      None
+  *
+  * @details     This macro is used to improve EBI write operation for EBI bank0 and bank1.
+  * \hideinitializer
+  */
+#define EBI_ENABLE_WRITE_BUFFER()           (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk);
+
+/**
+  * @brief       Disable EBI Write Buffer
+  *
+  * @param       None
+  *
+  * @return      None
+  *
+  * @details     This macro is used to disable EBI write buffer function.
+  * \hideinitializer
+  */
+#define EBI_DISABLE_WRITE_BUFFER()          (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk);
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/*@}*/ /* end of group M480_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_EBI_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_ecap.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,111 @@
+/**************************************************************************//**
+ * @file     ecap.c
+ * @version  V3.00
+ * @brief    Enhanced Input Capture Timer (ECAP) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+  @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable ECAP function
+  * @param[in]  ecap        The pointer of the specified ECAP module.
+  * @param[in]  u32FuncMask Input capture function select
+  *                         - \ref ECAP_DISABLE_COMPARE
+  *                         - \ref ECAP_COMPARE_FUNCTION
+  * @return     None
+  * @details    This macro enable input capture function and select compare and reload function.
+  */
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask)
+{
+    /* Clear Input capture mode*/
+    ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk);
+
+    /* Enable Input Capture and set mode */
+    ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask);
+}
+
+
+
+/**
+  * @brief      Disable ECAP function
+  * @param[in]  ecap        The pointer of the specified ECAP module.
+  * @return     None
+  * @details    This macro disable input capture function.
+  */
+void ECAP_Close(ECAP_T* ecap)
+{
+    /* Disable Input Capture*/
+    ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk;
+}
+
+/**
+  * @brief This macro is used to enable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel Mask
+  *                  - \ref ECAP_CTL0_CAPIEN0_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN1_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN2_Msk
+  *                  - \ref ECAP_CTL0_OVIEN_Msk
+  *                  - \ref ECAP_CTL0_CMPIEN_Msk
+  * @return None
+  * @details This macro will enable the input channel_n interrupt.
+  */
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+    /* Enable input channel interrupt */
+    ecap->CTL0 |= (u32Mask);
+
+    /* Enable NVIC ECAP IRQ */
+    if(ecap == (ECAP_T*)ECAP0) {
+        NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn);
+    } else {
+        NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn);
+    }
+}
+
+/**
+  * @brief This macro is used to disable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel number
+  *                  - \ref ECAP_CTL0_CAPIEN0_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN1_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN2_Msk
+  *                  - \ref ECAP_CTL0_OVIEN_Msk
+  *                  - \ref ECAP_CTL0_CMPIEN_Msk
+  * @return None
+  * @details This macro will disable the input channel_n interrupt.
+  */
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+    /* Disable input channel interrupt */
+    ecap->CTL0 &= ~(u32Mask);
+
+    /* Disable NVIC ECAP IRQ */
+    if(ecap == (ECAP_T*)ECAP0) {
+        NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn);
+    } else {
+        NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn);
+    }
+}
+
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ECAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_ecap.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,457 @@
+/**************************************************************************//**
+ * @file     ecap.h
+ * @version  V3.00
+ * @brief    EnHanced Input Capture Timer(ECAP) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __ECAP_H__
+#define __ECAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+  @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants
+  @{
+*/
+
+#define ECAP_IC0    (0UL)    /*!< ECAP IC0 Unit \hideinitializer */
+#define ECAP_IC1    (1UL)    /*!< ECAP IC1 Unit \hideinitializer */
+#define ECAP_IC2    (2UL)    /*!< ECAP IC2 Unit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ECAP CTL0 constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ECAP_NOISE_FILTER_CLKDIV_1            (0UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 1  \hideinitializer */
+#define ECAP_NOISE_FILTER_CLKDIV_2            (1UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 2  \hideinitializer */
+#define ECAP_NOISE_FILTER_CLKDIV_4            (2UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 4  \hideinitializer */
+#define ECAP_NOISE_FILTER_CLKDIV_16           (3UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 16 \hideinitializer */
+#define ECAP_NOISE_FILTER_CLKDIV_32           (4UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 32  \hideinitializer */
+#define ECAP_NOISE_FILTER_CLKDIV_64           (5UL<<ECAP_CTL0_NFCLKSEL_Pos)    /*!< Noise filter clock divide by 64  \hideinitializer */
+
+
+#define ECAP_CAP_INPUT_SRC_FROM_IC            (0UL)  /*!< CAP input source from IC             \hideinitializer */
+#define ECAP_CAP_INPUT_SRC_FROM_CH            (2UL)  /*!< CAP input source from CH of QEI      \hideinitializer */
+
+#define ECAP_DISABLE_COMPARE                  (0UL<<ECAP_CTL0_CMPEN_Pos)    /*!< Input capture compare and reload function disable \hideinitializer */
+#define ECAP_COMPARE_FUNCTION                 (1UL<<ECAP_CTL0_CMPEN_Pos)    /*!< Input capture compare function  \hideinitializer */
+/*---------------------------------------------------------------------------------------------------------*/
+/* ECAP CTL1 constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ECAP_RISING_EDGE                       (0UL<<ECAP_CTL1_EDGESEL0_Pos)   /*!< ECAP capture rising edge selection                      \hideinitializer */
+#define ECAP_FALLING_EDGE                      (1UL<<ECAP_CTL1_EDGESEL0_Pos)   /*!< ECAP capture falling edge selection                     \hideinitializer */
+#define ECAP_RISING_FALLING_EDGE               (2UL<<ECAP_CTL1_EDGESEL0_Pos)   /*!< ECAP capture either rising or falling edge selection    \hideinitializer */
+
+#define ECAP_CAPTURE_TIMER_CLKDIV_1            (0UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 1   \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_4            (1UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 4   \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_16           (2UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 16  \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_32           (3UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 32  \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_64           (4UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 64  \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_96           (5UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 96  \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_112          (6UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 112 \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLKDIV_128          (7UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer clock divide by 128 \hideinitializer */
+
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK     (0UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer/clock source from CAP_CLK \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP0        (1UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer/clock source from CAP0    \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP1        (2UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer/clock source from CAP1    \hideinitializer */
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP2        (3UL<<ECAP_CTL1_CLKSEL_Pos)    /*!< ECAP capture timer/clock source from CAP2    \hideinitializer */
+
+/*@}*/ /* end of group ECAP_EXPORTED_CONSTANTS */
+
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
+  @{
+*/
+
+/**
+  * @brief This macro is used to select noise filter clock pre-divide number
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32ClkSel The noise filter clock divide number
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_1
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_2
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_4
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_16
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_32
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_64
+  * @return None
+  * @details This macro will set the sampling frequency of the noise filter cock.
+  * \hideinitializer
+  */
+#define ECAP_SET_NOISE_FILTER_CLKDIV(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel))
+
+/**
+  * @brief This macro is used to disable noise filter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the noise filter of input capture.
+  * \hideinitializer
+  */
+#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk)
+
+/**
+  * @brief This macro is used to enable noise filter
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32ClkSel Select noise filter clock divide number
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_1
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_2
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_4
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_16
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_32
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_64
+  * @return None
+  * @details This macro will enable the noise filter of input capture and set noise filter clock divide.
+  * \hideinitializer
+  */
+#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel));
+
+/**
+  * @brief This macro is used to enable input channel unit
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask   The input channel mask
+  *                  - \ref ECAP_CTL0_IC0EN_Msk
+  *                  - \ref ECAP_CTL0_IC1EN_Msk
+  *                  - \ref ECAP_CTL0_IC2EN_Msk
+  * @return None
+  * @details This macro will enable the input channel_n to input capture.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable input channel unit
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_CTL0_IC0EN_Msk
+  *                  - \ref ECAP_CTL0_IC1EN_Msk
+  *                  - \ref ECAP_CTL0_IC2EN_Msk
+  * @return None
+  * @details This macro will disable the input channel_n to input capture.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to select input channel source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @param[in] u32Src    The input source
+  *                  - \ref ECAP_CAP_INPUT_SRC_FROM_IC
+  *                  - \ref ECAP_CAP_INPUT_SRC_FROM_CH
+  * @return None
+  * @details This macro will select the input source from ICx, CPOx, CHx, ADCMPO or OPDO.
+  * \hideinitializer
+  */
+#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<<ECAP_CTL0_CAPSEL0_Pos)<<((u32Index)<<1)))
+
+/**
+  * @brief This macro is used to enable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_CTL0_CAPIEN0_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN1_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN2_Msk
+  * @return None
+  * @details This macro will enable the input channel_n interrupt.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask   The input channel mask
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @return None
+  * @details This macro will disable the input channel_n interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to enable input channel overflow interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the input channel overflow interrupt.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)
+
+/**
+  * @brief This macro is used to disable input channel overflow interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the input channel overflow interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)
+
+/**
+  * @brief This macro is used to enable input channel compare-match interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the input channel compare-match interrupt.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)
+
+/**
+  * @brief This macro is used to disable input channel compare-match interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the input channel compare-match interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)
+
+/**
+  * @brief This macro is used to start capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will start capture counter up-counting.
+  * \hideinitializer
+  */
+#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)
+
+/**
+  * @brief This macro is used to stop capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will stop capture counter up-counting.
+  * \hideinitializer
+  */
+#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)
+
+/**
+  * @brief This macro is used to set event to clear capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Event The input channel number
+  *                  - \ref ECAP_CTL0_CMPCLREN_Msk
+  *                  - \ref ECAP_CTL1_CAP0RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP1RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP2RLDEN_Msk
+  *                  - \ref ECAP_CTL1_OVRLDEN_Msk
+
+  * @return None
+  * @details This macro will enable and select compare or capture event that can clear capture counter.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \
+  if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \
+    (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \
+  else \
+    (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \
+  (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \
+  }while(0);
+
+/**
+  * @brief This macro is used to enable compare function
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the compare function.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)
+
+/**
+  * @brief This macro is used to disable compare function
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the compare function.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)
+
+/**
+  * @brief This macro is used to enable input capture function.
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable input capture timer/counter.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)
+
+/**
+  * @brief This macro is used to disable input capture function.
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable input capture timer/counter.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)
+
+/**
+  * @brief This macro is used to select input channel edge detection
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @param[in] u32Edge   The input source
+  *                  - \ref ECAP_RISING_EDGE
+  *                  - \ref ECAP_FALLING_EDGE
+  *                  - \ref ECAP_RISING_FALLING_EDGE
+  * @return None
+  * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.
+  * \hideinitializer
+  */
+#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1)))
+
+/**
+  * @brief This macro is used to select ECAP counter reload trigger source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32TrigSrc The input source
+  *                  - \ref ECAP_CTL1_CAP0RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP1RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP2RLDEN_Msk
+  *                  - \ref ECAP_CTL1_OVRLDEN_Msk
+  * @return None
+  * @details This macro will select capture counter reload trigger source.
+  * \hideinitializer
+  */
+#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc))
+
+/**
+  * @brief This macro is used to select capture timer clock divide.
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Clkdiv The input source
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_1
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_4
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_16
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_32
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_64
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_96
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_112
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_128
+  * @return None
+  * @details This macro will select capture timer clock has a pre-divider with eight divided option.
+  * \hideinitializer
+  */
+#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv))
+
+/**
+  * @brief This macro is used to select capture timer/counter clock source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32ClkSrc The input source
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2
+  * @return None
+  * @details This macro will select capture timer/clock clock source.
+  * \hideinitializer
+  */
+#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32ClkSrc))
+
+/**
+  * @brief This macro is used to read input capture status
+  * @param[in] ecap      Specify ECAP port
+  * @return Input capture status flags
+  * @details This macro will get the input capture interrupt status.
+  * \hideinitializer
+  */
+#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)
+
+/**
+  * @brief This macro is used to get input channel interrupt flag
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_STATUS_CAPTF0_Msk
+  *                  - \ref ECAP_STATUS_CAPTF1_Msk
+  *                  - \ref ECAP_STATUS_CAPTF2_Msk
+  *                  - \ref ECAP_STATUS_CAPOVF_Msk
+  *                  - \ref ECAP_STATUS_CAPCMPF_Msk
+  * @return None
+  * @details This macro will write 1 to get the input channel_n interrupt flag.
+  * \hideinitializer
+  */
+#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)
+
+/**
+  * @brief This macro is used to clear input channel interrupt flag
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_STATUS_CAPTF0_Msk
+  *                  - \ref ECAP_STATUS_CAPTF1_Msk
+  *                  - \ref ECAP_STATUS_CAPTF2_Msk
+  *                  - \ref ECAP_STATUS_CAPOVF_Msk
+  *                  - \ref ECAP_STATUS_CAPCMPF_Msk
+  * @return None
+  * @details This macro will write 1 to clear the input channel_n interrupt flag.
+  * \hideinitializer
+  */
+#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))
+
+/**
+  * @brief This macro is used to set input capture counter value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Val    Counter value
+  * @return None
+  * @details This macro will set a counter value of input capture.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))
+
+/**
+  * @brief This macro is used to get input capture counter value
+  * @param[in] ecap      Specify ECAP port
+  * @return Capture counter value
+  * @details This macro will get a counter value of input capture.
+  * \hideinitializer
+  */
+#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)
+
+/**
+  * @brief This macro is used to get input capture counter hold value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @return Capture counter hold value
+  * @details This macro will get a hold value of input capture channel_n.
+  * \hideinitializer
+  */
+#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))
+
+/**
+  * @brief This macro is used to set input capture counter compare value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Val    Input capture compare value
+  * @return None
+  * @details This macro will set a compare value of input capture counter.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))
+
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask);
+void ECAP_Close(ECAP_T* ecap);
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ECAP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ECAP_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_emac.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     emac.c
+ * @version  V1.00
+ * @brief    M480 EMAC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <string.h>
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_EMAC_Driver EMAC Driver
+  @{
+*/
+
+
+/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+  @{
+*/
+
+/* PHY Register Description */
+#define PHY_CNTL_REG    0x00UL        /*!<  PHY control register address */
+#define PHY_STATUS_REG  0x01UL        /*!<  PHY status register address */
+#define PHY_ID1_REG     0x02UL        /*!<  PHY ID1 register */
+#define PHY_ID2_REG     0x03UL        /*!<  PHY ID2 register */
+#define PHY_ANA_REG     0x04UL        /*!<  PHY auto-negotiation advertisement register */
+#define PHY_ANLPA_REG   0x05UL        /*!<  PHY auto-negotiation link partner availability register */
+#define PHY_ANE_REG     0x06UL        /*!<  PHY auto-negotiation expansion register */
+
+/* PHY Control Register */
+#define PHY_CNTL_RESET_PHY      (1UL << 15UL)
+#define PHY_CNTL_DR_100MB       (1UL << 13UL)
+#define PHY_CNTL_ENABLE_AN      (1UL << 12UL)
+#define PHY_CNTL_POWER_DOWN     (1UL << 11UL)
+#define PHY_CNTL_RESTART_AN     (1UL << 9UL)
+#define PHY_CNTL_FULLDUPLEX     (1UL << 8UL)
+
+/* PHY Status Register */
+#define PHY_STATUS_AN_COMPLETE   (1UL << 5UL)
+#define PHY_STATUS_LINK_VALID    (1UL << 2UL)
+
+/* PHY Auto-negotiation Advertisement Register */
+#define PHY_ANA_DR100_TX_FULL   (1UL << 8UL)
+#define PHY_ANA_DR100_TX_HALF   (1UL << 7UL)
+#define PHY_ANA_DR10_TX_FULL    (1UL << 6UL)
+#define PHY_ANA_DR10_TX_HALF    (1UL << 5UL)
+#define PHY_ANA_IEEE_802_3_CSMA_CD   (1UL << 0UL)
+
+/* PHY Auto-negotiation Link Partner Advertisement Register */
+#define PHY_ANLPA_DR100_TX_FULL   (1UL << 8UL)
+#define PHY_ANLPA_DR100_TX_HALF   (1UL << 7UL)
+#define PHY_ANLPA_DR10_TX_FULL    (1UL << 6UL)
+#define PHY_ANLPA_DR10_TX_HALF    (1UL << 5UL)
+
+/* EMAC Tx/Rx descriptor's owner bit */
+#define EMAC_DESC_OWN_EMAC 0x80000000UL  /*!<  Set owner to EMAC */
+#define EMAC_DESC_OWN_CPU  0x00000000UL  /*!<  Set owner to CPU */
+
+/* Rx Frame Descriptor Status */
+#define EMAC_RXFD_RTSAS   0x0080UL  /*!<  Time Stamp Available */
+#define EMAC_RXFD_RP      0x0040UL  /*!<  Runt Packet */
+#define EMAC_RXFD_ALIE    0x0020UL  /*!<  Alignment Error */
+#define EMAC_RXFD_RXGD    0x0010UL  /*!<  Receiving Good packet received */
+#define EMAC_RXFD_PTLE    0x0008UL  /*!<  Packet Too Long Error */
+#define EMAC_RXFD_CRCE    0x0002UL  /*!<  CRC Error */
+#define EMAC_RXFD_RXINTR  0x0001UL  /*!<  Interrupt on receive */
+
+/* Tx Frame Descriptor's Control bits */
+#define EMAC_TXFD_TTSEN     0x08UL      /*!<  Tx time stamp enable */
+#define EMAC_TXFD_INTEN     0x04UL      /*!<  Tx interrupt enable */
+#define EMAC_TXFD_CRCAPP    0x02UL      /*!<  Append CRC */
+#define EMAC_TXFD_PADEN     0x01UL      /*!<  Padding mode enable */
+
+/* Tx Frame Descriptor Status */
+#define EMAC_TXFD_TXINTR 0x0001UL  /*!<  Interrupt on Transmit */
+#define EMAC_TXFD_DEF    0x0002UL  /*!<  Transmit deferred  */
+#define EMAC_TXFD_TXCP   0x0008UL  /*!<  Transmission Completion  */
+#define EMAC_TXFD_EXDEF  0x0010UL  /*!<  Exceed Deferral */
+#define EMAC_TXFD_NCS    0x0020UL  /*!<  No Carrier Sense Error */
+#define EMAC_TXFD_TXABT  0x0040UL  /*!<  Transmission Abort  */
+#define EMAC_TXFD_LC     0x0080UL  /*!<  Late Collision  */
+#define EMAC_TXFD_TXHA   0x0100UL  /*!<  Transmission halted */
+#define EMAC_TXFD_PAU    0x0200UL  /*!<  Paused */
+#define EMAC_TXFD_SQE    0x0400UL  /*!<  SQE error  */
+#define EMAC_TXFD_TTSAS  0x0800UL  /*!<  Time Stamp available */
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines
+  @{
+*/
+
+/** Tx/Rx buffer descriptor structure */
+typedef struct {
+    uint32_t u32Status1;   /*!<  Status word 1 */
+    uint32_t u32Data;      /*!<  Pointer to data buffer */
+    uint32_t u32Status2;   /*!<  Status word 2 */
+    uint32_t u32Next;      /*!<  Pointer to next descriptor */
+    uint32_t u32Backup1;   /*!<  For backup descriptor fields over written by time stamp */
+    uint32_t u32Backup2;   /*!<  For backup descriptor fields over written by time stamp */
+} EMAC_DESCRIPTOR_T;
+
+/** Tx/Rx buffer structure */
+typedef struct {
+    uint8_t au8Buf[1520];
+} EMAC_FRAME_T;
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_TYPEDEF */
+
+/* local variables */
+static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE];
+static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE];
+static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE];
+static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE];
+
+
+static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc;
+static uint32_t s_u32EnableTs = 0UL;
+
+static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data);
+static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr);
+static void EMAC_PhyInit(void);
+static void EMAC_TxDescInit(void);
+static void EMAC_RxDescInit(void);
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec);
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec);
+
+/** @addtogroup M480_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+/**
+  * @brief  Trigger EMAC Rx function
+  * @param  None
+  * @return None
+  */
+#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0)
+
+/**
+  * @brief  Trigger EMAC Tx function
+  * @param  None
+  * @return None
+  */
+#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0)
+
+
+/**
+  * @brief  Write PHY register
+  * @param[in]  u32Reg PHY register number
+  * @param[in]  u32Addr PHY address, this address is board dependent
+  * @param[in] u32Data data to write to PHY register
+  * @return None
+  */
+static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data)
+{
+    /* Set data register */
+    EMAC->MIIMDAT = u32Data ;
+    /* Set PHY address, PHY register address, busy bit and write bit */
+    EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
+    /* Wait write complete by polling busy bit. */
+    while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) {
+        ;
+    }
+
+}
+
+/**
+  * @brief  Read PHY register
+  * @param[in]  u32Reg PHY register number
+  * @param[in]  u32Addr PHY address, this address is board dependent
+  * @return Value read from PHY register
+  */
+static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr)
+{
+    /* Set PHY address, PHY register address, busy bit */
+    EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
+    /* Wait read complete by polling busy bit */
+    while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) {
+        ;
+    }
+    /* Get return data */
+    return EMAC->MIIMDAT;
+}
+
+/**
+  * @brief  Initialize PHY chip, check for the auto-negotiation result.
+  * @param  None
+  * @return None
+  */
+static void EMAC_PhyInit(void)
+{
+    uint32_t reg;
+    uint32_t i = 0UL;
+
+    /* Reset Phy Chip */
+    EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY);
+
+    /* Wait until reset complete */
+    while (1) {
+        reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ;
+        if ((reg & PHY_CNTL_RESET_PHY)==0UL) {
+            break;
+        }
+    }
+    while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) {
+        if(i++ > 80000UL) {     /* Cable not connected */
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+            break;
+        }
+    }
+
+    if(i <= 80000UL) {
+        /* Configure auto negotiation capability */
+        EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
+                       PHY_ANA_DR100_TX_HALF |
+                       PHY_ANA_DR10_TX_FULL |
+                       PHY_ANA_DR10_TX_HALF |
+                       PHY_ANA_IEEE_802_3_CSMA_CD);
+        /* Restart auto negotiation */
+        EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN);
+
+        /* Wait for auto-negotiation complete */
+        while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE)) {
+            ;
+        }
+        /* Check link valid again. Some PHYs needs to check result after link valid bit set */
+        while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) {
+            ;
+        }
+
+        /* Check link partner capability */
+        reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
+        if (reg & PHY_ANLPA_DR100_TX_FULL) {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+        } else if (reg & PHY_ANLPA_DR100_TX_HALF) {
+            EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+        } else if (reg & PHY_ANLPA_DR10_TX_FULL) {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
+        } else {
+            EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
+            EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
+        }
+    }
+}
+
+/**
+  * @brief  Initial EMAC Tx descriptors and get Tx descriptor base address
+  * @param None
+  * @return None
+  */
+static void EMAC_TxDescInit(void)
+{
+    uint32_t i;
+
+    /* Get Frame descriptor's base address. */
+    EMAC->TXDSA = (uint32_t)&tx_desc[0];
+    u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0];
+
+    for(i = 0UL; i < EMAC_TX_DESC_SIZE; i++) {
+
+        if(s_u32EnableTs) {
+            tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN;
+        } else {
+            tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN;
+        }
+        tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]);
+        tx_desc[i].u32Backup1 = tx_desc[i].u32Data;
+        tx_desc[i].u32Status2 = 0UL;
+        tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1UL) % EMAC_TX_DESC_SIZE];
+        tx_desc[i].u32Backup2 = tx_desc[i].u32Next;
+
+    }
+
+}
+
+
+/**
+  * @brief  Initial EMAC Rx descriptors and get Rx descriptor base address
+  * @param None
+  * @return None
+  */
+static void EMAC_RxDescInit(void)
+{
+
+    uint32_t i;
+
+    /* Get Frame descriptor's base address. */
+    EMAC->RXDSA = (uint32_t)&rx_desc[0];
+    u32CurrentRxDesc = (uint32_t)&rx_desc[0];
+
+    for(i = 0UL; i < EMAC_RX_DESC_SIZE; i++) {
+        rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC;
+        rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]);
+        rx_desc[i].u32Backup1 = rx_desc[i].u32Data;
+        rx_desc[i].u32Status2 = 0UL;
+        rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1UL) % EMAC_RX_DESC_SIZE];
+        rx_desc[i].u32Backup2 = rx_desc[i].u32Next;
+    }
+
+}
+
+/**
+  * @brief  Convert subsecond value to nano second
+  * @param[in]  subsec Subsecond value to be convert
+  * @return Nano second
+  */
+static uint32_t EMAC_Subsec2Nsec(uint32_t subsec)
+{
+    /* 2^31 subsec == 10^9 ns */
+    uint64_t i;
+    i = 1000000000ull * (uint64_t)subsec;
+    i >>= 31;
+    return((uint32_t)i);
+}
+
+/**
+  * @brief  Convert nano second to subsecond value
+  * @param[in]  nsec Nano second to be convert
+  * @return Subsecond
+  */
+static uint32_t EMAC_Nsec2Subsec(uint32_t nsec)
+{
+    /* 10^9 ns =  2^31 subsec */
+    uint64_t i;
+    i = (1ull << 31) * nsec;
+    i /= 1000000000ull;
+    return((uint32_t)i);
+}
+
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_FUNCTIONS */
+
+
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/** @addtogroup M480_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Initialize EMAC interface, including descriptors, MAC address, and PHY.
+  * @param[in]  pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  * @note This API sets EMAC to work in RMII mode, but could configure to MII mode later with \ref EMAC_ENABLE_MII_INTF macro
+  * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with
+  *       \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT
+  * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to
+  *       enable receive and transmit function.
+  */
+void EMAC_Open(uint8_t *pu8MacAddr)
+{
+    /* Enable transmit and receive descriptor */
+    EMAC_TxDescInit();
+    EMAC_RxDescInit();
+
+    /* Set the CAM Control register and the MAC address value */
+    EMAC_SetMacAddr(pu8MacAddr);
+
+    /* Configure the MAC interrupt enable register. */
+    EMAC->INTEN = EMAC_INTEN_RXIEN_Msk |
+                  EMAC_INTEN_TXIEN_Msk |
+                  EMAC_INTEN_RXGDIEN_Msk |
+                  EMAC_INTEN_TXCPIEN_Msk |
+                  EMAC_INTEN_RXBEIEN_Msk |
+                  EMAC_INTEN_TXBEIEN_Msk |
+                  EMAC_INTEN_RDUIEN_Msk |
+                  EMAC_INTEN_TSALMIEN_Msk |
+                  EMAC_INTEN_WOLIEN_Msk;
+
+    /* Configure the MAC control register. */
+    EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |
+                EMAC_CTL_RMIIEN_Msk;
+
+    /* Accept packets for us and all broadcast and multicast packets */
+    EMAC->CAMCTL =  EMAC_CAMCTL_CMPEN_Msk |
+                    EMAC_CAMCTL_AMP_Msk |
+                    EMAC_CAMCTL_ABP_Msk;
+
+    EMAC_PhyInit();
+}
+
+/**
+  * @brief  This function stop all receive and transmit activity and disable MAC interface
+  * @param None
+  * @return None
+  */
+
+void EMAC_Close(void)
+{
+    EMAC->CTL |= EMAC_CTL_RST_Msk;
+    while(EMAC->CTL & EMAC_CTL_RST_Msk) {}
+}
+
+/**
+  * @brief  Set the device MAC address
+  * @param[in]  pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  */
+void EMAC_SetMacAddr(uint8_t *pu8MacAddr)
+{
+    EMAC_EnableCamEntry(0UL, pu8MacAddr);
+
+}
+
+/**
+  * @brief Fill a CAM entry for MAC address comparison.
+  * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it.
+  * @param[in] pu8MacAddr  Pointer to uint8_t array holds MAC address
+  * @return None
+  */
+void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[])
+{
+    uint32_t u32Lsw, u32Msw;
+    uint32_t reg;
+    u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) |
+                        ((uint32_t)pu8MacAddr[5] << 16));
+    u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24)|
+                        ((uint32_t)pu8MacAddr[1] << 16)|
+                        ((uint32_t)pu8MacAddr[2] << 8)|
+                        (uint32_t)pu8MacAddr[3]);
+
+    reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL;
+    *(uint32_t volatile *)reg = u32Msw;
+    reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL;
+    *(uint32_t volatile *)reg = u32Lsw;
+
+    EMAC->CAMEN |= (1UL << u32Entry);
+}
+
+/**
+  * @brief  Disable a specified CAM entry
+  * @param[in]  u32Entry CAM entry to be disabled
+  * @return None
+  */
+void EMAC_DisableCamEntry(uint32_t u32Entry)
+{
+    EMAC->CAMEN &= ~(1UL << u32Entry);
+}
+
+
+/**
+  * @brief Receive an Ethernet packet
+  * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+  * @param[in] pu32Size Received packet size (without 4 byte CRC).
+  * @return Packet receive success or not
+  * @retval 0 No packet available for receive
+  * @retval 1 A packet is received
+  * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+  */
+uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
+{
+    EMAC_DESCRIPTOR_T *desc;
+    uint32_t status, reg;
+    uint32_t u32Count = 0UL;
+
+    /* Clear Rx interrupt flags */
+    reg = EMAC->INTSTS;
+    EMAC->INTSTS = reg & 0xFFFFUL;  /* Clear all RX related interrupt status */
+
+    if (reg & EMAC_INTSTS_RXBEIF_Msk) {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while(1) {}
+    } else {
+
+        /* Get Rx Frame Descriptor */
+        desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+        /* If we reach last recv Rx descriptor, leave the loop */
+        if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) { /* ownership=CPU */
+
+            status = desc->u32Status1 >> 16;
+
+            /* If Rx frame is good, process received frame */
+            if(status & EMAC_RXFD_RXGD) {
+                /* lower 16 bit in descriptor status1 stores the Rx packet length */
+                *pu32Size = desc->u32Status1 & 0xFFFFUL;
+                memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
+                u32Count = 1UL;
+            } else {
+                /* Save Error status if necessary */
+                if (status & EMAC_RXFD_RP) {}
+                if (status & EMAC_RXFD_ALIE) {}
+                if (status & EMAC_RXFD_PTLE) {}
+                if (status & EMAC_RXFD_CRCE) {}
+            }
+        }
+    }
+    return(u32Count);
+}
+
+/**
+  * @brief Receive an Ethernet packet and the time stamp while it's received
+  * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
+  * @param[out] pu32Size Received packet size (without 4 byte CRC).
+  * @param[out] pu32Sec Second value while packet sent
+  * @param[out] pu32Nsec Nano second value while packet sent
+  * @return Packet receive success or not
+  * @retval 0 No packet available for receive
+  * @retval 1 A packet is received
+  * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
+  * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give
+  *       a buffer large enough to store such packet
+  */
+uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+    EMAC_DESCRIPTOR_T *desc;
+    uint32_t status, reg;
+    uint32_t u32Count = 0UL;
+
+    /* Clear Rx interrupt flags */
+    reg = EMAC->INTSTS;
+    EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */
+
+    if (reg & EMAC_INTSTS_RXBEIF_Msk) {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while(1) {}
+    } else {
+
+        /* Get Rx Frame Descriptor */
+        desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+        /* If we reach last recv Rx descriptor, leave the loop */
+        if(EMAC->CRXDSA != (uint32_t)desc) {
+            if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) { /* ownership=CPU */
+
+                status = desc->u32Status1 >> 16;
+
+                /* If Rx frame is good, process received frame */
+                if(status & EMAC_RXFD_RXGD) {
+                    /* lower 16 bit in descriptor status1 stores the Rx packet length */
+                    *pu32Size = desc->u32Status1 & 0xFFFFUL;
+                    memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
+
+                    *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+                    *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+
+                    u32Count = 1UL;
+                } else {
+                    /* Save Error status if necessary */
+                    if (status & EMAC_RXFD_RP) {}
+                    if (status & EMAC_RXFD_ALIE) {}
+                    if (status & EMAC_RXFD_PTLE) {}
+                    if (status & EMAC_RXFD_CRCE) {}
+                }
+            }
+        }
+    }
+    return(u32Count);
+}
+
+/**
+  * @brief Clean up process after a packet is received
+  * @param None
+  * @return None
+  * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process
+  * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
+  */
+void EMAC_RecvPktDone(void)
+{
+    EMAC_DESCRIPTOR_T *desc;
+    /* Get Rx Frame Descriptor */
+    desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
+
+    /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+    desc->u32Data = desc->u32Backup1;
+    desc->u32Next = desc->u32Backup2;
+
+    /* Get Next Frame Descriptor pointer to process */
+    desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+    /* Save last processed Rx descriptor */
+    u32CurrentRxDesc = (uint32_t)desc;
+
+    /* Change ownership to DMA for next use */
+    desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+    EMAC_TRIGGER_RX();
+}
+
+
+/**
+  * @brief Send an Ethernet packet
+  * @param[in] pu8Data Pointer to a buffer holds the packet to transmit
+  * @param[in] u32Size Packet size (without 4 byte CRC).
+  * @return Packet transmit success or not
+  * @retval 0 Transmit failed due to descriptor unavailable.
+  * @retval 1 Packet is copied to descriptor and triggered to transmit.
+  * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
+  */
+uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size)
+{
+    EMAC_DESCRIPTOR_T *desc;
+    uint32_t status;
+    uint32_t ret = 0UL;
+    /* Get Tx frame descriptor & data pointer */
+    desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc;
+
+    status = desc->u32Status1;
+
+    /* Check descriptor ownership */
+    if((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) {
+        memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size);
+
+        /* Set Tx descriptor transmit byte count */
+        desc->u32Status2 = u32Size;
+
+        /* Change descriptor ownership to EMAC */
+        desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
+
+        /* Get next Tx descriptor */
+        u32NextTxDesc = (uint32_t)(desc->u32Next);
+
+        /* Trigger EMAC to send the packet */
+        EMAC_TRIGGER_TX();
+        ret = 1UL;
+    }
+    return(ret);
+}
+
+
+/**
+  * @brief Clean up process after packet(s) are sent
+  * @param None
+  * @return Number of packet sent between two function calls
+  * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to
+  *          release the resource use by transmit process
+  */
+uint32_t EMAC_SendPktDone(void)
+{
+    EMAC_DESCRIPTOR_T *desc;
+    uint32_t status, reg;
+    uint32_t last_tx_desc;
+    uint32_t u32Count = 0UL;
+
+    reg = EMAC->INTSTS;
+    /* Clear Tx interrupt flags */
+    EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+    if (reg & EMAC_INTSTS_TXBEIF_Msk) {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while(1) {}
+    } else {
+        /* Process the descriptor(s). */
+        last_tx_desc = EMAC->CTXDSA ;
+        /* Get our first descriptor to process */
+        desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
+        do {
+            /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+            if(desc->u32Status1 & EMAC_DESC_OWN_EMAC) {
+                break;
+            }
+            /* Get Tx status stored in descriptor */
+            status = desc->u32Status2 >> 16UL;
+            if (status & EMAC_TXFD_TXCP) {
+                u32Count++;
+            } else {
+                /* Do nothing here on error. */
+                if (status & EMAC_TXFD_TXABT) {}
+                if (status & EMAC_TXFD_DEF) {}
+                if (status & EMAC_TXFD_PAU) {}
+                if (status & EMAC_TXFD_EXDEF) {}
+                if (status & EMAC_TXFD_NCS) {}
+                if (status & EMAC_TXFD_SQE) {}
+                if (status & EMAC_TXFD_LC) {}
+                if (status & EMAC_TXFD_TXHA) {}
+            }
+
+            /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+            desc->u32Data = desc->u32Backup1;
+            desc->u32Next = desc->u32Backup2;
+            /* go to next descriptor in link */
+            desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+        } while (last_tx_desc != (uint32_t)desc);    /* If we reach last sent Tx descriptor, leave the loop */
+        /* Save last processed Tx descriptor */
+        u32CurrentTxDesc = (uint32_t)desc;
+    }
+    return(u32Count);
+}
+
+/**
+  * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent
+  * @param[in]  pu32Sec Second value while packet sent
+  * @param[in]  pu32Nsec Nano second value while packet sent
+  * @return If a packet sent successfully
+  * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless
+  * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent
+  * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to
+  *          release the resource use by transmit process
+  */
+uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+
+    EMAC_DESCRIPTOR_T *desc;
+    uint32_t status, reg;
+    uint32_t u32Count = 0UL;
+
+    reg = EMAC->INTSTS;
+    /* Clear Tx interrupt flags */
+    EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);
+
+
+    if (reg & EMAC_INTSTS_TXBEIF_Msk) {
+        /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
+        while(1) {}
+    } else {
+        /* Process the descriptor.
+           Get our first descriptor to process */
+        desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
+
+        /* Descriptor ownership is still EMAC, so this packet haven't been send. */
+        if((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) {
+            /* Get Tx status stored in descriptor */
+            status = desc->u32Status2 >> 16UL;
+            if (status & EMAC_TXFD_TXCP) {
+                u32Count = 1UL;
+                *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */
+                *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
+            } else {
+                /* Do nothing here on error. */
+                if (status & EMAC_TXFD_TXABT) {}
+                if (status & EMAC_TXFD_DEF) {}
+                if (status & EMAC_TXFD_PAU) {}
+                if (status & EMAC_TXFD_EXDEF) {}
+                if (status & EMAC_TXFD_NCS) {}
+                if (status & EMAC_TXFD_SQE) {}
+                if (status & EMAC_TXFD_LC) {}
+                if (status & EMAC_TXFD_TXHA) {}
+            }
+
+            /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
+            desc->u32Data = desc->u32Backup1;
+            desc->u32Next = desc->u32Backup2;
+            /* go to next descriptor in link */
+            desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
+
+            /* Save last processed Tx descriptor */
+            u32CurrentTxDesc = (uint32_t)desc;
+        }
+    }
+
+    return(u32Count);
+}
+
+/**
+  * @brief  Enable IEEE1588 time stamp function and set current time
+  * @param[in]  u32Sec Second value
+  * @param[in]  u32Nsec Nano second value
+  * @return None
+  */
+void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec)
+{
+    double f;
+    uint32_t reg;
+    EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+    EMAC->UPDSEC = u32Sec;   /* Assume current time is 0 sec + 0 nano sec */
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+
+    /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns
+       Assume we want to set each tick to 100ns.
+       Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
+       Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz
+       From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0
+       So:
+        EMAC->TSIR = 0xD7;
+        EMAC->TSAR = 0x1E70C600; */
+    f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5;
+    EMAC->TSINC = (reg = (uint32_t)f);
+    f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg);
+    EMAC->TSADDEND = (uint32_t)f;
+    EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */
+}
+
+/**
+  * @brief  Disable IEEE1588 time stamp function
+  * @param None
+  * @return None
+  */
+void EMAC_DisableTS(void)
+{
+    EMAC->TSCTL = 0UL;
+}
+
+/**
+  * @brief  Get current time stamp
+  * @param[out]  pu32Sec Current second value
+  * @param[out]  pu32Nsec Current nano second value
+  * @return None
+  */
+void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec)
+{
+    /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */
+    *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC);
+    *pu32Sec = EMAC->TSSEC;
+}
+
+/**
+  * @brief  Set current time stamp
+  * @param[in]  u32Sec Second value
+  * @param[in]  u32Nsec Nano second value
+  * @return None
+  */
+void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec)
+{
+    /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */
+    EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
+    EMAC->UPDSEC = u32Sec;
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+    EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk);
+
+}
+
+/**
+  * @brief  Enable alarm function and set alarm time
+  * @param[in]  u32Sec Second value to trigger alarm
+  * @param[in]  u32Nsec Nano second value to trigger alarm
+  * @return None
+  */
+void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec)
+{
+
+    EMAC->ALMSEC = u32Sec;
+    EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+    EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+  * @brief  Disable alarm function
+  * @param  None
+  * @return None
+  */
+void EMAC_DisableAlarm(void)
+{
+
+    EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk;
+
+}
+
+/**
+  * @brief  Add a offset to current time
+  * @param[in]  u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0).
+  * @param[in]  u32Sec Second value to add to current time
+  * @param[in]  u32Nsec Nano second value to add to current time
+  * @return None
+  */
+void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec)
+{
+    EMAC->UPDSEC = u32Sec;
+    EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
+    if(u32Neg) {
+        EMAC->UPDSUBSEC |= BIT31;   /* Set bit 31 indicates this is a negative value */
+    }
+    EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk;
+
+}
+
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_EMAC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_emac.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,190 @@
+/**************************************************************************//**
+ * @file     emac.h
+ * @version  V1.00
+ * @brief    M480 EMAC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __EMAC_H__
+#define __EMAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_EMAC_Driver EMAC Driver
+  @{
+*/
+
+/** @addtogroup M480_EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
+  @{
+*/
+
+#define EMAC_PHY_ADDR     1UL    /*!<  PHY address, this address is board dependent \hideinitializer */
+#define EMAC_RX_DESC_SIZE 4UL    /*!<  Number of Rx Descriptors, should be 2 at least \hideinitializer */
+#define EMAC_TX_DESC_SIZE 4UL    /*!<  Number of Tx Descriptors, should be 2 at least \hideinitializer */
+
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Enable EMAC Tx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Enable EMAC Rx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
+
+/**
+  * @brief  Disable EMAC Tx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
+
+
+/**
+  * @brief  Disable EMAC Rx function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
+
+/**
+  * @brief  Enable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
+
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
+
+/**
+  * @brief  Enable EMAC MII interface
+  * @param  None
+  * @return None
+  * @details After calling \ref EMAC_Open, EMAC use RMII interface by default, but can switch to
+  *          MII interface by calling this macro
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_MII_INTF() (EMAC->CTL &= ~(EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk))
+
+/**
+  * @brief  Enable EMAC to receive broadcast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Disable EMAC to receive broadcast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
+
+/**
+  * @brief  Enable EMAC to receive multicast packets
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Disable EMAC Magic Packet Wakeup function
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
+
+/**
+  * @brief  Check if EMAC time stamp alarm interrupt occurred or not
+  * @param  None
+  * @return If time stamp alarm interrupt occurred or not
+  * @retval 0 Alarm interrupt does not occur
+  * @retval 1 Alarm interrupt occurred
+  * \hideinitializer
+  */
+#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
+
+/**
+  * @brief  Clear EMAC time stamp alarm interrupt flag
+  * @param  None
+  * @return None
+  * \hideinitializer
+  */
+#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
+
+
+void EMAC_Open(uint8_t *pu8MacAddr);
+void EMAC_Close(void);
+void EMAC_SetMacAddr(uint8_t *pu8MacAddr);
+void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]);
+void EMAC_DisableCamEntry(uint32_t u32Entry);
+
+uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size);
+uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_RecvPktDone(void);
+
+uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size);
+uint32_t EMAC_SendPktDone(void);
+uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+
+void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableTS(void);
+void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec);
+void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec);
+void EMAC_DisableAlarm(void);
+
+
+
+/*@}*/ /* end of group M480_EMAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_EMAC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMAC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_epwm.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1401 @@
+/**************************************************************************//**
+ * @file     epwm.c
+ * @version  V3.00
+ * $Revision: 3 $
+ * $Date: 16/06/23 11:14a $
+ * @brief    M480 series EPWM driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+  @{
+*/
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Configure EPWM capture and get the nearest unit time.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure EPWM capture and get the nearest unit time.
+ */
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+    uint32_t u32Src;
+    uint32_t u32EPWMClockSrc;
+    uint32_t u32NearestUnitTimeNsec;
+    uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU;
+
+    if(epwm == EPWM0) {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+    } else { /* (epwm == EPWM1) */
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+    }
+
+    if(u32Src == 0U) {
+        /* clock source is from PLL clock */
+        u32EPWMClockSrc = CLK_GetPLLClockFreq();
+    } else {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if(epwm == EPWM0) {
+            u32EPWMClockSrc = CLK_GetPCLK0Freq();
+        } else { /* (epwm == EPWM1) */
+            u32EPWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+
+    u32EPWMClockSrc /= 1000U;
+    for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) {
+        uint32_t u32Exit = 0U;
+        u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc;
+        if(u32NearestUnitTimeNsec < u32UnitTimeNsec) {
+            if(u16Prescale == 0x1000U) {  /* limit to the maximum unit time(nano second) */
+                u32Exit = 1U;
+            } else {
+                u32Exit = 0U;
+            }
+            if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) {
+                u32Exit = 1U;
+            } else {
+                u32Exit = 0U;
+            }
+        } else {
+            u32Exit = 1U;
+        }
+        if (u32Exit == 1U) {
+            break;
+        } else {}
+    }
+
+    /* convert to real register value */
+    /* every two channels share a prescaler */
+    u16Prescale -= 1U;
+    EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale);
+
+    /* set EPWM to down count type(edge aligned) */
+    (epwm)->CTL1 = ((epwm)->CTL1 & ~((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U));
+    /* set EPWM to auto-reload mode */
+    (epwm)->CTL1 &= ~((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum);
+    EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR);
+
+    return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
+ *       existing frequency of other channel.
+ * @note This function is used for initial stage.
+ *       To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
+}
+
+/**
+ * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency / u32Frequency2
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
+ *       existing frequency of other channel.
+ * @note This function is used for initial stage.
+ *       To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle, uint32_t u32Frequency2)
+{
+    uint32_t u32Src;
+    uint32_t u32EPWMClockSrc;
+    uint32_t i;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+    if(epwm == EPWM0) {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+    } else { /* (epwm == EPWM1) */
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+    }
+
+    if(u32Src == 0U) {
+        /* clock source is from PLL clock */
+        u32EPWMClockSrc = CLK_GetPLLClockFreq();
+    } else {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if(epwm == EPWM0) {
+            u32EPWMClockSrc = CLK_GetPCLK0Freq();
+        } else { /* (epwm == EPWM1) */
+            u32EPWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+
+    for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) { /* prescale could be 0~0xFFF */
+        // Note: Support frequency < 1
+        i = (uint64_t) u32EPWMClockSrc * u32Frequency2 / u32Frequency / u32Prescale;
+        /* If target value is larger than CNR, need to use a larger prescaler */
+        if(i < (0x10000U)) {
+            u32CNR = i;
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
+    i = u32EPWMClockSrc / (u32Prescale * u32CNR);
+
+    /* convert to real register value */
+    /* every two channels share a prescaler */
+    u32Prescale -= 1U;
+    EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+    /* set EPWM to up counter type(edge aligned) and auto-reload mode */
+    (epwm)->CTL1 = ((epwm)->CTL1 & ~(((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum)));
+
+    u32CNR -= 1U;
+    EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+    EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
+
+    (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \
+                     ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));
+    (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~(((1UL << EPWM_WGCTL1_CMPDCTL0_Pos) | (1UL << EPWM_WGCTL1_CMPUCTL0_Pos)) << (u32ChannelNum << 1U))) | \
+                     ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos));
+
+    return(i);
+}
+
+/**
+ * @brief Start EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start EPWM module.
+ */
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM module.
+ */
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) {
+        if(u32ChannelMask & (1UL << i)) {
+            (epwm)->PERIOD[i] = 0U;
+        }
+    }
+}
+
+/**
+ * @brief Stop EPWM generation immediately by clear channel enable bit
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM generation immediately by clear channel enable bit.
+ */
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ *                  - \ref EPWM_TRG_ADC_EVEN_ZERO
+ *                  - \ref EPWM_TRG_ADC_EVEN_PERIOD
+ *                  - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD
+ *                  - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP
+ *                  - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN
+ *                  - \ref EPWM_TRG_ADC_ODD_ZERO
+ *                  - \ref EPWM_TRG_ADC_ODD_PERIOD
+ *                  - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD
+ *                  - \ref EPWM_TRG_ADC_ODD_COMPARE_UP
+ *                  - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC.
+ */
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    if(u32ChannelNum < 4U) {
+        (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U));
+        (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
+    } else {
+        (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U));
+        (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U));
+    }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC.
+ */
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    if(u32ChannelNum < 4U) {
+        (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U));
+    } else {
+        (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U));
+    }
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag.
+ */
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel.
+ */
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ *                  - \ref EPWM_TRIGGER_DAC_ZERO
+ *                  - \ref EPWM_TRIGGER_DAC_PERIOD
+ *                  - \ref EPWM_TRIGGER_DAC_COMPARE_UP
+ *                  - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \
+                           EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ *                         while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ *                  - \ref EPWM_FB_EDGE_ADCRM
+ *                  - \ref EPWM_FB_EDGE_ACMP0
+ *                  - \ref EPWM_FB_EDGE_ACMP1
+ *                  - \ref EPWM_FB_EDGE_BKP0
+ *                  - \ref EPWM_FB_EDGE_BKP1
+ *                  - \ref EPWM_FB_EDGE_SYS_CSS
+ *                  - \ref EPWM_FB_EDGE_SYS_BOD
+ *                  - \ref EPWM_FB_EDGE_SYS_RAM
+ *                  - \ref EPWM_FB_EDGE_SYS_COR
+ *                  - \ref EPWM_FB_LEVEL_ADCRM
+ *                  - \ref EPWM_FB_LEVEL_ACMP0
+ *                  - \ref EPWM_FB_LEVEL_ACMP1
+ *                  - \ref EPWM_FB_LEVEL_BKP0
+ *                  - \ref EPWM_FB_LEVEL_BKP1
+ *                  - \ref EPWM_FB_LEVEL_SYS_CSS
+ *                  - \ref EPWM_FB_LEVEL_SYS_BOD
+ *                  - \ref EPWM_FB_LEVEL_SYS_RAM
+ *                  - \ref EPWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+    uint32_t i;
+
+    for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) {
+        if(u32ChannelMask & (1UL << i)) {
+            if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \
+                    (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \
+                    (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \
+                    (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) {
+                (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk));
+                (epwm)->FAILBRK |= (u32BrakeSource & 0xFU);
+            } else {
+                (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;
+            }
+        }
+
+        if(u32LevelMask & (1UL << i)) {
+            if((i & 0x1U) == 0U) {
+                /* set brake action as high level for even channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+            } else {
+                /* set brake action as high level for odd channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        } else {
+            if((i & 0x1U) == 0U) {
+                /* set brake action as low level for even channel */
+                (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+                (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+            } else {
+                /* set brake action as low level for odd channel */
+                (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+                (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        }
+    }
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CAPINEN |= u32ChannelMask;
+    (epwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CAPINEN &= ~u32ChannelMask;
+    (epwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable EPWM output generation of selected channel(s).
+ */
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable EPWM output generation of selected channel(s).
+ */
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ *              - \ref EPWM_CAPTURE_PDMA_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH
+ *              - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+    uint32_t u32IsOddCh;
+    u32IsOddCh = u32ChannelNum & 0x1U;
+    (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \
+                      (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \
+                        u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ */
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+    /* every two channels share the same setting */
+    (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
+    (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    /* every two channels shares the same setting */
+    (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
+            (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ *              - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ *              - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+    (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
+{
+    (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ *              - \ref EPWM_IFA_ZERO_POINT
+ *              - \ref EPWM_IFA_PERIOD_POINT
+ *              - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT
+ *              - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ */
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+    (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \
+                                  (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) );
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ */
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTEN |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTEN &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTSTS = (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ */
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->APDMACTL |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ *              - \ref EPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref EPWM_LOAD_MODE_WINDOW
+ *              - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ *              - \ref EPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref EPWM_LOAD_MODE_WINDOW
+ *              - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc EPWM synchronize source selection.
+ *              - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ *              - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ *              - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ *              - \ref EPWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment  after synchronizing.
+ *              - \ref EPWM_PHS_DIR_DECREMENT
+ *              - \ref EPWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+    /* every two channels shares the same setting */
+    u32ChannelNum >>= 1U;
+    (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \
+                    (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)));
+    (epwm)->PHS[(u32ChannelNum)] = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) {
+        if(u32ChannelMask & (1UL << i)) {
+            (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
+        }
+    }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) {
+        if(u32ChannelMask & (1UL << i)) {
+            (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
+        }
+    }
+}
+
+/**
+ * @brief Enable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ *            The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref EPWM_NF_CLK_DIV_1
+ *              - \ref EPWM_NF_CLK_DIV_2
+ *              - \ref EPWM_NF_CLK_DIV_4
+ *              - \ref EPWM_NF_CLK_DIV_8
+ *              - \ref EPWM_NF_CLK_DIV_16
+ *              - \ref EPWM_NF_CLK_DIV_32
+ *              - \ref EPWM_NF_CLK_DIV_64
+ *              - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \
+                   ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
+{
+    (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to enable EPWM SYNC input pin inverse function.
+ */
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
+{
+    (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC input pin inverse function.
+ */
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
+{
+    (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk);
+}
+
+/**
+ * @brief Set EPWM clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel EPWM external clock source.
+ *              - \ref EPWM_CLKSRC_EPWM_CLK
+ *              - \ref EPWM_CLKSRC_TIMER0
+ *              - \ref EPWM_CLKSRC_TIMER1
+ *              - \ref EPWM_CLKSRC_TIMER2
+ *              - \ref EPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set EPWM clock source.
+ * @note Every two channels share the same setting.
+ * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1.
+ */
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+    (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \
+                     (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U));
+}
+
+/**
+ * @brief Enable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref EPWM_NF_CLK_DIV_1
+ *              - \ref EPWM_NF_CLK_DIV_2
+ *              - \ref EPWM_NF_CLK_DIV_4
+ *              - \ref EPWM_NF_CLK_DIV_8
+ *              - \ref EPWM_NF_CLK_DIV_16
+ *              - \ref EPWM_NF_CLK_DIV_32
+ *              - \ref EPWM_NF_CLK_DIV_64
+ *              - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM brake noise filter function.
+ */
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \
+                  (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Disable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake noise filter function.
+ */
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Enable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable EPWM brake pin inverse function.
+ */
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U));
+}
+
+/**
+ * @brief Disable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake pin inverse function.
+ */
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set EPWM brake pin source
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set EPWM brake pin source.
+ */
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+    (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U)));
+}
+
+/**
+ * @brief Set EPWM leading edge blanking function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32TrigSrcSel Leading edge blanking source selection.
+ *              - \ref EPWM_LEBCTL_SRCEN0
+ *              - \ref EPWM_LEBCTL_SRCEN2
+ *              - \ref EPWM_LEBCTL_SRCEN4
+ *              - \ref EPWM_LEBCTL_SRCEN0_2
+ *              - \ref EPWM_LEBCTL_SRCEN0_4
+ *              - \ref EPWM_LEBCTL_SRCEN2_4
+ *              - \ref EPWM_LEBCTL_SRCEN0_2_4
+ * @param[in] u32TrigType  Leading edge blanking trigger type.
+ *              - \ref EPWM_LEBCTL_TRGTYPE_RISING
+ *              - \ref EPWM_LEBCTL_TRGTYPE_FALLING
+ *              - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING
+ * @param[in] u32BlankingCnt  Leading Edge Blanking Counter. Valid values are between 1~512.
+                              This counter value decides leading edge blanking window size, and this counter clock base is ECLK.
+ * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE).
+ *              - \ref FALSE
+ *              - \ref TRUE
+ * @return None
+ * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition.
+ * @note EPWM leading edge blanking function is only used for brake source from ACMP.
+ */
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
+{
+    (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable);
+    /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */
+    (epwm)->LEBCNT = (u32BlankingCnt) - 1U;
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_epwm.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,621 @@
+/**************************************************************************//**
+ * @file     epwm.h
+ * @version  V3.00
+ * @brief    M480 series EPWM driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EPWM_H__
+#define __EPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+  @{
+*/
+
+/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
+  @{
+*/
+#define EPWM_CHANNEL_NUM                          (6U)      /*!< EPWM channel number \hideinitializer */
+#define EPWM_CH_0_MASK                            (0x1U)    /*!< EPWM channel 0 mask \hideinitializer */
+#define EPWM_CH_1_MASK                            (0x2U)    /*!< EPWM channel 1 mask \hideinitializer */
+#define EPWM_CH_2_MASK                            (0x4U)    /*!< EPWM channel 2 mask \hideinitializer */
+#define EPWM_CH_3_MASK                            (0x8U)    /*!< EPWM channel 3 mask \hideinitializer */
+#define EPWM_CH_4_MASK                            (0x10U)   /*!< EPWM channel 4 mask \hideinitializer */
+#define EPWM_CH_5_MASK                            (0x20U)   /*!< EPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_UP_COUNTER                           (0U)      /*!< Up counter type \hideinitializer */
+#define EPWM_DOWN_COUNTER                         (1U)      /*!< Down counter type \hideinitializer */
+#define EPWM_UP_DOWN_COUNTER                      (2U)      /*!< Up-Down counter type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Aligned Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_EDGE_ALIGNED                         (1U)      /*!< EPWM working in edge aligned type(down count) \hideinitializer */
+#define EPWM_CENTER_ALIGNED                       (2U)      /*!< EPWM working in center aligned type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_OUTPUT_NOTHING                       (0U)      /*!< EPWM output nothing \hideinitializer */
+#define EPWM_OUTPUT_LOW                           (1U)      /*!< EPWM output low \hideinitializer */
+#define EPWM_OUTPUT_HIGH                          (2U)      /*!< EPWM output high \hideinitializer */
+#define EPWM_OUTPUT_TOGGLE                        (3U)      /*!< EPWM output toggle \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Synchronous Start Function Control Constant Definitions                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SSCTL_SSRC_EPWM0                      (0U<<EPWM_SSCTL_SSRC_Pos)    /*!< Synchronous start source comes from EPWM0 \hideinitializer */
+#define EPWM_SSCTL_SSRC_EPWM1                      (1U<<EPWM_SSCTL_SSRC_Pos)    /*!< Synchronous start source comes from EPWM0 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Trigger Source Select Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_TRG_ADC_EVEN_ZERO                           (0U)     /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */
+#define EPWM_TRG_ADC_EVEN_PERIOD                         (1U)     /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */
+#define EPWM_TRG_ADC_EVEN_ZERO_PERIOD                    (2U)     /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
+#define EPWM_TRG_ADC_EVEN_COMPARE_UP                     (3U)     /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
+#define EPWM_TRG_ADC_EVEN_COMPARE_DOWN                   (4U)     /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
+#define EPWM_TRG_ADC_ODD_ZERO                            (5U)     /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */
+#define EPWM_TRG_ADC_ODD_PERIOD                          (6U)     /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */
+#define EPWM_TRG_ADC_ODD_ZERO_PERIOD                     (7U)     /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */
+#define EPWM_TRG_ADC_ODD_COMPARE_UP                      (8U)     /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
+#define EPWM_TRG_ADC_ODD_COMPARE_DOWN                    (9U)     /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_0_FREE_CMP_UP                    (10U)    /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN                  (11U)    /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_2_FREE_CMP_UP                    (12U)    /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN                  (13U)    /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_4_FREE_CMP_UP                    (14U)    /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */
+#define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN                  (15U)    /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */
+
+#define EPWM_TRIGGER_DAC_ZERO                            (0x1U)           /*!< EPWM trigger ADC while counter down count to 0  \hideinitializer */
+#define EPWM_TRIGGER_DAC_PERIOD                          (0x100U)         /*!< EPWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
+#define EPWM_TRIGGER_DAC_COMPARE_UP                      (0x10000U)       /*!< EPWM trigger ADC while counter up count to CMPDAT \hideinitializer */
+#define EPWM_TRIGGER_DAC_COMPARE_DOWN                    (0x1000000U)     /*!< EPWM trigger ADC while counter down count to CMPDAT \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Fail brake Control Constant Definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_FB_EDGE_ACMP0                        (EPWM_BRKCTL0_1_CPO0EBEN_Msk)    /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_ACMP1                        (EPWM_BRKCTL0_1_CPO1EBEN_Msk)    /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_BKP0                         (EPWM_BRKCTL0_1_BRKP0EEN_Msk)    /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_BKP1                         (EPWM_BRKCTL0_1_BRKP1EEN_Msk)    /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_ADCRM                        (EPWM_BRKCTL0_1_ADCEBEN_Msk)     /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_SYS_CSS                      (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk)    /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_SYS_BOD                      (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk)    /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_SYS_RAM                      (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk)    /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */
+#define EPWM_FB_EDGE_SYS_COR                      (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk)    /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
+
+#define EPWM_FB_LEVEL_ACMP0                       (EPWM_BRKCTL0_1_CPO0LBEN_Msk)    /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_ACMP1                       (EPWM_BRKCTL0_1_CPO1LBEN_Msk)    /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_BKP0                        (EPWM_BRKCTL0_1_BRKP0LEN_Msk)    /*!< BKP0 pin as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_BKP1                        (EPWM_BRKCTL0_1_BRKP1LEN_Msk)    /*!< BKP1 pin as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_ADCRM                       (EPWM_BRKCTL0_1_ADCLBEN_Msk)     /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_SYS_CSS                     (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk)    /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_SYS_BOD                     (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk)    /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_SYS_RAM                     (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk)    /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
+#define EPWM_FB_LEVEL_SYS_COR                     (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk)    /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
+
+#define EPWM_FB_EDGE                              (0U)    /*!< edge-detect fault brake \hideinitializer */
+#define EPWM_FB_LEVEL                             (8U)    /*!< level-detect fault brake \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Leading Edge Blanking Control Constant Definitions                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_LEBCTL_TRGTYPE_RISING              (0U<<EPWM_LEBCTL_TRGTYPE_Pos)    /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */
+#define EPWM_LEBCTL_TRGTYPE_FALLING             (1U<<EPWM_LEBCTL_TRGTYPE_Pos)    /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */
+#define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING   (2U<<EPWM_LEBCTL_TRGTYPE_Pos)    /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0                      (EPWM_LEBCTL_SRCEN0_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN2                      (EPWM_LEBCTL_SRCEN2_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN4                      (EPWM_LEBCTL_SRCEN4_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_2                    (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_4                    (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN2_4                    (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_2_4                  (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk)    /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Capture Control Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_CAPTURE_INT_RISING_LATCH             (1U)        /*!< EPWM capture interrupt if channel has rising transition \hideinitializer */
+#define EPWM_CAPTURE_INT_FALLING_LATCH            (0x100U)    /*!< EPWM capture interrupt if channel has falling transition \hideinitializer */
+
+#define EPWM_CAPTURE_PDMA_RISING_LATCH            (0x2U)      /*!< EPWM capture rising latched data transfer by PDMA \hideinitializer */
+#define EPWM_CAPTURE_PDMA_FALLING_LATCH           (0x4U)      /*!< EPWM capture falling latched data transfer by PDMA \hideinitializer */
+#define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH    (0x6U)      /*!< EPWM capture rising and falling latched data transfer by PDMA \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Duty Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP        (1U << EPWM_INTEN0_CMPDIEN0_Pos)   /*!< EPWM duty interrupt triggered if down count match comparator \hideinitializer */
+#define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP          (1U << EPWM_INTEN0_CMPUIEN0_Pos)   /*!< EPWM duty interrupt triggered if up down match comparator \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Interrupt Flag Accumulator Constant Definitions                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_IFA_ZERO_POINT                  (0U)         /*!< EPWM counter equal to zero  \hideinitializer */
+#define EPWM_IFA_PERIOD_POINT                (1U)         /*!< EPWM counter equal to period \hideinitializer */
+#define EPWM_IFA_COMPARE_UP_COUNT_POINT      (2U)         /*!< EPWM counter up count to comparator value \hideinitializer */
+#define EPWM_IFA_COMPARE_DOWN_COUNT_POINT    (3U)         /*!< EPWM counter down count to comparator value \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Load Mode Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_LOAD_MODE_IMMEDIATE                  (1U << EPWM_CTL0_IMMLDEN0_Pos)    /*!< EPWM immediately load mode \hideinitializer */
+#define EPWM_LOAD_MODE_WINDOW                     (1U << EPWM_CTL0_WINLDEN0_Pos)    /*!< EPWM window load mode \hideinitializer */
+#define EPWM_LOAD_MODE_CENTER                     (1U << EPWM_CTL0_CTRLD0_Pos)      /*!< EPWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Synchronize Control Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC          (0U)    /*!< Synchronize source from SYNC_IN or SWSYNC  \hideinitializer */
+#define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO          (1U)    /*!< Synchronize source from counter equal to 0  \hideinitializer */
+#define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR    (2U)    /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
+#define EPWM_SYNC_OUT_DISABLE                     (3U)    /*!< SYNC_OUT will not be generated \hideinitializer */
+#define EPWM_PHS_DIR_DECREMENT                    (0U)    /*!< EPWM counter count decrement  \hideinitializer */
+#define EPWM_PHS_DIR_INCREMENT                    (1U)    /*!< EPWM counter count increment  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Noise Filter Clock Divide Select Constant Definitions                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_NF_CLK_DIV_1                         (0U)    /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
+#define EPWM_NF_CLK_DIV_2                         (1U)    /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
+#define EPWM_NF_CLK_DIV_4                         (2U)    /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
+#define EPWM_NF_CLK_DIV_8                         (3U)    /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
+#define EPWM_NF_CLK_DIV_16                        (4U)    /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
+#define EPWM_NF_CLK_DIV_32                        (5U)    /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
+#define EPWM_NF_CLK_DIV_64                        (6U)    /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
+#define EPWM_NF_CLK_DIV_128                       (7U)    /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Clock Source Select Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_CLKSRC_EPWM_CLK                       (0U)    /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */
+#define EPWM_CLKSRC_TIMER0                        (1U)    /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER1                        (2U)    /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER2                        (3U)    /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER3                        (4U)    /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */
+
+
+/*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief This macro enable complementary mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to enable complementary mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
+
+/**
+ * @brief This macro disable complementary mode, and enable independent mode.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable complementary mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
+
+/**
+ * @brief This macro enable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to enable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32SyncSrc Synchronous start source selection, valid values are:
+ *              - \ref EPWM_SSCTL_SSRC_EPWM0
+ *              - \ref EPWM_SSCTL_SSRC_EPWM1
+ * @return None
+ * @details This macro is used to enable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \
+    do{ \
+        int i;\
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) \
+                (epwm)->SSCTL &= ~(1UL << i); \
+        } \
+    }while(0)
+
+/**
+ * @brief This macro enable EPWM counter synchronous start counting function.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time.
+ *          To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) (*(__IO uint32_t *) (&((epwm)->RCAPDAT0) + ((u32ChannelNum) << 1)))
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) (*(__IO uint32_t *) (&((epwm)->FCAPDAT0) + ((u32ChannelNum) << 1)))
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \
+    { \
+        (epwm)->MSKEN = (u32ChannelMask); \
+        (epwm)->MSK = (u32LevelMask); \
+    }
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ *       The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) (epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)
+
+/**
+ * @brief This macro get the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @details This macro is used to get the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ *       The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U])
+ 
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro get the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the comparator of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * @note EPWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR)  ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro get the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the period of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the period of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CNR(epwm, u32ChannelNum)  ((epwm)->PERIOD[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the EPWM aligned type
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType EPWM aligned type, valid values are:
+ *              - \ref EPWM_EDGE_ALIGNED
+ *              - \ref EPWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the EPWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \
+   do{ \
+        int i; \
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) \
+                (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
+        } \
+    }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+   do{ \
+        int i; \
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) { \
+                (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
+                (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
+                (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
+                (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
+            } \
+        } \
+    }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * \hideinitializer
+ */
+#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \
+    ((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \
+    ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EPWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm,
+                                  uint32_t u32ChannelNum,
+                                  uint32_t u32Frequency,
+                                  uint32_t u32DutyCycle,
+                                  uint32_t u32Frequency2);
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType);
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm);
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm);
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm);
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EPWM_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_fmc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,756 @@
+/**************************************************************************//**
+ * @file     fmc.c
+ * @version  V1.00
+ * @brief    M480 series FMC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_FMC_Driver FMC Driver
+  @{
+*/
+
+
+/** @addtogroup M480_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief Disable FMC ISP function.
+  * @return None
+  */
+void FMC_Close(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+  * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes.
+  * @param[in]  u32PageAddr Address of the flash page to be erased.
+  *             It must be a 4096 bytes aligned address.
+  * @return ISP page erase success or not.
+  * @retval   0  Success
+  * @retval   -1  Erase failed
+  */
+int32_t FMC_Erase(uint32_t u32PageAddr)
+{
+    int32_t  ret = 0;
+
+    if (u32PageAddr == FMC_SPROM_BASE) {
+        ret = FMC_Erase_SPROM();
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+        FMC->ISPADDR = u32PageAddr;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+            FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+    return ret;
+}
+
+
+/**
+  * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes.
+  * @return   SPROM page erase success or not.
+  * @retval   0  Success
+  * @retval   -1  Erase failed
+  */
+int32_t FMC_Erase_SPROM(void)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+    FMC->ISPADDR = FMC_SPROM_BASE;
+    FMC->ISPDAT = 0x0055AA03UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+/**
+  * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages.
+  * @param[in]  u32BlockAddr  Address of the flash block to be erased.
+  *             It must be a 4 pages aligned address.
+  * @return ISP page erase success or not.
+  * @retval   0  Success
+  * @retval   -1  Erase failed
+  */
+int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE;
+    FMC->ISPADDR = u32BlockAddr;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+/**
+  * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.
+  * @param[in]  u32BankAddr Base address of the flash bank to be erased.
+  * @return ISP page erase success or not.
+  * @retval   0  Success
+  * @retval   -1  Erase failed
+  */
+int32_t FMC_Erase_Bank(uint32_t u32BankAddr)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
+    FMC->ISPADDR = u32BankAddr;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+/**
+  * @brief Get the current boot source.
+  * @return The current boot source.
+  * @retval   0  Is boot from APROM.
+  * @retval   1  Is boot from LDROM.
+  */
+int32_t FMC_GetBootSource (void)
+{
+    int32_t  ret = 0;
+
+    if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) {
+        ret = 1;
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief Enable FMC ISP function
+  * @return None
+  */
+void FMC_Open(void)
+{
+    FMC->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+  * @brief Execute FMC_ISPCMD_READ command to read a word from flash.
+  * @param[in]  u32Addr Address of the flash location to be read.
+  *             It must be a word aligned address.
+  * @return The word data read from specified flash address.
+  */
+uint32_t FMC_Read(uint32_t u32Addr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC->ISPDAT;
+}
+
+
+/**
+  * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash.
+  * @param[in]  u32addr   Address of the flash location to be read.
+  *             It must be a double-word aligned address.
+  * @param[out] u32data0  Place holder of word 0 read from flash address u32addr.
+  * @param[out] u32data1  Place holder of word 0 read from flash address u32addr+4.
+  * @return   0   Success
+  * @return   -1  Failed
+  */
+int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_READ_64;
+    FMC->ISPADDR    = u32addr;
+    FMC->ISPDAT = 0x0UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+        FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+        ret = -1;
+    } else {
+        *u32data0 = FMC->MPDAT0;
+        *u32data1 = FMC->MPDAT1;
+    }
+    return ret;
+}
+
+
+/**
+  * @brief    Read company ID.
+  * @retval   The company ID.
+  */
+uint32_t FMC_ReadCID(void)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_CID;
+    FMC->ISPADDR = 0x0UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC->ISPDAT;
+}
+
+
+/**
+  * @brief    Read product ID.
+  * @retval   The product ID.
+  */
+uint32_t FMC_ReadPID(void)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_PID;
+    FMC->ISPADDR = 0x04UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC->ISPDAT;
+}
+
+
+/**
+  * @brief    This function reads one of the four UCID.
+  * @param[in]   u32Index  Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+  * @retval   The UCID.
+  */
+uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+    FMC->ISPADDR = (0x04UL * u32Index) + 0x10UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC->ISPDAT;
+}
+
+
+/**
+  * @brief    This function reads one of the three UID.
+  * @param[in]  u32Index Index of the UID to read. u32Index must be 0, 1, or 2.
+  * @retval   The UID.
+  */
+uint32_t FMC_ReadUID(uint32_t u32Index)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+    FMC->ISPADDR = 0x04UL * u32Index;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC->ISPDAT;
+}
+
+
+/**
+  * @brief    Get the base address of Data Flash if enabled.
+  * @retval   The base address of Data Flash
+  */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+    return FMC->DFBA;
+}
+
+
+/**
+  * @brief    This function will force re-map assigned flash page to CPU address 0x0.
+  * @param[in]  u32PageAddr Address of the page to be mapped to CPU address 0x0.
+  * @return  None
+  */
+void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_VECMAP;
+    FMC->ISPADDR = u32PageAddr;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+}
+
+
+/**
+  * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.
+  * @param[in]  u32Addr Address of the flash location to be programmed.
+  *             It must be a word aligned address.
+  * @param[in]  u32Data The word data to be programmed.
+  * @return None
+  */
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+    FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPDAT = u32Data;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+    while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+}
+
+/**
+  * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.
+  * @param[in]  u32addr Address of the flash location to be programmed.
+  *             It must be a double-word aligned address.
+  * @param[in]  u32data0   The word data to be programmed to flash address u32addr.
+  * @param[in]  u32data1   The word data to be programmed to flash address u32addr+4.
+  * @return   0   Success
+  * @return   -1  Failed
+  */
+int32_t FMC_Write_64(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD  = FMC_ISPCMD_PROGRAM_64;
+    FMC->ISPADDR = u32addr;
+    FMC->MPDAT0  = u32data0;
+    FMC->MPDAT1  = u32data1;
+    FMC->ISPTRG  = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+        FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+
+/**
+  * @brief Program a 64-bits data to the specified OTP.
+  * @param[in] otp_num    The OTP number.
+  * @param[in] low_word   Low word of the 64-bits data.
+  * @param[in] high_word   Low word of the 64-bits data.
+  * @retval   0   Success
+  * @retval   -1  Program failed.
+  * @retval   -2  Invalid OTP number.
+  */
+int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
+{
+    int32_t  ret = 0;
+
+    if (otp_num > 255UL) {
+        ret = -2;
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL;
+        FMC->ISPDAT = low_word;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL;
+        FMC->ISPDAT = high_word;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    return ret;
+}
+
+/**
+  * @brief  Read the 64-bits data from the specified OTP.
+  * @param[in] otp_num    The OTP number.
+  * @param[in] low_word   Low word of the 64-bits data.
+  * @param[in] high_word   Low word of the 64-bits data.
+  * @retval   0   Success
+  * @retval   -1  Read failed.
+  * @retval   -2  Invalid OTP number.
+  */
+int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
+{
+    int32_t  ret = 0;
+
+    if (otp_num > 255UL) {
+        ret = -2;
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_READ_64;
+        FMC->ISPADDR    = FMC_OTP_BASE + otp_num * 8UL ;
+        FMC->ISPDAT = 0x0UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+        if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        } else {
+            *low_word = FMC->MPDAT0;
+            *high_word = FMC->MPDAT1;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief  Lock the specified OTP.
+  * @param[in] otp_num    The OTP number.
+  * @retval   0   Success
+  * @retval   -1  Failed to write OTP lock bits.
+  * @retval   -2  Invalid OTP number.
+  */
+int32_t FMC_Lock_OTP(uint32_t otp_num)
+{
+    int32_t  ret = 0;
+
+    if (otp_num > 255UL) {
+        ret = -2;
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+        FMC->ISPDAT = 0UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief  Check the OTP is locked or not.
+  * @param[in] otp_num    The OTP number.
+  * @retval   1   OTP is locked.
+  * @retval   0   OTP is not locked.
+  * @retval   -1  Failed to read OTP lock bits.
+  * @retval   -2  Invalid OTP number.
+  */
+int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
+{
+    int32_t  ret = 0;
+
+    if (otp_num > 255UL) {
+        ret = -2;
+    }
+
+    if (ret == 0) {
+        FMC->ISPCMD = FMC_ISPCMD_READ;
+        FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        } else {
+            if (FMC->ISPDAT != 0xFFFFFFFFUL) {
+                ret = 1;   /* Lock work was progrmmed. OTP was locked. */
+            }
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief Execute FMC_ISPCMD_READ command to read User Configuration.
+  * @param[out]  u32Config A two-word array.
+  *              u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+  * @param[in] u32Count Available word count in u32Config.
+  * @return Success or not.
+  * @retval   0  Success.
+  * @retval   -1  Invalid parameter.
+  */
+int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+    int32_t   ret = 0;
+
+    u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
+
+    if (u32Count < 2UL) {
+        ret = -1;
+    } else {
+        u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL);
+    }
+    return ret;
+}
+
+
+/**
+  * @brief Execute ISP commands to erase then write User Configuration.
+  * @param[in] u32Config   A two-word array.
+  *            u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+  * @param[in] u32Count  Always be 2 in this BSP.
+  * @return Success or not.
+  * @retval   0  Success.
+  * @retval   -1  Invalid parameter.
+  */
+int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+    FMC_ENABLE_CFG_UPDATE();
+    FMC_Erase(FMC_CONFIG_BASE);
+    FMC_Write(FMC_CONFIG_BASE, u32Config[0]);
+    FMC_Write(FMC_CONFIG_BASE+4UL, u32Config[1]);
+    FMC_DISABLE_CFG_UPDATE();
+    return 0;
+}
+
+
+/**
+  * @brief Run CRC32 checksum calculation and get result.
+  * @param[in] u32addr   Starting flash address. It must be a page aligned address.
+  * @param[in] u32count  Byte count of flash to be calculated. It must be multiple of 512 bytes.
+  * @return Success or not.
+  * @retval   0           Success.
+  * @retval   0xFFFFFFFF  Invalid parameter.
+  */
+uint32_t  FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
+{
+    uint32_t   ret;
+
+    if ((u32addr % 512UL) || (u32count % 512UL)) {
+        ret = 0xFFFFFFFF;
+    } else {
+        FMC->ISPCMD  = FMC_ISPCMD_RUN_CKS;
+        FMC->ISPADDR = u32addr;
+        FMC->ISPDAT  = u32count;
+        FMC->ISPTRG  = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+        FMC->ISPCMD = FMC_ISPCMD_READ_CKS;
+        FMC->ISPADDR    = u32addr;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+        ret = FMC->ISPDAT;
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief Run flash all one verification and get result.
+  * @param[in] u32addr   Starting flash address. It must be a page aligned address.
+  * @param[in] u32count  Byte count of flash to be calculated. It must be multiple of 512 bytes.
+  * @retval   READ_ALLONE_YES      The contents of verified flash area are 0xFFFFFFFF.
+  * @retval   READ_ALLONE_NOT  Some contents of verified flash area are not 0xFFFFFFFF.
+  * @retval   READ_ALLONE_CMD_FAIL  Unexpected error occurred.
+  */
+uint32_t  FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
+{
+    uint32_t  ret = READ_ALLONE_CMD_FAIL;
+
+    FMC->ISPSTS = 0x80UL;   /* clear check all one bit */
+
+    FMC->ISPCMD   = FMC_ISPCMD_RUN_ALL1;
+    FMC->ISPADDR  = u32addr;
+    FMC->ISPDAT   = u32count;
+    FMC->ISPTRG   = FMC_ISPTRG_ISPGO_Msk;
+
+    while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    do {
+        FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
+        FMC->ISPADDR    = u32addr;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+    }  while (FMC->ISPDAT == 0UL);
+
+    if (FMC->ISPDAT == READ_ALLONE_YES) {
+        ret = FMC->ISPDAT;
+    }
+
+    if (FMC->ISPDAT == READ_ALLONE_NOT) {
+        ret = FMC->ISPDAT;
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief    Setup security key.
+  * @param[in] key      Key 0~2 to be setup.
+  * @param[in] kpmax    Maximum unmatched power-on counting number.
+  * @param[in] kemax    Maximum unmatched counting number.
+  * @param[in] lock_CONFIG   1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.
+  * @param[in] lock_SPROM    1: Security key lock SPROM to write-protect. 0: Don't lock SPROM.
+  * @retval   0     Success.
+  * @retval   -1    Key is locked. Cannot overwrite the current key.
+  * @retval   -2    Failed to erase flash.
+  * @retval   -3    Failed to program key.
+  * @retval   -4    Key lock function failed.
+  * @retval   -5    CONFIG lock function failed.
+  * @retval   -6    SPROM lock function failed.
+  * @retval   -7    KPMAX function failed.
+  * @retval   -8    KEMAX function failed.
+  */
+int32_t  FMC_SKey_Setup(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
+                        const int32_t lock_CONFIG, const int32_t lock_SPROM)
+{
+    uint32_t  lock_ctrl = 0UL;
+    uint32_t  u32KeySts;
+    int32_t   ret = 0;
+
+    if (FMC->KPKEYSTS != 0x200UL) {
+        ret = -1;
+    }
+
+    if (FMC_Erase(FMC_KPROM_BASE)) {
+        ret = -2;
+    }
+
+    if (FMC_Erase(FMC_KPROM_BASE+0x200UL)) {
+        ret = -3;
+    }
+
+    if (!lock_CONFIG) {
+        lock_ctrl |= 0x1UL;
+    }
+
+    if (!lock_SPROM) {
+        lock_ctrl |= 0x2UL;
+    }
+
+    if (ret == 0) {
+        FMC_Write(FMC_KPROM_BASE, key[0]);
+        FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]);
+        FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]);
+        FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax);
+        FMC_Write(FMC_KPROM_BASE+0x10UL, kemax);
+        FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl);
+
+        while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+        u32KeySts = FMC->KPKEYSTS;
+
+        if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) {
+            /* Security key lock failed! */
+            ret = -4;
+        } else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||
+                   ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) {
+            /* CONFIG lock failed! */
+            ret = -5;
+        } else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) ||
+                   ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) {
+            /* CONFIG lock failed! */
+            ret = -6;
+        } else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) {
+            /* KPMAX failed! */
+            ret = -7;
+        } else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) {
+            /* KEMAX failed! */
+            ret = -8;
+        }
+    }
+    return ret;
+}
+
+
+/**
+  * @brief    Execute security key comparison.
+  * @param[in] key  Key 0~2 to be compared.
+  * @retval   0     Key matched.
+  * @retval   -1    Forbidden. Times of key comparison mismatch reach the maximum count.
+  * @retval   -2    Key mismatched.
+  * @retval   -3    No security key lock. Key comparison is not required.
+  */
+int32_t  FMC_SKey_Compare(uint32_t key[3])
+{
+    uint32_t  u32KeySts;
+    int32_t   ret = 0;
+
+    if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) {
+        /* FMC_SKey_Compare - FORBID!  */
+        ret = -1;
+    }
+
+    if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) {
+        /* FMC_SKey_Compare - key is not locked!  */
+        ret = -3;
+    }
+
+    if (ret == 0) {
+        FMC->KPKEY0 = key[0];
+        FMC->KPKEY1 = key[1];
+        FMC->KPKEY2 = key[2];
+        FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk;
+
+        while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+        u32KeySts = FMC->KPKEYSTS;
+
+        if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) {
+            /* Key mismatched! */
+            ret = -2;
+        } else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) {
+            /* Key matched, but still be locked! */
+            ret = -2;
+        }
+    }
+    return ret;
+}
+
+
+/*@}*/ /* end of group M480_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_FMC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_fmc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,159 @@
+/**************************************************************************//**
+ * @file     fmc.h
+ * @version  V1.00
+ * @brief    M480 Series Flash Memory Controller Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_FMC_Driver FMC Driver
+  @{
+*/
+
+
+/** @addtogroup M480_FMC_EXPORTED_CONSTANTS FMC Exported Constants
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE          0x00000000UL    /*!< APROM base address          \hideinitializer */
+#define FMC_APROM_END           0x00080000UL    /*!< APROM end address           \hideinitializer */
+#define FMC_APROM_BANK0_END     (FMC_APROM_END/2UL)  /*!< APROM bank0 end address     \hideinitializer */
+#define FMC_LDROM_BASE          0x00100000UL    /*!< LDROM base address          \hideinitializer */
+#define FMC_LDROM_END           0x00101000UL    /*!< LDROM end address           \hideinitializer */
+#define FMC_SPROM_BASE          0x00200000UL    /*!< SPROM base address          \hideinitializer */
+#define FMC_SPROM_END           0x00201000UL    /*!< SPROM end address           \hideinitializer */
+#define FMC_CONFIG_BASE         0x00300000UL    /*!< User Configuration address  \hideinitializer */
+#define FMC_USER_CONFIG_0       0x00300000UL    /*!< User Config 0 address       \hideinitializer */
+#define FMC_USER_CONFIG_1       0x00300004UL    /*!< User Config 1 address       \hideinitializer */
+#define FMC_USER_CONFIG_2       0x00300008UL    /*!< User Config 2 address       \hideinitializer */
+#define FMC_KPROM_BASE          0x00301000UL    /*!< Security ROM base address   \hideinitializer */
+#define FMC_OTP_BASE            0x00310000UL    /*!< OTP flash base address      \hideinitializer */
+
+#define FMC_FLASH_PAGE_SIZE     0x1000UL        /*!< Flash Page Size (4K bytes)  \hideinitializer */
+#define FMC_PAGE_ADDR_MASK      0xFFFFF000UL    /*!< Flash page address mask     \hideinitializer */
+
+#define FMC_APROM_SIZE          FMC_APROM_END   /*!< APROM Size                  \hideinitializer */
+#define FMC_BANK_SIZE           (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size             \hideinitializer */
+#define FMC_LDROM_SIZE          0x1000UL        /*!< LDROM Size (4 Kbytes)       \hideinitializer */
+#define FMC_SPROM_SIZE          0x1000UL        /*!< SPROM Size (4 Kbytes)       \hideinitializer */
+#define FMC_OTP_ENTRY_CNT       256UL           /*!< OTP entry number            \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  ISPCMD constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ         0x00UL          /*!< ISP Command: Read flash word         \hideinitializer */
+#define FMC_ISPCMD_READ_UID     0x04UL          /*!< ISP Command: Read Unique ID          \hideinitializer */
+#define FMC_ISPCMD_READ_ALL1    0x08UL          /*!< ISP Command: Read all-one result     \hideinitializer */
+#define FMC_ISPCMD_READ_CID     0x0BUL          /*!< ISP Command: Read Company ID         \hideinitializer */
+#define FMC_ISPCMD_READ_PID     0x0CUL          /*!< ISP Command: Read Product ID         \hideinitializer */
+#define FMC_ISPCMD_READ_CKS     0x0DUL          /*!< ISP Command: Read checksum           \hideinitializer */
+#define FMC_ISPCMD_PROGRAM      0x21UL          /*!< ISP Command: Write flash word        \hideinitializer */
+#define FMC_ISPCMD_PAGE_ERASE   0x22UL          /*!< ISP Command: Page Erase Flash        \hideinitializer */
+#define FMC_ISPCMD_BANK_ERASE   0x23UL          /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */
+#define FMC_ISPCMD_BLOCK_ERASE  0x25UL          /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1  \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_MUL  0x27UL          /*!< ISP Command: Multuple word program   \hideinitializer */
+#define FMC_ISPCMD_RUN_ALL1     0x28UL          /*!< ISP Command: Run all-one verification \hideinitializer */
+#define FMC_ISPCMD_RUN_CKS      0x2DUL          /*!< ISP Command: Run checksum calculation \hideinitializer */
+#define FMC_ISPCMD_VECMAP       0x2EUL          /*!< ISP Command: Vector Page Remap       \hideinitializer */
+#define FMC_ISPCMD_READ_64      0x40UL          /*!< ISP Command: Read double flash word  \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_64   0x61UL          /*!< ISP Command: Write double flash word \hideinitializer */
+
+#define IS_BOOT_FROM_APROM      0UL             /*!< Is booting from APROM                \hideinitializer */
+#define IS_BOOT_FROM_LDROM      1UL             /*!< Is booting from LDROM                \hideinitializer */
+
+#define READ_ALLONE_YES         0xA11FFFFFUL    /*!< Check-all-one result is all one.     \hideinitializer */
+#define READ_ALLONE_NOT         0xA1100000UL    /*!< Check-all-one result is not all one. \hideinitializer */
+#define READ_ALLONE_CMD_FAIL    0xFFFFFFFFUL    /*!< Check-all-one command failed.        \hideinitializer */
+
+
+/*@}*/ /* end of group M480_FMC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Macros                                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define FMC_SET_APROM_BOOT()        (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)         /*!< Select booting from APROM  \hideinitializer */
+#define FMC_SET_LDROM_BOOT()        (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)          /*!< Select booting from LDROM  \hideinitializer */
+#define FMC_ENABLE_AP_UPDATE()      (FMC->ISPCTL |=  FMC_ISPCTL_APUEN_Msk)      /*!< Enable APROM update        \hideinitializer */
+#define FMC_DISABLE_AP_UPDATE()     (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)      /*!< Disable APROM update       \hideinitializer */
+#define FMC_ENABLE_CFG_UPDATE()     (FMC->ISPCTL |=  FMC_ISPCTL_CFGUEN_Msk)     /*!< Enable User Config update  \hideinitializer */
+#define FMC_DISABLE_CFG_UPDATE()    (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)     /*!< Disable User Config update \hideinitializer */
+#define FMC_ENABLE_LD_UPDATE()      (FMC->ISPCTL |=  FMC_ISPCTL_LDUEN_Msk)      /*!< Enable LDROM update        \hideinitializer */
+#define FMC_DISABLE_LD_UPDATE()     (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)      /*!< Disable LDROM update       \hideinitializer */
+#define FMC_ENABLE_SP_UPDATE()      (FMC->ISPCTL |=  FMC_ISPCTL_SPUEN_Msk)      /*!< Enable SPROM update        \hideinitializer */
+#define FMC_DISABLE_SP_UPDATE()     (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk)      /*!< Disable SPROM update       \hideinitializer */
+#define FMC_DISABLE_ISP()           (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)      /*!< Disable ISP function       \hideinitializer */
+#define FMC_ENABLE_ISP()            (FMC->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk)      /*!< Enable ISP function        \hideinitializer */
+#define FMC_GET_FAIL_FLAG()         ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL)  /*!< Get ISP fail flag  \hideinitializer */
+#define FMC_CLR_FAIL_FLAG()         (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk)       /*!< Clear ISP fail flag        \hideinitializer */
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Functions                                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+
+extern void FMC_Close(void);
+extern int32_t FMC_Erase(uint32_t u32PageAddr);
+extern int32_t FMC_Erase_SPROM(void);
+extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr);
+extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr);
+extern int32_t FMC_GetBootSource(void);
+extern void FMC_Open(void);
+extern uint32_t FMC_Read(uint32_t u32Addr);
+extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1);
+extern uint32_t FMC_ReadCID(void);
+extern uint32_t FMC_ReadPID(void);
+extern uint32_t FMC_ReadUCID(uint32_t u32Index);
+extern uint32_t FMC_ReadUID(uint32_t u32Index);
+extern uint32_t FMC_ReadDataFlashBaseAddr(void);
+extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
+extern int32_t  FMC_Write_64(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
+extern int32_t  FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
+extern int32_t  FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);
+extern int32_t  FMC_Lock_OTP(uint32_t otp_num);
+extern int32_t  FMC_Is_OTP_Locked(uint32_t otp_num);
+extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
+extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
+extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
+extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
+extern int32_t  FMC_SKey_Setup(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);
+extern int32_t  FMC_SKey_Compare(uint32_t key[3]);
+
+
+/*@}*/ /* end of group M480_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_FMC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* __FMC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_gpio.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,146 @@
+/**************************************************************************//**
+ * @file     gpio.c
+ * @version  V3.00
+ * @brief    M480 series GPIO driver source file
+ *
+ * @copyright (C) 2011~2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set GPIO operation mode
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @param[in]   u32Mode     Operation mode.  It could be \n
+ *                          GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t i;
+
+    for(i = 0ul; i < GPIO_PIN_MAX; i++) {
+        if((u32PinMask & (1ul << i))==(1ul << i)) {
+            port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Enable GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port.
+ *                          It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be 0 ~ 13 for PE GPIO port.
+ *                          It could be 0 ~ 11 for PG GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be \n
+ *                              GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+    port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+    port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief       Disable GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port.
+ *                          It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be 0 ~ 13 for PE GPIO port.
+ *                          It could be 0 ~ 11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+    port->INTTYPE &= ~(1UL << u32Pin);
+    port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief       Set GPIO slew rate control
+ *
+ * @param[in]   port        GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ * @param[in]   u32Mode     Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ *                                          \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ *                                          \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t i;
+
+    for(i = 0ul; i < GPIO_PIN_MAX; i++) {
+        if(u32PinMask & (1ul << i)) {
+            port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Set GPIO Pull-up and Pull-down control
+ *
+ * @param[in]   port          GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in]   u32PinMask    The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in]   u32Mode       The pin mode of specified GPIO pin. It could be
+ *                                \ref GPIO_PUSEL_DISABLE
+ *                                \ref GPIO_PUSEL_PULL_UP
+ *                                \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return      None
+ *
+ * @details     Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t i;
+
+    for(i = 0ul; i < GPIO_PIN_MAX; i++) {
+        if(u32PinMask & (1ul << i)) {
+            port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+        }
+    }
+}
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_gpio.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,496 @@
+/**************************************************************************//**
+ * @file     GPIO.h
+ * @version  V3.00
+ * @brief    M480 series GPIO driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+  @{
+*/
+
+
+#define GPIO_PIN_MAX            16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_MODE Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT          0x0UL /*!< Input Mode \hideinitializer */
+#define GPIO_MODE_OUTPUT         0x1UL /*!< Output Mode \hideinitializer */
+#define GPIO_MODE_OPEN_DRAIN     0x2UL /*!< Open-Drain Mode \hideinitializer */
+#define GPIO_MODE_QUASI          0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING         0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */
+#define GPIO_INT_FALLING        0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */
+#define GPIO_INT_BOTH_EDGE      0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */
+#define GPIO_INT_HIGH           0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */
+#define GPIO_INT_LOW            0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_INTTYPE Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE           0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */
+#define GPIO_INTTYPE_LEVEL          1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Slew Rate Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_SLEWCTL_NORMAL         0x0UL           /*!< GPIO slew setting for nornal Mode \hideinitializer */
+#define GPIO_SLEWCTL_HIGH           0x1UL           /*!< GPIO slew setting for high Mode \hideinitializer */
+#define GPIO_SLEWCTL_FAST           0x2UL           /*!< GPIO slew setting for fast Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Pull-up And Pull-down Type Constant Definitions                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PUSEL_DISABLE          0x0UL           /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_UP          0x1UL           /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_DOWN        0x2UL           /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_DBCTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON            0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */
+#define GPIO_DBCTL_ICLK_OFF           0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC      0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */
+#define GPIO_DBCTL_DBCLKSRC_HCLK      0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSEL_1         0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2         0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4         0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8         0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16        0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32        0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_64        0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_128       0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_256       0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_512       0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_1024      0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2048      0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4096      0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8192      0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16384     0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32768     0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */
+
+
+/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+   Example 1:
+
+       PA0 = 1;
+
+   It is used to set GPIO PA.0 to high;
+
+   Example 2:
+
+       if (PA0)
+           PA0 = 0;
+
+   If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
+ */
+#define GPIO_PIN_DATA(port, pin)    (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */
+#define PA0             GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */
+#define PA1             GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */
+#define PA2             GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */
+#define PA3             GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */
+#define PA4             GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */
+#define PA5             GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */
+#define PA6             GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */
+#define PA7             GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */
+#define PA8             GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */
+#define PA9             GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */
+#define PA10            GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */
+#define PA11            GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */
+#define PA12            GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */
+#define PA13            GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */
+#define PA14            GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */
+#define PA15            GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */
+#define PB0             GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */
+#define PB1             GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */
+#define PB2             GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */
+#define PB3             GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */
+#define PB4             GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */
+#define PB5             GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */
+#define PB6             GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */
+#define PB7             GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */
+#define PB8             GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */
+#define PB9             GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */
+#define PB10            GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */
+#define PB11            GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */
+#define PB12            GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */
+#define PB13            GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */
+#define PB14            GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */
+#define PB15            GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */
+#define PC0             GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */
+#define PC1             GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */
+#define PC2             GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */
+#define PC3             GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */
+#define PC4             GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */
+#define PC5             GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */
+#define PC6             GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */
+#define PC7             GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */
+#define PC8             GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */
+#define PC9             GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */
+#define PC10            GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */
+#define PC11            GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */
+#define PC12            GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */
+#define PC13            GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */
+#define PC14            GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */
+#define PD0             GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */
+#define PD1             GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */
+#define PD2             GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */
+#define PD3             GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */
+#define PD4             GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */
+#define PD5             GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */
+#define PD6             GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */
+#define PD7             GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */
+#define PD8             GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */
+#define PD9             GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */
+#define PD10            GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */
+#define PD11            GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */
+#define PD12            GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */
+#define PD13            GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */
+#define PD14            GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */
+#define PE0             GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */
+#define PE1             GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */
+#define PE2             GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */
+#define PE3             GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */
+#define PE4             GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */
+#define PE5             GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */
+#define PE6             GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */
+#define PE7             GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */
+#define PE8             GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */
+#define PE9             GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */
+#define PE10            GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */
+#define PE11            GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */
+#define PE12            GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */
+#define PE13            GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */
+#define PE14            GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */
+#define PE15            GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */
+#define PF0             GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */
+#define PF1             GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */
+#define PF2             GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */
+#define PF3             GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */
+#define PF4             GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */
+#define PF5             GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */
+#define PF6             GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */
+#define PF7             GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */
+#define PF8             GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */
+#define PF9             GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */
+#define PF10            GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */
+#define PF11            GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */
+#define PG0             GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */
+#define PG1             GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */
+#define PG2             GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */
+#define PG3             GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */
+#define PG4             GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */
+#define PG5             GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */
+#define PG6             GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */
+#define PG7             GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */
+#define PG8             GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */
+#define PG9             GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */
+#define PG10            GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */
+#define PG11            GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */
+#define PG12            GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */
+#define PG13            GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */
+#define PG14            GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */
+#define PG15            GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */
+#define PH0             GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
+#define PH1             GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
+#define PH2             GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
+#define PH3             GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
+#define PH4             GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
+#define PH5             GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
+#define PH6             GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
+#define PH7             GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
+#define PH8             GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
+#define PH9             GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
+#define PH10            GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
+#define PH11            GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Clear the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask)         ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief       Disable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Disable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask)     ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief       Enable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @return      None
+ *
+ * @details     Enable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask)      ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief       Disable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief       Enable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask)  ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief       Disable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask)    ((port)->DATMSK &= ~(u32PinMask))
+
+/**
+ * @brief       Enable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief       Get GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be BIT0 ~ BIT13 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @retval      0           No interrupt at specified GPIO pin
+ * @retval      1           The specified GPIO pin generate an interrupt
+ *
+ * @details     Get the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask)     ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief       Set De-bounce Sampling Cycle Time
+ *
+ * @param[in]   u32ClkSrc   The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in]   u32ClkSel   The de-bounce sampling cycle selection. It could be
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_64
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_128
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_256
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_512
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1024
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2048
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4096
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8192
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16384
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return      None
+ *
+ * @details     Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ *              Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ *              It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ *              Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ *              and system will sampling interrupt input once per 00 us.
+ * \hideinitializer
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel)    (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief       Get GPIO Port IN Data
+ *
+* @param[in]    port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ *
+ * @return      The specified port data
+ *
+ * @details     Get the PIN register of specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_GET_IN_DATA(port)  ((port)->PIN)
+
+/**
+ * @brief       Set GPIO Port OUT Data
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Data     GPIO port data.
+ *
+ * @return      None
+ *
+ * @details     Set the Data into specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data)    ((port)->DOUT = (u32Data))
+
+/**
+ * @brief       Toggle Specified GPIO pin
+ *
+ * @param[in]   u32Pin      Pxy
+ *
+ * @return      None
+ *
+ * @details     Toggle the specified GPIO pint.
+ * \hideinitializer
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+ * @brief       Enable External GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port.
+ *                          It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be 0 ~ 13 for PE GPIO port.
+ *                          It could be 0 ~ 11 for PG GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be \n
+ *                              GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_EnableEINT     GPIO_EnableInt
+
+/**
+ * @brief       Disable External GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port.
+ *                          It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ *                          It could be 0 ~ 13 for PE GPIO port.
+ *                          It could be 0 ~ 11 for PG GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_DisableEINT    GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __GPIO_H__ */
+
+/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsotg.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file     hsotg.h
+ * @version  V0.10
+ * @brief    M480 Series HSOTG Driver Header File
+ *
+ * @copyright  (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __HSOTG_H__
+#define __HSOTG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_HSOTG_Driver HSOTG Driver
+  @{
+*/
+
+
+/** @addtogroup M480_HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* HSOTG constant definitions                                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define HSOTG_VBUS_EN_ACTIVE_HIGH      (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
+#define HSOTG_VBUS_EN_ACTIVE_LOW       (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
+#define HSOTG_VBUS_ST_VALID_HIGH       (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
+#define HSOTG_VBUS_ST_VALID_LOW        (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
+
+
+/*@}*/ /* end of group M480_HSOTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable HSOTG function
+  * @param None
+  * @return None
+  * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function.
+  * \hideinitializer
+  */
+#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to disable HSOTG function
+  * @param None
+  * @return None
+  * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function.
+  * \hideinitializer
+  */
+#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to enable USB PHY
+  * @param None
+  * @return None
+  * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY.
+  *          This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY.
+  * \hideinitializer
+  */
+#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to disable USB PHY
+  * @param None
+  * @return None
+  * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY.
+  * \hideinitializer
+  */
+#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to enable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function.
+  * \hideinitializer
+  */
+#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to disable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function.
+  * \hideinitializer
+  */
+#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to enable HSOTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function.
+  * \hideinitializer
+  */
+#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable HSOTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function.
+  * \hideinitializer
+  */
+#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref HSOTG_VBUS_EN_ACTIVE_HIGH
+  *                    - \ref HSOTG_VBUS_EN_ACTIVE_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+  * \hideinitializer
+  */
+#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<HSOTG_PHYCTL_VBENPOL_Pos))
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_ST pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref HSOTG_VBUS_ST_VALID_HIGH
+  *                    - \ref HSOTG_VBUS_ST_VALID_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch status signal.
+  * \hideinitializer
+  */
+#define HSOTG_SET_VBUS_STS_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<HSOTG_PHYCTL_VBSTSPOL_Pos))
+
+/**
+  * @brief This macro is used to enable HSOTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref HSOTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_VBEIEN_Msk
+  *                    - \ref HSOTG_INTEN_SRPFIEN_Msk
+  *                    - \ref HSOTG_INTEN_HNPFIEN_Msk
+  *                    - \ref HSOTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref HSOTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_PDEVIEN_Msk
+  *                    - \ref HSOTG_INTEN_HOSTIEN_Msk
+  *                    - \ref HSOTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_SECHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will enable HSOTG related interrupts specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define HSOTG_ENABLE_INT(u32Mask) (HSOTG->INTEN |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable HSOTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref HSOTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_VBEIEN_Msk
+  *                    - \ref HSOTG_INTEN_SRPFIEN_Msk
+  *                    - \ref HSOTG_INTEN_HNPFIEN_Msk
+  *                    - \ref HSOTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref HSOTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_PDEVIEN_Msk
+  *                    - \ref HSOTG_INTEN_HOSTIEN_Msk
+  *                    - \ref HSOTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_SECHGIEN_Msk
+  *                    - \ref HSOTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to get HSOTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref HSOTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_VBEIF_Msk
+  *                    - \ref HSOTG_INTSTS_SRPFIF_Msk
+  *                    - \ref HSOTG_INTSTS_HNPFIF_Msk
+  *                    - \ref HSOTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref HSOTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_PDEVIF_Msk
+  *                    - \ref HSOTG_INTSTS_HOSTIF_Msk
+  *                    - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_SECHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_SRPDETIF_Msk
+  * @return Interrupt flags of selected sources.
+  * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask))
+
+/**
+  * @brief This macro is used to clear HSOTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref HSOTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_VBEIF_Msk
+  *                    - \ref HSOTG_INTSTS_SRPFIF_Msk
+  *                    - \ref HSOTG_INTSTS_HNPFIF_Msk
+  *                    - \ref HSOTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref HSOTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_PDEVIF_Msk
+  *                    - \ref HSOTG_INTSTS_HOSTIF_Msk
+  *                    - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_SECHGIF_Msk
+  *                    - \ref HSOTG_INTSTS_SRPDETIF_Msk
+  * @return None
+  * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask))
+
+/**
+  * @brief This macro is used to get HSOTG related status
+  * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+  *                    - \ref HSOTG_STATUS_OVERCUR_Msk
+  *                    - \ref HSOTG_STATUS_IDSTS_Msk
+  *                    - \ref HSOTG_STATUS_SESSEND_Msk
+  *                    - \ref HSOTG_STATUS_BVLD_Msk
+  *                    - \ref HSOTG_STATUS_AVLD_Msk
+  *                    - \ref HSOTG_STATUS_VBUSVLD_Msk
+  * @return The user specified status.
+  * @details This macro will return HSOTG related status specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group M480_HSOTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_HSOTG_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __HSOTG_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsusbd.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,621 @@
+/**************************************************************************//**
+ * @file     hsusbd.c
+ * @version  V1.00
+ * @brief    M480 HSUSBD driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_HSUSBD_Driver HSUSBD Driver
+  @{
+*/
+
+
+/** @addtogroup M480_HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions
+  @{
+*/
+/*--------------------------------------------------------------------------*/
+/** @cond HIDDEN_SYMBOLS */
+/* Global variables for Control Pipe */
+S_HSUSBD_CMD_T gUsbCmd;
+S_HSUSBD_INFO_T *g_hsusbd_sInfo;
+
+HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL;
+HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL;
+HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL;
+uint32_t g_u32HsEpStallLock = 0ul;       /* Bit map flag to lock specified EP when SET_FEATURE */
+
+static uint8_t *g_hsusbd_CtrlInPointer = 0;
+static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul;
+static uint8_t g_hsusbd_UsbConfig = 0ul;
+static uint8_t g_hsusbd_UsbAltInterface = 0ul;
+static uint8_t g_hsusbd_EnableTestMode = 0ul;
+static uint8_t g_hsusbd_TestSelector = 0ul;
+
+#ifdef __ICCARM__
+#pragma data_alignment=4
+static uint8_t g_hsusbd_buf[12];
+#elif defined (__CC_ARM)
+__align(4) static uint8_t g_hsusbd_buf[12];
+#elif defined ( __GNUC__ )
+static uint8_t g_hsusbd_buf[12] __attribute__((aligned (4)));
+#endif
+
+uint8_t g_hsusbd_Configured = 0ul;
+uint8_t g_hsusbd_CtrlZero = 0ul;
+uint8_t g_hsusbd_UsbAddr = 0ul;
+uint8_t g_hsusbd_ShortPacket = 0ul;
+uint32_t volatile g_hsusbd_DmaDone = 0ul;
+uint32_t g_hsusbd_CtrlInSize = 0ul;
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+ * @brief       HSUSBD Initial
+ *
+ * @param[in]   param               Descriptor
+ * @param[in]   pfnClassReq         Class Request Callback Function
+ * @param[in]   pfnSetInterface     SetInterface Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to initial HSUSBD.
+ */
+void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface)
+{
+    g_hsusbd_sInfo = param;
+    g_hsusbd_pfnClassRequest = pfnClassReq;
+    g_hsusbd_pfnSetInterface = pfnSetInterface;
+
+    /* get EP0 maximum packet size */
+    g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7];
+
+    /* Initial USB engine */
+    /* Enable PHY */
+    HSUSBD_ENABLE_PHY();
+    /* wait PHY clock ready */
+    while (1) {
+        HSUSBD->EP[EPA].EPMPS = 0x20ul;
+        if (HSUSBD->EP[EPA].EPMPS == 0x20ul) {
+            break;
+        }
+    }
+    /* Force SE0, and then clear it to connect*/
+    HSUSBD_SET_SE0();
+}
+
+/**
+ * @brief       HSUSBD Start
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to start transfer
+ */
+void HSUSBD_Start(void)
+{
+    HSUSBD_CLR_SE0();
+}
+
+/**
+ * @brief       Process Setup Packet
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to process Setup packet.
+ */
+void HSUSBD_ProcessSetupPacket(void)
+{
+    /* Setup packet process */
+    gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful);
+    gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful);
+    gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2;
+    gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4;
+    gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6;
+
+    /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */
+    switch (gUsbCmd.bmRequestType & 0x60ul) {
+    case REQ_STANDARD: {
+        HSUSBD_StandardRequest();
+        break;
+    }
+    case REQ_CLASS: {
+        if (g_hsusbd_pfnClassRequest != NULL) {
+            g_hsusbd_pfnClassRequest();
+        }
+        break;
+    }
+    case REQ_VENDOR: {
+        if (g_hsusbd_pfnVendorRequest != NULL) {
+            g_hsusbd_pfnVendorRequest();
+        }
+        break;
+    }
+    default: {
+        /* Setup error, stall the device */
+        HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+        break;
+    }
+    }
+}
+
+/**
+ * @brief       Get Descriptor request
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to process GetDescriptor request.
+ */
+int HSUSBD_GetDescriptor(void)
+{
+    uint32_t u32Len;
+    int val = 0;
+
+    u32Len = gUsbCmd.wLength;
+    g_hsusbd_CtrlZero = (uint8_t)0ul;
+
+    switch ((gUsbCmd.wValue & 0xff00ul) >> 8) {
+    /* Get Device Descriptor */
+    case DESC_DEVICE: {
+        u32Len = Minimum(u32Len, LEN_DEVICE);
+        HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len);
+        break;
+    }
+    /* Get Configuration Descriptor */
+    case DESC_CONFIG: {
+        uint32_t u32TotalLen;
+        if ((HSUSBD->OPER & 0x04ul) == 0x04ul) {
+            u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3];
+            u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+            u32Len = Minimum(u32Len, u32TotalLen);
+            if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+                g_hsusbd_CtrlZero = (uint8_t)1ul;
+            }
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len);
+        } else {
+            u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3];
+            u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8);
+
+            u32Len = Minimum(u32Len, u32TotalLen);
+            if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+                g_hsusbd_CtrlZero = (uint8_t)1ul;
+            }
+
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len);
+        }
+
+        break;
+    }
+    /* Get Qualifier Descriptor */
+    case DESC_QUALIFIER: {
+        u32Len = Minimum(u32Len, LEN_QUALIFIER);
+        HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len);
+        break;
+    }
+    /* Get Other Speed Descriptor - Full speed */
+    case DESC_OTHERSPEED: {
+        uint32_t u32TotalLen;
+        if ((HSUSBD->OPER & 0x04ul) == 0x04ul) {
+            u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3];
+            u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8);
+
+            u32Len = Minimum(u32Len, u32TotalLen);
+            if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+                g_hsusbd_CtrlZero = (uint8_t)1ul;
+            }
+
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len);
+        } else {
+            u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3];
+            u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8);
+
+            u32Len = Minimum(u32Len, u32TotalLen);
+            if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+                g_hsusbd_CtrlZero = (uint8_t)1ul;
+            }
+
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len);
+        }
+
+        break;
+    }
+    /* Get HID Descriptor */
+    case DESC_HID: {
+        u32Len = Minimum(u32Len, LEN_HID);
+        HSUSBD_MemCopy(g_hsusbd_buf, &g_hsusbd_sInfo->gu8ConfigDesc[LEN_CONFIG+LEN_INTERFACE], u32Len);
+        HSUSBD_PrepareCtrlIn(g_hsusbd_buf, u32Len);
+        break;
+    }
+    /* Get Report Descriptor */
+    case DESC_HID_RPT: {
+        if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+            g_hsusbd_CtrlZero = (uint8_t)1ul;
+        }
+
+        if ((HSUSBD->OPER & 0x04ul) == 0x04ul) {
+            u32Len = Minimum(u32Len, g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]);
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len);
+        } else {
+            u32Len = Minimum(u32Len, g_hsusbd_sInfo->gu32FSHidReportSize[gUsbCmd.wIndex & 0xfful]);
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSHidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len);
+        }
+        break;
+    }
+    /* Get String Descriptor */
+    case DESC_STRING: {
+        if((gUsbCmd.wValue & 0xfful) < 8ul) {
+            u32Len = Minimum(u32Len, g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]);
+            if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) {
+                g_hsusbd_CtrlZero = (uint8_t)1ul;
+            }
+            HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len);
+        } else {
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+            val = 1;
+        }
+        break;
+    }
+    default:
+        /* Not support. Reply STALL. */
+        HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+        val = 1;
+        break;
+    }
+    return val;
+}
+
+
+/**
+ * @brief       Process USB standard request
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to process USB Standard Request.
+ */
+void HSUSBD_StandardRequest(void)
+{
+    /* clear global variables for new request */
+    g_hsusbd_CtrlInPointer = 0;
+    g_hsusbd_CtrlInSize = 0ul;
+
+    if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) { /* request data transfer direction */
+        /* Device to host */
+        switch (gUsbCmd.bRequest) {
+        case GET_CONFIGURATION: {
+            /* Return current configuration setting */
+            HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul);
+
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        case GET_DESCRIPTOR: {
+            if (!HSUSBD_GetDescriptor()) {
+                HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+                HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+            }
+            break;
+        }
+        case GET_INTERFACE: {
+            /* Return current interface setting */
+            HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul);
+
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        case GET_STATUS: {
+            /* Device */
+            if (gUsbCmd.bmRequestType == 0x80ul) {
+                if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) {
+                    g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */
+                } else {
+                    g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */
+                }
+            }
+            /* Interface */
+            else if (gUsbCmd.bmRequestType == 0x81ul) {
+                g_hsusbd_buf[0] = (uint8_t)0ul;
+            }
+            /* Endpoint */
+            else if (gUsbCmd.bmRequestType == 0x82ul) {
+                uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul);
+                g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep)? (uint8_t)1 : (uint8_t)0;
+            }
+            g_hsusbd_buf[1] = (uint8_t)0ul;
+            HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul);
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
+            break;
+        }
+        default: {
+            /* Setup error, stall the device */
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+            break;
+        }
+        }
+    } else {
+        /* Host to device */
+        switch (gUsbCmd.bRequest) {
+        case CLEAR_FEATURE: {
+            if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) {
+
+                uint32_t epNum, i;
+
+                /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+                   a flag: g_u32HsEpStallLock is added to support it */
+                epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+                for (i=0ul; i<HSUSBD_MAX_EP; i++) {
+                    if ((((HSUSBD->EP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul)) {
+                        HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE;
+                    }
+                }
+            }
+            /* Status stage */
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_ADDRESS: {
+            g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue;
+            /* Status Stage */
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_CONFIGURATION: {
+            g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue;
+            g_hsusbd_Configured = (uint8_t)1ul;
+            /* Status stage */
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_FEATURE: {
+            if ((gUsbCmd.wValue & 0x3ul) == 2ul) {  /* TEST_MODE */
+                g_hsusbd_EnableTestMode = (uint8_t)1ul;
+                g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8);
+            }
+            if ((gUsbCmd.wValue & 0x3ul) == 3ul) {  /* HNP ebable */
+                HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk);
+            }
+
+            /* Status stage */
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        case SET_INTERFACE: {
+            g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue;
+            if (g_hsusbd_pfnSetInterface != NULL) {
+                g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface);
+            }
+            /* Status stage */
+            HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+            HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
+            break;
+        }
+        default: {
+            /* Setup error, stall the device */
+            HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk);
+            break;
+        }
+        }
+    }
+}
+
+/**
+ * @brief       Update Device State
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to update Device state when Setup packet complete
+ */
+/** @cond HIDDEN_SYMBOLS */
+#define TEST_J                  0x01ul
+#define TEST_K                  0x02ul
+#define TEST_SE0_NAK            0x03ul
+#define TEST_PACKET             0x04ul
+#define TEST_FORCE_ENABLE       0x05ul
+/** @endcond HIDDEN_SYMBOLS */
+
+void HSUSBD_UpdateDeviceState(void)
+{
+    switch (gUsbCmd.bRequest) {
+    case SET_ADDRESS: {
+        HSUSBD_SET_ADDR(g_hsusbd_UsbAddr);
+        break;
+    }
+    case SET_CONFIGURATION: {
+        if (g_hsusbd_UsbConfig == 0ul) {
+            uint32_t volatile i;
+            /* Reset PID DATA0 */
+            for (i=0ul; i<HSUSBD_MAX_EP; i++) {
+                if ((HSUSBD->EP[i].EPCFG & 0x1ul) == 0x1ul) {
+                    HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+                }
+            }
+        }
+        break;
+    }
+    case SET_FEATURE: {
+        if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) {
+            uint32_t idx;
+            idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+            HSUSBD_SetStall(idx);
+        } else if (g_hsusbd_EnableTestMode) {
+            g_hsusbd_EnableTestMode = (uint8_t)0ul;
+            if (g_hsusbd_TestSelector == TEST_J) {
+                HSUSBD->TEST = TEST_J;
+            } else if (g_hsusbd_TestSelector == TEST_K) {
+                HSUSBD->TEST = TEST_K;
+            } else if (g_hsusbd_TestSelector == TEST_SE0_NAK) {
+                HSUSBD->TEST = TEST_SE0_NAK;
+            } else if (g_hsusbd_TestSelector == TEST_PACKET) {
+                HSUSBD->TEST = TEST_PACKET;
+            } else if (g_hsusbd_TestSelector == TEST_FORCE_ENABLE) {
+                HSUSBD->TEST = TEST_FORCE_ENABLE;
+            }
+        }
+        break;
+    }
+    case CLEAR_FEATURE: {
+        if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) {
+            uint32_t idx;
+            idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
+            HSUSBD_ClearStall(idx);
+        }
+        break;
+    }
+    default:
+        break;
+    }
+}
+
+
+/**
+ * @brief       Prepare Control IN transaction
+ *
+ * @param[in]   pu8Buf      Control IN data pointer
+ * @param[in]   u32Size     IN transfer size
+ *
+ * @return      None
+ *
+ * @details     This function is used to prepare Control IN transfer
+ */
+void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
+{
+    g_hsusbd_CtrlInPointer = pu8Buf;
+    g_hsusbd_CtrlInSize = u32Size;
+}
+
+
+
+/**
+ * @brief       Start Control IN transfer
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to start Control IN
+ */
+void HSUSBD_CtrlIn(void)
+{
+    uint32_t volatile i, cnt;
+    uint8_t u8Value;
+    if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize) {
+        /* Data size > MXPLD */
+        cnt = g_hsusbd_CtrlMaxPktSize >> 2;
+        for (i=0ul; i<cnt; i++) {
+            HSUSBD->CEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer;
+            g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul);
+        }
+        HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize);
+        g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize;
+    } else {
+        /* Data size <= MXPLD */
+        cnt = g_hsusbd_CtrlInSize >> 2;
+        for (i=0ul; i<cnt; i++) {
+            HSUSBD->CEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer;
+            g_hsusbd_CtrlInPointer += 4ul;
+        }
+
+        for (i=0ul; i<(g_hsusbd_CtrlInSize % 4ul); i++) {
+            u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer+i);
+            outpb(&HSUSBD->CEPDAT, u8Value);
+        }
+
+        HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize);
+        g_hsusbd_CtrlInPointer = 0;
+        g_hsusbd_CtrlInSize = 0ul;
+    }
+}
+
+/**
+ * @brief       Start Control OUT transaction
+ *
+ * @param[in]   pu8Buf      Control OUT data pointer
+ * @param[in]   u32Size     OUT transfer size
+ *
+ * @return      None
+ *
+ * @details     This function is used to start Control OUT transfer
+ */
+void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size)
+{
+    uint32_t volatile i;
+    while(1) {
+        if ((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk) {
+            for (i=0ul; i<u32Size; i++) {
+                pu8Buf[i] = inpb(&HSUSBD->CEPDAT);
+            }
+            HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk;
+            break;
+        }
+    }
+}
+
+/**
+ * @brief       Clear all software flags
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This function is used to clear all software control flag
+ */
+void HSUSBD_SwReset(void)
+{
+    /* Reset all variables for protocol */
+    g_hsusbd_UsbAddr = (uint8_t)0ul;
+    g_hsusbd_DmaDone = 0ul;
+    g_hsusbd_ShortPacket = (uint8_t)0ul;
+    g_hsusbd_Configured = (uint8_t)0ul;
+
+    /* Reset USB device address */
+    HSUSBD_SET_ADDR(0ul);
+}
+
+/**
+ * @brief       HSUSBD Set Vendor Request
+ *
+ * @param[in]   pfnVendorReq         Vendor Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to set HSUSBD vendor request callback function
+ */
+void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq)
+{
+    g_hsusbd_pfnVendorRequest = pfnVendorReq;
+}
+
+
+/*@}*/ /* end of group M480_HSUSBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_HSUSBD_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsusbd.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,377 @@
+/**************************************************************************//**
+ * @file     hsusbd.h
+ * @version  V1.00
+ * @brief    M480 HSUSBD driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HSUSBD_H__
+#define __HSUSBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_HSUSBD_Driver HSUSBD Driver
+  @{
+*/
+
+/** @addtogroup M480_HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants
+  @{
+*/
+/** @cond HIDDEN_SYMBOLS */
+#define HSUSBD_MAX_EP     12ul
+
+#define Maximum(a,b)    (a)>(b) ? (a) : (b)
+#define Minimum(a,b)    (((a)<(b)) ? (a) : (b))
+
+
+#define CEP     0xfful    /*!< Control Endpoint  \hideinitializer */
+#define EPA     0ul       /*!< Endpoint A  \hideinitializer */
+#define EPB     1ul       /*!< Endpoint B  \hideinitializer */
+#define EPC     2ul       /*!< Endpoint C  \hideinitializer */
+#define EPD     3ul       /*!< Endpoint D  \hideinitializer */
+#define EPE     4ul       /*!< Endpoint E  \hideinitializer */
+#define EPF     5ul       /*!< Endpoint F  \hideinitializer */
+#define EPG     6ul       /*!< Endpoint G  \hideinitializer */
+#define EPH     7ul       /*!< Endpoint H  \hideinitializer */
+#define EPI     8ul       /*!< Endpoint I  \hideinitializer */
+#define EPJ     9ul       /*!< Endpoint J  \hideinitializer */
+#define EPK     10ul      /*!< Endpoint K  \hideinitializer */
+#define EPL     11ul      /*!< Endpoint L  \hideinitializer */
+
+/** @endcond HIDDEN_SYMBOLS */
+/********************* Bit definition of CEPCTL register **********************/
+#define HSUSBD_CEPCTL_NAKCLR               ((uint32_t)0x00000000ul)      /*!<NAK clear  \hideinitializer */
+#define HSUSBD_CEPCTL_STALL                ((uint32_t)0x00000002ul)      /*!<Stall  \hideinitializer */
+#define HSUSBD_CEPCTL_ZEROLEN              ((uint32_t)0x00000004ul)      /*!<Zero length packet  \hideinitializer */
+#define HSUSBD_CEPCTL_FLUSH                ((uint32_t)0x00000008ul)      /*!<CEP flush  \hideinitializer */
+
+/********************* Bit definition of EPxRSPCTL register **********************/
+#define HSUSBD_EP_RSPCTL_FLUSH             ((uint32_t)0x00000001ul)      /*!<Buffer Flush  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_MODE_AUTO         ((uint32_t)0x00000000ul)      /*!<Auto-Validate Mode  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_MODE_MANUAL       ((uint32_t)0x00000002ul)      /*!<Manual-Validate Mode  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_MODE_FLY          ((uint32_t)0x00000004ul)      /*!<Fly Mode  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_MODE_MASK         ((uint32_t)0x00000006ul)      /*!<Mode Mask  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_TOGGLE            ((uint32_t)0x00000008ul)      /*!<Clear Toggle bit  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_HALT              ((uint32_t)0x00000010ul)      /*!<Endpoint halt  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_ZEROLEN           ((uint32_t)0x00000020ul)      /*!<Zero length packet IN  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_SHORTTXEN         ((uint32_t)0x00000040ul)      /*!<Packet end  \hideinitializer */
+#define HSUSBD_EP_RSPCTL_DISBUF            ((uint32_t)0x00000080ul)      /*!<Disable buffer  \hideinitializer */
+
+/********************* Bit definition of EPxCFG register **********************/
+#define HSUSBD_EP_CFG_VALID                ((uint32_t)0x00000001ul)      /*!<Endpoint Valid  \hideinitializer */
+#define HSUSBD_EP_CFG_TYPE_BULK            ((uint32_t)0x00000002ul)      /*!<Endpoint type - bulk  \hideinitializer */
+#define HSUSBD_EP_CFG_TYPE_INT             ((uint32_t)0x00000004ul)      /*!<Endpoint type - interrupt  \hideinitializer */
+#define HSUSBD_EP_CFG_TYPE_ISO             ((uint32_t)0x00000006ul)      /*!<Endpoint type - isochronous  \hideinitializer */
+#define HSUSBD_EP_CFG_TYPE_MASK            ((uint32_t)0x00000006ul)      /*!<Endpoint type mask  \hideinitializer */
+#define HSUSBD_EP_CFG_DIR_OUT              ((uint32_t)0x00000000ul)      /*!<OUT endpoint  \hideinitializer */
+#define HSUSBD_EP_CFG_DIR_IN               ((uint32_t)0x00000008ul)      /*!<IN endpoint  \hideinitializer */
+
+
+/*@}*/ /* end of group M480_HSUSBD_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_HSUSBD_EXPORTED_STRUCT HSUSBD Exported Struct
+  @{
+*/
+
+
+typedef struct HSUSBD_CMD_STRUCT {
+    uint8_t  bmRequestType;
+    uint8_t  bRequest;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+
+} S_HSUSBD_CMD_T; /*!<USB Setup Packet Structure */
+
+
+
+
+typedef struct s_hsusbd_info {
+    uint8_t *gu8DevDesc;            /*!< Device descriptor */
+    uint8_t *gu8ConfigDesc;         /*!< Config descriptor */
+    uint8_t **gu8StringDesc;        /*!< Pointer for USB String Descriptor pointers */
+    uint8_t *gu8QualDesc;           /*!< Qualifier descriptor */
+    uint8_t *gu8FullConfigDesc;     /*!< Full Speed Config descriptor */
+    uint8_t *gu8HSOtherConfigDesc;  /*!< Other Speed Config descriptor */
+    uint8_t *gu8FSOtherConfigDesc;  /*!< Other Speed Config descriptor */
+    uint8_t **gu8HidReportDesc;     /*!< Pointer for HID Report descriptor */
+    uint32_t *gu32HidReportSize;    /*!< Pointer for HID Report descriptor Size */
+    uint8_t **gu8FSHidReportDesc;   /*!< Pointer for HID Report descriptor */
+    uint32_t *gu32FSHidReportSize;  /*!< Pointer for HID Report descriptor Size */
+
+} S_HSUSBD_INFO_T; /*!<USB Information Structure */
+
+
+/*@}*/ /* end of group M480_HSUSBD_EXPORTED_STRUCT */
+
+/** @cond HIDDEN_SYMBOLS */
+extern uint32_t g_u32HsEpStallLock;
+extern uint8_t g_hsusbd_Configured;
+extern uint8_t g_hsusbd_ShortPacket;
+extern uint8_t g_hsusbd_CtrlZero;
+extern uint8_t g_hsusbd_UsbAddr;
+extern uint32_t volatile g_hsusbd_DmaDone;
+extern uint32_t g_hsusbd_CtrlInSize;
+extern S_HSUSBD_INFO_T gsHSInfo;
+extern S_HSUSBD_CMD_T gUsbCmd;
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions
+  @{
+*/
+
+#define HSUSBD_ENABLE_USB()               ((uint32_t)(HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!<Enable USB  \hideinitializer */
+#define HSUSBD_DISABLE_USB()              ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!<Disable USB  \hideinitializer */
+#define HSUSBD_ENABLE_PHY()               ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!<Enable PHY  \hideinitializer */
+#define HSUSBD_DISABLE_PHY()              ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!<Disable PHY  \hideinitializer */
+#define HSUSBD_SET_SE0()                  ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!<Enable SE0, Force USB PHY Transceiver to Drive SE0  \hideinitializer */
+#define HSUSBD_CLR_SE0()                  ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!<Disable SE0  \hideinitializer */
+#define HSUSBD_SET_ADDR(addr)             (HSUSBD->FADDR = (addr)) /*!<Set USB address  \hideinitializer */
+#define HSUSBD_GET_ADDR()                 ((uint32_t)(HSUSBD->FADDR)) /*!<Get USB address  \hideinitializer */
+#define HSUSBD_ENABLE_USB_INT(intr)       (HSUSBD->GINTEN = (intr)) /*!<Enable USB Interrupt  \hideinitializer */
+#define HSUSBD_ENABLE_BUS_INT(intr)       (HSUSBD->BUSINTEN = (intr)) /*!<Enable BUS Interrupt  \hideinitializer */
+#define HSUSBD_GET_BUS_INT_FLAG()         (HSUSBD->BUSINTSTS)        /*!<Clear Bus interrupt flag  \hideinitializer */
+#define HSUSBD_CLR_BUS_INT_FLAG(flag)     (HSUSBD->BUSINTSTS = (flag)) /*!<Clear Bus interrupt flag  \hideinitializer */
+#define HSUSBD_ENABLE_CEP_INT(intr)       (HSUSBD->CEPINTEN = (intr)) /*!<Enable CEP Interrupt  \hideinitializer */
+#define HSUSBD_CLR_CEP_INT_FLAG(flag)     (HSUSBD->CEPINTSTS = (flag)) /*!<Clear CEP interrupt flag  \hideinitializer */
+#define HSUSBD_SET_CEP_STATE(flag)        (HSUSBD->CEPCTL = (flag)) /*!<Set CEP state  \hideinitializer */
+#define HSUSBD_START_CEP_IN(size)         (HSUSBD->CEPTXCNT = (size)) /*!<Start CEP IN Transfer  \hideinitializer */
+#define HSUSBD_SET_MAX_PAYLOAD(ep, size)  (HSUSBD->EP[(ep)].EPMPS = (size)) /*!<Set EPx Maximum Packet Size  \hideinitializer */
+#define HSUSBD_ENABLE_EP_INT(ep, intr)    (HSUSBD->EP[(ep)].EPINTEN = (intr)) /*!<Enable EPx Interrupt  \hideinitializer */
+#define HSUSBD_GET_EP_INT_FLAG(ep)        (HSUSBD->EP[(ep)].EPINTSTS) /*!<Get EPx interrupt flag  \hideinitializer */
+#define HSUSBD_CLR_EP_INT_FLAG(ep, flag)  (HSUSBD->EP[(ep)].EPINTSTS = (flag)) /*!<Clear EPx interrupt flag  \hideinitializer */
+#define HSUSBD_SET_DMA_LEN(len)           (HSUSBD->DMACNT = (len)) /*!<Set DMA transfer length  \hideinitializer */
+#define HSUSBD_SET_DMA_ADDR(addr)         (HSUSBD->DMAADDR = (addr)) /*!<Set DMA transfer address  \hideinitializer */
+#define HSUSBD_SET_DMA_READ(epnum)        (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!<Set DMA transfer type to read \hideinitializer */
+#define HSUSBD_SET_DMA_WRITE(epnum)       (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!<Set DMA transfer type to write \hideinitializer */
+#define HSUSBD_ENABLE_DMA()               (HSUSBD->DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!<Enable DMA transfer  \hideinitializer */
+#define HSUSBD_IS_ATTACHED()              ((uint32_t)(HSUSBD->PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!<Check cable connect state  \hideinitializer */
+
+/**
+  * @brief  HSUSBD_memcpy, Copy bytes hardware limitation
+  * @param[in]  u8Dst   Destination pointer.
+  * @param[in]  u8Src   Source pointer.
+  * @param[in]  u32Size Copy size.
+  * @retval None.
+  */
+static __INLINE void HSUSBD_MemCopy(uint8_t u8Dst[], uint8_t u8Src[], uint32_t u32Size)
+{
+    uint32_t i = 0ul;
+
+    while (u32Size--)
+    {
+        u8Dst[i] = u8Src[i];
+        i++;
+    }
+}
+
+/**
+  * @brief  HSUSBD_ResetDMA
+  * @param  None
+  * @retval None.
+  */
+static __INLINE void HSUSBD_ResetDMA(void)
+{
+    HSUSBD->DMACNT = 0ul;
+    HSUSBD->DMACTL = 0x80ul;
+    HSUSBD->DMACTL = 0x00ul;
+}
+/**
+  * @brief  HSUSBD_SetEpBufAddr, Set Endpoint buffer address
+  * @param[in]  u32Ep      Endpoint Number
+  * @param[in]  u32Base    Buffer Start Address
+  * @param[in]  u32Len     Buffer length
+  * @retval None.
+  */
+static __INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len)
+{
+    if (u32Ep == CEP) {
+        HSUSBD->CEPBUFST = u32Base;
+        HSUSBD->CEPBUFEND   = u32Base + u32Len - 1ul;
+    } else {
+        HSUSBD->EP[u32Ep].EPBUFST = u32Base;
+        HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul;
+    }
+}
+
+/**
+  * @brief  HSUSBD_ConfigEp, Config Endpoint
+  * @param[in]  u32Ep      USB endpoint
+  * @param[in]  u32EpNum   Endpoint number
+  * @param[in]  u32EpType  Endpoint type
+  * @param[in]  u32EpDir   Endpoint direction
+  * @retval None.
+  */
+static __INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir)
+{
+    if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK)
+    {
+        HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO);
+    }
+    else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT)
+    {
+        HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL);
+    }
+    else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO)
+    {
+        HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY);
+    }
+
+    HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4));
+}
+
+/**
+  * @brief       Set USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @return      None
+  * @details     Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+  */
+static __INLINE void HSUSBD_SetEpStall(uint32_t u32Ep)
+{
+    if (u32Ep == CEP)
+    {
+        HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
+    }
+    else
+    {
+        HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT;
+    }
+}
+
+/**
+ * @brief       Set USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @return      None
+ *
+ * @details     Set USB endpoint stall state, endpoint will return STALL token.
+ */
+static __INLINE void HSUSBD_SetStall(uint32_t u32EpNum)
+{
+    uint32_t i;
+
+    if (u32EpNum == 0ul)
+    {
+        HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
+    }
+    else
+    {
+        for (i=0ul; i<HSUSBD_MAX_EP; i++)
+        {
+            if (((HSUSBD->EP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+            {
+                HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT;
+            }
+        }
+    }
+}
+
+/**
+  * @brief       Clear USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @return      None
+  * @details     Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+  */
+static __INLINE void  HSUSBD_ClearEpStall(uint32_t u32Ep)
+{
+    HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+}
+
+/**
+ * @brief       Clear USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @return      None
+ *
+ * @details     Clear USB endpoint stall state, endpoint will return ACK/NAK token.
+ */
+static __INLINE void HSUSBD_ClearStall(uint32_t u32EpNum)
+{
+    uint32_t i;
+
+    for (i=0ul; i<HSUSBD_MAX_EP; i++)
+    {
+        if (((HSUSBD->EP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+        {
+            HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE;
+        }
+    }
+}
+
+/**
+  * @brief       Get USB endpoint stall state
+  * @param[in]   u32Ep  The USB endpoint ID.
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  * @details     Get USB endpoint stall state of the specified endpoint ID.
+  */
+static __INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep)
+{
+    return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT);
+}
+
+/**
+ * @brief       Get USB endpoint stall state
+ *
+ * @param[in]   u32EpNum         USB endpoint
+ * @retval      0: USB endpoint is not stalled.
+ * @retval      non-0: USB endpoint is stalled.
+ *
+ * @details     Get USB endpoint stall state.
+ */
+static __INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum)
+{
+    uint32_t i;
+    uint32_t val = 0ul;
+
+    for (i=0ul; i<HSUSBD_MAX_EP; i++)
+    {
+        if (((HSUSBD->EP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum)
+        {
+            val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT);
+            break;
+        }
+    }
+    return val;
+}
+
+
+/*-------------------------------------------------------------------------------------------*/
+typedef void (*HSUSBD_VENDOR_REQ)(void); /*!<USB Vendor request callback function */
+typedef void (*HSUSBD_CLASS_REQ)(void); /*!<USB Class request callback function */
+typedef void (*HSUSBD_SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!<USB Standard request "Set Interface" callback function */
+
+void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface);
+void HSUSBD_Start(void);
+void HSUSBD_ProcessSetupPacket(void);
+void HSUSBD_StandardRequest(void);
+void HSUSBD_UpdateDeviceState(void);
+void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
+void HSUSBD_CtrlIn(void);
+void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size);
+void HSUSBD_SwReset(void);
+void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq);
+
+
+
+/*@}*/ /* end of group M480_HSUSBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_HSUSBD_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HSUSBD_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_i2c.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,635 @@
+/**************************************************************************//**
+ * @file     i2c.c
+ * @version  V3.00
+ * @brief    M480 series I2C driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_I2C_Driver I2C Driver
+  @{
+*/
+
+
+/** @addtogroup M480_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable specify I2C Controller and set Clock Divider
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u32BusClock The target I2C bus clock in Hz
+  *
+  * @return     Actual I2C bus clock frequency
+  *
+  * @details    The function enable the specify I2C Controller and set proper Clock Divider
+  *             in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+  *             I2C Bus clock = PCLK / (4*(divider+1).
+  *
+  */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+    uint32_t u32Pclk;
+
+    if(i2c == I2C1) {
+        u32Pclk = CLK_GetPCLK1Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    /* Enable I2C */
+    i2c->CTL0 |= I2C_CTL0_I2CEN_Msk;
+
+    return (u32Pclk / ((u32Div + 1U) << 2U));
+}
+
+/**
+  * @brief      Disable specify I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    Reset I2C Controller and disable specify I2C port.
+    *
+  */
+
+void I2C_Close(I2C_T *i2c)
+{
+    /* Reset I2C Controller */
+    if((uint32_t)i2c == I2C0_BASE) {
+        SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
+    } else if((uint32_t)i2c == I2C1_BASE) {
+        SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
+    }
+
+    /* Disable I2C */
+    i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
+}
+
+/**
+  * @brief      Clear Time-out Counter flag
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
+    *
+  */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+    i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
+}
+
+/**
+  * @brief      Set Control bit of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u8Start     Set I2C START condition
+  * @param[in]  u8Stop      Set I2C STOP condition
+  * @param[in]  u8Si        Clear SI flag
+  * @param[in]  u8Ack       Set I2C ACK bit
+  *
+  * @return     None
+  *
+  * @details    The function set I2C Control bit of I2C Bus protocol.
+  *
+  */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+    uint32_t u32Reg = 0U;
+
+    if(u8Start) {
+        u32Reg |= I2C_CTL_STA;
+    }
+
+    if(u8Stop) {
+        u32Reg |= I2C_CTL_STO;
+    }
+
+    if(u8Si) {
+        u32Reg |= I2C_CTL_SI;
+    }
+
+    if(u8Ack) {
+        u32Reg |= I2C_CTL_AA;
+    }
+
+    i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg;
+}
+
+/**
+  * @brief      Disable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for disable I2C interrupt
+  *
+  */
+void I2C_DisableInt(I2C_T *i2c)
+{
+    i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for enable I2C interrupt
+  *
+  */
+void I2C_EnableInt(I2C_T *i2c)
+{
+    i2c->CTL0 |= I2C_CTL0_INTEN_Msk;
+}
+
+/**
+ * @brief      Get I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     The actual I2C Bus clock in Hz
+ *
+ * @details    To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+    uint32_t u32Divider = i2c->CLKDIV;
+    uint32_t u32Pclk;
+
+    if(i2c == I2C1) {
+        u32Pclk = CLK_GetPCLK1Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    return (u32Pclk / ((u32Divider + 1U) << 2U));
+}
+
+/**
+ * @brief      Set I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u32BusClock  The target I2C Bus Clock in Hz
+ *
+ * @return     The actual I2C Bus Clock in Hz
+ *
+ * @details    To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+    uint32_t u32Pclk;
+
+    if(i2c == I2C1) {
+        u32Pclk = CLK_GetPCLK1Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    return (u32Pclk / ((u32Div + 1U) << 2U));
+}
+
+/**
+ * @brief      Get Interrupt Flag
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C interrupt flag status
+ *
+ * @details    To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+    uint32_t u32Value;
+
+    if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) {
+        u32Value = 1U;
+    } else {
+        u32Value = 0U;
+    }
+
+    return u32Value;
+}
+
+/**
+ * @brief      Get I2C Bus Status Code
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Status Code
+ *
+ * @details    To get I2C Bus Status Code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+    return (i2c->STATUS0);
+}
+
+/**
+ * @brief      Read a Byte from I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Data
+ *
+ * @details    To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+    return (uint8_t)(i2c->DAT);
+}
+
+/**
+ * @brief      Send a byte to I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8Data       The data to send to I2C bus
+ *
+ * @return     None
+ *
+ * @details    This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+    i2c->DAT = u8Data;
+}
+
+/**
+ * @brief      Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8SlaveNo    Set the number of I2C address register (0~3)
+ * @param[in]  u8SlaveAddr  7-bit slave address
+ * @param[in]  u8GCMode     Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ *             and enable GC Mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+    switch(u8SlaveNo) {
+    case 1:
+        i2c->ADDR1  = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+        break;
+    case 2:
+        i2c->ADDR2  = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+        break;
+    case 3:
+        i2c->ADDR3  = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+        break;
+    case 0:
+    default:
+        i2c->ADDR0  = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
+        break;
+    }
+}
+
+/**
+ * @brief      Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SlaveNo        Set the number of I2C address mask register (0~3)
+ * @param[in]  u8SlaveAddrMask  A byte for slave address mask
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+    switch(u8SlaveNo) {
+    case 1:
+        i2c->ADDRMSK1  = (uint32_t)u8SlaveAddrMask << 1U;
+        break;
+    case 2:
+        i2c->ADDRMSK2  = (uint32_t)u8SlaveAddrMask << 1U;
+        break;
+    case 3:
+        i2c->ADDRMSK3  = (uint32_t)u8SlaveAddrMask << 1U;
+        break;
+    case 0:
+    default:
+        i2c->ADDRMSK0  = (uint32_t)u8SlaveAddrMask << 1U;
+        break;
+    }
+}
+
+/**
+ * @brief      Enable Time-out Counter Function and support Long Time-out
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8LongTimeout    Configure DIV4 to enable Long Time-out (0/1)
+ *
+ * @return     None
+ *
+ * @details    This function enable Time-out Counter function and configure DIV4 to support Long
+ *             Time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+    if(u8LongTimeout) {
+        i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
+    } else {
+        i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
+    }
+
+    i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Disable Time-out Counter Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Time-out Counter function in I2CTOC register.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Enable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To enable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      Disable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
+{
+    return (i2c->BUSSTS);
+}
+
+/**
+ * @brief      Clear SMBus Interrupt Flag
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SMBusIntFlag   Specify SMBus interrupt flag
+ *
+ * @return     None
+ *
+ * @details    To clear flags of I2C_BUSSTS status register if interrupt set.
+ *
+ */
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
+{
+    i2c->BUSSTS |= u8SMBusIntFlag;
+}
+
+/**
+ * @brief      Set SMBus Bytes Counts of Transmission or Reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
+{
+    i2c->PKTSIZE = u32PktSize;
+}
+
+/**
+ * @brief      Init SMBus Host/Device Mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8HostDevice     Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
+ *
+ * @return     None
+ *
+ * @details    Using SMBus communication must specify the port is a Host or a Device.
+ *
+ */
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
+{
+    /* Clear  BMHEN, BMDEN of BUSCTL Register */
+    i2c->BUSCTL &=  ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
+
+    /* Set SMBus Host/Device Mode, and enable Bus Management*/
+    if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) {
+        i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+    } else {
+        i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+    }
+}
+
+/**
+ * @brief      Disable SMBus function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
+ *
+ */
+void I2C_SMBusClose(I2C_T *i2c)
+{
+
+    i2c->BUSCTL = 0x00U;
+}
+
+/**
+ * @brief      Enable SMBus PEC Transmit Function
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8PECTxEn        CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    When enable CRC check function, the Host or Device needs to transmit CRC byte.
+ *
+ */
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
+{
+    i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
+
+    if(u8PECTxEn) {
+        i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
+    } else {
+        i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
+    }
+}
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     A byte is packet error check value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
+{
+    return (uint8_t)i2c->PKTCRC;
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus idle period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  us               Time-out length(us)
+ * @param[in]  u32Hclk          I2C peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Idle state.
+ *
+ */
+
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
+{
+    uint32_t  u32Div, u32Hclk_kHz;
+
+    i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
+    u32Hclk_kHz = u32Hclk / 1000U;
+    u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U;
+    if(u32Div > 255U) {
+        i2c->BUSTOUT = 0xFFU;
+    } else {
+        i2c->BUSTOUT = u32Div;
+    }
+
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in active state.
+ *             Time-out length is calculate the SCL line "one clock" pull low timing.
+ *
+ */
+
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000U;
+    u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+    if(u32Div <= 0xFFU) {
+        i2c->BUSTOUT = u32Div;
+    } else {
+        /* DIV4 enabled */
+        i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+        i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+    }
+}
+
+/**
+ * @brief      Calculate Cumulative Clock low Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Active state.
+ *             Time-out length is calculate the SCL line "clocks" low cumulative timing.
+ *
+ */
+
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000U;
+    u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+    if(u32Div <= 0xFFU) {
+        i2c->CLKTOUT = u32Div;
+    } else {
+        /* DIV4 enabled */
+        i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+        i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+    }
+}
+
+/*@}*/ /* end of group M480_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_I2C_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_i2c.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,489 @@
+/****************************************************************************//**
+ * @file     i2c.h
+ * @version  V1.00
+ * @brief    M480 series I2C driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_I2C_Driver I2C Driver
+  @{
+*/
+
+/** @addtogroup M480_I2C_EXPORTED_CONSTANTS I2C Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C_CTL constant definitions.                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_CTL_STA_SI            0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits          \hideinitializer */
+#define I2C_CTL_STA_SI_AA         0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits      \hideinitializer */
+#define I2C_CTL_STO_SI            0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits          \hideinitializer */
+#define I2C_CTL_STO_SI_AA         0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits      \hideinitializer */
+#define I2C_CTL_SI                0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit                   \hideinitializer */
+#define I2C_CTL_SI_AA             0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits           \hideinitializer */
+#define I2C_CTL_STA               0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit                  \hideinitializer */
+#define I2C_CTL_STO               0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit                  \hideinitializer */
+#define I2C_CTL_AA                0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit                   \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C GCMode constant definitions.                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_GCMODE_ENABLE           1    /*!< Enable  I2C GC Mode                                                         \hideinitializer */
+#define I2C_GCMODE_DISABLE          0    /*!< Disable I2C GC Mode                                                         \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C SMBUS constant definitions.                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_SMBH_ENABLE             1    /*!< Enable  SMBus Host Mode enable                                              \hideinitializer */
+#define I2C_SMBD_ENABLE             0    /*!< Enable  SMBus Device Mode enable                                            \hideinitializer */
+#define I2C_PECTX_ENABLE            1    /*!< Enable  SMBus Packet Error Check Transmit function                          \hideinitializer */
+#define I2C_PECTX_DISABLE           0    /*!< Disable SMBus Packet Error Check Transmit function                          \hideinitializer */
+
+/*@}*/ /* end of group M480_I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+/**
+ *    @brief        The macro is used to set I2C bus condition at One Time
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *    @param[in]    u8Ctrl     A byte writes to I2C control register
+ *
+ *    @return       None
+ *
+ *    @details      Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
+ *    \hideinitializer
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
+
+/**
+ *    @brief        The macro is used to set START condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus START condition in I2C_CTL register.
+ *    \hideinitializer
+ */
+#define I2C_START(i2c)  ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
+
+/**
+ *    @brief        The macro is used to wait I2C bus status get ready
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
+ *    \hideinitializer
+ */
+#define I2C_WAIT_READY(i2c)     while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
+
+/**
+ *    @brief        The macro is used to Read I2C Bus Data Register
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       A byte of I2C data register
+ *
+ *    @details      I2C controller read data from bus and save it in I2CDAT register.
+ *    \hideinitializer
+ */
+#define I2C_GET_DATA(i2c)   ((i2c)->DAT)
+
+/**
+ *    @brief        Write a Data to I2C Data Register
+ *
+ *    @param[in]    i2c         Specify I2C port
+ *    @param[in]    u8Data      A byte that writes to data register
+ *
+ *    @return       None
+ *
+ *    @details      When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
+ *    \hideinitializer
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
+
+/**
+ *    @brief        Get I2C Bus status code
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       I2C status code
+ *
+ *    @details      To get this status code to monitor I2C bus event.
+ *    \hideinitializer
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
+
+/**
+ *    @brief        Get Time-out flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       I2C Bus time-out is not happened
+ *    @retval       1       I2C Bus time-out is happened
+ *
+ *    @details      When I2C bus occurs time-out event, the time-out flag will be set.
+ *    \hideinitializer
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c)   ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
+
+/**
+ *    @brief        To get wake-up flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       Chip is not woken-up from power-down mode
+ *    @retval       1       Chip is woken-up from power-down mode
+ *
+ *    @details      I2C bus occurs wake-up event, wake-up flag will be set.
+ *    \hideinitializer
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0  )
+
+/**
+ *    @brief        To clear wake-up flag
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      If wake-up flag is set, use this macro to clear it.
+ *    \hideinitializer
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c)  ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ * \hideinitializer
+ *
+ */
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     Packet error check byte value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ * \hideinitializer
+ */
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
+
+/**
+ * @brief      Set SMBus Bytes number of Transmission or reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
+
+/**
+ * @brief      Enable SMBus Alert function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Disable SMBus Alert pin function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
+ * \hideinitializer
+ */
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is output mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
+ *
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is input mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
+ *
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_IN(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin output high state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
+
+
+/**
+ * @brief      Set SMBus SUSCON pin output low state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ACK_MANUAL(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable acknowledge response control by user.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_ACK_AUTO(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ * \hideinitializer
+ */
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ * \hideinitializer
+ */
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Enable SMBus PEC clear at REPEAT START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable the condition of REAEAT START can clear the PEC calculation.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief      Disable SMBus PEC clear at Repeat START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable the condition of Repeat START can clear the PEC calculation.
+ * \hideinitializer
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
+
+/**
+  * @brief      Enable RX PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define I2C_ENABLE_RX_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+  * @brief      Enable TX PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define I2C_ENABLE_TX_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define I2C_DISABLE_RX_PDMA(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define I2C_DISABLE_TX_PDMA(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+  * @brief      Enable PDMA stretch function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
+  * \hideinitializer
+  */
+#define I2C_ENABLE_PDMA_STRETCH(i2c)   ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
+
+/**
+  * @brief      Disable PDMA stretch function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    I2C will send STOP after PDMA transfers done automatically.
+  * \hideinitializer
+  */
+#define I2C_DISABLE_PDMA_STRETCH(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
+
+/**
+  * @brief      Reset PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    I2C PDMA engine will be reset after this function is called.
+  * \hideinitializer
+  */
+#define I2C_DISABLE_RST_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+  
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ 
+static __INLINE void I2C_STOP(I2C_T *i2c);  
+  
+/**
+ *    @brief        The macro is used to set STOP condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus STOP condition in I2C_CTL register.
+ */
+static __INLINE void I2C_STOP(I2C_T *i2c)
+{
+
+    (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
+    while(i2c->CTL0 & I2C_CTL0_STO_Msk) {
+    }
+}
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
+
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
+void I2C_SMBusClose(I2C_T *i2c);
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+
+/*@}*/ /* end of group M480_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_I2C_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_i2s.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,240 @@
+/**************************************************************************//**
+ * @file     i2s.c
+ * @version  V0.10
+ * @brief    M480 I2S driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup M480_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
+
+/**
+  * @brief  This function is used to get I2S source clock frequency.
+  * @param[in]  i2s is the base address of I2S module.
+  * @return I2S source clock frequency (Hz).
+  */
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
+{
+    uint32_t u32Freq, u32ClkSrcSel;
+
+    /* get I2S selection clock source */
+    u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk;
+
+    switch (u32ClkSrcSel) {
+    case CLK_CLKSEL3_I2S0SEL_HXT:
+        u32Freq = __HXT;
+        break;
+
+    case CLK_CLKSEL3_I2S0SEL_PLL:
+        u32Freq = CLK_GetPLLClockFreq();
+        break;
+
+    case CLK_CLKSEL3_I2S0SEL_HIRC:
+        u32Freq = __HIRC;
+        break;
+
+    case CLK_CLKSEL3_I2S0SEL_PCLK0:
+        u32Freq = (uint32_t)CLK_GetPCLK0Freq();
+        break;
+
+    default:
+        u32Freq = __HIRC;
+        break;
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief  This function configures some parameters of I2S interface for general purpose use.
+  *         The sample rate may not be used from the parameter, it depends on system's clock settings,
+  *         but real sample rate used by system will be returned for reference.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32MasterSlave I2S operation mode. Valid values are:
+  *                                     - \ref I2S_MODE_MASTER
+  *                                     - \ref I2S_MODE_SLAVE
+  * @param[in] u32SampleRate Sample rate
+  * @param[in] u32WordWidth Data length. Valid values are:
+  *                                     - \ref I2S_DATABIT_8
+  *                                     - \ref I2S_DATABIT_16
+  *                                     - \ref I2S_DATABIT_24
+  *                                     - \ref I2S_DATABIT_32
+  * @param[in] u32MonoData: Set audio data to mono or not. Valid values are:
+  *                                     - \ref I2S_ENABLE_MONO
+  *                                     - \ref I2S_DISABLE_MONO
+  * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are:
+  *                                     - \ref I2S_FORMAT_I2S
+  *                                     - \ref I2S_FORMAT_I2S_MSB
+  *                                     - \ref I2S_FORMAT_I2S_LSB
+  *                                     - \ref I2S_FORMAT_PCM
+  *                                     - \ref I2S_FORMAT_PCM_MSB
+  *                                     - \ref I2S_FORMAT_PCM_LSB
+  * @return Real sample rate.
+  */
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
+{
+    uint16_t u16Divider;
+    uint32_t u32BitRate, u32SrcClk;
+
+    SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
+    SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
+
+    i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8;
+
+    u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+    u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U;
+    u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U;
+    i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U);
+
+    /* calculate real sample rate */
+    u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U));
+    u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U);
+
+    i2s->CTL0 |= I2S_CTL0_I2SEN_Msk;
+
+    return u32SampleRate;
+}
+
+/**
+  * @brief  Disable I2S function and I2S clock.
+  * @param[in]  i2s is the base address of I2S module.
+  * @return none
+  */
+void I2S_Close(I2S_T *i2s)
+{
+    i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;
+}
+
+/**
+  * @brief This function enables the interrupt according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt bit.
+  * @return none
+  */
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+    i2s->IEN |= u32Mask;
+}
+
+/**
+  * @brief This function disables the interrupt according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt bit.
+  * @return none
+  */
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+    i2s->IEN &= ~u32Mask;
+}
+
+/**
+  * @brief  Enable MCLK .
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32BusClock is the target MCLK clock
+  * @return Actual MCLK clock
+  */
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
+{
+    uint8_t u8Divider;
+    uint32_t u32SrcClk, u32Reg, u32Clock;
+
+    u32SrcClk = I2S_GetSourceClockFreq(i2s);
+    if (u32BusClock == u32SrcClk) {
+        u8Divider = 0U;
+    } else {
+        u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U;
+    }
+
+    i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
+
+    i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;
+
+    u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
+
+    if (u32Reg == 0U) {
+        u32Clock = u32SrcClk;
+    } else {
+        u32Clock = ((u32SrcClk >> 1U) / u32Reg);
+    }
+
+    return u32Clock;
+}
+
+/**
+  * @brief  Disable MCLK .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  */
+void I2S_DisableMCLK(I2S_T *i2s)
+{
+    i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
+                 (u32TxThreshold << I2S_CTL1_TXTH_Pos) |
+                 (u32RxThreshold << I2S_CTL1_RXTH_Pos));
+}
+
+
+/**
+  * @brief  Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32ChannelWidth Channel width. Valid values are:
+  *                                                             - \ref I2S_TDM_WIDTH_8BIT
+  *                                                             - \ref I2S_TDM_WIDTH_16BIT
+  *                                                             - \ref I2S_TDM_WIDTH_24BIT
+  *                                                             - \ref I2S_TDM_WIDTH_32BIT
+  * @param[in]  u32ChannelNum Channel number. Valid values are:
+  *                                                             - \ref I2S_TDM_2CH
+  *                                                             - \ref I2S_TDM_4CH
+  *                                                             - \ref I2S_TDM_6CH
+  *                                                             - \ref I2S_TDM_8CH
+  * @param[in]  u32SyncWidth Width for sync pulse. Valid values are:
+  *                                                             - \ref I2S_TDM_SYNC_ONE_BCLK
+  *                                                             - \ref I2S_TDM_SYNC_ONE_CHANNEL
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
+{
+    i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
+                 (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
+                 (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
+                 (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos));
+}
+
+/*@}*/ /* end of group M480_I2S_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_I2S_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_i2s.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,350 @@
+/****************************************************************************//**
+ * @file     i2s.h
+ * @version  V0.10
+ * @brief    M480 I2S driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __I2S_H__
+#define __I2S_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup M480_I2S_EXPORTED_CONSTANTS I2S Exported Constants
+  @{
+*/
+#define I2S_DATABIT_8           (0U << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 8-bit  \hideinitializer */
+#define I2S_DATABIT_16          (1U << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 16-bit  \hideinitializer */
+#define I2S_DATABIT_24          (2U << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 24-bit  \hideinitializer */
+#define I2S_DATABIT_32          (3U << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 32-bit  \hideinitializer */
+
+/* Audio Format */
+#define I2S_ENABLE_MONO         I2S_CTL0_MONO_Msk                   /*!< Mono channel  \hideinitializer */
+#define I2S_DISABLE_MONO        (0U)                                /*!< Stereo channel  \hideinitializer */
+
+/* I2S Data Format */
+#define I2S_FORMAT_I2S          (0U << I2S_CTL0_FORMAT_Pos)         /*!< I2S data format  \hideinitializer */
+#define I2S_FORMAT_I2S_MSB      (1U << I2S_CTL0_FORMAT_Pos)         /*!< I2S MSB data format  \hideinitializer */
+#define I2S_FORMAT_I2S_LSB      (2U << I2S_CTL0_FORMAT_Pos)         /*!< I2S LSB data format  \hideinitializer */
+#define I2S_FORMAT_PCM          (4U << I2S_CTL0_FORMAT_Pos)         /*!< PCM data format  \hideinitializer */
+#define I2S_FORMAT_PCM_MSB      (5U << I2S_CTL0_FORMAT_Pos)         /*!< PCM MSB data format  \hideinitializer */
+#define I2S_FORMAT_PCM_LSB      (6U << I2S_CTL0_FORMAT_Pos)         /*!< PCM LSB data format  \hideinitializer */
+
+/* I2S Data Format */
+#define I2S_ORDER_AT_MSB        (0U)                                /*!< Channel data is at MSB  \hideinitializer */
+#define I2S_ORDER_AT_LSB        I2S_CTL0_ORDER_Msk                  /*!< Channel data is at LSB  \hideinitializer */
+
+/* I2S TDM Channel Number */
+#define I2S_TDM_2CH            0U                                   /*!< Use TDM 2 channel  \hideinitializer */
+#define I2S_TDM_4CH            1U                                   /*!< Use TDM 4 channel  \hideinitializer */
+#define I2S_TDM_6CH            2U                                   /*!< Use TDM 6 channel  \hideinitializer */
+#define I2S_TDM_8CH            3U                                   /*!< Use TDM 8 channel  \hideinitializer */
+
+/* I2S TDM Channel Width */
+#define I2S_TDM_WIDTH_8BIT      0U                                  /*!< TDM channel witch is 8-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_16BIT     1U                                  /*!< TDM channel witch is 16-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_24BIT     2U                                  /*!< TDM channel witch is 24-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_32BIT     3U                                  /*!< TDM channel witch is 32-bit  \hideinitializer */
+
+/* I2S TDM Sync Width */
+#define I2S_TDM_SYNC_ONE_BCLK       0U                              /*!< TDM sync widht is one BLCK period  \hideinitializer */
+#define I2S_TDM_SYNC_ONE_CHANNEL    1U                              /*!< TDM sync widht is one channel period  \hideinitializer */
+
+/* I2S Operation mode */
+#define I2S_MODE_SLAVE          I2S_CTL0_SLAVE_Msk                  /*!< As slave mode  \hideinitializer */
+#define I2S_MODE_MASTER         (0u)                                /*!< As master mode  \hideinitializer */
+
+/* I2S FIFO Threshold */
+#define I2S_FIFO_TX_LEVEL_WORD_0    (0U)                             /*!< TX threshold is 0 word  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_1    (1U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 1 word  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_2    (2U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 2 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_3    (3U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 3 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_4    (4U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 4 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_5    (5U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 5 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_6    (6U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 6 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_7    (7U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 7 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_8    (8U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 8 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_9    (9U << I2S_CTL1_TXTH_Pos)        /*!< TX threshold is 9 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_10   (10U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 10 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_11   (11U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 11 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_12   (12U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 12 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_13   (13U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 13 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_14   (14U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 14 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_15   (15U << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 15 words  \hideinitializer */
+
+#define I2S_FIFO_RX_LEVEL_WORD_1    (0U)                             /*!< RX threshold is 1 word  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_2    (1U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 2 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_3    (2U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 3 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_4    (3U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 4 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_5    (4U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 5 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_6    (5U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 6 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_7    (6U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 7 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_8    (7U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 8 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_9    (8U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 9 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_10   (9U << I2S_CTL1_RXTH_Pos)        /*!< RX threshold is 10 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_11   (10U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 11 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_12   (11U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 12 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_13   (12U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 13 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_14   (13U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 14 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_15   (14U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 15 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_16   (15U << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 16 words  \hideinitializer */
+
+/* I2S Record Channel */
+#define I2S_MONO_RIGHT          (0U)                                  /*!< Record mono right channel  \hideinitializer */
+#define I2S_MONO_LEFT           I2S_CTL0_RXLCH_Msk                    /*!< Record mono left channel  \hideinitializer */
+
+/* I2S Channel */
+#define I2S_RIGHT               (0U)                                  /*!< Select right channel  \hideinitializer */
+#define I2S_LEFT                (1U)                                  /*!< Select left channel  \hideinitializer */
+
+/*@}*/ /* end of group M480_I2S_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+  * @brief  Enable zero cross detect function.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+  * @return none
+  * \hideinitializer
+  */
+static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+    if((u32ChMask > 0U) && (u32ChMask < 9U)) {
+        i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
+    }
+}
+
+/**
+  * @brief  Disable zero cross detect function.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+  * @return none
+  * \hideinitializer
+  */
+static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+    if((u32ChMask > 0U) && (u32ChMask < 9U)) {
+        i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
+    }
+}
+
+/**
+  * @brief  Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TXDMA(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S Tx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
+
+/**
+  * @brief  Disable I2S Tx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
+
+/**
+  * @brief  Enable I2S Rx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
+
+/**
+  * @brief  Disable I2S Rx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
+
+/**
+  * @brief  Enable Tx Mute function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
+
+/**
+  * @brief  Disable Tx Mute function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
+
+/**
+  * @brief  Clear Tx FIFO. Internal pointer is reset to FIFO start point.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
+
+/**
+  * @brief  Clear Rx FIFO. Internal pointer is reset to FIFO start point.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
+
+/**
+  * @brief  This function sets the recording source channel when mono mode is used.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Ch left or right channel. Valid values are:
+  *                - \ref I2S_MONO_LEFT
+  *                - \ref I2S_MONO_RIGHT
+  * @return none
+  * \hideinitializer
+  */
+static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
+{
+    u32Ch == I2S_MONO_LEFT ?
+    (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
+    (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
+}
+
+/**
+  * @brief  Write data to I2S Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Data: The data written to FIFO.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TXFIFO = (u32Data) )
+
+/**
+  * @brief  Read Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return Data in Rx FIFO.
+  * \hideinitializer
+  */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
+
+/**
+  * @brief  This function gets the interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return The masked bit value of interrupt flag.
+  * \hideinitializer
+  */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
+
+/**
+  * @brief  This function clears the interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
+
+/**
+  * @brief  This function gets the zero crossing interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return The masked bit value of interrupt flag.
+  * \hideinitializer
+  */
+#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
+
+/**
+  * @brief  This function clears the zero crossing interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
+
+/**
+  * @brief  Get transmit FIFO level
+  * @param[in] i2s is the base address of I2S module.
+  * @return FIFO level
+  * \hideinitializer
+  */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
+
+/**
+  * @brief  Get receive FIFO level
+  * @param[in] i2s is the base address of I2S module.
+  * @return FIFO level
+  * \hideinitializer
+  */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
+
+void I2S_Close(I2S_T *i2s);
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(I2S_T *i2s);
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
+
+/*@}*/ /* end of group M480_I2S_EXPORTED_FUNCTIONS */
+
+
+/*@}*/ /* end of group M480_I2S_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_opa.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,190 @@
+/**************************************************************************//**
+ * @file     opa.h
+ * @version  V3.00
+ * @brief    M480 series OPA driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __OPA_H__
+#define __OPA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup OPA_Driver OPA Driver
+  @{
+*/
+
+/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants
+  @{
+*/
+#define OPA_CALIBRATION_CLK_1K                        (0UL)                     /*!< OPA calibration clock select 1 KHz  \hideinitializer */
+#define OPA_CALIBRATION_RV_1_2_AVDD                   (0UL)                     /*!< OPA calibration reference voltage select 1/2 AVDD  \hideinitializer */
+#define OPA_CALIBRATION_RV_H_L_VCM                    (1UL)                     /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */
+
+/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */
+
+/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define OPA functions prototype                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32LevelSel);
+
+/**
+  * @brief This macro is used to power on the OPA circuit
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will set OPx_EN (x=0, 1) bit of OPACR register to power on the OPA circuit.
+  * \hideinitializer
+  */
+#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to power down the OPA circuit
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will clear OPx_EN (x=0, 1) bit of OPACR register to power down the OPA circuit.
+  * \hideinitializer
+  */
+#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to enable the OPA Schmitt trigger buffer
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will set OPSCHx_EN (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger buffer.
+  * \hideinitializer
+  */
+#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to disable the OPA Schmitt trigger buffer
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will clear OPSCHx_EN (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger buffer.
+  * \hideinitializer
+  */
+#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will set OPDIEx (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger digital output interrupt.
+  * \hideinitializer
+  */
+#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return None
+  * @details This macro will clear OPDIEx (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger digital output interrupt.
+  * \hideinitializer
+  */
+#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
+
+/**
+  * @brief This macro is used to get OPA digital output state
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return  OPA digital output state
+  * @details This macro will return the OPA digital output value.
+  * \hideinitializer
+  */
+#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL)
+
+/**
+  * @brief This macro is used to get OPA interrupt flag
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @retval     0 OPA interrupt does not occur.
+  * @retval     1 OPA interrupt occurs.
+  * @details This macro will return the ACMP interrupt flag.
+  * \hideinitializer
+  */
+#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL)
+
+/**
+  * @brief This macro is used to clear OPA interrupt flag
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @return   None
+  * @details This macro will write 1 to OPDFx (x=0,1) bit of OPASR register to clear interrupt flag.
+  * \hideinitializer
+  */
+#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))
+
+
+/**
+  * @brief This function is used to configure and start OPA calibration
+  * @param[in] opa The pointer of the specified OPA module
+  * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
+  * @param[in] u32ClockSel Select OPA calibration clock
+  *                 - \ref OPA_CALIBRATION_CLK_1K
+  * @param[in] u32RefVol Select OPA reference voltage
+  *                 - \ref OPA_CALIBRATION_RV_1_2_AVDD
+  *                 - \ref OPA_CALIBRATION_RV_H_L_VCM
+  * @retval      0 PMOS and NMOS calibration successfully.
+  * @retval     -1 only PMOS calibration failed.
+  * @retval     -2 only NMOS calibration failed.
+  * @retval     -3 PMOS and NMOS calibration failed.
+  */
+__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa,
+        uint32_t u32OpaNum,
+        uint32_t u32ClockSel,
+        uint32_t u32RefVol)
+{
+    uint32_t u32CALResult;
+    int32_t i32Ret = 0L;
+
+    (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1)));
+    (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum));
+    (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum));
+    while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))){}
+
+    u32CALResult = ((opa)->CALST >> ((u32OpaNum)*4U)) & (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk);
+    if (u32CALResult == 0U) {
+        i32Ret = 0L;
+    } else if (u32CALResult == OPA_CALST_CALNS0_Msk) {
+        i32Ret = -2L;
+    } else if (u32CALResult == OPA_CALST_CALPS0_Msk) {
+        i32Ret = -1L;
+    } else if (u32CALResult == (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk)) {
+        i32Ret = -3L;
+    }
+
+    return i32Ret;
+}
+
+
+
+/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group OPA_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __OPA_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_otg.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,268 @@
+/**************************************************************************//**
+ * @file     otg.h
+ * @version  V0.10
+ * @brief    M480 Series OTG Driver Header File
+ *
+ * @copyright  (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __OTG_H__
+#define __OTG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_OTG_Driver OTG Driver
+  @{
+*/
+
+
+/** @addtogroup M480_OTG_EXPORTED_CONSTANTS OTG Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* OTG constant definitions                                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define OTG_VBUS_EN_ACTIVE_HIGH      (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
+#define OTG_VBUS_EN_ACTIVE_LOW       (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
+#define OTG_VBUS_ST_VALID_HIGH       (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
+#define OTG_VBUS_ST_VALID_LOW        (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
+
+
+/*@}*/ /* end of group M480_OTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_OTG_EXPORTED_FUNCTIONS OTG Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable OTG function
+  * @param None
+  * @return None
+  * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
+  * \hideinitializer
+  */
+#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to disable OTG function
+  * @param None
+  * @return None
+  * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
+  * \hideinitializer
+  */
+#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to enable USB PHY
+  * @param None
+  * @return None
+  * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
+  *          This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
+  * \hideinitializer
+  */
+#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to disable USB PHY
+  * @param None
+  * @return None
+  * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
+  * \hideinitializer
+  */
+#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to enable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
+  * \hideinitializer
+  */
+#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to disable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
+  * \hideinitializer
+  */
+#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to enable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
+  * \hideinitializer
+  */
+#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
+  * \hideinitializer
+  */
+#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref OTG_VBUS_EN_ACTIVE_HIGH
+  *                    - \ref OTG_VBUS_EN_ACTIVE_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+  * \hideinitializer
+  */
+#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_ST pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref OTG_VBUS_ST_VALID_HIGH
+  *                    - \ref OTG_VBUS_ST_VALID_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch status signal.
+  * \hideinitializer
+  */
+#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
+
+/**
+  * @brief This macro is used to enable OTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBEIEN_Msk
+  *                    - \ref OTG_INTEN_SRPFIEN_Msk
+  *                    - \ref OTG_INTEN_HNPFIEN_Msk
+  *                    - \ref OTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref OTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_PDEVIEN_Msk
+  *                    - \ref OTG_INTEN_HOSTIEN_Msk
+  *                    - \ref OTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref OTG_INTEN_SECHGIEN_Msk
+  *                    - \ref OTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will enable OTG related interrupts specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable OTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBEIEN_Msk
+  *                    - \ref OTG_INTEN_SRPFIEN_Msk
+  *                    - \ref OTG_INTEN_HNPFIEN_Msk
+  *                    - \ref OTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref OTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_PDEVIEN_Msk
+  *                    - \ref OTG_INTEN_HOSTIEN_Msk
+  *                    - \ref OTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref OTG_INTEN_SECHGIEN_Msk
+  *                    - \ref OTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to get OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return Interrupt flags of selected sources.
+  * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
+
+/**
+  * @brief This macro is used to clear OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return None
+  * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
+
+/**
+  * @brief This macro is used to get OTG related status
+  * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+  *                    - \ref OTG_STATUS_OVERCUR_Msk
+  *                    - \ref OTG_STATUS_IDSTS_Msk
+  *                    - \ref OTG_STATUS_SESSEND_Msk
+  *                    - \ref OTG_STATUS_BVLD_Msk
+  *                    - \ref OTG_STATUS_AVLD_Msk
+  *                    - \ref OTG_STATUS_VBUSVLD_Msk
+  * @return The user specified status.
+  * @details This macro will return OTG related status specified by u32Mask parameter.
+  * \hideinitializer
+  */
+#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group M480_OTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_OTG_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__OTG_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_pdma.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,419 @@
+/**************************************************************************//**
+ * @file     pdma.c
+ * @version  V1.00
+ * $Revision: 1 $
+ * $Date: 16/06/14 10:23a $
+ * @brief    M480 series PDMA driver source file
+ *
+ * @note
+ * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+static uint32_t u32ChSelect[PDMA_CH_MAX];
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+  @{
+*/
+
+/**
+ * @brief       PDMA Open
+ *
+ * @param[in]   u32Mask     Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable the PDMA channels.
+ */
+void PDMA_Open(uint32_t u32Mask)
+{
+    uint32_t i;
+
+    for (i=0UL; i<PDMA_CH_MAX; i++) {
+        PDMA->DSCT[i].CTL = 0UL;
+        u32ChSelect[i] = PDMA_MEM;
+    }
+
+    PDMA->CHCTL |= u32Mask;
+}
+
+/**
+ * @brief       PDMA Close
+ *
+ * @param       None
+ *
+ * @return      None
+ *
+ * @details     This function disable all PDMA channels.
+ */
+void PDMA_Close(void)
+{
+    PDMA->CHCTL = 0UL;
+}
+
+/**
+ * @brief       Set PDMA Transfer Count
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Width        Data width. Valid values are
+ *                - \ref PDMA_WIDTH_8
+ *                - \ref PDMA_WIDTH_16
+ *                - \ref PDMA_WIDTH_32
+ * @param[in]   u32TransCount   Transfer count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
+}
+
+/**
+ * @brief       Set PDMA Stride Mode
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32DestLen      Destination stride count
+ * @param[in]   u32SrcLen       Source stride count
+ * @param[in]   u32TransCount   Transfer count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected stride mode.
+ */
+void PDMA_SetStride(uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
+{
+    PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
+    PDMA->STRIDE[u32Ch].ASOCR =(u32DestLen<<16) | u32SrcLen;
+    PDMA->STRIDE[u32Ch].STCR = u32TransCount;
+}
+
+/**
+ * @brief       Set PDMA Transfer Address
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32SrcAddr      Source address
+ * @param[in]   u32SrcCtrl      Source control attribute. Valid values are
+ *                - \ref PDMA_SAR_INC
+ *                - \ref PDMA_SAR_FIX
+ * @param[in]   u32DstAddr      destination address
+ * @param[in]   u32DstCtrl      destination control attribute. Valid values are
+ *                - \ref PDMA_DAR_INC
+ *                - \ref PDMA_DAR_FIX
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+    PDMA->DSCT[u32Ch].SA = u32SrcAddr;
+    PDMA->DSCT[u32Ch].DA = u32DstAddr;
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief       Set PDMA Transfer Mode
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Peripheral   The selected peripheral. Valid values are
+ *                - \ref PDMA_MEM
+ *                - \ref PDMA_USB_TX
+ *                - \ref PDMA_USB_RX
+ *                - \ref PDMA_UART0_TX
+ *                - \ref PDMA_UART0_RX
+ *                - \ref PDMA_UART1_TX
+ *                - \ref PDMA_UART1_RX
+ *                - \ref PDMA_UART2_TX
+ *                - \ref PDMA_UART2_RX
+ *                - \ref PDMA_UART3_TX
+ *                - \ref PDMA_UART3_RX
+ *                - \ref PDMA_UART4_TX
+ *                - \ref PDMA_UART4_RX
+ *                - \ref PDMA_UART5_TX
+ *                - \ref PDMA_UART5_RX
+ *                - \ref PDMA_USCI0_TX
+ *                - \ref PDMA_USCI0_RX
+ *                - \ref PDMA_USCI1_TX
+ *                - \ref PDMA_USCI1_RX
+ *                - \ref PDMA_SPI0_TX
+ *                - \ref PDMA_SPI0_RX
+ *                - \ref PDMA_SPI1_TX
+ *                - \ref PDMA_SPI1_RX
+ *                - \ref PDMA_SPI2_TX
+ *                - \ref PDMA_SPI2_RX
+ *                - \ref PDMA_SPI3_TX
+ *                - \ref PDMA_SPI3_RX
+ *                - \ref PDMA_SPI4_TX
+ *                - \ref PDMA_SPI4_RX
+ *                - \ref PDMA_EPWM0_P1_RX
+ *                - \ref PDMA_EPWM0_P2_RX
+ *                - \ref PDMA_EPWM0_P3_RX
+ *                - \ref PDMA_EPWM1_P1_RX
+ *                - \ref PDMA_EPWM1_P2_RX
+ *                - \ref PDMA_EPWM1_P3_RX
+ *                - \ref PDMA_I2C0_TX
+ *                - \ref PDMA_I2C0_RX
+ *                - \ref PDMA_I2C1_TX
+ *                - \ref PDMA_I2C1_RX
+ *                - \ref PDMA_I2C2_TX
+ *                - \ref PDMA_I2C2_RX
+ *                - \ref PDMA_I2S0_TX
+ *                - \ref PDMA_I2S0_RX
+ *                - \ref PDMA_TMR0
+ *                - \ref PDMA_TMR1
+ *                - \ref PDMA_TMR2
+ *                - \ref PDMA_TMR3
+ *                - \ref PDMA_ADC_RX
+ *                - \ref PDMA_DAC0_TX
+ *                - \ref PDMA_DAC1_TX
+ * @param[in]   u32ScatterEn    Scatter-gather mode enable
+ * @param[in]   u32DescAddr     Scatter-gather descriptor address
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+    u32ChSelect[u32Ch] = u32Peripheral;
+    switch(u32Ch) {
+    case 0ul:
+        PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
+        break;
+    case 1ul:
+        PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
+        break;
+    case 2ul:
+        PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
+        break;
+    case 3ul:
+        PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
+        break;
+    case 4ul:
+        PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
+        break;
+    case 5ul:
+        PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
+        break;
+    case 6ul:
+        PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
+        break;
+    case 7ul:
+        PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
+        break;
+    case 8ul:
+        PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
+        break;
+    case 9ul:
+        PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
+        break;
+    case 10ul:
+        PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
+        break;
+    case 11ul:
+        PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
+        break;
+    case 12ul:
+        PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
+        break;
+    case 13ul:
+        PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos);
+        break;
+    case 14ul:
+        PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos);
+        break;
+    case 15ul:
+        PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos);
+        break;
+    default:
+        break;
+    }
+
+    if(u32ScatterEn) {
+        PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+        PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
+    } else {
+        PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
+    }
+}
+
+/**
+ * @brief       Set PDMA Burst Type and Size
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32BurstType    Burst mode or single mode. Valid values are
+ *                - \ref PDMA_REQ_SINGLE
+ *                - \ref PDMA_REQ_BURST
+ * @param[in]   u32BurstSize    Set the size of burst mode. Valid values are
+ *                - \ref PDMA_BURST_128
+ *                - \ref PDMA_BURST_64
+ *                - \ref PDMA_BURST_32
+ *                - \ref PDMA_BURST_16
+ *                - \ref PDMA_BURST_8
+ *                - \ref PDMA_BURST_4
+ *                - \ref PDMA_BURST_2
+ *                - \ref PDMA_BURST_1
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel burst type and size.
+ */
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
+{
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
+}
+
+/**
+ * @brief       Enable timeout function
+ *
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable timeout function of the selected channel(s).
+ */
+void PDMA_EnableTimeout(uint32_t u32Mask)
+{
+    PDMA->TOUTEN |= u32Mask;
+}
+
+/**
+ * @brief       Disable timeout function
+ *
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function disable timeout function of the selected channel(s).
+ */
+void PDMA_DisableTimeout(uint32_t u32Mask)
+{
+    PDMA->TOUTEN &= ~u32Mask;
+}
+
+/**
+ * @brief       Set PDMA Timeout Count
+ *
+ * @param[in]   u32Ch           The selected channel,
+ * @param[in]   u32OnOff        Enable/disable time out function
+ * @param[in]   u32TimeOutCnt   Timeout count
+ *
+ * @return      None
+ *
+ * @details     This function set the timeout count.
+ * @note        M480 only supported channel 0/1.
+ */
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+    switch(u32Ch) {
+    case 0ul:
+        PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
+        break;
+    case 1ul:
+        PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
+        break;
+    default:
+        break;
+    }
+}
+
+/**
+ * @brief       Trigger PDMA
+ *
+ * @param[in]   u32Ch           The selected channel
+ *
+ * @return      None
+ *
+ * @details     This function trigger the selected channel.
+ */
+void PDMA_Trigger(uint32_t u32Ch)
+{
+    if(u32ChSelect[u32Ch] == PDMA_MEM) {
+        PDMA->SWREQ = (1ul << u32Ch);
+    } else {}
+}
+
+/**
+ * @brief       Enable Interrupt
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TEMPTY
+ *                - \ref PDMA_INT_TIMEOUT
+ *
+ * @return      None
+ *
+ * @details     This function enable the selected channel interrupt.
+ */
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask) {
+    case PDMA_INT_TRANS_DONE:
+        PDMA->INTEN |= (1ul << u32Ch);
+        break;
+    case PDMA_INT_TEMPTY:
+        PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
+        break;
+    case PDMA_INT_TIMEOUT:
+        PDMA->TOUTIEN |= (1ul << u32Ch);
+        break;
+
+    default:
+        break;
+    }
+}
+
+/**
+ * @brief       Disable Interrupt
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TEMPTY
+ *                - \ref PDMA_INT_TIMEOUT
+ *
+ * @return      None
+ *
+ * @details     This function disable the selected channel interrupt.
+ */
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask) {
+    case PDMA_INT_TRANS_DONE:
+        PDMA->INTEN &= ~(1ul << u32Ch);
+        break;
+    case PDMA_INT_TEMPTY:
+        PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
+        break;
+    case PDMA_INT_TIMEOUT:
+        PDMA->TOUTIEN &= ~(1ul << u32Ch);
+        break;
+
+    default:
+        break;
+    }
+}
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_pdma.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,369 @@
+/**************************************************************************//**
+ * @file     pdma.h
+ * @version  V1.00
+ * @brief    M480 series PDMA driver header file
+ *
+ * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_H__
+#define __PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+  @{
+*/
+#define PDMA_CH_MAX    16UL   /*!< Specify Maximum Channels of PDMA  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Operation Mode Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_OP_STOP        0x00000000UL            /*!<DMA Stop Mode  \hideinitializer */
+#define PDMA_OP_BASIC       0x00000001UL            /*!<DMA Basic Mode  \hideinitializer */
+#define PDMA_OP_SCATTER     0x00000002UL            /*!<DMA Scatter-gather Mode  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Data Width Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_WIDTH_8        0x00000000UL            /*!<DMA Transfer Width 8-bit  \hideinitializer */
+#define PDMA_WIDTH_16       0x00001000UL            /*!<DMA Transfer Width 16-bit  \hideinitializer */
+#define PDMA_WIDTH_32       0x00002000UL            /*!<DMA Transfer Width 32-bit  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Address Attribute Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_SAR_INC        0x00000000UL            /*!<DMA SAR increment  \hideinitializer */
+#define PDMA_SAR_FIX        0x00000300UL            /*!<DMA SAR fix address  \hideinitializer */
+#define PDMA_DAR_INC        0x00000000UL            /*!<DMA DAR increment  \hideinitializer */
+#define PDMA_DAR_FIX        0x00000C00UL            /*!<DMA DAR fix address  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Burst Mode Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_REQ_SINGLE     0x00000004UL            /*!<DMA Single Request  \hideinitializer */
+#define PDMA_REQ_BURST      0x00000000UL            /*!<DMA Burst Request  \hideinitializer */
+
+#define PDMA_BURST_128      0x00000000UL            /*!<DMA Burst 128 Transfers  \hideinitializer */
+#define PDMA_BURST_64       0x00000010UL            /*!<DMA Burst 64 Transfers  \hideinitializer */
+#define PDMA_BURST_32       0x00000020UL            /*!<DMA Burst 32 Transfers  \hideinitializer */
+#define PDMA_BURST_16       0x00000030UL            /*!<DMA Burst 16 Transfers  \hideinitializer */
+#define PDMA_BURST_8        0x00000040UL            /*!<DMA Burst 8 Transfers  \hideinitializer */
+#define PDMA_BURST_4        0x00000050UL            /*!<DMA Burst 4 Transfers  \hideinitializer */
+#define PDMA_BURST_2        0x00000060UL            /*!<DMA Burst 2 Transfers  \hideinitializer */
+#define PDMA_BURST_1        0x00000070UL            /*!<DMA Burst 1 Transfers  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Table Interrupt Disable Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_TBINTDIS_ENABLE  (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos)  /*!<DMA Table Interrupt Enabled   \hideinitializer */
+#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos)  /*!<DMA Table Interrupt Disabled  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Peripheral Transfer Mode Constant Definitions                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_MEM          0UL   /*!<DMA Connect to Memory \hideinitializer */
+#define PDMA_USB_TX       2UL   /*!<DMA Connect to USB_TX \hideinitializer */
+#define PDMA_USB_RX       3UL /*!<DMA Connect to USB_RX \hideinitializer */
+#define PDMA_UART0_TX     4UL /*!<DMA Connect to UART0_TX \hideinitializer */
+#define PDMA_UART0_RX     5UL /*!<DMA Connect to UART0_RX \hideinitializer */
+#define PDMA_UART1_TX     6UL /*!<DMA Connect to UART1_TX \hideinitializer */
+#define PDMA_UART1_RX     7UL /*!<DMA Connect to UART1_RX \hideinitializer */
+#define PDMA_UART2_TX     8UL /*!<DMA Connect to UART2_TX \hideinitializer */
+#define PDMA_UART2_RX     9UL /*!<DMA Connect to UART2_RX \hideinitializer */
+#define PDMA_UART3_TX    10UL /*!<DMA Connect to UART3_TX \hideinitializer */
+#define PDMA_UART3_RX    11UL /*!<DMA Connect to UART3_RX \hideinitializer */
+#define PDMA_UART4_TX    12UL /*!<DMA Connect to UART4_TX \hideinitializer */
+#define PDMA_UART4_RX    13UL /*!<DMA Connect to UART4_RX \hideinitializer */
+#define PDMA_UART5_TX    14UL /*!<DMA Connect to UART5_TX \hideinitializer */
+#define PDMA_UART5_RX    15UL /*!<DMA Connect to UART5_RX \hideinitializer */
+#define PDMA_USCI0_TX    16UL /*!<DMA Connect to USCI0_TX \hideinitializer */
+#define PDMA_USCI0_RX    17UL /*!<DMA Connect to USCI0_RX \hideinitializer */
+#define PDMA_USCI1_TX    18UL /*!<DMA Connect to USCI1_TX \hideinitializer */
+#define PDMA_USCI1_RX    19UL /*!<DMA Connect to USCI1_RX \hideinitializer */
+#define PDMA_SPI0_TX     20UL /*!<DMA Connect to SPI0_TX \hideinitializer */
+#define PDMA_SPI0_RX     21UL /*!<DMA Connect to SPI0_RX \hideinitializer */
+#define PDMA_SPI1_TX     22UL /*!<DMA Connect to SPI1_TX \hideinitializer */
+#define PDMA_SPI1_RX     23UL /*!<DMA Connect to SPI1_RX \hideinitializer */
+#define PDMA_SPI2_TX     24UL /*!<DMA Connect to SPI2_TX \hideinitializer */
+#define PDMA_SPI2_RX     25UL /*!<DMA Connect to SPI2_RX \hideinitializer */
+#define PDMA_SPI3_TX     26UL /*!<DMA Connect to SPI3_TX \hideinitializer */
+#define PDMA_SPI3_RX     27UL /*!<DMA Connect to SPI3_RX \hideinitializer */
+#define PDMA_SPI4_TX     28UL /*!<DMA Connect to SPI4_TX \hideinitializer */
+#define PDMA_SPI4_RX     29UL /*!<DMA Connect to SPI4_RX \hideinitializer */
+#define PDMA_EPWM0_P1_RX  32UL /*!<DMA Connect to EPWM0_P1 \hideinitializer */
+#define PDMA_EPWM0_P2_RX  33UL /*!<DMA Connect to EPWM0_P2 \hideinitializer */
+#define PDMA_EPWM0_P3_RX  34UL /*!<DMA Connect to EPWM0_P3 \hideinitializer */
+#define PDMA_EPWM1_P1_RX  35UL /*!<DMA Connect to EPWM1_P1 \hideinitializer */
+#define PDMA_EPWM1_P2_RX  36UL /*!<DMA Connect to EPWM1_P2 \hideinitializer */
+#define PDMA_EPWM1_P3_RX  37UL /*!<DMA Connect to PWM1_P3 \hideinitializer */
+#define PDMA_I2C0_TX     38UL /*!<DMA Connect to I2C0_TX \hideinitializer */
+#define PDMA_I2C0_RX     39UL /*!<DMA Connect to I2C0_RX \hideinitializer */
+#define PDMA_I2C1_TX     40UL /*!<DMA Connect to I2C1_TX \hideinitializer */
+#define PDMA_I2C1_RX     41UL /*!<DMA Connect to I2C1_RX \hideinitializer */
+#define PDMA_I2C2_TX     42UL /*!<DMA Connect to I2C2_TX \hideinitializer */
+#define PDMA_I2C2_RX     43UL /*!<DMA Connect to I2C2_RX \hideinitializer */
+#define PDMA_I2S0_TX     44UL /*!<DMA Connect to I2S0_TX \hideinitializer */
+#define PDMA_I2S0_RX     45UL /*!<DMA Connect to I2S0_RX \hideinitializer */
+#define PDMA_TMR0        46UL /*!<DMA Connect to TMR0 \hideinitializer */
+#define PDMA_TMR1        47UL /*!<DMA Connect to TMR1 \hideinitializer */
+#define PDMA_TMR2        48UL /*!<DMA Connect to TMR2 \hideinitializer */
+#define PDMA_TMR3        49UL /*!<DMA Connect to TMR3 \hideinitializer */
+#define PDMA_ADC_RX      50UL /*!<DMA Connect to ADC_RX \hideinitializer */
+#define PDMA_DAC0_TX     51UL /*!<DMA Connect to DAC0_TX \hideinitializer */
+#define PDMA_DAC1_TX     52UL /*!<DMA Connect to DAC1_TX \hideinitializer */
+#define EPWM0_CH0_TX      53UL /*!<DMA Connect to EPWM0_CH0_TX \hideinitializer */
+#define EPWM0_CH1_TX      54UL /*!<DMA Connect to EPWM0_CH1_TX \hideinitializer */
+#define EPWM0_CH2_TX      55UL /*!<DMA Connect to EPWM0_CH2_TX \hideinitializer */
+#define EPWM0_CH3_TX      56UL /*!<DMA Connect to EPWM0_CH3_TX \hideinitializer */
+#define EPWM0_CH4_TX      57UL /*!<DMA Connect to EPWM0_CH4_TX \hideinitializer */
+#define EPWM0_CH5_TX      58UL /*!<DMA Connect to EPWM0_CH5_TX \hideinitializer */
+#define EPWM1_CH0_TX      59UL /*!<DMA Connect to EPWM1_CH0_TX \hideinitializer */
+#define EPWM1_CH1_TX      60UL /*!<DMA Connect to EPWM1_CH1_TX \hideinitializer */
+#define EPWM1_CH2_TX      61UL /*!<DMA Connect to EPWM1_CH2_TX \hideinitializer */
+#define EPWM1_CH3_TX      62UL /*!<DMA Connect to EPWM1_CH3_TX \hideinitializer */
+#define EPWM1_CH4_TX      63UL /*!<DMA Connect to EPWM1_CH4_TX \hideinitializer */
+#define EPWM1_CH5_TX      64UL /*!<DMA Connect to EPWM1_CH5_TX \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Interrupt Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_INT_TRANS_DONE 0x00000000UL            /*!<Transfer Done Interrupt  \hideinitializer */
+#define PDMA_INT_TEMPTY     0x00000001UL            /*!<Table Empty Interrupt  \hideinitializer */
+#define PDMA_INT_TIMEOUT    0x00000002UL            /*!<Timeout Interrupt \hideinitializer */
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Get PDMA Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This macro gets the interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
+
+/**
+ * @brief       Get Transfer Done Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the transfer done Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
+
+/**
+ * @brief       Clear Transfer Done Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the transfer done Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = (u32Mask)))
+
+/**
+ * @brief       Get Target Abort Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the target abort Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
+
+/**
+ * @brief       Clear Target Abort Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the target abort Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = (u32Mask)))
+
+/**
+ * @brief       Get Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the scatter-gather table empty Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
+
+/**
+ * @brief       Clear Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the scatter-gather table empty Interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = (u32Mask)))
+
+/**
+ * @brief       Clear Timeout Interrupt Status
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @return      None
+ *
+ * @details     Clear the selected channel timeout interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << ((u32Ch) + 8))))
+
+/**
+ * @brief       Check Channel Status
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @retval      0 Idle state
+ * @retval      1 Busy state
+ *
+ * @details     Check the selected channel is busy or not.
+ * \hideinitializer
+ */
+#define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << (u32Ch)))? 1 : 0)
+
+/**
+ * @brief       Set Source Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel source address.
+ * \hideinitializer
+ */
+#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].SA = (u32Addr)))
+
+/**
+ * @brief       Set Destination Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel destination address.
+ * \hideinitializer
+ */
+#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].DA = (u32Addr)))
+
+/**
+ * @brief       Set Transfer Count
+ *
+ * @param[in]   u32Ch          The selected channel
+ * @param[in]   u32TransCount  Transfer Count
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel transfer count.
+ * \hideinitializer
+ */
+#define PDMA_SET_TRANS_CNT(u32Ch, u32TransCount) ((uint32_t)(PDMA->DSCT[(u32Ch)].CTL=(PDMA->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
+
+/**
+ * @brief       Set Scatter-gather descriptor Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The descriptor address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel scatter-gather descriptor address.
+ * \hideinitializer
+ */
+#define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].NEXT = (u32Addr) - (PDMA->SCATBA)))
+
+/**
+ * @brief       Stop the channel
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro stop the selected channel.
+ * \hideinitializer
+ */
+#define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->PAUSE = (1 << (u32Ch))))
+
+/**
+ * @brief       Pause the channel
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro pause the selected channel.
+ * \hideinitializer
+ */
+#define PDMA_PAUSE(u32Ch) ((uint32_t)(PDMA->PAUSE = (1 << (u32Ch))))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PDMA functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+void PDMA_Open(uint32_t u32Mask);
+void PDMA_Close(void);
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
+void PDMA_EnableTimeout(uint32_t u32Mask);
+void PDMA_DisableTimeout(uint32_t u32Mask);
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(uint32_t u32Ch);
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_SetStride(uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PDMA_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_qei.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file     qei.c
+ * @version  V3.00
+ * $Revision: 1 $
+ * $Date: 16/06/16 10:23a $
+ * @brief    Quadrature Encoder Interface (QEI) driver source file
+ *
+ * @note
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+  @{
+*/
+
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Close QEI function
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function reset QEI configuration and stop QEI counting.
+  */
+void QEI_Close(QEI_T* qei)
+{
+    /* Reset QEI configuration */
+    qei->CTL = (uint32_t)0;
+}
+
+/**
+  * @brief      Disable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This function disable QEI specified interrupt.
+  */
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+    /* Disable QEI specified interrupt */
+    QEI_DISABLE_INT(qei, u32IntSel);
+
+    /* Disable NVIC QEI IRQ */
+    if(qei ==(QEI_T*)QEI0) {
+        NVIC_DisableIRQ((IRQn_Type)QEI0_IRQn);
+    } else {
+        NVIC_DisableIRQ((IRQn_Type)QEI1_IRQn);
+    }
+}
+
+/**
+  * @brief      Enable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This function enable QEI specified interrupt.
+  */
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+    /* Enable QEI specified interrupt */
+    QEI_ENABLE_INT(qei, u32IntSel);
+
+    /* Enable NVIC QEI IRQ */
+    if(qei == (QEI_T*)QEI0) {
+        NVIC_EnableIRQ(QEI0_IRQn);
+    } else {
+        NVIC_EnableIRQ(QEI1_IRQn);
+    }
+}
+
+/**
+  * @brief      Open QEI in specified mode and enable input
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Mode     QEI counting mode.
+  *                         - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+  * @param[in]  u32Value    The counter maximum value in compare-counting mode.
+  * @return     None
+  * @details    This function set QEI in specified mode and enable input.
+  */
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value)
+{
+    /* Set QEI function configuration */
+    /* Set QEI counting mode */
+    /* Enable IDX, QEA and QEB input to QEI controller */
+    qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk);
+
+    /* Set QEI maximum count value in in compare-counting mode */
+    qei->CNTMAX = u32Value;
+}
+
+/**
+  * @brief      Start QEI function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function enable QEI function and start QEI counting.
+  */
+void QEI_Start(QEI_T* qei)
+{
+    /* Enable QEI controller function */
+    qei->CTL |= QEI_CTL_QEIEN_Msk;
+}
+
+/**
+  * @brief      Stop QEI function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function disable QEI function and stop QEI counting.
+  */
+void QEI_Stop(QEI_T* qei)
+{
+    /* Disable QEI controller function */
+    qei->CTL &= (~QEI_CTL_QEIEN_Msk);
+}
+
+
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QEI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_qei.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,389 @@
+/**************************************************************************//**
+ * @file     qei.h
+ * @version  V3.00
+ * @brief    Quadrature Encoder Interface (QEI) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __QEI_H__
+#define __QEI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+  @{
+*/
+
+/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* QEI counting mode selection constants definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define QEI_CTL_X4_FREE_COUNTING_MODE       (0x0<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 free-counting mode \hideinitializer */
+#define QEI_CTL_X2_FREE_COUNTING_MODE       (0x1<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 free-counting mode \hideinitializer */
+#define QEI_CTL_X4_COMPARE_COUNTING_MODE    (0x2<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 compare-counting mode \hideinitializer */
+#define QEI_CTL_X2_COMPARE_COUNTING_MODE    (0x3<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 compare-counting mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* QEI noise filter clock pre-divide selection constants definitions                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define QEI_CTL_NFCLKSEL_DIV1   (0x0<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK \hideinitializer */
+#define QEI_CTL_NFCLKSEL_DIV2   (0x1<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/2 \hideinitializer */
+#define QEI_CTL_NFCLKSEL_DIV4   (0x2<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/4 \hideinitializer */
+#define QEI_CTL_NFCLKSEL_DIV16  (0x3<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 \hideinitializer */
+#define QEI_CTL_NFCLKSEL_DIV32  (0x4<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 \hideinitializer */
+#define QEI_CTL_NFCLKSEL_DIV64  (0x5<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 \hideinitializer */
+
+
+
+
+/*@}*/ /* end of group QEI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Disable QEI compare function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI counter compare function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_CNT_CMP(qei)    ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))
+
+/**
+  * @brief      Enable QEI compare function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI counter compare function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_CNT_CMP(qei)     ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
+
+/**
+  * @brief      Disable QEI index latch function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI index trigger counter latch function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INDEX_LATCH(qei)     ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
+
+/**
+  * @brief      Enable QEI index latch function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI index trigger counter latch function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INDEX_LATCH(qei)     ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
+
+/**
+  * @brief      Disable QEI index reload function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI index trigger counter reload function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INDEX_RELOAD(qei)    ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
+
+/**
+  * @brief      Enable QEI index reload function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI index trigger counter reload function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INDEX_RELOAD(qei)    ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
+
+/**
+  * @brief      Disable QEI input
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type.
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEA input
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEB input
+  *                             - \ref QEI_CTL_IDXEN_Msk    : IDX input
+  * @return     None
+  * @details    This macro disable specified QEI signal input.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INPUT(qei, u32InputType)     ((qei)->CTL &= ~(u32InputType))
+
+/**
+  * @brief      Enable QEI input
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type .
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEA input
+  *                             - \ref QEI_CTL_CHBEN_Msk    : QEB input
+  *                             - \ref QEI_CTL_IDXEN_Msk    : IDX input
+  * @return     None
+  * @details    This macro enable specified QEI signal input.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INPUT(qei, u32InputType)     ((qei)->CTL |= (u32InputType))
+
+/**
+  * @brief      Disable inverted input polarity
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type .
+  *                             - \ref QEI_CTL_CHAINV_Msk   : QEA Input
+  *                             - \ref QEI_CTL_CHBINV_Msk   : QEB Input
+  *                             - \ref QEI_CTL_IDXINV_Msk   : IDX Input
+  * @return     None
+  * @details    This macro disable specified QEI signal inverted input polarity.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INPUT_INV(qei, u32InputType)    ((qei)->CTL &= ~(u32InputType))
+
+/**
+  * @brief      Enable inverted input polarity
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type.
+  *                             - \ref QEI_CTL_CHAINV_Msk   : QEA Input
+  *                             - \ref QEI_CTL_CHBINV_Msk   : QEB Input
+  *                             - \ref QEI_CTL_IDXINV_Msk   : IDX Input
+  * @return     None
+  * @details    This macro inverse specified QEI signal input polarity.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INPUT_INV(qei, u32InputType)     ((qei)->CTL |= (u32InputType))
+
+/**
+  * @brief      Disable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This macro disable specified QEI interrupt.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INT(qei, u32IntSel)     ((qei)->CTL &= ~(u32IntSel))
+
+/**
+  * @brief      Enable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This macro disable specified QEI interrupt.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INT(qei, u32IntSel)      ((qei)->CTL |= (u32IntSel))
+
+/**
+  * @brief      Disable QEI noise filter
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI noise filter function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_NOISE_FILTER(qei)       ((qei)->CTL |= QEI_CTL_NFDIS_Msk)
+
+/**
+  * @brief      Enable QEI noise filter
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32ClkSel   The sampling frequency of the noise filter clock.
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV1
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV2
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV4
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV16
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV32
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV64
+  * @return     None
+  * @details    This macro enable QEI noise filter function and select noise filter clock.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel)     ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))
+
+/**
+  * @brief      Get QEI counter value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter register value.
+  * @details    This macro get QEI pulse counter value.
+  * \hideinitializer
+  */
+#define QEI_GET_CNT_VALUE(qei)      ((qei)->CNT)
+
+/**
+  * @brief      Get QEI counting direction
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @retval     0       QEI counter is in down-counting.
+  * @retval     1       QEI counter is in up-counting.
+  * @details    This macro get QEI counting direction.
+  * \hideinitializer
+  */
+#define QEI_GET_DIR(qei)    (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
+
+/**
+  * @brief      Get QEI counter hold value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter hold register value.
+  * @details    This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.
+  * \hideinitializer
+  */
+#define QEI_GET_HOLD_VALUE(qei)     ((qei)->CNTHOLD)
+
+/**
+  * @brief      Get QEI counter index latch value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter index latch value
+  * @details    This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+  * \hideinitializer
+  */
+#define QEI_GET_INDEX_LATCH_VALUE(qei)     ((qei)->CNTLATCH)
+
+/**
+  * @brief      Set QEI counter index latch value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @param[in]  u32Val  The latch value.
+  * @return     QEI pulse counter index latch value
+  * @details    This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+  * \hideinitializer
+  */
+#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val)     ((qei)->CNTLATCH = (u32Val))
+
+/**
+  * @brief      Get QEI interrupt flag status
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+*                           - \ref QEI_STATUS_DIRF_Msk      : Counting direction flag
+  *                         - \ref QEI_STATUS_DIRCHGF_Msk   : Direction change flag
+  *                         - \ref QEI_STATUS_OVUNF_Msk     : Counter overflow or underflow flag
+  *                         - \ref QEI_STATUS_CMPF_Msk      : Compare-match flag
+  *                         - \ref QEI_STATUS_IDXF_Msk      : Index detected flag
+  * @retval     0           QEI specified interrupt flag is not set.
+  * @retval     1           QEI specified interrupt flag is set.
+  * @details    This macro get QEI specified interrupt flag status.
+  * \hideinitializer
+  */
+#define QEI_GET_INT_FLAG(qei, u32IntSel)        (((qei)->STATUS & (u32IntSel))?1:0)
+
+
+/**
+  * @brief      Clear QEI interrupt flag
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_STATUS_DIRCHGF_Msk   : Direction change flag
+  *                         - \ref QEI_STATUS_OVUNF_Msk     : Counter overflow or underflow flag
+  *                         - \ref QEI_STATUS_CMPF_Msk      : Compare-match flag
+  *                         - \ref QEI_STATUS_IDXF_Msk      : Index detected flag
+  * @return     None
+  * @details    This macro clear QEI specified interrupt flag.
+  * \hideinitializer
+  */
+#define QEI_CLR_INT_FLAG(qei, u32IntSel)     ((qei)->STATUS = (u32IntSel))
+
+/**
+  * @brief      Set QEI counter compare value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter compare value.
+  * @return     None
+  * @details    This macro set QEI pulse counter compare value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_CMP(qei, u32Value)      ((qei)->CNTCMP = (u32Value))
+
+/**
+  * @brief      Set QEI counter value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter compare value.
+  * @return     None
+  * @details    This macro set QEI pulse counter compare value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_VALUE(qei, u32Value)      ((qei)->CNT = (u32Value))
+
+/**
+  * @brief      Enable QEI counter hold mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Type     The triggered type.
+  *                         - \ref QEI_CTL_HOLDCNT_Msk      : Hold QEI_CNT control
+  *                         - \ref QEI_CTL_HOLDTMR0_Msk     : Hold QEI_CNT by Timer0
+  *                         - \ref QEI_CTL_HOLDTMR1_Msk     : Hold QEI_CNT by Timer1
+  *                         - \ref QEI_CTL_HOLDTMR2_Msk     : Hold QEI_CNT by Timer2
+  *                         - \ref QEI_CTL_HOLDTMR3_Msk     : Hold QEI_CNT by Timer3
+  * @return     None
+  * @details    This macro set QEI counter hold mode.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL |= (u32Type))
+
+/**
+  * @brief      Disable QEI counter hold mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Type     The triggered type.
+  *                         - \ref QEI_CTL_HOLDCNT_Msk      : Hold QEI_CNT control
+  *                         - \ref QEI_CTL_HOLDTMR0_Msk     : Hold QEI_CNT by Timer0
+  *                         - \ref QEI_CTL_HOLDTMR1_Msk     : Hold QEI_CNT by Timer1
+  *                         - \ref QEI_CTL_HOLDTMR2_Msk     : Hold QEI_CNT by Timer2
+  *                         - \ref QEI_CTL_HOLDTMR3_Msk     : Hold QEI_CNT by Timer3
+  * @return     None
+  * @details    This macro set QEI counter hold mode.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL &= ~(u32Type))
+
+/**
+  * @brief      Set QEI maximum count value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter maximum value.
+  * @return     QEI maximum count value
+  * @details    This macro set QEI maximum count value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_MAX(qei, u32Value)      ((qei)->CNTMAX = (u32Value))
+
+/**
+  * @brief      Set QEI counting mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Mode     QEI counting mode.
+  *                         - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+  * @return     None
+  * @details    This macro set QEI counting mode.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_MODE(qei, u32Mode)       ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))
+
+
+void QEI_Close(QEI_T* qei);
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value);
+void QEI_Start(QEI_T* qei);
+void QEI_Stop(QEI_T* qei);
+
+
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QEI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QEI_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_rtc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,965 @@
+/**************************************************************************//**
+ * @file     rtc.c
+ * @version  V3.00
+ * $Revision: 5 $
+ * $Date: 14/06/10 5:49p $
+ * @brief    M480 series RTC driver source file
+ *
+ * @note
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup M480_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize RTC module and start counting
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This function is used to: \n
+  *                 1. Write initial key to let RTC start count.  \n
+  *                 2. Input parameter indicates start date/time. \n
+  *                 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+  * @note       Null pointer for using default starting date/time.
+  */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+    RTC->INIT = RTC_INIT_KEY;
+
+    if(RTC->INIT != RTC_INIT_ACTIVE_Msk) {
+        RTC->INIT = RTC_INIT_KEY;
+        while(RTC->INIT != RTC_INIT_ACTIVE_Msk) {
+        }
+    }
+
+    if(sPt == 0) {
+    } else {
+        /* Set RTC date and time */
+        RTC_SetDateAndTime(sPt);
+    }
+}
+
+/**
+  * @brief      Disable RTC Clock
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API will disable RTC peripheral clock and stops RTC counting.
+  */
+void RTC_Close(void)
+{
+    CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+}
+
+/**
+ *  @brief    Set Frequency Compensation Data
+  *
+ *  @param[in]    i32FrequencyX10000    Specify the RTC clock X10000, ex: 327736512 means 32773.6512.
+  *
+  * @return     None
+  *
+  */
+void RTC_32KCalibration(int32_t i32FrequencyX10000)
+{
+    uint64_t u64Compensate;
+
+    u64Compensate = (uint64_t)(0x2710000000000);
+    u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);
+
+    if(u64Compensate >= (uint64_t)0x400000) {
+        u64Compensate = (uint64_t)0x3FFFFF;
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->FREQADJ = (uint32_t)u64Compensate;
+}
+
+/**
+  * @brief      Get Current RTC Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the current RTC value. It includes: \n
+  *                     u32Year: Year value                                                   \n
+  *                     u32Month: Month value                                                 \n
+  *                     u32Day: Day value                                                     \n
+  *                     u32DayOfWeek: Day of week                                             \n
+  *                     u32Hour: Hour value                                                   \n
+  *                     u32Minute: Minute value                                               \n
+  *                     u32Second: Second value                                               \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                           \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                             \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the current RTC date and time value.
+  */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get [Date digit] data */
+    g_u32hiYear  = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+    g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+    g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+    g_u32hiDay   = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+    g_u32loDay   = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+
+    /* Get [Time digit] data */
+    g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+    g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+    g_u32hiMin  = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+    g_u32loMin  = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+    g_u32hiSec  = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+    g_u32loSec  = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10ul);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10ul);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10ul);
+    sPt->u32Day =  u32Tmp  + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == RTC_CLOCK_12) {
+        u32Tmp = (g_u32hiHour * 10ul);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21ul) {
+            sPt->u32AmPm  = RTC_PM;
+            sPt->u32Hour -= 20ul;
+        } else {
+            sPt->u32AmPm = RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin  * 10ul);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec  * 10ul);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    } else {
+        u32Tmp  = (g_u32hiHour * 10ul);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10ul);
+        u32Tmp +=  g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10ul);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Get RTC Alarm Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the RTC alarm value. It includes: \n
+  *                     u32Year: Year value                                                 \n
+  *                     u32Month: Month value                                               \n
+  *                     u32Day: Day value                                                   \n
+  *                     u32DayOfWeek: Day of week                                           \n
+  *                     u32Hour: Hour value                                                 \n
+  *                     u32Minute: Minute value                                             \n
+  *                     u32Second: Second value                                             \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                         \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                           \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the RTC alarm date and time setting.
+  */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get alarm [Date digit] data */
+    RTC_WaitAccessEnable();
+    g_u32hiYear  = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+    g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+    g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+    g_u32hiDay   = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+    g_u32loDay   = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+
+    /* Get alarm [Time digit] data */
+    RTC_WaitAccessEnable();
+    g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+    g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+    g_u32hiMin  = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+    g_u32loMin  = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+    g_u32hiSec  = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+    g_u32loSec  = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10ul);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10ul);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10ul);
+    sPt->u32Day = u32Tmp + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == RTC_CLOCK_12) {
+        u32Tmp  = (g_u32hiHour * 10ul);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21ul) {
+            sPt->u32AmPm  = RTC_PM;
+            sPt->u32Hour -= 20ul;
+        } else {
+            sPt->u32AmPm = RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin * 10ul);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10ul);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+
+    } else {
+        u32Tmp  = (g_u32hiHour * 10ul);
+        u32Tmp +=  g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10ul);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10ul);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Update Current RTC Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date and time to RTC.
+  */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCAL, u32RegTIME;
+
+    if(sPt == 0ul) {
+    } else {
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+        /*-----------------------------------------------------------------------------------------------------*/
+        RTC_WaitAccessEnable();
+        if(sPt->u32TimeScale == RTC_CLOCK_12) {
+            RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+            /*-------------------------------------------------------------------------------------------------*/
+            /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+            /*-------------------------------------------------------------------------------------------------*/
+            if(sPt->u32AmPm == RTC_PM) {
+                sPt->u32Hour += 20ul;
+            }
+        } else {
+            RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+        }
+
+        /* Set Day of the Week */
+        RTC_WaitAccessEnable();
+        RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Current Date and Time                                                                       */
+        /*-----------------------------------------------------------------------------------------------------*/
+        u32RegCAL  = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+        u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+        u32RegCAL |= ((sPt->u32Month  / 10ul) << 12);
+        u32RegCAL |= ((sPt->u32Month  % 10ul) << 8);
+        u32RegCAL |= ((sPt->u32Day    / 10ul) << 4);
+        u32RegCAL |= (sPt->u32Day     % 10ul);
+
+        u32RegTIME  = ((sPt->u32Hour   / 10ul) << 20);
+        u32RegTIME |= ((sPt->u32Hour   % 10ul) << 16);
+        u32RegTIME |= ((sPt->u32Minute / 10ul) << 12);
+        u32RegTIME |= ((sPt->u32Minute % 10ul) << 8);
+        u32RegTIME |= ((sPt->u32Second / 10ul) << 4);
+        u32RegTIME |= (sPt->u32Second % 10ul);
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Calender and Time Loading                                                                   */
+        /*-----------------------------------------------------------------------------------------------------*/
+        RTC_WaitAccessEnable();
+        RTC->CAL  = (uint32_t)u32RegCAL;
+        RTC_WaitAccessEnable();
+        RTC->TIME = (uint32_t)u32RegTIME;
+    }
+}
+
+/**
+  * @brief      Update RTC Alarm Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and alarm date and time. It includes:             \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date and time setting to RTC.
+  */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCALM, u32RegTALM;
+
+    if(sPt == 0) {
+    } else {
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+        /*-----------------------------------------------------------------------------------------------------*/
+        RTC_WaitAccessEnable();
+        if(sPt->u32TimeScale == RTC_CLOCK_12) {
+            RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+            /*-------------------------------------------------------------------------------------------------*/
+            /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+            /*-------------------------------------------------------------------------------------------------*/
+            if(sPt->u32AmPm == RTC_PM) {
+                sPt->u32Hour += 20ul;
+            }
+        } else {
+            RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+        }
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Alarm Date and Time                                                                         */
+        /*-----------------------------------------------------------------------------------------------------*/
+        u32RegCALM  = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+        u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+        u32RegCALM |= ((sPt->u32Month  / 10ul) << 12);
+        u32RegCALM |= ((sPt->u32Month  % 10ul) << 8);
+        u32RegCALM |= ((sPt->u32Day    / 10ul) << 4);
+        u32RegCALM |= (sPt->u32Day    % 10ul);
+
+        u32RegTALM  = ((sPt->u32Hour   / 10ul) << 20);
+        u32RegTALM |= ((sPt->u32Hour   % 10ul) << 16);
+        u32RegTALM |= ((sPt->u32Minute / 10ul) << 12);
+        u32RegTALM |= ((sPt->u32Minute % 10ul) << 8);
+        u32RegTALM |= ((sPt->u32Second / 10ul) << 4);
+        u32RegTALM |= (sPt->u32Second % 10ul);
+
+        RTC_WaitAccessEnable();
+        RTC->CALM = (uint32_t)u32RegCALM;
+        RTC_WaitAccessEnable();
+        RTC->TALM = (uint32_t)u32RegTALM;
+    }
+}
+
+/**
+  * @brief      Update RTC Current Date
+  *
+  * @param[in]  u32Year         The year calendar digit of current RTC setting.
+  * @param[in]  u32Month        The month calendar digit of current RTC setting.
+  * @param[in]  u32Day          The day calendar digit of current RTC setting.
+  * @param[in]  u32DayOfWeek    The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                   RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                   RTC_SATURDAY]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date to RTC.
+  */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+    uint32_t u32RegCAL;
+
+    u32RegCAL  = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+    u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+    u32RegCAL |= ((u32Month / 10ul) << 12);
+    u32RegCAL |= ((u32Month % 10ul) << 8);
+    u32RegCAL |= ((u32Day   / 10ul) << 4);
+    u32RegCAL |= (u32Day   % 10ul);
+
+    /* Set Day of the Week */
+    RTC_WaitAccessEnable();
+    RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+
+    /* Set RTC Calender Loading */
+    RTC_WaitAccessEnable();
+    RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+  * @brief      Update RTC Current Time
+  *
+  * @param[in]  u32Hour         The hour time digit of current RTC setting.
+  * @param[in]  u32Minute       The minute time digit of current RTC setting.
+  * @param[in]  u32Second       The second time digit of current RTC setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current time to RTC.
+  */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTIME;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) {
+        u32Hour += 20ul;
+    }
+
+    u32RegTIME  = ((u32Hour   / 10ul) << 20);
+    u32RegTIME |= ((u32Hour   % 10ul) << 16);
+    u32RegTIME |= ((u32Minute / 10ul) << 12);
+    u32RegTIME |= ((u32Minute % 10ul) << 8);
+    u32RegTIME |= ((u32Second / 10ul) << 4);
+    u32RegTIME |= (u32Second % 10ul);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(u32TimeMode == RTC_CLOCK_12) {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    } else {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+  * @brief      Update RTC Alarm Date
+  *
+  * @param[in]  u32Year         The year calendar digit of RTC alarm setting.
+  * @param[in]  u32Month        The month calendar digit of RTC alarm setting.
+  * @param[in]  u32Day          The day calendar digit of RTC alarm setting.
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date setting to RTC.
+  */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+    uint32_t u32RegCALM;
+
+    u32RegCALM  = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+    u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+    u32RegCALM |= ((u32Month / 10ul) << 12);
+    u32RegCALM |= ((u32Month % 10ul) << 8);
+    u32RegCALM |= ((u32Day   / 10ul) << 4);
+    u32RegCALM |= (u32Day   % 10ul);
+
+    RTC_WaitAccessEnable();
+
+    /* Set RTC Alarm Date */
+    RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+  * @brief      Update RTC Alarm Time
+  *
+  * @param[in]  u32Hour         The hour time digit of RTC alarm setting.
+  * @param[in]  u32Minute       The minute time digit of RTC alarm setting.
+  * @param[in]  u32Second       The second time digit of RTC alarm setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm time setting to RTC.
+  */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTALM;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) {
+        u32Hour += 20ul;
+    }
+
+    u32RegTALM  = ((u32Hour   / 10ul) << 20);
+    u32RegTALM |= ((u32Hour   % 10ul) << 16);
+    u32RegTALM |= ((u32Minute / 10ul) << 12);
+    u32RegTALM |= ((u32Minute % 10ul) << 8);
+    u32RegTALM |= ((u32Second / 10ul) << 4);
+    u32RegTALM |= (u32Second % 10ul);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(u32TimeMode == RTC_CLOCK_12) {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    } else {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    /* Set RTC Alarm Time */
+    RTC_WaitAccessEnable();
+    RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+  * @brief      Get Day of the Week
+  *
+  * @param      None
+  *
+  * @retval     0   Sunday
+  * @retval     1   Monday
+  * @retval     2   Tuesday
+  * @retval     3   Wednesday
+  * @retval     4   Thursday
+  * @retval     5   Friday
+  * @retval     6   Saturday
+  *
+  * @details    This API is used to get day of the week of current RTC date.
+  */
+uint32_t RTC_GetDayOfWeek(void)
+{
+    return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+  * @brief      Set RTC Tick Period Time
+  *
+  * @param[in]  u32TickSelection    It is used to set the RTC tick period time for Periodic Time Tick request. \n
+  *                                 It consists of:
+  *                                     - \ref RTC_TICK_1_SEC     : Time tick is 1 second
+  *                                     - \ref RTC_TICK_1_2_SEC   : Time tick is 1/2 second
+  *                                     - \ref RTC_TICK_1_4_SEC   : Time tick is 1/4 second
+  *                                     - \ref RTC_TICK_1_8_SEC   : Time tick is 1/8 second
+  *                                     - \ref RTC_TICK_1_16_SEC  : Time tick is 1/16 second
+  *                                     - \ref RTC_TICK_1_32_SEC  : Time tick is 1/32 second
+  *                                     - \ref RTC_TICK_1_64_SEC  : Time tick is 1/64 second
+  *                                     - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
+  *
+  * @return     None
+  *
+  * @details    This API is used to set RTC tick period time for each tick interrupt.
+  */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+  * @brief      Enable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                     - \ref RTC_INTEN_ALMIEN_Msk   : Alarm interrupt
+  *                                     - \ref RTC_INTEN_TICKIEN_Msk  : Tick interrupt
+  *                                     - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the specify RTC interrupt function.
+  */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+    RTC_WaitAccessEnable();
+    RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+  * @brief      Disable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                     - \ref RTC_INTEN_ALMIEN_Msk   : Alarm interrupt
+  *                                     - \ref RTC_INTEN_TICKIEN_Msk  : Tick interrupt
+  *                                     - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the specify RTC interrupt function.
+  */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+    RTC_WaitAccessEnable();
+    RTC->INTEN  &= ~u32IntFlagMask;
+    RTC_WaitAccessEnable();
+    RTC->INTSTS = u32IntFlagMask;
+}
+
+/**
+  * @brief      Enable Spare Registers Access
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the spare registers 0~19 can be accessed.
+  */
+void RTC_EnableSpareAccess(void)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+  * @brief      Disable Spare Register
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the spare register 0~19 cannot be accessed.
+  */
+void RTC_DisableSpareRegister(void)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+  * @brief      Static Tamper Detect
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref RTC_TAMPER5_SELECT
+  *                                 - \ref RTC_TAMPER4_SELECT
+  *                                 - \ref RTC_TAMPER3_SELECT
+  *                                 - \ref RTC_TAMPER2_SELECT
+  *                                 - \ref RTC_TAMPER1_SELECT
+  *                                 - \ref RTC_TAMPER0_SELECT
+  *
+  * @param[in]  u32DetecLevel       Tamper pin detection level select. Possible options are
+  *                                 - \ref RTC_TAMPER_HIGH_LEVEL_DETECT
+  *                                 - \ref RTC_TAMPER_LOW_LEVEL_DETECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the tamper pin detect function with specify trigger condition.
+  */
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    RTC_WaitAccessEnable();
+    u32Reg = RTC->TAMPCTL;
+
+    u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
+                  (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) );
+
+    for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) {
+        if(u32TamperSelect & (0x1ul << i)) {
+            u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul));
+            u32Reg |= (u32TmpReg << (i*4ul));
+        }
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->TAMPCTL = u32Reg;
+
+}
+
+/**
+  * @brief      Static Tamper Disable
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref RTC_TAMPER5_SELECT
+  *                                 - \ref RTC_TAMPER4_SELECT
+  *                                 - \ref RTC_TAMPER3_SELECT
+  *                                 - \ref RTC_TAMPER2_SELECT
+  *                                 - \ref RTC_TAMPER1_SELECT
+  *                                 - \ref RTC_TAMPER0_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the static tamper pin detect.
+  */
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    RTC_WaitAccessEnable();
+    u32Reg = RTC->TAMPCTL;
+
+    u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
+
+    for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) {
+        if(u32TamperSelect & (0x1ul << i)) {
+            u32Reg &= ~(u32TmpReg << (i*4ul));
+        }
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Detect
+  *
+  * @param[in]  u32PairSel          Tamper pin detection enable. Possible options are
+  *                                 - \ref RTC_PAIR0_SELECT
+  *                                 - \ref RTC_PAIR1_SELECT
+  *                                 - \ref RTC_PAIR2_SELECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+  *
+  *  @param[in]  u32Pair1Source     Dynamic Pair 1 Input Source Select
+  *                                 0: Pair 1 source select tamper 2
+  *                                 1: Pair 1 source select tamper 0
+  *
+  *  @param[in]  u32Pair2Source     Dynamic Pair 2 Input Source Select
+  *                                 0: Pair 2 source select tamper 4
+  *                                 1: Pair 2 source select tamper 0
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the dynamic tamper.
+  */
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2Debounce, u32Tamper4Debounce;
+
+    RTC_WaitAccessEnable();
+    u32Reg = RTC->TAMPCTL;
+
+    u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk;
+    u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk;
+
+    u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |
+                RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);
+    u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
+    u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos);
+
+    if(u32DebounceEn) {
+        u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
+                     RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+    } else {
+        u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+    }
+
+    for(i = 0ul; i < MAX_PAIR_NUM; i++) {
+        if(u32PairSel & (0x1ul << i)) {
+            u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul));
+            u32Reg |= (u32TmpReg << (i*8ul));
+        }
+    }
+
+    if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT)) {
+        u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
+        u32Reg |= u32Tamper2Debounce;
+    }
+
+    if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT)) {
+        u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
+        u32Reg |= u32Tamper4Debounce;
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Disable
+  *
+  * @param[in]  u32PairSel          Tamper pin detection enable. Possible options are
+  *                                 - \ref RTC_PAIR0_SELECT
+  *                                 - \ref RTC_PAIR1_SELECT
+  *                                 - \ref RTC_PAIR2_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the dynamic tamper.
+  */
+void RTC_DynamicTamperDisable(uint32_t u32PairSel)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul;
+
+    RTC_WaitAccessEnable();
+    u32Reg = RTC->TAMPCTL;
+
+    if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT)) {
+        u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
+    }
+
+    if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT)) {
+        u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
+    }
+
+    u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+
+    for(i = 0ul; i < MAX_PAIR_NUM; i++) {
+        if(u32PairSel & (0x1ul << i)) {
+            u32Reg &= ~(u32TmpReg << ((i*8ul)));
+        }
+    }
+
+    u32Reg |= (u32Tamper2En | u32Tamper4En);
+
+    RTC_WaitAccessEnable();
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Config dynamic tamper
+  *
+  * @param[in]  u32ChangeRate       The dynamic tamper output change rate
+  *                                 - \ref RTC_2POW10_CLK
+  *                                 - \ref RTC_2POW11_CLK
+  *                                 - \ref RTC_2POW12_CLK
+  *                                 - \ref RTC_2POW13_CLK
+  *                                 - \ref RTC_2POW14_CLK
+  *                                 - \ref RTC_2POW15_CLK
+  *                                 - \ref RTC_2POW16_CLK
+  *                                 - \ref RTC_2POW17_CLK
+  *
+  * @param[in]  u32SeedReload       Reload new seed or not
+  *                                 0: not reload new seed
+  *                                 1: reload new seed
+  *
+  * @param[in]  u32RefPattern       Reference pattern
+  *                                 - \ref REF_RANDOM_PATTERN
+  *                                 - \ref REF_PREVIOUS_PATTERN
+  *                                 - \ref REF_SEED
+  *
+  * @param[in]  u32Seed             Seed Value (0x0 ~ 0xFFFFFFFF)
+  *
+  * @return     None
+  *
+  * @details    This API is used to config dynamic tamper setting.
+  */
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)
+{
+    uint32_t u32Reg;
+    RTC_WaitAccessEnable();
+    u32Reg = RTC->TAMPCTL;
+
+    u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk);
+
+    u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) |
+              ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos);
+
+    RTC_WaitAccessEnable();
+    RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */
+    RTC->TAMPCTL = u32Reg;
+}
+
+/*@}*/ /* end of group M480_RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_RTC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_rtc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+ * @file     rtc.h
+ * @version  V3.00
+ * @brief    M480 series RTC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __RTC_H__
+#define __RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup M480_RTC_EXPORTED_CONSTANTS RTC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Initial Keyword Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY            0xA5EB1357UL    /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
+#define RTC_WRITE_KEY           0x0000A965UL    /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Time Attribute Constant Definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12            0UL               /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
+#define RTC_CLOCK_24            1UL               /*!< RTC as 24-hour time scale \hideinitializer */
+#define RTC_AM                  1UL               /*!< RTC as AM indication \hideinitializer */
+#define RTC_PM                  2UL               /*!< RTC as PM indication \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Tick Period Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC          0x0UL           /*!< RTC time tick period is 1 second \hideinitializer */
+#define RTC_TICK_1_2_SEC        0x1UL           /*!< RTC time tick period is 1/2 second \hideinitializer */
+#define RTC_TICK_1_4_SEC        0x2UL           /*!< RTC time tick period is 1/4 second \hideinitializer */
+#define RTC_TICK_1_8_SEC        0x3UL           /*!< RTC time tick period is 1/8 second \hideinitializer */
+#define RTC_TICK_1_16_SEC       0x4UL           /*!< RTC time tick period is 1/16 second \hideinitializer */
+#define RTC_TICK_1_32_SEC       0x5UL           /*!< RTC time tick period is 1/32 second \hideinitializer */
+#define RTC_TICK_1_64_SEC       0x6UL           /*!< RTC time tick period is 1/64 second \hideinitializer */
+#define RTC_TICK_1_128_SEC      0x7UL           /*!< RTC time tick period is 1/128 second \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Day of Week Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY              0x0UL           /*!< Day of the Week is Sunday \hideinitializer */
+#define RTC_MONDAY              0x1UL           /*!< Day of the Week is Monday \hideinitializer */
+#define RTC_TUESDAY             0x2UL           /*!< Day of the Week is Tuesday \hideinitializer */
+#define RTC_WEDNESDAY           0x3UL           /*!< Day of the Week is Wednesday \hideinitializer */
+#define RTC_THURSDAY            0x4UL           /*!< Day of the Week is Thursday \hideinitializer */
+#define RTC_FRIDAY              0x5UL           /*!< Day of the Week is Friday \hideinitializer */
+#define RTC_SATURDAY            0x6UL           /*!< Day of the Week is Saturday \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Miscellaneous Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_WAIT_COUNT          0xFFFFFFFFUL      /*!< Initial Time-out Value \hideinitializer */
+#define RTC_YEAR2000            2000UL            /*!< RTC Reference for compute year data \hideinitializer */
+#define RTC_FCR_REFERENCE       32761UL           /*!< RTC Reference for frequency compensation \hideinitializer */
+
+
+#define RTC_TAMPER0_SELECT (0x1ul << 0)     /*!< Select Tamper 0 \hideinitializer */
+#define RTC_TAMPER1_SELECT (0x1ul << 1)     /*!< Select Tamper 1 \hideinitializer */
+#define RTC_TAMPER2_SELECT (0x1ul << 2)     /*!< Select Tamper 2 \hideinitializer */
+#define RTC_TAMPER3_SELECT (0x1ul << 3)     /*!< Select Tamper 3 \hideinitializer */
+#define RTC_TAMPER4_SELECT (0x1ul << 4)     /*!< Select Tamper 4 \hideinitializer */
+#define RTC_TAMPER5_SELECT (0x1ul << 5)     /*!< Select Tamper 5 \hideinitializer */
+#define MAX_TAMPER_PIN_NUM 6ul              /*!< Tamper Pin number \hideinitializer */
+
+#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul    /*!< Tamper pin detect voltage level is high \hideinitializer */
+#define RTC_TAMPER_LOW_LEVEL_DETECT  0ul    /*!< Tamper pin detect voltage level is low  \hideinitializer */
+
+#define RTC_TAMPER_DEBOUNCE_ENABLE   1ul    /*!< Enable RTC tamper pin de-bounce function \hideinitializer */
+#define RTC_TAMPER_DEBOUNCE_DISABLE  0ul    /*!< Disable RTC tamper pin de-bounce function \hideinitializer */
+
+#define RTC_PAIR0_SELECT (0x1ul << 0)       /*!< Select Pair 0 \hideinitializer */
+#define RTC_PAIR1_SELECT (0x1ul << 1)       /*!< Select Pair 1 \hideinitializer */
+#define RTC_PAIR2_SELECT (0x1ul << 2)       /*!< Select Pair 2 \hideinitializer */
+#define MAX_PAIR_NUM     3ul                /*!< Pair number \hideinitializer */
+
+#define RTC_2POW10_CLK  (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */
+#define RTC_2POW11_CLK  (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */
+#define RTC_2POW12_CLK  (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */
+#define RTC_2POW13_CLK  (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */
+#define RTC_2POW14_CLK  (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */
+#define RTC_2POW15_CLK  (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */
+#define RTC_2POW16_CLK  (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */
+#define RTC_2POW17_CLK  (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */
+
+#define REF_RANDOM_PATTERN    0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */
+#define REF_PREVIOUS_PATTERN  0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */
+#define REF_SEED              0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */
+
+/*@}*/ /* end of group M480_RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_RTC_EXPORTED_STRUCTS RTC Exported Structs
+  @{
+*/
+/**
+  * @details    RTC define Time Data Struct
+  */
+typedef struct {
+    uint32_t u32Year;           /*!< Year value */
+    uint32_t u32Month;          /*!< Month value */
+    uint32_t u32Day;            /*!< Day value */
+    uint32_t u32DayOfWeek;      /*!< Day of week value */
+    uint32_t u32Hour;           /*!< Hour value */
+    uint32_t u32Minute;         /*!< Minute value */
+    uint32_t u32Second;         /*!< Second value */
+    uint32_t u32TimeScale;      /*!< 12-Hour, 24-Hour */
+    uint32_t u32AmPm;           /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group M480_RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup M480_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Indicate is Leap Year or not
+  *
+  * @param      None
+  *
+  * @retval     0   This year is not a leap year
+  * @retval     1   This year is a leap year
+  *
+  * @details    According to current date, return this year is leap year or not.
+  * \hideinitializer
+  */
+#define RTC_IS_LEAP_YEAR()              (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
+
+/**
+  * @brief      Clear RTC Alarm Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC alarm interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_ALARM_INT_FLAG()      (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
+
+/**
+  * @brief      Clear RTC Tick Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC tick interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_TICK_INT_FLAG()       (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
+
+/**
+  * @brief      Clear RTC Tamper Interrupt Flag
+  *
+  * @param      u32TamperFlag   Tamper interrupt flag. It consists of:    \n
+  *                             - \ref RTC_INTSTS_TAMP0IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP1IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP2IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP3IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP4IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP5IF_Msk
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC snooper pin interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag)    (RTC->INTSTS = (u32TamperFlag))
+
+/**
+  * @brief      Get RTC Alarm Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC alarm interrupt did not occur
+  * @retval     1   RTC alarm interrupt occurred
+  *
+  * @details    This macro indicates RTC alarm interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_ALARM_INT_FLAG()        ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Time Tick Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC time tick interrupt did not occur
+  * @retval     1   RTC time tick interrupt occurred
+  *
+  * @details    This macro indicates RTC time tick interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_TICK_INT_FLAG()         ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Tamper Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC snooper pin interrupt did not occur
+  * @retval     1   RTC snooper pin interrupt occurred
+  *
+  * @details    This macro indicates RTC snooper pin interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_TAMPER_INT_FLAG()      ((RTC->INTSTS & (0x3F00))? 1:0)
+
+/**
+  * @brief      Get RTC TAMPER Interrupt Status
+  *
+  * @param      None
+  *
+  * @retval     RTC_INTSTS_TAMP0IF_Msk    Tamper 0 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP1IF_Msk    Tamper 1 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP2IF_Msk    Tamper 2 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP3IF_Msk    Tamper 3 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP4IF_Msk    Tamper 4 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP5IF_Msk    Tamper 5 interrupt flag is generated
+  *
+  * @details    This macro indicates RTC snooper pin interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_TAMPER_INT_STATUS()      ((RTC->INTSTS & (0x3F00)))
+
+/**
+  * @brief      Read Spare Register
+  *
+  * @param[in]  u32RegNum   The spare register number, 0~19.
+  *
+  * @return     Spare register content
+  *
+  * @details    Read the specify spare register content.
+  * @note       The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+  *             And its controlled by RTC Access Enable Register.
+  * \hideinitializer
+  */
+#define RTC_READ_SPARE_REGISTER(u32RegNum)                  (RTC->SPR[(u32RegNum)])
+
+/**
+  * @brief      Write Spare Register
+  *
+  * @param[in]  u32RegNum    The spare register number, 0~19.
+  * @param[in]  u32RegValue  The spare register value.
+  *
+  * @return     None
+  *
+  * @details    Write specify data to spare register.
+  * @note       This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+  *             And its controlled by RTC Access Enable Register(RTC_RWEN).
+  * \hideinitializer
+  */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue)    (RTC->SPR[(u32RegNum)] = (u32RegValue))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void RTC_WaitAccessEnable(void);
+
+/**
+  * @brief      Wait RTC Access Enable
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the maximum RTC read/write accessible time.
+  */
+static __INLINE void RTC_WaitAccessEnable(void)
+{
+    while((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk) {
+    }
+
+    /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
+    RTC->RWEN = RTC_WRITE_KEY;
+
+    /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
+    while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0) {
+    }
+}
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX10000);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
+void RTC_DynamicTamperDisable(uint32_t u32PairSel);
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
+
+/*@}*/ /* end of group M480_RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_RTC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RTC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,337 @@
+/**************************************************************************//**
+ * @file     sc.c
+ * @version  V3.00
+ * @brief    M480 Smartcard(SC) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M480.h"
+
+/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL};
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SC_Driver SC Driver
+  @{
+*/
+
+/** @addtogroup M480_SC_EXPORTED_FUNCTIONS SC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function indicates specified smartcard slot status
+  * @param[in] sc Base address of smartcard module
+  * @return Card insert status
+  * @retval TRUE Card insert
+  * @retval FALSE Card remove
+  */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+    uint32_t ret;
+    /* put conditions into two variable to remove IAR compilation warning */
+    uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
+    uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
+
+    if((sc == SC0) && (u32CardStateIgnore[0] == 1UL)) {
+        ret = (uint32_t)TRUE;
+    } else if((sc == SC1) && (u32CardStateIgnore[1] == 1UL)) {
+        ret = (uint32_t)TRUE;
+    } else if((sc == SC2) && (u32CardStateIgnore[2] == 1UL)) {
+        ret = (uint32_t)TRUE;
+    } else if(cond1 != cond2) {
+        ret = (uint32_t)FALSE;
+    } else {
+        ret = (uint32_t)TRUE;
+    }
+    return ret;
+}
+
+/**
+  * @brief This function reset both transmit and receive FIFO of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @return None
+  */
+void SC_ClearFIFO(SC_T *sc)
+{
+    while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {
+        ;
+    }
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
+}
+
+/**
+  * @brief This function disable specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @return None
+  */
+void SC_Close(SC_T *sc)
+{
+    sc->INTEN = 0UL;
+    while(sc->PINCTL & SC_PINCTL_SYNC_Msk) {
+        ;
+    }
+    sc->PINCTL = 0UL;
+    sc->ALTCTL = 0UL;
+    while(sc->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    sc->CTL = 0UL;
+}
+
+/**
+  * @brief This function initialized smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be
+  *                 -\ref SC_PIN_STATE_HIGH
+  *                 -\ref SC_PIN_STATE_LOW
+  *                 -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present
+  * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be
+  *                 -\ref SC_PIN_STATE_HIGH
+  *                 -\ref SC_PIN_STATE_LOW
+  * @return None
+  */
+void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
+{
+    uint32_t u32Reg = 0UL, u32Intf;
+
+    if(sc == SC0) {
+        u32Intf = 0UL;
+    } else if(sc == SC1) {
+        u32Intf = 1UL;
+    } else {
+        u32Intf = 2UL;
+    }
+
+    if(u32CD != SC_PIN_STATE_IGNORE) {
+        u32Reg = u32CD ? 0UL: SC_CTL_CDLV_Msk;
+        u32CardStateIgnore[u32Intf] = 0UL;
+    } else {
+        u32CardStateIgnore[u32Intf] = 1UL;
+    }
+    sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;
+    while(sc->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
+}
+
+/**
+  * @brief This function reset specified smartcard module to its default state for activate smartcard
+  * @param[in] sc Base address of smartcard module
+  * @return None
+  */
+void SC_ResetReader(SC_T *sc)
+{
+    uint32_t u32Intf;
+
+    if(sc == SC0) {
+        u32Intf = 0UL;
+    } else if(sc == SC1) {
+        u32Intf = 1UL;
+    } else {
+        u32Intf = 2UL;
+    }
+
+    /* Reset FIFO, enable auto de-activation while card removal */
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
+    /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */
+    while(sc->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    sc->CTL &= ~(SC_CTL_RXTRGLV_Msk |
+                 SC_CTL_CDDBSEL_Msk |
+                 SC_CTL_TXRTY_Msk |
+                 SC_CTL_TXRTYEN_Msk |
+                 SC_CTL_RXRTY_Msk |
+                 SC_CTL_RXRTYEN_Msk);
+    while(sc->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    /* Enable auto convention, and all three smartcard internal timers */
+    sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
+    /* Disable Rx timeout */
+    sc->RXTOUT = 0UL;
+    /* 372 clocks per ETU by default */
+    sc->ETUCTL= 371UL;
+
+
+    /* Enable necessary interrupt for smartcard operation */
+    if(u32CardStateIgnore[u32Intf]) {/* Do not enable card detect interrupt if card present state ignore */
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk);
+    } else {
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_CDIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk);
+    }
+    return;
+}
+
+/**
+  * @brief This function block guard time (BGT) of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32
+  * @return None
+  */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+    sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);
+}
+
+/**
+  * @brief This function character guard time (CGT) of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267
+  * @return None
+  */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+    u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL: 12UL;
+    sc->EGT = u32CGT;
+}
+
+/**
+  * @brief This function stop all smartcard timer of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @return None
+  * @note This function stop the timers within smartcard module, \b not timer module
+  */
+void SC_StopAllTimer(SC_T *sc)
+{
+    while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {
+        ;
+    }
+    sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
+}
+
+/**
+  * @brief This function configure and start a smartcard timer of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
+  * @param[in] u32Mode Timer operating mode, valid values are:
+  *             - \ref SC_TMR_MODE_0
+  *             - \ref SC_TMR_MODE_1
+  *             - \ref SC_TMR_MODE_2
+  *             - \ref SC_TMR_MODE_3
+  *             - \ref SC_TMR_MODE_4
+  *             - \ref SC_TMR_MODE_5
+  *             - \ref SC_TMR_MODE_6
+  *             - \ref SC_TMR_MODE_7
+  *             - \ref SC_TMR_MODE_8
+  *             - \ref SC_TMR_MODE_F
+  * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid  range are between 1~0x1000000ETUs.
+  *                        For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs
+  * @return None
+  * @note This function start the timer within smartcard module, \b not timer module
+  * @note Depend on the timer operating mode, timer may not start counting immediately
+  */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+    uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));
+    while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {
+        ;
+    }
+    if(u32TimerNum == 0UL) {
+        while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) {
+            ;
+        }
+        sc->TMRCTL0 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
+    } else if(u32TimerNum == 1UL) {
+        while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) {
+            ;
+        }
+        sc->TMRCTL1 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
+    } else {   /* timer 2 */
+        while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) {
+            ;
+        }
+        sc->TMRCTL2 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
+    }
+}
+
+/**
+  * @brief This function stop a smartcard timer of specified smartcard module
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
+  * @return None
+  * @note This function stop the timer within smartcard module, \b not timer module
+  */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+    while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {
+        ;
+    }
+    if(u32TimerNum == 0UL) {
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
+    } else if(u32TimerNum == 1UL) {
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
+    } else {    /* timer 2 */
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
+    }
+}
+
+/**
+  * @brief  This function gets smartcard clock frequency.
+  * @param[in] sc Base address of smartcard module
+  * @return Smartcard frequency in kHZ
+  */
+uint32_t SC_GetInterfaceClock(SC_T *sc)
+{
+    uint32_t u32ClkSrc, u32Num, u32Clk;
+
+    if(sc == SC0) {
+        u32Num = 0UL;
+    } else if(sc == SC1) {
+        u32Num = 1UL;
+    } else {
+        u32Num = 2UL;
+    }
+
+    u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+    /* Get smartcard module clock */
+    if(u32ClkSrc == 0UL) {
+        u32Clk = __HXT;
+    } else if(u32ClkSrc == 1UL) {
+        u32Clk = CLK_GetPLLClockFreq();
+    } else if(u32ClkSrc == 2UL) {
+        if(u32Num == 1UL) {
+            u32Clk = CLK_GetPCLK1Freq();
+        } else {
+            u32Clk = CLK_GetPCLK0Freq();
+        }
+    } else {
+        u32Clk = __HIRC;
+    }
+
+    u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL;
+    return u32Clk;
+}
+
+/*@}*/ /* end of group M480_SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,261 @@
+/**************************************************************************//**
+ * @file     sc.h
+ * @version  V1.00
+ * @brief    M480 Smartcard (SC) driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_H__
+#define __SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SC_Driver SC Driver
+  @{
+*/
+
+/** @addtogroup M480_SC_EXPORTED_CONSTANTS SC Exported Constants
+  @{
+*/
+#define SC_INTERFACE_NUM        3                /*!< Smartcard interface numbers \hideinitializer */
+#define SC_PIN_STATE_HIGH       1                /*!< Smartcard pin status high   \hideinitializer */
+#define SC_PIN_STATE_LOW        0                /*!< Smartcard pin status low    \hideinitializer */
+#define SC_PIN_STATE_IGNORE     0xFFFFFFFF       /*!< Ignore pin status           \hideinitializer */
+#define SC_CLK_ON               1                /*!< Smartcard clock on          \hideinitializer */
+#define SC_CLK_OFF              0                /*!< Smartcard clock off         \hideinitializer */
+
+#define SC_TMR_MODE_0                   (0ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 0, down count                                                      \hideinitializer */
+#define SC_TMR_MODE_1                   (1ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 1, down count, start after detect start bit                        \hideinitializer */
+#define SC_TMR_MODE_2                   (2ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 2, down count, start after receive start bit                       \hideinitializer */
+#define SC_TMR_MODE_3                   (3ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode  \hideinitializer */
+#define SC_TMR_MODE_4                   (4ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 4, down count with reload after timeout                            \hideinitializer */
+#define SC_TMR_MODE_5                   (5ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout  \hideinitializer */
+#define SC_TMR_MODE_6                   (6ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */
+#define SC_TMR_MODE_7                   (7ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 7, down count, start and reload after detect start bit             \hideinitializer */
+#define SC_TMR_MODE_8                   (8ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 8, up count                                                        \hideinitializer */
+#define SC_TMR_MODE_F                   (0xF << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 15, down count, reload after detect start bit                      \hideinitializer */
+
+
+/*@}*/ /* end of group M480_SC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_SC_EXPORTED_FUNCTIONS SC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This macro enable smartcard interrupt
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32Mask Interrupt mask to be enabled. A combination of
+  *             - \ref SC_INTEN_ACERRIEN_Msk
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_INITIEN_Msk
+  *             - \ref SC_INTEN_CDIEN_Msk
+  *             - \ref SC_INTEN_BGTIEN_Msk
+  *             - \ref SC_INTEN_TMR2IEN_Msk
+  *             - \ref SC_INTEN_TMR1IEN_Msk
+  *             - \ref SC_INTEN_TMR0IEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+  * @brief This macro disable smartcard interrupt
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32Mask Interrupt mask to be disabled. A combination of
+  *             - \ref SC_INTEN_ACERRIEN_Msk
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_INITIEN_Msk
+  *             - \ref SC_INTEN_CDIEN_Msk
+  *             - \ref SC_INTEN_BGTIEN_Msk
+  *             - \ref SC_INTEN_TMR2IEN_Msk
+  *             - \ref SC_INTEN_TMR1IEN_Msk
+  *             - \ref SC_INTEN_TMR0IEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief This macro set VCC pin state of smartcard interface
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+  * @return None
+  * \hideinitializer
+  */
+#define SC_SET_VCC_PIN(sc, u32State) \
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
+    }while(0)
+
+
+/**
+  * @brief This macro turns CLK output on or off
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
+  * @return None
+  * \hideinitializer
+  */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32OnOff)\
+                (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
+            else\
+                (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
+    }while(0)
+
+/**
+  * @brief This macro set I/O pin state of smartcard interface
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+  * @return None
+  * \hideinitializer
+  */
+#define SC_SET_IO_PIN(sc, u32State)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
+    }while(0)
+
+/**
+  * @brief This macro set RST pin state of smartcard interface
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+  * @return None
+  * \hideinitializer
+  */
+#define SC_SET_RST_PIN(sc, u32State)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
+    }while(0)
+
+/**
+  * @brief This macro read one byte from smartcard module receive FIFO
+  * @param[in] sc Base address of smartcard module
+  * @return One byte read from receive FIFO
+  * \hideinitializer
+  */
+#define SC_READ(sc) ((char)((sc)->DAT))
+
+/**
+  * @brief This macro write one byte to smartcard module transmit FIFO
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u8Data Data to write to transmit FIFO
+  * @return None
+  * \hideinitializer
+  */
+#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+  * @brief This macro set smartcard stop bit length
+  * @param[in] sc Base address of smartcard module
+  * @param[in] u32Len Stop bit length, ether 1 or 2.
+  * @return None
+  * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+  * \hideinitializer
+  */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count);
+__STATIC_INLINE void  SC_SetRxRetry(SC_T *sc, uint32_t u32Count);
+
+/**
+  * @brief  Enable/Disable Tx error retry, and set Tx error retry count
+  * @param[in]  sc Base address of smartcard module
+  * @param[in]  u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
+  * @return None
+  */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while((sc)->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    /* Retry count must set while enable bit disabled, so disable it first */
+    (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
+
+    if((u32Count) != 0UL) {
+        while((sc)->CTL & SC_CTL_SYNC_Msk) {
+            ;
+        }
+        (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
+    }
+}
+
+/**
+  * @brief  Enable/Disable Rx error retry, and set Rx error retry count
+  * @param[in]  sc Base address of smartcard module
+  * @param[in]  u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
+  * @return None
+  */
+__STATIC_INLINE void  SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while((sc)->CTL & SC_CTL_SYNC_Msk) {
+        ;
+    }
+    /* Retry count must set while enable bit disabled, so disable it first */
+    (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
+
+    if((u32Count) != 0UL) {
+        while((sc)->CTL & SC_CTL_SYNC_Msk) {
+            ;
+        }
+        (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
+    }
+
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+uint32_t SC_GetInterfaceClock(SC_T *sc);
+
+
+/*@}*/ /* end of group M480_SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SC_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SC_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_scuart.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,218 @@
+/**************************************************************************//**
+ * @file     scuart.c
+ * @brief    M480 Smartcard UART mode (SCUART) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+static uint32_t SCUART_GetClock(SC_T *sc);
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SCUART_Driver SCUART Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/**
+  * @brief The function is used to disable smartcard interface UART mode.
+  * @param sc The base address of smartcard module.
+  * @return None
+  */
+void SCUART_Close(SC_T* sc)
+{
+    sc->INTEN = 0UL;
+    sc->UARTCTL = 0UL;
+    sc->CTL = 0UL;
+
+}
+/** @cond HIDDEN_SYMBOLS */
+/**
+  * @brief This function returns module clock of specified SC interface
+  * @param[in] sc The base address of smartcard module.
+  * @return Module clock of specified SC interface
+  */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+    uint32_t u32ClkSrc, u32Num, u32Clk;
+
+    if(sc == SC0) {
+        u32Num = 0UL;
+    } else if(sc == SC1) {
+        u32Num = 1UL;
+    } else {
+        u32Num = 2UL;
+    }
+
+    u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+    /* Get smartcard module clock */
+    if(u32ClkSrc == 0UL) {
+        u32Clk = __HXT;
+    } else if(u32ClkSrc == 1UL) {
+        u32Clk = CLK_GetPLLClockFreq();
+    } else if(u32ClkSrc == 2UL) {
+        if(u32Num == 1UL) {
+            u32Clk = CLK_GetPCLK1Freq();
+        } else {
+            u32Clk = CLK_GetPCLK0Freq();
+        }
+    } else {
+        u32Clk = __HIRC;
+    }
+
+    u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL);
+
+
+    return u32Clk;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief This function use to enable smartcard module UART mode and set baudrate.
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] u32baudrate Target baudrate of smartcard module.
+  * @return Actual baudrate of smartcard mode
+  * @details This function configures character width to 8 bits, 1 stop bit, and no parity.
+  *          And can use \ref SCUART_SetLineConfig function to update these settings
+  *          The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+  *          by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+  *          register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+  *          (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+  *          4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+  */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
+{
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    /* Calculate divider for target baudrate */
+    u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL;
+
+    /* Enable smartcard interface and stop bit = 1 */
+    sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk;
+    /* Enable UART mode, disable parity and 8 bit per character */
+    sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk;
+    sc->ETUCTL = u32Div;
+
+    return(u32Clk / (u32Div + 1UL));
+}
+
+/**
+  * @brief The function is used to read Rx data from RX FIFO.
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] pu8RxBuf The buffer to store receive the data
+  * @param[in] u32ReadBytes Target number of characters to receive
+  * @return Actual character number reads to buffer
+  * @note This function does not block and return immediately if there's no data available
+  */
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) {
+        if(SCUART_GET_RX_EMPTY(sc)) { /* no data available */
+            break;
+        }
+        pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc);    /* get data from FIFO */
+    }
+
+    return u32Count;
+}
+
+/**
+  * @brief This function use to configure smartcard UART mode line setting.
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+  * @param[in] u32DataWidth The data length, could be
+  *                 - \ref SCUART_CHAR_LEN_5
+  *                 - \ref SCUART_CHAR_LEN_6
+  *                 - \ref SCUART_CHAR_LEN_7
+  *                 - \ref SCUART_CHAR_LEN_8
+  * @param[in] u32Parity The parity setting, could be
+  *                 - \ref SCUART_PARITY_NONE
+  *                 - \ref SCUART_PARITY_ODD
+  *                 - \ref SCUART_PARITY_EVEN
+  * @param[in] u32StopBits The stop bit length, could be
+  *                 - \ref SCUART_STOP_BIT_1
+  *                 - \ref SCUART_STOP_BIT_2
+  * @return Actual baudrate of smartcard
+  * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+  *          by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+  *          register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+  *          (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+  *          4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+  */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t  u32StopBits)
+{
+
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    if(u32Baudrate == 0UL) {  /* keep original baudrate setting */
+        u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
+    } else {
+        /* Calculate divider for target baudrate */
+        u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL)/ u32Baudrate - 1UL;
+        sc->ETUCTL = u32Div;
+    }
+    /* Set stop bit */
+    sc->CTL = u32StopBits | SC_CTL_SCEN_Msk;
+    /* Set character width and parity */
+    sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk;
+
+    return(u32Clk / (u32Div + 1UL));
+}
+
+/**
+  * @brief This function use to set receive timeout count.
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+  *                   set this value to 0 will disable timeout counter
+  * @return None
+  * @details The time-out counter resets and starts counting whenever the RX buffer received a
+  *          new data word. Once the counter decrease to 1 and no new data is received or CPU
+  *          does not read any data from FIFO, a receiver time-out interrupt will be generated.
+  */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+    sc->RXTOUT= u32TOC;
+}
+
+
+/**
+  * @brief This function is to write data into transmit FIFO to send data out.
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+  * @param[in] u32WriteBytes Number of data to send.
+  * @return None
+  * @note This function blocks until all data write into FIFO
+  */
+void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) {
+        /* Wait 'til FIFO not full */
+        while(SCUART_GET_TX_FULL(sc)) {
+            ;
+        }
+        /* Write 1 byte to FIFO */
+        sc->DAT = pu8TxBuf[u32Count];
+    }
+}
+
+
+/*@}*/ /* end of group M480_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SCUART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_scuart.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     scuart.h
+ * @version  V1.00
+ * @brief    M480 Smartcard UART mode (SCUART) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SCUART_H__
+#define __SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SCUART_Driver SCUART Driver
+  @{
+*/
+
+/** @addtogroup M480_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+  @{
+*/
+#define SCUART_CHAR_LEN_5     (0x3ul << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 5 bits \hideinitializer */
+#define SCUART_CHAR_LEN_6     (0x2ul << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 6 bits \hideinitializer */
+#define SCUART_CHAR_LEN_7     (0x1ul << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 7 bits \hideinitializer */
+#define SCUART_CHAR_LEN_8     (0UL)                             /*!< Set SCUART word length to 8 bits \hideinitializer */
+
+#define SCUART_PARITY_NONE    (SC_UARTCTL_PBOFF_Msk)            /*!< Set SCUART transfer with no parity   \hideinitializer */
+#define SCUART_PARITY_ODD     (SC_UARTCTL_OPE_Msk)              /*!< Set SCUART transfer with odd parity  \hideinitializer */
+#define SCUART_PARITY_EVEN    (0UL)                             /*!< Set SCUART transfer with even parity \hideinitializer */
+
+#define SCUART_STOP_BIT_1     (SC_CTL_NSB_Msk)                  /*!< Set SCUART transfer with one stop bit  \hideinitializer */
+#define SCUART_STOP_BIT_2     (0UL)                             /*!< Set SCUART transfer with two stop bits \hideinitializer */
+
+
+/*@}*/ /* end of group M480_SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/* TX Macros */
+/**
+  * @brief Write Data to Tx data register
+  * @param[in] sc The base address of smartcard module.
+  * @param[in] u8Data Data byte to transmit
+  * @return None
+  * \hideinitializer
+  */
+#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+  * @brief Get TX FIFO empty flag status from register
+  * @param[in] sc The base address of smartcard module
+  * @return Transmit FIFO empty status
+  * @retval 0 Transmit FIFO is not empty
+  * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
+
+/**
+  * @brief Get TX FIFO full flag status from register
+  * @param[in] sc The base address of smartcard module
+  * @return Transmit FIFO full status
+  * @retval 0 Transmit FIFO is not full
+  * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
+
+/**
+  * @brief Wait specified smartcard port transmission complete
+  * @param[in] sc The base address of smartcard module
+  * @return None
+  * @note This Macro blocks until transmit complete.
+  * \hideinitializer
+  */
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
+
+/**
+  * @brief Check specified smartcard port transmit FIFO is full or not
+  * @param[in] sc The base address of smartcard module
+  * @return Transmit FIFO full status
+  * @retval 0 Transmit FIFO is not full
+  * @retval 1 Transmit FIFO is full
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
+
+/**
+  * @brief Check specified smartcard port transmission is over
+  * @param[in] sc The base address of smartcard module
+  * @return Transmit complete status
+  * @retval 0 Transmit is not complete
+  * @retval 1 Transmit complete
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
+
+/**
+  * @brief      Check specified Smartcard port Transmission Status
+  * @param[in]  sc      The pointer of smartcard module.
+  * @retval     0       Transmit is completed
+  * @retval     1       Transmit is active
+  * @details    TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_ACTIVE(sc)     (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
+
+/* RX Macros */
+
+/**
+  * @brief Read Rx data register
+  * @param[in] sc The base address of smartcard module
+  * @return The oldest data byte in RX FIFO
+  * \hideinitializer
+  */
+#define SCUART_READ(sc) ((sc)->DAT)
+
+/**
+  * @brief Get RX FIFO empty flag status from register
+  * @param[in] sc The base address of smartcard module
+  * @return Receive FIFO empty status
+  * @retval 0 Receive FIFO is not empty
+  * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
+
+
+/**
+  * @brief Get RX FIFO full flag status from register
+  * @param[in] sc The base address of smartcard module
+  * @return Receive FIFO full status
+  * @retval 0 Receive FIFO is not full
+  * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
+
+/**
+  * @brief Check if receive data number in FIFO reach FIFO trigger level or not
+  * @param[in] sc The base address of smartcard module
+  * @return Receive FIFO data status
+  * @retval 0 The number of bytes in receive FIFO is less than trigger level
+  * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
+  * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
+
+/**
+  * @brief Check specified smartcard port receive FIFO is full or not
+  * @param[in] sc The base address of smartcard module
+  * @return Receive FIFO full status
+  * @retval 0 Receive FIFO is not full
+  * @retval 1 Receive FIFO is full
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
+
+/* Interrupt Macros */
+
+/**
+  * @brief Enable specified interrupts
+  * @param[in] sc The base address of smartcard module
+  * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return    None
+  * \hideinitializer
+  */
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+  * @brief Disable specified interrupts
+  * @param[in] sc The base address of smartcard module
+  * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
+  *             - \ref SC_INTEN_RXTOIEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return    None
+  * \hideinitializer
+  */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief Get specified interrupt flag/status
+  * @param[in] sc The base address of smartcard module
+  * @param[in] u32Type Interrupt flag/status to check, could be one of following value
+  *             - \ref SC_INTSTS_RXTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  *             - \ref SC_INTSTS_RDAIF_Msk
+  * @return The status of specified interrupt
+  * @retval 0 Specified interrupt does not happened
+  * @retval 1 Specified interrupt happened
+  * \hideinitializer
+  */
+#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
+
+/**
+  * @brief Clear specified interrupt flag/status
+  * @param[in] sc The base address of smartcard module
+  * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
+  *             - \ref SC_INTSTS_RXTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
+
+/**
+  * @brief Get receive error flag/status
+  * @param[in] sc The base address of smartcard module
+  * @return Current receive error status, could one of following errors:
+  * @retval SC_STATUS_PEF_Msk Parity error
+  * @retval SC_STATUS_FEF_Msk Frame error
+  * @retval SC_STATUS_BEF_Msk Break error
+  * \hideinitializer
+  */
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
+
+/**
+  * @brief Clear specified receive error flag/status
+  * @param[in] sc The base address of smartcard module
+  * @param[in] u32Mask Receive error flag/status to clear, combination following values
+  *             - \ref SC_STATUS_PEF_Msk
+  *             - \ref SC_STATUS_FEF_Msk
+  *             - \ref SC_STATUS_BEF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t  u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+/*@}*/ /* end of group M480_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SCUART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SCUART_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sdh.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1026 @@
+/**************************************************************************//**
+ * @file     SDH.c
+ * @version  V1.00
+ * $Revision: 13 $
+ * $Date: 16/07/01 9:02a $
+ * @brief    M480 SDH driver source file
+ *
+ * @note
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SDH_Driver SDH Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+#define SDH_BLOCK_SIZE   512ul
+
+/** @cond HIDDEN_SYMBOLS */
+
+/* global variables */
+/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */
+/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */
+/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */
+uint32_t _SDH_uR3_CMD = 0ul;
+uint32_t _SDH_uR7_CMD = 0ul;
+uint8_t volatile _SDH_SDDataReady = FALSE;
+
+uint32_t _SDH_ReferenceClock;
+
+#if defined (__CC_ARM)
+__align(4) uint8_t _SDH_ucSDHCBuffer[512];
+#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
+#pragma data_alignment = 4
+uint8_t _SDH_ucSDHCBuffer[512];
+#elif defined ( __GNUC__ )
+uint8_t _SDH_ucSDHCBuffer[512] __attribute__((aligned (4)));
+#endif
+
+int SDH_ok = 0;
+
+SDH_INFO_T SD0, SD1;
+
+void SDH_CheckRB(SDH_T *sdh)
+{
+    while(1) {
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+        }
+        if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk) {
+            break;
+        }
+    }
+}
+
+
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+    volatile uint32_t buf, val = 0ul;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk);
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) {
+        if (pSD->IsCardInsert == 0ul) {
+            val = SDH_NO_SD_CARD;
+        }
+    }
+    return val;
+}
+
+
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount)
+{
+    volatile uint32_t buf;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
+    sdh->CTL = buf;
+
+    if (ntickCount > 0ul) {
+        while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) {
+            if(ntickCount-- == 0ul) {
+                sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */
+                return 2ul;
+            }
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    } else {
+        while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) {
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    }
+
+    if (_SDH_uR7_CMD) {
+        uint32_t tmp0 = 0ul , tmp1= 0ul;
+        tmp1 = sdh->RESP1 & 0xfful;
+        tmp0 = sdh->RESP0 & 0xful;
+        if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul)) {
+            _SDH_uR7_CMD = 0ul;
+            return SDH_CMD8_ERROR;
+        }
+    }
+
+    if (!_SDH_uR3_CMD) {
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) {   /* check CRC7 */
+            return Successful;
+        } else {
+            return SDH_CRC7_ERROR;
+        }
+    } else {
+        /* ignore CRC error for R3 case */
+        _SDH_uR3_CMD = 0ul;
+        sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+        return Successful;
+    }
+}
+
+
+uint32_t SDH_Swap32(uint32_t val)
+{
+    uint32_t buf;
+
+    buf = val;
+    val <<= 24;
+    val |= (buf<<8) & 0xff0000ul;
+    val |= (buf>>8) & 0xff00ul;
+    val |= (buf>>24)& 0xfful;
+    return val;
+}
+
+/* Get 16 bytes CID or CSD */
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[])
+{
+    uint32_t i, buf;
+    uint32_t tmpBuf[5];
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk) {
+        if (pSD->IsCardInsert == FALSE) {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) {
+        for (i=0ul; i<5ul; i++) {
+            tmpBuf[i] = SDH_Swap32(sdh->FB[i]);
+        }
+        for (i=0ul; i<4ul; i++) {
+            puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24);
+        }
+    } else {
+        return SDH_CRC7_ERROR;
+    }
+    return Successful;
+}
+
+
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg)
+{
+    volatile uint32_t buf;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    sdh->CMDARG = uArg;
+    buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|
+          (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+
+    sdh->CTL = buf;
+
+    while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) {
+        if (pSD->IsCardInsert == FALSE) {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk) {
+        if (pSD->IsCardInsert == FALSE) {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) {
+        /* check CRC7 */
+        return SDH_CRC7_ERROR;
+    }
+
+    if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) {
+        /* check CRC16 */
+        return SDH_CRC16_ERROR;
+    }
+    return 0ul;
+}
+
+/* there are 8 bits for divider0, maximum is 256 */
+#define SDH_CLK_DIV0_MAX     256ul
+
+void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz)
+{
+    uint32_t rate, div1;
+    static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul;
+
+    SYS_UnlockReg();
+
+    /* initial state, clock source use HIRC */
+    if (sd_clock_khz <= 400ul) {
+        u32SD_PwrCtl = CLK->PWRCTL;
+        if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul) {
+            CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+        }
+
+        if (sdh == SDH0) {
+            u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk);
+            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC;
+        } else {
+            u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk);
+            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC;
+        }
+        _SDH_ReferenceClock = (__HIRC / 1000ul);
+    }
+    /* transfer state, clock source use sys_init() */
+    else {
+        CLK->PWRCTL = u32SD_PwrCtl;
+        if (sdh == SDH0) {
+            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc;
+            if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) {
+                _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) {
+                _SDH_ReferenceClock = (__HIRC / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) {
+                _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) {
+                _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul);
+            }
+        } else {
+            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc;
+            if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT) {
+                _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC) {
+                _SDH_ReferenceClock = (__HIRC / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL) {
+                _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul);
+            } else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK) {
+                _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul);
+            }
+        }
+
+        if(sd_clock_khz >= 50000ul) {
+            sd_clock_khz = 50000ul;
+        }
+    }
+    rate = _SDH_ReferenceClock / sd_clock_khz;
+
+    /* choose slower clock if system clock cannot divisible by wanted clock */
+    if ((_SDH_ReferenceClock % sd_clock_khz) != 0ul) {
+        rate++;
+    }
+
+    if(rate >= SDH_CLK_DIV0_MAX) {
+        rate = SDH_CLK_DIV0_MAX;
+    }
+
+    /*--- calculate the second divider CLKDIV0[SDHOST_N]*/
+    div1 = (rate - 1ul) & 0xFFul;
+
+    /*--- setup register */
+    if (sdh == SDH0) {
+        CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk;
+        CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos);
+    } else {
+        CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk;
+        CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos);
+    }
+    return;
+}
+
+uint32_t SDH_CardDetection(SDH_T *sdh)
+{
+    uint32_t i, val = TRUE;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+
+    if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) { /* Card detect pin from GPIO */
+        if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) { /* Card remove */
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            val = FALSE;
+        } else {
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        }
+    } else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk) {
+        sdh->CTL |= SDH_CTL_CLKKEEP_Msk;
+        for(i= 0ul; i < 5000ul; i++) {
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) { /* Card insert */
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        } else {
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            val = FALSE;
+        }
+
+        sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk;
+    }
+
+    return val;
+}
+
+uint32_t SDH_Init(SDH_T *sdh)
+{
+    uint32_t volatile i, status;
+    unsigned int resp;
+    uint32_t CIDBuffer[4];
+    uint32_t volatile u32CmdTimeOut;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    /* set the clock to 300KHz */
+    SDH_Set_clock(sdh, 300ul);
+
+    /* power ON 74 clock */
+    sdh->CTL |= SDH_CTL_CLK74OEN_Msk;
+
+    while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) {
+        if (pSD->IsCardInsert == FALSE) {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    SDH_SDCommand(sdh, 0ul, 0ul);        /* reset all cards */
+    for (i=0x1000ul; i>0ul; i--) {
+    }
+
+    /* initial SDHC */
+    _SDH_uR7_CMD = 1ul;
+    u32CmdTimeOut = 0xFFFFFul;
+
+    i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut);
+    if (i == Successful) {
+        /* SD 2.0 */
+        SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+        _SDH_uR3_CMD = 1ul;
+        SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */
+        resp = sdh->RESP0;
+
+        while ((resp & 0x00800000ul) != 0x00800000ul) {      /* check if card is ready */
+            SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+            _SDH_uR3_CMD = 1ul;
+            SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+            resp = sdh->RESP0;
+        }
+        if ((resp & 0x00400000ul) == 0x00400000ul) {
+            pSD->CardType = SDH_TYPE_SD_HIGH;
+        } else {
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        }
+    } else {
+        /* SD 1.1 */
+        SDH_SDCommand(sdh, 0ul, 0ul);        /* reset all cards */
+        for (i=0x100ul; i>0ul; i--) {
+        }
+
+        i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+        if (i == 2ul) {   /* MMC memory */
+
+            SDH_SDCommand(sdh, 0ul, 0ul);        /* reset */
+            for (i=0x100ul; i>0ul; i--) {
+            }
+
+            _SDH_uR3_CMD = 1ul;
+
+            if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) {  /* eMMC memory */
+                resp = sdh->RESP0;
+                while ((resp & 0x00800000ul) != 0x00800000ul) {
+                    /* check if card is ready */
+                    _SDH_uR3_CMD = 1ul;
+
+                    SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut);      /* high voltage */
+                    resp = sdh->RESP0;
+                }
+
+                if ((resp & 0x00400000ul) == 0x00400000ul) {
+                    pSD->CardType = SDH_TYPE_EMMC;
+                } else {
+                    pSD->CardType = SDH_TYPE_MMC;
+                }
+            } else {
+                pSD->CardType = SDH_TYPE_UNKNOWN;
+                return SDH_ERR_DEVICE;
+            }
+        } else if (i == 0ul) { /* SD Memory */
+            _SDH_uR3_CMD = 1ul;
+            SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+            resp = sdh->RESP0;
+            while ((resp & 0x00800000ul) != 0x00800000ul) {      /* check if card is ready */
+                SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut);
+                _SDH_uR3_CMD = 1ul;
+                SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */
+                resp = sdh->RESP0;
+            }
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        } else {
+            pSD->CardType = SDH_TYPE_UNKNOWN;
+            return SDH_INIT_ERROR;
+        }
+    }
+
+    if (pSD->CardType != SDH_TYPE_UNKNOWN) {
+        SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer);
+        if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) {
+            if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) {   /* set RCA */
+                return status;
+            }
+            pSD->RCA = 0x10000ul;
+        } else {
+            if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) {     /* get RCA */
+                return status;
+            } else {
+                pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000;
+            }
+        }
+    }
+    return Successful;
+}
+
+
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)
+{
+    uint32_t volatile status=0ul;
+    uint16_t current_comsumption, busy_status0;
+
+    sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;
+    sdh->BLEN = 63ul;
+
+    if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful) {
+        return Fail;
+    }
+
+    current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8;
+    current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];
+    if (!current_comsumption) {
+        return Fail;
+    }
+
+    busy_status0 = (uint16_t)_SDH_ucSDHCBuffer[28] << 8;
+    busy_status0 |= (uint16_t)_SDH_ucSDHCBuffer[29];
+
+    if (!busy_status0) { /* function ready */
+        sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;
+        sdh->BLEN = 63ul;    /* 512 bit */
+
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful) {
+            return Fail;
+        }
+
+        /* function change timing: 8 clocks */
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+        }
+
+        current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8;
+        current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];
+        if (!current_comsumption) {
+            return Fail;
+        }
+
+        return Successful;
+    } else {
+        return Fail;
+    }
+}
+
+
+uint32_t SDH_SelectCardType(SDH_T *sdh)
+{
+    uint32_t volatile status=0ul;
+    uint32_t param;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) {
+        return status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* if SD card set 4bit */
+    if (pSD->CardType == SDH_TYPE_SD_HIGH) {
+        sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;
+        sdh->BLEN = 0x07ul;  /* 64 bit */
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) {
+            return status;
+        }
+
+        if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0x2ul) {
+//        if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0xful) {
+            status = SDH_SwitchToHighSpeed(sdh, pSD);
+            if (status == Successful) {
+                /* divider */
+                SDH_Set_clock(sdh, SDHC_FREQ);
+            }
+        }
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) { /* set bus width */
+            return status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    } else if (pSD->CardType == SDH_TYPE_SD_LOW) {
+        sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer;
+        sdh->BLEN = 0x07ul;
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) {
+            return status;
+        }
+        if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) {
+            return status;
+        }
+
+        /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */
+        if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) {
+            return status;
+        }
+
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) {
+            return status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    } else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC)) {
+
+        if(pSD->CardType == SDH_TYPE_MMC) {
+            sdh->CTL &= ~SDH_CTL_DBW_Msk;
+        }
+
+        /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */
+        /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */
+        param = (3ul << 24) | (183ul << 16) | (1ul << 8);
+        if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful) {
+            return status;
+        }
+        SDH_CheckRB(sdh);
+
+        sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
+
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful) {
+        return status;
+    }
+    sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+    }
+
+    sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;
+
+    return Successful;
+}
+
+void SDH_Get_SD_info(SDH_T *sdh)
+{
+    unsigned int R_LEN, C_Size, MULT, size;
+    uint32_t Buffer[4];
+    unsigned char *ptr;
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer);
+
+    if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) {
+        /* for MMC/eMMC card */
+        if ((Buffer[0] & 0xc0000000) == 0xc0000000) {
+            /* CSD_STRUCTURE [127:126] is 3 */
+            /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */
+            SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul);
+
+            ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer );
+            sdh->DMASA = (uint32_t)ptr;
+            sdh->BLEN = 511ul;  /* read 512 bytes for EXT_CSD */
+
+            if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful) {
+                SDH_SDCommand(sdh, 7ul, 0ul);
+                sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+                while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+                }
+
+                pSD->totalSectorN = _SDH_ucSDHCBuffer[212];
+                pSD->diskSize = pSD->totalSectorN / 2ul;
+            }
+        } else {
+            /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */
+            R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+            C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+            MULT = (Buffer[2] & 0x00038000ul) >> 15;
+            size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<<R_LEN);
+
+            pSD->diskSize = size / 1024ul;
+            pSD->totalSectorN = size / 512ul;
+        }
+    } else {
+        if ((Buffer[0] & 0xc0000000) != 0x0ul) {
+            C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16);
+            size = (C_Size+1ul) * 512ul;    /* Kbytes */
+
+            pSD->diskSize = size;
+            pSD->totalSectorN = size << 1;
+        } else {
+            R_LEN = (Buffer[1] & 0x000f0000ul) >> 16;
+            C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30);
+            MULT = (Buffer[2] & 0x00038000ul) >> 15;
+            size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<<R_LEN);
+
+            pSD->diskSize = size / 1024ul;
+            pSD->totalSectorN = size / 512ul;
+        }
+    }
+    pSD->sectorSize = (int)512;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/**
+ *  @brief  This function use to reset SD function and select card detection source and pin.
+ *
+ *  @param[in]  sdh    Select SDH0 or SDH1.
+ *  @param[in]  u32CardDetSrc   Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
+ *
+ *  @return None
+ */
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc)
+{
+    sdh->DMACTL = SDH_DMACTL_DMARST_Msk;
+    while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) {
+    }
+
+    sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;
+
+    sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk;
+    while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) {
+    }
+
+    if (sdh == SDH0) {
+        NVIC_EnableIRQ(SDH0_IRQn);
+        memset(&SD0, 0, sizeof(SDH_INFO_T));
+    } else if (sdh == SDH1) {
+        NVIC_EnableIRQ(SDH1_IRQn);
+        memset(&SD1, 0, sizeof(SDH_INFO_T));
+    } else {
+    }
+
+    sdh->GCTL = SDH_GCTL_SDEN_Msk;
+
+    if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3) {
+        sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk;
+    } else {
+        sdh->INTEN |= SDH_INTEN_CDSRC_Msk;
+    }
+    sdh->INTEN |= SDH_INTEN_CDIEN_Msk;
+
+    sdh->CTL |= SDH_CTL_CTLRST_Msk;
+    while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) {
+    }
+}
+
+/**
+ *  @brief  This function use to initial SD card.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return None
+ *
+ *  @details This function is used to initial SD card.
+ *           SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.
+ *           And then switch back to the user's setting.
+ */
+uint32_t SDH_Probe(SDH_T *sdh)
+{
+    uint32_t val;
+
+    sdh->GINTEN = 0ul;
+    sdh->CTL &= ~SDH_CTL_SDNWR_Msk;
+    sdh->CTL |=  0x09ul << SDH_CTL_SDNWR_Pos;   /* set SDNWR = 9 */
+    sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;
+    sdh->CTL |=  0x01ul << SDH_CTL_BLKCNT_Pos;  /* set BLKCNT = 1 */
+    sdh->CTL &= ~SDH_CTL_DBW_Msk;               /* SD 1-bit data bus */
+
+    if(!(SDH_CardDetection(sdh))) {
+        return SDH_NO_SD_CARD;
+    }
+
+    if ((val = SDH_Init(sdh)) != 0ul) {
+        return val;
+    }
+
+    /* divider */
+    if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC)) {
+        SDH_Set_clock(sdh, MMC_FREQ);
+    } else {
+        SDH_Set_clock(sdh, SD_FREQ);
+    }
+    SDH_Get_SD_info(sdh);
+
+    if ((val = SDH_SelectCardType(sdh)) != 0ul) {
+        return val;
+    }
+
+    SDH_ok = 1;
+    return 0ul;
+}
+
+/**
+ *  @brief  This function use to read data from SD card.
+ *
+ *  @param[in]     sdh           Select SDH0 or SDH1.
+ *  @param[out]    pu8BufAddr    The buffer to receive the data from SD card.
+ *  @param[in]     u32StartSec   The start read sector address.
+ *  @param[in]     u32SecCount   The the read sector number of data
+ *
+ *  @return None
+ */
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile bIsSendCmd = FALSE;
+    uint32_t volatile reg;
+    uint32_t volatile i, loop, status;
+    uint32_t blksize = SDH_BLOCK_SIZE;
+
+    SDH_INFO_T *pSD;
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    if (u32SecCount == 0ul) {
+        return SDH_SELECT_ERROR;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) {
+        return status;
+    }
+    SDH_CheckRB(sdh);
+
+    sdh->BLEN = blksize - 1ul;       /* the actual byte count is equal to (SDBLEN+1) */
+
+    if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) ) {
+        sdh->CMDARG = u32StartSec;
+    } else {
+        sdh->CMDARG = u32StartSec * blksize;
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+
+    loop = u32SecCount / 255ul;
+    for (i=0ul; i<loop; i++) {
+        _SDH_SDDataReady = (uint8_t)FALSE;
+        reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;
+        reg = reg | 0xff0000ul;   /* set BLK_CNT to 255 */
+        if (bIsSendCmd == FALSE) {
+            sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            bIsSendCmd = TRUE;
+        } else {
+            sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while(!_SDH_SDDataReady) {
+            if(_SDH_SDDataReady) {
+                break;
+            }
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) {    /* check CRC7 */
+            return SDH_CRC7_ERROR;
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) {   /* check CRC16 */
+            return SDH_CRC16_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255ul;
+    if (loop != 0ul) {
+        _SDH_SDDataReady = (uint8_t)FALSE;
+        reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);
+        reg = reg & (~SDH_CTL_BLKCNT_Msk);
+        reg |= (loop << 16);    /* setup SDCR_BLKCNT */
+
+        if (bIsSendCmd == FALSE) {
+            sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            bIsSendCmd = TRUE;
+        } else {
+            sdh->CTL = reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while(!_SDH_SDDataReady) {
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) {    /* check CRC7 */
+            return SDH_CRC7_ERROR;
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) {   /* check CRC16 */
+            return SDH_CRC16_ERROR;
+        }
+    }
+
+    if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) {    /* stop command */
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+    }
+
+    return Successful;
+}
+
+
+/**
+ *  @brief  This function use to write data to SD card.
+ *
+ *  @param[in]    sdh           Select SDH0 or SDH1.
+ *  @param[in]    pu8BufAddr    The buffer to send the data to SD card.
+ *  @param[in]    u32StartSec   The start write sector address.
+ *  @param[in]    u32SecCount   The the write sector number of data.
+ *
+ *  @return   \ref SDH_SELECT_ERROR : u32SecCount is zero. \n
+ *            \ref SDH_NO_SD_CARD : SD card be removed. \n
+ *            \ref SDH_CRC_ERROR : CRC error happen. \n
+ *            \ref SDH_CRC7_ERROR : CRC7 error happen. \n
+ *            \ref Successful : Write data to SD card success.
+ */
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile bIsSendCmd = FALSE;
+    uint32_t volatile reg;
+    uint32_t volatile i, loop, status;
+
+    SDH_INFO_T *pSD;
+
+    if (sdh == SDH0) {
+        pSD = &SD0;
+    } else {
+        pSD = &SD1;
+    }
+
+    if (u32SecCount == 0ul) {
+        return SDH_SELECT_ERROR;
+    }
+
+    if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) {
+        return status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */
+    sdh->BLEN = SDH_BLOCK_SIZE - 1ul;
+
+    if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) {
+        sdh->CMDARG = u32StartSec;
+    } else {
+        sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE;  /* set start address for SD CMD */
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+    loop = u32SecCount / 255ul;   /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */
+    for (i=0ul; i<loop; i++) {
+        _SDH_SDDataReady = (uint8_t)FALSE;
+        reg = sdh->CTL & 0xff00c080;
+        reg = reg | 0xff0000ul;   /* set BLK_CNT to 0xFF=255 */
+        if (!bIsSendCmd) {
+            sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            bIsSendCmd = TRUE;
+        } else {
+            sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while(!_SDH_SDDataReady) {
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+    }
+
+    loop = u32SecCount % 255ul;
+    if (loop != 0ul) {
+        _SDH_SDDataReady = (uint8_t)FALSE;
+        reg = (sdh->CTL & 0xff00c080) | (loop << 16);
+        if (!bIsSendCmd) {
+            sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            bIsSendCmd = TRUE;
+        } else {
+            sdh->CTL = reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while(!_SDH_SDDataReady) {
+            if (pSD->IsCardInsert == FALSE) {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+    }
+    sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+
+    if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) {    /* stop command */
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7ul, 0ul);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) {
+    }
+
+    return Successful;
+}
+
+/*@}*/ /* end of group M480_SDH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SDH_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sdh.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,197 @@
+/**************************************************************************//**
+ * @file     sdh.h
+ * @version  V1.00
+ * @brief    M480 SDH driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include <stdio.h>
+
+#ifndef __SDH_H__
+#define __SDH_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SDH_Driver SDH Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SDH_EXPORTED_CONSTANTS SDH Exported Constants
+  @{
+*/
+
+#define SDH_ERR_ID       0xFFFF0100ul /*!< SDH error ID  \hideinitializer */
+
+#define SDH_TIMEOUT      (SDH_ERR_ID|0x01ul) /*!< Timeout  \hideinitializer */
+#define SDH_NO_MEMORY    (SDH_ERR_ID|0x02ul) /*!< OOM  \hideinitializer */
+
+/*-- function return value */
+#define    Successful  0ul   /*!< Success  \hideinitializer */
+#define    Fail        1ul   /*!< Failed  \hideinitializer */
+
+/*--- define type of SD card or MMC */
+#define SDH_TYPE_UNKNOWN     0ul /*!< Unknown card type  \hideinitializer */
+#define SDH_TYPE_SD_HIGH     1ul /*!< SD card  \hideinitializer */
+#define SDH_TYPE_SD_LOW      2ul /*!< SDHC card  \hideinitializer */
+#define SDH_TYPE_MMC         3ul /*!< MMC card  \hideinitializer */
+#define SDH_TYPE_EMMC        4ul /*!< eMMC card  \hideinitializer */
+
+/* SD error */
+#define SDH_NO_SD_CARD       (SDH_ERR_ID|0x10ul) /*!< Card removed  \hideinitializer */
+#define SDH_ERR_DEVICE       (SDH_ERR_ID|0x11ul) /*!< Device error  \hideinitializer */
+#define SDH_INIT_TIMEOUT     (SDH_ERR_ID|0x12ul) /*!< Card init timeout  \hideinitializer */
+#define SDH_SELECT_ERROR     (SDH_ERR_ID|0x13ul) /*!< Card select error  \hideinitializer */
+#define SDH_WRITE_PROTECT    (SDH_ERR_ID|0x14ul) /*!< Card write protect  \hideinitializer */
+#define SDH_INIT_ERROR       (SDH_ERR_ID|0x15ul) /*!< Card init error  \hideinitializer */
+#define SDH_CRC7_ERROR       (SDH_ERR_ID|0x16ul) /*!< CRC 7 error  \hideinitializer */
+#define SDH_CRC16_ERROR      (SDH_ERR_ID|0x17ul) /*!< CRC 16 error  \hideinitializer */
+#define SDH_CRC_ERROR        (SDH_ERR_ID|0x18ul) /*!< CRC error  \hideinitializer */
+#define SDH_CMD8_ERROR       (SDH_ERR_ID|0x19ul) /*!< Command 8 error  \hideinitializer */
+
+#define MMC_FREQ        20000ul   /*!< output 20MHz to MMC  \hideinitializer */
+#define SD_FREQ         25000ul   /*!< output 25MHz to SD  \hideinitializer */
+#define SDHC_FREQ       50000ul   /*!< output 50MHz to SDH \hideinitializer */
+
+#define SD_PORT0        (1 << 0)  /*!< Card select SD0 \hideinitializer */
+#define SD_PORT1        (1 << 2)  /*!< Card select SD1 \hideinitializer */
+#define CardDetect_From_GPIO  (1ul << 8)   /*!< Card detection pin is GPIO \hideinitializer */
+#define CardDetect_From_DAT3  (1ul << 9)   /*!< Card detection pin is DAT3 \hideinitializer */
+
+/*@}*/ /* end of group M480_SDH_EXPORTED_CONSTANTS */
+
+/** @addtogroup M480_SDH_EXPORTED_TYPEDEF SDH Exported Type Defines
+  @{
+*/
+typedef struct SDH_info_t {
+    unsigned int    CardType;       /*!< SDHC, SD, or MMC */
+    unsigned int    RCA;            /*!< Relative card address */
+    unsigned char   IsCardInsert;   /*!< Card insert state */
+    unsigned int    totalSectorN;   /*!< Total sector number */
+    unsigned int    diskSize;       /*!< Disk size in K bytes */
+    int             sectorSize;     /*!< Sector size in bytes */
+} SDH_INFO_T;                       /*!< Structure holds SD card info */
+
+/*@}*/ /* end of group M480_SDH_EXPORTED_TYPEDEF */
+
+/** @cond HIDDEN_SYMBOLS */
+extern SDH_INFO_T SD0, SD1;
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup M480_SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+
+/**
+ *  @brief    Enable specified interrupt.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ *                           \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
+ *                           \ref SDH_INTEN_WKIEN_Msk
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_ENABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN |= (u32IntMask))
+
+/**
+ *  @brief    Disable specified interrupt.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ *                           \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_DISABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN &= ~(u32IntMask))
+
+/**
+ *  @brief    Get specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
+ *                           \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
+ *                           \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk /
+ *                           \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / 
+ *                           \ref SDH_INTSTS_DAT1STS_Msk
+ *
+ *
+ *  @return  0 = The specified interrupt is not happened.
+ *            1 = The specified interrupt is happened.
+ * \hideinitializer
+ */
+#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0)
+
+
+/**
+ *  @brief    Clear specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /
+ *                           \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
+ *
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask))
+
+
+/**
+ *  @brief    Check SD Card inserted or removed.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return   1: Card inserted.
+ *            0: Card removed.
+ * \hideinitializer
+ */
+#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert)
+
+/**
+ *  @brief    Get SD Card capacity.
+ *
+ *  @param[in]    sdh    Select SDH0 or SDH1.
+ *
+ *  @return   SD Card capacity. (unit: KByte)
+ * \hideinitializer
+ */
+#define SDH_GET_CARD_CAPACITY(sdh)  (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize)
+
+
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
+uint32_t SDH_Probe(SDH_T *sdh);
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+
+uint32_t SDH_CardDetection(SDH_T *sdh);
+void SDH_Open_Disk(SDH_T *sdh, unsigned int u32CardDetSrc);
+void SDH_Close_Disk(SDH_T *sdh);
+
+
+/*@}*/ /* end of group M480_SDH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SDH_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __SDH_H__ */
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spi.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1239 @@
+/**************************************************************************//**
+ * @file     spi.c
+ * @version  V3.00
+ * $Revision: 2 $
+ * $Date: 16/05/31 3:57p $
+ * @brief    M480 series SPI driver source file
+ *
+ * @note
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SPI_Driver SPI Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s);
+
+/**
+  * @brief  This function make SPI module be ready to transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+  * @param[in]  u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
+  * @param[in]  u32DataWidth Decides the data width of a SPI transaction.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI peripheral clock.
+  * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+  *          slave selection function is disabled.
+  *          In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
+  *          The actual clock rate may be different from the target SPI clock rate.
+  *          For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the
+  *          actual SPI clock rate will be 6MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  * @note   In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+  */
+uint32_t SPI_Open(SPI_T *spi,
+                  uint32_t u32MasterSlave,
+                  uint32_t u32SPIMode,
+                  uint32_t u32DataWidth,
+                  uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U;
+
+    /* Disable I2S mode */
+    spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+
+    if(u32DataWidth == 32U) {
+        u32DataWidth = 0U;
+    }
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32MasterSlave == SPI_MASTER) {
+        /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        if(u32BusClock >= u32HCLKFreq) {
+            /* Select PCLK as the clock source of SPI */
+            if(spi == SPI0) {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+            } else if(spi == SPI1) {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            } else if(spi == SPI2) {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+            } else if(spi == SPI3) {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK1;
+            } else {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI4SEL_Msk)) | CLK_CLKSEL2_SPI4SEL_PCLK0;
+            }
+        }
+
+        /* Check clock source of SPI */
+        if(spi == SPI0) {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) {
+                /* Clock source is PCLK0 */
+                u32ClkSrc = CLK_GetPCLK0Freq();
+            } else {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        } else if(spi == SPI1) {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) {
+                /* Clock source is PCLK1 */
+                u32ClkSrc = CLK_GetPCLK1Freq();
+            } else {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        } else if(spi == SPI2) {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) {
+                /* Clock source is PCLK0 */
+                u32ClkSrc = CLK_GetPCLK0Freq();
+            } else {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        } else if(spi == SPI3) {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK1) {
+                u32ClkSrc = CLK_GetPCLK1Freq();
+            } else {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        } else {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_HXT) {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PLL) {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PCLK0) {
+                /* Clock source is PCLK0 */
+                u32ClkSrc = CLK_GetPCLK0Freq();
+            } else {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+
+        if(u32BusClock >= u32HCLKFreq) {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0U;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        } else if(u32BusClock >= u32ClkSrc) {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0U;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        } else if(u32BusClock == 0U) {
+            /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+        } else {
+            u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+            if(u32Div > 0xFFU) {
+                u32Div = 0xFFU;
+                spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+            } else {
+                spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (u32Div + 1U));
+            }
+        }
+    } else { /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
+        /* Default setting: slave selection signal is low level active. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0U;
+
+        /* Select PCLK as the clock source of SPI */
+        if(spi == SPI0) {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        } else  if(spi == SPI1) {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK1Freq();
+        } else if(spi == SPI2) {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        } else if(spi == SPI3) {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK1;
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK1Freq();
+        } else {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI4SEL_Msk)) | CLK_CLKSEL2_SPI4SEL_PCLK0;
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will reset SPI controller.
+  */
+void SPI_Close(SPI_T *spi)
+{
+    if(spi == SPI0) {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+    } else if(spi == SPI1) {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+    } else if(spi == SPI2) {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+    } else if(spi == SPI3) {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
+    } else {
+        /* Reset SPI */
+        SYS->IPRST2 |= SYS_IPRST2_SPI4RST_Msk;
+        SYS->IPRST2 &= ~SYS_IPRST2_SPI4RST_Msk;
+    }
+}
+
+/**
+  * @brief  Clear RX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
+  */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+  * @brief  Clear TX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
+  * @note The TX shift register will not be cleared.
+  */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+  * @brief  Disable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+  */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+    spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
+}
+
+/**
+  * @brief  Enable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SSPinMask Specifies slave selection pins. (SPI_SS)
+  * @param[in]  u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+  * @return None
+  * @details This function will enable the automatic slave selection function. Only available in Master mode.
+  *          The slave selection pin and the active level will be set in this function.
+  */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+  * @brief  Set the SPI bus clock.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI bus clock.
+  * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
+  *          For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock
+  *          rate will be 6 MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc, u32HCLKFreq;
+    uint32_t u32Div, u32RetValue;
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32BusClock >= u32HCLKFreq) {
+        /* Select PCLK as the clock source of SPI */
+        if(spi == SPI0)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+        else if(spi == SPI1)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+        else if(spi == SPI2)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+        else if(spi == SPI3)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK1;
+        else
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI4SEL_Msk)) | CLK_CLKSEL2_SPI4SEL_PCLK0;
+    }
+
+    /* Check clock source of SPI */
+    if(spi == SPI0) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI1) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32ClkSrc = CLK_GetPCLK1Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI2) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI3) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32ClkSrc = CLK_GetPCLK1Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    if(u32BusClock >= u32HCLKFreq) {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0U;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    } else if(u32BusClock >= u32ClkSrc) {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0U;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    } else if(u32BusClock == 0U) {
+        /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+        spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+        /* Return master peripheral clock rate */
+        u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+    } else {
+        u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */
+        if(u32Div > 0x1FFU) {
+            u32Div = 0x1FFU;
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0xFFU + 1U));
+        } else {
+            spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (u32Div + 1U));
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+                   (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                   (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+  * @brief  Get the actual frequency of SPI bus clock. Only available in Master mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return Actual SPI bus clock frequency in Hz.
+  * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
+  */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+    uint32_t u32Div;
+    uint32_t u32ClkSrc;
+
+    /* Get DIVIDER setting */
+    u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
+
+    /* Check clock source of SPI */
+    if(spi == SPI0) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI1) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32ClkSrc = CLK_GetPCLK1Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI2) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(spi == SPI3) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32ClkSrc = CLK_GetPCLK1Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    } else {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_HXT) {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PLL) {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32ClkSrc = CLK_GetPCLK0Freq();
+        } else {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    /* Return SPI bus clock rate */
+    return (u32ClkSrc / (u32Div + 1U));
+}
+
+/**
+  * @brief  Enable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt enable bit.
+  *                     This parameter decides which interrupts will be enabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Enable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Enable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) {
+        spi->CTL |= SPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) {
+        spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) {
+        spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Enable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) {
+        spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) {
+        spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Enable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) {
+        spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) {
+        spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Disable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt bit.
+  *                     This parameter decides which interrupts will be disabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Disable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Disable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) {
+        spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) {
+        spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) {
+        spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Disable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) {
+        spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) {
+        spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Disable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be read. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return Interrupt flags of selected sources.
+  * @details Get SPI related interrupt flags specified by u32Mask parameter.
+  */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0U, u32TmpVal;
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk;
+    /* Check unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_UNIT_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk;
+    /* Check slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_SSACT_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk;
+    /* Check slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_SSINACT_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk;
+    /* Check slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_SLVUR_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk;
+    /* Check slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_SLVBE_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk;
+    /* Check slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_TXUF_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk;
+    /* Check TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk;
+    /* Check RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk;
+    /* Check RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+    }
+
+    u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk;
+    /* Check RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) {
+        u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Clear SPI related interrupt flags specified by u32Mask parameter.
+  */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    if(u32Mask & SPI_UNIT_INT_MASK) {
+        spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+    }
+
+    if(u32Mask & SPI_SSACT_INT_MASK) {
+        spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+    }
+
+    if(u32Mask & SPI_SSINACT_INT_MASK) {
+        spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+    }
+
+    if(u32Mask & SPI_SLVUR_INT_MASK) {
+        spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+    }
+
+    if(u32Mask & SPI_SLVBE_INT_MASK) {
+        spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+    }
+
+    if(u32Mask & SPI_TXUF_INT_MASK) {
+        spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+    }
+
+    if(u32Mask & SPI_FIFO_RXOV_INT_MASK) {
+        spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+    }
+
+    if(u32Mask & SPI_FIFO_RXTO_INT_MASK) {
+        spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+    }
+}
+
+/**
+  * @brief  Get SPI status.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref SPI_BUSY_MASK
+  *                       - \ref SPI_RX_EMPTY_MASK
+  *                       - \ref SPI_RX_FULL_MASK
+  *                       - \ref SPI_TX_EMPTY_MASK
+  *                       - \ref SPI_TX_FULL_MASK
+  *                       - \ref SPI_TXRX_RESET_MASK
+  *                       - \ref SPI_SPIEN_STS_MASK
+  *                       - \ref SPI_SSLINE_STS_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get SPI related status specified by u32Mask parameter.
+  */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32Flag = 0U, u32TmpValue;
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk;
+    /* Check busy status */
+    if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_BUSY_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk;
+    /* Check RX empty flag */
+    if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_RX_EMPTY_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk;
+    /* Check RX full flag */
+    if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_RX_FULL_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk;
+    /* Check TX empty flag */
+    if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_TX_EMPTY_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk;
+    /* Check TX full flag */
+    if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_TX_FULL_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk;
+    /* Check TX/RX reset flag */
+    if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_TXRX_RESET_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk;
+    /* Check SPIEN flag */
+    if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_SPIEN_STS_MASK;
+    }
+
+    u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk;
+    /* Check SPIx_SS line status */
+    if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) {
+        u32Flag |= SPI_SSLINE_STS_MASK;
+    }
+
+    return u32Flag;
+}
+
+
+/**
+  * @brief  This function is used to get I2S source clock frequency.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return I2S source clock frequency (Hz).
+  * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[25:24]) or SPI1SEL (CLKSEL2[27:26]).
+  */
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s)
+{
+    uint32_t u32Freq;
+
+    if(i2s == SPI0) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) {
+            u32Freq = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32Freq = CLK_GetPCLK0Freq();
+        } else {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(i2s == SPI1) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) {
+            u32Freq = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32Freq = CLK_GetPCLK1Freq();
+        } else {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(i2s == SPI2) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) {
+            u32Freq = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32Freq = CLK_GetPCLK0Freq();
+        } else {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    } else if(i2s == SPI3) {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) {
+            u32Freq = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK1) {
+            /* Clock source is PCLK1 */
+            u32Freq = CLK_GetPCLK1Freq();
+        } else {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    } else {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_HXT) {
+            u32Freq = __HXT; /* Clock source is HXT */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PLL) {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        } else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI4SEL_Msk) == CLK_CLKSEL2_SPI4SEL_PCLK0) {
+            /* Clock source is PCLK0 */
+            u32Freq = CLK_GetPCLK0Freq();
+        } else {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief  This function configures some parameters of I2S interface for general purpose use.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
+  *                                     - \ref SPII2S_MODE_MASTER
+  *                                     - \ref SPII2S_MODE_SLAVE
+  * @param[in] u32SampleRate Sample rate
+  * @param[in] u32WordWidth Data length. Valid values are listed below.
+  *                                     - \ref SPII2S_DATABIT_8
+  *                                     - \ref SPII2S_DATABIT_16
+  *                                     - \ref SPII2S_DATABIT_24
+  *                                     - \ref SPII2S_DATABIT_32
+  * @param[in] u32Channels Audio format. Valid values are listed below.
+  *                                     - \ref SPII2S_MONO
+  *                                     - \ref SPII2S_STEREO
+  * @param[in] u32DataFormat Data format. Valid values are listed below.
+  *                                     - \ref SPII2S_FORMAT_I2S
+  *                                     - \ref SPII2S_FORMAT_MSB
+  *                                     - \ref SPII2S_FORMAT_PCMA
+  *                                     - \ref SPII2S_FORMAT_PCMB
+  * @return Real sample rate of master mode or peripheral clock rate of slave mode.
+  * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
+  *          Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled.
+  *          The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
+  * @note   In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+  */
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
+{
+    uint32_t u32Divider;
+    uint32_t u32BitRate, u32SrcClk, u32RetValue;
+
+    /* Reset SPI/I2S */
+    if(i2s == SPI0) {
+        SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+    } else if(i2s == SPI1) {
+        SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+    } else if(i2s == SPI2) {
+        SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+    } else if(i2s == SPI3) {
+        SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
+    } else {
+        SYS->IPRST2 |= SYS_IPRST2_SPI4RST_Msk;
+        SYS->IPRST2 &= ~SYS_IPRST2_SPI4RST_Msk;
+    }
+
+    /* Configure I2S controller */
+    i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
+    /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */
+    i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2;
+
+    if(u32MasterSlave == SPI_MASTER) {
+        /* Get the source clock rate */
+        u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+
+        /* Calculate the bit clock rate */
+        u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U;
+        u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U;
+        /* Set BCLKDIV setting */
+        i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
+
+        /* Calculate bit clock rate */
+        u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U);
+        /* Calculate real sample rate */
+        u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U);
+
+        /* Enable TX function, RX function and I2S mode. */
+        i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+
+        /* Return the real sample rate */
+        u32RetValue = u32SampleRate;
+    } else {
+        /* Set BCLKDIV = 0 */
+        i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
+
+        if(i2s == SPI0) {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        } else if(i2s == SPI1) {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK1Freq();
+        } else if(i2s == SPI2) {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        } else if(i2s == SPI3) {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK1;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK1Freq();
+        } else {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI4SEL_Msk)) | CLK_CLKSEL2_SPI4SEL_PCLK0;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            u32RetValue = CLK_GetPCLK0Freq();
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable I2S function.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Disable I2S function.
+  */
+void SPII2S_Close(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+}
+
+/**
+  * @brief Enable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref SPII2S_FIFO_TXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXOV_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTO_INT_MASK
+  *            - \ref SPII2S_TXUF_INT_MASK
+  *            - \ref SPII2S_RIGHT_ZC_INT_MASK
+  *            - \ref SPII2S_LEFT_ZC_INT_MASK
+  * @return None
+  * @details This function enables the interrupt according to the u32Mask parameter.
+  */
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) {
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+
+    /* Enable TX underflow interrupt flag */
+    if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) {
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Enable right channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) {
+        i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
+    }
+
+    /* Enable left channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) {
+        i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
+    }
+}
+
+/**
+  * @brief Disable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref SPII2S_FIFO_TXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXOV_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTO_INT_MASK
+  *            - \ref SPII2S_TXUF_INT_MASK
+  *            - \ref SPII2S_RIGHT_ZC_INT_MASK
+  *            - \ref SPII2S_LEFT_ZC_INT_MASK
+  * @return None
+  * @details This function disables the interrupt according to the u32Mask parameter.
+  */
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+
+    /* Disable TX underflow interrupt flag */
+    if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Disable right channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) {
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
+    }
+
+    /* Disable left channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) {
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Enable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32BusClock The target MCLK clock rate.
+  * @return Actual MCLK clock rate
+  * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+  *          The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+  */
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
+{
+    uint32_t u32Divider;
+    uint32_t u32SrcClk, u32RetValue;
+
+    u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+    if(u32BusClock == u32SrcClk) {
+        u32Divider = 0U;
+    } else {
+        u32Divider = (u32SrcClk / u32BusClock) >> 1U;
+        /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */
+        if(u32Divider > 0x3FU) {
+            u32Divider = 0x3FU;
+        }
+    }
+
+    /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
+    i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
+
+    /* Enable MCLK output */
+    i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
+
+    if(u32Divider == 0U) {
+        u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
+    } else {
+        u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
+  */
+void SPII2S_DisableMCLK(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+                   (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                   (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/*@}*/ /* end of group M480_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SPI_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spi.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     spi.h
+ * @version  V3.00
+ * @brief    M480 series SPI driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SPI_Driver SPI Driver
+  @{
+*/
+
+/** @addtogroup M480_SPI_EXPORTED_CONSTANTS SPI Exported Constants
+  @{
+*/
+
+#define SPI_MODE_0        (SPI_CTL_TXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
+#define SPI_MODE_1        (SPI_CTL_RXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
+#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
+#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
+
+#define SPI_SLAVE         (SPI_CTL_SLAVE_Msk)                             /*!< Set as slave \hideinitializer */
+#define SPI_MASTER        (0x0U)                                          /*!< Set as master \hideinitializer */
+
+#define SPI_SS                (SPI_SSCTL_SS_Msk)                          /*!< Set SS \hideinitializer */
+#define SPI_SS_ACTIVE_HIGH    (SPI_SSCTL_SSACTPOL_Msk)                    /*!< SS active high \hideinitializer */
+#define SPI_SS_ACTIVE_LOW     (0x0U)                                      /*!< SS active low \hideinitializer */
+
+/* SPI Interrupt Mask */
+#define SPI_UNIT_INT_MASK                (0x001U)                          /*!< Unit transfer interrupt mask \hideinitializer */
+#define SPI_SSACT_INT_MASK               (0x002U)                          /*!< Slave selection signal active interrupt mask \hideinitializer */
+#define SPI_SSINACT_INT_MASK             (0x004U)                          /*!< Slave selection signal inactive interrupt mask \hideinitializer */
+#define SPI_SLVUR_INT_MASK               (0x008U)                          /*!< Slave under run interrupt mask \hideinitializer */
+#define SPI_SLVBE_INT_MASK               (0x010U)                          /*!< Slave bit count error interrupt mask \hideinitializer */
+#define SPI_TXUF_INT_MASK                (0x040U)                          /*!< Slave TX underflow interrupt mask \hideinitializer */
+#define SPI_FIFO_TXTH_INT_MASK           (0x080U)                          /*!< FIFO TX threshold interrupt mask \hideinitializer */
+#define SPI_FIFO_RXTH_INT_MASK           (0x100U)                          /*!< FIFO RX threshold interrupt mask \hideinitializer */
+#define SPI_FIFO_RXOV_INT_MASK           (0x200U)                          /*!< FIFO RX overrun interrupt mask \hideinitializer */
+#define SPI_FIFO_RXTO_INT_MASK           (0x400U)                          /*!< FIFO RX time-out interrupt mask \hideinitializer */
+
+/* SPI Status Mask */
+#define SPI_BUSY_MASK                    (0x01U)                           /*!< Busy status mask \hideinitializer */
+#define SPI_RX_EMPTY_MASK                (0x02U)                           /*!< RX empty status mask \hideinitializer */
+#define SPI_RX_FULL_MASK                 (0x04U)                           /*!< RX full status mask \hideinitializer */
+#define SPI_TX_EMPTY_MASK                (0x08U)                           /*!< TX empty status mask \hideinitializer */
+#define SPI_TX_FULL_MASK                 (0x10U)                           /*!< TX full status mask \hideinitializer */
+#define SPI_TXRX_RESET_MASK              (0x20U)                           /*!< TX or RX reset status mask \hideinitializer */
+#define SPI_SPIEN_STS_MASK               (0x40U)                           /*!< SPIEN status mask \hideinitializer */
+#define SPI_SSLINE_STS_MASK              (0x80U)                           /*!< SPIx_SS line status mask \hideinitializer */
+
+
+/* I2S Data Width */
+#define SPII2S_DATABIT_8           (0U << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 8-bit \hideinitializer */
+#define SPII2S_DATABIT_16          (1U << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 16-bit \hideinitializer */
+#define SPII2S_DATABIT_24          (2U << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 24-bit \hideinitializer */
+#define SPII2S_DATABIT_32          (3U << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 32-bit \hideinitializer */
+
+/* I2S Audio Format */
+#define SPII2S_MONO                SPI_I2SCTL_MONO_Msk                /*!< Monaural channel \hideinitializer */
+#define SPII2S_STEREO              (0U)                               /*!< Stereo channel \hideinitializer */
+
+/* I2S Data Format */
+#define SPII2S_FORMAT_I2S          (0U<<SPI_I2SCTL_FORMAT_Pos)         /*!< I2S data format \hideinitializer */
+#define SPII2S_FORMAT_MSB          (1U<<SPI_I2SCTL_FORMAT_Pos)         /*!< MSB justified data format \hideinitializer */
+#define SPII2S_FORMAT_PCMA         (2U<<SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode A data format \hideinitializer */
+#define SPII2S_FORMAT_PCMB         (3U<<SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode B data format \hideinitializer */
+
+/* I2S Operation mode */
+#define SPII2S_MODE_SLAVE          SPI_I2SCTL_SLAVE_Msk               /*!< As slave mode \hideinitializer */
+#define SPII2S_MODE_MASTER         (0U)                               /*!< As master mode \hideinitializer */
+
+/* I2S TX FIFO Threshold */
+#define SPII2S_FIFO_TX_LEVEL_WORD_0    (0U)                            /*!< TX threshold is 0 word \hideinitializer */
+#define SPII2S_FIFO_TX_LEVEL_WORD_1    (1U << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 1 word \hideinitializer */
+#define SPII2S_FIFO_TX_LEVEL_WORD_2    (2U << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 2 words \hideinitializer */
+#define SPII2S_FIFO_TX_LEVEL_WORD_3    (3U << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 3 words \hideinitializer */
+/* I2S RX FIFO Threshold */
+#define SPII2S_FIFO_RX_LEVEL_WORD_1    (0U)                            /*!< RX threshold is 1 word \hideinitializer */
+#define SPII2S_FIFO_RX_LEVEL_WORD_2    (1U << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 2 words \hideinitializer */
+#define SPII2S_FIFO_RX_LEVEL_WORD_3    (2U << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 3 words \hideinitializer */
+#define SPII2S_FIFO_RX_LEVEL_WORD_4    (3U << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 4 words \hideinitializer */
+
+/* I2S Record Channel */
+#define SPII2S_MONO_RIGHT          (0U)                               /*!< Record mono right channel \hideinitializer */
+#define SPII2S_MONO_LEFT           SPI_I2SCTL_RXLCH_Msk               /*!< Record mono left channel \hideinitializer */
+
+/* I2S Channel */
+#define SPII2S_RIGHT               (0U)                               /*!< Select right channel \hideinitializer */
+#define SPII2S_LEFT                (1U)                               /*!< Select left channel \hideinitializer */
+
+/* I2S Interrupt Mask */
+#define SPII2S_FIFO_TXTH_INT_MASK           (0x01U)                          /*!< TX FIFO threshold interrupt mask \hideinitializer */
+#define SPII2S_FIFO_RXTH_INT_MASK           (0x02U)                          /*!< RX FIFO threshold interrupt mask \hideinitializer */
+#define SPII2S_FIFO_RXOV_INT_MASK           (0x04U)                          /*!< RX FIFO overrun interrupt mask \hideinitializer */
+#define SPII2S_FIFO_RXTO_INT_MASK           (0x08U)                          /*!< RX FIFO time-out interrupt mask \hideinitializer */
+#define SPII2S_TXUF_INT_MASK                (0x10U)                          /*!< TX FIFO underflow interrupt mask \hideinitializer */
+#define SPII2S_RIGHT_ZC_INT_MASK            (0x20U)                          /*!< Right channel zero cross interrupt mask \hideinitializer */
+#define SPII2S_LEFT_ZC_INT_MASK             (0x40U)                          /*!< Left channel zero cross interrupt mask \hideinitializer */
+
+/*@}*/ /* end of group M480_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear the unit transfer interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
+  * \hideinitializer
+  */
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi)   ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_TRIGGER_RX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_TRIGGER_TX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Get the count of available data in RX FIFO.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     The count of available data in RX FIFO.
+  * @details    Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+  * \hideinitializer
+  */
+#define SPI_GET_RX_FIFO_COUNT(spi)   (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
+
+/**
+  * @brief      Get the RX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 RX FIFO is not empty.
+  * @retval     1 RX FIFO is empty.
+  * @details    Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
+  * \hideinitializer
+  */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
+
+/**
+  * @brief      Get the TX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not empty.
+  * @retval     1 TX FIFO is empty.
+  * @details    Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
+  * \hideinitializer
+  */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
+
+/**
+  * @brief      Get the TX FIFO full flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not full.
+  * @retval     1 TX FIFO is full.
+  * @details    Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
+  * \hideinitializer
+  */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
+
+/**
+  * @brief      Get the datum read from RX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     Data in RX register.
+  * @details    Read SPI_RX register to get the received datum.
+  * \hideinitializer
+  */
+#define SPI_READ_RX(spi)   ((spi)->RX)
+
+/**
+  * @brief      Write datum to TX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through SPI bus.
+  * @return     None.
+  * @details    Write u32TxData to SPI_TX register.
+  * \hideinitializer
+  */
+#define SPI_WRITE_TX(spi, u32TxData)   ((spi)->TX = (u32TxData))
+
+/**
+  * @brief      Set SPIx_SS pin to high state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIx_SS pin to high state.
+  * \hideinitializer
+  */
+#define SPI_SET_SS_HIGH(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
+
+/**
+  * @brief      Set SPIx_SS pin to low state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIx_SS pin to low state.
+  * \hideinitializer
+  */
+#define SPI_SET_SS_LOW(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
+
+/**
+  * @brief      Enable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
+  * \hideinitializer
+  */
+#define SPI_ENABLE_BYTE_REORDER(spi)   ((spi)->CTL |=  SPI_CTL_REORDER_Msk)
+
+/**
+  * @brief      Disable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
+  * \hideinitializer
+  */
+#define SPI_DISABLE_BYTE_REORDER(spi)   ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
+
+/**
+  * @brief      Set the length of suspend interval.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+  * @return     None.
+  * @details    Set the length of suspend interval according to u32SuspCycle.
+  *             The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
+  * \hideinitializer
+  */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
+
+/**
+  * @brief      Set the SPI transfer sequence with LSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
+  * \hideinitializer
+  */
+#define SPI_SET_LSB_FIRST(spi)   ((spi)->CTL |= SPI_CTL_LSB_Msk)
+
+/**
+  * @brief      Set the SPI transfer sequence with MSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
+  * \hideinitializer
+  */
+#define SPI_SET_MSB_FIRST(spi)   ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
+
+/**
+  * @brief      Set the data width of a SPI transaction.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Width The bit width of one transaction.
+  * @return     None.
+  * @details    The data width can be 8 ~ 32 bits.
+  * \hideinitializer
+  */
+#define SPI_SET_DATA_WIDTH(spi, u32Width)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
+
+/**
+  * @brief      Get the SPI busy state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 SPI controller is not busy.
+  * @retval     1 SPI controller is busy.
+  * @details    This macro will return the busy state of SPI controller.
+  * \hideinitializer
+  */
+#define SPI_IS_BUSY(spi)   ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
+
+/**
+  * @brief      Enable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set SPIEN (SPI_CTL[0]) to enable SPI controller.
+  * \hideinitializer
+  */
+#define SPI_ENABLE(spi)   ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
+
+/**
+  * @brief      Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
+  * \hideinitializer
+  */
+#define SPI_DISABLE(spi)   ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
+
+/**
+  * @brief  Disable SPI Dual IO function.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk )
+
+/**
+  * @brief  Enable Dual IO function and set SPI Dual IO direction to input.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DATDIR_Msk) | SPI_CTL_DUALIOEN_Msk )
+
+/**
+  * @brief  Enable Dual IO function and set SPI Dual IO direction to output.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_DATDIR_Msk | SPI_CTL_DUALIOEN_Msk )
+
+/**
+  * @brief  Disable SPI Dual IO function.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_DISABLE_QUAD_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk )
+
+/**
+  * @brief  Set SPI Quad IO direction to input.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DATDIR_Msk) | SPI_CTL_QUADIOEN_Msk )
+
+/**
+  * @brief  Set SPI Quad IO direction to output.
+  * @param[in]  spi is the base address of SPI module.
+  * @return none
+  * \hideinitializer
+  */
+#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_DATDIR_Msk | SPI_CTL_QUADIOEN_Msk )
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
+static __INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
+static __INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
+
+/**
+  * @brief  Enable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref SPII2S_RIGHT
+  *                    - \ref SPII2S_LEFT
+  * @return None
+  * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
+  */
+static __INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == SPII2S_RIGHT) {
+        i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
+    } else {
+        i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
+    }
+}
+
+/**
+  * @brief  Disable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref SPII2S_RIGHT
+  *                    - \ref SPII2S_LEFT
+  * @return None
+  * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
+  */
+static __INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == SPII2S_RIGHT) {
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
+    } else {
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
+    }
+}
+
+/**
+  * @brief  Enable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
+  * \hideinitializer
+  */
+#define SPII2S_ENABLE_TXDMA(i2s)  ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
+  * \hideinitializer
+  */
+#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
+  * \hideinitializer
+  */
+#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
+  * \hideinitializer
+  */
+#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
+  * \hideinitializer
+  */
+#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Disable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
+  * \hideinitializer
+  */
+#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Enable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
+  * \hideinitializer
+  */
+#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Disable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
+  * \hideinitializer
+  */
+#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Enable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
+  * \hideinitializer
+  */
+#define SPII2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Disable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
+  * \hideinitializer
+  */
+#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Clear TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
+  * \hideinitializer
+  */
+#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
+
+/**
+  * @brief  Clear RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
+  * \hideinitializer
+  */
+#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
+
+/**
+  * @brief  This function sets the recording source channel when mono mode is used.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Ch left or right channel. Valid values are:
+  *                - \ref SPII2S_MONO_LEFT
+  *                - \ref SPII2S_MONO_RIGHT
+  * @return None
+  * @details This function selects the recording source channel of monaural mode.
+  * \hideinitializer
+  */
+static __INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
+{
+    u32Ch == SPII2S_MONO_LEFT ?
+    (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
+    (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
+}
+
+/**
+  * @brief  Write data to I2S TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Data The value written to TX FIFO.
+  * @return None
+  * @details This macro will write a value to TX FIFO.
+  * \hideinitializer
+  */
+#define SPII2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TX = (u32Data) )
+
+/**
+  * @brief  Read RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return The value read from RX FIFO.
+  * @details This function will return a value read from RX FIFO.
+  * \hideinitializer
+  */
+#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
+
+/**
+  * @brief  Get the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return The interrupt flags specified by the u32mask parameter.
+  * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
+  * \hideinitializer
+  */
+#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
+
+/**
+  * @brief  Clear the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return None
+  * @details This macro will clear the interrupt flags specified by the u32mask parameter.
+  * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
+  * \hideinitializer
+  */
+#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
+
+/**
+  * @brief  Get transmit FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return TX FIFO level
+  * @details This macro will return the number of available words in TX FIFO.
+  * \hideinitializer
+  */
+#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos  )
+
+/**
+  * @brief  Get receive FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return RX FIFO level
+  * @details This macro will return the number of available words in RX FIFO.
+  * \hideinitializer
+  */
+#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
+
+
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
+void SPII2S_Close(SPI_T *i2s);
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
+void SPII2S_DisableMCLK(SPI_T *i2s);
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+
+/*@}*/ /* end of group M480_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SPI_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1195 @@
+/**************************************************************************//**
+ * @file    spim.c
+ * @version V1.00
+ * $Revision:1$
+ * $Date:14/5/5 5:45p$
+ * @brief   M480 series SPIM driver
+ *
+ * @note
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SPIM_Driver SPIM Driver
+  @{
+*/
+
+/** @addtogroup M480_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
+  @{
+*/
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+
+#define ENABLE_DEBUG    0
+
+#if ENABLE_DEBUG
+#define SPIM_DBGMSG   printf
+#else
+#define SPIM_DBGMSG(...)   do { } while (0)      /* disable debug */
+#endif
+
+static volatile uint8_t  g_Supported_List[] = {
+    MFGID_WINBOND,
+    MFGID_MXIC,
+    MFGID_EON,
+    MFGID_ISSI,
+    MFGID_SPANSION
+};
+
+static void  N_delay(int n);
+static void SwitchNBitOutput(uint32_t u32NBit);
+static void SwitchNBitInput(uint32_t u32NBit);
+static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx);
+static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx);
+static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
+static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
+static int spim_is_write_done(uint32_t u32NBit);
+static int spim_wait_write_done(uint32_t u32NBit);
+static void spim_set_write_enable(int isEn, uint32_t u32NBit);
+static void spim_enable_spansion_quad_mode(int isEn);
+static void spim_eon_set_qpi_mode(int isEn);
+static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit);
+static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+                                     uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync);
+static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx,
+        uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync);
+
+
+static void  N_delay(int n)
+{
+    while (n-- > 0) {
+        __NOP();
+    }
+}
+
+static void SwitchNBitOutput(uint32_t u32NBit)
+{
+    switch (u32NBit) {
+    case 1UL:
+        SPIM_ENABLE_SING_OUTPUT_MODE();     /* 1-bit, Output. */
+        break;
+
+    case 2UL:
+        SPIM_ENABLE_DUAL_OUTPUT_MODE();     /* 2-bit, Output. */
+        break;
+
+    case 4UL:
+        SPIM_ENABLE_QUAD_OUTPUT_MODE();     /* 4-bit, Output. */
+        break;
+
+    default:
+        break;
+    }
+}
+
+static void SwitchNBitInput(uint32_t u32NBit)
+{
+    switch (u32NBit) {
+    case 1UL:
+        SPIM_ENABLE_SING_INPUT_MODE();      /* 1-bit, Input.  */
+        break;
+
+    case 2UL:
+        SPIM_ENABLE_DUAL_INPUT_MODE();      /* 2-bit, Input.  */
+        break;
+
+    case 4UL:
+        SPIM_ENABLE_QUAD_INPUT_MODE();      /* 4-bit, Input.  */
+        break;
+
+    default:
+        break;
+    }
+}
+
+
+/**
+  * @brief      Write data to SPI slave.
+  * @param      pu8TxBuf    Transmit buffer.
+  * @param      u32NTx      Number of bytes to transmit.
+  * @return     None.
+  */
+static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx)
+{
+    uint32_t  buf_idx = 0UL;
+
+    while (u32NTx) {
+        uint32_t dataNum = 0UL, dataNum2;
+
+        if (u32NTx >= 16UL) {
+            dataNum = 4UL;
+        } else if (u32NTx >= 12UL) {
+            dataNum = 3UL;
+        } else if (u32NTx >= 8UL) {
+            dataNum = 2UL;
+        } else if (u32NTx >= 4UL) {
+            dataNum = 1UL;
+        }
+
+        dataNum2 = dataNum;
+        while (dataNum2) {
+            uint32_t tmp;
+
+            memcpy(&tmp, &pu8TxBuf[buf_idx], 4U);
+            buf_idx += 4UL;
+            u32NTx -= 4UL;
+
+            dataNum2 --;
+            /*  *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */
+            SPIM->TX[dataNum2] = tmp;
+        }
+
+        if (dataNum) {
+            SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO);    /* Switch to Normal mode. */
+            SPIM_SET_DATA_WIDTH(32UL);
+            SPIM_SET_DATA_NUM(dataNum);
+            SPIM_SET_GO();
+            SPIM_WAIT_FREE();
+        }
+
+        if (u32NTx && (u32NTx < 4UL)) {
+            uint32_t  rnm, tmp;
+
+            rnm = u32NTx;
+            memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx);
+            buf_idx += u32NTx;
+            u32NTx = 0UL;
+            SPIM->TX[0] = tmp;
+
+            SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO);    /* Switch to Normal mode. */
+            SPIM_SET_DATA_WIDTH(rnm * 8UL);
+            SPIM_SET_DATA_NUM(1UL);
+            SPIM_SET_GO();
+            SPIM_WAIT_FREE();
+        }
+    }
+}
+
+/**
+  * @brief      Read data from SPI slave.
+  * @param      pu8TxBuf    Receive buffer.
+  * @param      u32NRx      Size of receive buffer in bytes.
+  * @return     None.
+  */
+static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
+{
+    uint32_t  buf_idx = 0UL;
+
+    while (u32NRx) {
+        uint32_t dataNum = 0UL;   /* number of words */
+
+        if (u32NRx >= 16UL) {
+            dataNum = 4UL;
+        } else if (u32NRx >= 12UL) {
+            dataNum = 3UL;
+        } else if (u32NRx >= 8UL) {
+            dataNum = 2UL;
+        } else if (u32NRx >= 4UL) {
+            dataNum = 1UL;
+        }
+
+        if (dataNum) {
+            SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO);    /* Switch to Normal mode. */
+            SPIM_SET_DATA_WIDTH(32UL);
+            SPIM_SET_DATA_NUM(dataNum);
+            SPIM_SET_GO();
+            SPIM_WAIT_FREE();
+        }
+
+        while (dataNum) {
+            uint32_t tmp;
+
+            tmp = SPIM->RX[dataNum-1UL];
+            memcpy(&pu8RxBuf[buf_idx], &tmp, 4U);
+            buf_idx += 4UL;
+            dataNum --;
+            u32NRx -= 4UL;
+        }
+
+        if (u32NRx && (u32NRx < 4UL)) {
+            uint32_t tmp;
+
+            SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO);    /* Switch to Normal mode. */
+            SPIM_SET_DATA_WIDTH(u32NRx * 8UL);
+            SPIM_SET_DATA_NUM(1UL);
+            SPIM_SET_GO();
+            SPIM_WAIT_FREE();
+
+            tmp = SPIM->RX[0];
+            memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx);
+            buf_idx += u32NRx;
+            u32NRx = 0UL;
+        }
+    }
+}
+
+/**
+  * @brief      Issue Read Status Register #1 command.
+  * @param      dataBuf     Receive buffer.
+  * @param      u32NRx      Size of receive buffer.
+ * @param       u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_RDSR};            /* 1-byte Read Status Register #1 command. */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(u32NBit);
+    spim_read(dataBuf, u32NRx);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+
+/**
+  * @brief      Issue Write Status Register #1 command.
+  * @param      dataBuf     Transmit buffer.
+  * @param      u32NTx      Size of transmit buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U};     /* 1-byte Write Status Register #1 command + 1-byte data. */
+
+    cmdBuf[1] = dataBuf[0];
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+
+/**
+  * @brief      Issue Read Status Register #2 command.
+  * @param      dataBuf     Receive buffer.
+  * @param      u32NRx      Size of receive buffer.
+ * @param       u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_RDSR2};           /* 1-byte Read Status Register #1 command. */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.  */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(u32NBit);
+    spim_read(dataBuf, u32NRx);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+/**
+  * @brief      Issue Winbond Write Status Register command. This command write both Status Register-1
+  *             and Status Register-2.
+  * @param      dataBuf     Transmit buffer.
+  * @param      u32NTx      Size of transmit buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U};
+
+    cmdBuf[1] = dataBuf[0];
+    cmdBuf[2] = dataBuf[1];
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+#if 0  /* not used */
+/**
+  * @brief      Issue Write Status Register #3 command.
+  * @param      dataBuf     Transmit buffer.
+  * @param      u32NTx      Size of transmit buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U};    /* 1-byte Write Status Register #2 command + 1-byte data. */
+    cmdBuf[1] = dataBuf[0];
+
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+#endif
+
+/**
+  * @brief      Issue Read Status Register #3 command.
+  * @param      dataBuf     Receive buffer.
+  * @param      u32NRx      Size of receive buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_RDSR3};           /* 1-byte Read Status Register #1 command. */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(u32NBit);
+    spim_read(dataBuf, u32NRx);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+
+#if 0  /* not used */
+/**
+  * @brief      Issue Write Security Register command.
+  * @param      dataBuf     Transmit buffer.
+  * @param      u32NTx      Size of transmit buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U};   /* 1-byte Write Status Register #2 command + 1-byte data. */
+    cmdBuf[1] = dataBuf[0];
+
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+#endif
+
+/**
+  * @brief      Issue Read Security Register command.
+  * @param      dataBuf     Receive buffer.
+  * @param      u32NRx      Size of receive buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {OPCODE_RDSCUR};          /* 1-byte Read Status Register #1 command. */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated. */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(u32NBit);
+    spim_read(dataBuf, u32NRx);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated. */
+}
+
+/**
+  * @brief      Check if Erase/Write is done.
+  * @return     0: Not done. 1: Done.
+  */
+static int spim_is_write_done(uint32_t u32NBit)
+{
+    uint8_t status[1];
+    SPIM_ReadStatusRegister(status, sizeof (status), u32NBit);
+    return ! (status[0] & SR_WIP);
+}
+
+/**
+  * @brief      Wait until Erase/Write done.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     0           SPIM write done.
+  */
+static int spim_wait_write_done(uint32_t u32NBit)
+{
+    uint32_t   count;
+    int        ret = -1;
+
+    for (count = 0UL; count < SystemCoreClock/1000UL; count++) {
+        if (spim_is_write_done(u32NBit)) {
+            ret = 0;
+            break;
+        }
+    }
+    if (ret != 0) {
+        SPIM_DBGMSG("spim_wait_write_done time-out!!\n");
+    }
+    return -1;
+}
+
+/**
+  * @brief      Issue Write Enable/disable command.
+  * @param      isEn        Enable/disable.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+static void spim_set_write_enable(int isEn, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = {0U};                     /* 1-byte Write Enable command. */
+    cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI;
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.   */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Get SPIM serial clock.
+  * @return     SPI serial clock.
+  * @details    This function calculates the serial clock of SPI in Hz.
+  */
+uint32_t SPIM_GetSClkFreq(void)
+{
+    uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER();
+
+    return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock;
+}
+
+/**
+  * @brief      Initialize SPIM flash.
+  * @param      clrWP       Clear Write Protect or not.
+  * @return     0    Success.
+  * @return     -1   Unrecognized manufacture ID or failed on reading manufacture ID.
+  */
+int SPIM_InitFlash(int clrWP)
+{
+    uint8_t   idBuf[3];
+    uint8_t   cmdBuf[1];
+    uint32_t  i;
+    int32_t   ret = -1;
+
+    SPIM_SET_SS_ACTLVL(0);
+
+    /*
+     * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset.
+     */
+    /* QPI Reset Enable */
+    cmdBuf[0] = OPCODE_RSTEN;
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SPIM_ENABLE_QUAD_OUTPUT_MODE();             /* 1-bit, Output.   */
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    /* QPI Reset */
+    cmdBuf[0] = OPCODE_RST;
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SPIM_ENABLE_QUAD_OUTPUT_MODE();             /* 1-bit, Output.   */
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    /* SPI ResetEnable */
+    cmdBuf[0] = OPCODE_RSTEN;
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SPIM_ENABLE_SING_OUTPUT_MODE();             /* 1-bit, Output.   */
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    /* SPI Reset */
+    cmdBuf[0] = OPCODE_RST;
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SPIM_ENABLE_SING_OUTPUT_MODE();             /* 1-bit, Output.   */
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    if (clrWP) {
+        uint8_t dataBuf[] = {0x00U};
+
+        spim_set_write_enable(1, 1UL);           /* Clear Block Protect. */
+        SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U);
+        spim_wait_write_done(1UL);
+    }
+
+    SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL);
+
+    /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */
+
+    for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++) {
+        if (idBuf[0] == g_Supported_List[i]) {
+            ret = 0;
+        }
+    }
+    if (ret != 0) {
+        SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]);
+    }
+    return ret;
+}
+
+/**
+  * @brief      Issue JEDEC ID command.
+  * @param      idBuf       ID buffer.
+  * @param      u32NRx      Size of ID buffer.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[] = { OPCODE_RDID };          /* 1-byte JEDEC ID command.  */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(u32NBit);
+    spim_read(idBuf, u32NRx);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+static void spim_enable_spansion_quad_mode(int isEn)
+{
+    uint8_t cmdBuf[3];
+    uint8_t dataBuf[1], status1;
+
+    cmdBuf[0] = 0x5U;                            /* Read Status Register-1 */
+
+    SPIM_SET_SS_EN(1);
+    SwitchNBitOutput(1UL);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(1UL);
+    spim_read(dataBuf, sizeof (dataBuf));
+    SPIM_SET_SS_EN(0);
+    /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */
+
+    status1 = dataBuf[0];
+
+    cmdBuf[0] = 0x35U;                           /* Read Configuration Register-1 */
+
+    SPIM_SET_SS_EN(1);
+    SwitchNBitOutput(1UL);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(1UL);
+    spim_read(dataBuf, sizeof (dataBuf));
+    SPIM_SET_SS_EN(0);
+    /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
+
+    spim_set_write_enable(1, 1UL);
+
+    cmdBuf[0] =  0x1U;                           /* Write register   */
+    cmdBuf[1] =  status1;
+
+    if (isEn) {
+        cmdBuf[2] = dataBuf[0] | 0x2U;           /* set QUAD         */
+    } else {
+        cmdBuf[2] = dataBuf[0] & ~0x2U;          /* clear QUAD       */
+    }
+
+    SPIM_SET_SS_EN(1);
+    SwitchNBitOutput(1UL);
+    spim_write(cmdBuf, 3UL);
+    SPIM_SET_SS_EN(0);
+
+    spim_set_write_enable(0, 1UL);
+
+
+    cmdBuf[0] = 0x35U;                           /* Read Configuration Register-1 */
+
+    SPIM_SET_SS_EN(1);
+    SwitchNBitOutput(1UL);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SwitchNBitInput(1UL);
+    spim_read(dataBuf, sizeof (dataBuf));
+    SPIM_SET_SS_EN(0);
+
+    /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
+    N_delay(10000);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Set Quad Enable/disable.
+  * @param      isEn        Enable/disable.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     None.
+  */
+void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit)
+{
+    uint8_t  idBuf[3];
+    uint8_t  dataBuf[2];
+
+    SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+    SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]);
+
+    switch (idBuf[0]) {
+    case MFGID_WINBOND:                      /* Winbond SPI flash  */
+        SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+        SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+        SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+        if (isEn) {
+            dataBuf[1] |= SR2_QE;
+        } else {
+            dataBuf[1] &= ~SR2_QE;
+        }
+
+        spim_set_write_enable(1, u32NBit);   /* Write Enable.    */
+        SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit);
+        spim_wait_write_done(u32NBit);
+
+        SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
+        SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
+        SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
+        break;
+
+    case MFGID_MXIC:                         /* MXIC SPI flash.  */
+    case MFGID_EON:
+    case MFGID_ISSI:                         /* ISSI SPI flash.  */
+        spim_set_write_enable(1, u32NBit);   /* Write Enable.    */
+        dataBuf[0] = isEn ? SR_QE : 0U;
+        SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit);
+        spim_wait_write_done(u32NBit);
+        break;
+
+    case MFGID_SPANSION:
+        spim_enable_spansion_quad_mode(isEn);
+        break;
+
+    default:
+        break;
+    }
+}
+
+/**
+  * @brief      Enter/exit QPI mode.
+  * @param      isEn        Enable/disable.
+  * @return     None.
+  */
+static void spim_eon_set_qpi_mode(int isEn)
+{
+    uint8_t cmdBuf[1];                           /* 1-byte command.  */
+
+    uint8_t status[1];
+    SPIM_ReadStatusRegister(status, sizeof (status), 1UL);
+    SPIM_DBGMSG("Status: 0x%x\n", status[0]);
+
+    if (isEn) {                                  /* Assume in SPI mode. */
+        cmdBuf[0] = OPCODE_ENQPI;
+
+        SPIM_SET_SS_EN(1);                      /* CS activated.    */
+        SwitchNBitOutput(1UL);
+        spim_write(cmdBuf, sizeof (cmdBuf));
+        SPIM_SET_SS_EN(0);                      /* CS deactivated.  */
+    } else {                                     /* Assume in QPI mode. */
+        cmdBuf[0] = OPCODE_EXQPI;
+
+        SPIM_SET_SS_EN(1);                      /* CS activated.    */
+        SwitchNBitOutput(4UL);
+        spim_write(cmdBuf, sizeof (cmdBuf));
+        SPIM_SET_SS_EN(0);                      /* CS deactivated.  */
+    }
+
+    SPIM_ReadStatusRegister(status, sizeof (status), 1UL);
+    SPIM_DBGMSG("Status: 0x%x\n", status[0]);
+}
+
+
+static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit)
+{
+    uint8_t cmdBuf[2];
+    uint8_t dataBuf[1];
+
+    cmdBuf[0] = OPCODE_BRRD;
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, 1UL);
+    SwitchNBitInput(1UL);
+    spim_read(dataBuf, 1UL);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]);
+
+    cmdBuf[0] =  OPCODE_BRWR;
+
+    if (isEn) {
+        cmdBuf[1] = dataBuf[0] | 0x80U;          /* set EXTADD       */
+    } else {
+        cmdBuf[1] = dataBuf[0] & ~0x80U;         /* clear EXTADD     */
+    }
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SwitchNBitOutput(1UL);
+    spim_write(cmdBuf, 2UL);
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+/** @cond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Query 4-byte address mode enabled or not.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     0: 4-byte address mode disabled. 1: 4-byte address mode enabled.
+  */
+int SPIM_Is4ByteModeEnable(uint32_t u32NBit)
+{
+    int  isEn = 0;
+    int  isSupt = 0;
+    uint8_t  idBuf[3];
+    uint8_t  dataBuf[1];
+
+    SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+    /* Based on Flash size, check if 4-byte address mode is supported.  */
+    switch (idBuf[0]) {
+    case MFGID_WINBOND:
+    case MFGID_MXIC:
+    case MFGID_EON:
+        isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
+        break;
+
+    case MFGID_ISSI:
+        isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
+        break;
+
+    default:
+        break;
+    }
+
+    if (isSupt != 0) {
+        if (idBuf[0] == MFGID_WINBOND) {
+            /* Winbond SPI flash. */
+            SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit);
+            isEn = !! (dataBuf[0] & SR3_ADR);
+        } else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON)) {
+            /* MXIC/EON SPI flash. */
+            SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit);
+            isEn = !! (dataBuf[0] & SCUR_4BYTE);
+        }
+    }
+
+    return isEn;
+}
+
+/** @endcond HIDDEN_SYMBOLS  */
+
+
+/**
+  * @brief      Enter/Exit 4-byte address mode.
+  * @param      isEn        Enable/disable.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @return     0           success
+  *             -1          failed
+  */
+int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit)
+{
+    int  isSupt = 0L, ret = -1;
+    uint8_t idBuf[3];
+    uint8_t cmdBuf[1];                           /* 1-byte Enter/Exit 4-Byte Mode command. */
+
+    SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
+
+    /* Based on Flash size, check if 4-byte address mode is supported. */
+    switch (idBuf[0]) {
+    case MFGID_WINBOND:
+    case MFGID_MXIC:
+    case MFGID_EON:
+        isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
+        break;
+
+    case MFGID_ISSI:
+        isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
+        break;
+
+    case MFGID_SPANSION:
+        SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit);
+        isSupt = 1L;
+        ret = 0L;
+        break;
+
+    default:
+        break;
+    }
+
+    if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) {
+        cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B;
+
+        SPIM_SET_SS_EN(1);                      /* CS activated.    */
+        SwitchNBitOutput(u32NBit);
+        spim_write(cmdBuf, sizeof (cmdBuf));
+        SPIM_SET_SS_EN(0);                      /* CS deactivated.  */
+
+        /*
+         * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which
+         * doesn't match spec(MX25L25635E), so skip the check below.
+         */
+        if (idBuf[0] != MFGID_MXIC) {
+            if (isEn) {
+                while (! SPIM_Is4ByteModeEnable(u32NBit)) { }
+            } else {
+                while (SPIM_Is4ByteModeEnable(u32NBit)) { }
+            }
+        }
+        ret = 0;
+    }
+    return ret;
+}
+
+/**
+  * @brief      Erase whole chip.
+  * @param      u32NBit     N-bit transmit/receive.
+  * @param      isSync      Block or not.
+  * @return     None.
+  */
+void SPIM_ChipErase(uint32_t u32NBit, int isSync)
+{
+    uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE };    /* 1-byte Chip Erase command. */
+
+    spim_set_write_enable(1, u32NBit);           /* Write Enable.    */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, sizeof (cmdBuf));
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    if (isSync) {
+        spim_wait_write_done(u32NBit);
+    }
+}
+
+/**
+  * @brief      Erase one block.
+  * @param      u32Addr         Block to erase which contains the u32Addr.
+  * @param      is4ByteAddr     4-byte u32Address or not.
+  * @param      u8ErsCmd        Erase command.
+  * @param      u32NBit         N-bit transmit/receive.
+  * @param      isSync      Block or not.
+  * @return     None.
+  */
+void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync)
+{
+    uint8_t  cmdBuf[16];
+    uint32_t  buf_idx = 0UL;
+
+    spim_set_write_enable(1, u32NBit);           /* Write Enable.    */
+
+    cmdBuf[buf_idx++] = u8ErsCmd;
+
+    if (is4ByteAddr) {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
+    } else {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
+    }
+
+    SPIM_SET_SS_EN(1);                      /* CS activated.    */
+    SwitchNBitOutput(u32NBit);
+    spim_write(cmdBuf, buf_idx);
+    SPIM_SET_SS_EN(0);                      /* CS deactivated.  */
+
+    if (isSync) {
+        spim_wait_write_done(u32NBit);
+    }
+}
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Write data in the same page by I/O mode.
+  * @param      u32Addr     Start u32Address to write.
+  * @param      is4ByteAddr 4-byte u32Address or not.
+  * @param      u32NTx      Number of bytes to write.
+  * @param      pu8TxBuf    Transmit buffer.
+  * @param      wrCmd       Write command.
+  * @param      u32NBitCmd  N-bit transmit command.
+  * @param      u32NBitAddr N-bit transmit u32Address.
+  * @param      u32NBitDat  N-bit transmit/receive data.
+  * @param      isSync      Block or not.
+  * @return     None.
+  */
+static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+                                     uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync)
+{
+    uint8_t   cmdBuf[16];
+    uint32_t  buf_idx;
+
+    spim_set_write_enable(1, u32NBitCmd);        /* Write Enable.    */
+
+    SPIM_SET_SS_EN(1);                          /* CS activated.    */
+
+    SwitchNBitOutput(u32NBitCmd);
+    cmdBuf[0] = wrCmd;
+    spim_write(cmdBuf, 1UL);                     /* Write out command. */
+
+    buf_idx = 0UL;
+    if (is4ByteAddr) {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+    } else {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+    }
+
+    SwitchNBitOutput(u32NBitAddr);
+    spim_write(cmdBuf, buf_idx);                 /* Write out u32Address. */
+
+    SwitchNBitOutput(u32NBitDat);
+    spim_write(pu8TxBuf, u32NTx);                /* Write out data.  */
+
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+
+    if (isSync) {
+        spim_wait_write_done(u32NBitCmd);
+    }
+}
+
+/**
+  * @brief      Write data in the same page by Page Write mode.
+  * @param      u32Addr     Start u32Address to write.
+  * @param      is4ByteAddr 4-byte u32Address or not.
+  * @param      u32NTx      Number of bytes to write.
+  * @param      pu8TxBuf    Transmit buffer.
+  * @param      wrCmd       Write command.
+  * @param      isSync      Block or not.
+  * @return     None.
+  */
+static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx,
+        uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync)
+{
+    if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) ||
+            (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC)) {
+        SPIM_SetQuadEnable(1, 1UL);              /* Set Quad Enable. */
+    } else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) {
+        SPIM_SetQuadEnable(1, 1UL);              /* Set Quad Enable. */
+        spim_eon_set_qpi_mode(1);                /* Enter QPI mode.  */
+    }
+
+    SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode.   */
+    SPIM_SET_SPIM_MODE(wrCmd);                  /* SPIM mode.       */
+    SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr);        /* Enable/disable 4-Byte Address.  */
+
+    SPIM->SRAMADDR = (uint32_t) pu8TxBuf;        /* SRAM u32Address. */
+    SPIM->DMACNT = u32NTx;                       /* Transfer length. */
+    SPIM->FADDR = u32Addr;                       /* Flash u32Address.*/
+    SPIM_SET_GO();                              /* Go.              */
+
+    if (isSync) {
+        SPIM_WAIT_FREE();
+    }
+
+    if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) {
+        spim_eon_set_qpi_mode(0);                /* Exit QPI mode.   */
+    }
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Write data to SPI Flash by sending commands manually (I/O mode).
+  * @param      u32Addr: Start u32Address to write.
+  * @param      is4ByteAddr: 4-byte u32Address or not.
+  * @param      u32NTx: Number of bytes to write.
+  * @param      pu8TxBuf: Transmit buffer.
+  * @param      wrCmd: Write command.
+  * @param      u32NBitCmd: N-bit transmit command.
+  * @param      u32NBitAddr: N-bit transmit u32Address.
+  * @param      u32NBitDat: N-bit transmit/receive data.
+  * @return     None.
+  */
+void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
+                   uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat)
+{
+    uint32_t  pageOffset, toWr;
+    uint32_t  buf_idx = 0UL;
+
+    pageOffset = u32Addr % 256UL;
+
+    if ((pageOffset + u32NTx) <= 256UL) {        /* Do all the bytes fit onto one page ? */
+        SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx],
+                                 wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+    } else {
+        toWr = 256UL - pageOffset;               /* Size of data remaining on the first page. */
+
+        SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
+                                 wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+        u32Addr += toWr;                         /* Advance indicator.  */
+        u32NTx -= toWr;
+        buf_idx += toWr;
+
+        while (u32NTx) {
+            toWr = 256UL;
+            if (toWr > u32NTx) {
+                toWr = u32NTx;
+            }
+
+            SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
+                                     wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
+            u32Addr += toWr;                 /* Advance indicator.  */
+            u32NTx -= toWr;
+            buf_idx += toWr;
+        }
+    }
+}
+
+/**
+  * @brief      Read data from SPI Flash by sending commands manually (I/O mode).
+  * @param      u32Addr     Start u32Address to read.
+  * @param      is4ByteAddr 4-byte u32Address or not.
+  * @param      u32NRx      Number of bytes to read.
+  * @param      pu8RxBuf    Receive buffer.
+  * @param      rdCmd       Read command.
+  * @param      u32NBitCmd  N-bit transmit command.
+  * @param      u32NBitAddr N-bit transmit u32Address.
+  * @param      u32NBitDat  N-bit transmit/receive data.
+  * @param      u32NDummy   Number of dummy bytes following address.
+  * @return     None.
+  */
+void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd,
+                  uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy)
+{
+    uint8_t   cmdBuf[16];
+    uint32_t  buf_idx;
+
+    SPIM_SET_SS_EN(1);                      /* CS activated.    */
+
+    cmdBuf[0] = rdCmd;
+    SwitchNBitOutput(u32NBitCmd);
+    spim_write(cmdBuf, 1UL);                 /* Write out command. */
+
+    buf_idx = 0UL;
+    if (is4ByteAddr) {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+    } else {
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
+        cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
+        cmdBuf[buf_idx++] = (uint8_t) u32Addr;
+    }
+    SwitchNBitOutput(u32NBitAddr);
+    spim_write(cmdBuf, buf_idx);                 /* Write out u32Address. */
+
+    buf_idx = 0UL;
+    while (u32NDummy --) {
+        cmdBuf[buf_idx++] = 0x00U;
+    }
+
+    /* Same bit mode as above. */
+    spim_write(cmdBuf, buf_idx);                 /* Write out dummy bytes. */
+
+    SwitchNBitInput(u32NBitDat);
+    spim_read(pu8RxBuf, u32NRx);                 /* Read back data.  */
+
+    SPIM_SET_SS_EN(0);                          /* CS deactivated.  */
+}
+
+/**
+  * @brief      Write data to SPI Flash by Page Write mode.
+  * @param      u32Addr     Start address to write.
+  * @param      is4ByteAddr 4-byte address or not.
+  * @param      u32NTx      Number of bytes to write.
+  * @param      pu8TxBuf    Transmit buffer.
+  * @param      wrCmd       Write command.
+  * @return     None.
+  */
+void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd)
+{
+    uint32_t   pageOffset, toWr;
+    uint32_t   buf_idx = 0UL;
+
+    pageOffset = u32Addr % 256UL;
+
+    if ((pageOffset + u32NTx) <= 256UL) {
+        /* Do all the bytes fit onto one page ? */
+        SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1);
+    } else {
+        toWr = 256UL - pageOffset;               /* Size of data remaining on the first page. */
+
+        SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
+
+        u32Addr += toWr;                         /* Advance indicator. */
+        u32NTx -= toWr;
+        buf_idx += toWr;
+
+        while (u32NTx) {
+            toWr = 256UL;
+            if (toWr > u32NTx) {
+                toWr = u32NTx;
+            }
+
+            SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
+
+            u32Addr += toWr;                 /* Advance indicator. */
+            u32NTx -= toWr;
+            buf_idx += toWr;
+        }
+    }
+}
+
+/**
+  * @brief      Read data from SPI Flash by Page Read mode.
+  * @param      u32Addr     Start address to read.
+  * @param      is4ByteAddr 4-byte u32Address or not.
+  * @param      u32NRx      Number of bytes to read.
+  * @param      pu8RxBuf    Receive buffer.
+  * @param      u32RdCmd    Read command.
+  * @param      isSync      Block or not.
+  * @return     None.
+  */
+void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[],
+                   uint32_t u32RdCmd, int isSync)
+{
+    SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */
+    SPIM_SET_SPIM_MODE(u32RdCmd);               /* SPIM mode.       */
+    SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr);        /* Enable/disable 4-Byte Address. */
+
+    SPIM->SRAMADDR = (uint32_t) pu8RxBuf;        /* SRAM u32Address. */
+    SPIM->DMACNT = u32NRx;                       /* Transfer length. */
+    SPIM->FADDR = u32Addr;                       /* Flash u32Address.*/
+    SPIM_SET_GO();                              /* Go.              */
+
+    if (isSync) {
+        SPIM_WAIT_FREE();                       /* Wait for DMA done.  */
+    }
+}
+
+/**
+  * @brief      Enter Direct Map mode.
+  * @param      is4ByteAddr     4-byte u32Address or not.
+  * @param      u32RdCmd        Read command.
+  * @param      u32IdleIntvl    Idle interval.
+  * @return     None.
+  */
+void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl)
+{
+    SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr);        /* Enable/disable 4-byte u32Address. */
+    SPIM_SET_SPIM_MODE(u32RdCmd);               /* SPIM mode.       */
+    SPIM_SET_IDL_INTVL(u32IdleIntvl);            /* Idle interval.   */
+    SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP);   /* Switch to Direct Map mode.     */
+}
+
+/**
+  * @brief      Exit Direct Map mode.
+  * @return     None.
+  */
+void SPIM_ExitDirectMapMode(void)
+{
+    SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO);       /* Switch back to Normal mode.  */
+}
+
+
+/*@}*/ /* end of group M480_SPIM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SPIM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,630 @@
+/**************************************************************************//**
+ * @file    spim.h
+ * @version V1.00
+ * @brief   M480 series SPIM driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SPIM_H__
+#define __SPIM_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SPIM_Driver SPIM Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SPIM_EXPORTED_CONSTANTS SPIM Exported Constants
+  @{
+*/
+
+#define SPIM_DMM_MAP_ADDR      0x8000000UL       /*!< DMM mode memory map base address    \hideinitializer */
+#define SPIM_DMM_SIZE          0x2000000UL       /*!< DMM mode memory mapping size        \hideinitializer */
+#define SPIM_CCM_ADDR          0x20020000UL      /*!< CCM mode memory map base address    \hideinitializer */
+#define SPIM_CCM_SIZE          0x8000UL          /*!< CCM mode memory size                \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SPIM_CTL0 constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SPIM_CTL0_RW_IN(x)              ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos))      /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */
+#define SPIM_CTL0_BITMODE_SING          (0UL << SPIM_CTL0_BITMODE_Pos)          /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */
+#define SPIM_CTL0_BITMODE_DUAL          (1UL << SPIM_CTL0_BITMODE_Pos)          /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */
+#define SPIM_CTL0_BITMODE_QUAD          (2UL << SPIM_CTL0_BITMODE_Pos)          /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */
+#define SPIM_CTL0_OPMODE_IO             (0UL << SPIM_CTL0_OPMODE_Pos)           /*!< SPIM_CTL0: I/O Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_PAGEWRITE      (1UL << SPIM_CTL0_OPMODE_Pos)           /*!< SPIM_CTL0: Page Write Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_PAGEREAD       (2UL << SPIM_CTL0_OPMODE_Pos)           /*!< SPIM_CTL0: Page Read Mode \hideinitializer */
+#define SPIM_CTL0_OPMODE_DIRECTMAP      (3UL << SPIM_CTL0_OPMODE_Pos)           /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */
+
+#define CMD_NORMAL_PAGE_PROGRAM         (0x02UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */
+#define CMD_NORMAL_PAGE_PROGRAM_4B      (0x12UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_WINBOND   (0x32UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_MXIC      (0x38UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */
+#define CMD_QUAD_PAGE_PROGRAM_EON       (0x40UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */
+
+#define CMD_DMA_NORMAL_READ             (0x03UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ               (0x0BUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_NORMAL_DUAL_READ        (0x3BUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ_DUAL_OUTPUT   (0x3BUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_READ_QUAD_OUTPUT   (0x6BUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_DUAL_READ          (0xBBUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_NORMAL_QUAD_READ        (0xE7UL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
+#define CMD_DMA_FAST_QUAD_READ          (0xEBUL << SPIM_CTL0_CMDCODE_Pos)       /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
+
+/** @cond HIDDEN_SYMBOLS */
+
+typedef enum {
+    MFGID_UNKNOW    = 0x00U,
+    MFGID_SPANSION  = 0x01U,
+    MFGID_EON       = 0x1CU,
+    MFGID_ISSI      = 0x7FU,
+    MFGID_MXIC      = 0xC2U,
+    MFGID_WINBOND   = 0xEFU
+}
+E_MFGID;
+
+/* Flash opcodes. */
+#define OPCODE_WREN             0x06U   /* Write enable */
+#define OPCODE_RDSR             0x05U   /* Read status register #1*/
+#define OPCODE_WRSR             0x01U   /* Write status register #1 */
+#define OPCODE_RDSR2            0x35U   /* Read status register #2*/
+#define OPCODE_WRSR2            0x31U   /* Write status register #2 */
+#define OPCODE_RDSR3            0x15U   /* Read status register #3*/
+#define OPCODE_WRSR3            0x11U   /* Write status register #3 */
+#define OPCODE_PP               0x02U   /* Page program (up to 256 bytes) */
+#define OPCODE_SE_4K            0x20U   /* Erase 4KB sector */
+#define OPCODE_BE_32K           0x52U   /* Erase 32KB block */
+#define OPCODE_CHIP_ERASE       0xc7U   /* Erase whole flash chip */
+#define OPCODE_BE_64K           0xd8U   /* Erase 64KB block */
+#define OPCODE_READ_ID          0x90U   /* Read ID */
+#define OPCODE_RDID             0x9fU   /* Read JEDEC ID */
+#define OPCODE_BRRD             0x16U   /* SPANSION flash - Bank Register Read command  */
+#define OPCODE_BRWR             0x17U   /* SPANSION flash - Bank Register write command */
+#define OPCODE_NORM_READ        0x03U   /* Read data bytes */
+#define OPCODE_FAST_READ        0x0bU   /* Read data bytes */
+#define OPCODE_FAST_DUAL_READ   0x3bU   /* Read data bytes */
+#define OPCODE_FAST_QUAD_READ   0x6bU   /* Read data bytes */
+
+/* Used for SST flashes only. */
+#define OPCODE_BP               0x02U   /* Byte program */
+#define OPCODE_WRDI             0x04U   /* Write disable */
+#define OPCODE_AAI_WP           0xadU   /* Auto u32Address increment word program */
+
+/* Used for Macronix flashes only. */
+#define OPCODE_EN4B             0xb7U   /* Enter 4-byte mode */
+#define OPCODE_EX4B             0xe9U   /* Exit 4-byte mode */
+
+#define OPCODE_RDSCUR           0x2bU
+#define OPCODE_WRSCUR           0x2fU
+
+#define OPCODE_RSTEN            0x66U
+#define OPCODE_RST              0x99U
+
+#define OPCODE_ENQPI            0x38U
+#define OPCODE_EXQPI            0xFFU
+
+/* Status Register bits. */
+#define SR_WIP                  0x1U    /* Write in progress */
+#define SR_WEL                  0x2U    /* Write enable latch */
+#define SR_QE                   0x40U   /* Quad Enable for MXIC */
+/* Status Register #2 bits. */
+#define SR2_QE                  0x2U    /* Quad Enable for Winbond */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0                  0x4U    /* Block protect 0 */
+#define SR_BP1                  0x8U    /* Block protect 1 */
+#define SR_BP2                  0x10U   /* Block protect 2 */
+#define SR_SRWD                 0x80U   /* SR write protect */
+#define SR3_ADR                 0x01U   /* 4-byte u32Address mode */
+
+#define SCUR_4BYTE              0x04U   /* 4-byte u32Address mode */
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group M480_SPIM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+ * @details    Enable cipher.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CIPHER()       (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk)
+
+/**
+ * @details    Disable cipher.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CIPHER()      (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk)
+
+/**
+ * @details    Enable cipher balance
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_BALEN()        (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk)
+
+/**
+ * @details    Disable cipher balance
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_BALEN()       (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk)
+
+/**
+ * @details    Set 4-byte address to be enabled/disabled.
+ * \hideinitializer
+ */
+#define SPIM_SET_4BYTE_ADDR_EN(x) \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \
+    } while (0)
+
+/**
+ * @details    Enable SPIM interrupt
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_INT()       (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk)
+
+/**
+ * @details    Disable SPIM interrupt
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_INT()      (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk)
+
+/**
+ * @details    Is interrupt flag on.
+ * \hideinitializer
+ */
+#define SPIM_IS_IF_ON()    ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL)
+
+/**
+ * @details    Clear interrupt flag.
+ * \hideinitializer
+ */
+#define SPIM_CLR_INT() \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos);  \
+    } while (0)
+
+/**
+ * @details    Set transmit/receive bit length
+ * \hideinitializer
+ */
+#define SPIM_SET_DATA_WIDTH(x)   \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos);  \
+    } while (0)
+
+/**
+ * @details    Get data transmit/receive bit length setting
+ * \hideinitializer
+ */
+#define SPIM_GET_DATA_WIDTH()   \
+    (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U)
+
+/**
+ * @details    Set data transmit/receive burst number
+ * \hideinitializer
+ */
+#define SPIM_SET_DATA_NUM(x) \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos);  \
+    } while (0)
+
+/**
+ * @details    Get data transmit/receive burst number
+ * \hideinitializer
+ */
+#define SPIM_GET_DATA_NUM() \
+    (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U)
+
+/**
+ * @details    Enable Single Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_SING_INPUT_MODE()  \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1));    \
+    } while (0)
+
+/**
+ * @details    Enable Single Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_SING_OUTPUT_MODE() \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0));    \
+    } while (0)
+
+/**
+ * @details    Enable Dual Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_DUAL_INPUT_MODE()  \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U));    \
+    } while (0)
+
+/**
+ * @details    Enable Dual Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U));    \
+    } while (0)
+
+/**
+ * @details    Enable Quad Input mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_QUAD_INPUT_MODE()  \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U));    \
+    } while (0)
+
+/**
+ * @details    Enable Quad Output mode.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U));    \
+    } while (0)
+
+/**
+ * @details    Set suspend interval which ranges between 0 and 15.
+ * \hideinitializer
+ */
+#define SPIM_SET_SUSP_INTVL(x) \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos);    \
+    } while (0)
+
+/**
+ * @details    Get suspend interval setting
+ * \hideinitializer
+ */
+#define SPIM_GET_SUSP_INTVL() \
+    ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos)
+
+/**
+ * @details    Set operation mode.
+ * \hideinitializer
+ */
+#define SPIM_SET_OPMODE(x)  \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \
+    } while (0)
+
+/**
+ * @details    Get operation mode.
+ * \hideinitializer
+ */
+#define SPIM_GET_OP_MODE()         (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk)
+
+/**
+ * @details    Set SPIM mode.
+ * \hideinitializer
+ */
+#define SPIM_SET_SPIM_MODE(x)    \
+    do {    \
+        SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x);   \
+    } while (0)
+
+/**
+ * @details    Get SPIM mode.
+ * \hideinitializer
+ */
+#define SPIM_GET_SPIM_MODE()       (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk)
+
+/**
+ * @details    Start operation.
+ * \hideinitializer
+ */
+#define SPIM_SET_GO()              (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk)
+
+/**
+ * @details    Is engine busy.
+ * \hideinitializer
+ */
+#define SPIM_IS_BUSY()             (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk)
+
+/**
+ * @details    Wait for free.
+ * \hideinitializer
+ */
+#define SPIM_WAIT_FREE()   \
+    do {    \
+        while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { }   \
+    } while (0)
+
+/**
+ * @details    Enable cache.
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CACHE()        (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk)
+
+/**
+ * @details    Disable cache.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CACHE()       (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk)
+
+/**
+ * @details    Is cache enabled.
+ * \hideinitializer
+ */
+#define SPIM_IS_CACHE_EN()         ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1)
+
+/**
+ * @details    Enable CCM
+ * \hideinitializer
+ */
+#define SPIM_ENABLE_CCM()          (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk)
+
+/**
+ * @details    Disable CCM.
+ * \hideinitializer
+ */
+#define SPIM_DISABLE_CCM()         (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk)
+
+/**
+ * @details    Is CCM enabled.
+ * \hideinitializer
+ */
+#define SPIM_IS_CCM_EN()           ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos)
+
+/**
+ * @details    Invalidate cache.
+ * \hideinitializer
+ */
+#define SPIM_INVALID_CACHE()       (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk)
+
+/**
+ * @details    Set SS(Select Active) to active level.
+ * \hideinitializer
+ */
+#define SPIM_SET_SS_EN(x) \
+    do {    \
+        (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) |  ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \
+    } while (0)
+
+/**
+ * @details    Is SS(Select Active) in active level.
+ * \hideinitializer
+ */
+#define SPIM_GET_SS_EN() \
+    (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk))
+
+/**
+ * @details    Set active level of slave select to be high/low.
+ * \hideinitializer
+ */
+#define SPIM_SET_SS_ACTLVL(x) \
+    do {    \
+        (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos));   \
+    } while (0)
+
+/**
+ * @details    Set idle time interval
+ * \hideinitializer
+ */
+#define SPIM_SET_IDL_INTVL(x) \
+    do {    \
+       SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos);  \
+    } while (0)
+
+/**
+ * @details    Get idle time interval setting
+ * \hideinitializer
+ */
+#define SPIM_GET_IDL_INTVL() \
+    ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos)
+
+/**
+ * @details    Set SPIM clock divider
+ * \hideinitializer
+ */
+#define SPIM_SET_CLOCK_DIVIDER(x)    \
+    do {    \
+       SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos);    \
+    } while (0)
+
+/**
+ * @details    Get SPIM current clock divider setting
+ * \hideinitializer
+ */
+#define SPIM_GET_CLOCK_DIVIDER()   \
+    ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos)
+
+/**
+ * @details    Set SPI flash deselect time interval of DMA write mode
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \
+    do {    \
+        (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) |  ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \
+    } while (0)
+
+/**
+ * @details    Get SPI flash deselect time interval of DMA write mode
+ * \hideinitializer
+ */
+#define SPIM_GET_RXCLKDLY_DWDELSEL() \
+    ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos)
+
+/**
+ * @details    Set sampling clock delay selection for received data
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \
+    do {    \
+        (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) |  ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \
+    } while (0)
+
+/**
+ * @details    Get sampling clock delay selection for received data
+ * \hideinitializer
+ */
+#define SPIM_GET_RXCLKDLY_RDDLYSEL() \
+    ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos)
+
+/**
+ * @details    Set sampling clock edge selection for received data
+ * \hideinitializer
+ */
+#define SPIM_SET_RXCLKDLY_RDEDGE() \
+    (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \
+
+/**
+ * @details    Get sampling clock edge selection for received data
+ * \hideinitializer
+ */
+#define SPIM_CLR_RXCLKDLY_RDEDGE() \
+    (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk)
+
+/**
+ * @details    Set mode bits data for continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_SET_DMMCTL_CRMDAT(x) \
+    do {    \
+        (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) |  ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \
+    } while (0)
+
+/**
+ * @details    Get mode bits data for continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_GET_DMMCTL_CRMDAT() \
+    ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos)
+
+/**
+ * @details    Set DMM mode SPI flash deselect time
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_DESELTIM(x) \
+    do {    \
+        SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos);   \
+    } while (0)
+
+/**
+ * @details    Get current DMM mode SPI flash deselect time setting
+ * \hideinitializer
+ */
+#define SPIM_DMM_GET_DESELTIM() \
+        ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos)
+
+/**
+ * @details    Enable DMM mode burst wrap mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_ENABLE_BWEN()         (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk)
+
+/**
+ * @details    Disable DMM mode burst wrap mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_DISABLE_BWEN()        (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk)
+
+/**
+ * @details    Enable DMM mode continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_ENABLE_CREN()         (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk)
+
+/**
+ * @details    Disable DMM mode continuous read mode
+ * \hideinitializer
+ */
+#define SPIM_DMM_DISABLE_CREN()        (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk)
+
+/**
+ * @details    Set DMM mode SPI flash active SCLK time
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_ACTSCLKT(x) \
+    do {    \
+        SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk;   \
+    } while (0)
+
+/**
+ * @details    Set SPI flash active SCLK time as SPIM default
+ * \hideinitializer
+ */
+#define SPIM_DMM_SET_DEFAULT_ACTSCLK()     (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk)
+
+/**
+ * @details    Set dummy cycle number (Only for DMM mode and DMA mode)
+ * \hideinitializer
+ */
+#define SPIM_SET_DCNUM(x) \
+    do {    \
+        SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk;   \
+    } while (0)
+
+/**
+ * @details    Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default
+ * \hideinitializer
+ */
+#define SPIM_SET_DEFAULT_DCNUM(x)           (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Function Prototypes                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+int  SPIM_InitFlash(int clrWP);
+uint32_t SPIM_GetSClkFreq(void);
+void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit);
+int  SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit);
+int  SPIM_Is4ByteModeEnable(uint32_t u32NBit);
+
+void SPIM_ChipErase(uint32_t u32NBit, int isSync);
+void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync);
+
+void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat);
+void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy);
+
+void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd);
+void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync);
+
+void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl);
+void SPIM_ExitDirectMapMode(void);
+
+void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit);
+
+/*@}*/ /* end of group M480_SPIM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SPIM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SPIM_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,245 @@
+/**************************************************************************//**
+ * @file     sys.c
+ * @version  V1.00
+ * $Revision: 1 $
+ * $Date: 16/06/14 10:32a $
+ * @brief    M480 series SYS driver source file
+ *
+ * @note
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M480.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SYS_Driver SYS Driver
+  @{
+*/
+
+
+/** @addtogroup M480_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear reset source
+  * @param[in]  u32Src is system reset source. Including :
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  * @return     None
+  * @details    This function clear the selected system reset source.
+  */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+    SYS->RSTSTS |= u32Src;
+}
+
+/**
+  * @brief      Get Brown-out detector output status
+  * @param      None
+  * @retval     0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
+  * @retval     1 System voltage is lower than BOD_VL setting.
+  * @details    This function get Brown-out detector output status.
+  */
+uint32_t SYS_GetBODStatus(void)
+{
+    return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+  * @brief      Get reset status register value
+  * @param      None
+  * @return     Reset source
+  * @details    This function get the system reset status register value.
+  */
+uint32_t SYS_GetResetSrc(void)
+{
+    return (SYS->RSTSTS);
+}
+
+/**
+  * @brief      Check if register is locked nor not
+  * @param      None
+  * @retval     0 Write-protection function is disabled.
+  *             1 Write-protection function is enabled.
+  * @details    This function check register write-protection bit setting.
+  */
+uint32_t SYS_IsRegLocked(void)
+{
+    return SYS->REGLCTL & 1UL ? 0UL : 1UL;
+}
+
+/**
+  * @brief      Get product ID
+  * @param      None
+  * @return     Product ID
+  * @details    This function get product ID.
+  */
+uint32_t  SYS_ReadPDID(void)
+{
+    return SYS->PDID;
+}
+
+/**
+  * @brief      Reset chip with chip reset
+  * @param      None
+  * @return     None
+  * @details    This function reset chip with chip reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetChip(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+  * @brief      Reset chip with CPU reset
+  * @param      None
+  * @return     None
+  * @details    This function reset CPU with CPU reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetCPU(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+  * @brief      Reset selected module
+  * @param[in]  u32ModuleIndex is module index. Including :
+  *             - \ref PDMA_RST
+  *             - \ref EBI_RST
+  *             - \ref EMAC_RST
+  *             - \ref SDH0_RST
+  *             - \ref CRC_RST
+  *             - \ref HSUSBD_RST
+  *             - \ref CRPT_RST
+  *             - \ref SPIM_RST
+  *             - \ref USBH_RST
+  *             - \ref SDH1_RST
+  *             - \ref GPIO_RST
+  *             - \ref TMR0_RST
+  *             - \ref TMR1_RST
+  *             - \ref TMR2_RST
+  *             - \ref TMR3_RST
+  *             - \ref ACMP01_RST
+  *             - \ref I2C0_RST
+  *             - \ref I2C1_RST
+  *             - \ref I2C2_RST
+  *             - \ref SPI0_RST
+  *             - \ref SPI1_RST
+  *             - \ref SPI2_RST
+  *             - \ref SPI3_RST
+  *             - \ref UART0_RST
+  *             - \ref UART1_RST
+  *             - \ref UART2_RST
+  *             - \ref UART3_RST
+  *             - \ref UART4_RST
+  *             - \ref UART5_RST
+  *             - \ref CAN0_RST
+  *             - \ref CAN1_RST
+  *             - \ref USBD_RST
+  *             - \ref EADC_RST
+  *             - \ref I2S0_RST
+  *             - \ref SC0_RST
+  *             - \ref SC1_RST
+  *             - \ref SC2_RST
+  *             - \ref SPI4_RST
+  *             - \ref USCI0_RST
+  *             - \ref USCI1_RST
+  *             - \ref DAC_RST
+  *             - \ref EPWM0_RST
+  *             - \ref EPWM1_RST
+  *             - \ref BPWM0_RST
+  *             - \ref BPWM1_RST
+  *             - \ref QEI0_RST
+  *             - \ref QEI1_RST
+  *             - \ref ECAP0_RST
+  *             - \ref ECAP1_RST
+  *             - \ref OPA_RST
+  * @return     None
+  * @details    This function reset selected module.
+  */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+    uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+
+    /* Generate reset signal to the corresponding module */
+    u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));
+    u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));
+    *(uint32_t *)u32tmpAddr |= u32tmpVal;
+
+    /* Release corresponding module from reset state */
+    u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
+    *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+/**
+  * @brief      Enable and configure Brown-out detector function
+  * @param[in]  i32Mode is reset or interrupt mode. Including :
+  *             - \ref SYS_BODCTL_BOD_RST_EN
+  *             - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+  * @param[in]  u32BODLevel is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_3_0V
+  *             - \ref SYS_BODCTL_BODVL_2_8V
+  *             - \ref SYS_BODCTL_BODVL_2_6V
+  *             - \ref SYS_BODCTL_BODVL_2_4V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  *             - \ref SYS_BODCTL_BODVL_2_0V
+  *             - \ref SYS_BODCTL_BODVL_1_8V
+  *             - \ref SYS_BODCTL_BODVL_1_6V
+  * @return     None
+  * @details    This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+    /* Enable Brown-out Detector function */
+    SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
+
+    /* Enable Brown-out interrupt or reset function */
+    SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode;
+
+    /* Select Brown-out Detector threshold voltage */
+    SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
+}
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This function disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_DisableBOD(void)
+{
+    SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+
+
+/*@}*/ /* end of group M480_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SYS_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1488 @@
+/**************************************************************************//**
+ * @file     SYS.h
+ * @version  V3.0
+ * @brief    M480 Series SYS Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+#ifndef __SYS_H__
+#define __SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_SYS_Driver SYS Driver
+  @{
+*/
+
+/** @addtogroup M480_SYS_EXPORTED_CONSTANTS SYS Exported Constants
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Module Reset Control Resister constant definitions.                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_RST            ((0UL<<24) | SYS_IPRST0_PDMARST_Pos)        /*!< Reset PDMA \hideinitializer*/
+#define EBI_RST             ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)         /*!< Reset EBI \hideinitializer*/
+#define EMAC_RST            ((0UL<<24) | SYS_IPRST0_EMACRST_Pos)        /*!< Reset EMAC \hideinitializer */
+#define SDH0_RST            ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos)        /*!< Reset SDH0 \hideinitializer */
+#define CRC_RST             ((0UL<<24) | SYS_IPRST0_CRCRST_Pos)         /*!< Reset CRC \hideinitializer */
+#define HSUSBD_RST          ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos)      /*!< Reset HSUSBD \hideinitializer */
+#define CRPT_RST            ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos)        /*!< Reset CRPT \hideinitializer */
+#define SPIM_RST            ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos)        /*!< Reset SPIM \hideinitializer */
+#define USBH_RST            ((0UL<<24) | SYS_IPRST0_USBHRST_Pos)        /*!< Reset USBH \hideinitializer */
+#define SDH1_RST            ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos)        /*!< Reset SDH1 \hideinitializer */
+
+#define GPIO_RST            ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)        /*!< Reset GPIO \hideinitializer */
+#define TMR0_RST            ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)        /*!< Reset TMR0 \hideinitializer */
+#define TMR1_RST            ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)        /*!< Reset TMR1 \hideinitializer */
+#define TMR2_RST            ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)        /*!< Reset TMR2 \hideinitializer */
+#define TMR3_RST            ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)        /*!< Reset TMR3 \hideinitializer */
+#define ACMP01_RST          ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)      /*!< Reset ACMP01 \hideinitializer */
+#define I2C0_RST            ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)        /*!< Reset I2C0 \hideinitializer */
+#define I2C1_RST            ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)        /*!< Reset I2C1 \hideinitializer */
+#define I2C2_RST            ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos)        /*!< Reset I2C2 \hideinitializer */
+#define SPI0_RST            ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos)        /*!< Reset SPI0 \hideinitializer */
+#define SPI1_RST            ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos)        /*!< Reset SPI1 \hideinitializer */
+#define SPI2_RST            ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos)        /*!< Reset SPI2 \hideinitializer */
+#define SPI3_RST            ((4UL<<24) | SYS_IPRST1_SPI3RST_Pos)        /*!< Reset SPI3 \hideinitializer */
+#define UART0_RST           ((4UL<<24) | SYS_IPRST1_UART0RST_Pos)       /*!< Reset UART0 \hideinitializer */
+#define UART1_RST           ((4UL<<24) | SYS_IPRST1_UART1RST_Pos)       /*!< Reset UART1 \hideinitializer */
+#define UART2_RST           ((4UL<<24) | SYS_IPRST1_UART2RST_Pos)       /*!< Reset UART2 \hideinitializer */
+#define UART3_RST           ((4UL<<24) | SYS_IPRST1_UART3RST_Pos)       /*!< Reset UART3 \hideinitializer */
+#define UART4_RST           ((4UL<<24) | SYS_IPRST1_UART4RST_Pos)       /*!< Reset UART4 \hideinitializer */
+#define UART5_RST           ((4UL<<24) | SYS_IPRST1_UART5RST_Pos)       /*!< Reset UART5 \hideinitializer */
+#define CAN0_RST            ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos)        /*!< Reset CAN0 \hideinitializer */
+#define CAN1_RST            ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos)        /*!< Reset CAN1 \hideinitializer */
+#define USBD_RST            ((4UL<<24) | SYS_IPRST1_USBDRST_Pos)        /*!< Reset USBD \hideinitializer */
+#define EADC_RST            ((4UL<<24) | SYS_IPRST1_EADCRST_Pos)        /*!< Reset EADC \hideinitializer */
+#define I2S0_RST            ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos)        /*!< Reset I2S0 \hideinitializer */
+
+#define SC0_RST             ((8UL<<24) | SYS_IPRST2_SC0RST_Pos)         /*!< Reset SC0 \hideinitializer */
+#define SC1_RST             ((8UL<<24) | SYS_IPRST2_SC1RST_Pos)         /*!< Reset SC1 \hideinitializer */
+#define SC2_RST             ((8UL<<24) | SYS_IPRST2_SC2RST_Pos)         /*!< Reset SC2 \hideinitializer */
+#define SPI4_RST            ((8UL<<24) | SYS_IPRST2_SPI4RST_Pos)        /*!< Reset SPI4 \hideinitializer */
+#define USCI0_RST           ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos)       /*!< Reset USCI0 \hideinitializer */
+#define USCI1_RST           ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos)       /*!< Reset USCI1 \hideinitializer */
+#define DAC_RST             ((8UL<<24) | SYS_IPRST2_DACRST_Pos)         /*!< Reset DAC \hideinitializer */
+#define EPWM0_RST           ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos)       /*!< Reset EPWM0 \hideinitializer */
+#define EPWM1_RST           ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos)       /*!< Reset EPWM1 \hideinitializer */
+#define BPWM0_RST           ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos)       /*!< Reset BPWM0 \hideinitializer */
+#define BPWM1_RST           ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos)       /*!< Reset BPWM1 \hideinitializer */
+#define QEI0_RST            ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos)        /*!< Reset QEI0 \hideinitializer */
+#define QEI1_RST            ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos)        /*!< Reset QEI1 \hideinitializer */
+#define ECAP0_RST           ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos)       /*!< Reset ECAP0 \hideinitializer */
+#define ECAP1_RST           ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos)       /*!< Reset ECAP1 \hideinitializer */
+#define OPA_RST             ((8UL<<24) | SYS_IPRST2_OPARST_Pos)         /*!< Reset OPA \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brown Out Detector Threshold Voltage Selection constant definitions.                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN           (1UL << SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Reset Enable \hideinitializer */
+#define SYS_BODCTL_BOD_INTERRUPT_EN     (0UL << SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Interrupt Enable \hideinitializer */
+#define SYS_BODCTL_BODVL_3_0V           (7UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_8V           (6UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_6V           (5UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_4V           (4UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_2V           (3UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_0V           (2UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_8V           (1UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_6V           (0UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  VREFCTL constant definitions. (Write-Protection Register)                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_VREFCTL_VREF_PIN        (0x0UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = Vref pin \hideinitializer */
+#define SYS_VREFCTL_VREF_1_6V       (0x3UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 1.6V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_0V       (0x7UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 2.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_5V       (0xBUL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 2.5V \hideinitializer */
+#define SYS_VREFCTL_VREF_3_0V       (0xFUL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 3.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_AVDD       (0x10UL << SYS_VREFCTL_VREFCTL_Pos)   /*!< Vref = AVDD \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USBPHY constant definitions. (Write-Protection Register)                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_USBPHY_USBROLE_STD_USBD   (0x0UL << SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB device \hideinitializer */
+#define SYS_USBPHY_USBROLE_STD_USBH   (0x1UL << SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB host \hideinitializer */
+#define SYS_USBPHY_USBROLE_ID_DEPH    (0x2UL << SYS_USBPHY_USBROLE_Pos)   /*!<  ID dependent device \hideinitializer */
+#define SYS_USBPHY_USBROLE_ON_THE_GO  (0x3UL << SYS_USBPHY_USBROLE_Pos)   /*!<  On-The-Go device \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Multi-Function constant definitions.                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+/* How to use below #define?
+Example 1: If user want to set PA.0 as SC0_CLK in initial function,
+           user can issue following command to achieve it.
+
+           SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK  ;
+
+*/
+/********************* Bit definition of GPA_MFPL register **********************/
+#define SYS_GPA_MFPL_PA0MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI         (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI0        (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SPI1_MOSI         (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SD1_DAT0          (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SC0_CLK           (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_UART0_RXD         (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_UART1_nRTS        (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_I2C2_SDA          (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0         (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5         (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_DAC0_ST           (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< DAC0 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SPIM_MISO         (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SPI0_MISO0        (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SPI1_MISO         (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SD1_DAT1          (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SC0_DAT           (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_UART0_TXD         (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_UART1_nCTS        (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_I2C2_SCL          (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1         (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4         (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_DAC1_ST           (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< DAC1 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SPIM_CLK          (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SPI0_CLK          (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SPI1_CLK          (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SD1_DAT2          (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SC0_RST           (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_UART4_RXD         (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_UART1_RXD         (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_I2C1_SDA          (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2         (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3         (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPIM_SS           (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPI0_SS           (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPI1_SS           (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SD1_DAT3          (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SC0_PWR           (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_UART4_TXD         (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_UART1_TXD         (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_I2C1_SCL          (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3         (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2         (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_QEI0_B            (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SPIM_D3           (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SPI0_MOSI1        (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SPI1_I2SMCLK      (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SD1_CLK           (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SC0_nCD           (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_UART0_nRTS        (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_UART5_RXD         (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_I2C0_SDA          (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_CAN0_RXD          (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4         (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1         (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_QEI0_A            (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SPIM_D2           (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SPI0_MISO1        (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SPI2_I2SMCLK      (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SD1_CMD           (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SC2_nCD           (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_UART0_nCTS        (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_UART5_TXD         (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_I2C0_SCL          (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_CAN0_TXD          (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5         (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0         (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX        (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EBI_AD6           (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< EBI address/data bus bit6. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR    (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< RMII Receive Data error. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SPI2_SS           (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SD1_nCD           (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< SD/SDIO 1 card detect  \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SC2_CLK           (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_UART0_RXD         (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_I2C1_SDA          (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5         (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3         (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT        (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Analog comparator1 window latch input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_TM3               (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_INT0              (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< External interrupt0 input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EBI_AD7           (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< EBI address/data bus bit7. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV     (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_SPI2_CLK          (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_SC2_DAT           (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_UART0_TXD         (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_I2C1_SCL          (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4         (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2         (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT        (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Analog comparator0 window latch input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_TM2               (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_INT1              (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< External interrupt1 input pin. \hideinitializer */
+/********************* Bit definition of GPA_MFPH register **********************/
+#define SYS_GPA_MFPH_PA8MFP_GPIO              (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_OPA1_P            (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_EBI_ALE           (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< EBI address latch enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SC2_CLK           (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SPI3_MOSI         (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SD1_DAT0          (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1        (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_UART1_RXD         (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3         (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_QEI1_B            (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2         (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_TM3_EXT           (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_INT4              (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< External interrupt4 input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_GPIO              (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_OPA1_N            (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_EBI_MCLK          (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< EBI external clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SC2_DAT           (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SPI3_MISO         (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SD1_DAT1          (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1        (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_UART1_TXD         (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2         (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_QEI1_A            (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1         (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_TM2_EXT           (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SWDH_DAT          (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SWD Host interface input/output bus bit. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_ACMP1_P0         (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_OPA1_O           (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_EBI_nWR          (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SC2_RST          (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SPI3_CLK         (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SD1_DAT2         (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0       (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_I2C2_SDA         (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1        (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX       (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0        (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_TM1_EXT          (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_DAC0_ST          (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SWDH_CLK         (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SWD Host interface clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_ACMP0_P0         (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_EBI_nRD          (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SC2_PWR          (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SPI3_SS          (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SD1_DAT3         (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_USCI0_CLK        (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL         (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0        (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT   (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_TM0_EXT          (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_DAC1_ST          (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK        (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_UART4_TXD        (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_I2C1_SCL         (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_SPI3_SS          (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD         (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_SC2_PWR          (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2        (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX       (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_USB_VBUS         (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK        (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_UART4_RXD        (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_I2C1_SDA         (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_SPI3_CLK         (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD         (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_SC2_RST          (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3        (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_QEI1_A           (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_USB_D_N          (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< USB Full speed differential signal D-. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_I2S0_DI          (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_UART0_TXD        (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_SPI3_MISO        (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_I2C2_SCL         (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_SC2_DAT          (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4        (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_QEI1_B           (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_USB_D_P          (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< USB Full speed differential signal D+. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_I2S0_DO          (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_UART0_RXD        (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_SPI3_MOSI        (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_I2C2_SDA         (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_SC2_CLK          (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5        (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN    (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID       (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< USB Full speed identification. \hideinitializer */
+/********************* Bit definition of GPB_MFPL register **********************/
+#define SYS_GPB_MFPL_PB0MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0         (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EADC0 channel0 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_OPA0_P            (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9          (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_SD0_CMD           (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< SD/SDIO 0 command/response. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_UART2_RXD         (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_SPI1_I2SMCLK      (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA          (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5         (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5         (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1      (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Brake input pin 1 of EPWM0. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EADC0_CH1         (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_OPA0_N            (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EBI_ADR8          (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SD0_CLK           (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SD/SDIO 0 clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR    (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< RMII Receive Data error. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SPI2_I2SMCLK      (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SPI4_I2SMCLK      (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SPI4 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_UART2_TXD         (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_USCI1_CLK         (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_I2C1_SCL          (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK         (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4         (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4         (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0      (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Brake input pin 0 of EPWM0. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_ACMP0_P1          (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EADC0_CH2         (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EADC0 channel2 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_OPA0_O            (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EBI_ADR3          (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SD0_DAT0          (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV     (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SPI2_SS           (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_UART1_RXD         (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_UART5_nCTS        (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Clear to Send input pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0        (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SC0_PWR           (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_I2S0_DO           (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3         (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_TM3               (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_INT3              (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< External interrupt3 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_ACMP0_N           (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Analog comparator0 negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EADC0_CH3         (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EADC0 channel3 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EBI_ADR2          (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SD0_DAT1          (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1     (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< RMII Receive Data bus bit 1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SPI2_CLK          (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_UART1_TXD         (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_UART5_nRTS        (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Request to Send output pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1        (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SC0_RST           (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_I2S0_DI           (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2         (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_TM2               (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_INT2              (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< External interrupt2 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_ACMP1_P1          (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EADC0_CH4         (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EADC0 channel4 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EBI_ADR1          (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SD0_DAT2          (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0     (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< RMII Receive Data bus bit 0. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SPI2_MOSI         (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_I2C0_SDA          (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_UART5_RXD         (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1        (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SC0_DAT           (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK         (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1         (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_TM1               (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_INT1              (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< External interrupt1 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_ACMP1_N           (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Analog comparator1 negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EADC0_CH5         (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EADC0 channel5 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EBI_ADR0          (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SD0_DAT3          (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK       (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EMAC mode clock input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SPI2_MISO         (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_I2C0_SCL          (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_UART5_TXD         (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0        (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SC0_CLK           (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK         (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0         (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_TM0               (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_INT0              (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< External interrupt0 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EADC0_CH6         (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EADC0 channel6 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EBI_nWRH          (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EMAC_PPS          (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EMAC Pulse Per Second output  \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1        (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_CAN1_RXD          (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_UART1_RXD         (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_SD1_CLK           (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EBI_nCS1          (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5         (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1      (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Brake input pin 1 of EPWM1. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5         (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_INT4              (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< External interrupt4 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN       (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_ACMP1_O           (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EADC0_CH7         (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EADC0 channel7 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EBI_nWRL          (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN     (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< RMII? Transmit Enable. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0        (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_CAN1_TXD          (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_UART1_TXD         (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_SD1_CMD           (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EBI_nCS0          (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4         (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0      (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Brake input pin 0 of EPWM1. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4         (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_INT5              (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< External interrupt5 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST       (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_ACMP0_O           (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Analog comparator0 output. \hideinitializer */
+/********************* Bit definition of GPB_MFPH register **********************/
+#define SYS_GPB_MFPH_PB8MFP_GPIO              (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EADC0_CH8         (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< EADC0 channel8 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EBI_ADR19         (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1     (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< RMII Transmit Data bus bit 1. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_USCI1_CLK         (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_UART0_RXD         (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS        (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS       (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3         (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_SPI4_MOSI         (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_INT6              (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< External interrupt6 input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_GPIO              (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EADC0_CH9         (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< EADC0 channel9 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EBI_ADR18         (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0     (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< RMII Transmit Data bus bit 0. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1        (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_UART0_TXD         (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_UART1_nCTS        (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL        (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin   \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2         (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_SPI4_MISO         (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_INT7              (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< External interrupt7 input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EADC0_CH10       (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EBI_ADR17        (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO    (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0       (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_UART0_nRTS       (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_UART4_RXD        (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_I2C1_SDA         (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_CAN0_RXD         (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1        (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_SPI4_SS          (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI4 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN    (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EADC0_CH11       (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EBI_ADR16        (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC     (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_UART0_nCTS       (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_UART4_TXD        (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_I2C1_SCL         (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_CAN0_TXD         (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_SPI1_I2SMCLK     (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0        (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_SPI4_CLK         (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST    (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ACMP0_P2         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ACMP1_P2         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_DAC0_OUT         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< DAC0 channel analog output. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EADC0_CH12       (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EBI_AD15         (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SC1_CLK          (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SPI1_MOSI        (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_USCI0_CLK        (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_UART0_RXD        (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_UART3_nCTS       (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_I2C2_SDA         (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SD0_nCD          (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SD/SDIO 0 card detect  \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3        (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3  (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_TM3_EXT          (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Timer3 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ACMP0_P3         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ACMP1_P3         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_DAC1_OUT         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< DAC1 channel analog output. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EADC0_CH13       (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EBI_AD14         (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_SC1_DAT          (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_SPI1_MISO        (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0       (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_UART0_TXD        (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_UART3_nRTS       (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_I2C2_SCL         (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2        (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2  (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_TM2_EXT          (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EADC0_CH14       (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EBI_AD13         (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_SC1_RST          (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_SPI1_CLK         (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1       (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_UART0_nRTS       (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_UART3_RXD        (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS      (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1        (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1  (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_TM1_EXT          (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_CLKO             (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EADC0_CH15       (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EBI_AD12         (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_SC1_PWR          (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_SPI1_SS          (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1       (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_UART0_nCTS       (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_UART3_TXD        (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL       (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< I2C2 SMBus SMBALTER# pin   \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0        (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0  (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_TM0_EXT          (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Timer0 event counter input / toggle output  \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN      (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN    (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+/********************* Bit definition of GPC_MFPL register **********************/
+#define SYS_GPC_MFPL_PC0MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_EBI_AD0           (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< EBI address/data bus bit0. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI         (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SPI0_MOSI0        (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SC1_CLK           (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK         (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SPI2_SS           (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_UART2_RXD         (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA          (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5         (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_ACMP1_O           (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_EBI_AD1           (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SPIM_MISO         (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SPI0_MISO0        (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SC1_DAT           (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_I2S0_DO           (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SPI2_CLK          (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_UART2_TXD         (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL          (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4         (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_ACMP0_O           (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< Analog comparator0 output. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_EBI_AD2           (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< EBI address/data bus bit2. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SPIM_CLK          (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SPI0_CLK          (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SC1_RST           (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_I2S0_DI           (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SPI2_MOSI         (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_UART2_nCTS        (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS       (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_CAN1_RXD          (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_UART3_RXD         (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3         (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_EBI_AD3           (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< EBI address/data bus bit3. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SPIM_SS           (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SPI0_SS           (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SC1_PWR           (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK         (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SPI2_MISO         (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_UART2_nRTS        (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL        (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< I2C0 SMBus SMBALTER# pin  \hideinitializer  */
+#define SYS_GPC_MFPL_PC3MFP_CAN1_TXD          (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_UART3_TXD         (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2         (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_EBI_AD4           (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< EBI address/data bus bit4. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPIM_D3           (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1        (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SC1_nCD           (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK         (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPI2_I2SMCLK      (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_UART2_RXD         (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_I2C1_SDA          (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD          (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_UART4_RXD         (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1         (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_EBI_AD5           (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< EBI address/data bus bit5. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_SPIM_D2           (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_SPI0_MISO1        (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_UART2_TXD         (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_I2C1_SCL          (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD          (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_UART4_TXD         (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0         (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EBI_AD8           (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< EBI address/data bus bit8. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1     (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< RMII Receive Data bus bit 1. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_SPI2_MOSI         (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_UART4_RXD         (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_SC2_RST           (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_UART0_nRTS        (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS       (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3         (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1         (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_TM1               (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_INT2              (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< External interrupt2 input pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_EBI_AD9           (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< EBI address/data bus bit9. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0     (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< RMII Receive Data bus bit 0. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_SPI2_MISO         (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_UART4_TXD         (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_SC2_PWR           (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_UART0_nCTS        (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL        (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer  */
+#define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2         (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0         (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_TM0               (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_INT3              (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< External interrupt3 input pin. \hideinitializer */
+/********************* Bit definition of GPC_MFPH register **********************/
+#define SYS_GPC_MFPH_PC8MFP_GPIO              (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EBI_ADR16         (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK       (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EMAC mode clock input. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_I2C0_SDA          (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_UART4_nCTS        (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< Clear to Send input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_UART1_RXD         (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1         (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4         (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_GPIO              (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_EBI_ADR7          (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_SPI4_SS           (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< 1st SPI4 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_UART3_RXD         (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_CAN1_RXD          (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3         (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_EBI_ADR6         (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_SPI4_CLK         (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< SPI4 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_UART3_TXD        (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_CAN1_TXD         (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0        (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2        (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_EBI_ADR5         (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_UART0_RXD        (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_I2C0_SDA         (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_SPI4_MOSI        (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1        (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1        (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_ACMP1_O          (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_EBI_ADR4         (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_UART0_TXD        (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_I2C0_SCL         (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_SPI4_MISO        (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_SC0_nCD          (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2        (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0        (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_ACMP0_O          (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_EBI_ADR10        (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_SC2_nCD          (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_SPI3_I2SMCLK     (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_CAN1_TXD         (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0       (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_UART2_TXD        (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4        (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_CLKO             (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_EADC0_ST         (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_EBI_AD11         (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_SC1_nCD          (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_SPI1_I2SMCLK     (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0       (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_SPI0_CLK         (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN    (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK    (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_TM1              (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST      (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST    (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+/********************* Bit definition of GPD_MFPL register **********************/
+#define SYS_GPD_MFPL_PD0MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_EBI_AD13          (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_USCI0_CLK         (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_SPI1_MOSI         (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_UART3_RXD         (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_I2C2_SDA          (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_SC2_CLK           (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_TM2               (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_EBI_AD12          (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0        (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_SPI1_MISO         (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_UART3_TXD         (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_I2C2_SCL          (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_SC2_DAT           (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_EBI_AD11          (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1        (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_SPI1_CLK          (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_UART3_nCTS        (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_SC2_RST           (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_UART0_RXD         (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_EBI_AD10          (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1        (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SPI1_SS           (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_UART3_nRTS        (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0        (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SC2_PWR           (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SC1_nCD           (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_UART0_TXD         (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0        (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_I2C1_SDA          (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_SPI2_SS           (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1        (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_SC1_CLK           (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST       (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_I2C1_SCL          (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_SPI2_CLK          (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0        (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_SC1_DAT           (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_UART1_RXD         (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_I2C0_SDA          (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_SPI2_MOSI         (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1        (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_SC1_RST           (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_UART1_TXD         (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_I2C0_SCL          (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_SPI2_MISO         (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_USCI1_CLK         (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_SC1_PWR           (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
+/********************* Bit definition of GPD_MFPH register **********************/
+#define SYS_GPD_MFPH_PD8MFP_GPIO              (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_EBI_AD6           (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< EBI address/data bus bit6. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA          (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS        (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_GPIO              (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_EBI_AD7           (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< EBI address/data bus bit7. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_I2C2_SCL          (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_UART2_nCTS        (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_OPA2_P           (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_EBI_nCS2         (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_UART1_RXD        (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_CAN0_RXD         (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_QEI0_B           (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_INT7             (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_OPA2_N           (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_EBI_nCS1         (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_UART1_TXD        (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_CAN0_TXD         (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_QEI0_A           (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_INT6             (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_OPA2_O           (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_EBI_nCS0         (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_CAN1_RXD         (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_UART2_RXD        (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5        (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX       (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_CLKO             (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_EADC0_ST         (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_INT5             (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_EBI_AD10         (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SD0_nCD          (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SD/SDIO 0 card detect  \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK     (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SPI2_I2SMCLK     (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SC2_nCD          (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_EBI_nCS0         (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_SPI4_I2SMCLK     (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI4 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_SC1_nCD          (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4        (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+/********************* Bit definition of GPE_MFPL register **********************/
+#define SYS_GPE_MFPL_PE0MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_EBI_AD11          (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_SPI0_MOSI0        (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_SC2_CLK           (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK         (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_SPI2_MOSI         (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_UART3_RXD         (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA          (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_UART4_nRTS        (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< Request to Send output pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_EBI_AD10          (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_SPI0_MISO0        (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_SC2_DAT           (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK         (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_SPI2_MISO         (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_UART3_TXD         (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL          (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS        (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< Clear to Send input pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_EBI_ALE           (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< EBI address latch enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SD0_DAT0          (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI         (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SPI4_MOSI         (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SC0_CLK           (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK         (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_QEI0_B            (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5         (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0         (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_EBI_MCLK          (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< EBI external clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SD0_DAT1          (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SPIM_MISO         (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SPI4_MISO         (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SC0_DAT           (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0        (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_QEI0_A            (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4         (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1         (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_EBI_nWR           (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SD0_DAT2          (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SPIM_CLK          (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SPI4_CLK          (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SPI4 serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SC0_RST           (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1        (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX        (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3         (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2         (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_EBI_nRD           (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< EBI read enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SD0_DAT3          (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SPIM_SS           (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SPI4_SS           (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< 1st SPI4 slave select pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SC0_PWR           (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1        (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_QEI1_B            (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2         (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3         (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SD0_CLK           (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SD/SDIO 0 clock. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SPIM_D3           (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SPI4_I2SMCLK      (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SPI4 I2S master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SC0_nCD           (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0        (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_UART5_RXD         (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_CAN1_RXD          (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_QEI1_A            (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1         (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4         (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_SD0_CMD           (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< SD/SDIO 0 command/response. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_SPIM_D2           (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_UART5_TXD         (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_CAN1_TXD          (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX        (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0         (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5         (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+/********************* Bit definition of GPE_MFPH register **********************/
+#define SYS_GPE_MFPH_PE8MFP_GPIO              (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EBI_ADR10         (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC      (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< RMII Management Data Clock. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK         (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_SPI3_CLK          (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1        (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_UART2_TXD         (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0         (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0      (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Brake input pin 0 of EPWM0. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0         (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_TRACE_CLK         (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< ETM Rx clock input pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_GPIO              (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EBI_ADR11         (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO     (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< RMII Management Data I/O. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK         (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_SPI3_MISO         (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0        (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_UART2_RXD         (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1         (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1      (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Brake input pin 1 of EPWM0. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1         (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA0       (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< ETM Rx input bus bit0. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EBI_ADR12        (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0    (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_I2S0_DI          (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_SPI3_MOSI        (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0       (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_UART3_TXD        (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2        (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0     (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2        (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1      (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EBI_ADR13        (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1    (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_I2S0_DO          (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_SPI3_SS          (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1       (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_UART3_RXD        (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_UART1_nCTS       (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3        (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1     (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2        (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA2      (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EBI_ADR14        (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN    (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK        (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_SPI3_I2SMCLK     (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_USCI1_CLK        (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS       (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4        (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1        (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_TRACE_DATA3      (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EBI_ADR15        (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EMAC_PPS         (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EMAC Pulse Per Second output  \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_I2C0_SCL         (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_UART4_nRTS       (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_UART1_TXD        (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5        (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0        (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5        (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0        (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_EBI_AD8          (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_UART2_TXD        (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_CAN0_TXD         (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_SD1_nCD          (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< SD/SDIO 1 card detect  \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_EBI_AD9          (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_UART2_RXD        (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_CAN0_RXD         (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+/********************* Bit definition of GPF_MFPL register **********************/
+#define SYS_GPF_MFPL_PF0MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_UART1_TXD         (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_I2C1_SCL          (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0         (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_ICE_DAT           (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< Serial wired debugger data pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_UART1_RXD         (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_I2C1_SDA          (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1         (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_ICE_CLK           (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< Serial wired debugger clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_EBI_nCS1          (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_UART0_RXD         (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_I2C0_SDA          (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_SPI0_CLK          (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_XT1_OUT           (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< External 4~24 MHz (high speed) crystal output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1         (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_EBI_nCS0          (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_UART0_TXD         (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_I2C0_SCL          (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_XT1_IN            (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< External 4~24 MHz (high speed) crystal input pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0         (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_UART2_TXD         (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_UART2_nRTS        (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5         (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_X32_OUT           (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< External 32.768 kHz (low speed) crystal output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_UART2_RXD         (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_UART2_nCTS        (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4         (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT    (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_X32_IN            (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< External 32.768 kHz (low speed) crystal input pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_EADC0_ST          (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_EBI_ADR19         (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_SC0_CLK           (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK         (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_SPI1_MOSI         (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_UART4_RXD         (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_EBI_nCS0          (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_TAMPER0           (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< TAMPER detector loop pin0. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_EBI_ADR18         (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_SC0_DAT           (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_I2S0_DO           (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_SPI1_MISO         (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_UART4_TXD         (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_TAMPER1           (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< TAMPER detector loop pin1. \hideinitializer */
+/********************* Bit definition of GPF_MFPH register **********************/
+#define SYS_GPF_MFPH_PF8MFP_GPIO              (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_EBI_ADR17         (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_SC0_RST           (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_I2S0_DI           (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_SPI1_CLK          (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_TAMPER2           (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< TAMPER detector loop pin2. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_GPIO              (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_EBI_ADR16         (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_SC0_PWR           (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK         (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_SPI1_SS           (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_TAMPER3           (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< TAMPER detector loop pin3. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_GPIO             (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_EBI_ADR15        (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_SC0_nCD          (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK        (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_SPI1_I2SMCLK     (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_TAMPER4          (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< TAMPER detector loop pin4. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_GPIO             (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_EBI_ADR14        (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_SPI3_MOSI        (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_TAMPER5          (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< TAMPER detector loop pin5. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_TM3              (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Timer3 event counter input / toggle output  \hideinitializer */
+/********************* Bit definition of GPG_MFPL register **********************/
+#define SYS_GPG_MFPL_PG0MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_EBI_ADR8          (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_I2C0_SCL          (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL        (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer  */
+#define SYS_GPG_MFPL_PG0MFP_UART2_RXD         (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_CAN1_TXD          (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_UART1_TXD         (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_EBI_ADR9          (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_SPI3_I2SMCLK      (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_I2C0_SDA          (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS       (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_UART2_TXD         (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_CAN1_RXD          (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_UART1_RXD         (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_EBI_ADR11         (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_SPI3_SS           (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL        (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< I2C0 SMBus SMBALTER# pin  \hideinitializer  */
+#define SYS_GPG_MFPL_PG2MFP_I2C1_SCL          (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_TM0               (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_EBI_ADR12         (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_SPI3_CLK          (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS       (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_I2C1_SDA          (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_TM1               (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_EBI_ADR13         (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_SPI3_MISO         (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_TM2               (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< Timer2 event counter input / toggle output \hideinitializer  */
+#define SYS_GPG_MFPL_PG5MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_EBI_nCS1          (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_SPI4_SS           (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< 1st SPI4 slave select pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_SC1_PWR           (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3         (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_EBI_nCS2          (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_SPI4_CLK          (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< SPI4 serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_SC1_RST           (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2         (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_EBI_nWRL          (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_SPI4_MISO         (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< 1st SPI4 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_SC1_DAT           (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1         (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+/********************* Bit definition of GPG_MFPH register **********************/
+#define SYS_GPG_MFPH_PG8MFP_GPIO              (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_EBI_nWRH          (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_SPI4_MOSI         (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< 1st SPI4 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_SC1_CLK           (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0         (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_GPIO              (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_EBI_AD0           (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< EBI address/data bus bit0. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_SD1_DAT3          (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_SPIM_D2           (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5         (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_EBI_AD1          (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_SD1_DAT2         (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_SPIM_D3          (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4        (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_EBI_AD2          (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_SD1_DAT1         (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_SPIM_SS          (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3        (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_EBI_AD3          (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_SD1_DAT0         (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_SPIM_CLK         (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2        (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_EBI_AD4          (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_SD1_CMD          (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_SPIM_MISO        (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1        (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_EBI_AD5          (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_SD1_CLK          (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI        (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0        (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_SD1_nCD          (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< SD/SDIO 1 card detect  \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_CLKO             (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_EADC0_ST         (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+/********************* Bit definition of GPH_MFPL register **********************/
+#define SYS_GPH_MFPL_PH0MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_EBI_ADR7          (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_UART5_TXD         (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_TM0_EXT           (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_EBI_ADR6          (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_UART5_RXD         (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_TM1_EXT           (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_EBI_ADR5          (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_UART5_nRTS        (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Request to Send output pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_UART4_TXD         (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_I2C0_SCL          (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_TM2_EXT           (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_EBI_ADR4          (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_SPI2_I2SMCLK      (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_UART5_nCTS        (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Clear to Send input pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_UART4_RXD         (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_I2C0_SDA          (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_TM3_EXT           (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_EBI_ADR3          (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_SPI2_MISO         (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_EBI_ADR2          (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_SPI2_MOSI         (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_EBI_ADR1          (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_SPI2_CLK          (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_EBI_ADR0          (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_SPI2_SS           (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+/********************* Bit definition of GPH_MFPH register **********************/
+#define SYS_GPH_MFPH_PH8MFP_GPIO              (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_EBI_AD12          (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_SPI0_CLK          (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_SC2_PWR           (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_I2S0_DI           (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_SPI2_CLK          (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_UART3_nRTS        (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL        (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer  */
+#define SYS_GPH_MFPH_PH8MFP_I2C2_SCL          (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_UART1_TXD         (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_GPIO              (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_EBI_AD13          (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_SPI0_SS           (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_SC2_RST           (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2S0_DO           (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_SPI2_SS           (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_UART3_nCTS        (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS       (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2C2_SDA          (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_UART1_RXD         (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_GPIO             (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_EBI_AD14         (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_SPI0_MISO1       (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< 2nd SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_SC2_nCD          (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK        (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_SPI2_I2SMCLK     (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_UART4_TXD        (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_UART0_TXD        (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_GPIO             (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_EBI_AD15         (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_SPI0_MOSI1       (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< 2nd SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_UART4_RXD        (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_UART0_RXD        (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5        (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+
+/*@}*/ /* end of group M480_SYS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Clear Brown-out detector interrupt flag
+  * @param      None
+  * @return     None
+  * @details    This macro clear Brown-out detector interrupt flag.
+  * \hideinitializer
+  */
+#define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
+
+/**
+  * @brief      Set Brown-out detector function to normal mode
+  * @param      None
+  * @return     None
+  * @details    This macro set Brown-out detector to normal mode.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_CLEAR_BOD_LPM()             (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_DISABLE_BOD()               (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
+
+/**
+  * @brief      Enable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_ENABLE_BOD()                (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
+
+/**
+  * @brief      Get Brown-out detector interrupt flag
+  * @param      None
+  * @retval     0   Brown-out detect interrupt flag is not set.
+  * @retval     >=1 Brown-out detect interrupt flag is set.
+  * @details    This macro get Brown-out detector interrupt flag.
+  * \hideinitializer
+  */
+#define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+  * @brief      Get Brown-out detector status
+  * @param      None
+  * @retval     0   System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+  * @retval     >=1 System voltage is lower than BOD threshold voltage setting.
+  * @details    This macro get Brown-out detector output status.
+  *             If the BOD function is disabled, this function always return 0.
+  * \hideinitializer
+  */
+#define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+  * @brief      Enable Brown-out detector interrupt function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector interrupt function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_DISABLE_BOD_RST()           (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+  * @brief      Enable Brown-out detector reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detect reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_ENABLE_BOD_RST()            (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+  * @brief      Set Brown-out detector function low power mode
+  * @param      None
+  * @return     None
+  * @details    This macro set Brown-out detector to low power mode.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_SET_BOD_LPM()               (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
+
+/**
+  * @brief      Set Brown-out detector voltage level
+  * @param[in]  u32Level is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_3_0V
+  *             - \ref SYS_BODCTL_BODVL_2_8V
+  *             - \ref SYS_BODCTL_BODVL_2_6V
+  *             - \ref SYS_BODCTL_BODVL_2_4V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  *             - \ref SYS_BODCTL_BODVL_2_0V
+  *             - \ref SYS_BODCTL_BODVL_1_8V
+  *             - \ref SYS_BODCTL_BODVL_1_6V
+  * @return     None
+  * @details    This macro set Brown-out detector voltage level.
+  *             The write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_SET_BOD_LEVEL(u32Level)     (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
+
+/**
+  * @brief      Get reset source is from Brown-out detector reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Brown-out detector reset
+  * @retval     >=1 Previous reset source is from Brown-out detector reset
+  * @details    This macro get previous reset source is from Brown-out detect reset or not.
+  * \hideinitializer
+  */
+#define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+  * @brief      Get reset source is from CPU reset
+  * @param      None
+  * @retval     0   Previous reset source is not from CPU reset
+  * @retval     >=1 Previous reset source is from CPU reset
+  * @details    This macro get previous reset source is from CPU reset.
+  * \hideinitializer
+  */
+#define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+  * @brief      Get reset source is from LVR Reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Low-Voltage-Reset
+  * @retval     >=1 Previous reset source is from Low-Voltage-Reset
+  * @details    This macro get previous reset source is from Low-Voltage-Reset.
+  * \hideinitializer
+  */
+#define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+  * @brief      Get reset source is from Power-on Reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Power-on Reset
+  * @retval     >=1 Previous reset source is from Power-on Reset
+  * @details    This macro get previous reset source is from Power-on Reset.
+  * \hideinitializer
+  */
+#define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+  * @brief      Get reset source is from reset pin reset
+  * @param      None
+  * @retval     0   Previous reset source is not from reset pin reset
+  * @retval     >=1 Previous reset source is from reset pin reset
+  * @details    This macro get previous reset source is from reset pin reset.
+  * \hideinitializer
+  */
+#define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+  * @brief      Get reset source is from system reset
+  * @param      None
+  * @retval     0   Previous reset source is not from system reset
+  * @retval     >=1 Previous reset source is from system reset
+  * @details    This macro get previous reset source is from system reset.
+  * \hideinitializer
+  */
+#define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+  * @brief      Get reset source is from window watch dog reset
+  * @param      None
+  * @retval     0   Previous reset source is not from window watch dog reset
+  * @retval     >=1 Previous reset source is from window watch dog reset
+  * @details    This macro get previous reset source is from window watch dog reset.
+  * \hideinitializer
+  */
+#define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+  * @brief      Disable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_DISABLE_LVR()               (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
+
+/**
+  * @brief      Enable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_ENABLE_LVR()                (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
+
+/**
+  * @brief      Disable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_DISABLE_POR()               (SYS->PORCTL = 0x5AA5)
+
+/**
+  * @brief      Enable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  * \hideinitializer
+  */
+#define SYS_ENABLE_POR()                (SYS->PORCTL = 0)
+
+/**
+  * @brief      Clear reset source flag
+  * @param[in]  u32RstSrc is reset source. Including :
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  * @return     None
+  * @details    This macro clear reset source flag.
+  * \hideinitializer
+  */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void SYS_UnlockReg(void);
+static __INLINE void SYS_LockReg(void);
+
+/**
+  * @brief      Disable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function disable register write-protection function.
+  *             To unlock the protected register to allow write access.
+  */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+    do {
+        SYS->REGLCTL = 0x59UL;
+        SYS->REGLCTL = 0x16UL;
+        SYS->REGLCTL = 0x88UL;
+    } while(SYS->REGLCTL == 0UL);
+}
+
+/**
+  * @brief      Enable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function is used to enable register write-protection function.
+  *             To lock the protected register to forbid write access.
+  */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+    SYS->REGLCTL = 0UL;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+
+
+/*@}*/ /* end of group M480_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_SYS_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __SYS_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_timer.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,351 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @brief    M480 Timer Controller(Timer) driver source file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open Timer with Operate Mode and Frequency
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Mode     Operation mode. Possible options are
+  *                         - \ref TIMER_ONESHOT_MODE
+  *                         - \ref TIMER_PERIODIC_MODE
+  *                         - \ref TIMER_TOGGLE_MODE
+  *                         - \ref TIMER_CONTINUOUS_MODE
+  * @param[in]  u32Freq     Target working frequency
+  *
+  * @return     Real timer working frequency
+  *
+  * @details    This API is used to configure timer to operate in specified mode and frequency.
+  *             If timer cannot work in target frequency, a closest frequency will be chose and returned.
+  * @note       After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+  *             \ref TIMER_Start macro or program registers directly.
+  */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(timer);
+    uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;
+
+    /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */
+    if(u32Freq > (u32Clk / 2UL)) {
+        u32Cmpr = 2UL;
+    } else {
+        if(u32Clk > 128000000UL) {
+            u32Prescale = 15UL;    /* real prescaler value is 16 */
+            u32Clk >>= 4;
+        } else if(u32Clk > 64000000UL) {
+            u32Prescale = 7UL;    /* real prescaler value is 8 */
+            u32Clk >>= 3;
+        } else if(u32Clk > 32000000UL) {
+            u32Prescale = 3UL;    /* real prescaler value is 4 */
+            u32Clk >>= 2;
+        } else if(u32Clk > 16000000UL) {
+            u32Prescale = 1UL;    /* real prescaler value is 2 */
+            u32Clk >>= 1;
+        }
+
+        u32Cmpr = u32Clk / u32Freq;
+    }
+
+    timer->CTL = u32Mode | u32Prescale;
+    timer->CMP = u32Cmpr;
+
+    return(u32Clk / (u32Cmpr * (u32Prescale + 1UL)));
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API stops timer counting and disable all timer interrupt function.
+  */
+void TIMER_Close(TIMER_T *timer)
+{
+    timer->CTL = 0UL;
+    timer->EXTCTL = 0UL;
+}
+
+/**
+  * @brief      Create a specify Delay Time
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Usec     Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+  *
+  * @return     None
+  *
+  * @details    This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
+  * @note       This API overwrites the register setting of the timer used to count the delay time.
+  * @note       This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+  */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(timer);
+    uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL;
+    uint32_t u32Cmpr, u32NsecPerTick;
+
+    /* Clear current timer configuration */
+    timer->CTL = 0UL;
+    timer->EXTCTL = 0UL;
+
+    if(u32Clk <= 1000000UL) { /* min delay is 1000 us if timer clock source is <= 1 MHz */
+        if(u32Usec < 1000UL) {
+            u32Usec = 1000UL;
+        }
+        if(u32Usec > 1000000UL) {
+            u32Usec = 1000000UL;
+        }
+    } else {
+        if(u32Usec < 100UL) {
+            u32Usec = 100UL;
+        }
+        if(u32Usec > 1000000UL) {
+            u32Usec = 1000000UL;
+        }
+    }
+
+    if(u32Clk <= 1000000UL) {
+        u32Prescale = 0UL;
+        u32NsecPerTick = 1000000000UL / u32Clk;
+        u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
+    } else {
+        if(u32Clk > 128000000UL) {
+            u32Prescale = 15UL;    /* real prescaler value is 16 */
+            u32Clk >>= 4;
+        } else if(u32Clk > 64000000UL) {
+            u32Prescale = 7UL;    /* real prescaler value is 8 */
+            u32Clk >>= 3;
+        } else if(u32Clk > 32000000UL) {
+            u32Prescale = 3UL;    /* real prescaler value is 4 */
+            u32Clk >>= 2;
+        } else if(u32Clk > 16000000UL) {
+            u32Prescale = 1UL;    /* real prescaler value is 2 */
+            u32Clk >>= 1;
+        }
+
+        if(u32Usec < 250UL) {
+            u32Cmpr = (u32Usec * u32Clk) / 1000000UL;
+        } else {
+            u32NsecPerTick = 1000000000UL / u32Clk;
+            u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
+        }
+    }
+
+    timer->CMP = u32Cmpr;
+    timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
+
+    /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+       And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */
+    for(; delay > 0UL; delay--) {
+        __NOP();
+    }
+
+    while(timer->CTL & TIMER_CTL_ACTSTS_Msk) {
+        ;
+    }
+}
+
+/**
+  * @brief      Enable Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CapMode  Timer capture mode. Could be
+  *                         - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+  *                         - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+  * @param[in]  u32Edge     Timer capture trigger edge. Possible values are
+  *                         - \ref TIMER_CAPTURE_EVENT_FALLING
+  *                         - \ref TIMER_CAPTURE_EVENT_RISING
+  *                         - \ref TIMER_CAPTURE_EVENT_FALLING_RISING
+  *                         - \ref TIMER_CAPTURE_EVENT_RISING_FALLING
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable timer capture function with specify capture trigger edge \n
+  *             to get current counter value or reset counter value to 0.
+  * @note       Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+  */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+    timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
+                    u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Capture Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer capture function.
+  */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Counter Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Edge     Detection edge of counter pin. Could be ether
+  *                         - \ref TIMER_COUNTER_EVENT_FALLING, or
+  *                         - \ref TIMER_COUNTER_EVENT_RISING
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer counter function with specify detection edge.
+  * @note       Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+  * @note       While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+  */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+    timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
+    timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Counter Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer event counter function.
+  */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Clock Frequency
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     Timer clock frequency
+  *
+  * @details    This API is used to get the timer clock frequency.
+  * @note       This API cannot return correct clock rate if timer source is from external clock input.
+  */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+    uint32_t u32Src, u32Clk;
+    const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};
+
+    if(timer == TIMER0) {
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
+    } else if(timer == TIMER1) {
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
+    } else if(timer == TIMER2) {
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
+    } else {  /* Timer 3 */
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
+    }
+
+    if(u32Src == 2UL) {
+        if((timer == TIMER0) || (timer == TIMER1)) {
+            u32Clk = CLK_GetPCLK0Freq();
+        } else {
+            u32Clk = CLK_GetPCLK1Freq();
+        }
+    } else {
+        u32Clk = au32Clk[u32Src];
+    }
+
+    return u32Clk;
+}
+
+
+
+/**
+  * @brief This function is used to enable the Timer frequency counter function
+  * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2
+  * @param[in] u32DropCount This parameter has no effect in M480 series BSP
+  * @param[in] u32Timeout This parameter has no effect in M480 series BSP
+  * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
+  * @return None
+  * @details This function is used to calculate input event frequency. After enable
+  *          this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3
+  *          will be configured for this function. The mode used to calculate input
+  *          event frequency is mentioned as "Inter Timer Trigger Mode" in Technical
+  *          Reference Manual
+  */
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+                             uint32_t u32DropCount,
+                             uint32_t u32Timeout,
+                             uint32_t u32EnableInt)
+{
+    TIMER_T *t;    /* store the timer base to configure compare value */
+
+    t = (timer == TIMER0) ? TIMER1 : TIMER3;
+
+    t->CMP = 0xFFFFFFUL;
+    t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL;
+    timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
+
+    return;
+}
+/**
+  * @brief This function is used to disable the Timer frequency counter function.
+  * @param[in] timer The base address of Timer module
+  * @return None
+  */
+void TIMER_DisableFreqCounter(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
+}
+
+
+/**
+  * @brief This function is used to select the interrupt source used to trigger other modules.
+  * @param[in] timer The base address of Timer module
+  * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:
+  *              - \ref TIMER_TRGSRC_TIMEOUT_EVENT
+  *              - \ref TIMER_TRGSRC_CAPTURE_EVENT
+  * @return None
+  */
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
+{
+    timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;
+}
+
+/**
+  * @brief This function is used to set modules trigger by timer interrupt
+  * @param[in] timer The base address of Timer module
+  * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of
+  *             - \ref TIMER_TRG_TO_EPWM,
+  *             - \ref TIMER_TRG_TO_EADC,
+  *             - \ref TIMER_TRG_TO_DAC, and
+  *             - \ref TIMER_TRG_TO_PDMA
+  * @return None
+  */
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
+{
+    timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;
+}
+
+/*@}*/ /* end of group M480_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_TIMER_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_timer.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,506 @@
+/**************************************************************************//**
+ * @file     timer.h
+ * @version  V1.00
+ * @brief    M480 series Timer Controller(Timer) driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  TIMER Operation Mode, External Counter and Capture Mode Constant Definitions                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TIMER_ONESHOT_MODE                      (0UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in one-shot mode \hideinitializer */
+#define TIMER_PERIODIC_MODE                     (1UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in periodic mode \hideinitializer */
+#define TIMER_TOGGLE_MODE                       (2UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in toggle-output mode \hideinitializer */
+#define TIMER_CONTINUOUS_MODE                   (3UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in continuous counting mode \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX                 (0UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from TMx pin \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX_EXT             (1UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */
+
+#define TIMER_COUNTER_EVENT_FALLING             (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */
+#define TIMER_COUNTER_EVENT_RISING              (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE        (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE        (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */
+
+#define TIMER_CAPTURE_EVENT_FALLING             (0UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Falling edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING              (1UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Rising edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_FALLING_RISING      (2UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING_FALLING      (3UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD      (6UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD     (7UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */
+
+#define TIMER_TRGSRC_TIMEOUT_EVENT              (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */
+#define TIMER_TRGSRC_CAPTURE_EVENT              (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */
+#define TIMER_TRG_TO_EPWM                       (TIMER_TRGCTL_TRGEPWM_Msk)        /*!< Each timer event as EPWM counter clock source \hideinitializer */
+#define TIMER_TRG_TO_EADC                       (TIMER_TRGCTL_TRGEADC_Msk)        /*!< Each timer event to start ADC conversion \hideinitializer */
+#define TIMER_TRG_TO_DAC                        (TIMER_TRGCTL_TRGDAC_Msk)         /*!< Each timer event to start DAC conversion \hideinitializer */
+#define TIMER_TRG_TO_PDMA                       (TIMER_TRGCTL_TRGPDMA_Msk)        /*!< Each timer event to trigger PDMA transfer \hideinitializer */
+
+/*@}*/ /* end of group M480_TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set Timer Compared Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Value    Timer compare value. Valid values are between 2 to 0xFFFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer compared value to adjust timer time-out interval.
+  * @note       1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
+  *             2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
+  *                But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
+  * \hideinitializer
+  */
+#define TIMER_SET_CMP_VALUE(timer, u32Value)        ((timer)->CMP = (u32Value))
+
+/**
+  * @brief      Set Timer Prescale Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Value    Timer prescale value. Valid values are between 0 to 0xFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
+  *             before it is fed into timer.
+  * \hideinitializer
+  */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value)   ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
+
+/**
+  * @brief      Check specify Timer Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer 24-bit up counter is inactive
+  * @retval     1   Timer 24-bit up counter is active
+  *
+  * @details    This macro is used to check if specify Timer counter is inactive or active.
+  * \hideinitializer
+  */
+#define TIMER_IS_ACTIVE(timer)                      (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
+
+/**
+  * @brief      Select Toggle-output Pin
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32ToutSel  Toggle-output pin selection, valid values are:
+  *                         - \ref TIMER_TOUT_PIN_FROM_TMX
+  *                         - \ref TIMER_TOUT_PIN_FROM_TMX_EXT
+  *
+  * @return     None
+  *
+  * @details    This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin.
+  * \hideinitializer
+  */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel)    ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void TIMER_Start(TIMER_T *timer);
+static __INLINE void TIMER_Stop(TIMER_T *timer);
+static __INLINE void TIMER_EnableWakeup(TIMER_T *timer);
+static __INLINE void TIMER_DisableWakeup(TIMER_T *timer);
+static __INLINE void TIMER_StartCapture(TIMER_T *timer);
+static __INLINE void TIMER_StopCapture(TIMER_T *timer);
+static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer);
+static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer);
+static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer);
+static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer);
+static __INLINE void TIMER_EnableInt(TIMER_T *timer);
+static __INLINE void TIMER_DisableInt(TIMER_T *timer);
+static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer);
+static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer);
+static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer);
+static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer);
+static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer);
+static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer);
+static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer);
+static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer);
+static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer);
+static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer);
+static __INLINE void TIMER_ResetCounter(TIMER_T *timer);
+
+/**
+  * @brief      Start Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to start Timer counting.
+  */
+static __INLINE void TIMER_Start(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to stop/suspend Timer counting.
+  */
+static __INLINE void TIMER_Stop(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Interrupt Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
+  *             counter event interrupt or capture trigger interrupt.
+  * @note       To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+  */
+static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer interrupt wake-up function.
+  */
+static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Start Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to start Timer capture function.
+  */
+static __INLINE void TIMER_StartCapture(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Stop Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to stop Timer capture function.
+  */
+static __INLINE void TIMER_StopCapture(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of capture pin.
+  */
+static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of capture pin.
+  */
+static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of counter pin.
+  */
+static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of counter pin.
+  */
+static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer time-out interrupt function.
+  */
+static __INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer time-out interrupt function.
+  */
+static __INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer capture trigger interrupt function.
+  */
+static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer capture trigger interrupt function.
+  */
+static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer time-out interrupt did not occur
+  * @retval     1   Timer time-out interrupt occurred
+  *
+  * @details    This function indicates timer time-out interrupt occurred or not.
+  */
+static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+    return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer time-out interrupt flag to 0.
+  */
+static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+    timer->INTSTS = TIMER_INTSTS_TIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer capture interrupt did not occur
+  * @retval     1   Timer capture interrupt occurred
+  *
+  * @details    This function indicates timer capture trigger interrupt occurred or not.
+  */
+static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+    return timer->EINTSTS;
+}
+
+/**
+  * @brief      Clear Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer capture trigger interrupt flag to 0.
+  */
+static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+    timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Wake-up Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer does not cause CPU wake-up
+  * @retval     1   Timer interrupt event cause CPU wake-up
+  *
+  * @details    This function indicates timer interrupt event has waked up system or not.
+  */
+static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+    return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Timer Wake-up Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears the timer wake-up system flag to 0.
+  */
+static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+    timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
+}
+
+/**
+  * @brief      Get Capture value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     24-bit Capture Value
+  *
+  * @details    This function reports the current 24-bit timer capture value.
+  */
+static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+    return timer->CAP;
+}
+
+/**
+  * @brief      Get Counter value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     24-bit Counter Value
+  *
+  * @details    This function reports the current 24-bit timer counter value.
+  */
+static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+    return timer->CNT;
+}
+
+/**
+  * @brief      Reset Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to reset current counter value and internal prescale counter value.
+  */
+static __INLINE void TIMER_ResetCounter(TIMER_T *timer)
+{
+    timer->CNT = 0UL;
+    while((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {
+        ;
+    }
+}
+
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+                             uint32_t u32DropCount,
+                             uint32_t u32Timeout,
+                             uint32_t u32EnableInt);
+void TIMER_DisableFreqCounter(TIMER_T *timer);
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
+
+/*@}*/ /* end of group M480_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_TIMER_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_H__ */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_timer_pwm.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,434 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @brief    M480 Timer PWM Controller(Timer PWM) driver source file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_PWM_Driver TIMER PWM Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set PWM Counter Clock Source
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CntClkSrc    PWM counter clock source, could be one of following source
+  *                                 - \ref TPWM_CNTR_CLKSRC_TMR_CLK
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER0_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER1_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER2_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER3_INT
+  *
+  * @return     None
+  *
+  * @details    This function is used to set PWM counter clock source.
+  */
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc)
+{
+    (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc;
+}
+
+/**
+  * @brief      Configure PWM Output Frequency and Duty Cycle
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Frequency    Target generator frequency.
+  * @param[in]  u32DutyCycle    Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...
+  *
+  * @return     Nearest frequency clock in nano second
+  *
+  * @details    This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.
+  * @note       This API is only available if Timer PWM counter clock source is from TMRx_CLK.
+  */
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    uint32_t u32PWMClockFreq, u32TargetFreq;
+    uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP;
+
+    if((timer == TIMER0) || (timer == TIMER1)) {
+        u32PWMClockFreq = CLK_GetPCLK0Freq();
+    } else {
+        u32PWMClockFreq = CLK_GetPCLK1Freq();
+    }
+
+    /* Calculate u16PERIOD and u16PSC */
+    for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) {
+        u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;
+
+        /* If target u32Period is larger than 0x10000, need to use a larger prescaler */
+        if(u32Period <= 0x10000UL) {
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */
+    u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;
+
+    /* Set PWM to up count type */
+    timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos);
+
+    /* Set PWM to auto-reload mode */
+    timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE;
+
+    /* Convert to real register value */
+    TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));
+
+    TPWM_SET_PERIOD(timer, (u32Period - 1UL));
+    if(u32DutyCycle) {
+        u32CMP = (u32DutyCycle * u32Period) / 100UL;
+    } else {
+        u32CMP = 0UL;
+    }
+
+    TPWM_SET_CMPDAT(timer, u32CMP);
+
+    return (u32TargetFreq);
+}
+
+/**
+  * @brief      Enable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32DTCount  Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount)
+{
+    timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+  * @brief      Enable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32DTCount  Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount)
+{
+    timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+  * @brief      Disable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable Dead-time of selected channel.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_DisableDeadTime(TIMER_T *timer)
+{
+    timer->PWMDTCTL = 0x0UL;
+}
+
+/**
+  * @brief      Enable PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable PWM generator and start counter counting.
+  */
+void TPWM_EnableCounter(TIMER_T *timer)
+{
+    timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Disable PWM Generator
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.
+  */
+void TPWM_DisableCounter(TIMER_T *timer)
+{
+    timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Enable Trigger EADC
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Condition    The condition to trigger EADC. It could be one of following conditions:
+  *                                 - \ref TPWM_TRIGGER_EADC_AT_ZERO_POINT
+  *                                 - \ref TPWM_TRIGGER_EADC_AT_PERIOD_POINT
+  *                                 - \ref TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT
+  *                                 - \ref TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT
+  *                                 - \ref TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable specified counter compare event to trigger EADC.
+  */
+void TPWM_EnableTriggerEADC(TIMER_T *timer, uint32_t u32Condition)
+{
+    timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition;
+}
+
+/**
+  * @brief      Disable Trigger EADC
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable counter compare event to trigger EADC.
+  */
+void TPWM_DisableTriggerEADC(TIMER_T *timer)
+{
+    timer->PWMEADCTS = 0x0UL;
+}
+
+/**
+  * @brief      Enable Fault Brake Function
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CH0Level     PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting
+  *                                 - \ref TPWM_OUTPUT_TOGGLE
+  *                                 - \ref TPWM_OUTPUT_NOTHING
+  *                                 - \ref TPWM_OUTPUT_LOW
+  *                                 - \ref TPWM_OUTPUT_HIGH
+  * @param[in]  u32CH1Level     PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting
+  *                                 - \ref TPWM_OUTPUT_TOGGLE
+  *                                 - \ref TPWM_OUTPUT_NOTHING
+  *                                 - \ref TPWM_OUTPUT_LOW
+  *                                 - \ref TPWM_OUTPUT_HIGH
+  * @param[in]  u32BrakeSource  Fault brake source, combination of following source
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable fault brake function.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource)
+{
+    timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL);
+    timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) |
+                       (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos);
+}
+
+/**
+  * @brief      Enable Fault Brake Interrupt
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable fault brake interrupt.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTEN1 |= u32IntSource;
+}
+
+/**
+  * @brief      Disable Fault Brake Interrupt
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable fault brake interrupt.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTEN1 &= ~u32IntSource;
+}
+
+/**
+  * @brief      Indicate Fault Brake Interrupt Flag
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     Fault brake interrupt flag of specified source
+  * @retval     0       Fault brake interrupt did not occurred
+  * @retval     1       Fault brake interrupt occurred
+  *
+  * @details    This function is used to indicate fault brake interrupt flag occurred or not of selected source.
+  */
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+    return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Fault Brake Interrupt Flags
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to clear fault brake interrupt flags of selected source.
+  * @note       The register write-protection function should be disabled before using this function.
+  */
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTSTS1 = (0x3UL << u32IntSource);
+}
+
+/**
+  * @brief      Enable load mode of selected channel
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32LoadMode  Timer PWM counter loading mode, could be one of following mode
+  *                             - \ref TPWM_LOAD_MODE_PERIOD
+  *                             - \ref TPWM_LOAD_MODE_IMMEDIATE
+  *                             - \ref TPWM_LOAD_MODE_CENTER
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable load mode of selected channel.
+  * @note       The default loading mode is period loading mode.
+  */
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode)
+{
+    timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode;
+}
+
+/**
+  * @brief      Enable brake pin noise filter function
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32BrakePinSrc  The external brake pin source, could be one of following source
+  *                                 - \ref TPWM_TM_BRAKE0
+  *                                 - \ref TPWM_TM_BRAKE1
+  *                                 - \ref TPWM_TM_BRAKE2
+  *                                 - \ref TPWM_TM_BRAKE3
+  * @param[in]  u32DebounceCnt  This value controls the real debounce sample time.
+  *                             The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt).
+  * @param[in]  u32ClkSrcSel    Brake pin detector debounce clock source, could be one of following source
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_1
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_2
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_4
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_8
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_16
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_32
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_64
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_128
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable external brake pin detector noise filter function.
+  */
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel)
+{
+    timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) |
+                    (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) |
+                    (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) |
+                    (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+/**
+  * @brief      Disable brake pin noise filter function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable external brake pin detector noise filter function.
+  */
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer)
+{
+    timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+
+/**
+  * @brief Enable brake pin inverse function
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @return None
+  * @details This function is used to enable PWM brake pin inverse function.
+  */
+void TPWM_EnableBrakePinInverse(TIMER_T *timer)
+{
+    timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+  * @brief Disable brake pin inverse function
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @return None
+  * @details This function is used to disable PWM brake pin inverse function.
+  */
+void TPWM_DisableBrakePinInverse(TIMER_T *timer)
+{
+    timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+  * @brief Set brake pin source
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in] u32BrakePinNum Brake pin selection. One of the following:
+  *                 - \ref TPWM_TM_BRAKE0
+  *                 - \ref TPWM_TM_BRAKE1
+  *                 - \ref TPWM_TM_BRAKE2
+  *                 - \ref TPWM_TM_BRAKE3
+  * @return None
+  * @details This function is used to set PWM brake pin source.
+  */
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum)
+{
+    timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos));
+}
+
+
+/*@}*/ /* end of group M480_TIMER_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_TIMER_PWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_timer_pwm.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,745 @@
+/**************************************************************************//**
+ * @file     timer.h
+ * @version  V1.00
+ * @brief    M480 series Timer PWM Controller(Timer PWM) driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_PWM_H__
+#define __TIMER_PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+/** @addtogroup M480_TIMER_PWM_Driver TIMER PWM Driver
+  @{
+*/
+
+/** @addtogroup M480_TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Channel Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CH0                                (BIT0)       /*!< Indicate PWMx_CH0 \hideinitializer */
+#define TPWM_CH1                                (BIT1)       /*!< Indicate PWMx_CH1 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_UP_COUNT                           (0UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Up count type \hideinitializer */
+#define TPWM_DOWN_COUNT                         (1UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Down count type \hideinitializer */
+#define TPWM_UP_DOWN_COUNT                      (2UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Up-Down count type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_AUTO_RELOAD_MODE                   (0UL)                            /*!< Auto-reload mode \hideinitializer */
+#define TPWM_ONE_SHOT_MODE                      (TIMER_PWMCTL_CNTMODE_Msk)       /*!< One-shot mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_OUTPUT_TOGGLE                      (0UL)      /*!< Timer PWM output toggle \hideinitializer */
+#define TPWM_OUTPUT_NOTHING                     (1UL)      /*!< Timer PWM output nothing \hideinitializer */
+#define TPWM_OUTPUT_LOW                         (2UL)      /*!< Timer PWM output low \hideinitializer */
+#define TPWM_OUTPUT_HIGH                        (3UL)      /*!< Timer PWM output high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Trigger EADC Source Select Constant Definitions                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TRIGGER_EADC_AT_ZERO_POINT                      (0UL << TIMER_PWMEADCTS_TRGSEL_Pos)     /*!< Timer PWM trigger EADC while counter zero point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EADC_AT_PERIOD_POINT                    (1UL << TIMER_PWMEADCTS_TRGSEL_Pos)     /*!< Timer PWM trigger EADC while counter period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT            (2UL << TIMER_PWMEADCTS_TRGSEL_Pos)     /*!< Timer PWM trigger EADC while counter zero or period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT          (3UL << TIMER_PWMEADCTS_TRGSEL_Pos)     /*!< Timer PWM trigger EADC while counter up count compare point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT        (4UL << TIMER_PWMEADCTS_TRGSEL_Pos)     /*!< Timer PWM trigger EADC while counter down count compare point event occurred \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Control Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP0            (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP1            (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_BKPIN            (TIMER_PWMBRKCTL_BRKPEEN_Msk)  /*!< Brake pin as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16))    /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16))    /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16))    /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16))    /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */
+
+
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0           (TIMER_PWMBRKCTL_CPO0LBEN_Msk)  /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1           (TIMER_PWMBRKCTL_CPO1LBEN_Msk)  /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN           (TIMER_PWMBRKCTL_BRKPLEN_Msk)   /*!< Brake pin as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16))    /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16))    /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16))    /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16))    /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
+
+#define TPWM_BRAKE_EDGE                         (TIMER_PWMSWBRK_BRKETRG_Msk)    /*!< Edge-detect fault brake \hideinitializer */
+#define TPWM_BRAKE_LEVEL                        (TIMER_PWMSWBRK_BRKLTRG_Msk)    /*!< Level-detect fault brake \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Load Mode Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_LOAD_MODE_PERIOD                   (0UL)                       /*!< Timer PWM period load mode \hideinitializer \hideinitializer */
+#define TPWM_LOAD_MODE_IMMEDIATE                (TIMER_PWMCTL_IMMLDEN_Msk)  /*!< Timer PWM immediately load mode \hideinitializer \hideinitializer */
+#define TPWM_LOAD_MODE_CENTER                   (TIMER_PWMCTL_CTRLD_Msk)    /*!< Timer PWM center load mode \hideinitializer \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Pin De-bounce Clock Source Select Constant Definitions                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BKP_DBCLK_PCLK_DIV_1               (0UL)    /*!< De-bounce clock is PCLK divide by 1 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_2               (1UL)    /*!< De-bounce clock is PCLK divide by 2 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_4               (2UL)    /*!< De-bounce clock is PCLK divide by 4 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_8               (3UL)    /*!< De-bounce clock is PCLK divide by 8 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_16              (4UL)    /*!< De-bounce clock is PCLK divide by 16 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_32              (5UL)    /*!< De-bounce clock is PCLK divide by 32 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_64              (6UL)    /*!< De-bounce clock is PCLK divide by 64 \hideinitializer \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_128             (7UL)    /*!< De-bounce clock is PCLK divide by 128 \hideinitializer \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Pin Source Select Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TM_BRAKE0                          (0UL)    /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer \hideinitializer */
+#define TPWM_TM_BRAKE1                          (1UL)    /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer \hideinitializer */
+#define TPWM_TM_BRAKE2                          (2UL)    /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer \hideinitializer */
+#define TPWM_TM_BRAKE3                          (3UL)    /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Clock Source Select Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_CLKSRC_TMR_CLK             (0UL)    /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER0_INT          (1UL)    /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER1_INT          (2UL)    /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER2_INT          (3UL)    /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER3_INT          (4UL)    /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Synchronous Mode Constant Definitions                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_SYNC_DISABLE               (0UL)    /*!< Disable TIMER PWM synchronous function \hideinitializer \hideinitializer */
+#define TPWM_CNTR_SYNC_START_BY_TIMER0       ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos))  /*!< PWM counter synchronous start by TIMER0 PWM \hideinitializer \hideinitializer */
+#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER0       ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos))  /*!< PWM counter synchronous clear by TIMER0 PWM \hideinitializer \hideinitializer */
+#define TPWM_CNTR_SYNC_START_BY_TIMER2       ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos))  /*!< PWM counter synchronous start by TIMER2 PWM \hideinitializer \hideinitializer */
+#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER2       ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos))  /*!< PWM counter synchronous clear by TIMER2 PWM \hideinitializer \hideinitializer */
+
+/*@}*/ /* end of group M480_TIMER_PWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable PWM Counter Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable specified Timer channel as PWM counter mode, then timer counter mode is invalid.
+  * @note       All registers about time counter function will be cleared to 0 and timer clock source will be changed to PCLKx automatically after executing this macro.
+  * \hideinitializer 
+  */
+#define TPWM_ENABLE_PWM_MODE(timer)         ((timer)->ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos))
+
+/**
+  * @brief      Disable PWM Counter Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.
+  * @note       All registers about PWM counter function will be cleared to 0 after executing this macro.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_PWM_MODE(timer)        ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos))
+
+/**
+  * @brief      Enable Independent Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_INDEPENDENT_MODE(timer)     ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+  * @brief      Enable Complementary Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer)   ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+  * @brief      Set Counter Type
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  type        Timer PWM count type, could be one of the following type
+  *                             - \ref TPWM_UP_COUNT
+  *                             - \ref TPWM_DOWN_COUNT
+  *                             - \ref TPWM_UP_DOWN_COUNT
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set Timer PWM counter type.
+  * \hideinitializer
+  */
+#define TPWM_SET_COUNTER_TYPE(timer, type)      ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type))
+
+/**
+  * @brief      Start PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable PWM generator and start counter counting.
+  * \hideinitializer
+  */
+#define TPWM_START_COUNTER(timer)               ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)
+
+/**
+  * @brief      Stop PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to stop PWM counter after current period is completed.
+  * \hideinitializer
+  */
+#define TPWM_STOP_COUNTER(timer)                ((timer)->PWMPERIOD = 0x0)
+
+/**
+  * @brief      Set Counter Clock Prescaler
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  prescaler    Clock prescaler of specified channel. Valid values are between 0x0~0xFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the prescaler of specified TIMER PWM.
+  * @note       If prescaler is 0, then there is no scaling in counter clock source.
+  * \hideinitializer
+  */
+#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler))
+
+/**
+  * @brief      Get Counter Clock Prescaler
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])
+  *
+  * @details    Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).
+  * \hideinitializer
+  */
+#define TPWM_GET_PRESCALER(timer)       ((timer)->PWMCLKPSC)
+
+/**
+  * @brief      Set Counter Period
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  period      Period of specified channel. Valid values are between 0x0~0xFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the period of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_SET_PERIOD(timer, period)  ((timer)->PWMPERIOD = (period))
+
+/**
+  * @brief      Get Counter Period
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])
+  *
+  * @details    This macro is used to get the period of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_GET_PERIOD(timer)          ((timer)->PWMPERIOD)
+
+/**
+  * @brief      Set Comparator Value
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  cmp     Comparator of specified channel. Valid values are between 0x0~0xFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the comparator value of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_SET_CMPDAT(timer, cmp)     ((timer)->PWMCMPDAT = (cmp))
+
+/**
+  * @brief      Get Comparator Value
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])
+  *
+  * @details    This macro is used to get the comparator value of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMPDAT(timer)          ((timer)->PWMCMPDAT)
+
+/**
+  * @brief      Clear Counter
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear counter of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_COUNTER(timer)       ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)
+
+/**
+  * @brief      Software Trigger Brake Event
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  type        Type of brake trigger. Valid values are:
+  *                             - \ref TPWM_BRAKE_EDGE
+  *                             - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This macro is used to trigger brake event by writing PWMSWBRK register.
+  * \hideinitializer
+  */
+#define TPWM_SW_TRIGGER_BRAKE(timer, type)  ((timer)->PWMSWBRK = (type))
+
+/**
+  * @brief      Enable Output Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  ch          Enable specified channel output function. Valid values are:
+  *                             - \ref TPWM_CH0
+  *                             - \ref TPWM_CH1
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output function of specified output pins.
+  * @note       If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_OUTPUT(timer, ch)  ((timer)->PWMPOEN = (ch))
+
+/**
+  * @brief      Set Output Inverse
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  ch          Set specified channel output is inversed or not. Valid values are:
+  *                             - \ref TPWM_CH0
+  *                             - \ref TPWM_CH1
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output inverse of specified output pins.
+  * @note       If u32ChMask parameter is 0, then output inverse function will be disabled.
+  * \hideinitializer
+  */
+#define TPWM_SET_OUTPUT_INVERSE(timer, ch)  ((timer)->PWMPOLCTL = (ch))
+
+/**
+  * @brief      Enable Output Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  ch       Enable specified channel output mask function. Valid values are:
+  *                             - \ref TPWM_CH0
+  *                             - \ref TPWM_CH1
+  *
+  * @param[in]  level    Output to high or low on specified mask channel.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output function of specified output pins.
+  * @note       If u32ChMask parameter is 0, then output mask function will be disabled.
+  * \hideinitializer
+  */
+#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0)
+
+/**
+  * @brief      Set Counter Synchronous Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  mode    Synchronous mode. Possible options are:
+  *                         - \ref TPWM_CNTR_SYNC_DISABLE
+  *                         - \ref TPWM_CNTR_SYNC_START_BY_TIMER0
+  *                         - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0
+  *                         - \ref TPWM_CNTR_SYNC_START_BY_TIMER2
+  *                         - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set counter synchronous mode of specified Timer PWM module.
+  * @note       Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and
+  *             TIMER2~3 PWM counter synchronous by TIMER2 PWM.
+  * \hideinitializer
+  */
+#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode))
+
+/**
+  * @brief      Trigger Counter Synchronous
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to trigger synchronous event by specified TIMER PWM.
+  * @note       1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n
+  *             2. STRGEN (PWMSTRG[0]) is write only and always read as 0.
+  * \hideinitializer
+  */
+#define TPWM_TRIGGER_COUNTER_SYNC(timer)    ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk)
+
+/**
+  * @brief      Enable Zero Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the zero event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_ZERO_INT(timer)         ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+  * @brief      Disable Zero Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the zero event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_ZERO_INT(timer)        ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+  * @brief      Get Zero Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Zero event interrupt did not occur
+  * @retval     1   Zero event interrupt occurred
+  *
+  * @details    This macro indicates zero event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_ZERO_INT_FLAG(timer)       (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Zero Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears zero event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_ZERO_INT_FLAG(timer)     ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk)
+
+/**
+  * @brief      Enable Period Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the period event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_PERIOD_INT(timer)       ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+  * @brief      Disable Period Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the period event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_PERIOD_INT(timer)      ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+  * @brief      Get Period Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Period event interrupt did not occur
+  * @retval     1   Period event interrupt occurred
+  *
+  * @details    This macro indicates period event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_PERIOD_INT_FLAG(timer)     (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Period Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears period event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_PERIOD_INT_FLAG(timer)   ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)
+
+/**
+  * @brief      Enable Compare Up Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the compare up event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_CMP_UP_INT(timer)       ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+  * @brief      Disable Compare Up Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the compare up event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_CMP_UP_INT(timer)      ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+  * @brief      Get Compare Up Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Compare up event interrupt did not occur
+  * @retval     1   Compare up event interrupt occurred
+  *
+  * @details    This macro indicates compare up event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMP_UP_INT_FLAG(timer)     (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Compare Up Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears compare up event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer)   ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)
+
+/**
+  * @brief      Enable Compare Down Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the compare down event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_CMP_DOWN_INT(timer)     ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+  * @brief      Disable Compare Down Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the compare down event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_CMP_DOWN_INT(timer)    ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+  * @brief      Get Compare Down Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Compare down event interrupt did not occur
+  * @retval     1   Compare down event interrupt occurred
+  *
+  * @details    This macro indicates compare down event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMP_DOWN_INT_FLAG(timer)   (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Compare Down Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears compare down event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk)
+
+/**
+  * @brief      Get Counter Reach Maximum Count Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer PWM counter never counts to maximum value
+  * @retval     1   Timer PWM counter counts to maximum value, 0xFFFF
+  *
+  * @details    This macro indicates Timer PWM counter has count to 0xFFFF or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_REACH_MAX_CNT_STATUS(timer)    (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Counter Reach Maximum Count Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears reach maximum count status.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer)  ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)
+
+/**
+  * @brief      Get Trigger EADC Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0       Trigger EADC start conversion is not occur
+  * @retval     1       Specified counter compare event has trigger ADC start conversion
+  *
+  * @details    This macro is used to indicate PWM counter compare event has triggered EADC start conversion.
+  * \hideinitializer
+  */
+#define TPWM_GET_TRG_EADC_STATUS(timer)          (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Trigger EADC Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear PWM counter compare event trigger EADC status.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_TRG_EADC_STATUS(timer)        ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)
+
+/**
+  * @brief      Set Brake Event at Brake Pin High or Low-to-High
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+  * @note       The default brake pin detection is high level or from low to high.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer)   ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+  * @brief      Set Brake Event at Brake Pin Low or High-to-Low
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at low level or transfer from high to low.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer)    ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+  * @brief      Set External Brake Pin Source
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  pin         The external brake pin source, could be one of following source
+  *                                 - \ref TPWM_TM_BRAKE0
+  *                                 - \ref TPWM_TM_BRAKE1
+  *                                 - \ref TPWM_TM_BRAKE2
+  *                                 - \ref TPWM_TM_BRAKE3
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin)   ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<<TIMER_PWMBNF_BKPINSRC_Pos))
+
+
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc);
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount);
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount);
+void TPWM_DisableDeadTime(TIMER_T *timer);
+void TPWM_EnableCounter(TIMER_T *timer);
+void TPWM_DisableCounter(TIMER_T *timer);
+void TPWM_EnableTriggerEADC(TIMER_T *timer, uint32_t u32Condition);
+void TPWM_DisableTriggerEADC(TIMER_T *timer);
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource);
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode);
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel);
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer);
+void TPWM_EnableBrakePinInverse(TIMER_T *timer);
+void TPWM_DisableBrakePinInverse(TIMER_T *timer);
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum);
+
+/*@}*/ /* end of group M480_TIMER_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_TIMER_PWM_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_PWM_H__ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_uart.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,578 @@
+/**************************************************************************//**
+ * @file     uart.c
+ * @version  V3.00
+ * @brief    M480 series UART driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_UART_Driver UART Driver
+  @{
+*/
+
+/** @addtogroup M480_UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear UART specified interrupt flag
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTSTS_LININT_Msk    : LIN bus interrupt
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ *                                      - \ref UART_INTSTS_MODEMINT_Msk  : Modem Status interrupt
+ *                                      - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear UART specified interrupt flag.
+ */
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
+{
+
+    if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) { /* Clear Receive Line Status Interrupt */
+        uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
+        uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) { /* Clear Modem Status Interrupt */
+        uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+    } else {
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) { /* Clear Buffer Error Interrupt */
+        uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) { /* Clear Wake-up Interrupt */
+        uart->WKSTS = UART_WKSTS_CTSWKF_Msk  | UART_WKSTS_DATWKF_Msk  |
+                      UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk |
+                      UART_WKSTS_TOUTWKF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_LININT_Msk) { /* Clear LIN Bus Interrupt */
+        uart->INTSTS = UART_INTSTS_LINIF_Msk;
+        uart->LINSTS = UART_LINSTS_BITEF_Msk    | UART_LINSTS_BRKDETF_Msk  |
+                       UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+                       UART_LINSTS_SLVHEF_Msk   | UART_LINSTS_SLVHDETF_Msk ;
+    }
+}
+
+
+/**
+ *  @brief      Disable UART interrupt
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+    uart->INTEN = 0ul;
+}
+
+
+/**
+ *  @brief      Disable UART auto flow control function
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+    uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ *    @brief        Disable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt *
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+    /* Disable UART specified interrupt */
+    UART_DISABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+    /* Set RTS pin output is low level active */
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+    /* Set CTS pin input is low level active */
+    uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+    /* Set RTS and CTS auto flow control enable */
+    uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ *    @brief        The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module:
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt *
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+    /* Enable UART specified interrupt */
+    UART_ENABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Open and set UART function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The baudrate of UART module.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+    uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+    uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
+    uint32_t u32Baud_Div = 0ul;
+
+
+    if(uart==(UART_T*)UART0) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+    } else if(uart==(UART_T*)UART1) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+    } else if(uart==(UART_T*)UART2) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+    } else if(uart==(UART_T*)UART3) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+    } else if(uart==(UART_T*)UART4) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+    } else if(uart==(UART_T*)UART5) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+    }
+
+    /* Select UART function */
+    uart->FUNCSEL = UART_FUNCSEL_UART;
+
+    /* Set UART line configuration */
+    uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+    /* Set UART Rx and RTS trigger level */
+    uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul) {
+        u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul) {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32Baud_Div > 0xFFFFul) {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        } else {
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+        }
+    }
+}
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive FIFO.
+ *    @param[in]    u32ReadBytes    The the read bytes number of data.
+ *
+ *    @return       u32Count Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) {
+        u32delayno = 0ul;
+
+        while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) { /* Check RX empty => failed */
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul) {
+                u32Exit = 1ul;
+                break;
+            } else {
+            }
+        }
+
+        if(u32Exit == 1ul) {
+            break;
+        } else {
+            pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX  */
+        }
+    }
+
+    return u32Count;
+
+}
+
+
+/**
+ *    @brief        Set UART line configuration
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The register value of baudrate of UART module.
+ *                                  If u32baudrate = 0, UART baudrate will not change.
+ *    @param[in]    u32data_width   The data length of UART module.
+ *                                  - \ref UART_WORD_LEN_5
+ *                                  - \ref UART_WORD_LEN_6
+ *                                  - \ref UART_WORD_LEN_7
+ *                                  - \ref UART_WORD_LEN_8
+ *    @param[in]    u32parity       The parity setting (none/odd/even/mark/space) of UART module.
+ *                                  - \ref UART_PARITY_NONE
+ *                                  - \ref UART_PARITY_ODD
+ *                                  - \ref UART_PARITY_EVEN
+ *                                  - \ref UART_PARITY_MARK
+ *                                  - \ref UART_PARITY_SPACE
+ *    @param[in]    u32stop_bits    The stop bit length (1/1.5/2 bit) of UART module.
+ *                                  - \ref UART_STOP_BIT_1
+ *                                  - \ref UART_STOP_BIT_1_5
+ *                                  - \ref UART_STOP_BIT_2
+ *
+ *    @return       None
+ *
+ *    @details      This function use to config UART line setting.
+ */
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
+{
+    uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+    uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+    uint32_t u32Baud_Div = 0ul;
+
+
+    if(uart==(UART_T*)UART0) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+    } else if(uart==(UART_T*)UART1) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+    } else if(uart==(UART_T*)UART2) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+    } else if(uart==(UART_T*)UART3) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+    } else if(uart==(UART_T*)UART4) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+    } else if(uart==(UART_T*)UART5) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul) {
+        u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    } else {
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul) {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32Baud_Div > 0xFFFFul) {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        } else {
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+        }
+    }
+
+    /* Set UART line configuration */
+    uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ *    @brief        Set Rx timeout count
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *    @param[in]    u32TOC  Rx timeout counter.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+    /* Set time-out interrupt comparator */
+    uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+    /* Set time-out counter enable */
+    uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ *    @brief        Select and configure IrDA function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Buadrate     The baudrate of UART module.
+ *    @param[in]    u32Direction    The direction of UART module in IrDA mode:
+ *                                  - \ref UART_IRDA_TXEN
+ *                                  - \ref UART_IRDA_RXEN
+ *
+ *    @return       None
+  *
+ *    @details      The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+    uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
+    uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+    uint32_t u32Baud_Div;
+
+    /* Select IrDA function mode */
+    uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+
+    if(uart==UART0) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+    } else if(uart==UART1) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+    } else if(uart==UART2) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+    } else if(uart==UART3) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+    } else if(uart==UART4) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+    } else if(uart==UART5) {
+        /* Get UART clock source selection */
+        u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+        /* Get UART clock divider number */
+        u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+    }
+
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul) {
+        u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    } else {
+    }
+
+    /* Set UART IrDA baud rate in mode 0 */
+    if(u32Buadrate != 0ul) {
+        u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
+
+        if(u32Baud_Div < 0xFFFFul) {
+            uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+        } else {
+        }
+    }
+
+    /* Configure IrDA relative settings */
+    if(u32Direction == UART_IRDA_RXEN) {
+        uart->IRDA |= UART_IRDA_RXINV_Msk;     /*Rx signal is inverse*/
+        uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+    } else {
+        uart->IRDA &= ~UART_IRDA_TXINV_Msk;    /*Tx signal is not inverse*/
+        uart->IRDA |= UART_IRDA_TXEN_Msk;
+    }
+
+}
+
+
+/**
+ *    @brief        Select and configure RS485 function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *    @param[in]    u32Mode     The operation mode(NMM/AUD/AAD).
+ *                              - \ref UART_ALTCTL_RS485NMM_Msk
+ *                              - \ref UART_ALTCTL_RS485AUD_Msk
+ *                              - \ref UART_ALTCTL_RS485AAD_Msk
+ *    @param[in]    u32Addr     The RS485 address.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+    /* Select UART RS485 function mode */
+    uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+    /* Set RS585 configuration */
+    uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+    uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ *    @brief        Select and configure LIN function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Mode         The LIN direction :
+ *                                  - \ref UART_ALTCTL_LINTXEN_Msk
+ *                                  - \ref UART_ALTCTL_LINRXEN_Msk
+ *    @param[in]    u32BreakLength  The break field length.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+    /* Select LIN function mode */
+    uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+    /* Select LIN function setting : Tx enable, Rx enable and break field length */
+    uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+    uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to UART transmission FIFO.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       u32Count transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) {
+        u32delayno = 0ul;
+        while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) { /* Wait Tx empty and Time-out manner */
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul) {
+                u32Exit = 1ul;
+                break;
+            } else {
+            }
+        }
+
+        if(u32Exit == 1ul) {
+            break;
+        } else {
+            uart->DAT = pu8TxBuf[u32Count];    /* Send UART Data from buffer */
+        }
+    }
+
+    return u32Count;
+
+}
+
+
+/*@}*/ /* end of group M480_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_UART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_uart.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,479 @@
+/**************************************************************************//**
+ * @file     uart.h
+ * @version  V3.00
+ * @brief    M480 series UART driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __UART_H__
+#define __UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_UART_Driver UART Driver
+  @{
+*/
+
+/** @addtogroup M480_UART_EXPORTED_CONSTANTS UART Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART FIFO size constants definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART2_FIFO_SIZE 16ul /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART3_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART4_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART5_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FIFO constants definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FIFO_RFITL_1BYTE      (0x0ul << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */
+#define UART_FIFO_RFITL_4BYTES     (0x1ul << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */
+#define UART_FIFO_RFITL_8BYTES     (0x2ul << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */
+#define UART_FIFO_RFITL_14BYTES    (0x3ul << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */
+
+#define UART_FIFO_RTSTRGLV_1BYTE      (0x0ul << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */
+#define UART_FIFO_RTSTRGLV_4BYTES     (0x1ul << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */
+#define UART_FIFO_RTSTRGLV_8BYTES     (0x2ul << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */
+#define UART_FIFO_RTSTRGLV_14BYTES    (0x3ul << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINE constants definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5     (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */
+#define UART_WORD_LEN_6     (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */
+#define UART_WORD_LEN_7     (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */
+#define UART_WORD_LEN_8     (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */
+
+#define UART_PARITY_NONE    (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity   \hideinitializer */
+#define UART_PARITY_ODD     (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity  \hideinitializer */
+#define UART_PARITY_EVEN    (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */
+#define UART_PARITY_MARK    (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1'  \hideinitializer */
+#define UART_PARITY_SPACE   (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0'  \hideinitializer */
+
+#define UART_STOP_BIT_1     (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit  \hideinitializer */
+#define UART_STOP_BIT_1_5   (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length  \hideinitializer */
+#define UART_STOP_BIT_2     (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS ACTIVE LEVEL constants definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_LOW_LEV_ACTIVE   (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */
+#define UART_RTS_IS_HIGH_LEV_ACTIVE  (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_IRDA constants definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_IRDA_TXEN      (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */
+#define UART_IRDA_RXEN      (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FUNCSEL constants definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNCSEL_UART  (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function  (Default) \hideinitializer */
+#define UART_FUNCSEL_LIN   (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function             \hideinitializer */
+#define UART_FUNCSEL_IrDA  (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function            \hideinitializer */
+#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function           \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINCTL constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_LINCTL_BRKFL(x)    (((x)-1) << UART_LINCTL_BRKFL_Pos)  /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 \hideinitializer */
+#define UART_LINCTL_BSL(x)      (((x)-1) << UART_LINCTL_BSL_Pos)    /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK             (0x0UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK_SYNC        (0x1UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK_SYNC_ID     (0x2UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field \hideinitializer */
+#define UART_LINCTL_PID(x)      ((x) << UART_LINCTL_PID_Pos)       /*!< UART_LINCTL setting to set LIN PID value \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART BAUDRATE MODE constants definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_BAUD_MODE0     (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */
+#define UART_BAUD_MODE2     (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */
+
+
+/*@}*/ /* end of group M480_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+
+/**
+ *    @brief        Calculate UART baudrate mode0 divider
+ *
+ *    @param[in]    u32SrcFreq      UART clock frequency
+ *    @param[in]    u32BaudRate     Baudrate of UART module
+ *
+ *    @return       UART baudrate mode0 divider
+ *
+ *    @details      This macro calculate UART baudrate mode0 divider.
+ *    \hideinitializer
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate)    ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)
+
+
+/**
+ *    @brief        Calculate UART baudrate mode2 divider
+ *
+ *    @param[in]    u32SrcFreq      UART clock frequency
+ *    @param[in]    u32BaudRate     Baudrate of UART module
+ *
+ *    @return       UART baudrate mode2 divider
+ *
+ *    @details      This macro calculate UART baudrate mode2 divider.
+ *    \hideinitializer
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)    ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ *    \hideinitializer
+ */
+#define UART_WRITE(uart, u8Data)    ((uart)->DAT = (u8Data))
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       The oldest data byte in RX FIFO.
+ *
+ *    @details      This macro read Rx data register.
+ *    \hideinitializer
+ */
+#define UART_READ(uart)    ((uart)->DAT)
+
+
+/**
+ *    @brief        Get Tx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not empty
+ *    @retval       >=1 Tx FIFO is empty
+ *
+ *    @details      This macro get Transmitter FIFO empty register value.
+ *    \hideinitializer
+ */
+#define UART_GET_TX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not empty
+ *    @retval       >=1 Rx FIFO is empty
+ *
+ *    @details      This macro get Receiver FIFO empty register value.
+ *    \hideinitializer
+ */
+#define UART_GET_RX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ *    @brief        Check specified UART port transmission is over.
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Tx transmission is not over
+ *    @retval       1 Tx transmission is over
+ *
+ *    @details      This macro return Transmitter Empty Flag register bit value.
+ *                  It indicates if specified UART port transmission is over nor not.
+ *    \hideinitializer
+ */
+#define UART_IS_TX_EMPTY(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ *    @brief        Wait specified UART port transmission is over
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro wait specified UART port transmission is over.
+ *    \hideinitializer
+ */
+#define UART_WAIT_TX_EMPTY(uart)    while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ *    @brief        Check RX is ready or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 The number of bytes in the RX FIFO is less than the RFITL
+ *    @retval       1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ *    @details      This macro check receive data available interrupt flag is set or not.
+ *    \hideinitializer
+ */
+#define UART_IS_RX_READY(uart)    (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ *    @brief        Check TX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 TX FIFO is full
+ *    @retval       0 TX FIFO is not full
+ *
+ *    @details      This macro check TX FIFO is full or not.
+ *    \hideinitializer
+ */
+#define UART_IS_TX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ *    @brief        Check RX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 RX FIFO is full
+ *    @retval       0 RX FIFO is not full
+ *
+ *    @details      This macro check RX FIFO is full or not.
+ *    \hideinitializer
+ */
+#define UART_IS_RX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ *    @brief        Get Tx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not full.
+ *    @retval       >=1 Tx FIFO is full.
+ *
+ *    @details      This macro get Tx full register value.
+ *    \hideinitializer
+ */
+#define UART_GET_TX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ *    @brief        Get Rx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not full.
+ *    @retval       >=1 Rx FIFO is full.
+ *
+ *    @details      This macro get Rx full register value.
+ *    \hideinitializer
+ */
+#define UART_GET_RX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+
+/**
+ *    @brief        Enable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto baud rate interrupt
+ *                              - \ref UART_INTEN_WKIEN_Msk      : Wakeup interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : Modem interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Rx Line status interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ *    \hideinitializer
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel)    ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ *    @brief        Disable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto baud rate interrupt
+ *                              - \ref UART_INTEN_WKIEN_Msk      : Wakeup interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ *    \hideinitializer
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel)    ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ *    @brief        Get specified interrupt flag/status
+ *
+ *    @param[in]    uart            The pointer of the specified UART module
+ *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWTOINT_Msk   : In DMA Mode, Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWMODINT_Msk  : In DMA Mode, MODEM Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWRLSINT_Msk  : In DMA Mode, Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWBUFEIF_Msk  : In DMA Mode, Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWTOIF_Msk    : In DMA Mode, Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWMODIF_Msk   : In DMA Mode, MODEM Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWRLSIF_Msk   : In DMA Mode, Receive Line Status Flag
+ *                                  - \ref UART_INTSTS_LININT_Msk    : LIN Bus Interrupt Indicator
+ *                                  - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RXTOINT_Msk   : Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_MODEMINT_Msk  : Modem Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_THREINT_Msk   : Transmit Holding Register Empty Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RDAINT_Msk    : Receive Data Available Interrupt Indicator
+ *                                  - \ref UART_INTSTS_LINIF_Msk     : LIN Bus Flag
+ *                                  - \ref UART_INTSTS_BUFERRIF_Msk  : Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_RXTOIF_Msk    : Rx Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_MODEMIF_Msk   : Modem Interrupt Flag
+ *                                  - \ref UART_INTSTS_RLSIF_Msk     : Receive Line Status Interrupt Flag
+ *                                  - \ref UART_INTSTS_THREIF_Msk    : Tx Empty Interrupt Flag
+ *                                  - \ref UART_INTSTS_RDAIF_Msk     : Rx Ready Interrupt Flag
+ *
+ *    @retval       0 The specified interrupt is not happened.
+ *                  1 The specified interrupt is happened.
+ *
+ *    @details      This macro get specified interrupt flag or interrupt indicator status.
+ *    \hideinitializer
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag)    (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ *    @brief        Clear RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear RS-485 address byte detection flag.
+ *    \hideinitializer
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart)    ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ *    @brief        Get RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Receiver detects a data that is not an address bit.
+ *    @retval       1 Receiver detects a data that is an address bit.
+ *
+ *    @details      This macro get RS-485 address byte detection flag.
+ *    \hideinitializer
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart)    (((uart)->FIFOSTS  & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart);
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart);
+
+
+/**
+ *    @brief        Set RTS pin to low
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+    uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ *    @brief        Set RTS pin to high
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+
+
+
+/*@}*/ /* end of group M480_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_UART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__UART_H__*/
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,644 @@
+/**************************************************************************//**
+ * @file     usbd.c
+ * @version  V1.00
+ * @brief    M480 USBD driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <string.h>
+#include "M480.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USBD_Driver USBD Driver
+  @{
+*/
+
+
+/** @addtogroup M480_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+
+/* Global variables for Control Pipe */
+uint8_t g_usbd_SetupPacket[8] = {0ul};        /*!< Setup packet buffer */
+volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static uint8_t *g_usbd_CtrlInPointer = 0;
+static uint8_t *g_usbd_CtrlOutPointer = 0;
+static volatile uint32_t g_usbd_CtrlInSize = 0ul;
+static volatile uint32_t g_usbd_CtrlOutSize = 0ul;
+static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul;
+static volatile uint32_t g_usbd_UsbAddr = 0ul;
+static volatile uint32_t g_usbd_UsbConfig = 0ul;
+static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul;
+static volatile uint32_t g_usbd_UsbAltInterface = 0ul;
+/**
+ * @endcond
+ */
+
+const S_USBD_INFO_T *g_usbd_sInfo;                  /*!< A pointer for USB information structure */
+
+VENDOR_REQ g_usbd_pfnVendorRequest       = NULL;    /*!< USB Vendor Request Functional Pointer */
+CLASS_REQ g_usbd_pfnClassRequest         = NULL;    /*!< USB Class Request Functional Pointer */
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL;    /*!< USB Set Interface Functional Pointer */
+SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL;   /*!< USB Set configuration callback function pointer */
+uint32_t g_u32EpStallLock                = 0ul;       /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+  * @brief      This function makes USBD module to be ready to use
+  *
+  * @param[in]  param           The structure of USBD information.
+  * @param[in]  pfnClassReq     USB Class request callback function.
+  * @param[in]  pfnSetInterface USB Set Interface request callback function.
+  *
+  * @return     None
+  *
+  * @details    This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+  */
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+    g_usbd_sInfo = param;
+    g_usbd_pfnClassRequest = pfnClassReq;
+    g_usbd_pfnSetInterface = pfnSetInterface;
+
+    /* get EP0 maximum packet size */
+    g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+    /* Initial USB engine */
+    USBD->ATTR = 0x6D0ul;
+    /* Force SE0 */
+    USBD_SET_SE0();
+}
+
+/**
+  * @brief    This function makes USB host to recognize the device
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+  */
+void USBD_Start(void)
+{
+    /* Disable software-disconnect function */
+    USBD_CLR_SE0();
+    USBD->ATTR = 0x7D0ul;
+
+    /* Clear USB-related interrupts before enable interrupt */
+    USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+
+    /* Enable USB-related interrupts. */
+    USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+}
+
+/**
+  * @brief      Get the received SETUP packet
+  *
+  * @param[in]  buf A buffer pointer used to store 8-byte SETUP packet.
+  *
+  * @return     None
+  *
+  * @details    Store SETUP packet to a user-specified buffer.
+  *
+  */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+    USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul);
+}
+
+/**
+  * @brief    Process SETUP packet
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse SETUP packet and perform the corresponding action.
+  *
+  */
+void USBD_ProcessSetupPacket(void)
+{
+    /* Get SETUP packet from USB buffer */
+    USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul);
+
+    /* Check the request type */
+    switch(g_usbd_SetupPacket[0] & 0x60ul) {
+    case REQ_STANDARD: {
+        USBD_StandardRequest();
+        break;
+    }
+    case REQ_CLASS: {
+        if(g_usbd_pfnClassRequest != NULL) {
+            g_usbd_pfnClassRequest();
+        }
+        break;
+    }
+    case REQ_VENDOR: {
+        if(g_usbd_pfnVendorRequest != NULL) {
+            g_usbd_pfnVendorRequest();
+        }
+        break;
+    }
+    default: {
+        /* Setup error, stall the device */
+        USBD_SET_EP_STALL(EP0);
+        USBD_SET_EP_STALL(EP1);
+        break;
+    }
+    }
+}
+
+/**
+  * @brief    Process GetDescriptor request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse GetDescriptor request and perform the corresponding action.
+  *
+  */
+void USBD_GetDescriptor(void)
+{
+    uint32_t u32Len;
+
+    u32Len = 0ul;
+    u32Len = g_usbd_SetupPacket[7];
+    u32Len <<= 8ul;
+    u32Len += g_usbd_SetupPacket[6];
+
+    switch(g_usbd_SetupPacket[3]) {
+    /* Get Device Descriptor */
+    case DESC_DEVICE: {
+        u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+
+        break;
+    }
+    /* Get Configuration Descriptor */
+    case DESC_CONFIG: {
+        uint32_t u32TotalLen;
+
+        u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+        u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+        u32Len = USBD_Minimum(u32Len, u32TotalLen);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+
+        break;
+    }
+
+    /* Get BOS Descriptor */
+    case DESC_BOS: {
+        u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len);
+        break;
+    }
+    /* Get HID Descriptor */
+    case DESC_HID: {
+        /* CV3.0 HID Class Descriptor Test,
+           Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+        uint32_t u32ConfigDescOffset;   /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
+        u32Len = USBD_Minimum(u32Len, LEN_HID);
+        u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
+        USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+
+        break;
+    }
+    /* Get Report Descriptor */
+    case DESC_HID_RPT: {
+        u32Len = USBD_Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
+        USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
+        break;
+    }
+    /* Get String Descriptor */
+    case DESC_STRING: {
+        /* Get String Descriptor */
+        if(g_usbd_SetupPacket[2] < 4ul) {
+            u32Len = USBD_Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
+            USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
+
+
+            break;
+        } else {
+            /* Not support. Reply STALL. */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+        }
+    }
+    default:
+        /* Not support. Reply STALL.*/
+        USBD_SET_EP_STALL(EP0);
+        USBD_SET_EP_STALL(EP1);
+        break;
+    }
+}
+
+/**
+  * @brief    Process standard request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse standard request and perform the corresponding action.
+  *
+  */
+void USBD_StandardRequest(void)
+{
+    uint32_t addr;
+    /* clear global variables for new request */
+    g_usbd_CtrlInPointer = 0;
+    g_usbd_CtrlInSize = 0ul;
+
+    if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) {  /* request data transfer direction */
+        /* Device to host */
+        switch(g_usbd_SetupPacket[1]) {
+        case GET_CONFIGURATION: {
+            /* Return current configuration setting */
+            /* Data stage */
+            addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            M8(addr) = (uint8_t)g_usbd_UsbConfig;
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 1ul);
+            /* Status stage */
+            USBD_PrepareCtrlOut(0, 0ul);
+            break;
+        }
+        case GET_DESCRIPTOR: {
+            USBD_GetDescriptor();
+            USBD_PrepareCtrlOut(0, 0ul); /* For status stage */
+            break;
+        }
+        case GET_INTERFACE: {
+            /* Return current interface setting */
+            /* Data stage */
+            addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            M8(addr) = (uint8_t)g_usbd_UsbAltInterface;
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 1ul);
+            /* Status stage */
+            USBD_PrepareCtrlOut(0, 0ul);
+            break;
+        }
+        case GET_STATUS: {
+            /* Device */
+            if(g_usbd_SetupPacket[0] == 0x80ul) {
+                uint8_t u8Tmp;
+
+                u8Tmp = (uint8_t)0ul;
+                if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) {
+                    u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/
+                }
+                if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul) {
+                    u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */
+                }
+
+                addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                M8(addr) = u8Tmp;
+
+            }
+            /* Interface */
+            else if(g_usbd_SetupPacket[0] == 0x81ul) {
+                addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                M8(addr) = (uint8_t)0ul;
+            }
+            /* Endpoint */
+            else if(g_usbd_SetupPacket[0] == 0x82ul) {
+                uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
+                addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul);
+            }
+
+            addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul;
+            M8(addr) = (uint8_t)0ul;
+            /* Data stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 2ul);
+            /* Status stage */
+            USBD_PrepareCtrlOut(0, 0ul);
+            break;
+        }
+        default: {
+            /* Setup error, stall the device */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+        }
+        }
+    } else {
+        /* Host to device */
+        switch(g_usbd_SetupPacket[1]) {
+        case CLEAR_FEATURE: {
+            if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) {
+                uint32_t epNum, i;
+
+                /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+                   a flag: g_u32EpStallLock is added to support it */
+                epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
+                for(i = 0ul; i < USBD_MAX_EP; i++) {
+                    if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul)) {
+                        USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
+                    }
+                }
+            } else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) {
+                g_usbd_RemoteWakeupEn = (uint8_t)0;
+            }
+
+            /* Status stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+            break;
+        }
+        case SET_ADDRESS: {
+            g_usbd_UsbAddr = g_usbd_SetupPacket[2];
+            /* Status Stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+
+            break;
+        }
+        case SET_CONFIGURATION: {
+            g_usbd_UsbConfig = g_usbd_SetupPacket[2];
+
+            if(g_usbd_pfnSetConfigCallback) {
+                g_usbd_pfnSetConfigCallback();
+            }
+
+            /* Status stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+            break;
+        }
+        case SET_FEATURE: {
+            if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) { /* 0: device */
+                if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) { /* 3: HNP enable */
+                    OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk);
+                }
+            }
+            if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) {
+                USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul));
+            } else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) {
+                g_usbd_RemoteWakeupEn = (uint8_t)1ul;
+            }
+
+            /* Status stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+
+            break;
+        }
+        case SET_INTERFACE: {
+            g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
+            if(g_usbd_pfnSetInterface != NULL) {
+                g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
+            }
+            /* Status stage */
+            USBD_SET_DATA1(EP0);
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+            break;
+        }
+        default: {
+            /* Setup error, stall the device */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+        }
+        }
+    }
+}
+
+/**
+  * @brief      Prepare the first Control IN pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data sent to USB host.
+  * @param[in]  u32Size The IN transfer size.
+  *
+  * @return     None
+  *
+  * @details    Prepare data for Control IN transfer.
+  *
+  */
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
+{
+    uint32_t addr;
+    if(u32Size > g_usbd_CtrlMaxPktSize) {
+        /* Data size > MXPLD */
+        g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
+        g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
+        USBD_SET_DATA1(EP0);
+        addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+        USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize);
+        USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+    } else {
+        /* Data size <= MXPLD */
+        g_usbd_CtrlInPointer = 0;
+        g_usbd_CtrlInSize = 0ul;
+        USBD_SET_DATA1(EP0);
+        addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+        USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size);
+        USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+    }
+}
+
+/**
+  * @brief    Repeat Control IN pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the remained data of Control IN transfer.
+  *
+  */
+void USBD_CtrlIn(void)
+{
+    static uint8_t u8ZeroFlag = 0ul;
+    uint32_t addr;
+
+    if(g_usbd_CtrlInSize) {
+        /* Process remained data */
+        if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) {
+            /* Data size > MXPLD */
+            addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
+            USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+            g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
+            g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+        } else {
+            /* Data size <= MXPLD */
+            addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
+            USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
+            if(g_usbd_CtrlInSize == g_usbd_CtrlMaxPktSize) {
+                u8ZeroFlag = (uint8_t)1ul;
+            }
+            g_usbd_CtrlInPointer = 0;
+            g_usbd_CtrlInSize = 0ul;
+        }
+    } else {
+        /* In ACK for Set address */
+        if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) {
+            addr = USBD_GET_ADDR();
+            if((addr != g_usbd_UsbAddr) && (addr == 0ul)) {
+                USBD_SET_ADDR(g_usbd_UsbAddr);
+            }
+        }
+
+        /* For the case of data size is integral times maximum packet size */
+        if(u8ZeroFlag) {
+            USBD_SET_PAYLOAD_LEN(EP0, 0ul);
+            u8ZeroFlag = (uint8_t)0ul;
+        }
+    }
+}
+
+/**
+  * @brief      Prepare the first Control OUT pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data received from USB host.
+  * @param[in]  u32Size The OUT transfer size.
+  *
+  * @return     None
+  *
+  * @details    This function is used to prepare the first Control OUT transfer.
+  *
+  */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    g_usbd_CtrlOutPointer = pu8Buf;
+    g_usbd_CtrlOutSize = 0ul;
+    g_usbd_CtrlOutSizeLimit = u32Size;
+    USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+}
+
+/**
+  * @brief    Repeat Control OUT pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the successive Control OUT transfer.
+  *
+  */
+void USBD_CtrlOut(void)
+{
+    uint32_t u32Size;
+    uint32_t addr;
+
+    if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) {
+        u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+        addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1);
+        USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size);
+        g_usbd_CtrlOutPointer += u32Size;
+        g_usbd_CtrlOutSize += u32Size;
+
+        if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) {
+            USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+        }
+
+    }
+}
+
+/**
+  * @brief    Reset software flags
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function resets all variables for protocol and resets USB device address to 0.
+  *
+  */
+void USBD_SwReset(void)
+{
+    uint32_t i;
+
+    /* Reset all variables for protocol */
+    g_usbd_CtrlInPointer = 0;
+    g_usbd_CtrlInSize = 0ul;
+    g_usbd_CtrlOutPointer = 0;
+    g_usbd_CtrlOutSize = 0ul;
+    g_usbd_CtrlOutSizeLimit = 0ul;
+    g_u32EpStallLock = 0ul;
+    memset(g_usbd_SetupPacket, 0, 8ul);
+
+    /* Reset PID DATA0 */
+    for(i=0ul; i<USBD_MAX_EP; i++) {
+        USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+    }
+
+    /* Reset USB device address */
+    USBD_SET_ADDR(0ul);
+}
+
+/**
+ * @brief       USBD Set Vendor Request
+ *
+ * @param[in]   pfnVendorReq    Vendor Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+    g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+/**
+ * @brief       The callback function which called when get SET CONFIGURATION request
+ *
+ * @param[in]   pfnSetConfigCallback    Callback function pointer for SET CONFIGURATION request
+ *
+ * @return      None
+ *
+ * @details     This function is used to set the callback function which will be called at SET CONFIGURATION request.
+ */
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
+{
+    g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
+}
+
+
+/**
+ * @brief       EP stall lock function to avoid stall clear by USB SET FEATURE request.
+ *
+ * @param[in]   u32EpBitmap    Use bitmap to select which endpoints will be locked
+ *
+ * @return      None
+ *
+ * @details     This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.
+ *              If ep stall locked, user needs to reset USB device or re-configure device to clear it.
+ */
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+    g_u32EpStallLock = u32EpBitmap;
+}
+
+
+/*@}*/ /* end of group M480_USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USBD_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,685 @@
+/**************************************************************************//**
+ * @file     usbd.h
+ * @version  V1.00
+ * @brief    M480 series USB driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __USBD_H__
+#define __USBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USBD_Driver USBD Driver
+  @{
+*/
+
+/** @addtogroup M480_USBD_EXPORTED_STRUCT USBD Exported Struct
+  @{
+*/
+typedef struct s_usbd_info {
+    uint8_t *gu8DevDesc;            /*!< Pointer for USB Device Descriptor          */
+    uint8_t *gu8ConfigDesc;         /*!< Pointer for USB Configuration Descriptor   */
+    uint8_t **gu8StringDesc;        /*!< Pointer for USB String Descriptor pointers */
+    uint8_t **gu8HidReportDesc;     /*!< Pointer for USB HID Report Descriptor      */
+    uint8_t *gu8BosDesc;            /*!< Pointer for USB BOS Descriptor             */
+    uint32_t *gu32HidReportSize;    /*!< Pointer for HID Report descriptor Size */
+    uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
+
+} S_USBD_INFO_T;  /*!< Device description structure */
+
+extern const S_USBD_INFO_T gsInfo;
+
+/*@}*/ /* end of group M480_USBD_EXPORTED_STRUCT */
+
+
+
+
+/** @addtogroup M480_USBD_EXPORTED_CONSTANTS USBD Exported Constants
+  @{
+*/
+#define USBD_BUF_BASE   (USBD_BASE+0x100ul)  /*!< USBD buffer base address \hideinitializer */
+#define USBD_MAX_EP     12ul /*!< Total EP number \hideinitializer */
+
+#define EP0     0ul       /*!< Endpoint 0 \hideinitializer */
+#define EP1     1ul       /*!< Endpoint 1 \hideinitializer */
+#define EP2     2ul       /*!< Endpoint 2 \hideinitializer */
+#define EP3     3ul       /*!< Endpoint 3 \hideinitializer */
+#define EP4     4ul       /*!< Endpoint 4 \hideinitializer */
+#define EP5     5ul       /*!< Endpoint 5 \hideinitializer */
+#define EP6     6ul       /*!< Endpoint 6 \hideinitializer */
+#define EP7     7ul       /*!< Endpoint 7 \hideinitializer */
+#define EP8     8ul       /*!< Endpoint 8 \hideinitializer */
+#define EP9     9ul       /*!< Endpoint 9 \hideinitializer */
+#define EP10    10ul      /*!< Endpoint 10 \hideinitializer */
+#define EP11    11ul      /*!< Endpoint 11 \hideinitializer */
+
+/** @cond HIDDEN_SYMBOLS */
+/* USB Request Type */
+#define REQ_STANDARD        0x00ul
+#define REQ_CLASS           0x20ul
+#define REQ_VENDOR          0x40ul
+
+/* USB Standard Request */
+#define GET_STATUS          0x00ul
+#define CLEAR_FEATURE       0x01ul
+#define SET_FEATURE         0x03ul
+#define SET_ADDRESS         0x05ul
+#define GET_DESCRIPTOR      0x06ul
+#define SET_DESCRIPTOR      0x07ul
+#define GET_CONFIGURATION   0x08ul
+#define SET_CONFIGURATION   0x09ul
+#define GET_INTERFACE       0x0Aul
+#define SET_INTERFACE       0x0Bul
+#define SYNC_FRAME          0x0Cul
+
+/* USB Descriptor Type */
+#define DESC_DEVICE         0x01ul
+#define DESC_CONFIG         0x02ul
+#define DESC_STRING         0x03ul
+#define DESC_INTERFACE      0x04ul
+#define DESC_ENDPOINT       0x05ul
+#define DESC_QUALIFIER      0x06ul
+#define DESC_OTHERSPEED     0x07ul
+#define DESC_IFPOWER        0x08ul
+#define DESC_OTG            0x09ul
+#define DESC_BOS            0x0Ful
+#define DESC_CAPABILITY     0x10ul
+
+/* USB Device Capability Type */
+#define CAP_WIRELESS        0x01ul
+#define CAP_USB20_EXT       0x02ul
+
+/* USB HID Descriptor Type */
+#define DESC_HID            0x21ul
+#define DESC_HID_RPT        0x22ul
+
+/* USB Descriptor Length */
+#define LEN_DEVICE          18ul
+#define LEN_QUALIFIER       10ul
+#define LEN_CONFIG          9ul
+#define LEN_INTERFACE       9ul
+#define LEN_ENDPOINT        7ul
+#define LEN_OTG             5ul
+#define LEN_BOS             5ul
+#define LEN_HID             9ul
+#define LEN_CCID            0x36ul
+#define LEN_BOSCAP          7ul
+
+/* USB Endpoint Type */
+#define EP_ISO              0x01
+#define EP_BULK             0x02
+#define EP_INT              0x03
+
+#define EP_INPUT            0x80
+#define EP_OUTPUT           0x00
+
+/* USB Feature Selector */
+#define FEATURE_DEVICE_REMOTE_WAKEUP    0x01ul
+#define FEATURE_ENDPOINT_HALT           0x00ul
+/** @endcond HIDDEN_SYMBOLS */
+
+/******************************************************************************/
+/*                USB Specific Macros                                         */
+/******************************************************************************/
+
+#define USBD_WAKEUP_EN          USBD_INTEN_WKEN_Msk         /*!< USB Wake-up Enable \hideinitializer */
+#define USBD_DRVSE0             USBD_SE0_SE0_Msk            /*!< Drive SE0 \hideinitializer */
+
+#define USBD_DPPU_EN            USBD_ATTR_DPPUEN_Msk        /*!< USB D+ Pull-up Enable \hideinitializer */
+#define USBD_PWRDN              USBD_ATTR_PWRDN_Msk         /*!< PHY Turn-On \hideinitializer */
+#define USBD_PHY_EN             USBD_ATTR_PHYEN_Msk         /*!< PHY Enable \hideinitializer */
+#define USBD_USB_EN             USBD_ATTR_USBEN_Msk         /*!< USB Enable \hideinitializer */
+
+#define USBD_INT_BUS            USBD_INTEN_BUSIEN_Msk       /*!< USB Bus Event Interrupt \hideinitializer */
+#define USBD_INT_USB            USBD_INTEN_USBIEN_Msk       /*!< USB Event Interrupt \hideinitializer */
+#define USBD_INT_FLDET          USBD_INTEN_VBDETIEN_Msk     /*!< USB VBUS Detection Interrupt \hideinitializer */
+#define USBD_INT_WAKEUP         (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk)     /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */
+
+#define USBD_INTSTS_WAKEUP      USBD_INTSTS_NEVWKIF_Msk     /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */
+#define USBD_INTSTS_FLDET       USBD_INTSTS_VBDETIF_Msk     /*!< USB Float Detect Interrupt Status \hideinitializer */
+#define USBD_INTSTS_BUS         USBD_INTSTS_BUSIF_Msk       /*!< USB Bus Event Interrupt Status \hideinitializer */
+#define USBD_INTSTS_USB         USBD_INTSTS_USBIF_Msk       /*!< USB Event Interrupt Status \hideinitializer */
+#define USBD_INTSTS_SETUP       USBD_INTSTS_SETUP_Msk       /*!< USB Setup Event \hideinitializer */
+#define USBD_INTSTS_EP0         USBD_INTSTS_EPEVT0_Msk      /*!< USB Endpoint 0 Event \hideinitializer */
+#define USBD_INTSTS_EP1         USBD_INTSTS_EPEVT1_Msk      /*!< USB Endpoint 1 Event \hideinitializer */
+#define USBD_INTSTS_EP2         USBD_INTSTS_EPEVT2_Msk      /*!< USB Endpoint 2 Event \hideinitializer */
+#define USBD_INTSTS_EP3         USBD_INTSTS_EPEVT3_Msk      /*!< USB Endpoint 3 Event \hideinitializer */
+#define USBD_INTSTS_EP4         USBD_INTSTS_EPEVT4_Msk      /*!< USB Endpoint 4 Event \hideinitializer */
+#define USBD_INTSTS_EP5         USBD_INTSTS_EPEVT5_Msk      /*!< USB Endpoint 5 Event \hideinitializer */
+#define USBD_INTSTS_EP6         USBD_INTSTS_EPEVT6_Msk      /*!< USB Endpoint 6 Event \hideinitializer */
+#define USBD_INTSTS_EP7         USBD_INTSTS_EPEVT7_Msk      /*!< USB Endpoint 7 Event \hideinitializer */
+#define USBD_INTSTS_EP8         USBD_INTSTS_EPEVT8_Msk      /*!< USB Endpoint 8 Event \hideinitializer */
+#define USBD_INTSTS_EP9         USBD_INTSTS_EPEVT9_Msk      /*!< USB Endpoint 9 Event \hideinitializer */
+#define USBD_INTSTS_EP10        USBD_INTSTS_EPEVT10_Msk     /*!< USB Endpoint 10 Event \hideinitializer */
+#define USBD_INTSTS_EP11        USBD_INTSTS_EPEVT11_Msk     /*!< USB Endpoint 11 Event \hideinitializer */
+
+#define USBD_STATE_USBRST       USBD_ATTR_USBRST_Msk        /*!< USB Bus Reset \hideinitializer */
+#define USBD_STATE_SUSPEND      USBD_ATTR_SUSPEND_Msk       /*!< USB Bus Suspend \hideinitializer */
+#define USBD_STATE_RESUME       USBD_ATTR_RESUME_Msk        /*!< USB Bus Resume \hideinitializer */
+#define USBD_STATE_TIMEOUT      USBD_ATTR_TOUT_Msk          /*!< USB Bus Timeout \hideinitializer */
+
+#define USBD_CFGP_SSTALL        USBD_CFGP_SSTALL_Msk        /*!< Set Stall \hideinitializer */
+#define USBD_CFG_CSTALL         USBD_CFG_CSTALL_Msk         /*!< Clear Stall \hideinitializer */
+
+#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable \hideinitializer */
+#define USBD_CFG_EPMODE_OUT     (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint \hideinitializer */
+#define USBD_CFG_EPMODE_IN      (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint \hideinitializer */
+#define USBD_CFG_TYPE_ISO       (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */
+
+
+
+/*@}*/ /* end of group M480_USBD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+/**
+  * @brief      Compare two input numbers and return maximum one.
+  *
+  * @param[in]  a   First number to be compared.
+  * @param[in]  b   Second number to be compared.
+  *
+  * @return     Maximum value between a and b.
+  *
+  * @details    If a > b, then return a. Otherwise, return b.
+  * \hideinitializer
+  */
+#define USBD_Maximum(a,b)        ((a)>(b) ? (a) : (b))
+
+
+/**
+  * @brief      Compare two input numbers and return minimum one
+  *
+  * @param[in]  a   First number to be compared
+  * @param[in]  b   Second number to be compared
+  *
+  * @return     Minimum value between a and b
+  *
+  * @details    If a < b, then return a. Otherwise, return b.
+  * \hideinitializer
+  */
+#define USBD_Minimum(a,b)        ((a)<(b) ? (a) : (b))
+
+
+/**
+  * @brief    Enable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB and PHY.
+  * \hideinitializer
+  */
+#define USBD_ENABLE_USB()           ((uint32_t)(USBD->ATTR |= 0x7D0))
+
+/**
+  * @brief    Disable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB.
+  * \hideinitializer
+  */
+#define USBD_DISABLE_USB()          ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
+
+/**
+  * @brief    Enable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB PHY.
+  * \hideinitializer
+  */
+#define USBD_ENABLE_PHY()           ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
+
+/**
+  * @brief    Disable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB PHY.
+  * \hideinitializer
+  */
+#define USBD_DISABLE_PHY()          ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
+
+/**
+  * @brief    Enable SE0. Force USB PHY transceiver to drive SE0.
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
+  * \hideinitializer
+  */
+#define USBD_SET_SE0()              ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
+
+/**
+  * @brief    Disable SE0
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
+  * \hideinitializer
+  */
+#define USBD_CLR_SE0()              ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
+
+/**
+  * @brief       Set USB device address
+  *
+  * @param[in]   addr The USB device address.
+  *
+  * @return      None
+  *
+  * @details     Write USB device address to USB_FADDR register.
+  * \hideinitializer
+  */
+#define USBD_SET_ADDR(addr)         (USBD->FADDR = (addr))
+
+/**
+  * @brief    Get USB device address
+  *
+  * @param    None
+  *
+  * @return   USB device address
+  *
+  * @details  Read USB_FADDR register to get USB device address.
+  * \hideinitializer
+  */
+#define USBD_GET_ADDR()             ((uint32_t)(USBD->FADDR))
+
+/**
+  * @brief      Enable USB interrupt function
+  *
+  * @param[in]  intr The combination of the specified interrupt enable bits.
+  *             Each bit corresponds to a interrupt enable bit.
+  *             This parameter decides which interrupts will be enabled.
+  *             (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
+  *
+  * @return     None
+  *
+  * @details    Enable USB related interrupt functions specified by intr parameter.
+  * \hideinitializer
+  */
+#define USBD_ENABLE_INT(intr)       (USBD->INTEN |= (intr))
+
+/**
+  * @brief    Get interrupt status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_INTSTS register
+  *
+  * @details  Return all interrupt flags of USB_INTSTS register.
+  * \hideinitializer
+  */
+#define USBD_GET_INT_FLAG()         ((uint32_t)(USBD->INTSTS))
+
+/**
+  * @brief      Clear USB interrupt flag
+  *
+  * @param[in]  flag The combination of the specified interrupt flags.
+  *             Each bit corresponds to a interrupt source.
+  *             This parameter decides which interrupt flags will be cleared.
+  *             (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
+  *
+  * @return     None
+  *
+  * @details    Clear USB related interrupt flags specified by flag parameter.
+  * \hideinitializer
+  */
+#define USBD_CLR_INT_FLAG(flag)     (USBD->INTSTS = (flag))
+
+/**
+  * @brief    Get endpoint status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_EPSTS register.
+  *
+  * @details  Return all endpoint status.
+  * \hideinitializer
+  */
+#define USBD_GET_EP_FLAG()          ((uint32_t)(USBD->EPSTS))
+
+/**
+  * @brief    Get USB bus state
+  *
+  * @param    None
+  *
+  * @return   The value of USB_ATTR[3:0].
+  *           Bit 0 indicates USB bus reset status.
+  *           Bit 1 indicates USB bus suspend status.
+  *           Bit 2 indicates USB bus resume status.
+  *           Bit 3 indicates USB bus time-out status.
+  *
+  * @details  Return USB_ATTR[3:0] for USB bus events.
+  * \hideinitializer
+  */
+#define USBD_GET_BUS_STATE()        ((uint32_t)(USBD->ATTR & 0xf))
+
+/**
+  * @brief    Check cable connection state
+  *
+  * @param    None
+  *
+  * @retval   0 USB cable is not attached.
+  * @retval   1 USB cable is attached.
+  *
+  * @details  Check the connection state by FLDET bit of USB_FLDET register.
+  * \hideinitializer
+  */
+#define USBD_IS_ATTACHED()          ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
+
+/**
+  * @brief      Stop USB transaction of the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
+  * \hideinitializer
+  */
+#define USBD_STOP_TRANSACTION(ep)   (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
+
+/**
+  * @brief      Set USB DATA1 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+  * \hideinitializer
+  */
+#define USBD_SET_DATA1(ep)          (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
+
+/**
+  * @brief      Set USB DATA0 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+  * \hideinitializer
+  */
+#define USBD_SET_DATA0(ep)          (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
+
+/**
+  * @brief      Set USB payload size (IN data)
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  size The transfer length.
+  *
+  * @return     None
+  *
+  * @details    This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
+  * \hideinitializer
+  */
+#define USBD_SET_PAYLOAD_LEN(ep, size)  (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
+
+/**
+  * @brief      Get USB payload size (OUT data)
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     The value of USB_MXPLDx register.
+  *
+  * @details    Get the data length of OUT data transaction by reading USB_MXPLDx register.
+  * \hideinitializer
+  */
+#define USBD_GET_PAYLOAD_LEN(ep)        ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
+
+/**
+  * @brief      Configure endpoint
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  config The USB configuration.
+  *
+  * @return     None
+  *
+  * @details    This macro will write config parameter to USB_CFGx register of specified endpoint ID.
+  * \hideinitializer
+  */
+#define USBD_CONFIG_EP(ep, config)      (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
+
+/**
+  * @brief      Set USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  offset The SRAM offset.
+  *
+  * @return     None
+  *
+  * @details    This macro will set the SRAM offset for the specified endpoint ID.
+  * \hideinitializer
+  */
+#define USBD_SET_EP_BUF_ADDR(ep, offset)    (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
+
+/**
+  * @brief      Get the offset of the specified USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     The offset of the specified endpoint buffer.
+  *
+  * @details    This macro will return the SRAM offset of the specified endpoint ID.
+  * \hideinitializer
+  */
+#define USBD_GET_EP_BUF_ADDR(ep)        ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+  * \hideinitializer
+  */
+#define USBD_SET_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+  * \hideinitializer
+  */
+#define USBD_CLR_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state of the specified endpoint ID.
+  * \hideinitializer
+  */
+#define USBD_GET_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief      To support byte access between USB SRAM and system SRAM
+  *
+  * @param[in]  dest Destination pointer.
+  *
+  * @param[in]  src  Source pointer.
+  *
+  * @param[in]  size Byte count.
+  *
+  * @return     None
+  *
+  * @details    This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+  *
+  */
+static __INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)
+{
+    uint32_t volatile i=0ul;
+
+    while(size--)
+    {
+        dest[i] = src[i];
+        i++;
+    }
+}
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state. Endpoint will respond STALL token automatically.
+  *
+  */
+static __INLINE void USBD_SetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    uint32_t i;
+
+    for(i = 0ul; i < USBD_MAX_EP; i++) {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xful) == epnum) {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
+  */
+static __INLINE void USBD_ClearStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    uint32_t i;
+
+    for(i = 0ul; i < USBD_MAX_EP; i++) {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xful) == epnum) {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state.
+  *
+  */
+static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    uint32_t i;
+
+    for(i = 0ul; i < USBD_MAX_EP; i++) {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xful) == epnum) {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            break;
+        }
+    }
+
+    return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
+}
+
+
+extern volatile uint8_t g_usbd_RemoteWakeupEn;
+
+
+typedef void (*VENDOR_REQ)(void);           /*!< Functional pointer type definition for Vendor class */
+typedef void (*CLASS_REQ)(void);            /*!< Functional pointer type declaration for USB class request callback handler */
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface);    /*!< Functional pointer type declaration for USB set interface request callback handler */
+typedef void (*SET_CONFIG_CB)(void);       /*!< Functional pointer type declaration for USB set configuration request callback handler */
+
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+/*@}*/ /* end of group M480_USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USBD_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__USBD_H__*/
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_i2c.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,564 @@
+/****************************************************************************//**
+ * @file     usci_i2c.c
+ * @version  V3.00
+ * @brief    M480 series USCI I2C(UI2C) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_I2C_Driver USCI_I2C Driver
+  @{
+*/
+
+
+/** @addtogroup M480_USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        This function makes USCI_I2C module be ready and set the wanted bus clock
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32BusClock     The target bus speed of USCI_I2C module.
+ *
+ *    @return       Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format).
+ */
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if( ui2c == UI2C0 ) {
+        u32Pclk = CLK_GetPCLK0Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */
+
+    /* Enable USCI_I2C protocol */
+    ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+    ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos;
+
+    /* Data format configuration */
+    /* 8 bit data length */
+    ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk;
+    ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos;
+
+    /* MSB data format */
+    ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk;
+
+    /* Set USCI_I2C bus clock */
+    ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+    ui2c->BRGEN |=  (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+    ui2c->PROTCTL |=  UI2C_PROTCTL_PROTEN_Msk;
+
+    return ( u32Pclk / ((u32ClkDiv+1U)<<1U) );
+}
+
+/**
+ *    @brief        This function closes the USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Close USCI_I2C protocol function.
+ */
+void UI2C_Close(UI2C_T *ui2c)
+{
+    /* Disable USCI_I2C function */
+    ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+}
+
+/**
+ *    @brief        This function clears the time-out flag
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Clear time-out flag when time-out flag is set.
+ */
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c)
+{
+    ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+}
+
+/**
+ *    @brief        This function sets the control bit of the USCI_I2C module.
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Start         Set START bit to USCI_I2C module.
+ *    @param[in]    u8Stop Set      STOP bit to USCI_I2C module.
+ *    @param[in]    u8Ptrg Set      PTRG bit to USCI_I2C module.
+ *    @param[in]    u8Ack Set       ACK bit to USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      The function set USCI_I2C control bit of USCI_I2C bus protocol.
+ */
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack)
+{
+    uint32_t u32Reg = 0U;
+    uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk);
+
+    if (u8Start) {
+        u32Reg |= UI2C_PROTCTL_STA_Msk;
+    }
+    if (u8Stop) {
+        u32Reg |= UI2C_PROTCTL_STO_Msk;
+    }
+    if (u8Ptrg) {
+        u32Reg |= UI2C_PROTCTL_PTRG_Msk;
+    }
+    if (u8Ack) {
+        u32Reg |= UI2C_PROTCTL_AA_Msk;
+    }
+
+    ui2c->PROTCTL = u32Val | u32Reg;
+}
+
+/**
+ *    @brief        This function disables the interrupt of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt enable bits.
+ *                                  Each bit corresponds to an interrupt enable bit.
+ *                                  This parameter decides which interrupts will be disabled. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable USCI_I2C bus interrupt events.
+ */
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    /* Disable time-out interrupt flag */
+    if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk;
+    }
+
+    /* Disable start condition received interrupt flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk;
+    }
+
+    /* Disable stop condition received interrupt flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk;
+    }
+
+    /* Disable non-acknowledge interrupt flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk;
+    }
+
+    /* Disable arbitration lost interrupt flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk;
+    }
+
+    /* Disable error interrupt flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk;
+    }
+
+    /* Disable acknowledge interrupt flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk;
+    }
+}
+
+/**
+ *    @brief        This function enables the interrupt of USCI_I2C module.
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt enable bits.
+ *                                  Each bit corresponds to a interrupt enable bit.
+ *                                  This parameter decides which interrupts will be enabled. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *    @return None
+ *
+ *    @details      The function is used to enable USCI_I2C bus interrupt events.
+ */
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    /* Enable time-out interrupt flag */
+    if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk;
+    }
+
+    /* Enable start condition received interrupt flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk;
+    }
+
+    /* Enable stop condition received interrupt flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk;
+    }
+
+    /* Enable non-acknowledge interrupt flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk;
+    }
+
+    /* Enable arbitration lost interrupt flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk;
+    }
+
+    /* Enable error interrupt flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk;
+    }
+
+    /* Enable acknowledge interrupt flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk;
+    }
+}
+
+/**
+ *    @brief        This function returns the real bus clock of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      The function returns the actual USCI_I2C module bus clock.
+ */
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c)
+{
+    uint32_t u32Divider;
+    uint32_t u32Pclk;
+
+    if (ui2c == UI2C0) {
+        u32Pclk = CLK_GetPCLK0Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos;
+
+    return ( u32Pclk / ((u32Divider+1U)<<1U) );
+}
+
+/**
+ *    @brief        This function sets bus clock frequency of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32BusClock     The target bus speed of USCI_I2C module.
+ *
+ *    @return Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      Use this function set USCI_I2C bus clock frequency and return actual bus clock.
+ */
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if( ui2c == UI2C0 ) {
+        u32Pclk = CLK_GetPCLK0Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */
+
+    /* Set USCI_I2C bus clock */
+    ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+    ui2c->BRGEN |=  (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+
+    return ( u32Pclk / ((u32ClkDiv+1U)<<1U) );
+}
+
+/**
+ *    @brief        This function gets the interrupt flag of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt sources.
+ *                                  Each bit corresponds to a interrupt source.
+ *                                  This parameter decides which interrupt flags will be read. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       Interrupt flags of selected sources.
+ *
+ *    @details      Use this function to get USCI_I2C interrupt flag when module occurs interrupt event.
+ */
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0U;
+    uint32_t u32TmpValue;
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk;
+    /* Check Time-out Interrupt Flag */
+    if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_TO_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk;
+    /* Check Start Condition Received Interrupt Flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_STAR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk;
+    /* Check Stop Condition Received Interrupt Flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_STOR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk;
+    /* Check Non-Acknowledge Interrupt Flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_NACK_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk;
+    /* Check Arbitration Lost Interrupt Flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_ARBLO_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk;
+    /* Check Error Interrupt Flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_ERR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk;
+    /* Check Acknowledge Interrupt Flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) {
+        u32IntFlag |= UI2C_ACK_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+ *    @brief        This function clears the interrupt flag of USCI_I2C module.
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt sources.
+ *                                  Each bit corresponds to a interrupt source.
+ *                                  This parameter decides which interrupt flags will be cleared. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag.
+ */
+void UI2C_ClearIntFlag(UI2C_T *ui2c , uint32_t u32Mask)
+{
+    /* Clear Time-out Interrupt Flag */
+    if(u32Mask & UI2C_TO_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+    }
+
+    /* Clear Start Condition Received Interrupt Flag */
+    if(u32Mask & UI2C_STAR_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk;
+    }
+
+    /* Clear Stop Condition Received Interrupt Flag */
+    if(u32Mask & UI2C_STOR_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk;
+    }
+
+    /* Clear Non-Acknowledge Interrupt Flag */
+    if(u32Mask & UI2C_NACK_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk;
+    }
+
+    /* Clear Arbitration Lost Interrupt Flag */
+    if(u32Mask & UI2C_ARBLO_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk;
+    }
+
+    /* Clear Error Interrupt Flag */
+    if(u32Mask & UI2C_ERR_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk;
+    }
+
+    /* Clear Acknowledge Interrupt Flag */
+    if(u32Mask & UI2C_ACK_INT_MASK) {
+        ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk;
+    }
+}
+
+/**
+ *    @brief        This function returns the data stored in data register of USCI_I2C module.
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       USCI_I2C data.
+ *
+ *    @details      To read a byte data from USCI_I2C module receive data register.
+ */
+uint32_t UI2C_GetData(UI2C_T *ui2c)
+{
+    return ( ui2c->RXDAT );
+}
+
+/**
+ *    @brief        This function writes a byte data to data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Data          The data which will be written to data register of USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To write a byte data to transmit data register to transmit data.
+ */
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data)
+{
+    ui2c->TXDAT = u8Data;
+}
+
+/**
+ *    @brief        Configure slave address and enable GC mode
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8SlaveNo       Slave channel number [0/1]
+ *    @param[in]    u16SlaveAddr    The slave address.
+ *    @param[in]    u8GCMode        GC mode enable or not. Valid values are:
+ *                                  - \ref UI2C_GCMODE_ENABLE
+ *                                  - \ref UI2C_GCMODE_DISABLE
+ *
+ *    @return None
+ *
+ *    @details      To configure USCI_I2C module slave address and GC mode.
+ */
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode)
+{
+    if(u8SlaveNo) {
+        ui2c->DEVADDR1  = u16SlaveAddr;
+    } else {
+        ui2c->DEVADDR0  = u16SlaveAddr;
+    }
+
+    ui2c->PROTCTL  = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode;
+}
+
+/**
+ *    @brief        Configure the mask bit of slave address.
+ *
+ *    @param[in]    ui2c             The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8SlaveNo        Slave channel number [0/1]
+ *    @param[in]    u16SlaveAddrMask The slave address mask.
+ *
+ *    @return None
+ *
+ *    @details      To configure USCI_I2C module slave  address mask bit.
+ *    @note         The corresponding address bit is "Don't Care".
+ */
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask)
+{
+    if(u8SlaveNo) {
+        ui2c->ADDRMSK1  = u16SlaveAddrMask;
+    } else {
+        ui2c->ADDRMSK0  = u16SlaveAddrMask;
+    }
+}
+
+/**
+ *    @brief        This function enables time-out function and configures timeout counter
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32TimeoutCnt   Timeout counter. Valid values are between 0~0x3FF
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C bus time-out function and set time-out counter.
+ */
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt)
+{
+    ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos);
+    ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ *    @brief        This function disables time-out function
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To disable USCI_I2C bus time-out function.
+ */
+void UI2C_DisableTimeout(UI2C_T *ui2c)
+{
+    ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk;
+    ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ *    @brief        This function enables the wakeup function of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8WakeupMode    The wake-up mode selection. Valid values are:
+ *                                  - \ref UI2C_DATA_TOGGLE_WK
+ *                                  - \ref UI2C_ADDR_MATCH_WK
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C module wake-up function.
+ */
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode)
+{
+    ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk);
+}
+
+/**
+ *    @brief        This function disables the wakeup function of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To disable USCI_I2C module wake-up function.
+ */
+void UI2C_DisableWakeup(UI2C_T *ui2c)
+{
+    ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk;
+}
+
+/*@}*/ /* end of group M480_USCI_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USCI_I2C_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_i2c.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,317 @@
+/**************************************************************************//**
+ * @file     USCI_I2C.h
+ * @version  V3.0
+ * @brief    M480 series USCI I2C(UI2C) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __USCI_I2C_H__
+#define __USCI_I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_I2C_Driver USCI_I2C Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C master event definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_MASTER_EVENT {
+    MASTER_SEND_ADDRESS = 10,    /*!< Master send address to Slave */
+    MASTER_SEND_H_WR_ADDRESS,    /*!< Master send High address to Slave */
+    MASTER_SEND_H_RD_ADDRESS,    /*!< Master send address to Slave (Read ADDR) */
+    MASTER_SEND_L_ADDRESS,       /*!< Master send Low address to Slave */
+    MASTER_SEND_DATA,            /*!< Master Send Data to Slave */
+    MASTER_SEND_REPEAT_START,    /*!< Master send repeat start to Slave */
+    MASTER_READ_DATA,            /*!< Master Get Data from Slave */
+    MASTER_STOP,                 /*!< Master send stop to Slave */
+    MASTER_SEND_START            /*!< Master send start to Slave */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C slave event definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_SLAVE_EVENT {
+    SLAVE_ADDRESS_ACK = 100,      /*!< Slave send address ACK */
+    SLAVE_H_WR_ADDRESS_ACK,       /*!< Slave send High address ACK */
+    SLAVE_L_WR_ADDRESS_ACK,       /*!< Slave send Low address ACK */
+    SLAVE_GET_DATA,               /*!< Slave Get Data from Master (Write CMD) */
+    SLAVE_SEND_DATA,              /*!< Slave Send Data to Master (Read CMD) */
+    SLAVE_H_RD_ADDRESS_ACK,       /*!< Slave send High address ACK */
+    SLAVE_L_RD_ADDRESS_ACK        /*!< Slave send Low address ACK */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_CTL constant definitions.                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_CTL_PTRG              0x20UL    /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */
+#define UI2C_CTL_STA               0x08UL    /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
+#define UI2C_CTL_STO               0x04UL    /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
+#define UI2C_CTL_AA                0x02UL    /*!< USCI_CTL setting for I2C control bits. It would set AA bit  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_I2C GCMode constant definitions.                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_GCMODE_ENABLE         (1U)    /*!< Enable  USCI_I2C GC Mode \hideinitializer */
+#define UI2C_GCMODE_DISABLE        (0U)    /*!< Disable USCI_I2C GC Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_I2C Wakeup Mode constant definitions.                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_DATA_TOGGLE_WK        (0x0U << UI2C_WKCTL_WKADDREN_Pos)    /*!< Wakeup according data toggle \hideinitializer */
+#define UI2C_ADDR_MATCH_WK         (0x1U << UI2C_WKCTL_WKADDREN_Pos)    /*!< Wakeup according address match \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C interrupt mask definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_TO_INT_MASK           (0x001U)    /*!< Time-out interrupt mask \hideinitializer */
+#define UI2C_STAR_INT_MASK         (0x002U)    /*!< Start condition received interrupt mask \hideinitializer */
+#define UI2C_STOR_INT_MASK         (0x004U)    /*!< Stop condition received interrupt mask \hideinitializer */
+#define UI2C_NACK_INT_MASK         (0x008U)    /*!< Non-acknowledge interrupt mask \hideinitializer */
+#define UI2C_ARBLO_INT_MASK        (0x010U)    /*!< Arbitration lost interrupt mask \hideinitializer */
+#define UI2C_ERR_INT_MASK          (0x020U)    /*!< Error interrupt mask \hideinitializer */
+#define UI2C_ACK_INT_MASK          (0x040U)    /*!< Acknowledge interrupt mask \hideinitializer */
+
+/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        This macro sets the USCI_I2C protocol control register at one time
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Ctrl    Set the register value of USCI_I2C control register.
+ *
+ *    @return       None
+ *
+ *    @details      Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK.
+ *    \hideinitializer 
+ */
+#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl))
+
+/**
+ *    @brief        This macro only set START bit to protocol control register of USCI_I2C module.
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
+ *    \hideinitializer 
+ */
+#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
+
+/**
+ *    @brief        This macro only set STOP bit to the control register of USCI_I2C module
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
+ *    \hideinitializer 
+ */
+#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
+
+/**
+ *    @brief        This macro returns the data stored in data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       Data
+ *
+ *    @details      Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
+ *    \hideinitializer 
+ */
+#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)
+
+/**
+ *    @brief        This macro writes the data to data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Data   The data which will be written to data register of USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
+ *    \hideinitializer 
+ */
+#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))
+
+/**
+ *    @brief        This macro returns time-out flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @retval       0        USCI_I2C bus time-out is not happened
+ *    @retval       1        USCI_I2C bus time-out is happened
+ *
+ *    @details      USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
+ *    \hideinitializer 
+ */
+#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
+
+/**
+ *    @brief        This macro returns wake-up flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @retval       0        Chip is not woken-up from power-down mode
+ *    @retval       1        Chip is woken-up from power-down mode
+ *
+ *    @details      USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
+ *    \hideinitializer 
+ */
+#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
+
+/**
+ *    @brief        This macro is used to clear USCI_I2C wake-up flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      If USCI_I2C wake-up flag is set, use this macro to clear it.
+ *    \hideinitializer 
+ */
+#define UI2C_CLR_WAKEUP_FLAG(ui2c)  ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)
+
+/**
+ *    @brief        This macro disables the USCI_I2C 10-bit address mode
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
+ *    \hideinitializer 
+ */
+#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c)  ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
+
+/**
+ *    @brief        This macro enables the 10-bit address mode
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C 10-bit address match function.
+ *    \hideinitializer 
+ */
+#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c)  ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
+
+/**
+ *    @brief        This macro gets USCI_I2C protocol interrupt flag or bus status
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       A word data of USCI_I2C_PROTSTS register
+ *
+ *    @details      Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
+ *    \hideinitializer 
+ */
+#define UI2C_GET_PROT_STATUS(ui2c)    ((ui2c)->PROTSTS)
+
+/**
+ *    @brief        This macro clears specified protocol interrupt flag
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref UI2C_PROTSTS_ACKIF_Msk
+ *                                  - \ref UI2C_PROTSTS_ERRIF_Msk
+ *                                  - \ref UI2C_PROTSTS_ARBLOIF_Msk
+ *                                  - \ref UI2C_PROTSTS_NACKIF_Msk
+ *                                  - \ref UI2C_PROTSTS_STORIF_Msk
+ *                                  - \ref UI2C_PROTSTS_STARIF_Msk
+ *                                  - \ref UI2C_PROTSTS_TOIF_Msk
+ *    @return None
+ *
+ *    @details      To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
+ *    \hideinitializer 
+ */
+#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag)    ((ui2c)->PROTSTS = (u32IntTypeFlag))
+
+/**
+ *    @brief        This macro enables specified protocol interrupt
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntSel Interrupt Type, should be
+ *                                  - \ref UI2C_PROTIEN_ACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ERRIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_NACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STORIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STARIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_TOIEN_Msk
+ *    @return None
+ *
+ *    @details      Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
+ *    \hideinitializer 
+ */
+#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel)    ((ui2c)->PROTIEN |= (u32IntSel))
+
+/**
+ *    @brief        This macro disables specified protocol interrupt
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntSel Interrupt Type, should be
+ *                                  - \ref UI2C_PROTIEN_ACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ERRIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_NACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STORIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STARIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_TOIEN_Msk
+ *    @return None
+ *
+ *    @details      Clear specified USCI_I2C protocol interrupt bits to disable interrupt function.
+ *    \hideinitializer 
+ */
+#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel)    ((ui2c)->PROTIEN &= ~ (u32IntSel))
+
+
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);
+void UI2C_Close(UI2C_T *ui2c);
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_ClearIntFlag(UI2C_T* ui2c , uint32_t u32Mask);
+uint32_t UI2C_GetData(UI2C_T *ui2c);
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);
+void UI2C_DisableTimeout(UI2C_T *ui2c);
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);
+void UI2C_DisableWakeup(UI2C_T *ui2c);
+
+/*@}*/ /* end of group M480_USCI_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USCI_I2C_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_spi.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,553 @@
+/****************************************************************************//**
+ * @file     usci_spi.c
+ * @version  V3.00
+ * @brief    M480 series USCI_SPI driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_SPI_Driver USCI_SPI Driver
+  @{
+*/
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  This function make USCI_SPI module be ready to transfer.
+  *         By default, the USCI_SPI transfer sequence is MSB first, the slave selection
+  *         signal is active low and the automatic slave select function is disabled. In
+  *         Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
+  *         divider setting will be 0.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
+  *                    - \ref USPI_SLAVE
+  *                    - \ref USPI_MASTER
+  * @param[in]  u32SPIMode Decide the transfer timing. Valid values are:
+  *                    - \ref USPI_MODE_0
+  *                    - \ref USPI_MODE_1
+  *                    - \ref USPI_MODE_2
+  *                    - \ref USPI_MODE_3
+  * @param[in]  u32DataWidth The data width of a USCI_SPI transaction.
+  * @param[in]  u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
+  * @return Actual frequency of USCI_SPI peripheral clock.
+  */
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv = 0ul;
+    uint32_t u32Pclk;
+    uint32_t u32UspiClk = 0ul;
+
+    if(uspi == (USPI_T *)USPI0) {
+        u32Pclk = CLK_GetPCLK0Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    if(u32BusClock != 0ul) {
+        u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
+    } else {}
+
+    /* Enable USCI_SPI protocol */
+    uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+    uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos;
+
+    /* Data format configuration */
+    if(u32DataWidth == 16ul) {
+        u32DataWidth = 0ul;
+    } else {}
+    uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
+    uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
+
+    /* MSB data format */
+    uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
+
+    /* Set slave selection signal active low */
+    if(u32MasterSlave == USPI_MASTER) {
+        uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
+    } else {
+        uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
+    }
+
+    /* Set operating mode and transfer timing */
+    uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
+    uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
+
+    /* Set USCI_SPI bus clock */
+    uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+    uspi->BRGEN |=  (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+    uspi->PROTCTL |=  USPI_PROTCTL_PROTEN_Msk;
+
+    if(u32BusClock != 0ul) {
+        u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) );
+    } else {}
+
+    return u32UspiClk;
+}
+
+/**
+  * @brief Disable USCI_SPI function mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_Close(USPI_T *uspi)
+{
+    uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+}
+
+/**
+  * @brief Clear Rx buffer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_ClearRxBuf(USPI_T *uspi)
+{
+    uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
+}
+
+/**
+  * @brief Clear Tx buffer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_ClearTxBuf(USPI_T *uspi)
+{
+    uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
+}
+
+/**
+  * @brief Disable the automatic slave select function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_DisableAutoSS(USPI_T *uspi)
+{
+    uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
+}
+
+/**
+  * @brief Enable the automatic slave select function. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32SSPinMask This parameter is not used.
+  * @param[in]  u32ActiveLevel The active level of slave select signal. Valid values are:
+  *                     - \ref USPI_SS_ACTIVE_HIGH
+  *                     - \ref USPI_SS_ACTIVE_LOW
+  * @return None
+  */
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
+    uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
+}
+
+/**
+  * @brief Set the USCI_SPI bus clock. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32BusClock The expected frequency of USCI_SPI bus clock.
+  * @return Actual frequency of USCI_SPI peripheral clock.
+  */
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if(uspi == USPI0) {
+        u32Pclk = CLK_GetPCLK0Freq();
+    } else {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
+
+    /* Set USCI_SPI bus clock */
+    uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+    uspi->BRGEN |=  (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+
+    return ( u32Pclk / ((u32ClkDiv+1ul)<<1) );
+}
+
+/**
+  * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Actual USCI_SPI bus clock frequency.
+  */
+uint32_t USPI_GetBusClock(USPI_T *uspi)
+{
+    uint32_t u32BusClk;
+    uint32_t u32ClkDiv;
+
+    u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
+
+    if(uspi == USPI0) {
+        u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) );
+    } else {
+        u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) );
+    }
+
+    return u32BusClk;
+}
+
+/**
+  * @brief Enable related interrupts specified by u32Mask parameter.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *         Each bit corresponds to a interrupt bit.
+  *         This parameter decides which interrupts will be enabled. Valid values are:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) {
+        uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
+    } else {}
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) {
+        uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
+    } else {}
+    /* Enable slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) {
+        uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
+    } else {}
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) {
+        uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
+    } else {}
+    /* Enable TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) {
+        uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
+    } else {}
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) {
+        uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
+    } else {}
+    /* Enable TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) {
+        uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
+    } else {}
+    /* Enable TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) {
+        uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
+    } else {}
+    /* Enable RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) {
+        uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
+    } else {}
+    /* Enable RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) {
+        uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
+    } else {}
+}
+
+/**
+  * @brief Disable related interrupts specified by u32Mask parameter.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *         Each bit corresponds to a interrupt bit.
+  *         This parameter decides which interrupts will be disabled. Valid values are:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
+    } else {}
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
+    } else {}
+    /* Disable slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
+    } else {}
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
+    } else {}
+    /* Disable TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) {
+        uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
+    } else {}
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) {
+        uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
+    } else {}
+    /* Disable TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) {
+        uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
+    } else {}
+    /* Disable TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) {
+        uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
+    } else {}
+    /* Disable RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) {
+        uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
+    } else {}
+    /* Disable RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) {
+        uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
+    } else {}
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *         Each bit corresponds to a interrupt source.
+  *         This parameter decides which interrupt flags will be read. It is combination of:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return Interrupt flags of selected sources.
+  */
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+    uint32_t u32TmpFlag;
+    uint32_t u32IntFlag = 0ul;
+
+    /* Check slave selection signal inactive interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk;
+    if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK)  && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) ) {
+        u32IntFlag |= USPI_SSINACT_INT_MASK;
+    } else {}
+    /* Check slave selection signal active interrupt flag */
+
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk;
+    if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) {
+        u32IntFlag |= USPI_SSACT_INT_MASK;
+    } else {}
+
+    /* Check slave time-out interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk;
+    if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) {
+        u32IntFlag |= USPI_SLVTO_INT_MASK;
+    } else {}
+
+    /* Check slave bit count error interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk;
+    if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) {
+        u32IntFlag |= USPI_SLVBE_INT_MASK;
+    } else {}
+
+    /* Check TX under run interrupt flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk;
+    if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) {
+        u32IntFlag |= USPI_TXUDR_INT_MASK;
+    } else {}
+
+    /* Check RX overrun interrupt flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk;
+    if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) {
+        u32IntFlag |= USPI_RXOV_INT_MASK;
+    } else {}
+
+    /* Check TX start interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk;
+    if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) {
+        u32IntFlag |= USPI_TXST_INT_MASK;
+    } else {}
+
+    /* Check TX end interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk;
+    if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) {
+        u32IntFlag |= USPI_TXEND_INT_MASK;
+    } else {}
+
+    /* Check RX start interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk;
+    if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) {
+        u32IntFlag |= USPI_RXST_INT_MASK;
+    } else {}
+
+    /* Check RX end interrupt flag */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk;
+    if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) {
+        u32IntFlag |= USPI_RXEND_INT_MASK;
+    } else {}
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *         Each bit corresponds to a interrupt source.
+  *         This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Clear slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
+    } else {}
+    /* Clear slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
+    } else {}
+    /* Clear slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
+    } else {}
+    /* Clear slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
+    } else {}
+    /* Clear TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) {
+        uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
+    } else {}
+    /* Clear RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) {
+        uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
+    } else {}
+    /* Clear TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
+    } else {}
+    /* Clear TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
+    } else {}
+    /* Clear RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
+    } else {}
+
+    /* Clear RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) {
+        uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
+    } else {}
+}
+
+/**
+  * @brief  Get USCI_SPI status.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *         Each bit corresponds to a source.
+  *         This parameter decides which flags will be read. It is combination of:
+  *           - \ref USPI_BUSY_MASK
+  *           - \ref USPI_RX_EMPTY_MASK
+  *           - \ref USPI_RX_FULL_MASK
+  *           - \ref USPI_TX_EMPTY_MASK
+  *           - \ref USPI_TX_FULL_MASK
+  *           - \ref USPI_SSLINE_STS_MASK
+  * @return Flags of selected sources.
+  */
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
+{
+    uint32_t u32Flag = 0ul;
+    uint32_t u32TmpFlag;
+
+    /* Check busy status */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk;
+    if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) {
+        u32Flag |= USPI_BUSY_MASK;
+    } else {}
+
+    /* Check RX empty flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk;
+    if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) {
+        u32Flag |= USPI_RX_EMPTY_MASK;
+    } else {}
+
+    /* Check RX full flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk;
+    if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) {
+        u32Flag |= USPI_RX_FULL_MASK;
+    } else {}
+
+    /* Check TX empty flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk;
+    if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) {
+        u32Flag |= USPI_TX_EMPTY_MASK;
+    } else {}
+
+    /* Check TX full flag */
+    u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk;
+    if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) {
+        u32Flag |= USPI_TX_FULL_MASK;
+    } else {}
+
+    /* Check USCI_SPI_SS line status */
+    u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk;
+    if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) {
+        u32Flag |= USPI_SSLINE_STS_MASK;
+    } else {}
+    return u32Flag;
+}
+
+/**
+  * @brief  Enable USCI_SPI Wake-up Function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_EnableWakeup(USPI_T *uspi)
+{
+    uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
+}
+
+/**
+  * @brief  Disable USCI_SPI Wake-up Function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_DisableWakeup(USPI_T *uspi)
+{
+    uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
+}
+
+/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USCI_SPI_Driver */
+
+/*@}*/ /* end of group Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_spi.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,409 @@
+/****************************************************************************//**
+ * @file     usci_spi.h
+ * @version  V3.00
+ * @brief    M480 series USCI_SPI driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __USCI_SPI_H__
+#define __USCI_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_SPI_Driver USCI_SPI Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
+  @{
+*/
+
+#define USPI_MODE_0        (0x0 << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */
+#define USPI_MODE_1        (0x1 << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */
+#define USPI_MODE_2        (0x2 << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */
+#define USPI_MODE_3        (0x3 << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */
+
+#define USPI_SLAVE         (USPI_PROTCTL_SLAVE_Msk)                  /*!< Set as slave \hideinitializer */
+#define USPI_MASTER        (0x0ul)                                     /*!< Set as master \hideinitializer */
+
+#define USPI_SS                (USPI_PROTCTL_SS_Msk)                 /*!< Set SS \hideinitializer */
+#define USPI_SS_ACTIVE_HIGH    (0x0ul)                                 /*!< SS active high \hideinitializer */
+#define USPI_SS_ACTIVE_LOW     (USPI_LINECTL_CTLOINV_Msk)            /*!< SS active low \hideinitializer */
+
+/* USCI_SPI Interrupt Mask */
+#define USPI_SSINACT_INT_MASK        (0x001ul)                         /*!< Slave Slave Inactive interrupt mask \hideinitializer */
+#define USPI_SSACT_INT_MASK          (0x002ul)                         /*!< Slave Slave Active interrupt mask \hideinitializer */
+#define USPI_SLVTO_INT_MASK          (0x004ul)                         /*!< Slave Mode Time-out interrupt mask \hideinitializer */
+#define USPI_SLVBE_INT_MASK          (0x008ul)                         /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */
+#define USPI_TXUDR_INT_MASK          (0x010ul)                         /*!< Slave Transmit Under Run interrupt mask \hideinitializer */
+#define USPI_RXOV_INT_MASK           (0x020ul)                         /*!< Receive Buffer Overrun interrupt mask \hideinitializer */
+#define USPI_TXST_INT_MASK           (0x040ul)                         /*!< Transmit Start interrupt mask \hideinitializer */
+#define USPI_TXEND_INT_MASK          (0x080ul)                         /*!< Transmit End interrupt mask \hideinitializer */
+#define USPI_RXST_INT_MASK           (0x100ul)                         /*!< Receive Start interrupt mask \hideinitializer */
+#define USPI_RXEND_INT_MASK          (0x200ul)                         /*!< Receive End interrupt mask \hideinitializer */
+
+/* USCI_SPI Status Mask */
+#define USPI_BUSY_MASK               (0x01ul)                          /*!< Busy status mask \hideinitializer */
+#define USPI_RX_EMPTY_MASK           (0x02ul)                          /*!< RX empty status mask \hideinitializer */
+#define USPI_RX_FULL_MASK            (0x04ul)                          /*!< RX full status mask \hideinitializer */
+#define USPI_TX_EMPTY_MASK           (0x08ul)                          /*!< TX empty status mask \hideinitializer */
+#define USPI_TX_FULL_MASK            (0x10ul)                          /*!< TX full status mask \hideinitializer */
+#define USPI_SSLINE_STS_MASK         (0x20ul)                          /*!< USCI_SPI_SS line status mask \hideinitializer */
+
+/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  Disable slave 3-wire mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief  Enable slave 3-wire mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief  Get the Rx buffer empty flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Rx buffer flag
+  * @retval 0: Rx buffer is not empty
+  * @retval 1: Rx buffer is empty
+  * \hideinitializer
+  */
+#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
+
+/**
+  * @brief  Get the Tx buffer empty flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Tx buffer flag
+  * @retval 0: Tx buffer is not empty
+  * @retval 1: Tx buffer is empty
+  * \hideinitializer
+  */
+#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
+
+/**
+  * @brief  Get the Tx buffer full flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Tx buffer flag
+  * @retval 0: Tx buffer is not full
+  * @retval 1: Tx buffer is full
+  * \hideinitializer
+  */
+#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
+
+/**
+  * @brief  Get the datum read from RX register.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return data in Rx register
+  * \hideinitializer
+  */
+#define USPI_READ_RX(uspi) ((uspi)->RXDAT)
+
+/**
+  * @brief  Write datum to TX register.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through USCI_SPI bus.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) )
+
+/**
+  * @brief      Set USCI_SPI_SS pin to high state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
+  * \hideinitializer
+  */
+#define USPI_SET_SS_HIGH(uspi) \
+    do{ \
+        (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
+        (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \
+    }while(0)
+
+/**
+  * @brief      Set USCI_SPI_SS pin to low state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
+  * \hideinitializer
+  */
+#define USPI_SET_SS_LOW(uspi) \
+    do{ \
+        (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
+        (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
+    }while(0)
+
+/**
+  * @brief  Set the length of suspend interval.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32SuspCycle Decide the length of suspend interval.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )
+
+/**
+  * @brief  Set the USCI_SPI transfer sequence with LSB first.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )
+
+/**
+  * @brief  Set the USCI_SPI transfer sequence with MSB first.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
+
+/**
+  * @brief  Set the data width of a USCI_SPI transaction.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Width The data width
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_DATA_WIDTH(uspi,u32Width) \
+    do{ \
+      if((u32Width) == 16ul){ \
+        (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \
+      }else {} \
+        (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \
+    }while(0)
+
+/**
+  * @brief  Get the USCI_SPI busy state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return USCI_SPI busy status
+  * @retval 0: USCI_SPI module is not busy
+  * @retval 1: USCI_SPI module is busy
+  * \hideinitializer
+  */
+#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
+
+/**
+  * @brief Get the USCI_SPI wakeup flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return Wakeup status.
+  * @retval 0 Flag is not set.
+  * @retval 1 Flag is set.
+  * \hideinitializer
+  */
+#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0)
+
+/**
+  * @brief Clear the USCI_SPI wakeup flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_WAKEUP_FLAG(uspi)  ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk)
+
+/**
+  * @brief Get protocol interrupt flag/status.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return The interrupt flag/status of protocol status register.
+  * \hideinitializer
+  */
+#define USPI_GET_PROT_STATUS(uspi)    ( (uspi)->PROTSTS)
+
+/**
+  * @brief Clear specified protocol interrupt flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+  *                                  - \ref USPI_PROTSTS_SSACTIF_Msk
+  *                                  - \ref USPI_PROTSTS_SSINAIF_Msk
+  *                                  - \ref USPI_PROTSTS_SLVBEIF_Msk
+  *                                  - \ref USPI_PROTSTS_SLVTOIF_Msk
+  *                                  - \ref USPI_PROTSTS_RXENDIF_Msk
+  *                                  - \ref USPI_PROTSTS_RXSTIF_Msk
+  *                                  - \ref USPI_PROTSTS_TXENDIF_Msk
+  *                                  - \ref USPI_PROTSTS_TXSTIF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag)    ( (uspi)->PROTSTS = (u32IntTypeFlag))
+
+/**
+  * @brief Get buffer interrupt flag/status.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return The interrupt flag/status of buffer status register.
+  * \hideinitializer
+  */
+#define USPI_GET_BUF_STATUS(uspi)    ( (uspi)->BUFSTS)
+
+/**
+  * @brief Clear specified buffer interrupt flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+  *                                  - \ref USPI_BUFSTS_TXUDRIF_Msk
+  *                                  - \ref USPI_BUFSTS_RXOVIF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag)    ( (uspi)->BUFSTS = (u32IntTypeFlag))
+
+/**
+  * @brief Enable specified protocol interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_PROTIEN_SLVBEIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SLVTOIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSACTIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSINAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_PROT_INT(uspi, u32IntSel)    ((uspi)->PROTIEN |= (u32IntSel))
+
+/**
+  * @brief Disable specified protocol interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_PROTIEN_SLVBEIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SLVTOIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSACTIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSINAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_PROT_INT(uspi, u32IntSel)    ((uspi)->PROTIEN &= ~ (u32IntSel))
+
+/**
+  * @brief Enable specified buffer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_BUFCTL_RXOVIEN_Msk
+  *                                  - \ref USPI_BUFCTL_TXUDRIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_BUF_INT(uspi, u32IntSel)    ((uspi)->BUFCTL |= (u32IntSel))
+
+/**
+  * @brief Disable specified buffer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_BUFCTL_RXOVIEN_Msk
+  *                                  - \ref USPI_BUFCTL_TXUDRIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_BUF_INT(uspi, u32IntSel)    ((uspi)->BUFCTL &= ~ (u32IntSel))
+
+/**
+  * @brief Enable specified transfer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_INTEN_RXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_RXSTIEN_Msk
+  *                                  - \ref USPI_INTEN_TXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_TXSTIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel)    ((uspi)->INTEN |= (u32IntSel))
+
+/**
+  * @brief Disable specified transfer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_INTEN_RXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_RXSTIEN_Msk
+  *                                  - \ref USPI_INTEN_TXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_TXSTIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel)    ((uspi)->INTEN &= ~ (u32IntSel))
+
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_TRIGGER_RX_PDMA(uspi)   ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_TRIGGER_TX_PDMA(uspi)   ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
+
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock);
+void USPI_Close(USPI_T *uspi);
+void USPI_ClearRxBuf(USPI_T *uspi);
+void USPI_ClearTxBuf(USPI_T *uspi);
+void USPI_DisableAutoSS(USPI_T *uspi);
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);
+uint32_t USPI_GetBusClock(USPI_T *uspi);
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);
+void USPI_EnableWakeup(USPI_T *uspi);
+void USPI_DisableWakeup(USPI_T *uspi);
+
+
+/*@}*/ /* end of group M480_USCI_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USCI_SPI_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USCI_SPI_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_uart.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,603 @@
+/**************************************************************************//**
+ * @file     usci_uart.c
+ * @version  V3.00
+ * @brief    M480 series USCI UART (UUART) driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "M480.h"
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_UART_Driver USCI_UART Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear USCI_UART specified interrupt flag
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt sources.
+ *                          Each bit corresponds to a interrupt source.
+ *                          This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+void UUART_ClearIntFlag(UUART_T* uuart , uint32_t u32Mask)
+{
+
+    if(u32Mask & UUART_ABR_INT_MASK) { /* Clear Auto-baud Rate Interrupt */
+        uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;
+    }
+
+    if(u32Mask & UUART_RLS_INT_MASK) { /* Clear Receive Line Status Interrupt */
+        uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);
+    }
+
+    if(u32Mask & UUART_BUF_RXOV_INT_MASK) { /* Clear Receive Buffer Over-run Error Interrupt */
+        uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;
+    }
+
+    if(u32Mask & UUART_TXST_INT_MASK) { /* Clear Transmit Start Interrupt */
+        uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;
+    }
+
+    if(u32Mask & UUART_TXEND_INT_MASK) { /* Clear Transmit End Interrupt */
+        uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;
+    }
+
+    if(u32Mask & UUART_RXST_INT_MASK) { /* Clear Receive Start Interrupt */
+        uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;
+    }
+
+    if(u32Mask & UUART_RXEND_INT_MASK) { /* Clear Receive End Interrupt */
+        uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;
+    }
+
+}
+
+/**
+ *    @brief        Get USCI_UART specified interrupt flag
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt sources.
+ *                          Each bit corresponds to a interrupt source.
+ *                          This parameter decides which interrupt flags will be read. It is combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       Interrupt flags of selected sources.
+ *
+ *    @details      The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+uint32_t UUART_GetIntFlag(UUART_T* uuart , uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0ul;
+    uint32_t u32Tmp1, u32Tmp2;
+
+    /* Check Auto-baud Rate Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_ABR_INT_MASK;
+    }
+
+    /* Check Receive Line Status Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk));
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_RLS_INT_MASK;
+    }
+
+    /* Check Receive Buffer Over-run Error Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK);
+    u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_BUF_RXOV_INT_MASK;
+    }
+
+    /* Check Transmit Start Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_TXST_INT_MASK;
+    }
+
+    /* Check Transmit End Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_TXEND_INT_MASK;
+    }
+
+    /* Check Receive Start Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_RXST_INT_MASK;
+    }
+
+    /* Check Receive End Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk);
+    if(u32Tmp1 && u32Tmp2) {
+        u32IntFlag |= UUART_RXEND_INT_MASK;
+    }
+
+    return u32IntFlag;
+
+}
+
+
+/**
+ *  @brief      Disable USCI_UART function mode
+ *
+ *  @param[in]  uuart The pointer of the specified USCI_UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable USCI_UART function mode.
+ */
+void UUART_Close(UUART_T* uuart)
+{
+    uuart->CTL = 0ul;
+}
+
+
+/**
+ *    @brief        Disable interrupt function.
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt enable bits.
+ *                          Each bit corresponds to a interrupt enable bit.
+ *                          This parameter decides which interrupts will be disabled. It is combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter.
+ */
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)
+{
+
+    /* Disable Auto-baud rate interrupt flag */
+    if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) {
+        uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;
+    }
+
+    /* Disable receive line status interrupt flag */
+    if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) {
+        uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) {
+        uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable TX start interrupt flag */
+    if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) {
+        uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Disable TX end interrupt flag */
+    if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) {
+        uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Disable RX start interrupt flag */
+    if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) {
+        uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Disable RX end interrupt flag */
+    if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) {
+        uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;
+    }
+}
+
+
+/**
+ *    @brief        Enable interrupt function.
+ *
+ *    @param[in]    uuart       The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask     The combination of all related interrupt enable bits.
+ *                              Each bit corresponds to a interrupt enable bit.
+ *                              This parameter decides which interrupts will be enabled. It is combination of:
+ *                              - \ref UUART_ABR_INT_MASK
+ *                              - \ref UUART_RLS_INT_MASK
+ *                              - \ref UUART_BUF_RXOV_INT_MASK
+ *                              - \ref UUART_TXST_INT_MASK
+ *                              - \ref UUART_TXEND_INT_MASK
+ *                              - \ref UUART_RXST_INT_MASK
+ *                              - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable USCI_UART related interrupts specified by u32Mask parameter.
+ */
+void UUART_EnableInt(UUART_T*  uuart, uint32_t u32Mask)
+{
+    /* Enable Auto-baud rate interrupt flag */
+    if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) {
+        uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;
+    }
+
+    /* Enable receive line status interrupt flag */
+    if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) {
+        uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) {
+        uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable TX start interrupt flag */
+    if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) {
+        uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Enable TX end interrupt flag */
+    if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) {
+        uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Enable RX start interrupt flag */
+    if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) {
+        uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Enable RX end interrupt flag */
+    if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) {
+        uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;
+    }
+}
+
+
+/**
+ *    @brief        Open and set USCI_UART function
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32baudrate     The baud rate of USCI_UART module.
+ *
+ *    @return       Real baud rate of USCI_UART module.
+ *
+ *    @details      This function use to enable USCI_UART function and set baud-rate.
+ */
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)
+{
+    uint32_t u32PCLKFreq, u32PDSClk, u32PDSCnt, u32DSCnt, u32ClkDiv;
+    uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+
+    /* Get PCLK frequency */
+    if( uuart == UUART0) {
+        u32PDSClk = u32PCLKFreq = CLK_GetPCLK0Freq();
+    } else {
+        u32PDSClk = u32PCLKFreq = CLK_GetPCLK1Freq();
+    }
+
+    for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) { /* PDSCNT could be 0~0x3 */
+        u32PDSClk = u32PCLKFreq / u32PDSCnt;
+
+        if(u32PDSClk > (80000000ul/4ul)) { /* max. PCLK freq = 80MHz */
+        } else {
+            break;
+        }
+    }
+
+    /* Find best solution */
+    u32Min = (uint32_t) - 1;
+    u32MinDSCnt = 0ul;
+    u32MinClkDiv = 0ul;
+    for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) { /* DSCNT could be 0x5~0xF */
+        for(u32ClkDiv = 1ul; u32ClkDiv <= 0x400ul; u32ClkDiv++) { /* CLKDIV could be 0~0x3FF */
+
+            u32Tmp = u32PDSClk / u32DSCnt / u32ClkDiv;
+
+            u32Tmp2 = (u32Tmp > u32baudrate) ? u32Tmp - u32baudrate : u32baudrate - u32Tmp;
+
+            if(u32Tmp2 < u32Min) {
+                u32Min = u32Tmp2;
+                u32MinDSCnt = u32DSCnt;
+                u32MinClkDiv = u32ClkDiv;
+
+                /* Break when get good results */
+                if(u32Min == 0ul) {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Enable USCI_UART protocol */
+    uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;
+    uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos;
+
+    /* Set USCI_UART line configuration */
+    uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;
+    uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos);  /* Set falling edge detection */
+
+    /* Set USCI_UART baud rate */
+    uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
+                   ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
+                   ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
+
+    uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;
+
+    return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
+}
+
+
+/**
+ *    @brief        Read USCI_UART data
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive buffer.
+ *    @param[in]    u32ReadBytes    The read bytes number of data.
+ *
+ *    @return       Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf.
+ */
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) {
+        u32delayno = 0ul;
+
+        while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) { /* Check RX empty => failed */
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul) {
+                break;
+            }
+        }
+
+        if(u32delayno >= 0x40000000ul) {
+            break;
+        }
+
+        pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT;    /* Get Data from USCI RX  */
+    }
+
+    return u32Count;
+
+}
+
+
+/**
+ *    @brief        Set USCI_UART line configuration
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32baudrate     The register value of baud rate of USCI_UART module.
+ *                                  If u32baudrate = 0, USCI_UART baud rate will not change.
+ *    @param[in]    u32data_width   The data length of USCI_UART module.
+ *                                  - \ref UUART_WORD_LEN_6
+ *                                  - \ref UUART_WORD_LEN_7
+ *                                  - \ref UUART_WORD_LEN_8
+ *                                  - \ref UUART_WORD_LEN_9
+ *    @param[in]    u32parity       The parity setting (none/odd/even) of USCI_UART module.
+ *                                  - \ref UUART_PARITY_NONE
+ *                                  - \ref UUART_PARITY_ODD
+ *                                  - \ref UUART_PARITY_EVEN
+ *    @param[in]    u32stop_bits    The stop bit length (1/2 bit) of USCI_UART module.
+ *                                  - \ref UUART_STOP_BIT_1
+ *                                  - \ref UUART_STOP_BIT_2
+ *
+ *    @return       Real baud rate of USCI_UART module.
+ *
+ *    @details      This function use to config USCI_UART line setting.
+ */
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+    uint32_t u32PCLKFreq, u32PDSClk, u32PDSCnt, u32DSCnt, u32ClkDiv;
+    uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+
+    /* Get PCLK frequency */
+    if(uuart == UUART0) {
+        u32PDSClk = u32PCLKFreq = CLK_GetPCLK0Freq();
+    } else { /* UUART1 */
+        u32PDSClk = u32PCLKFreq = CLK_GetPCLK1Freq();
+    }
+
+    if(u32baudrate != 0ul) {
+        for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) { /* PDSCNT could be 0~0x3 */
+            u32PDSClk = u32PCLKFreq / u32PDSCnt;
+
+            if(u32PDSClk > (80000000ul/4ul)) { /* max. PCLK freq = 80MHz */
+            } else {
+                break;
+            }
+        }
+
+        /* Find best solution */
+        u32Min = (uint32_t) - 1;
+        u32MinDSCnt = 0ul;
+        u32MinClkDiv = 0ul;
+        for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) { /* DSCNT could be 0x5~0xF */
+            for(u32ClkDiv = 1ul; u32ClkDiv <= 0x400ul; u32ClkDiv++) { /* CLKDIV could be 0~0x3FF */
+                u32Tmp = u32PDSClk / u32DSCnt / u32ClkDiv;
+
+                u32Tmp2 = (u32Tmp > u32baudrate) ? u32Tmp - u32baudrate : u32baudrate - u32Tmp;
+
+                if(u32Tmp2 < u32Min) {
+                    u32Min = u32Tmp2;
+                    u32MinDSCnt = u32DSCnt;
+                    u32MinClkDiv = u32ClkDiv;
+
+                    /* Break when get good results */
+                    if(u32Min == 0ul) {
+                        break;
+                    }
+                }
+            }
+        }
+
+        /* Set USCI_UART baud rate */
+        uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
+                       ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
+                       ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
+    } else {
+        u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul;
+        u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul;
+        u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul;
+    }
+
+    /* Set USCI_UART line configuration */
+    uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;
+    uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |
+                                         UUART_PROTCTL_PARITYEN_Msk)) | u32parity;
+    uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits;
+
+    return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
+}
+
+
+/**
+ *    @brief        Write USCI_UART data
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to USCI transmission buffer.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       Transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by USCI_UART.
+ */
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) {
+        u32delayno = 0ul;
+        while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) { /* Wait Tx empty */
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul) {
+                break;
+            }
+        }
+
+        if(u32delayno >= 0x40000000ul) {
+            break;
+        }
+
+        uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count];    /* Send USCI_UART Data to buffer */
+    }
+
+    return u32Count;
+
+}
+
+
+/**
+ *    @brief        Enable USCI_UART Wake-up Function
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32WakeupMode   The wakeup mode of USCI_UART module.
+ *                                   - \ref UUART_PROTCTL_DATWKEN_Msk    : Data wake-up Mode
+ *                                   - \ref UUART_PROTCTL_CTSWKEN_Msk    : nCTS wake-up Mode
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable Wake-up function of USCI_UART.
+ */
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)
+{
+    uuart->PROTCTL |= u32WakeupMode;
+    uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;
+}
+
+
+/**
+ *    @brief        Disable USCI_UART Wake-up Function
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable Wake-up function of USCI_UART.
+ */
+void UUART_DisableWakeup(UUART_T* uuart)
+{
+    uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk);
+    uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;
+}
+
+/**
+ *    @brief        Enable USCI_UART auto flow control
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable USCI_UART auto flow control.
+ */
+void UUART_EnableFlowCtrl(UUART_T* uuart)
+{
+    /* Set RTS signal is low level active */
+    uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;
+
+    /* Set CTS signal is low level active */
+    uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;
+
+    /* Enable CTS and RTS auto flow control function */
+    uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk;
+}
+
+/**
+ *    @brief        Disable USCI_UART auto flow control
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable USCI_UART auto flow control.
+ */
+void UUART_DisableFlowCtrl(UUART_T* uuart)
+{
+    /* Disable CTS and RTS auto flow control function */
+    uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk);
+}
+
+
+
+
+/*@}*/ /* end of group M480_USCI_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USCI_UART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_uart.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,438 @@
+/**************************************************************************//**
+ * @file     usci_uart.h
+ * @version  V3.00
+ * @brief    M480 series USCI UART (UUART) driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __USCI_UART_H__
+#define __USCI_UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_UART_Driver USCI_UART Driver
+  @{
+*/
+
+/** @addtogroup M480_USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_LINECTL constants definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_WORD_LEN_6     (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */
+#define UUART_WORD_LEN_7     (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */
+#define UUART_WORD_LEN_8     (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */
+#define UUART_WORD_LEN_9     (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_PROTCTL constants definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_PARITY_NONE    (0x0ul << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */
+#define UUART_PARITY_ODD     (0x1ul << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */
+#define UUART_PARITY_EVEN    (0x3ul << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */
+
+#define UUART_STOP_BIT_1     (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */
+#define UUART_STOP_BIT_2     (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI UART interrupt mask definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_ABR_INT_MASK      (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */
+#define UUART_RLS_INT_MASK      (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */
+#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */
+#define UUART_TXST_INT_MASK     (0x010ul) /*!< TX start interrupt mask \hideinitializer */
+#define UUART_TXEND_INT_MASK    (0x020ul) /*!< Tx end interrupt mask \hideinitializer */
+#define UUART_RXST_INT_MASK     (0x040ul) /*!< RX start interrupt mask \hideinitializer */
+#define UUART_RXEND_INT_MASK    (0x080ul) /*!< RX end interrupt mask \hideinitializer */
+
+
+/*@}*/ /* end of group M480_USCI_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup M480_USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+  @{
+*/
+
+
+/**
+ *    @brief        Write USCI_UART data
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ *    \hideinitializer
+ */
+#define UUART_WRITE(uuart, u8Data)    ((uuart)->TXDAT = (u8Data))
+
+
+/**
+ *    @brief        Read USCI_UART data
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @return       The oldest data byte in RX buffer.
+ *
+ *    @details      This macro read Rx data register.
+ *    \hideinitializer
+ */
+#define UUART_READ(uuart)    ((uuart)->RXDAT)
+
+
+/**
+ *    @brief        Get Tx empty
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Tx buffer is not empty
+ *    @retval       >=1 Tx buffer is empty
+ *
+ *    @details      This macro get Transmitter buffer empty register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_TX_EMPTY(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Rx buffer is not empty
+ *    @retval       >=1 Rx buffer is empty
+ *
+ *    @details      This macro get Receiver buffer empty register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_RX_EMPTY(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
+
+
+/**
+ *    @brief        Check specified usci_uart port transmission is over.
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0 Tx transmission is not over
+ *    @retval       1 Tx transmission is over
+ *
+ *    @details      This macro return Transmitter Empty Flag register bit value. \n
+ *                  It indicates if specified usci_uart port transmission is over nor not.
+ *    \hideinitializer
+ */
+#define UUART_IS_TX_EMPTY(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
+
+
+/**
+ *    @brief        Check specified usci_uart port receiver is empty.
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0 Rx receiver is not empty
+ *    @retval       1 Rx receiver is empty
+ *
+ *    @details      This macro return Receive Empty Flag register bit value. \n
+ *                  It indicates if specified usci_uart port receiver is empty nor not.
+ *    \hideinitializer
+ */
+#define UUART_IS_RX_EMPTY(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
+
+
+/**
+ *    @brief        Wait specified usci_uart port transmission is over
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro wait specified usci_uart port transmission is over.
+ *    \hideinitializer
+ */
+#define UUART_WAIT_TX_EMPTY(uuart)    while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
+
+
+/**
+ *    @brief        Check TX buffer is full or not
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       1 TX buffer is full
+ *    @retval       0 TX buffer is not full
+ *
+ *    @details      This macro check TX buffer is full or not.
+ *    \hideinitializer
+ */
+#define UUART_IS_TX_FULL(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
+
+
+/**
+ *    @brief        Check RX buffer is full or not
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       1 RX buffer is full
+ *    @retval       0 RX buffer is not full
+ *
+ *    @details      This macro check RX buffer is full or not.
+ *    \hideinitializer
+ */
+#define UUART_IS_RX_FULL(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
+
+
+/**
+ *    @brief        Get Tx full register value
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Tx buffer is not full.
+ *    @retval       >=1 Tx buffer is full.
+ *
+ *    @details      This macro get Tx full register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_TX_FULL(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
+
+
+/**
+ *    @brief        Get Rx full register value
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Rx buffer is not full.
+ *    @retval       >=1 Rx buffer is full.
+ *
+ *    @details      This macro get Rx full register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_RX_FULL(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
+
+
+/**
+ *    @brief        Enable specified USCI_UART protocol interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_PROTIEN_RLSIEN_Msk   : Rx Line status interrupt
+ *                             - \ref UUART_PROTIEN_ABRIEN_Msk   : Auto-baud rate interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART protocol interrupt.
+ *    \hideinitializer
+ */
+#define UUART_ENABLE_PROT_INT(uuart, u32IntSel)    ((uuart)->PROTIEN |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART protocol interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_PROTIEN_RLSIEN_Msk   : Rx Line status interrupt
+ *                             - \ref UUART_PROTIEN_ABRIEN_Msk   : Auto-baud rate interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART protocol interrupt.
+ *    \hideinitializer
+ */
+#define UUART_DISABLE_PROT_INT(uuart, u32IntSel)    ((uuart)->PROTIEN &= ~(u32IntSel))
+
+
+/**
+ *    @brief        Enable specified USCI_UART buffer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_BUFCTL_RXOVIEN_Msk     : Receive buffer overrun error interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART buffer interrupt.
+ *    \hideinitializer
+ */
+#define UUART_ENABLE_BUF_INT(uuart, u32IntSel)    ((uuart)->BUFCTL |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART buffer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_BUFCTL_RXOVIEN_Msk     : Receive buffer overrun error interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART buffer interrupt.
+ *    \hideinitializer
+ */
+#define UUART_DISABLE_BUF_INT(uuart, u32IntSel)    ((uuart)->BUFCTL &= ~ (u32IntSel))
+
+
+/**
+ *    @brief        Enable specified USCI_UART transfer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_INTEN_RXENDIEN_Msk  : Receive end interrupt
+ *                             - \ref UUART_INTEN_RXSTIEN_Msk   : Receive start interrupt
+ *                             - \ref UUART_INTEN_TXENDIEN_Msk  : Transmit end interrupt
+ *                             - \ref UUART_INTEN_TXSTIEN_Msk   : Transmit start interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART transfer interrupt.
+ *    \hideinitializer
+ */
+#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel)    ((uuart)->INTEN |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART transfer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_INTEN_RXENDIEN_Msk  : Receive end interrupt
+ *                             - \ref UUART_INTEN_RXSTIEN_Msk   : Receive start interrupt
+ *                             - \ref UUART_INTEN_TXENDIEN_Msk  : Transmit end interrupt
+ *                             - \ref UUART_INTEN_TXSTIEN_Msk   : Transmit start interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART transfer interrupt.
+ *    \hideinitializer
+ */
+#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel)    ((uuart)->INTEN &= ~(u32IntSel))
+
+
+/**
+ *    @brief        Get protocol interrupt flag/status
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       The interrupt flag/status of protocol status register.
+ *
+ *    @details      This macro get protocol status register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_PROT_STATUS(uuart)    ((uuart)->PROTSTS)
+
+
+/**
+ *    @brief        Clear specified protocol interrupt flag
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntTypeFlag  Interrupt Type Flag, should be
+ *                                  - \ref UUART_PROTSTS_ABERRSTS_Msk    : Auto-baud Rate Error Interrupt Indicator
+ *                                  - \ref UUART_PROTSTS_ABRDETIF_Msk    : Auto-baud Rate Detected Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_BREAK_Msk       : Break Flag
+ *                                  - \ref UUART_PROTSTS_FRMERR_Msk      : Framing Error Flag
+ *                                  - \ref UUART_PROTSTS_PARITYERR_Msk   : Parity Error Flag
+ *                                  - \ref UUART_PROTSTS_RXENDIF_Msk     : Receive End Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_RXSTIF_Msk      : Receive Start Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_TXENDIF_Msk     : Transmit End Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_TXSTIF_Msk      : Transmit Start Interrupt Flag
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear specified protocol interrupt flag.
+ *    \hideinitializer
+ */
+#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag)    ((uuart)->PROTSTS = (u32IntTypeFlag))
+
+
+/**
+ *    @brief        Get transmit/receive buffer interrupt flag/status
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       The interrupt flag/status of buffer status register.
+ *
+ *    @details      This macro get buffer status register value.
+ *    \hideinitializer
+ */
+#define UUART_GET_BUF_STATUS(uuart)    ((uuart)->BUFSTS)
+
+
+/**
+ *    @brief        Clear specified buffer interrupt flag
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntTypeFlag  Interrupt Type Flag, should be
+ *                                  - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error  Interrupt Indicator
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear specified buffer interrupt flag.
+ *    \hideinitializer
+ */
+#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag)    ((uuart)->BUFSTS = (u32IntTypeFlag))
+
+
+/**
+ *    @brief        Get wakeup flag
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0       Chip did not wake up from power-down mode.
+ *    @retval       1       Chip waked up from power-down mode.
+ *
+ *    @details      This macro get wakeup flag.
+ *    \hideinitializer
+ */
+#define UUART_GET_WAKEUP_FLAG(uuart)    ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
+
+
+/**
+ *    @brief        Clear wakeup flag
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear wakeup flag.
+ *    \hideinitializer
+ */
+#define UUART_CLR_WAKEUP_FLAG(uuart)    ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)
+
+
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);
+void UUART_Close(UUART_T* uuart);
+void UUART_DisableInt(UUART_T*  uuart, uint32_t u32Mask);
+void UUART_EnableInt(UUART_T*  uuart, uint32_t u32Mask);
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);
+void UUART_DisableWakeup(UUART_T* uuart);
+void UUART_EnableFlowCtrl(UUART_T* uuart);
+void UUART_DisableFlowCtrl(UUART_T* uuart);
+
+
+/*@}*/ /* end of group M480_USCI_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group M480_USCI_UART_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USCI_UART_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_wdt.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     wdt.c
+ * @version  V3.00
+ * @brief    M480 series WDT driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize WDT and start counting
+  *
+  * @param[in]  u32TimeoutInterval  Time-out interval period of WDT module. Valid values are:
+  *                                 - \ref WDT_TIMEOUT_2POW4
+  *                                 - \ref WDT_TIMEOUT_2POW6
+  *                                 - \ref WDT_TIMEOUT_2POW8
+  *                                 - \ref WDT_TIMEOUT_2POW10
+  *                                 - \ref WDT_TIMEOUT_2POW12
+  *                                 - \ref WDT_TIMEOUT_2POW14
+  *                                 - \ref WDT_TIMEOUT_2POW16
+  *                                 - \ref WDT_TIMEOUT_2POW18
+  * @param[in]  u32ResetDelay       Configure WDT time-out reset delay period. Valid values are:
+  *                                 - \ref WDT_RESET_DELAY_1026CLK
+  *                                 - \ref WDT_RESET_DELAY_130CLK
+  *                                 - \ref WDT_RESET_DELAY_18CLK
+  *                                 - \ref WDT_RESET_DELAY_3CLK
+  * @param[in]  u32EnableReset      Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+  * @param[in]  u32EnableWakeup     Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+  *             enable or disable WDT time-out reset system or wake-up system.
+  * @note       Please make sure that Register Write-Protection Function has been disabled before using this function.
+  */
+void WDT_Open(uint32_t u32TimeoutInterval,
+              uint32_t u32ResetDelay,
+              uint32_t u32EnableReset,
+              uint32_t u32EnableWakeup)
+{
+    WDT->ALTCTL = u32ResetDelay;
+
+    WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
+               (u32EnableReset << WDT_CTL_RSTEN_Pos) |
+               (u32EnableWakeup << WDT_CTL_WKEN_Pos);
+    return;
+}
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_wdt.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,210 @@
+/**************************************************************************//**
+ * @file     wdt.h
+ * @version  V3.00
+ * @brief    M480 series WDT driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT Time-out Interval Period Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4           (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW6           (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW8           (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW10          (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW12          (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW14          (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW16          (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW18          (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT  Reset Delay Period Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK     (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_130CLK      (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_18CLK       (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_3CLK        (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */
+
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_RESET_FLAG()          (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
+
+/**
+  * @brief      Clear WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out interrupt flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG()    (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
+
+/**
+  * @brief      Clear WDT Wake-up Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out wake-up system flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
+
+/**
+  * @brief      Get WDT Time-out Reset Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out reset system did not occur
+  * @retval     1   WDT time-out reset system occurred
+  *
+  * @details    This macro indicates system has been reset by WDT time-out reset or not.
+  * \hideinitializer
+  */
+#define WDT_GET_RESET_FLAG()            ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt did not occur
+  * @retval     1   WDT time-out interrupt occurred
+  *
+  * @details    This macro indicates WDT time-out interrupt occurred or not.
+  * \hideinitializer
+  */
+#define WDT_GET_TIMEOUT_INT_FLAG()      ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get WDT Time-out Wake-up Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt does not cause CPU wake-up
+  * @retval     1   WDT time-out interrupt event cause CPU wake-up
+  *
+  * @details    This macro indicates WDT time-out interrupt event has waked up system or not.
+  * \hideinitializer
+  */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG()   ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Reset WDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reset the internal 18-bit WDT up counter value.
+  * @note       If WDT is activated and time-out reset system function is enabled also, user should \n
+  *             reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+  *             reset system before the WDT time-out reset delay period expires.
+  * \hideinitializer
+  */
+#define WDT_RESET_COUNTER()             (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void WDT_Close(void);
+static __INLINE void WDT_EnableInt(void);
+static __INLINE void WDT_DisableInt(void);
+
+/**
+  * @brief      Stop WDT Counting
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will stop WDT counting and disable WDT module.
+  */
+static __INLINE void WDT_Close(void)
+{
+    WDT->CTL = 0UL;
+    return;
+}
+
+/**
+  * @brief      Enable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will enable the WDT time-out interrupt function.
+  */
+static __INLINE void WDT_EnableInt(void)
+{
+    WDT->CTL |= WDT_CTL_INTEN_Msk;
+    return;
+}
+
+/**
+  * @brief      Disable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will disable the WDT time-out interrupt function.
+  */
+static __INLINE void WDT_DisableInt(void)
+{
+    /* Do not touch another write 1 clear bits */
+    WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
+    return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WDT_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_wwdt.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     wwdt.c
+ * @version  V3.00
+ * @brief    M480 series WWDT driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M480.h"
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open WWDT and start counting
+  *
+  * @param[in]  u32PreScale     Pre-scale setting of WWDT counter. Valid values are:
+  *                             - \ref WWDT_PRESCALER_1
+  *                             - \ref WWDT_PRESCALER_2
+  *                             - \ref WWDT_PRESCALER_4
+  *                             - \ref WWDT_PRESCALER_8
+  *                             - \ref WWDT_PRESCALER_16
+  *                             - \ref WWDT_PRESCALER_32
+  *                             - \ref WWDT_PRESCALER_64
+  *                             - \ref WWDT_PRESCALER_128
+  *                             - \ref WWDT_PRESCALER_192
+  *                             - \ref WWDT_PRESCALER_256
+  *                             - \ref WWDT_PRESCALER_384
+  *                             - \ref WWDT_PRESCALER_512
+  *                             - \ref WWDT_PRESCALER_768
+  *                             - \ref WWDT_PRESCALER_1024
+  *                             - \ref WWDT_PRESCALER_1536
+  *                             - \ref WWDT_PRESCALER_2048
+  * @param[in]  u32CmpValue     Setting the window compared value. Valid values are between 0x0 to 0x3F.
+  * @param[in]  u32EnableInt    Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
+  * @note       This WWDT_CTL register can be write only one time after chip is powered on or reset.
+  */
+void WWDT_Open(uint32_t u32PreScale,
+               uint32_t u32CmpValue,
+               uint32_t u32EnableInt)
+{
+    WWDT->CTL = u32PreScale |
+                (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
+                ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) |
+                WWDT_CTL_WWDTEN_Msk;
+    return;
+}
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_wwdt.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,151 @@
+/**************************************************************************//**
+ * @file     wwdt.h
+ * @version  V3.00
+ * @brief    M480 series WWDT driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_H__
+#define __WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup M480_Device_Driver M480 Device Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Prescale Period Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1        (0 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2        (1 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_4        (2 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_8        (3 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_16       (4 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_32       (5 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_64       (6 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_128      (7 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_192      (8 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_256      (9 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_384      (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_512      (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_768      (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1024     (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1536     (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2048     (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Reload Counter Keyword Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_RELOAD_WORD        (0x00005AA5)                /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */
+
+/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_RESET_FLAG()     (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTIF_Msk) | WWDT_STATUS_WWDTRF_Msk)
+
+/**
+  * @brief      Clear WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT compared match interrupt flag.
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_INT_FLAG()       (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTRF_Msk) | WWDT_STATUS_WWDTIF_Msk)
+
+/**
+  * @brief      Get WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT time-out reset system did not occur
+  * @retval     1   WWDT time-out reset system occurred
+  *
+  * @details    This macro is used to indicate system has been reset by WWDT time-out reset or not.
+  * \hideinitializer
+  */
+#define WWDT_GET_RESET_FLAG()       ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT compare match interrupt did not occur
+  * @retval     1   WWDT compare match interrupt occurred
+  *
+  * @details    This macro is used to indicate WWDT counter value matches CMPDAT value or not.
+  * \hideinitializer
+  */
+#define WWDT_GET_INT_FLAG()         ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     WWDT Counter Value
+  *
+  * @details    This macro reflects the current WWDT counter value.
+  * \hideinitializer
+  */
+#define WWDT_GET_COUNTER()          (WWDT->CNT)
+
+/**
+  * @brief      Reload WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reload the WWDT counter value to 0x3F.
+  * @note       User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
+  *             between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
+  *             WWDT reset signal will generate immediately to reset system.
+  * \hideinitializer
+  */
+#define WWDT_RELOAD_COUNTER()       (WWDT->RLDCNT = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group M480_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WWDT_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,39 @@
+#! armcc -E
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+#define SPIM_CCM_START  0x20020000
+#define SPIM_CCM_END    0x20028000
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
+   *(RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  
+  ;UVISOR AlignExpr(+0, 16) {  ; 16 byte-aligned
+  ;  uvisor-lib.a (+RW +ZI)
+  ;}
+  
+  ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
+  }
+  
+  ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 96)) {  ; Reserve for vectors
+  }
+  
+  RW_IRAM1 AlignExpr(+0, 16) {  ; 16 byte-aligned
+   .ANY (+RW +ZI)
+  }
+  
+  ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x28000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+  }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))  ; 512 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20028000)   ; 160 KB SRAM

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+    struct __initial_stackheap r;
+    r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,39 @@
+#! armcc -E
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+#define SPIM_CCM_START  0x20020000
+#define SPIM_CCM_END    0x20028000
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
+   *(RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  
+  ;UVISOR AlignExpr(+0, 16) {  ; 16 byte-aligned
+  ;  uvisor-lib.a (+RW +ZI)
+  ;}
+  
+  ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
+  }
+  
+  ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 96)) {  ; Reserve for vectors
+  }
+  
+  RW_IRAM1 AlignExpr(+0, 16) {  ; 16 byte-aligned
+   .ANY (+RW +ZI)
+  }
+  
+  ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x28000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+  }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))  ; 512 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20028000)   ; 160 KB SRAM

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+    struct __initial_stackheap r;
+    r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,290 @@
+/*
+ * Nuvoton M487 GCC linker script file
+ */
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif 
+
+StackSize = 0x800;
+SPIM_CCM_START = 0x20020000;
+SPIM_CCM_END = 0x20028000;
+
+MEMORY
+{
+  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
+  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
+  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00028000 - 0x00000000
+}
+
+/**
+ * Must match cmsis_nvic.h
+ */
+__vector_size = 4 * (16 + 96);
+
+ 
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .isr_vector :
+    {
+        __vector_table = .;
+        KEEP(*(.vector_table))
+         . = ALIGN(4);
+    } > VECTORS
+
+    /* Note: Ensure that uVisor bss is at the beginning of SRAM to match vmpu_arch_init_hw of
+             uvisor/core/system/src/mpu/vmpu_armv7m.c */
+    /* Note: The uVisor expects this section at a fixed location, as specified
+             by the porting process configuration parameter: SRAM_OFFSET. */
+    __UVISOR_SRAM_OFFSET = 0x0;
+    __UVISOR_BSS_START = ORIGIN(RAM_INTERN) + __UVISOR_SRAM_OFFSET;
+    .uvisor.bss __UVISOR_BSS_START (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uvisor_bss_start = .;
+
+        /* uVisor main BSS section */
+        . = ALIGN(32);
+        __uvisor_bss_main_start = .;
+        KEEP(*(.keep.uvisor.bss.main))
+        . = ALIGN(32);
+        __uvisor_bss_main_end = .;
+
+        /* Secure boxes BSS section */
+        . = ALIGN(32);
+        __uvisor_bss_boxes_start = .;
+        KEEP(*(.keep.uvisor.bss.boxes))
+        . = ALIGN(32);
+        __uvisor_bss_boxes_end = .;
+
+        . = ALIGN(32);
+        __uvisor_bss_end = .;
+    } > RAM_INTERN
+
+    /* Heap space for the page allocator */
+    .page_heap (NOLOAD) :
+    {
+        . = ALIGN(32);
+        __uvisor_page_start = .;
+        KEEP(*(.keep.uvisor.page_heap))
+        . = ALIGN((1 << LOG2CEIL(LENGTH(RAM_INTERN))) / 8);
+        __uvisor_page_end = .;
+    } > RAM_INTERN
+    
+    /* Note: The uVisor expects this section at a fixed location, as specified
+             by the porting process configuration parameter: FLASH_OFFSET. */
+    __UVISOR_TEXT_OFFSET = 0x400;
+    __UVISOR_TEXT_START = ORIGIN(VECTORS) + __UVISOR_TEXT_OFFSET;
+    .text __UVISOR_TEXT_START :
+    {
+        /* uVisor code and data */
+        . = ALIGN(4);
+        __uvisor_main_start = .;
+        *(.uvisor.main)
+        __uvisor_main_end = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    .ARM.exidx :
+    {
+       __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+       __exidx_end = .;
+    } > FLASH
+
+    /* .stack section doesn't contains any symbols. It is only
+     * used for linker to reserve space for the main stack section
+     * WARNING: .stack should come immediately after the last secure memory
+     * section.  This provides stack overflow detection. */
+    .stack (NOLOAD):
+    {
+        __StackLimit = .;
+        *(.stack*);
+        . += StackSize - (. - __StackLimit);
+    } > RAM_INTERN
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ADDR(.stack) + SIZEOF(.stack);
+    __StackLimit = ADDR(.stack);
+    PROVIDE(__stack = __StackTop);
+
+    /* Relocate vector table in SRAM */
+    .isr_vector.reloc (NOLOAD) :
+    {
+        . = ALIGN(1 << LOG2CEIL(__vector_size));
+        PROVIDE(__start_vector_table__ = .);
+        . += __vector_size;
+        PROVIDE(__end_vector_table__ = .);
+    } > RAM_INTERN
+    
+    .data :
+    {
+        PROVIDE( __etext = LOADADDR(.data) );
+
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        /* All data end */
+        . = ALIGN(32);
+        __data_end__ = .;
+
+    } >RAM_INTERN AT>FLASH
+
+    /* uVisor configuration section
+     * This section must be located after all other flash regions. */
+    .uvisor.secure :
+    {
+        . = ALIGN(32);
+        __uvisor_secure_start = .;
+
+        /* uVisor secure boxes configuration tables */
+        . = ALIGN(32);
+        __uvisor_cfgtbl_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl))
+        . = ALIGN(32);
+        __uvisor_cfgtbl_end = .;
+
+        /* Pointers to the uVisor secure boxes configuration tables */
+        /* Note: Do not add any further alignment here, as uVisor will need to
+                 have access to the exact list of pointers. */
+        __uvisor_cfgtbl_ptr_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+        KEEP(*(.keep.uvisor.cfgtbl_ptr))
+        __uvisor_cfgtbl_ptr_end = .;
+
+        /* Pointers to all boxes register gateways. These are grouped here to
+           allow discoverability and firmware verification. */
+        __uvisor_register_gateway_ptr_start = .;
+        KEEP(*(.keep.uvisor.register_gateway_ptr))
+        __uvisor_register_gateway_ptr_end = .;
+
+        . = ALIGN(32);
+        __uvisor_secure_end = .;
+    } > FLASH
+
+    /* Uninitialized data section
+     * This region is not initialized by the C/C++ library and can be used to
+     * store state across soft reboots. */
+    .uninitialized (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uninitialized_start = .;
+        *(.uninitialized)
+        KEEP(*(.keep.uninitialized))
+        . = ALIGN(32);
+        __uninitialized_end = .;
+    } > RAM_INTERN
+
+    .bss (NOLOAD):
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM_INTERN
+    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __uvisor_heap_start = .;
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        *(.heap*);
+        . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
+        __HeapLimit = .;
+        __uvisor_heap_end = . - 4;
+    } > RAM_INTERN
+    PROVIDE(__heap_size = SIZEOF(.heap));
+    PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+    
+    /* Provide physical memory boundaries for uVisor. */
+    __uvisor_flash_start = ORIGIN(VECTORS);
+    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+    __uvisor_sram_start = ORIGIN(RAM_INTERN);
+    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
+    __uvisor_public_sram_start = __uvisor_sram_start;
+    __uvisor_public_sram_end = __uvisor_sram_end;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/m480_retarget.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,40 @@
+/******************************************************************************
+ * @file     startup_NUC472_442.c
+ * @version  V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480 MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M480.h"
+#include <errno.h>
+#include "nu_miscutil.h"
+
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+#define NU_HEAP_ALIGN       32
+
+/**
+ * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
+ * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
+ * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
+ */
+void *__wrap__sbrk(int incr)
+{
+    static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+    uint32_t heap_ind_old = NU_ALIGN_UP(heap_ind, NU_HEAP_ALIGN);
+    uint32_t heap_ind_new = NU_ALIGN_UP(heap_ind_old + incr, NU_HEAP_ALIGN);
+    
+    if (heap_ind_new > (uint32_t) &__mbed_krbs_start) {
+        errno = ENOMEM;
+        return (void *) -1;
+    } 
+    
+    heap_ind = heap_ind_new;
+    
+    return (void *) heap_ind_old;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_IAR/M487.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,38 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20028000 - 1;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__   = 0x10000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region IRAM_region  = mem:[from __ICFEDIT_region_IRAM_start__  to __ICFEDIT_region_IRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
+define block IRAMVEC   with alignment = 1024, size = 4 * (16 + 96)          { };
+
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place at start of IRAM_region   { block CSTACK };
+place in IRAM_region   { block IRAMVEC };
+place in IRAM_region   { readwrite };
+place in IRAM_region   { block HEAP };
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "M480.h"
+#include "cmsis_nvic.h"
+
+// Support linker-generated symbol as start of relocated vector table.
+#if defined(__CC_ARM)
+extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base;
+#elif defined(__ICCARM__)
+
+#elif defined(__GNUC__)
+extern uint32_t __start_vector_table__;
+#endif
+
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis_nvic.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_USER_IRQ_NUMBER 96
+#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+#if defined(__CC_ARM)
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
+#elif defined(__ICCARM__)
+#   pragma section = "IRAMVEC"
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) __section_begin("IRAMVEC"))
+#elif defined(__GNUC__)
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &__start_vector_table__)
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,474 @@
+/******************************************************************************
+ * @file     startup_M480.c
+ * @version  V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M480.h"
+#include "PeripheralNames.h"
+
+/* Suppress warning messages */
+#if defined(__CC_ARM)
+// Suppress warning message: extended constant initialiser used
+#pragma diag_suppress 1296
+#elif defined(__ICCARM__)
+#elif defined(__GNUC__)
+#endif
+
+/* Macro Definitions */
+#if defined(__CC_ARM)
+#define WEAK            __attribute__ ((weak))
+#define ALIAS(f)        __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#elif defined(__ICCARM__)
+//#define STRINGIFY(x) #x
+//#define _STRINGIFY(x) STRINGIFY(x)
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void);                         \
+_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
+#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
+#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
+// Suppress warning message Pe1665
+#pragma diag_suppress=Pe1665
+
+#elif defined(__GNUC__)
+#define WEAK            __attribute__ ((weak))
+#define ALIAS(f)        __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#endif
+
+
+/* Initialize segments */
+#if defined(__CC_ARM)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern void __main(void);
+#elif defined(__ICCARM__)
+void __iar_program_start(void);
+#elif defined(__GNUC__)
+extern uint32_t __StackTop;
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+extern void uvisor_init(void);
+#if defined(TOOLCHAIN_GCC_ARM)
+extern void _start(void);
+#else
+#error("For GCC toolchain, only support GNU ARM Embedded")
+#endif
+#endif
+
+/* Default empty handler */
+void Default_Handler(void);
+
+/* Reset handler */
+void Reset_Handler(void);
+void Reset_Handler_1(void);
+void Reset_Handler_2(void);
+void Reset_Handler_Cascade(void *sp, void *pc);
+
+/* Cortex-M4 core handlers */
+WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(BusFault_Handler , Default_Handler)
+WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
+
+/* Peripherals handlers */
+WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler)        // 0: Brown Out detection
+WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler)        // 1: Internal RC
+WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler)      // 2: Power down wake up
+WEAK_ALIAS_FUNC(RAMPE_IRQHandler, Default_Handler)      // 3: RAM parity error
+WEAK_ALIAS_FUNC(CKFAIL_IRQHandler, Default_Handler)     // 4: Clock detection fail
+                                                        // 5: Reserved
+WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler)        // 6: Real Time Clock
+WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler)     // 7: Tamper detection
+WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler)        // 8: Watchdog timer
+WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler)       // 9: Window watchdog timer
+WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler)      // 10: External Input 0
+WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler)      // 11: External Input 1
+WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler)      // 12: External Input 2
+WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler)      // 13: External Input 3
+WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler)      // 14: External Input 4
+WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler)      // 15: External Input 5
+WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler)        // 16: GPIO Port A
+WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler)        // 17: GPIO Port B
+WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler)        // 18: GPIO Port C
+WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler)        // 19: GPIO Port D
+WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler)        // 20: GPIO Port E
+WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler)        // 21: GPIO Port F
+WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler)       // 22: SPI0
+WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler)       // 23: SPI1
+WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler)     // 24:
+WEAK_ALIAS_FUNC(PWM0P0_IRQHandler, Default_Handler)     // 25:
+WEAK_ALIAS_FUNC(PWM0P1_IRQHandler, Default_Handler)     // 26:
+WEAK_ALIAS_FUNC(PWM0P2_IRQHandler, Default_Handler)     // 27:
+WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler)     // 28:
+WEAK_ALIAS_FUNC(PWM1P0_IRQHandler, Default_Handler)     // 29:
+WEAK_ALIAS_FUNC(PWM1P1_IRQHandler, Default_Handler)     // 30:
+WEAK_ALIAS_FUNC(PWM1P2_IRQHandler, Default_Handler)     // 31:
+WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler)       // 32: Timer 0
+WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler)       // 33: Timer 1
+WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler)       // 34: Timer 2
+WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler)       // 35: Timer 3
+WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler)      // 36: UART0
+WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler)      // 37: UART1
+WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler)       // 38: I2C0
+WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler)       // 39: I2C1
+WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler)       // 40: Peripheral DMA
+WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler)        // 41: DAC
+WEAK_ALIAS_FUNC(ADC00_IRQHandler, Default_Handler)      // 42: ADC0 interrupt source 0
+WEAK_ALIAS_FUNC(ADC01_IRQHandler, Default_Handler)      // 43: ADC0 interrupt source 1
+WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler)     // 44: ACMP0 and ACMP1
+                                                        // 45: Reserved
+WEAK_ALIAS_FUNC(ADC02_IRQHandler, Default_Handler)      // 46: ADC0 interrupt source 2
+WEAK_ALIAS_FUNC(ADC03_IRQHandler, Default_Handler)      // 47: ADC0 interrupt source 3
+WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler)      // 48: UART2
+WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler)      // 49: UART3
+                                                        // 50: Reserved
+WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler)       // 51: SPI2
+WEAK_ALIAS_FUNC(SPI3_IRQHandler, Default_Handler)       // 52: SPI3
+WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler)       // 53: USB device
+WEAK_ALIAS_FUNC(OHCI_IRQHandler, Default_Handler)       // 54: OHCI
+WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler)     // 55: USB OTG
+WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler)       // 56: CAN0
+WEAK_ALIAS_FUNC(CAN1_IRQHandler, Default_Handler)       // 57: CAN1
+WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler)        // 58:
+WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler)        // 59:
+WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler)        // 60:
+                                                        // 61:
+WEAK_ALIAS_FUNC(SPI4_IRQHandler, Default_Handler)       // 62: SPI4
+                                                        // 63:
+WEAK_ALIAS_FUNC(SDH0_IRQHandler, Default_Handler)       // 64: SDH0
+WEAK_ALIAS_FUNC(USBD20_IRQHandler, Default_Handler)     // 65: USBD20
+WEAK_ALIAS_FUNC(EMAC_TX_IRQHandler, Default_Handler)    // 66: EMAC_TX
+WEAK_ALIAS_FUNC(EMAC_RX_IRQHandler, Default_Handler)    // 67: EMAX_RX
+WEAK_ALIAS_FUNC(I2S0_IRQHandler, Default_Handler)       // 68: I2S0
+                                                        // 69: ToDo: Add description to this Interrupt
+WEAK_ALIAS_FUNC(OPA0_IRQHandler, Default_Handler)       // 70: OPA0
+WEAK_ALIAS_FUNC(CRYPTO_IRQHandler, Default_Handler)     // 71: CRYPTO
+WEAK_ALIAS_FUNC(GPG_IRQHandler, Default_Handler)        // 72:
+WEAK_ALIAS_FUNC(EINT6_IRQHandler, Default_Handler)      // 73:
+WEAK_ALIAS_FUNC(UART4_IRQHandler, Default_Handler)      // 74: UART4
+WEAK_ALIAS_FUNC(UART5_IRQHandler, Default_Handler)      // 75: UART5
+WEAK_ALIAS_FUNC(USCI0_IRQHandler, Default_Handler)      // 76: USCI0
+WEAK_ALIAS_FUNC(USCI1_IRQHandler, Default_Handler)      // 77: USCI1
+WEAK_ALIAS_FUNC(BPWM0_IRQHandler, Default_Handler)      // 78: BPWM0
+WEAK_ALIAS_FUNC(BPWM1_IRQHandler, Default_Handler)      // 79: BPWM1
+WEAK_ALIAS_FUNC(SPIM_IRQHandler, Default_Handler)       // 80: SPIM
+                                                        // 81:
+WEAK_ALIAS_FUNC(I2C2_IRQHandler, Default_Handler)       // 82: I2C2
+                                                        // 83:
+WEAK_ALIAS_FUNC(QEI0_IRQHandler, Default_Handler)       // 84: QEI0
+WEAK_ALIAS_FUNC(QEI1_IRQHandler, Default_Handler)       // 85: QEI1
+WEAK_ALIAS_FUNC(ECAP0_IRQHandler, Default_Handler)      // 86: ECAP0
+WEAK_ALIAS_FUNC(ECAP1_IRQHandler, Default_Handler)      // 87: ECAP1
+WEAK_ALIAS_FUNC(GPH_IRQHandler, Default_Handler)        // 88:
+WEAK_ALIAS_FUNC(EINT7_IRQHandler, Default_Handler)      // 89:
+WEAK_ALIAS_FUNC(SDH1_IRQHandler, Default_Handler)       // 90: SDH1
+                                                        // 91:
+WEAK_ALIAS_FUNC(EHCI_IRQHandler, Default_Handler)       // 92: EHCI
+WEAK_ALIAS_FUNC(USBOTG20_IRQHandler, Default_Handler)   // 93:
+WEAK_ALIAS_FUNC(SWDC_IRQHandler, Default_Handler)       // 94:
+WEAK_ALIAS_FUNC(ETMC_IRQHandler, Default_Handler)       // 95:
+
+/* Vector table */
+#if defined(__CC_ARM)
+__attribute__ ((section("RESET")))
+const uint32_t __vector_handlers[] = {
+#elif defined(__ICCARM__)
+extern uint32_t CSTACK$$Limit;
+const uint32_t __vector_table[] @ ".intvec" = {
+#elif defined(__GNUC__)
+__attribute__ ((section(".vector_table")))
+const uint32_t __vector_handlers[] = {
+#endif
+
+#if defined(__CC_ARM)
+    (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
+#elif defined(__ICCARM__)
+    (uint32_t) &CSTACK$$Limit,
+#elif defined(__GNUC__)
+    (uint32_t) &__StackTop,
+#endif
+
+    (uint32_t) Reset_Handler,           // Reset Handler
+    (uint32_t) NMI_Handler,             // NMI Handler
+    (uint32_t) HardFault_Handler,       // Hard Fault Handler
+    (uint32_t) MemManage_Handler,       // MPU Fault Handler
+    (uint32_t) BusFault_Handler,        // Bus Fault Handler
+    (uint32_t) UsageFault_Handler,      // Usage Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    (uint32_t) SVC_Handler,             // SVCall Handler
+    (uint32_t) DebugMon_Handler,        // Debug Monitor Handler
+    0,                                  // Reserved
+    (uint32_t) PendSV_Handler,          // PendSV Handler
+    (uint32_t) SysTick_Handler,         // SysTick Handler
+
+    /* External Interrupts */
+    (uint32_t) BOD_IRQHandler,          // 0: Brown Out detection
+    (uint32_t) IRC_IRQHandler,          // 1: Internal RC
+    (uint32_t) PWRWU_IRQHandler,        // 2: Power down wake up
+    (uint32_t) RAMPE_IRQHandler,        // 3: RAM parity error
+    (uint32_t) CKFAIL_IRQHandler,       // 4: Clock detection fail
+    (uint32_t) Default_Handler,         // 5: Reserved
+    (uint32_t) RTC_IRQHandler,          // 6: Real Time Clock
+    (uint32_t) TAMPER_IRQHandler,       // 7: Tamper detection
+    (uint32_t) WDT_IRQHandler,          // 8: Watchdog timer
+    (uint32_t) WWDT_IRQHandler,         // 9: Window watchdog timer
+    (uint32_t) EINT0_IRQHandler,        // 10: External Input 0
+    (uint32_t) EINT1_IRQHandler,        // 11: External Input 1
+    (uint32_t) EINT2_IRQHandler,        // 12: External Input 2
+    (uint32_t) EINT3_IRQHandler,        // 13: External Input 3
+    (uint32_t) EINT4_IRQHandler,        // 14: External Input 4
+    (uint32_t) EINT5_IRQHandler,        // 15: External Input 5
+    (uint32_t) GPA_IRQHandler,          // 16: GPIO Port A
+    (uint32_t) GPB_IRQHandler,          // 17: GPIO Port B
+    (uint32_t) GPC_IRQHandler,          // 18: GPIO Port C
+    (uint32_t) GPD_IRQHandler,          // 19: GPIO Port D
+    (uint32_t) GPE_IRQHandler,          // 20: GPIO Port E
+    (uint32_t) GPF_IRQHandler,          // 21: GPIO Port F
+    (uint32_t) SPI0_IRQHandler,         // 22: SPI0
+    (uint32_t) SPI1_IRQHandler,         // 23: SPI1
+    (uint32_t) BRAKE0_IRQHandler,       // 24:
+    (uint32_t) PWM0P0_IRQHandler,       // 25:
+    (uint32_t) PWM0P1_IRQHandler,       // 26:
+    (uint32_t) PWM0P2_IRQHandler,       // 27:
+    (uint32_t) BRAKE1_IRQHandler,       // 28:
+    (uint32_t) PWM1P0_IRQHandler,       // 29:
+    (uint32_t) PWM1P1_IRQHandler,       // 30:
+    (uint32_t) PWM1P2_IRQHandler,       // 31:
+    (uint32_t) TMR0_IRQHandler,         // 32: Timer 0
+    (uint32_t) TMR1_IRQHandler,         // 33: Timer 1
+    (uint32_t) TMR2_IRQHandler,         // 34: Timer 2
+    (uint32_t) TMR3_IRQHandler,         // 35: Timer 3
+    (uint32_t) UART0_IRQHandler,        // 36: UART0
+    (uint32_t) UART1_IRQHandler,        // 37: UART1
+    (uint32_t) I2C0_IRQHandler,         // 38: I2C0
+    (uint32_t) I2C1_IRQHandler,         // 39: I2C1
+    (uint32_t) PDMA_IRQHandler,         // 40: Peripheral DMA
+    (uint32_t) DAC_IRQHandler,          // 41: DAC
+    (uint32_t) ADC00_IRQHandler,        // 42: ADC0 interrupt source 0
+    (uint32_t) ADC01_IRQHandler,        // 43: ADC0 interrupt source 1
+    (uint32_t) ACMP01_IRQHandler,       // 44: ACMP0 and ACMP1
+    (uint32_t) Default_Handler,         // 45: Reserved
+    (uint32_t) ADC02_IRQHandler,        // 46: ADC0 interrupt source 2
+    (uint32_t) ADC03_IRQHandler,        // 47: ADC0 interrupt source 3
+    (uint32_t) UART2_IRQHandler,        // 48: UART2
+    (uint32_t) UART3_IRQHandler,        // 49: UART3
+    (uint32_t) Default_Handler,         // 50: Reserved
+    (uint32_t) SPI2_IRQHandler,         // 51: SPI2
+    (uint32_t) SPI3_IRQHandler,         // 52: SPI3
+    (uint32_t) USBD_IRQHandler,         // 53: USB device
+    (uint32_t) OHCI_IRQHandler,         // 54: OHCI
+    (uint32_t) USBOTG_IRQHandler,       // 55: USB OTG
+    (uint32_t) CAN0_IRQHandler,         // 56: CAN0
+    (uint32_t) CAN1_IRQHandler,         // 57: CAN1
+    (uint32_t) SC0_IRQHandler,          // 58:
+    (uint32_t) SC1_IRQHandler,          // 59:
+    (uint32_t) SC2_IRQHandler,          // 60:
+    (uint32_t) Default_Handler,         // 61:
+    (uint32_t) SPI4_IRQHandler,         // 62: SPI4
+    (uint32_t) Default_Handler,         // 63:
+    (uint32_t) SDH0_IRQHandler,         // 64: SDH0
+    (uint32_t) USBD20_IRQHandler,       // 65: USBD20
+    (uint32_t) EMAC_TX_IRQHandler,      // 66: EMAC_TX
+    (uint32_t) EMAC_RX_IRQHandler,      // 67: EMAX_RX
+    (uint32_t) I2S0_IRQHandler,         // 68: I2S0
+    (uint32_t) Default_Handler,         // 69: ToDo: Add description to this Interrupt
+    (uint32_t) OPA0_IRQHandler,         // 70: OPA0
+    (uint32_t) CRYPTO_IRQHandler,       // 71: CRYPTO
+    (uint32_t) GPG_IRQHandler,          // 72:
+    (uint32_t) EINT6_IRQHandler,        // 73:
+    (uint32_t) UART4_IRQHandler,        // 74: UART4
+    (uint32_t) UART5_IRQHandler,        // 75: UART5
+    (uint32_t) USCI0_IRQHandler,        // 76: USCI0
+    (uint32_t) USCI1_IRQHandler,        // 77: USCI1
+    (uint32_t) BPWM0_IRQHandler,        // 78: BPWM0
+    (uint32_t) BPWM1_IRQHandler,        // 79: BPWM1
+    (uint32_t) SPIM_IRQHandler,         // 80: SPIM
+    (uint32_t) Default_Handler,         // 81:
+    (uint32_t) I2C2_IRQHandler,         // 82: I2C2
+    (uint32_t) Default_Handler,         // 83:
+    (uint32_t) QEI0_IRQHandler,         // 84: QEI0
+    (uint32_t) QEI1_IRQHandler,         // 85: QEI1
+    (uint32_t) ECAP0_IRQHandler,        // 86: ECAP0
+    (uint32_t) ECAP1_IRQHandler,        // 87: ECAP1
+    (uint32_t) GPH_IRQHandler,          // 88:
+    (uint32_t) EINT7_IRQHandler,        // 89:
+    (uint32_t) SDH1_IRQHandler,         // 90: SDH1
+    (uint32_t) Default_Handler,         // 91:
+    (uint32_t) EHCI_IRQHandler,         // 92: EHCI
+    (uint32_t) USBOTG20_IRQHandler,     // 93:
+    (uint32_t) SWDC_IRQHandler,         // 94:
+    (uint32_t) ETMC_IRQHandler,         // 95:
+};
+
+/* 
+ * Reset_Handler: 
+ *  Divert one small memory block for Initial Stack
+ *  Continue Initial Stack for Reset_Handler_1
+ *  Jump to Reset_Handler_1
+ * 
+ * Reset_Handler_1
+ *  Enable SPIM CCM memory. From now on, this memory could be used for Initial Stack, depending on linker.
+ *  Configure Initial Stack, using linker-generated symbols for Reset_Handler_2
+ *  Jump to Reset_Handler_2
+ * 
+ * Reset_Handler_2
+ *  C/C++ runtime initialization
+ */
+     
+#if defined (__CC_ARM)
+
+__asm static void Reset_Handler(void)
+{    
+    LDR SP, =0x20000200
+    LDR R0, =0x20000200
+    LDR R1, =__cpp(Reset_Handler_1)
+    LDR R2, =__cpp(Reset_Handler_Cascade)
+    BX  R2
+}
+
+__asm void Reset_Handler_Cascade(void *sp, void *pc)
+{
+    MOV SP, R0
+    BX R1
+}
+
+#elif defined (__GNUC__) || defined (__ICCARM__)
+
+void Reset_Handler(void)
+{
+    /* NOTE: In debugger disassembly view, check initial stack cannot be accessed until initial stack pointer has changed to 0x20000200 */
+    __asm volatile (
+        "mov    sp, %0                  \n"
+        "mov    r0, sp                  \n"
+        "mov    r1, %1                  \n"
+        "b     Reset_Handler_Cascade    \n"
+        :                                           /* output operands */
+        : "l"(0x20000200), "l"(&Reset_Handler_1)    /* input operands */
+        : "r0", "r1", "cc"                          /* list of clobbered registers */
+    );
+}
+
+void Reset_Handler_Cascade(void *sp, void *pc)
+{
+    __asm volatile (
+        "mov    sp,  %0             \n"
+        "bx     %1                  \n"
+        :                           /* output operands */
+        : "l"(sp), "l"(pc)          /* input operands */
+        : "cc"                      /* list of clobbered registers */
+    );
+}
+
+#else
+
+#error "Unsupported toolchain"
+
+#endif
+
+void Reset_Handler_1(void)
+{
+    /* Disable register write-protection function */
+    SYS_UnlockReg();
+    
+    /* Disable Power-on Reset function */
+    SYS_DISABLE_POR();
+    
+    /**
+     * NOTE 1: Some register accesses require unlock.
+     * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
+     */
+    SystemInit();
+    
+    /* Enable register write-protection function */
+    SYS_LockReg();
+    
+#if defined(__CC_ARM)
+    Reset_Handler_Cascade((void *) &Image$$ARM_LIB_STACK$$ZI$$Limit, (void *) Reset_Handler_2);
+#elif defined(__ICCARM__)
+    Reset_Handler_Cascade((void *) &CSTACK$$Limit, (void *) Reset_Handler_2);
+#elif defined(__GNUC__)
+    Reset_Handler_Cascade((void *) &__StackTop, (void *) Reset_Handler_2);
+#endif
+}
+
+void Reset_Handler_2(void)
+{
+    /**
+     * The call to uvisor_init() happens independently of uVisor being enabled or
+     * not, so it is conditionally compiled only based on FEATURE_UVISOR.
+     *
+     * The call to uvisor_init() must be right after system initialization (usually called SystemInit()) and 
+     * right before the C/C++ library initialization (zeroing the BSS section, loading data from flash to SRAM). 
+     * Otherwise, we might get data corruption.
+     */
+#if defined(FEATURE_UVISOR)
+    uvisor_init();
+#endif
+
+#if defined(__CC_ARM)
+    __main();
+    
+#elif defined(__ICCARM__)
+    __iar_program_start();
+
+#elif defined(__GNUC__)
+    uint32_t *src_ind = (uint32_t *) &__etext;
+    uint32_t *dst_ind = (uint32_t *) &__data_start__;
+    uint32_t *dst_end = (uint32_t *) &__data_end__;
+
+    /* Move .data section from ROM to RAM */
+    if (src_ind != dst_ind) {
+        for (; dst_ind < dst_end;) {
+            *dst_ind ++ = *src_ind ++;
+        }
+    }
+   
+    /* Initialize .bss section to zero */
+    dst_ind = (uint32_t *) &__bss_start__;
+    dst_end = (uint32_t *) &__bss_end__;
+    if (dst_ind != dst_end) {
+        for (; dst_ind < dst_end;) {
+            *dst_ind ++ = 0;
+        }
+    }
+    
+    _start();
+    
+#endif
+
+    /* Infinite loop */
+    while (1);
+}
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+    while (1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     system_M480.c
+ * @version  V1.000
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M480.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock  = __SYSTEM_CLOCK;    /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs      = (__HSI / 1000000UL); /* Cycles per micro second */
+uint32_t PllClock         = __HSI;             /*!< PLL Output Clock Frequency         */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+    uint32_t u32Freq, u32ClkSrc;
+    uint32_t u32HclkDiv;
+
+    /* Update PLL Clock */
+    PllClock = CLK_GetPLLClockFreq();
+
+    u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+    if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) {
+        /* Use PLL clock */
+        u32Freq = PllClock;
+    } else {
+        /* Use the clock sources directly */
+        u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+    }
+
+    u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
+
+    /* Update System Core Clock */
+    SystemCoreClock = u32Freq / u32HclkDiv;
+
+    CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the micro controller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+    /* ToDo: add code to initialize the system
+             do not use global variables because this function is called before
+             reaching pre-main. RW section maybe overwritten afterwards.          */
+
+
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+#endif
+
+    /* Disable Flash Access Cycle Auto-tuning, set access cycle for CPU @ 192MHz */
+    FMC->CYCCTL = FMC_CYCCTL_FADIS_Msk | (8 << FMC_CYCCTL_CYCLE_Pos);
+
+    // Divert SRAM bank2 (32 KB) to CCM from SPIM cache
+    // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in function below.
+    // NOTE: SPIM must keep enabled to run CCM mode.
+    CLK_EnableModuleClock(SPIM_MODULE);
+    SYS_ResetModule(SPIM_RST);
+    SPIM_DISABLE_CACHE();
+    SPIM_ENABLE_CCM();
+    while (! SPIM_IS_CCM_EN());
+    
+#ifndef MBED_CONF_TARGET_CTRL01_ENABLE
+#define MBED_CONF_TARGET_CTRL01_ENABLE 1
+#endif
+
+#if (! MBED_CONF_TARGET_CTRL01_ENABLE)
+    M32(0x4000c018) |= 0x00000080;
+#endif
+}
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file     system_M480.h
+ * @version  V1.00
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M480_H__
+#define __SYSTEM_M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define __HSI       (12000000UL)    /*!< PLL default output is 50MHz */
+#define __HXT       (12000000UL)    /*!< External Crystal Clock Frequency     */
+#define __LXT       (32768UL)       /*!< External Crystal Clock Frequency 32.768KHz */
+#define __HIRC      (12000000UL)    /*!< Internal 12M RC Oscillator Frequency */
+#define __LIRC      (10000UL)       /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+
+#define __SYSTEM_CLOCK    (1UL*__HXT)
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t CyclesPerUs;         /*!< Cycles per micro second              */
+extern uint32_t PllClock;            /*!< PLL Output Clock Frequency           */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M480_H__ */
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/dma.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DMA_H
+#define MBED_DMA_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DMA_CAP_NONE    (0 << 0)
+
+#define DMA_EVENT_ABORT             (1 << 0)
+#define DMA_EVENT_TRANSFER_DONE     (1 << 1)
+#define DMA_EVENT_TIMEOUT           (1 << 2)
+#define DMA_EVENT_ALL               (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT)
+#define DMA_EVENT_MASK              DMA_EVENT_ALL
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
+PDMA_T *dma_modbase(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/dma_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,167 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "dma_api.h"
+#include "string.h"
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "PeripheralNames.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include "dma.h"
+
+#define NU_PDMA_CH_MAX      PDMA_CH_MAX     /* Specify maximum channels of PDMA */
+#define NU_PDMA_CH_Pos      0               /* Specify first channel number of PDMA */
+#define NU_PDMA_CH_Msk      (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
+
+struct nu_dma_chn_s {
+    void        (*handler)(uint32_t, uint32_t);
+    uint32_t    id;
+    uint32_t    event;
+};
+
+static int dma_inited = 0;
+static uint32_t dma_chn_mask = 0;
+static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX];
+
+static void pdma_vec(void);
+static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
+
+
+void dma_init(void)
+{
+    if (dma_inited) {
+        return;
+    }
+
+    dma_inited = 1;
+    dma_chn_mask = ~NU_PDMA_CH_Msk;
+    memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
+
+    // Reset this module
+    SYS_ResetModule(dma_modinit.rsetidx);
+
+    // Enable IP clock
+    CLK_EnableModuleClock(dma_modinit.clkidx);
+
+    PDMA_Open(0);
+
+    NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+    NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+int dma_channel_allocate(uint32_t capabilities)
+{
+    if (! dma_inited) {
+        dma_init();
+    }
+
+    int i = nu_cto(dma_chn_mask);
+    if (i != 32) {
+        dma_chn_mask |= 1 << i;
+        memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s));
+        return i;
+    }
+
+    // No channel available
+    return DMA_ERROR_OUT_OF_CHANNELS;
+}
+
+int dma_channel_free(int channelid)
+{
+    if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_chn_mask &= ~(1 << channelid);
+    }
+
+    return 0;
+}
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
+{
+    MBED_ASSERT(dma_chn_mask & (1 << channelid));
+
+    dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler;
+    dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id;
+    dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event;
+
+    // Set interrupt vector if someone has removed it.
+    NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+    NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+PDMA_T *dma_modbase(void)
+{
+    return (PDMA_T *) NU_MODBASE(dma_modinit.modname);
+}
+
+static void pdma_vec(void)
+{
+    uint32_t intsts = PDMA_GET_INT_STATUS();
+
+    // Abort
+    if (intsts & PDMA_INTSTS_ABTIF_Msk) {
+        uint32_t abtsts = PDMA_GET_ABORT_STS();
+        // Clear all Abort flags
+        PDMA_CLR_ABORT_FLAG(abtsts);
+
+        while (abtsts) {
+            int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIF0_Pos + NU_PDMA_CH_Pos;
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
+                }
+            }
+            abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIF0_Pos));
+        }
+    }
+
+    // Transfer done
+    if (intsts & PDMA_INTSTS_TDIF_Msk) {
+        uint32_t tdsts = PDMA_GET_TD_STS();
+        // Clear all transfer done flags
+        PDMA_CLR_TD_FLAG(tdsts);
+
+        while (tdsts) {
+            int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIF0_Pos + NU_PDMA_CH_Pos;
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
+                }
+            }
+            tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIF0_Pos));
+        }
+    }
+
+    // Timeout
+    uint32_t reqto = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk);
+    if (reqto) {
+        // Clear all Timeout flags
+        PDMA->INTSTS = reqto;
+
+        while (reqto) {
+            int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOF0_Pos + NU_PDMA_CH_Pos;
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
+                }
+            }
+            reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOF0_Pos));
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian.
+static uint32_t FLASH_ALGO[] = {
+    0x4603b530, 0x2164460c, 0x4df72059, 0x20166028, 0xf8c5070d, 0x20880100, 0x0100f8c5, 0xf8d006c0,
+    0xf0000100, 0xb9080001, 0xbd302001, 0x680048ef, 0x0004f040, 0x4580f04f, 0x0200f8c5, 0xf8d04628,
+    0xf0400204, 0xf8c50004, 0xbf000204, 0xf1a11e08, 0xd1fb0101, 0x680048e6, 0x0029f040, 0x60284de4,
+    0x68004628, 0x0001f000, 0x2001b908, 0x48e0e7dd, 0xf0406800, 0x4dde0040, 0x20006028, 0x4601e7d5,
+    0x48dbbf00, 0xf0006900, 0x28000001, 0x48d8d1f9, 0xf0206800, 0x4ad60029, 0x20006010, 0x60104ad2,
+    0x46014770, 0x48d2bf00, 0xf0006900, 0x28000001, 0x48cfd1f9, 0xf0406800, 0x4acd0040, 0x20226010,
+    0xf02160d0, 0x60500003, 0x1f00f5b1, 0x48c9d101, 0x20016090, 0x61104ac6, 0x8f60f3bf, 0x48c4bf00,
+    0xf0006900, 0x28000001, 0x48c1d1f9, 0xf0006800, 0xb1380040, 0x680048be, 0x0040f040, 0x60104abc,
+    0x47702001, 0xe7fc2000, 0x4603b570, 0x2500460c, 0x4629e009, 0xf8531c6d, 0xf7ff0021, 0x1e06ffc2,
+    0x4630d001, 0x42a5bd70, 0x2000d3f3, 0xb570e7fa, 0x460b4604, 0x22004615, 0xf1034629, 0xf020000f,
+    0xbf00030f, 0x690048aa, 0x0001f000, 0xd1f92800, 0x680048a7, 0x0040f040, 0x60304ea5, 0x000ff024,
+    0x20276070, 0x461060f0, 0xf8511c52, 0x4ea00020, 0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e9c,
+    0x46100084, 0xf8511c52, 0x4e990020, 0x60303688, 0x1c524610, 0x0020f851, 0x60301d36, 0x4e942001,
+    0x3b106130, 0xbf00e02c, 0x30c04891, 0xf0006800, 0x28000030, 0x4610d1f8, 0xf8511c52, 0x4e8c0020,
+    0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e88, 0xbf000084, 0x30c04886, 0xf0006800, 0x280000c0,
+    0x4610d1f8, 0xf8511c52, 0x4e810020, 0x60303688, 0x1c524610, 0x0020f851, 0xf8c64e7d, 0x3b10008c,
+    0xd1d02b00, 0x487abf00, 0xf0006900, 0x28000001, 0xbd70d1f9, 0x4603b510, 0xf0201cc8, 0xbf000103,
+    0x69004873, 0x0001f000, 0xd1f92800, 0x68004870, 0x0040f040, 0x60204c6e, 0x60e02021, 0xf023e020,
+    0x4c6b0003, 0x68106060, 0x200160a0, 0xf3bf6120, 0xbf008f60, 0x69004866, 0x0001f000, 0xd1f92800,
+    0x68004863, 0x0040f000, 0x4861b138, 0xf0406800, 0x4c5f0040, 0x20016020, 0x1d1bbd10, 0x1f091d12,
+    0xd1dc2900, 0xe7f72000, 0x47f0e92d, 0x460c4605, 0xf04f4616, 0x46c20800, 0x4855bf00, 0xf0006900,
+    0x28000001, 0x4852d1f9, 0xf0406800, 0x49500040, 0x1ce06008, 0x0403f020, 0xf3c5e02f, 0xb9600008,
+    0x7f00f5b4, 0xf44fd309, 0xeb067700, 0x46390208, 0xf7ff4628, 0x4682ff2c, 0xf3c5e016, 0xb9580008,
+    0xd3092c10, 0x070ff024, 0x0208eb06, 0x46284639, 0xff1df7ff, 0xe0074682, 0xeb064627, 0x46390208,
+    0xf7ff4628, 0x4682ff87, 0x44b8443d, 0xf1ba1be4, 0xd0020f00, 0xe8bd2001, 0x2c0087f0, 0x2000d1cd,
+    0xb510e7f9, 0xf0231ccb, 0xbf000103, 0x691b4b30, 0x0301f003, 0xd1f92b00, 0x681b4b2d, 0x0340f043,
+    0x60234c2b, 0x60e32300, 0xf020e025, 0x4c280303, 0x23006063, 0x230160a3, 0xf3bf6123, 0xbf008f60,
+    0x691b4b23, 0x0301f003, 0xd1f92b00, 0x681b4b20, 0x0340f003, 0x4b1eb133, 0xf043681b, 0x4c1c0340,
+    0xbd106023, 0x689b4b1a, 0x42a36814, 0xe7f8d000, 0x1d121d00, 0x29001f09, 0xbf00d1d7, 0xb510e7f1,
+    0x48134603, 0xf0006e00, 0xb1680002, 0x65034810, 0x65826541, 0x4c0e2001, 0xbf0065e0, 0x6e00480c,
+    0x0001f000, 0xd1f92800, 0x6e004809, 0x0004f000, 0x2002b908, 0x4806bd10, 0xf0006e00, 0xb1080002,
+    0xe7f72001, 0xe7f52000, 0x40000100, 0x40000200, 0x4000c000, 0x0055aa03, 0x00000000,
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init = 0x00000001,
+    .uninit = 0x0000007f,
+    .erase_sector = 0x000000a3,
+    .program_page = 0x00000289,
+    .static_base = 0x000003f8,
+    .algo_blob = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+    {0x0, 0x1000},          // (start, sector size)
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size  = 0x200,    // 512 bytes
+    .flash_start = 0x0,
+    .flash_size = 0x80000,  // 512 KB
+    .sectors = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_api.h"
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+uint32_t gpio_set(PinName pin)
+{
+    if (pin == (PinName) NC) {
+        return 0;
+    }
+
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+
+#if 1
+    pin_function(pin, 0 << NU_MFP_POS(pin_index));
+#else
+    pinmap_pinout(pin, PinMap_GPIO);
+#endif
+
+    return (uint32_t)(1 << pin_index);    // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+
+    obj->mask = gpio_set(pin);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+    uint32_t mode_intern = GPIO_MODE_INPUT;
+
+    switch (direction) {
+    case PIN_INPUT:
+        mode_intern = GPIO_MODE_INPUT;
+        break;
+
+    case PIN_OUTPUT:
+        mode_intern = GPIO_MODE_OUTPUT;
+        break;
+
+    default:
+        return;
+    }
+
+    GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,266 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_irq_api.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_bitutil.h"
+
+#define NU_MAX_PIN_PER_PORT     16
+
+struct nu_gpio_irq_var {
+    gpio_irq_t *    obj_arr[NU_MAX_PIN_PER_PORT];
+    IRQn_Type       irq_n;
+    void            (*vec)(void);
+    uint32_t        port_index;
+};
+
+static void gpio_irq_0_vec(void);
+static void gpio_irq_1_vec(void);
+static void gpio_irq_2_vec(void);
+static void gpio_irq_3_vec(void);
+static void gpio_irq_4_vec(void);
+static void gpio_irq_5_vec(void);
+static void gpio_irq_6_vec(void);
+static void gpio_irq_7_vec(void);
+static void gpio_irq(struct nu_gpio_irq_var *var);
+
+//EINT0_IRQn
+static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
+    {{NULL}, GPA_IRQn, gpio_irq_0_vec, 0},
+    {{NULL}, GPB_IRQn, gpio_irq_1_vec, 1},
+    {{NULL}, GPC_IRQn, gpio_irq_2_vec, 2},
+    {{NULL}, GPD_IRQn, gpio_irq_3_vec, 3},
+    {{NULL}, GPE_IRQn, gpio_irq_4_vec, 4},
+    {{NULL}, GPF_IRQn, gpio_irq_5_vec, 5},
+    {{NULL}, GPG_IRQn, gpio_irq_6_vec, 6},
+    {{NULL}, GPH_IRQn, gpio_irq_7_vec, 7},
+};
+
+#define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
+
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#endif
+
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
+#endif
+static PinName gpio_irq_debounce_arr[] = {
+    MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+};
+
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
+#endif
+
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
+#endif
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    if (pin == NC) {
+        return -1;
+    }
+
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
+        return -1;
+    }
+
+    obj->pin = pin;
+    obj->irq_handler = (uint32_t) handler;
+    obj->irq_id = id;
+
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
+    //       There is no need to call gpio_set() redundantly.
+
+    {
+#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
+        // Suppress compiler warning
+        (void) gpio_irq_debounce_arr;
+
+        // Configure de-bounce clock source and sampling cycle time
+        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+        GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#else
+        // Enable de-bounce if the pin is in the de-bounce enable list
+
+        // De-bounce defaults to disabled.
+        GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+
+        PinName *debounce_pos = gpio_irq_debounce_arr;
+        PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
+        for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
+            uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
+            uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
+
+            if (pin_index == pin_index_debunce &&
+                    port_index == port_index_debounce) {
+                // Configure de-bounce clock source and sampling cycle time
+                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+                break;
+            }
+        }
+#endif
+    }
+
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+    var->obj_arr[pin_index] = obj;
+
+    // NOTE: InterruptIn requires IRQ enabled by default.
+    gpio_irq_enable(obj);
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+    NVIC_DisableIRQ(var->irq_n);
+    NU_PORT_BASE(port_index)->INTEN = 0;
+
+    MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
+    var->obj_arr[pin_index] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+    switch (event) {
+    case IRQ_RISE:
+        if (enable) {
+            GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
+        } else {
+            gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
+        }
+        break;
+
+    case IRQ_FALL:
+        if (enable) {
+            GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
+        } else {
+            gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
+        }
+        break;
+
+    case IRQ_NONE:
+    default:
+        break;
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+    NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
+    NVIC_EnableIRQ(var->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+    NVIC_DisableIRQ(var->irq_n);
+}
+
+static void gpio_irq_0_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 0);
+}
+static void gpio_irq_1_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 1);
+}
+static void gpio_irq_2_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 2);
+}
+static void gpio_irq_3_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 3);
+}
+static void gpio_irq_4_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 4);
+}
+static void gpio_irq_5_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 5);
+}
+static void gpio_irq_6_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 6);
+}
+static void gpio_irq_7_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 7);
+}
+
+static void gpio_irq(struct nu_gpio_irq_var *var)
+{
+    // NOTE: GPA_IRQn, GPB_IRQn, ... are not arranged sequentially, so we cannot calculate out port_index through offset from GPA_IRQn.
+    //       Instead, we add port_index into gpio_irq_var_arr table.
+    uint32_t port_index = var->port_index;
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+    uint32_t intsrc = gpio_base->INTSRC;
+    uint32_t inten = gpio_base->INTEN;
+    while (intsrc) {
+        int pin_index = nu_ctz(intsrc);
+        gpio_irq_t *obj = var->obj_arr[pin_index];
+        if (inten & (GPIO_INT_RISING << pin_index)) {
+            if (GPIO_PIN_DATA(port_index, pin_index)) {
+                if (obj->irq_handler) {
+                    ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
+                }
+            }
+        }
+
+        if (inten & (GPIO_INT_FALLING << pin_index)) {
+            if (! GPIO_PIN_DATA(port_index, pin_index)) {
+                if (obj->irq_handler) {
+                    ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
+                }
+            }
+        }
+
+        intsrc &= ~(1 << pin_index);
+    }
+    // Clear all interrupt flags
+    gpio_base->INTSRC = gpio_base->INTSRC;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_object.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+
+    GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+
+    return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,935 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+#include "mbed_critical.h"
+
+struct nu_i2c_var {
+    i2c_t *     obj;
+    void        (*vec)(void);
+};
+
+static void i2c0_vec(void);
+static void i2c1_vec(void);
+static void i2c2_vec(void);
+static void i2c_irq(i2c_t *obj);
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
+static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
+
+static struct nu_i2c_var i2c0_var = {
+    .obj                =   NULL,
+    .vec                =   i2c0_vec,
+};
+static struct nu_i2c_var i2c1_var = {
+    .obj                =   NULL,
+    .vec                =   i2c1_vec,
+};
+static struct nu_i2c_var i2c2_var = {
+    .obj                =   NULL,
+    .vec                =   i2c2_vec,
+};
+
+static uint32_t i2c_modinit_mask = 0;
+
+static const struct nu_modinit_s i2c_modinit_tab[] = {
+    {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
+    {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
+    {I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var},
+
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
+#define NU_I2C_TIMEOUT_STAT_INT     500000
+#define NU_I2C_TIMEOUT_STOP         500000
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
+static int i2c_is_trsn_done(i2c_t *obj);
+static int i2c_is_tran_started(i2c_t *obj);
+static int i2c_addr2data(int address, int read);
+#if DEVICE_I2CSLAVE
+// Convert mbed address to BSP address.
+static int i2c_addr2bspaddr(int address);
+#endif  // #if DEVICE_I2CSLAVE
+static void i2c_enable_int(i2c_t *obj);
+static void i2c_disable_int(i2c_t *obj);
+static int i2c_set_int(i2c_t *obj, int inten);
+
+
+#if DEVICE_I2C_ASYNCH
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
+static void i2c_rollback_vector_interrupt(i2c_t *obj);
+#endif
+
+#define TRANCTRL_STARTED        (1)
+#define TRANCTRL_NAKLASTDATA    (1 << 1)
+#define TRANCTRL_LASTDATANAKED  (1 << 2)
+
+uint32_t us_ticker_read(void);
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+    uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->i2c.i2c != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
+
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+
+#if DEVICE_I2C_ASYNCH
+    obj->i2c.dma_usage = DMA_USAGE_NEVER;
+    obj->i2c.event = 0;
+    obj->i2c.stop = 0;
+    obj->i2c.address = 0;
+#endif
+
+    // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
+    I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
+    // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. We cannot control interrupt through
+    //       INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk);
+
+    // Enable sync-mode vector interrupt.
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    var->obj = obj;
+    obj->i2c.tran_ctrl = 0;
+    obj->i2c.stop = 0;
+    i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
+
+    // Mark this module to be inited.
+    int i = modinit - i2c_modinit_tab;
+    i2c_modinit_mask |= 1 << i;
+}
+
+int i2c_start(i2c_t *obj)
+{
+    return i2c_do_trsn(obj, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk, 1);
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    return i2c_do_trsn(obj, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk, 1);
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Read in bytes
+    length = i2c_do_tran(obj, data, length, 1, 1);
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Write out bytes
+    length = i2c_do_tran(obj, (char *) data, length, 0, 1);
+
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    char data = 0;
+    i2c_do_tran(obj, &data, 1, 1, last);
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    char data_[1];
+    data_[0] = data & 0xFF;
+
+    if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
+            ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+#if DEVICE_I2CSLAVE
+
+// See I2CSlave.h
+#define NoData         0    // the slave has not been addressed
+#define ReadAddressed  1    // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral   2    // the master is writing to all slave
+#define WriteAddressed 3    // the master is writing to this slave (slave = receiver)
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    i2c_disable_int(obj);
+
+    obj->i2c.slaveaddr_state = NoData;
+
+    // Switch to not addressed mode
+    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+
+    i2c_enable_int(obj);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+    int slaveaddr_state;
+
+    i2c_disable_int(obj);
+    slaveaddr_state = obj->i2c.slaveaddr_state;
+    i2c_enable_int(obj);
+
+    return slaveaddr_state;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+    return i2c_do_tran(obj, data, length, 1, 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+    return i2c_do_tran(obj, (char *) data, length, 0, 1);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    i2c_disable_int(obj);
+
+    // NOTE: On NUC472/M451, non-zero slave address can still work as GC mode is enabled.
+    //       On M480, non-zero slave address won't work as GC mode is enabled.
+    I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_DISABLE);
+
+    i2c_enable_int(obj);
+}
+
+static int i2c_addr2bspaddr(int address)
+{
+    return (address >> 1);
+}
+
+#endif // #if DEVICE_I2CSLAVE
+
+static void i2c_enable_int(i2c_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+
+    core_util_critical_section_enter();
+
+    // Enable I2C interrupt
+    NVIC_EnableIRQ(modinit->irq_n);
+    obj->i2c.inten = 1;
+
+    core_util_critical_section_exit();
+}
+
+static void i2c_disable_int(i2c_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+
+    core_util_critical_section_enter();
+
+    // Disable I2C interrupt
+    NVIC_DisableIRQ(modinit->irq_n);
+    obj->i2c.inten = 0;
+
+    core_util_critical_section_exit();
+}
+
+static int i2c_set_int(i2c_t *obj, int inten)
+{
+    int inten_back;
+
+    core_util_critical_section_enter();
+
+    inten_back = obj->i2c.inten;
+
+    core_util_critical_section_exit();
+
+    if (inten) {
+        i2c_enable_int(obj);
+    } else {
+        i2c_disable_int(obj);
+    }
+
+    return inten_back;
+}
+
+int i2c_allow_powerdown(void)
+{
+    uint32_t modinit_mask = i2c_modinit_mask;
+    while (modinit_mask) {
+        int i2c_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
+        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+        if (var->obj) {
+            // Disallow entering power-down mode if I2C transfer is enabled.
+            if (i2c_active(var->obj)) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << i2c_idx);
+    }
+
+    return 1;
+}
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
+{
+    if (! buf || ! length) {
+        return 0;
+    }
+
+    int tran_len = 0;
+
+    i2c_disable_int(obj);
+    obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
+    obj->i2c.tran_beg = buf;
+    obj->i2c.tran_pos = buf;
+    obj->i2c.tran_end = buf + length;
+    i2c_enable_int(obj);
+
+    if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
+        // N/A
+    } else {
+        i2c_disable_int(obj);
+        tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
+        obj->i2c.tran_beg = NULL;
+        obj->i2c.tran_pos = NULL;
+        obj->i2c.tran_end = NULL;
+        i2c_enable_int(obj);
+    }
+
+    return tran_len;
+}
+
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int err = 0;
+
+    i2c_disable_int(obj);
+
+    if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+        err = I2C_ERROR_BUS_BUSY;
+    } else {
+        // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
+        uint32_t status = I2C_GET_STATUS(i2c_base);
+
+        switch (status) {
+        case 0x08:  // Start
+        case 0x10:  // Master Repeat Start
+            if (i2c_ctl & I2C_CTL0_STA_Msk) {
+                return 0;
+            } else {
+                break;
+            }
+        case 0xF8:  // Bus Released
+            if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) {
+                return 0;
+            } else {
+                break;
+            }
+        }
+        I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+        if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+            err = I2C_ERROR_BUS_BUSY;
+        }
+    }
+
+    i2c_enable_int(obj);
+
+    return err;
+}
+
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
+{
+    uint32_t t1, t2, elapsed = 0;
+    int status_assert = 0;
+
+    t1 = us_ticker_read();
+    while (1) {
+        status_assert = is_status(obj);
+        if (status_assert) {
+            break;
+        }
+
+        t2 = us_ticker_read();
+        elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+        if (elapsed >= timeout) {
+            break;
+        }
+    }
+
+    return (elapsed >= timeout);
+}
+
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
+{
+    uint32_t t1, t2, elapsed = 0;
+    int tran_started;
+    char *tran_pos = NULL;
+    char *tran_pos2 = NULL;
+
+    i2c_disable_int(obj);
+    tran_pos = obj->i2c.tran_pos;
+    i2c_enable_int(obj);
+    t1 = us_ticker_read();
+    while (1) {
+        i2c_disable_int(obj);
+        tran_started = i2c_is_tran_started(obj);
+        i2c_enable_int(obj);
+        if (! tran_started) {    // Transfer completed or stopped
+            break;
+        }
+
+        i2c_disable_int(obj);
+        tran_pos2 = obj->i2c.tran_pos;
+        i2c_enable_int(obj);
+        t2 = us_ticker_read();
+        if (tran_pos2 != tran_pos) {    // Transfer on-going
+            t1 = t2;
+            tran_pos = tran_pos2;
+            continue;
+        }
+
+        elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+        if (elapsed >= timeout) {   // Transfer idle
+            break;
+        }
+    }
+
+    return (elapsed >= timeout);
+}
+
+#if 0
+static int i2c_is_stat_int(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    return !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk);
+}
+
+static int i2c_is_stop_det(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    return ! (i2c_base->CTL0 & I2C_CTL0_STO_Msk);
+}
+#endif
+
+static int i2c_is_trsn_done(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int i2c_int;
+    uint32_t status;
+    int inten_back;
+
+    inten_back = i2c_set_int(obj, 0);
+    i2c_int = !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk);
+    status = I2C_GET_STATUS(i2c_base);
+    i2c_set_int(obj, inten_back);
+
+    return (i2c_int || status == 0xF8);
+}
+
+static int i2c_is_tran_started(i2c_t *obj)
+{
+    int started;
+    int inten_back;
+
+    inten_back = i2c_set_int(obj, 0);
+    started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
+    i2c_set_int(obj, inten_back);
+
+    return started;
+}
+
+static int i2c_addr2data(int address, int read)
+{
+    return read ? (address | 1) : (address & 0xFE);
+}
+
+static void i2c0_vec(void)
+{
+    i2c_irq(i2c0_var.obj);
+}
+static void i2c1_vec(void)
+{
+    i2c_irq(i2c1_var.obj);
+}
+static void i2c2_vec(void)
+{
+    i2c_irq(i2c2_var.obj);
+}
+
+static void i2c_irq(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    uint32_t status;
+
+    if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
+        I2C_ClearTimeoutFlag(i2c_base);
+        return;
+    }
+
+    status = I2C_GET_STATUS(i2c_base);
+
+    switch (status) {
+    // Master Transmit
+    case 0x28:  // Master Transmit Data ACK
+    case 0x18:  // Master Transmit Address ACK
+    case 0x08:  // Start
+    case 0x10:  // Master Repeat Start
+        if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+            if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+            } else {
+                i2c_fsm_tranfini(obj, 0);
+            }
+        } else {
+            i2c_disable_int(obj);
+        }
+        break;
+
+    case 0x30:  // Master Transmit Data NACK
+        i2c_fsm_tranfini(obj, 1);
+        break;
+
+    case 0x20:  // Master Transmit Address NACK
+        i2c_fsm_tranfini(obj, 1);
+        break;
+
+    case 0x38:  // Master Arbitration Lost
+        i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+        break;
+
+    case 0x48:  // Master Receive Address NACK
+        i2c_fsm_tranfini(obj, 1);
+        break;
+
+    case 0x40:  // Master Receive Address ACK
+    case 0x50:  // Master Receive Data ACK
+    case 0x58:  // Master Receive Data NACK
+        if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+            if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                if (status == 0x50 || status == 0x58) {
+                    *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                }
+
+                if (status == 0x58) {
+                    i2c_fsm_tranfini(obj, 1);
+                } else {
+                    uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
+                    if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                        // Last data
+                        i2c_ctl &= ~I2C_CTL0_AA_Msk;
+                    }
+                    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                }
+            } else {
+                obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                i2c_disable_int(obj);
+                break;
+            }
+        } else {
+            i2c_disable_int(obj);
+        }
+        break;
+
+    //case 0x00:  // Bus error
+
+    // Slave Transmit
+    case 0xB8:  // Slave Transmit Data ACK
+    case 0xA8:  // Slave Transmit Address ACK
+    case 0xB0:  // Slave Transmit Arbitration Lost
+        if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+            if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
+
+                I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+                if (obj->i2c.tran_pos == obj->i2c.tran_end &&
+                        obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                    // Last data
+                    i2c_ctl &= ~I2C_CTL0_AA_Msk;
+                }
+                I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+            } else {
+                obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                i2c_disable_int(obj);
+                break;
+            }
+        } else {
+            i2c_disable_int(obj);
+        }
+        obj->i2c.slaveaddr_state = ReadAddressed;
+        break;
+    //case 0xA0:  // Slave Transmit Repeat Start or Stop
+    case 0xC0:  // Slave Transmit Data NACK
+    case 0xC8:  // Slave Transmit Last Data ACK
+        obj->i2c.slaveaddr_state = NoData;
+        i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+        break;
+
+    // Slave Receive
+    case 0x80:  // Slave Receive Data ACK
+    case 0x88:  // Slave Receive Data NACK
+    case 0x60:  // Slave Receive Address ACK
+    case 0x68:  // Slave Receive Arbitration Lost
+        obj->i2c.slaveaddr_state = WriteAddressed;
+        if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+            if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                if (status == 0x80 || status == 0x88) {
+                    *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                }
+
+                if (status == 0x88) {
+                    obj->i2c.slaveaddr_state = NoData;
+                    i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+                } else {
+                    uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
+                    if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                        // Last data
+                        i2c_ctl &= ~I2C_CTL0_AA_Msk;
+                    }
+                    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                }
+            } else {
+                obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                i2c_disable_int(obj);
+                break;
+            }
+        } else {
+            i2c_disable_int(obj);
+        }
+        break;
+    //case 0xA0:  // Slave Receive Repeat Start or Stop
+
+    // GC mode
+    //case 0xA0:  // GC mode Repeat Start or Stop
+    case 0x90:  // GC mode Data ACK
+    case 0x98:  // GC mode Data NACK
+    case 0x70:  // GC mode Address ACK
+    case 0x78:  // GC mode Arbitration Lost
+        obj->i2c.slaveaddr_state = WriteAddressed;
+        if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+            if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                if (status == 0x90 || status == 0x98) {
+                    *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                }
+
+                if (status == 0x98) {
+                    obj->i2c.slaveaddr_state = NoData;
+                    i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+                } else {
+                    uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk;
+                    if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                        // Last data
+                        i2c_ctl &= ~I2C_CTL0_AA_Msk;
+                    }
+                    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                }
+            } else {
+                obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                i2c_disable_int(obj);
+                break;
+            }
+        } else {
+            i2c_disable_int(obj);
+        }
+        break;
+
+    case 0xF8:  // Bus Released
+        break;
+
+    default:
+        i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
+    }
+}
+
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    obj->i2c.stop = 0;
+
+    obj->i2c.tran_ctrl = 0;
+
+    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+    obj->i2c.slaveaddr_state = NoData;
+}
+
+static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
+{
+    if (lastdatanaked) {
+        obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
+    }
+
+    obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+    i2c_disable_int(obj);
+}
+
+#if DEVICE_I2C_ASYNCH
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
+    MBED_ASSERT((address & 0xFFFFFF00) == 0);
+
+    // NOTE: First transmit and then receive.
+
+    (void) hint;
+    obj->i2c.dma_usage = DMA_USAGE_NEVER;
+    obj->i2c.stop = stop;
+    obj->i2c.address = address;
+    obj->i2c.event = event;
+    i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
+
+    i2c_enable_vector_interrupt(obj, handler, 1);
+    i2c_start(obj);
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+    int event = 0;
+
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    uint32_t status = I2C_GET_STATUS(i2c_base);
+    switch (status) {
+    case 0x08:  // Start
+    case 0x10: {// Master Repeat Start
+        if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+            I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
+        } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+            I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
+        } else {
+            event = I2C_EVENT_TRANSFER_COMPLETE;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+            }
+        }
+        break;
+    }
+
+    case 0x18:  // Master Transmit Address ACK
+    case 0x28:  // Master Transmit Data ACK
+        if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+            uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
+            I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
+        } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
+        } else {
+            event = I2C_EVENT_TRANSFER_COMPLETE;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+            }
+        }
+        break;
+
+    case 0x20:  // Master Transmit Address NACK
+        event = I2C_EVENT_ERROR_NO_SLAVE;
+        if (obj->i2c.stop) {
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+        }
+        break;
+
+    case 0x30:  // Master Transmit Data NACK
+        if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+            event = I2C_EVENT_TRANSFER_EARLY_NACK;
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+        } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
+        } else {
+            event = I2C_EVENT_TRANSFER_COMPLETE;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+            }
+        }
+        break;
+
+    case 0x38:  // Master Arbitration Lost
+        I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);  // Enter not addressed SLV mode
+        event = I2C_EVENT_ERROR;
+        break;
+
+    case 0x50:  // Master Receive Data ACK
+        if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+            uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+            rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+        }
+    case 0x40:  // Master Receive Address ACK
+        I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL0_AA_Msk : 0));
+        break;
+
+    case 0x48:  // Master Receive Address NACK
+        event = I2C_EVENT_ERROR_NO_SLAVE;
+        if (obj->i2c.stop) {
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+        }
+        break;
+
+    case 0x58:  // Master Receive Data NACK
+        if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+            uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+            rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+        }
+        I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
+        break;
+
+    case 0x00:  // Bus error
+        event = I2C_EVENT_ERROR;
+        i2c_reset(obj);
+        break;
+
+    default:
+        event = I2C_EVENT_ERROR;
+        if (obj->i2c.stop) {
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
+        }
+    }
+
+    if (event) {
+        i2c_rollback_vector_interrupt(obj);
+    }
+
+    return (event & obj->i2c.event);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
+
+    // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
+    uint32_t vec = NVIC_GetVector(modinit->irq_n);
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    return (vec && vec != (uint32_t) var->vec);
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+    i2c_rollback_vector_interrupt(obj);
+    i2c_stop(obj);
+}
+
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+}
+
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
+
+    if (enable) {
+        NVIC_SetVector(modinit->irq_n, handler);
+        i2c_enable_int(obj);
+    } else {
+        i2c_disable_int(obj);
+    }
+
+}
+
+static void i2c_rollback_vector_interrupt(i2c_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
+
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
+}
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,228 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "sleep_api.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "mbed_critical.h"
+
+// lp_ticker tick = us = timestamp
+#define US_PER_TICK             (1)
+#define US_PER_SEC              (1000 * 1000)
+
+#define US_PER_TMR2_INT         (US_PER_SEC * 10)
+#define TMR2_CLK_PER_SEC        (__LXT)
+#define TMR2_CLK_PER_TMR2_INT   ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
+#define TMR3_CLK_PER_SEC        (__LXT)
+
+static void tmr2_vec(void);
+static void tmr3_vec(void);
+static void lp_ticker_arm_cd(void);
+
+static int lp_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile uint32_t cd_major_minor_clks = 0;
+static volatile uint32_t cd_minor_clks = 0;
+static volatile uint32_t wakeup_tick = (uint32_t) -1;
+
+// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
+// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
+static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
+static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
+
+#define TMR_CMP_MIN         2
+#define TMR_CMP_MAX         0xFFFFFFu
+
+void lp_ticker_init(void)
+{
+    if (lp_ticker_inited) {
+        return;
+    }
+    lp_ticker_inited = 1;
+
+    counter_major = 0;
+    cd_major_minor_clks = 0;
+    cd_minor_clks = 0;
+    wakeup_tick = (uint32_t) -1;
+
+    // Reset module
+    SYS_ResetModule(timer2_modinit.rsetidx);
+    SYS_ResetModule(timer3_modinit.rsetidx);
+
+    // Select IP clock source
+    CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
+    CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(timer2_modinit.clkidx);
+    CLK_EnableModuleClock(timer3_modinit.clkidx);
+
+    // Configure clock
+    uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
+    MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
+    MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
+    MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+    // Continuous mode
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
+    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
+    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
+
+    // Set vector
+    NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
+    NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
+
+    NVIC_EnableIRQ(timer2_modinit.irq_n);
+    NVIC_EnableIRQ(timer3_modinit.irq_n);
+
+    TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+
+    // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
+    //       timer is not running.
+
+    // Start timer
+    TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+
+    // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
+    lp_ticker_set_interrupt(wakeup_tick);
+
+
+}
+
+timestamp_t lp_ticker_read()
+{
+    if (! lp_ticker_inited) {
+        lp_ticker_init();
+    }
+
+    TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
+
+    do {
+        uint64_t major_minor_clks;
+        uint32_t minor_clks;
+
+        // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
+        // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
+        do {
+            core_util_critical_section_enter();
+
+            // NOTE: Order of reading minor_us/carry here is significant.
+            minor_clks = TIMER_GetCounter(timer2_base);
+            uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
+            // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Handle carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
+            if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
+                major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
+            } else {
+                major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
+            }
+
+            core_util_critical_section_exit();
+        } while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
+
+        // Add power-down compensation
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
+    } while (0);
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    uint32_t now = lp_ticker_read();
+    wakeup_tick = timestamp;
+
+    TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+
+    int delta = (int) (timestamp - now);
+    if (delta > 0) {
+        cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+        lp_ticker_arm_cd();
+    } else {
+        // NOTE: With lp_ticker_fire_interrupt() introduced, upper layer would handle past event case.
+        //       This code fragment gets redundant, but it is still kept here for backward-compatible.
+        void lp_ticker_fire_interrupt(void);
+        lp_ticker_fire_interrupt();
+    }
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+    // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+    //       This prevents a recursive loop under heavy load which can lead to a stack overflow.
+    cd_major_minor_clks = cd_minor_clks = 0;
+    NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+static void tmr2_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    counter_major ++;
+}
+
+static void tmr3_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
+    if (cd_major_minor_clks == 0) {
+        // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+        lp_ticker_irq_handler();
+    } else {
+        lp_ticker_arm_cd();
+    }
+}
+
+static void lp_ticker_arm_cd(void)
+{
+    TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+
+    // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
+    // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
+    // M480
+    timer3_base->CNT = 0;
+    while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk);
+    // One-shot mode, Clock = 1 KHz
+    uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
+    MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
+    MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
+    timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
+    timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
+
+    cd_minor_clks = cd_major_minor_clks;
+    cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer3_base->CMP = cd_minor_clks;
+
+    TIMER_EnableInt(timer3_base);
+    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    TIMER_Start(timer3_base);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+/**
+ * Configure pin multi-function
+ */
+void pin_function(PinName pin, int data)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
+    uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
+
+    // E.g.: SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD  ;
+    *GPx_MFPx  = (*GPx_MFPx & (~MFP_Msk)) | data;
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+    uint32_t mode_intern = GPIO_MODE_INPUT;
+
+    switch (mode) {
+    case PullUp:
+        mode_intern = GPIO_MODE_INPUT;
+        break;
+
+    case PullDown:
+    case PullNone:
+        // NOTE: Not support
+        return;
+
+    case PushPull:
+        mode_intern = GPIO_MODE_OUTPUT;
+        break;
+
+    case OpenDrain:
+        mode_intern = GPIO_MODE_OPEN_DRAIN;
+        break;
+
+    case Quasi:
+        mode_intern = GPIO_MODE_QUASI;
+        break;
+    }
+
+    GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/port_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "port_api.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
+
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    obj->port      = port;
+    obj->mask      = mask;
+    obj->direction = dir;
+
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            gpio_set(port_pin(port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            if (dir == PIN_OUTPUT) {
+                GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT);
+            } else { // PIN_INPUT
+                GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT);
+            }
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    uint32_t i;
+    uint32_t port_index = obj->port;
+
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
+        }
+    }
+}
+
+int port_read(port_t *obj)
+{
+    uint32_t i;
+    uint32_t port_index = obj->port;
+    int value = 0;
+
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            value = value | (GPIO_PIN_DATA(port_index, i) << i);
+        }
+    }
+
+    return value;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,214 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+struct nu_pwm_var {
+    uint32_t    en_msk;
+};
+
+static struct nu_pwm_var pwm0_var = {
+    .en_msk = 0
+};
+
+static struct nu_pwm_var pwm1_var = {
+    .en_msk = 0
+};
+
+static uint32_t pwm_modinit_mask = 0;
+
+static const struct nu_modinit_s pwm_modinit_tab[] = {
+    {PWM_0_0, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var},
+    {PWM_0_1, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var},
+    {PWM_0_2, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var},
+    {PWM_0_3, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var},
+    {PWM_0_4, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var},
+    {PWM_0_5, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var},
+
+    {PWM_1_0, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var},
+    {PWM_1_1, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var},
+    {PWM_1_2, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var},
+    {PWM_1_3, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var},
+    {PWM_1_4, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var},
+    {PWM_1_5, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var},
+
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static void pwmout_config(pwmout_t* obj, int start);
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+    obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT((int) obj->pwm != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->pwm);
+
+    // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
+    if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
+        // Reset this module if no channel enabled
+        SYS_ResetModule(modinit->rsetidx);
+    }
+
+    uint32_t chn =  NU_MODSUBINDEX(obj->pwm);
+
+    // NOTE: Channels 0/1/2/3/4/5 share a clock source.
+    if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
+        // Select clock source of paired channels
+        CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+        // Enable clock of paired channels
+        CLK_EnableModuleClock(modinit->clkidx);
+    }
+
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+
+    // Default: period = 10 ms, pulse width = 0 ms
+    obj->period_us = 1000 * 10;
+    obj->pulsewidth_us = 0;
+    pwmout_config(obj, 0);
+
+    ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
+
+    // Mark this module to be inited.
+    int i = modinit - pwm_modinit_tab;
+    pwm_modinit_mask |= 1 << i;
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+    EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm);
+    uint32_t chn =  NU_MODSUBINDEX(obj->pwm);
+    EPWM_ForceStop(pwm_base, 1 << chn);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->pwm);
+    ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
+
+
+    if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
+        CLK_DisableModuleClock(modinit->clkidx);
+    }
+
+    // Mark this module to be deinited.
+    int i = modinit - pwm_modinit_tab;
+    pwm_modinit_mask &= ~(1 << i);
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+    obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
+    pwmout_config(obj, 1);
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+    return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+    uint32_t period_us_old = obj->period_us;
+    uint32_t pulsewidth_us_old = obj->pulsewidth_us;
+    obj->period_us = us;
+    obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
+    pwmout_config(obj, 1);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+    obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
+    pwmout_config(obj, 1);
+}
+
+int pwmout_allow_powerdown(void)
+{
+    uint32_t modinit_mask = pwm_modinit_mask;
+    while (modinit_mask) {
+        int pwm_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
+        if (modinit->modname != NC) {
+            EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(modinit->modname);
+            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
+            // Disallow entering power-down mode if PWM counter is enabled.
+            if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << pwm_idx);
+    }
+
+    return 1;
+}
+
+static void pwmout_config(pwmout_t* obj, int start)
+{
+    EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm);
+    uint32_t chn = NU_MODSUBINDEX(obj->pwm);
+
+    // To avoid abnormal pulse on (re-)configuration, follow the sequence: stop/configure(/re-start).
+    // NOTE: The issue is met in ARM mbed CI test tests-api-pwm on M487.
+    EPWM_ForceStop(pwm_base, 1 << chn);
+
+    // NOTE: Support period < 1s
+    // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
+    //       1. Inverse duty cycle (100 - duty)
+    //       2. Inverse PWM output polarity
+    //       This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
+    EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
+    pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);
+
+    if (start) {
+        // Enable output of the specified PWM channel
+        EPWM_EnableOutput(pwm_base, 1 << chn);
+        EPWM_Start(pwm_base, 1 << chn);
+    }
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_wait_api.h"
+#include "mbed_error.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+
+#define YEAR0       1900
+//#define EPOCH_YR    1970
+
+static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
+
+void rtc_init(void)
+{
+    if (rtc_isenabled()) {
+        return;
+    }
+
+    RTC_Open(NULL);
+}
+
+void rtc_free(void)
+{
+    // N/A
+}
+
+int rtc_isenabled(void)
+{
+    // NOTE: To access (RTC) registers, clock must be enabled first.
+    if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
+        // Enable IP clock
+        CLK_EnableModuleClock(rtc_modinit.clkidx);
+    }
+
+    // NOTE: Check RTC Init Active flag to support crossing reset cycle.
+    return !! (RTC->INIT & RTC_INIT_ACTIVE_Msk);
+}
+
+/*
+ struct tm
+   tm_sec      seconds after the minute 0-61
+   tm_min      minutes after the hour 0-59
+   tm_hour     hours since midnight 0-23
+   tm_mday     day of the month 1-31
+   tm_mon      months since January 0-11
+   tm_year     years since 1900
+   tm_wday     days since Sunday 0-6
+   tm_yday     days since January 1 0-365
+   tm_isdst    Daylight Saving Time flag
+*/
+
+time_t rtc_read(void)
+{
+    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+    //       NUC472/M453: Known issue
+    //       M487: Fixed
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    S_RTC_TIME_DATA_T rtc_datetime;
+    RTC_GetDateAndTime(&rtc_datetime);
+
+    struct tm timeinfo;
+
+    // Convert struct tm to S_RTC_TIME_DATA_T
+    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
+    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
+    timeinfo.tm_mday = rtc_datetime.u32Day;
+    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
+    timeinfo.tm_hour = rtc_datetime.u32Hour;
+    timeinfo.tm_min  = rtc_datetime.u32Minute;
+    timeinfo.tm_sec  = rtc_datetime.u32Second;
+
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+
+    return t;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    // Convert timestamp to struct tm
+    struct tm *timeinfo = localtime(&t);
+
+    S_RTC_TIME_DATA_T rtc_datetime;
+
+    // Convert S_RTC_TIME_DATA_T to struct tm
+    rtc_datetime.u32Year        = timeinfo->tm_year + YEAR0;
+    rtc_datetime.u32Month       = timeinfo->tm_mon + 1;
+    rtc_datetime.u32Day         = timeinfo->tm_mday;
+    rtc_datetime.u32DayOfWeek   = timeinfo->tm_wday;
+    rtc_datetime.u32Hour        = timeinfo->tm_hour;
+    rtc_datetime.u32Minute      = timeinfo->tm_min;
+    rtc_datetime.u32Second      = timeinfo->tm_sec;
+    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
+
+    // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
+    RTC_SetDateAndTime(&rtc_datetime);
+    wait_us(100);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1167 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "mbed_error.h"
+#include "mbed_assert.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include <string.h>
+
+#if DEVICE_SERIAL_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+struct nu_uart_var {
+    uint32_t    ref_cnt;                // Reference count of the H/W module
+    serial_t *  obj;
+    uint32_t    fifo_size_tx;
+    uint32_t    fifo_size_rx;
+    void        (*vec)(void);
+#if DEVICE_SERIAL_ASYNCH
+    void        (*vec_async)(void);
+    uint8_t     pdma_perp_tx;
+    uint8_t     pdma_perp_rx;
+#endif
+};
+
+static void uart0_vec(void);
+static void uart1_vec(void);
+static void uart2_vec(void);
+static void uart3_vec(void);
+static void uart4_vec(void);
+static void uart5_vec(void);
+static void uart_irq(serial_t *obj);
+
+#if DEVICE_SERIAL_ASYNCH
+static void uart0_vec_async(void);
+static void uart1_vec_async(void);
+static void uart2_vec_async(void);
+static void uart3_vec_async(void);
+static void uart4_vec_async(void);
+static void uart5_vec_async(void);
+static void uart_irq_async(serial_t *obj);
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event);
+static void uart_dma_handler_rx(uint32_t id, uint32_t event);
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
+static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
+static int serial_write_async(serial_t *obj);
+static int serial_read_async(serial_t *obj);
+
+static uint32_t serial_rx_event_check(serial_t *obj);
+static uint32_t serial_tx_event_check(serial_t *obj);
+
+static int serial_is_tx_complete(serial_t *obj);
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
+static int serial_is_rx_complete(serial_t *obj);
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
+#endif
+
+static struct nu_uart_var uart0_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart0_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart0_vec_async,
+    .pdma_perp_tx       =   PDMA_UART0_TX,
+    .pdma_perp_rx       =   PDMA_UART0_RX
+#endif
+};
+static struct nu_uart_var uart1_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart1_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart1_vec_async,
+    .pdma_perp_tx       =   PDMA_UART1_TX,
+    .pdma_perp_rx       =   PDMA_UART1_RX
+#endif
+};
+static struct nu_uart_var uart2_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart2_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart2_vec_async,
+    .pdma_perp_tx       =   PDMA_UART2_TX,
+    .pdma_perp_rx       =   PDMA_UART2_RX
+#endif
+};
+static struct nu_uart_var uart3_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart3_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart3_vec_async,
+    .pdma_perp_tx       =   PDMA_UART3_TX,
+    .pdma_perp_rx       =   PDMA_UART3_RX
+#endif
+};
+static struct nu_uart_var uart4_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart4_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart4_vec_async,
+    .pdma_perp_tx       =   PDMA_UART4_TX,
+    .pdma_perp_rx       =   PDMA_UART4_RX
+#endif
+};
+static struct nu_uart_var uart5_var = {
+    .ref_cnt            =   0,
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart5_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart5_vec_async,
+    .pdma_perp_tx       =   PDMA_UART5_TX,
+    .pdma_perp_rx       =   PDMA_UART5_RX
+#endif
+};
+
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+static uint32_t uart_modinit_mask = 0;
+
+static const struct nu_modinit_s uart_modinit_tab[] = {
+    {UART_0, UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1), UART0_RST, UART0_IRQn, &uart0_var},
+    {UART_1, UART1_MODULE, CLK_CLKSEL1_UART1SEL_HIRC, CLK_CLKDIV0_UART1(1), UART1_RST, UART1_IRQn, &uart1_var},
+    {UART_2, UART2_MODULE, CLK_CLKSEL3_UART2SEL_HIRC, CLK_CLKDIV4_UART2(1), UART2_RST, UART2_IRQn, &uart2_var},
+    {UART_3, UART3_MODULE, CLK_CLKSEL3_UART3SEL_HIRC, CLK_CLKDIV4_UART3(1), UART3_RST, UART3_IRQn, &uart3_var},
+    {UART_4, UART4_MODULE, CLK_CLKSEL3_UART4SEL_HIRC, CLK_CLKDIV4_UART4(1), UART4_RST, UART4_IRQn, &uart4_var},
+    {UART_5, UART5_MODULE, CLK_CLKSEL3_UART5SEL_HIRC, CLK_CLKDIV4_UART5(1), UART5_RST, UART5_IRQn, &uart5_var},
+
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+extern void mbed_sdk_init(void);
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
+    mbed_sdk_init();
+
+    // Determine which UART_x the pins are used for
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    // Get the peripheral name (UART_x) from the pins and assign it to the object
+    obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->serial.uart != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+
+    if (! var->ref_cnt) {
+        do {
+            // Reset this module
+            SYS_ResetModule(modinit->rsetidx);
+
+            // Select IP clock source
+            CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+            // Enable IP clock
+            CLK_EnableModuleClock(modinit->clkidx);
+
+            pinmap_pinout(tx, PinMap_UART_TX);
+            pinmap_pinout(rx, PinMap_UART_RX);
+        } while (0);
+
+        obj->serial.pin_tx = tx;
+        obj->serial.pin_rx = rx;
+    }
+    var->ref_cnt ++;
+
+    // Configure the UART module and set its baudrate
+    serial_baud(obj, 9600);
+    // Configure data bits, parity, and stop bits
+    serial_format(obj, 8, ParityNone, 1);
+
+    obj->serial.vec = var->vec;
+    obj->serial.irq_en = 0;
+
+#if DEVICE_SERIAL_ASYNCH
+    obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
+    obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+    obj->serial.event = 0;
+    obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+    // For stdio management
+    if (obj->serial.uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+
+    if (var->ref_cnt) {
+        // Mark this module to be inited.
+        int i = modinit - uart_modinit_tab;
+        uart_modinit_mask |= 1 << i;
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+
+    var->ref_cnt --;
+    if (! var->ref_cnt) {
+#if DEVICE_SERIAL_ASYNCH
+        if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+            dma_channel_free(obj->serial.dma_chn_id_tx);
+            obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+        }
+        if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+            dma_channel_free(obj->serial.dma_chn_id_rx);
+            obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+        }
+#endif
+
+        do {
+            UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
+
+            UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+            NVIC_DisableIRQ(modinit->irq_n);
+
+            // Disable IP clock
+            CLK_DisableModuleClock(modinit->clkidx);
+        } while (0);
+    }
+
+    if (var->obj == obj) {
+        var->obj = NULL;
+    }
+
+    if (obj->serial.uart == STDIO_UART) {
+        stdio_uart_inited = 0;
+    }
+
+    if (! var->ref_cnt) {
+        // Mark this module to be deinited.
+        int i = modinit - uart_modinit_tab;
+        uart_modinit_mask &= ~(1 << i);
+    }
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+    obj->serial.baudrate = baudrate;
+    UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+    // Sanity check arguments
+    MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+
+    obj->serial.databits = data_bits;
+    obj->serial.parity = parity;
+    obj->serial.stopbits = stop_bits;
+
+    uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
+                               (data_bits == 6) ? UART_WORD_LEN_6 :
+                               (data_bits == 7) ? UART_WORD_LEN_7 :
+                               UART_WORD_LEN_8;
+    uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
+                             (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
+                             UART_PARITY_NONE;
+    uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
+    UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
+                        0,  // Don't change baudrate
+                        databits_intern,
+                        parity_intern,
+                        stopbits_intern);
+}
+
+#if DEVICE_SERIAL_FC
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    // First, disable flow control completely.
+    uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+
+    if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
+        // Check if RTS pin matches.
+        uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
+        MBED_ASSERT(uart_rts == obj->serial.uart);
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+
+        // NOTE: Added in M480. Before configuring RTSACTLV, disable TX/RX.
+        uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk;
+        while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk);
+        // nRTS pin output is low level active
+        uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
+        // NOTE: Added in M480. After configuring RTSACTLV, re-enable TX/RX.
+        uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk;
+
+        uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
+
+        // Enable RTS
+        uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
+    }
+
+    if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC)  {
+        // Check if CTS pin matches.
+        uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
+        MBED_ASSERT(uart_cts == obj->serial.uart);
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+
+        // NOTE: Added in M480. Before configuring CTSACTLV, disable TX/RX.
+        uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk;
+        while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk);
+        // nCTS pin input is low level active
+        uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+        // NOTE: Added in M480. After configuring CTSACTLV, re-enable TX/RX.
+        uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk;
+
+        // Enable CTS
+        uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
+    }
+}
+
+#endif  //DEVICE_SERIAL_FC
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    obj->serial.irq_handler = (uint32_t) handler;
+    obj->serial.irq_id = id;
+
+    // Restore sync-mode vector
+    obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    obj->serial.irq_en = enable;
+    serial_enable_interrupt(obj, irq, enable);
+}
+
+int serial_getc(serial_t *obj)
+{
+    // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
+    while (! serial_readable(obj));
+    int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+    // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
+    //       Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
+    if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+    }
+
+    return c;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
+    while (! serial_writable(obj));
+    UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
+
+    // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
+    //       Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
+    if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+    }
+}
+
+int serial_readable(serial_t *obj)
+{
+    return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+int serial_writable(serial_t *obj)
+{
+    return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
+}
+
+static void uart0_vec(void)
+{
+    uart_irq(uart0_var.obj);
+}
+
+static void uart1_vec(void)
+{
+    uart_irq(uart1_var.obj);
+}
+
+static void uart2_vec(void)
+{
+    uart_irq(uart2_var.obj);
+}
+
+static void uart3_vec(void)
+{
+    uart_irq(uart3_var.obj);
+}
+
+static void uart4_vec(void)
+{
+    uart_irq(uart4_var.obj);
+}
+
+static void uart5_vec(void)
+{
+    uart_irq(uart5_var.obj);
+}
+
+static void uart_irq(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+        UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+        if (obj->serial.irq_handler) {
+            ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
+        }
+    }
+
+    if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+        UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
+        if (obj->serial.irq_handler) {
+            ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
+        }
+    }
+
+    // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
+    uart_base->INTSTS = uart_base->INTSTS;
+    uart_base->FIFOSTS = uart_base->FIFOSTS;
+}
+
+
+#if DEVICE_SERIAL_ASYNCH
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
+
+    obj->serial.dma_usage_tx = hint;
+    serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
+
+    // UART IRQ is necessary for both interrupt way and DMA way
+    serial_tx_enable_event(obj, event, 1);
+    serial_tx_buffer_set(obj, tx, tx_length, tx_width);
+
+    int n_word = 0;
+    if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+        // Interrupt way
+        n_word = serial_write_async(obj);
+        serial_tx_enable_interrupt(obj, handler, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+        PDMA_T *pdma_base = dma_modbase();
+
+        pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
+                             ((struct nu_uart_var *) modinit->var)->pdma_perp_tx,    // Peripheral connected to this PDMA
+                             0,  // Scatter-gather disabled
+                             0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
+                            (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+                            tx_length);
+        PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
+                             (uint32_t) tx,  // NOTE:
+                             // NUC472: End of source address
+                             // M451: Start of source address
+                             // M480: Start of source address
+                             PDMA_SAR_INC,   // Source address incremental
+                             (uint32_t) NU_MODBASE(obj->serial.uart),   // Destination address
+                             PDMA_DAR_FIX);  // Destination address fixed
+        PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
+                          PDMA_REQ_SINGLE,    // Single mode
+                          0); // Burst size
+        PDMA_EnableInt(obj->serial.dma_chn_id_tx,
+                       PDMA_INT_TRANS_DONE); // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+        serial_tx_enable_interrupt(obj, handler, 1);
+        ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk;  // Start DMA transfer
+    }
+
+    return n_word;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+    MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
+
+    obj->serial.dma_usage_rx = hint;
+    serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
+    // DMA doesn't support char match, so fall back to IRQ if it is requested.
+    if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
+            (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
+            char_match != SERIAL_RESERVED_CHAR_MATCH) {
+        obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+        dma_channel_free(obj->serial.dma_chn_id_rx);
+        obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+
+    // UART IRQ is necessary for both interrupt way and DMA way
+    serial_rx_enable_event(obj, event, 1);
+    serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+    serial_rx_set_char_match(obj, char_match);
+
+    if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+        // Interrupt way
+        serial_rx_enable_interrupt(obj, handler, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+        PDMA_T *pdma_base = dma_modbase();
+
+        pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
+                             ((struct nu_uart_var *) modinit->var)->pdma_perp_rx,    // Peripheral connected to this PDMA
+                             0,  // Scatter-gather disabled
+                             0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
+                            (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+                            rx_length);
+        PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
+                             (uint32_t) NU_MODBASE(obj->serial.uart),    // Source address
+                             PDMA_SAR_FIX,   // Source address fixed
+                             (uint32_t) rx,  // NOTE:
+                             // NUC472: End of destination address
+                             // M451: Start of destination address
+                             // M480: Start of destination address
+                             PDMA_DAR_INC);  // Destination address incremental
+        PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
+                          PDMA_REQ_SINGLE,    // Single mode
+                          0); // Burst size
+        PDMA_EnableInt(obj->serial.dma_chn_id_rx,
+                       PDMA_INT_TRANS_DONE); // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+        serial_rx_enable_interrupt(obj, handler, 1);
+        ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk;  // Start DMA transfer
+    }
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+    if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
+        PDMA_T *pdma_base = dma_modbase();
+
+        if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
+            // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
+        }
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
+    }
+
+    // Necessary for both interrupt way and DMA way
+    serial_enable_interrupt(obj, TxIrq, 0);
+    serial_rollback_interrupt(obj, TxIrq);
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
+        PDMA_T *pdma_base = dma_modbase();
+
+        if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
+            // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
+        }
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
+    }
+
+    // Necessary for both interrupt way and DMA way
+    serial_enable_interrupt(obj, RxIrq, 0);
+    serial_rollback_interrupt(obj, RxIrq);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+    // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+    return (obj->serial.vec == var->vec_async);
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+    // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+    return (obj->serial.vec == var->vec_async);
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    int event_rx = 0;
+    int event_tx = 0;
+
+    // Necessary for both interrupt way and DMA way
+    if (serial_is_irq_en(obj, RxIrq)) {
+        event_rx = serial_rx_event_check(obj);
+        if (event_rx) {
+            serial_rx_abort_asynch(obj);
+        }
+    }
+
+    if (serial_is_irq_en(obj, TxIrq)) {
+        event_tx = serial_tx_event_check(obj);
+        if (event_tx) {
+            serial_tx_abort_asynch(obj);
+        }
+    }
+
+    return (obj->serial.event & (event_rx | event_tx));
+}
+
+int serial_allow_powerdown(void)
+{
+    uint32_t modinit_mask = uart_modinit_mask;
+    while (modinit_mask) {
+        int uart_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
+        if (modinit->modname != NC) {
+            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+            // Disallow entering power-down mode if Tx FIFO has data to flush
+            if (! UART_IS_TX_EMPTY((uart_base))) {
+                return 0;
+            }
+            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
+            if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+                return 0;
+            }
+            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
+            if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << uart_idx);
+    }
+
+    return 1;
+}
+
+static void uart0_vec_async(void)
+{
+    uart_irq_async(uart0_var.obj);
+}
+
+static void uart1_vec_async(void)
+{
+    uart_irq_async(uart1_var.obj);
+}
+
+static void uart2_vec_async(void)
+{
+    uart_irq_async(uart2_var.obj);
+}
+
+static void uart3_vec_async(void)
+{
+    uart_irq_async(uart3_var.obj);
+}
+
+static void uart4_vec_async(void)
+{
+    uart_irq_async(uart4_var.obj);
+}
+
+static void uart5_vec_async(void)
+{
+    uart_irq_async(uart5_var.obj);
+}
+
+static void uart_irq_async(serial_t *obj)
+{
+    if (serial_is_irq_en(obj, RxIrq)) {
+        (*obj->serial.irq_handler_rx_async)();
+    }
+    if (serial_is_irq_en(obj, TxIrq)) {
+        (*obj->serial.irq_handler_tx_async)();
+    }
+}
+
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
+{
+    obj->char_match = char_match;
+    obj->char_found = 0;
+}
+
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+    obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
+    obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
+
+    if (event & SERIAL_EVENT_TX_COMPLETE) {
+        // N/A
+    }
+}
+
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+    obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
+    obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
+
+    if (event & SERIAL_EVENT_RX_COMPLETE) {
+        // N/A
+    }
+    if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+        // N/A
+    }
+    if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
+    }
+    if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
+    }
+    if (event & SERIAL_EVENT_RX_OVERFLOW) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
+    }
+    if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+        // N/A
+    }
+}
+
+static int serial_is_tx_complete(serial_t *obj)
+{
+    // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
+    return (obj->tx_buff.pos == obj->tx_buff.length);
+}
+
+static int serial_is_rx_complete(serial_t *obj)
+{
+    return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static uint32_t serial_tx_event_check(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+        UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
+    }
+
+    uint32_t event = 0;
+
+    if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+        serial_write_async(obj);
+    }
+
+    if (serial_is_tx_complete(obj)) {
+        event |= SERIAL_EVENT_TX_COMPLETE;
+    }
+
+    return event;
+}
+
+static uint32_t serial_rx_event_check(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+        UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+    }
+
+    uint32_t event = 0;
+
+    if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
+    }
+    if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
+        event |= SERIAL_EVENT_RX_FRAMING_ERROR;
+    }
+    if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
+        event |= SERIAL_EVENT_RX_PARITY_ERROR;
+    }
+
+    if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
+        event |= SERIAL_EVENT_RX_OVERFLOW;
+    }
+
+    if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+        serial_read_async(obj);
+    }
+
+    if (serial_is_rx_complete(obj)) {
+        event |= SERIAL_EVENT_RX_COMPLETE;
+    }
+    if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
+        event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+    }
+
+    return event;
+}
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+    serial_t *obj = (serial_t *) id;
+
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect UART IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->tx_buff.pos = obj->tx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+
+    uart_irq_async(obj);
+}
+
+static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+    serial_t *obj = (serial_t *) id;
+
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect UART IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->rx_buff.pos = obj->rx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+
+    uart_irq_async(obj);
+}
+
+static int serial_write_async(serial_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
+    uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
+    if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
+        tx_fifo_busy = tx_fifo_max;
+    }
+    uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
+    if (tx_fifo_free == 0) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+        }
+        return 0;
+    }
+
+    uint32_t bytes_per_word = obj->tx_buff.width / 8;
+
+    uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+    int n_words = 0;
+    while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
+        switch (bytes_per_word) {
+        case 4:
+            UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+            UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+        case 2:
+            UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+        case 1:
+            UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+        }
+
+        n_words ++;
+        tx_fifo_free -= bytes_per_word;
+        obj->tx_buff.pos ++;
+    }
+
+    if (n_words) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+        }
+    }
+
+    return n_words;
+}
+
+static int serial_read_async(serial_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
+
+    uint32_t bytes_per_word = obj->rx_buff.width / 8;
+
+    uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+    int n_words = 0;
+    while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
+        switch (bytes_per_word) {
+        case 4:
+            *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+            *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+        case 2:
+            *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+        case 1:
+            *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+        }
+
+        n_words ++;
+        rx_fifo_busy -= bytes_per_word;
+        obj->rx_buff.pos ++;
+
+        if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
+                obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
+            uint8_t *rx_cmp = rx;
+            switch (bytes_per_word) {
+            case 4:
+                rx_cmp -= 2;
+            case 2:
+                rx_cmp --;
+            case 1:
+                rx_cmp --;
+            }
+            if (*rx_cmp == obj->char_match) {
+                obj->char_found = 1;
+                break;
+            }
+        }
+    }
+
+    if (n_words) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+        }
+    }
+
+    return n_words;
+}
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = width;
+}
+
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
+{
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = width;
+}
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    // Necessary for both interrupt way and DMA way
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+    // With our own async vector, tx/rx handlers can be different.
+    obj->serial.vec = var->vec_async;
+    obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
+    serial_enable_interrupt(obj, TxIrq, enable);
+}
+
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    // Necessary for both interrupt way and DMA way
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+    // With our own async vector, tx/rx handlers can be different.
+    obj->serial.vec = var->vec_async;
+    obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
+    serial_enable_interrupt(obj, RxIrq, enable);
+}
+
+static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    if (enable) {
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+        NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
+        NVIC_EnableIRQ(modinit->irq_n);
+
+        struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+        // Multiple serial S/W objects for single UART H/W module possibly.
+        // Bind serial S/W object to UART H/W module as interrupt is enabled.
+        var->obj = obj;
+
+        switch (irq) {
+        // NOTE: Setting inten_msk first to avoid race condition
+        case RxIrq:
+            obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+            break;
+        case TxIrq:
+            obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+            break;
+        }
+    } else { // disable
+        switch (irq) {
+        case RxIrq:
+            UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+            obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+            break;
+        case TxIrq:
+            UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+            obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
+            break;
+        }
+    }
+}
+
+static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+    struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+
+    obj->serial.vec = var->vec;
+    serial_enable_interrupt(obj, irq, obj->serial.irq_en);
+}
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
+{
+    if (*dma_usage != DMA_USAGE_NEVER) {
+        if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
+        }
+        if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_usage = DMA_USAGE_NEVER;
+        }
+    } else {
+        dma_channel_free(*dma_ch);
+        *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+}
+
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
+{
+    int inten_msk = 0;
+
+    switch (irq) {
+    case RxIrq:
+        inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+        break;
+    case TxIrq:
+        inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
+        break;
+    }
+
+    return !! inten_msk;
+}
+
+#endif  // #if DEVICE_SERIAL_ASYNCH
+#endif  // #if DEVICE_SERIAL

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sleep_api.h"
+#include "serial_api.h"
+#include "lp_ticker_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+#include "device.h"
+#include "objects.h"
+#include "PeripheralPins.h"
+
+static void mbed_enter_sleep(struct sleep_s *obj);
+static void mbed_exit_sleep(struct sleep_s *obj);
+
+int serial_allow_powerdown(void);
+int spi_allow_powerdown(void);
+int i2c_allow_powerdown(void);
+int pwmout_allow_powerdown(void);
+
+/**
+ * Enter Idle mode.
+ */
+void hal_sleep(void)
+{
+    struct sleep_s sleep_obj;
+    sleep_obj.powerdown = 0;
+    mbed_enter_sleep(&sleep_obj);
+    mbed_exit_sleep(&sleep_obj);
+}
+
+/**
+ * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ */
+void hal_deepsleep(void)
+{
+    struct sleep_s sleep_obj;
+    sleep_obj.powerdown = 1;
+    mbed_enter_sleep(&sleep_obj);
+    mbed_exit_sleep(&sleep_obj);
+}
+
+static void mbed_enter_sleep(struct sleep_s *obj)
+{
+    // Check if serial allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = serial_allow_powerdown();
+    }
+    // Check if spi allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = spi_allow_powerdown();
+    }
+    // Check if i2c allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = i2c_allow_powerdown();
+    }
+    // Check if pwmout allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = pwmout_allow_powerdown();
+    }
+    // TODO: Check if other peripherals allow entering power-down mode
+
+    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
+        SYS_UnlockReg();
+        CLK_PowerDown();
+        SYS_LockReg();
+    } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
+        SYS_UnlockReg();
+        CLK_Idle();
+        SYS_LockReg();
+    }
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+}
+
+static void mbed_exit_sleep(struct sleep_s *obj)
+{
+    (void)obj;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,793 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+#define NU_SPI_FRAME_MIN    8
+#define NU_SPI_FRAME_MAX    32
+
+struct nu_spi_var {
+#if DEVICE_SPI_ASYNCH
+    uint8_t     pdma_perp_tx;
+    uint8_t     pdma_perp_rx;
+#endif
+};
+
+static struct nu_spi_var spi0_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI0_TX,
+    .pdma_perp_rx       =   PDMA_SPI0_RX
+#endif
+};
+static struct nu_spi_var spi1_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI1_TX,
+    .pdma_perp_rx       =   PDMA_SPI1_RX
+#endif
+};
+static struct nu_spi_var spi2_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI2_TX,
+    .pdma_perp_rx       =   PDMA_SPI2_RX
+#endif
+};
+static struct nu_spi_var spi3_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI3_TX,
+    .pdma_perp_rx       =   PDMA_SPI3_RX
+#endif
+};
+static struct nu_spi_var spi4_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI4_TX,
+    .pdma_perp_rx       =   PDMA_SPI4_RX
+#endif
+};
+
+#if DEVICE_SPI_ASYNCH
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
+static uint32_t spi_master_read_asynch(spi_t *obj);
+static uint32_t spi_event_check(spi_t *obj);
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
+static uint8_t spi_get_data_width(spi_t *obj);
+static int spi_is_tx_complete(spi_t *obj);
+static int spi_is_rx_complete(spi_t *obj);
+static int spi_writeable(spi_t * obj);
+static int spi_readable(spi_t * obj);
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
+static uint32_t spi_fifo_depth(spi_t *obj);
+#endif
+
+static uint32_t spi_modinit_mask = 0;
+
+static const struct nu_modinit_s spi_modinit_tab[] = {
+    {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
+    {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK1, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
+    {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK0, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
+    {SPI_3, SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK1, MODULE_NoMsk, SPI3_RST, SPI3_IRQn, &spi3_var},
+    {SPI_4, SPI4_MODULE, CLK_CLKSEL2_SPI4SEL_PCLK0, MODULE_NoMsk, SPI4_RST, SPI4_IRQn, &spi4_var},
+
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // Determine which SPI_x the pins are used for
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->spi.spi != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+
+    // Select IP clock source
+    CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    pinmap_pinout(ssel, PinMap_SPI_SSEL);
+
+    obj->spi.pin_mosi = mosi;
+    obj->spi.pin_miso = miso;
+    obj->spi.pin_sclk = sclk;
+    obj->spi.pin_ssel = ssel;
+
+
+#if DEVICE_SPI_ASYNCH
+    obj->spi.dma_usage = DMA_USAGE_NEVER;
+    obj->spi.event = 0;
+    obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+    // Mark this module to be inited.
+    int i = modinit - spi_modinit_tab;
+    spi_modinit_mask |= 1 << i;
+}
+
+void spi_free(spi_t *obj)
+{
+#if DEVICE_SPI_ASYNCH
+    if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->spi.dma_chn_id_tx);
+        obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+    if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->spi.dma_chn_id_rx);
+        obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+#endif
+
+    SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+    SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK));
+    NVIC_DisableIRQ(modinit->irq_n);
+
+    // Disable IP clock
+    CLK_DisableModuleClock(modinit->clkidx);
+
+    // Mark this module to be deinited.
+    int i = modinit - spi_modinit_tab;
+    spi_modinit_mask &= ~(1 << i);
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
+
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    // NOTE 1: All configurations should be ready before enabling SPI peripheral.
+    // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+
+    SPI_Open(spi_base,
+             slave ? SPI_SLAVE : SPI_MASTER,
+             (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
+             bits,
+             SPI_GetBusClock(spi_base));
+    // NOTE: Hardcode to be MSB first.
+    SPI_SET_MSB_FIRST(spi_base);
+
+    if (! slave) {
+        // Master
+        if (obj->spi.pin_ssel != NC) {
+            // Configure SS as low active.
+            SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
+        } else {
+            SPI_DisableAutoSS(spi_base);
+        }
+    } else {
+        // Slave
+        // Configure SS as low active.
+        spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
+    }
+
+    // NOTE: M451's/M480's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). This will violate judgement of spi_active(). Disable it.
+    SPI_DISABLE(spi_base);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+
+    SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
+}
+
+
+int spi_master_write(spi_t *obj, int value)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    // NOTE: Data in receive FIFO can be read out via ICE.
+    SPI_ENABLE(spi_base);
+
+    // Wait for tx buffer empty
+    while(! spi_writeable(obj));
+    SPI_WRITE_TX(spi_base, value);
+
+    // Wait for rx buffer full
+    while (! spi_readable(obj));
+    int value2 = SPI_READ_RX(spi_base);
+
+    SPI_DISABLE(spi_base);
+
+    return value2;
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
+    int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+    for (int i = 0; i < total; i++) {
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+        char in = spi_master_write(obj, out);
+        if (i < rx_length) {
+            rx_buffer[i] = in;
+        }
+    }
+
+    return total;
+}
+
+#if DEVICE_SPISLAVE
+int spi_slave_receive(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    SPI_ENABLE(spi_base);
+
+    return spi_readable(obj);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    SPI_ENABLE(spi_base);
+
+    // Wait for rx buffer full
+    while (! spi_readable(obj));
+    int value = SPI_READ_RX(spi_base);
+    return value;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    SPI_ENABLE(spi_base);
+
+    // Wait for tx buffer empty
+    while(! spi_writeable(obj));
+    SPI_WRITE_TX(spi_base, value);
+}
+#endif
+
+#if DEVICE_SPI_ASYNCH
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    SPI_SET_DATA_WIDTH(spi_base, bit_width);
+
+    obj->spi.dma_usage = hint;
+    spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
+    uint32_t data_width = spi_get_data_width(obj);
+    // Conditions to go DMA way:
+    // (1) No DMA support for non-8 multiple data width.
+    // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
+    if ((data_width % 8) ||
+            (tx_length < rx_length)) {
+        obj->spi.dma_usage = DMA_USAGE_NEVER;
+        dma_channel_free(obj->spi.dma_chn_id_tx);
+        obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+        dma_channel_free(obj->spi.dma_chn_id_rx);
+        obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+
+    // SPI IRQ is necessary for both interrupt way and DMA way
+    spi_enable_event(obj, event, 1);
+    spi_buffer_set(obj, tx, tx_length, rx, rx_length);
+
+    SPI_ENABLE(spi_base);
+
+    if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+        // Interrupt way
+        spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2);
+        spi_enable_vector_interrupt(obj, handler, 1);
+        spi_master_enable_interrupt(obj, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+        PDMA_T *pdma_base = dma_modbase();
+
+        // Configure tx DMA
+        pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
+                             ((struct nu_spi_var *) modinit->var)->pdma_perp_tx,    // Peripheral connected to this PDMA
+                             0,  // Scatter-gather disabled
+                             0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
+                            (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+                            tx_length);
+        PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
+                             (uint32_t) tx,  // NOTE:
+                             // NUC472: End of source address
+                             // M451/M480: Start of source address
+                             PDMA_SAR_INC,   // Source address incremental
+                             (uint32_t) &spi_base->TX,   // Destination address
+                             PDMA_DAR_FIX);  // Destination address fixed
+        PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
+                          PDMA_REQ_SINGLE,    // Single mode
+                          0); // Burst size
+        PDMA_EnableInt(obj->spi.dma_chn_id_tx,
+                       PDMA_INT_TRANS_DONE);   // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+
+        // Configure rx DMA
+        pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
+                             ((struct nu_spi_var *) modinit->var)->pdma_perp_rx,    // Peripheral connected to this PDMA
+                             0,  // Scatter-gather disabled
+                             0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
+                            (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+                            rx_length);
+        PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
+                             (uint32_t) &spi_base->RX,   // Source address
+                             PDMA_SAR_FIX,   // Source address fixed
+                             (uint32_t) rx,  // NOTE:
+                             // NUC472: End of destination address
+                             // M451/M480: Start of destination address
+                             PDMA_DAR_INC);  // Destination address incremental
+        PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
+                          PDMA_REQ_SINGLE,    // Single mode
+                          0); // Burst size
+        PDMA_EnableInt(obj->spi.dma_chn_id_rx,
+                       PDMA_INT_TRANS_DONE);   // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+
+        // Start tx/rx DMA transfer
+        spi_enable_vector_interrupt(obj, handler, 1);
+        // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
+        SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+        SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+        spi_master_enable_interrupt(obj, 1);
+    }
+}
+
+/**
+ * Abort an SPI transfer
+ * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
+ * transfers
+ * @param[in] obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    PDMA_T *pdma_base = dma_modbase();
+
+    if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
+        // Receive FIFO Overrun in case of tx length > rx length on DMA way
+        if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
+            spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
+        }
+
+        if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
+            // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
+        }
+        SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+
+        if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
+            // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
+        }
+        SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+    }
+
+    // Necessary for both interrupt way and DMA way
+    spi_enable_vector_interrupt(obj, 0, 0);
+    spi_master_enable_interrupt(obj, 0);
+
+    // NOTE: SPI H/W may get out of state without the busy check.
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+
+    SPI_ClearRxFIFO(spi_base);
+    SPI_ClearTxFIFO(spi_base);
+}
+
+/**
+ * Handle the SPI interrupt
+ * Read frames until the RX FIFO is empty.  Write at most as many frames as were read.  This way,
+ * it is unlikely that the RX FIFO will overflow.
+ * @param[in] obj The SPI peripheral that generated the interrupt
+ * @return
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    // Check for SPI events
+    uint32_t event = spi_event_check(obj);
+    if (event) {
+        spi_abort_asynch(obj);
+    }
+
+    return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
+}
+
+int spi_allow_powerdown(void)
+{
+    uint32_t modinit_mask = spi_modinit_mask;
+    while (modinit_mask) {
+        int spi_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
+        if (modinit->modname != NC) {
+            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
+            // Disallow entering power-down mode if SPI transfer is enabled.
+            if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << spi_idx);
+    }
+
+    return 1;
+}
+
+static int spi_writeable(spi_t * obj)
+{
+    // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
+    return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
+}
+
+static int spi_readable(spi_t * obj)
+{
+    return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+}
+
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
+{
+    obj->spi.event &= ~SPI_EVENT_ALL;
+    obj->spi.event |= (event & SPI_EVENT_ALL);
+    if (event & SPI_EVENT_RX_OVERFLOW) {
+        SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK);
+    }
+}
+
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+    if (enable) {
+        NVIC_SetVector(modinit->irq_n, handler);
+        NVIC_EnableIRQ(modinit->irq_n);
+    } else {
+        NVIC_DisableIRQ(modinit->irq_n);
+    }
+}
+
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    if (enable) {
+        uint32_t fifo_depth = spi_fifo_depth(obj);
+        SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2);
+        // Enable tx/rx FIFO threshold interrupt
+        SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
+    } else {
+        SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
+    }
+}
+
+static uint32_t spi_event_check(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    uint32_t event = 0;
+
+    if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+        uint32_t n_rec = spi_master_read_asynch(obj);
+        spi_master_write_asynch(obj, n_rec);
+    }
+
+    if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
+        event |= SPI_EVENT_COMPLETE;
+    }
+
+    // Receive FIFO Overrun
+    if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
+        // In case of tx length > rx length on DMA way
+        if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+            event |= SPI_EVENT_RX_OVERFLOW;
+        }
+    }
+
+    // Receive Time-Out
+    if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
+        // Not using this IF. Just clear it.
+    }
+    // Transmit FIFO Under-Run
+    if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
+        event |= SPI_EVENT_ERROR;
+    }
+
+    return event;
+}
+
+/**
+ * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
+ * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
+ * @param[in] obj       The SPI object on which to operate
+ * @param[in] tx_limit  The maximum number of words to send
+ * @return The number of SPI words that have been transfered
+ */
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
+{
+    uint32_t n_words = 0;
+    uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+    uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+    uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
+    max_tx = NU_MIN(max_tx, tx_limit);
+    uint8_t data_width = spi_get_data_width(obj);
+    uint8_t bytes_per_word = (data_width + 7) / 8;
+    uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    while ((n_words < max_tx) && spi_writeable(obj)) {
+        if (spi_is_tx_complete(obj)) {
+            // Transmit dummy as transmit buffer is empty
+            SPI_WRITE_TX(spi_base, 0);
+        } else {
+            switch (bytes_per_word) {
+            case 4:
+                SPI_WRITE_TX(spi_base, nu_get32_le(tx));
+                tx += 4;
+                break;
+            case 2:
+                SPI_WRITE_TX(spi_base, nu_get16_le(tx));
+                tx += 2;
+                break;
+            case 1:
+                SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
+                tx += 1;
+                break;
+            }
+
+            obj->tx_buff.pos ++;
+        }
+        n_words ++;
+    }
+
+    //Return the number of words that have been sent
+    return n_words;
+}
+
+/**
+ * Read SPI words out of the RX FIFO
+ * Continues reading words out of the RX FIFO until the following condition is met:
+ * o There are no more words in the FIFO
+ * OR BOTH OF:
+ * o At least as many words as the TX buffer have been received
+ * o At least as many words as the RX buffer have been received
+ * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
+ * @param[in] obj The SPI object on which to operate
+ * @return Returns the number of words extracted from the RX FIFO
+ */
+static uint32_t spi_master_read_asynch(spi_t *obj)
+{
+    uint32_t n_words = 0;
+    uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+    uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+    uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
+    uint8_t data_width = spi_get_data_width(obj);
+    uint8_t bytes_per_word = (data_width + 7) / 8;
+    uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    while ((n_words < max_rx) && spi_readable(obj)) {
+        if (spi_is_rx_complete(obj)) {
+            // Disregard as receive buffer is full
+            SPI_READ_RX(spi_base);
+        } else {
+            switch (bytes_per_word) {
+            case 4: {
+                uint32_t val = SPI_READ_RX(spi_base);
+                nu_set32_le(rx, val);
+                rx += 4;
+                break;
+            }
+            case 2: {
+                uint16_t val = SPI_READ_RX(spi_base);
+                nu_set16_le(rx, val);
+                rx += 2;
+                break;
+            }
+            case 1:
+                *rx ++ = SPI_READ_RX(spi_base);
+                break;
+            }
+
+            obj->rx_buff.pos ++;
+        }
+        n_words ++;
+    }
+
+    // Return the number of words received
+    return n_words;
+}
+
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = spi_get_data_width(obj);
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = spi_get_data_width(obj);
+}
+
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
+{
+    if (*dma_usage != DMA_USAGE_NEVER) {
+        if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
+        }
+        if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
+        }
+
+        if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_usage = DMA_USAGE_NEVER;
+        }
+    }
+
+    if (*dma_usage == DMA_USAGE_NEVER) {
+        dma_channel_free(*dma_ch_tx);
+        *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
+        dma_channel_free(*dma_ch_rx);
+        *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+}
+
+static uint8_t spi_get_data_width(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
+    if (data_width == 0) {
+        data_width = 32;
+    }
+
+    return data_width;
+}
+
+static int spi_is_tx_complete(spi_t *obj)
+{
+    return (obj->tx_buff.pos == obj->tx_buff.length);
+}
+
+static int spi_is_rx_complete(spi_t *obj)
+{
+    return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+    spi_t *obj = (spi_t *) id;
+
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect SPI IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->tx_buff.pos = obj->tx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+    void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+    vec();
+}
+
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+    spi_t *obj = (spi_t *) id;
+
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect SPI IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->rx_buff.pos = obj->rx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == (int) obj->spi.spi);
+
+    void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+    vec();
+}
+
+/** Return FIFO depth of the SPI peripheral
+ *
+ * @details
+ *  M487
+ *      SPI0            8
+ *      SPI1/2/3/4      8 if data width <=16; 4 otherwise
+ */
+static uint32_t spi_fifo_depth(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+    if (spi_base == SPI0) {
+        return 8;
+    }
+
+    return (spi_get_data_width(obj) <= 16) ? 8 : 4;
+}
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if DEVICE_TRNG
+
+#include <stdlib.h>
+#include <string.h>
+#include "cmsis.h"
+#include "us_ticker_api.h"
+#include "trng_api.h"
+
+/*
+ * Get Random number generator.
+ */
+static volatile int  g_PRNG_done;
+volatile int  g_AES_done;
+
+void CRYPTO_IRQHandler()
+{
+    if (PRNG_GET_INT_FLAG()) {
+        g_PRNG_done = 1;
+        PRNG_CLR_INT_FLAG();
+    } else	if (AES_GET_INT_FLAG()) {
+        g_AES_done = 1;
+        AES_CLR_INT_FLAG();
+    }
+}
+
+static void trng_get(unsigned char *pConversionData)
+{
+    uint32_t *p32ConversionData;
+
+    p32ConversionData = (uint32_t *)pConversionData;
+
+    PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read());
+    PRNG_Start();
+    while (!g_PRNG_done);
+
+    PRNG_Read(p32ConversionData);
+}
+
+void trng_init(trng_t *obj)
+{
+    (void)obj;
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+    /* Enable IP clock */
+    CLK_EnableModuleClock(CRPT_MODULE);
+
+    /* Lock protected registers */
+    SYS_LockReg();
+
+    NVIC_EnableIRQ(CRPT_IRQn);
+    PRNG_ENABLE_INT();
+}
+
+void trng_free(trng_t *obj)
+{
+    (void)obj;
+    PRNG_DISABLE_INT();
+    NVIC_DisableIRQ(CRPT_IRQn);
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    (void)obj;
+
+    *output_length = 0;
+    if (length < 32) {
+        unsigned char tmpBuff[32];
+        trng_get(tmpBuff);
+        memcpy(output, &tmpBuff, length);
+        *output_length = length;
+    } else {
+        for (unsigned i = 0; i < (length/32); i++) {
+            trng_get(output);
+            *output_length += 32;
+            output += 32;
+        }
+    }
+
+    return 0;
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,214 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "us_ticker_api.h"
+#include "sleep_api.h"
+#include "mbed_assert.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "mbed_critical.h"
+
+// us_ticker tick = us = timestamp
+#define US_PER_TICK             1
+#define US_PER_SEC              (1000 * 1000)
+
+#define TMR0HIRES_CLK_PER_SEC           (1000 * 1000)
+#define TMR1HIRES_CLK_PER_SEC           (1000 * 1000)
+
+#define US_PER_TMR0HIRES_CLK            (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
+#define US_PER_TMR1HIRES_CLK            (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
+
+#define US_PER_TMR0HIRES_INT            (1000 * 1000 * 10)
+#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
+
+
+static void tmr0_vec(void);
+static void tmr1_vec(void);
+static void us_ticker_arm_cd(void);
+
+static int us_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile uint32_t cd_major_minor_us = 0;
+static volatile uint32_t cd_minor_us = 0;
+
+// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
+// NOTE: Choose clock source of timer:
+//       1. HIRC: Be the most accurate but might cause unknown HardFault.
+//       2. HXT: Less accurate and cannot pass mbed-drivers test.
+//       3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
+// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
+static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
+static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+
+#define TMR_CMP_MIN         2
+#define TMR_CMP_MAX         0xFFFFFFu
+
+void us_ticker_init(void)
+{
+    if (us_ticker_inited) {
+        return;
+    }
+
+    counter_major = 0;
+    cd_major_minor_us = 0;
+    cd_minor_us = 0;
+    us_ticker_inited = 1;
+
+    // Reset IP
+    SYS_ResetModule(timer0hires_modinit.rsetidx);
+    SYS_ResetModule(timer1hires_modinit.rsetidx);
+
+    // Select IP clock source
+    CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
+    CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(timer0hires_modinit.clkidx);
+    CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+
+    // Timer for normal counter
+    uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
+    MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
+    MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
+    MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
+    ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
+    ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
+
+    NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
+    NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
+
+    NVIC_EnableIRQ(timer0hires_modinit.irq_n);
+    NVIC_EnableIRQ(timer1hires_modinit.irq_n);
+
+    TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+}
+
+uint32_t us_ticker_read()
+{
+    if (! us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
+
+    do {
+        uint32_t major_minor_us;
+        uint32_t minor_us;
+
+        // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
+        // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
+        do {
+            core_util_critical_section_enter();
+
+            // NOTE: Order of reading minor_us/carry here is significant.
+            minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
+            uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
+            // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
+            if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
+                major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
+            } else {
+                major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
+            }
+
+            core_util_critical_section_exit();
+        } while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
+
+        return (major_minor_us / US_PER_TICK);
+    } while (0);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+
+    int delta = (int) (timestamp - us_ticker_read());
+    if (delta > 0) {
+        cd_major_minor_us = delta * US_PER_TICK;
+        us_ticker_arm_cd();
+    } else {
+        // NOTE: With us_ticker_fire_interrupt() introduced, upper layer would handle past event case.
+        //       This code fragment gets redundant, but it is still kept here for backward-compatible.
+        void us_ticker_fire_interrupt(void);
+        us_ticker_fire_interrupt();
+    }
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+    //       This prevents a recursive loop under heavy load which can lead to a stack overflow.
+    cd_major_minor_us = cd_minor_us = 0;
+    NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+}
+
+static void tmr0_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    counter_major ++;
+}
+
+static void tmr1_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+    cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
+    if (cd_major_minor_us == 0) {
+        // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+        us_ticker_irq_handler();
+    } else {
+        us_ticker_arm_cd();
+    }
+}
+
+static void us_ticker_arm_cd(void)
+{
+    TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
+
+    cd_minor_us = cd_major_minor_us;
+
+    // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
+    // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
+    // M480
+    timer1_base->CNT = 0;
+    while (timer1_base->CNT & TIMER_CNT_RSTACT_Msk);
+    // One-shot mode, Clock = 1 MHz
+    uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+    uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
+    MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
+    MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
+    timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
+    timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
+
+    uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
+    cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer1_base->CMP = cmp_timer1;
+
+    TIMER_EnableInt(timer1_base);
+    TIMER_Start(timer1_base);
+}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -118,7 +118,7 @@
     LED1 = PD_9,
     LED2 = PA_4,
     LED3 = PD_8,
-    LED4 = D0,  // No real LED. Just for passing ATS.
+    LED4 = LED1,    // No real LED. Just for passing ATS.
     LED_RED = LED1,
     LED_GREEN = LED2,
     LED_BLUE = LED3,

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c	Thu Aug 31 17:27:04 2017 +0100
@@ -17,13 +17,6 @@
 #include "cmsis.h"
 #include "analogin_api.h"
 
-// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
-#if defined(__CC_ARM) || defined(__GNUC__)
-void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
-#elif defined(__ICCARM__)
-    // FIXME: How to achieve it in IAR?
-#endif
-
 void mbed_sdk_init(void)
 {
     // NOTE: Support singleton semantics to be called from other init functions
@@ -88,8 +81,3 @@
     /* Lock protected registers */
     SYS_LockReg();
 }
-
-void mbed_sdk_init_forced(void)
-{
-    mbed_sdk_init();
-}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,595 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
- *
- *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
- *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_AES_C)
-#if defined(MBEDTLS_AES_ALT)
-
-#include <string.h>
-
-#include "mbedtls/aes.h"
-
-#include "NUC472_442.h"
-#include "mbed_toolchain.h"
-#include "mbed_assert.h"
-
-//static int aes_init_done = 0;
-
-
-#define mbedtls_trace(...) //printf(__VA_ARGS__)
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-
-static uint32_t au32MyAESIV[4] = {
-    0x00000000, 0x00000000, 0x00000000, 0x00000000
-};
-
-extern volatile int  g_AES_done;
-
-// Must be a multiple of 16 bytes block size 
-#define MAX_DMA_CHAIN_SIZE (16*6)
-static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
-static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
-
-static void dumpHex(const unsigned char au8Data[], int len)
-{
-		int j;									
-		for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]);									
-		mbedtls_trace("\r\n");										
-}	
-
-static void swapInitVector(unsigned char iv[16])
-{
-	  unsigned int* piv;
-	  int i;
-		// iv SWAP
-		piv = (unsigned int*)iv;
-		for( i=0; i< 4; i++)
-		{
-				*piv = (((*piv) & 0x000000FF) << 24) |
-				(((*piv) & 0x0000FF00) << 8) |
-				(((*piv) & 0x00FF0000) >> 8) |
-				(((*piv) & 0xFF000000) >> 24);
-				piv++;
-		}			
-}	
-
-//volatile void CRYPTO_IRQHandler()
-//{
-//    if (AES_GET_INT_FLAG()) {
-//        g_AES_done = 1;
-//        AES_CLR_INT_FLAG();
-//    }
-//}
-
-// AES available channel 0~3
-static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00};  // 0: idle, 1: busy
-static int channel_alloc()
-{
-	int i;
-	for(i=0; i< (int)sizeof(channel_flag); i++)
-	{
-		if( channel_flag[i] == 0x00 )
-		{
-			channel_flag[i] = 0x01;
-			return i;
-		}	
-	}
-	return(-1);
-}
-
-static void channel_free(int i)
-{
-	if( i >=0 && i < (int)sizeof(channel_flag) )
-		channel_flag[i] = 0x00;
-}
-
-
-void mbedtls_aes_init( mbedtls_aes_context *ctx )
-{
-	int i =-1;
-
-//	sw_mbedtls_aes_init(ctx); 
-//	return;
-	
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
-    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
-	
-    ctx->swapType = AES_IN_OUT_SWAP;
-		while( (i = channel_alloc()) < 0 ) 	
-		{	
-		  mbed_assert_internal("No available AES channel", __FILE__, __LINE__);
-			//osDelay(300);
-    }
-    ctx->channel = i;
-    ctx->iv = au32MyAESIV;
-	
-    /* Unlock protected registers */
-    SYS_UnlockReg();
-	  CLK_EnableModuleClock(CRPT_MODULE);
-    /* Lock protected registers */
-    SYS_LockReg();
-
-    NVIC_EnableIRQ(CRPT_IRQn);
-    AES_ENABLE_INT();    	
-	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel);
-}
-
-void mbedtls_aes_free( mbedtls_aes_context *ctx )
-{
-
-	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel);	
-
-    if( ctx == NULL )
-        return;
-
-    /* Unlock protected registers */
-//    SYS_UnlockReg();
-//    CLK_DisableModuleClock(CRPT_MODULE);
-    /* Lock protected registers */
-//    SYS_LockReg();
-
-//    NVIC_DisableIRQ(CRPT_IRQn);
-//    AES_DISABLE_INT();       	
-		channel_free(ctx->channel);
-    mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
-}
-
-/*
- * AES key schedule (encryption)
- */
-#if defined(MBEDTLS_AES_SETKEY_ENC_ALT)
-int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits )
-{
-    unsigned int i;
-	
-	mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
-	dumpHex(key,keybits/8);
-
-    switch( keybits )
-    {
-        case 128: 
-       	    ctx->keySize = AES_KEY_SIZE_128;
-            break;
-        case 192:  
-        	ctx->keySize = AES_KEY_SIZE_192;
-            break;
-        case 256:  
-            ctx->keySize = AES_KEY_SIZE_256;
-            break;
-        default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
-    }
-
-
-
-	// key swap
-		for( i = 0; i < ( keybits >> 5 ); i++ )
-		{
-						ctx->buf[i] = (*(key+i*4) << 24) |
-													(*(key+1+i*4) << 16) |
-													(*(key+2+i*4) << 8) |
-													(*(key+3+i*4) );
-		}
-    AES_SetKey(ctx->channel, ctx->buf, ctx->keySize);
-
-
-    return( 0 );
-}
-#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */
-
-/*
- * AES key schedule (decryption)
- */
-#if defined(MBEDTLS_AES_SETKEY_DEC_ALT)
-int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits )
-{
-    int ret;
-	
-	  mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
-	  dumpHex((uint8_t *)key,keybits/8);
-	
-    /* Also checks keybits */
-    if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 )
-        goto exit;    
-
-exit:
-
-    return( ret );
-}
-#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */
-
-
-static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16], int dataSize)
-{
-		unsigned char* pIn;
-	  unsigned char* pOut;
-
-//	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
-	  dumpHex(input,16);
- 
-    AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType);
-    AES_SetInitVect(ctx->channel, ctx->iv);
-		if( ((uint32_t)input) & 0x03 )
-		{
-			memcpy(au8InputData, input, dataSize);
-			pIn = au8InputData;
-		}else{
-		  pIn = (unsigned char*)input;
-    }
-		if( (((uint32_t)output) & 0x03) || (dataSize%4))   // HW CFB output byte count must be multiple of word
-		{		
-			pOut = au8OutputData;
-		} else {
-		  pOut = output;
-    }			
-
-    AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize);		
-
-    g_AES_done = 0;
-    AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT);
-    while (!g_AES_done);
-
-    if( pOut != output ) memcpy(output, au8OutputData, dataSize);
-		dumpHex(output,16);
-
-}
-
-/*
- * AES-ECB block encryption
- */
-#if defined(MBEDTLS_AES_ENCRYPT_ALT)
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] )
-{
-
-	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
-	
-	  ctx->encDec = 1;
-	  __nvt_aes_crypt(ctx, input, output, 16);
-  
-}
-#endif /* MBEDTLS_AES_ENCRYPT_ALT */
-
-/*
- * AES-ECB block decryption
- */
-#if defined(MBEDTLS_AES_DECRYPT_ALT)
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] )
-{
- 
-	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
-
-	  ctx->encDec = 0;
-	  __nvt_aes_crypt(ctx, input, output, 16);
-
-
-}
-#endif /* MBEDTLS_AES_DECRYPT_ALT */
-
-/*
- * AES-ECB block encryption/decryption
- */
-int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
-                    int mode,
-                    const unsigned char input[16],
-                    unsigned char output[16] )
-{
-	
-	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
-		
-	  ctx->opMode = AES_MODE_ECB;
-    if( mode == MBEDTLS_AES_ENCRYPT )
-        mbedtls_aes_encrypt( ctx, input, output );
-    else
-        mbedtls_aes_decrypt( ctx, input, output );
-		
-
-    return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * AES-CBC buffer encryption/decryption
- */
-int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
-                    int mode,
-                    size_t len,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output )
-{
-    unsigned char temp[16];
-    int length = len;
-	  int blockChainLen;
-		mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length);
-    if( length % 16 )
-        return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
-
-    if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) )
-		{
-			  blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  MAX_DMA_CHAIN_SIZE : length );
-    } else {
-			  blockChainLen = length;
-    }			
-		
-    while( length > 0 )
-    {
-			  ctx->opMode = AES_MODE_CBC;
-			  swapInitVector(iv); // iv SWAP
-			  ctx->iv = (uint32_t *)iv;
-
-    		if( mode == MBEDTLS_AES_ENCRYPT )
-    		{					
-	            ctx->encDec = 1;
-	            __nvt_aes_crypt(ctx, input, output, blockChainLen);
-//					    if( blockChainLen == length ) break;		// finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
-							memcpy( iv, output+blockChainLen-16, 16 );
-				}else{
-					    memcpy( temp, input+blockChainLen-16, 16 );
-		          ctx->encDec = 0;
-	            __nvt_aes_crypt(ctx, input, output, blockChainLen);
-//					    if( blockChainLen == length ) break;		// finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
-					    memcpy( iv, temp, 16 );
-         }	
-         length -= blockChainLen;
-         input  += blockChainLen;
-         output += blockChainLen;
-			   if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length;		// For last remainder block chain				
-	
-    }
-
-    return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/*
- * AES-CFB128 buffer encryption/decryption
- */
-/* Support partial block encryption/decryption */
-static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output )
-{
-    int c;
-    size_t n = *iv_off;
-		unsigned char iv_tmp[16];
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
-    if( mode == MBEDTLS_AES_DECRYPT )
-    {
-        while( length-- )
-        {
-            if( n == 0)
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-						else if( ctx->opMode == AES_MODE_CFB)		// For previous cryption is CFB mode 
-						{
-							memcpy(iv_tmp, iv, n);
-							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
-							memcpy(iv, iv_tmp, n);
-						}
-						
-            c = *input++;
-            *output++ = (unsigned char)( c ^ iv[n] );
-            iv[n] = (unsigned char) c;
-
-            n = ( n + 1 ) & 0x0F;
-        }
-    }
-    else
-    {
-        while( length-- )
-        {
-            if( n == 0 )
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-						else if( ctx->opMode == AES_MODE_CFB)	// For previous cryption is CFB mode
-						{
-							memcpy(iv_tmp, iv, n);
-							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
-							memcpy(iv, iv_tmp, n);
-						}
-						
-            iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
-
-            n = ( n + 1 ) & 0x0F;
-        }
-    }
-
-    *iv_off = n;
-
-    return( 0 );
-}
-
-int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t len,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output )
-{
-		size_t n = *iv_off;
-    unsigned char temp[16];
-   	int length=len;
-	  int blockChainLen;
-		int remLen=0;
-   	int ivLen;
-	
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
-		
-	// proceed: start with partial block by ECB mode first
-	  if( n !=0 ) {
-				__nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output);
-				input += (16 - n);
-				output += (16 - n);
-				length -= (16 - n);
-		}
-		
-		// For address or byte count non-word alignment, go through reserved DMA buffer.
-		if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) )  // Must reserved DMA buffer for each block
-		{	
-			  blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  MAX_DMA_CHAIN_SIZE : length );
-		} else if(length%4) {																						// Need reserved DMA buffer once for last chain
-				blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  (length - length%16) : length );
-    } else {																												// Not need reserved DMA buffer
-			  blockChainLen = length;
-    }						
-		
-		// proceed: start with block alignment
-		while( length > 0 )
-		{
-
-				ctx->opMode = AES_MODE_CFB;
-
-				swapInitVector(iv); // iv SWAP
-	
-				ctx->iv = (uint32_t *)iv;
-				remLen = blockChainLen%16;
-				ivLen = (( remLen > 0) ? remLen: 16 );
-	
-				if( mode == MBEDTLS_AES_DECRYPT )
-				{
-						memcpy(temp, input+blockChainLen - ivLen, ivLen);
-						if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16);
-						ctx->encDec = 0;
-						__nvt_aes_crypt(ctx, input, output, blockChainLen);
-						memcpy(iv,temp, ivLen);
-				}
-				else
-				{
-						ctx->encDec = 1;
-						__nvt_aes_crypt(ctx, input, output, blockChainLen);					
-						if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16);
-						memcpy(iv,output+blockChainLen-ivLen,ivLen);
-				}
-				length -= blockChainLen;
-        input  += blockChainLen;
-        output += blockChainLen;
-			  if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length;		// For last remainder block chain							
-		}
-		
-    *iv_off = remLen;
-
-    return( 0 );		
-}
-
-
-/*
- * AES-CFB8 buffer encryption/decryption
- */
-int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output )
-{
-    unsigned char c;
-    unsigned char ov[17];
-
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
-    while( length-- )
-    {
-        memcpy( ov, iv, 16 );
-        mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-
-        if( mode == MBEDTLS_AES_DECRYPT )
-            ov[16] = *input;
-
-        c = *output++ = (unsigned char)( iv[0] ^ *input++ );
-
-        if( mode == MBEDTLS_AES_ENCRYPT )
-            ov[16] = c;
-
-        memcpy( iv, ov + 1, 16 );
-    }
-
-    return( 0 );
-}
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/*
- * AES-CTR buffer encryption/decryption
- */
-int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
-                       size_t length,
-                       size_t *nc_off,
-                       unsigned char nonce_counter[16],
-                       unsigned char stream_block[16],
-                       const unsigned char *input,
-                       unsigned char *output )
-{
-    int c, i;
-    size_t n = *nc_off;
-
-	mbedtls_trace("=== %s \r\n", __FUNCTION__);	
-    while( length-- )
-    {
-        if( n == 0 ) {
-            mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
-
-            for( i = 16; i > 0; i-- )
-                if( ++nonce_counter[i - 1] != 0 )
-                    break;
-        }
-        c = *input++;
-        *output++ = (unsigned char)( c ^ stream_block[n] );
-
-        n = ( n + 1 ) & 0x0F;
-    }
-
-    *nc_off = n;
-
-    return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-#endif /* MBEDTLS_AES_ALT */
-
-
-#endif /* MBEDTLS_AES_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,274 +0,0 @@
-/**
- * \file aes_alt.h
- *
- * \brief AES block cipher
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#if defined(MBEDTLS_AES_ALT)
-// Regular implementation
-//
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          AES context structure
- *
- * \note           buf is able to hold 32 extra bytes, which can be used:
- *                 - for alignment purposes if VIA padlock is used, and/or
- *                 - to simplify key expansion in the 256-bit case by
- *                 generating an extra round key
- */
-typedef struct
-{
-    uint32_t keySize;
-    uint32_t encDec;
-    uint32_t opMode;
-    uint32_t channel;
-    uint32_t swapType;
-    uint32_t *iv;
-		unsigned char prv_iv[16];
-#if 1	
-    uint32_t buf[8]; 
-/* For comparsion with software AES for correctness */ 
-#else
-    uint32_t buf[68];           /*!<  unaligned data    */    
-    int nr;                     /*!<  number of rounds  */
-    uint32_t *rk;               /*!<  AES round keys    */    
-#endif    
-}
-mbedtls_aes_context;
-
-/**
- * \brief          Initialize AES context
- *
- * \param ctx      AES context to be initialized
- */
-void mbedtls_aes_init( mbedtls_aes_context *ctx );
-
-/**
- * \brief          Clear AES context
- *
- * \param ctx      AES context to be cleared
- */
-void mbedtls_aes_free( mbedtls_aes_context *ctx );
-
-/**
- * \brief          AES key schedule (encryption)
- *
- * \param ctx      AES context to be initialized
- * \param key      encryption key
- * \param keybits  must be 128, 192 or 256
- *
- * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
- */
-int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits );
-
-/**
- * \brief          AES key schedule (decryption)
- *
- * \param ctx      AES context to be initialized
- * \param key      decryption key
- * \param keybits  must be 128, 192 or 256
- *
- * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
- */
-int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits );
-
-/**
- * \brief          AES-ECB block encryption/decryption
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param input    16-byte input block
- * \param output   16-byte output block
- *
- * \return         0 if successful
- */
-int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
-                    int mode,
-                    const unsigned char input[16],
-                    unsigned char output[16] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          AES-CBC buffer encryption/decryption
- *                 Length should be a multiple of the block
- *                 size (16 bytes)
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
- */
-int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief          AES-CFB128 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length   length of the input data
- * \param iv_off   offset in IV (updated after use)
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful
- */
-int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-
-/**
- * \brief          AES-CFB8 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful
- */
-int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief               AES-CTR buffer encryption/decryption
- *
- * Warning: You have to keep the maximum use of your counter in mind!
- *
- * Note: Due to the nature of CTR you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \param ctx           AES context
- * \param length        The length of the data
- * \param nc_off        The offset in the current stream_block (for resuming
- *                      within current cipher stream). The offset pointer to
- *                      should be 0 at the start of a stream.
- * \param nonce_counter The 128-bit nonce and counter.
- * \param stream_block  The saved stream-block for resuming. Is overwritten
- *                      by the function.
- * \param input         The input data stream
- * \param output        The output data stream
- *
- * \return         0 if successful
- */
-int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
-                       size_t length,
-                       size_t *nc_off,
-                       unsigned char nonce_counter[16],
-                       unsigned char stream_block[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-/**
- * \brief           Internal AES block encryption function
- *                  (Only exposed to allow overriding it,
- *                  see MBEDTLS_AES_ENCRYPT_ALT)
- *
- * \param ctx       AES context
- * \param input     Plaintext block
- * \param output    Output (ciphertext) block
- */
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] );
-
-/**
- * \brief           Internal AES block decryption function
- *                  (Only exposed to allow overriding it,
- *                  see MBEDTLS_AES_DECRYPT_ALT)
- *
- * \param ctx       AES context
- * \param input     Ciphertext block
- * \param output    Output (plaintext) block
- */
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] );
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* MBEDTLS_AES_ALT */
-
-

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-
-#include "cmsis.h"
-#include "mbed_assert.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-#include "crypto-misc.h"
-
-static int crypto_inited = 0;
-static int crypto_sha_avail = 1;
-
-void crypto_init(void)
-{
-    if (crypto_inited) {
-        return;
-    }
-    crypto_inited = 1;
-    
-    CLK_EnableModuleClock(CRPT_MODULE);
-}
-
-/* Implementation that should never be optimized out by the compiler */
-void crypto_zeroize(void *v, size_t n)
-{
-    volatile unsigned char *p = (unsigned char*) v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-
-int crypto_sha_acquire(void)
-{
-    if (crypto_sha_avail) {
-        crypto_sha_avail = 0;
-        return 1;
-    }
-    else {
-        return 0;
-    }
-    
-}
-
-void crypto_sha_release(void)
-{
-    if (! crypto_sha_avail) {
-        crypto_sha_avail = 1;
-    }
-}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_CRYPTO_MISC_H
-#define MBED_CRYPTO_MISC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void crypto_init(void);
-void crypto_zeroize(void *v, size_t n);
-int crypto_sha_acquire(void);
-void crypto_sha_release(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,415 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include <string.h>
-#include "mbedtls/des.h"
-#include "des_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "mbed_toolchain.h"
-
-// Must be a multiple of 64-bit block size
-#define MAXSIZE_DMABUF  (8 * 5)
-static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4);
-static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4);
-
-static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, 
-    unsigned char iv[8], const unsigned char *input, unsigned char *output);
-
-void mbedtls_des_init(mbedtls_des_context *ctx)
-{
-    crypto_init();
-    memset(ctx, 0, sizeof(mbedtls_des_context));
-}
-
-void mbedtls_des_free( mbedtls_des_context *ctx )
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    crypto_zeroize(ctx, sizeof(mbedtls_des_context));
-}
-
-void mbedtls_des3_init( mbedtls_des3_context *ctx )
-{
-    crypto_init();
-    memset(ctx, 0, sizeof(mbedtls_des3_context));
-}
-
-void mbedtls_des3_free( mbedtls_des3_context *ctx )
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    crypto_zeroize(ctx, sizeof (mbedtls_des3_context));
-}
-
-static const unsigned char odd_parity_table[128] = { 1,  2,  4,  7,  8,
-        11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
-        47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
-        82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
-        115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
-        143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
-        171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
-        199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
-        227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
-        254 };
-
-void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE])
-{
-    int i;
-
-    for (i = 0; i < MBEDTLS_DES_KEY_SIZE; i++) {
-        key[i] = odd_parity_table[key[i] / 2];
-    }
-}
-
-/*
- * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
- */
-int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
-        if( key[i] != odd_parity_table[key[i] / 2] )
-            return( 1 );
-
-    return( 0 );
-}
-
-/*
- * Table of weak and semi-weak keys
- *
- * Source: http://en.wikipedia.org/wiki/Weak_key
- *
- * Weak:
- * Alternating ones + zeros (0x0101010101010101)
- * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
- * '0xE0E0E0E0F1F1F1F1'
- * '0x1F1F1F1F0E0E0E0E'
- *
- * Semi-weak:
- * 0x011F011F010E010E and 0x1F011F010E010E01
- * 0x01E001E001F101F1 and 0xE001E001F101F101
- * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
- * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
- * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
- * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
- *
- */
-
-#define WEAK_KEY_COUNT 16
-
-static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
-{
-    { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
-    { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
-    { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
-    { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
-
-    { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
-    { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
-    { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
-    { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
-    { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
-    { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
-    { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
-    { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
-    { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
-    { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
-    { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
-    { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
-};
-
-int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    for( i = 0; i < WEAK_KEY_COUNT; i++ )
-        if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
-            return( 1 );
-
-    return( 0 );
-}
-
-/*
- * DES key schedule (56-bit, encryption)
- */
-int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    ctx->enc = 1;
-    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
-    ctx->keyopt = 3;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-    
-    return 0;
-}
-
-/*
- * DES key schedule (56-bit, decryption)
- */
-int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    ctx->enc = 0;
-    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
-    ctx->keyopt = 3;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
-    return 0;
-}
-
-/*
- * Triple-DES key schedule (112-bit, encryption)
- */
-int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
-    ctx->enc = 1;
-    // Keying option 2: K1 and K2 are independent, and K3 = K1.
-    ctx->keyopt = 2;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
-    return 0;
-}
-
-/*
- * Triple-DES key schedule (112-bit, decryption)
- */
-int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
-    ctx->enc = 0;
-    // Keying option 2: K1 and K2 are independent, and K3 = K1.
-    ctx->keyopt = 2;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
-    return 0;
-}
-
-/*
- * Triple-DES key schedule (168-bit, encryption)
- */
-int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
-    ctx->enc = 1;
-    // Keying option 1: All three keys are independent.
-    ctx->keyopt = 1;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
-
-    return 0;
-}
-
-/*
- * Triple-DES key schedule (168-bit, decryption)
- */
-int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
-    ctx->enc = 0;
-    // Keying option 1: All three keys are independent.
-    ctx->keyopt = 1;
-    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
-    memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
-
-    return 0;
-}
-
-/*
- * DES-ECB block encryption/decryption
- */
-int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] )
-{
-    unsigned char iv[8] = {0x00};
-    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output);
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * DES-CBC buffer encryption/decryption
- */
-int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output )
-{
-    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output);
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/*
- * 3DES-ECB block encryption/decryption
- */
-int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
-                     const unsigned char input[8],
-                     unsigned char output[8] )
-{
-    unsigned char iv[8] = {0x00};
-    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output);
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * 3DES-CBC buffer encryption/decryption
- */
-int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
-                     int mode,
-                     size_t length,
-                     unsigned char iv[8],
-                     const unsigned char *input,
-                     unsigned char *output )
-{
-    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output);
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-
-
-static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, 
-    unsigned char iv[8], const unsigned char *input, unsigned char *output)
-{
-    if (length % 8) {
-        return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH;
-    }
-    
-    // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting.
-    CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) |
-        tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos);
-
-    // Keying option 1: All three keys are independent.
-    // Keying option 2: K1 and K2 are independent, and K3 = K1.
-    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. 
-    if (keyopt == 1) {
-        CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk;
-    }
-    else {
-        CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk;
-    }
-
-    // Set DES/TDES keys
-    // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap.
-    uint32_t val;
-    volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0));
-    val = nu_get32_be(key[0] + 0);
-    *tdes_key ++ = val;
-    val = nu_get32_be(key[0] + 4);
-    *tdes_key ++ = val;
-    val = nu_get32_be(key[1] + 0);
-    *tdes_key ++ = val;
-    val = nu_get32_be(key[1] + 4);
-    *tdes_key ++ = val;
-    val = nu_get32_be(key[2] + 0);
-    *tdes_key ++ = val;
-    val = nu_get32_be(key[2] + 4);
-    *tdes_key ++ = val;
-    
-    uint32_t rmn = length;
-    const unsigned char *in_pos = input;
-    const unsigned char *out_pos = output;
-    
-    while (rmn) {
-        uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF;
-        
-        uint32_t ivh, ivl;
-        ivh = nu_get32_be(iv);
-        ivl = nu_get32_be(iv + 4);
-        TDES_SetInitVect(0, ivh, ivl);
-    
-        memcpy(dmabuf_in, in_pos, data_len);
-        
-        TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len);
-        
-        // Start enc/dec.
-        // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting.
-        CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos);
-        while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk);
-        
-        memcpy(out_pos, dmabuf_out, data_len);
-        in_pos += data_len;
-        out_pos += data_len;
-        rmn -= data_len;
-        
-        // Update IV for next block enc/dec in next function call
-        switch (tdes_opmode) {
-            case DES_MODE_OFB:
-            case TDES_MODE_OFB: {
-                // OFB: IV (enc/dec) = output block XOR input block
-                uint32_t lbh, lbl;
-                // Last block of input data
-                lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4);
-                lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0);
-                // Last block of output data
-                ivh = nu_get32_be(dmabuf_out + 4);
-                ivl = nu_get32_be(dmabuf_out + 0);
-                ivh = ivh ^ lbh;
-                ivl = ivl ^ lbl;
-                nu_set32_be(iv + 4, ivh);
-                nu_set32_be(iv, ivl);
-                break;
-            }
-            case DES_MODE_CBC:
-            case DES_MODE_CFB:
-            case TDES_MODE_CBC:
-            case TDES_MODE_CFB: {
-                // CBC/CFB: IV (enc) = output block
-                //          IV (dec) = input block
-                if (enc) {    
-                    memcpy(iv, dmabuf_out + data_len - 8, 8);
-                }
-                else {
-                    memcpy(iv, dmabuf_in + data_len - 8, 8);
-                }
-            }
-        }
-    }
-    
-    return 0;
-}
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,280 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- 
-#ifndef MBEDTLS_DES_ALT_H
-#define MBEDTLS_DES_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-#include "des.h"
-#include "des_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          DES context structure
- */
-typedef struct
-{
-    int enc;                                            /*!<  0: dec, 1: enc    */
-    uint16_t keyopt;
-    uint8_t key[3][MBEDTLS_DES_KEY_SIZE];               /*!<  3DES keys         */
-}
-mbedtls_des_context;
-
-/**
- * \brief          Triple-DES context structure
- */
-typedef struct
-{
-    int enc;                                            /*!<  0: dec, 1: enc    */
-    uint16_t keyopt;
-    uint8_t key[3][MBEDTLS_DES_KEY_SIZE];               /*!<  3DES keys         */
-}
-mbedtls_des3_context;
-
-/**
- * \brief          Initialize DES context
- *
- * \param ctx      DES context to be initialized
- */
-void mbedtls_des_init( mbedtls_des_context *ctx );
-
-/**
- * \brief          Clear DES context
- *
- * \param ctx      DES context to be cleared
- */
-void mbedtls_des_free( mbedtls_des_context *ctx );
-
-/**
- * \brief          Initialize Triple-DES context
- *
- * \param ctx      DES3 context to be initialized
- */
-void mbedtls_des3_init( mbedtls_des3_context *ctx );
-
-/**
- * \brief          Clear Triple-DES context
- *
- * \param ctx      DES3 context to be cleared
- */
-void mbedtls_des3_free( mbedtls_des3_context *ctx );
-
-/**
- * \brief          Set key parity on the given key to odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- */
-void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key parity on the given key is odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- *
- * \return         0 is parity was ok, 1 if parity was not correct.
- */
-int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key is not a weak or semi-weak DES key
- *
- * \param key      8-byte secret key
- *
- * \return         0 if no weak key was found, 1 if a weak key was identified.
- */
-int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, encryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- */
-int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, decryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- */
-int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          DES-ECB block encryption/decryption
- *
- * \param ctx      DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- */
-int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- */
-int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          3DES-ECB block encryption/decryption
- *
- * \param ctx      3DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- */
-int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
-                     const unsigned char input[8],
-                     unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          3DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      3DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
- */
-int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
-                     int mode,
-                     size_t length,
-                     unsigned char iv[8],
-                     const unsigned char *input,
-                     unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          Internal function for key expansion.
- *                 (Only exposed to allow overriding it,
- *                 see MBEDTLS_DES_SETKEY_ALT)
- *
- * \param SK       Round keys
- * \param key      Base key
- */
-void mbedtls_des_setkey( uint32_t SK[32],
-                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_DES_ALT */
-
-#endif /* des_alt.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,802 +0,0 @@
-/*
- *  FIPS-46-3 compliant Triple-DES implementation
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- *  DES, on which TDES is based, was originally designed by Horst Feistel
- *  at IBM in 1974, and was adopted as a standard by NIST (formerly NBS).
- *
- *  http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include "mbedtls/des.h"
-
-#include <string.h>
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i)                            \
-{                                                       \
-    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-        | ( (uint32_t) (b)[(i) + 3]       );            \
-}
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i)                            \
-{                                                       \
-    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-}
-#endif
-
-/*
- * Expanded DES S-boxes
- */
-static const uint32_t SB1[64] =
-{
-    0x01010400, 0x00000000, 0x00010000, 0x01010404,
-    0x01010004, 0x00010404, 0x00000004, 0x00010000,
-    0x00000400, 0x01010400, 0x01010404, 0x00000400,
-    0x01000404, 0x01010004, 0x01000000, 0x00000004,
-    0x00000404, 0x01000400, 0x01000400, 0x00010400,
-    0x00010400, 0x01010000, 0x01010000, 0x01000404,
-    0x00010004, 0x01000004, 0x01000004, 0x00010004,
-    0x00000000, 0x00000404, 0x00010404, 0x01000000,
-    0x00010000, 0x01010404, 0x00000004, 0x01010000,
-    0x01010400, 0x01000000, 0x01000000, 0x00000400,
-    0x01010004, 0x00010000, 0x00010400, 0x01000004,
-    0x00000400, 0x00000004, 0x01000404, 0x00010404,
-    0x01010404, 0x00010004, 0x01010000, 0x01000404,
-    0x01000004, 0x00000404, 0x00010404, 0x01010400,
-    0x00000404, 0x01000400, 0x01000400, 0x00000000,
-    0x00010004, 0x00010400, 0x00000000, 0x01010004
-};
-
-static const uint32_t SB2[64] =
-{
-    0x80108020, 0x80008000, 0x00008000, 0x00108020,
-    0x00100000, 0x00000020, 0x80100020, 0x80008020,
-    0x80000020, 0x80108020, 0x80108000, 0x80000000,
-    0x80008000, 0x00100000, 0x00000020, 0x80100020,
-    0x00108000, 0x00100020, 0x80008020, 0x00000000,
-    0x80000000, 0x00008000, 0x00108020, 0x80100000,
-    0x00100020, 0x80000020, 0x00000000, 0x00108000,
-    0x00008020, 0x80108000, 0x80100000, 0x00008020,
-    0x00000000, 0x00108020, 0x80100020, 0x00100000,
-    0x80008020, 0x80100000, 0x80108000, 0x00008000,
-    0x80100000, 0x80008000, 0x00000020, 0x80108020,
-    0x00108020, 0x00000020, 0x00008000, 0x80000000,
-    0x00008020, 0x80108000, 0x00100000, 0x80000020,
-    0x00100020, 0x80008020, 0x80000020, 0x00100020,
-    0x00108000, 0x00000000, 0x80008000, 0x00008020,
-    0x80000000, 0x80100020, 0x80108020, 0x00108000
-};
-
-static const uint32_t SB3[64] =
-{
-    0x00000208, 0x08020200, 0x00000000, 0x08020008,
-    0x08000200, 0x00000000, 0x00020208, 0x08000200,
-    0x00020008, 0x08000008, 0x08000008, 0x00020000,
-    0x08020208, 0x00020008, 0x08020000, 0x00000208,
-    0x08000000, 0x00000008, 0x08020200, 0x00000200,
-    0x00020200, 0x08020000, 0x08020008, 0x00020208,
-    0x08000208, 0x00020200, 0x00020000, 0x08000208,
-    0x00000008, 0x08020208, 0x00000200, 0x08000000,
-    0x08020200, 0x08000000, 0x00020008, 0x00000208,
-    0x00020000, 0x08020200, 0x08000200, 0x00000000,
-    0x00000200, 0x00020008, 0x08020208, 0x08000200,
-    0x08000008, 0x00000200, 0x00000000, 0x08020008,
-    0x08000208, 0x00020000, 0x08000000, 0x08020208,
-    0x00000008, 0x00020208, 0x00020200, 0x08000008,
-    0x08020000, 0x08000208, 0x00000208, 0x08020000,
-    0x00020208, 0x00000008, 0x08020008, 0x00020200
-};
-
-static const uint32_t SB4[64] =
-{
-    0x00802001, 0x00002081, 0x00002081, 0x00000080,
-    0x00802080, 0x00800081, 0x00800001, 0x00002001,
-    0x00000000, 0x00802000, 0x00802000, 0x00802081,
-    0x00000081, 0x00000000, 0x00800080, 0x00800001,
-    0x00000001, 0x00002000, 0x00800000, 0x00802001,
-    0x00000080, 0x00800000, 0x00002001, 0x00002080,
-    0x00800081, 0x00000001, 0x00002080, 0x00800080,
-    0x00002000, 0x00802080, 0x00802081, 0x00000081,
-    0x00800080, 0x00800001, 0x00802000, 0x00802081,
-    0x00000081, 0x00000000, 0x00000000, 0x00802000,
-    0x00002080, 0x00800080, 0x00800081, 0x00000001,
-    0x00802001, 0x00002081, 0x00002081, 0x00000080,
-    0x00802081, 0x00000081, 0x00000001, 0x00002000,
-    0x00800001, 0x00002001, 0x00802080, 0x00800081,
-    0x00002001, 0x00002080, 0x00800000, 0x00802001,
-    0x00000080, 0x00800000, 0x00002000, 0x00802080
-};
-
-static const uint32_t SB5[64] =
-{
-    0x00000100, 0x02080100, 0x02080000, 0x42000100,
-    0x00080000, 0x00000100, 0x40000000, 0x02080000,
-    0x40080100, 0x00080000, 0x02000100, 0x40080100,
-    0x42000100, 0x42080000, 0x00080100, 0x40000000,
-    0x02000000, 0x40080000, 0x40080000, 0x00000000,
-    0x40000100, 0x42080100, 0x42080100, 0x02000100,
-    0x42080000, 0x40000100, 0x00000000, 0x42000000,
-    0x02080100, 0x02000000, 0x42000000, 0x00080100,
-    0x00080000, 0x42000100, 0x00000100, 0x02000000,
-    0x40000000, 0x02080000, 0x42000100, 0x40080100,
-    0x02000100, 0x40000000, 0x42080000, 0x02080100,
-    0x40080100, 0x00000100, 0x02000000, 0x42080000,
-    0x42080100, 0x00080100, 0x42000000, 0x42080100,
-    0x02080000, 0x00000000, 0x40080000, 0x42000000,
-    0x00080100, 0x02000100, 0x40000100, 0x00080000,
-    0x00000000, 0x40080000, 0x02080100, 0x40000100
-};
-
-static const uint32_t SB6[64] =
-{
-    0x20000010, 0x20400000, 0x00004000, 0x20404010,
-    0x20400000, 0x00000010, 0x20404010, 0x00400000,
-    0x20004000, 0x00404010, 0x00400000, 0x20000010,
-    0x00400010, 0x20004000, 0x20000000, 0x00004010,
-    0x00000000, 0x00400010, 0x20004010, 0x00004000,
-    0x00404000, 0x20004010, 0x00000010, 0x20400010,
-    0x20400010, 0x00000000, 0x00404010, 0x20404000,
-    0x00004010, 0x00404000, 0x20404000, 0x20000000,
-    0x20004000, 0x00000010, 0x20400010, 0x00404000,
-    0x20404010, 0x00400000, 0x00004010, 0x20000010,
-    0x00400000, 0x20004000, 0x20000000, 0x00004010,
-    0x20000010, 0x20404010, 0x00404000, 0x20400000,
-    0x00404010, 0x20404000, 0x00000000, 0x20400010,
-    0x00000010, 0x00004000, 0x20400000, 0x00404010,
-    0x00004000, 0x00400010, 0x20004010, 0x00000000,
-    0x20404000, 0x20000000, 0x00400010, 0x20004010
-};
-
-static const uint32_t SB7[64] =
-{
-    0x00200000, 0x04200002, 0x04000802, 0x00000000,
-    0x00000800, 0x04000802, 0x00200802, 0x04200800,
-    0x04200802, 0x00200000, 0x00000000, 0x04000002,
-    0x00000002, 0x04000000, 0x04200002, 0x00000802,
-    0x04000800, 0x00200802, 0x00200002, 0x04000800,
-    0x04000002, 0x04200000, 0x04200800, 0x00200002,
-    0x04200000, 0x00000800, 0x00000802, 0x04200802,
-    0x00200800, 0x00000002, 0x04000000, 0x00200800,
-    0x04000000, 0x00200800, 0x00200000, 0x04000802,
-    0x04000802, 0x04200002, 0x04200002, 0x00000002,
-    0x00200002, 0x04000000, 0x04000800, 0x00200000,
-    0x04200800, 0x00000802, 0x00200802, 0x04200800,
-    0x00000802, 0x04000002, 0x04200802, 0x04200000,
-    0x00200800, 0x00000000, 0x00000002, 0x04200802,
-    0x00000000, 0x00200802, 0x04200000, 0x00000800,
-    0x04000002, 0x04000800, 0x00000800, 0x00200002
-};
-
-static const uint32_t SB8[64] =
-{
-    0x10001040, 0x00001000, 0x00040000, 0x10041040,
-    0x10000000, 0x10001040, 0x00000040, 0x10000000,
-    0x00040040, 0x10040000, 0x10041040, 0x00041000,
-    0x10041000, 0x00041040, 0x00001000, 0x00000040,
-    0x10040000, 0x10000040, 0x10001000, 0x00001040,
-    0x00041000, 0x00040040, 0x10040040, 0x10041000,
-    0x00001040, 0x00000000, 0x00000000, 0x10040040,
-    0x10000040, 0x10001000, 0x00041040, 0x00040000,
-    0x00041040, 0x00040000, 0x10041000, 0x00001000,
-    0x00000040, 0x10040040, 0x00001000, 0x00041040,
-    0x10001000, 0x00000040, 0x10000040, 0x10040000,
-    0x10040040, 0x10000000, 0x00040000, 0x10001040,
-    0x00000000, 0x10041040, 0x00040040, 0x10000040,
-    0x10040000, 0x10001000, 0x10001040, 0x00000000,
-    0x10041040, 0x00041000, 0x00041000, 0x00001040,
-    0x00001040, 0x00040040, 0x10000000, 0x10041000
-};
-
-/*
- * PC1: left and right halves bit-swap
- */
-static const uint32_t LHs[16] =
-{
-    0x00000000, 0x00000001, 0x00000100, 0x00000101,
-    0x00010000, 0x00010001, 0x00010100, 0x00010101,
-    0x01000000, 0x01000001, 0x01000100, 0x01000101,
-    0x01010000, 0x01010001, 0x01010100, 0x01010101
-};
-
-static const uint32_t RHs[16] =
-{
-    0x00000000, 0x01000000, 0x00010000, 0x01010000,
-    0x00000100, 0x01000100, 0x00010100, 0x01010100,
-    0x00000001, 0x01000001, 0x00010001, 0x01010001,
-    0x00000101, 0x01000101, 0x00010101, 0x01010101,
-};
-
-/*
- * Initial Permutation macro
- */
-#define DES_IP(X,Y)                                             \
-{                                                               \
-    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
-    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
-    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
-    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
-    Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF;                    \
-    T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T;                   \
-    X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF;                    \
-}
-
-/*
- * Final Permutation macro
- */
-#define DES_FP(X,Y)                                             \
-{                                                               \
-    X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF;                    \
-    T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T;                   \
-    Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF;                    \
-    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
-    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
-    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
-    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
-}
-
-/*
- * DES round macro
- */
-#define DES_ROUND(X,Y)                          \
-{                                               \
-    T = *SK++ ^ X;                              \
-    Y ^= SB8[ (T      ) & 0x3F ] ^              \
-         SB6[ (T >>  8) & 0x3F ] ^              \
-         SB4[ (T >> 16) & 0x3F ] ^              \
-         SB2[ (T >> 24) & 0x3F ];               \
-                                                \
-    T = *SK++ ^ ((X << 28) | (X >> 4));         \
-    Y ^= SB7[ (T      ) & 0x3F ] ^              \
-         SB5[ (T >>  8) & 0x3F ] ^              \
-         SB3[ (T >> 16) & 0x3F ] ^              \
-         SB1[ (T >> 24) & 0x3F ];               \
-}
-
-#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; }
-
-void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx )
-{
-    memset( ctx, 0, sizeof( mbedtls_des_sw_context ) );
-}
-
-void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx )
-{
-    if( ctx == NULL )
-        return;
-
-    mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) );
-}
-
-void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx )
-{
-    memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) );
-}
-
-void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx )
-{
-    if( ctx == NULL )
-        return;
-
-    mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) );
-}
-
-static const unsigned char odd_parity_table[128] = { 1,  2,  4,  7,  8,
-        11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
-        47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
-        82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
-        115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
-        143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
-        171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
-        199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
-        227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
-        254 };
-
-void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
-        key[i] = odd_parity_table[key[i] / 2];
-}
-
-/*
- * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
- */
-int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
-        if( key[i] != odd_parity_table[key[i] / 2] )
-            return( 1 );
-
-    return( 0 );
-}
-
-/*
- * Table of weak and semi-weak keys
- *
- * Source: http://en.wikipedia.org/wiki/Weak_key
- *
- * Weak:
- * Alternating ones + zeros (0x0101010101010101)
- * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
- * '0xE0E0E0E0F1F1F1F1'
- * '0x1F1F1F1F0E0E0E0E'
- *
- * Semi-weak:
- * 0x011F011F010E010E and 0x1F011F010E010E01
- * 0x01E001E001F101F1 and 0xE001E001F101F101
- * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
- * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
- * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
- * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
- *
- */
-
-#define WEAK_KEY_COUNT 16
-
-static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
-{
-    { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
-    { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
-    { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
-    { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
-
-    { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
-    { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
-    { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
-    { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
-    { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
-    { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
-    { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
-    { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
-    { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
-    { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
-    { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
-    { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
-};
-
-int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    for( i = 0; i < WEAK_KEY_COUNT; i++ )
-        if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
-            return( 1 );
-
-    return( 0 );
-}
-
-void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-    uint32_t X, Y, T;
-
-    GET_UINT32_BE( X, key, 0 );
-    GET_UINT32_BE( Y, key, 4 );
-
-    /*
-     * Permuted Choice 1
-     */
-    T =  ((Y >>  4) ^ X) & 0x0F0F0F0F;  X ^= T; Y ^= (T <<  4);
-    T =  ((Y      ) ^ X) & 0x10101010;  X ^= T; Y ^= (T      );
-
-    X =   (LHs[ (X      ) & 0xF] << 3) | (LHs[ (X >>  8) & 0xF ] << 2)
-        | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ]     )
-        | (LHs[ (X >>  5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6)
-        | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4);
-
-    Y =   (RHs[ (Y >>  1) & 0xF] << 3) | (RHs[ (Y >>  9) & 0xF ] << 2)
-        | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ]     )
-        | (RHs[ (Y >>  4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6)
-        | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4);
-
-    X &= 0x0FFFFFFF;
-    Y &= 0x0FFFFFFF;
-
-    /*
-     * calculate subkeys
-     */
-    for( i = 0; i < 16; i++ )
-    {
-        if( i < 2 || i == 8 || i == 15 )
-        {
-            X = ((X <<  1) | (X >> 27)) & 0x0FFFFFFF;
-            Y = ((Y <<  1) | (Y >> 27)) & 0x0FFFFFFF;
-        }
-        else
-        {
-            X = ((X <<  2) | (X >> 26)) & 0x0FFFFFFF;
-            Y = ((Y <<  2) | (Y >> 26)) & 0x0FFFFFFF;
-        }
-
-        *SK++ =   ((X <<  4) & 0x24000000) | ((X << 28) & 0x10000000)
-                | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000)
-                | ((X <<  6) & 0x01000000) | ((X <<  9) & 0x00200000)
-                | ((X >>  1) & 0x00100000) | ((X << 10) & 0x00040000)
-                | ((X <<  2) & 0x00020000) | ((X >> 10) & 0x00010000)
-                | ((Y >> 13) & 0x00002000) | ((Y >>  4) & 0x00001000)
-                | ((Y <<  6) & 0x00000800) | ((Y >>  1) & 0x00000400)
-                | ((Y >> 14) & 0x00000200) | ((Y      ) & 0x00000100)
-                | ((Y >>  5) & 0x00000020) | ((Y >> 10) & 0x00000010)
-                | ((Y >>  3) & 0x00000008) | ((Y >> 18) & 0x00000004)
-                | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001);
-
-        *SK++ =   ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000)
-                | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000)
-                | ((X >>  2) & 0x02000000) | ((X <<  1) & 0x01000000)
-                | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000)
-                | ((X <<  3) & 0x00080000) | ((X >>  6) & 0x00040000)
-                | ((X << 15) & 0x00020000) | ((X >>  4) & 0x00010000)
-                | ((Y >>  2) & 0x00002000) | ((Y <<  8) & 0x00001000)
-                | ((Y >> 14) & 0x00000808) | ((Y >>  9) & 0x00000400)
-                | ((Y      ) & 0x00000200) | ((Y <<  7) & 0x00000100)
-                | ((Y >>  7) & 0x00000020) | ((Y >>  3) & 0x00000011)
-                | ((Y <<  2) & 0x00000004) | ((Y >> 21) & 0x00000002);
-    }
-}
-
-/*
- * DES key schedule (56-bit, encryption)
- */
-int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    mbedtls_des_setkey( ctx->sk, key );
-
-    return( 0 );
-}
-
-/*
- * DES key schedule (56-bit, decryption)
- */
-int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
-    int i;
-
-    mbedtls_des_setkey( ctx->sk, key );
-
-    for( i = 0; i < 16; i += 2 )
-    {
-        SWAP( ctx->sk[i    ], ctx->sk[30 - i] );
-        SWAP( ctx->sk[i + 1], ctx->sk[31 - i] );
-    }
-
-    return( 0 );
-}
-
-static void des3_set2key( uint32_t esk[96],
-                          uint32_t dsk[96],
-                          const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] )
-{
-    int i;
-
-    mbedtls_des_setkey( esk, key );
-    mbedtls_des_setkey( dsk + 32, key + 8 );
-
-    for( i = 0; i < 32; i += 2 )
-    {
-        dsk[i     ] = esk[30 - i];
-        dsk[i +  1] = esk[31 - i];
-
-        esk[i + 32] = dsk[62 - i];
-        esk[i + 33] = dsk[63 - i];
-
-        esk[i + 64] = esk[i    ];
-        esk[i + 65] = esk[i + 1];
-
-        dsk[i + 64] = dsk[i    ];
-        dsk[i + 65] = dsk[i + 1];
-    }
-}
-
-/*
- * Triple-DES key schedule (112-bit, encryption)
- */
-int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
-    uint32_t sk[96];
-
-    des3_set2key( ctx->sk, sk, key );
-    mbedtls_zeroize( sk,  sizeof( sk ) );
-
-    return( 0 );
-}
-
-/*
- * Triple-DES key schedule (112-bit, decryption)
- */
-int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
-    uint32_t sk[96];
-
-    des3_set2key( sk, ctx->sk, key );
-    mbedtls_zeroize( sk,  sizeof( sk ) );
-
-    return( 0 );
-}
-
-static void des3_set3key( uint32_t esk[96],
-                          uint32_t dsk[96],
-                          const unsigned char key[24] )
-{
-    int i;
-
-    mbedtls_des_setkey( esk, key );
-    mbedtls_des_setkey( dsk + 32, key +  8 );
-    mbedtls_des_setkey( esk + 64, key + 16 );
-
-    for( i = 0; i < 32; i += 2 )
-    {
-        dsk[i     ] = esk[94 - i];
-        dsk[i +  1] = esk[95 - i];
-
-        esk[i + 32] = dsk[62 - i];
-        esk[i + 33] = dsk[63 - i];
-
-        dsk[i + 64] = esk[30 - i];
-        dsk[i + 65] = esk[31 - i];
-    }
-}
-
-/*
- * Triple-DES key schedule (168-bit, encryption)
- */
-int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
-    uint32_t sk[96];
-
-    des3_set3key( ctx->sk, sk, key );
-    mbedtls_zeroize( sk,  sizeof( sk ) );
-
-    return( 0 );
-}
-
-/*
- * Triple-DES key schedule (168-bit, decryption)
- */
-int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
-    uint32_t sk[96];
-
-    des3_set3key( sk, ctx->sk, key );
-    mbedtls_zeroize( sk,  sizeof( sk ) );
-
-    return( 0 );
-}
-
-/*
- * DES-ECB block encryption/decryption
- */
-int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] )
-{
-    int i;
-    uint32_t X, Y, T, *SK;
-
-    SK = ctx->sk;
-
-    GET_UINT32_BE( X, input, 0 );
-    GET_UINT32_BE( Y, input, 4 );
-
-    DES_IP( X, Y );
-
-    for( i = 0; i < 8; i++ )
-    {
-        DES_ROUND( Y, X );
-        DES_ROUND( X, Y );
-    }
-
-    DES_FP( Y, X );
-
-    PUT_UINT32_BE( Y, output, 0 );
-    PUT_UINT32_BE( X, output, 4 );
-
-    return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * DES-CBC buffer encryption/decryption
- */
-int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output )
-{
-    int i;
-    unsigned char temp[8];
-
-    if( length % 8 )
-        return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
-
-    if( mode == MBEDTLS_DES_ENCRYPT )
-    {
-        while( length > 0 )
-        {
-            for( i = 0; i < 8; i++ )
-                output[i] = (unsigned char)( input[i] ^ iv[i] );
-
-            mbedtls_des_sw_crypt_ecb( ctx, output, output );
-            memcpy( iv, output, 8 );
-
-            input  += 8;
-            output += 8;
-            length -= 8;
-        }
-    }
-    else /* MBEDTLS_DES_DECRYPT */
-    {
-        while( length > 0 )
-        {
-            memcpy( temp, input, 8 );
-            mbedtls_des_sw_crypt_ecb( ctx, input, output );
-
-            for( i = 0; i < 8; i++ )
-                output[i] = (unsigned char)( output[i] ^ iv[i] );
-
-            memcpy( iv, temp, 8 );
-
-            input  += 8;
-            output += 8;
-            length -= 8;
-        }
-    }
-
-    return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/*
- * 3DES-ECB block encryption/decryption
- */
-int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
-                     const unsigned char input[8],
-                     unsigned char output[8] )
-{
-    int i;
-    uint32_t X, Y, T, *SK;
-
-    SK = ctx->sk;
-
-    GET_UINT32_BE( X, input, 0 );
-    GET_UINT32_BE( Y, input, 4 );
-
-    DES_IP( X, Y );
-
-    for( i = 0; i < 8; i++ )
-    {
-        DES_ROUND( Y, X );
-        DES_ROUND( X, Y );
-    }
-
-    for( i = 0; i < 8; i++ )
-    {
-        DES_ROUND( X, Y );
-        DES_ROUND( Y, X );
-    }
-
-    for( i = 0; i < 8; i++ )
-    {
-        DES_ROUND( Y, X );
-        DES_ROUND( X, Y );
-    }
-
-    DES_FP( Y, X );
-
-    PUT_UINT32_BE( Y, output, 0 );
-    PUT_UINT32_BE( X, output, 4 );
-
-    return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * 3DES-CBC buffer encryption/decryption
- */
-int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
-                     int mode,
-                     size_t length,
-                     unsigned char iv[8],
-                     const unsigned char *input,
-                     unsigned char *output )
-{
-    int i;
-    unsigned char temp[8];
-
-    if( length % 8 )
-        return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
-
-    if( mode == MBEDTLS_DES_ENCRYPT )
-    {
-        while( length > 0 )
-        {
-            for( i = 0; i < 8; i++ )
-                output[i] = (unsigned char)( input[i] ^ iv[i] );
-
-            mbedtls_des3_sw_crypt_ecb( ctx, output, output );
-            memcpy( iv, output, 8 );
-
-            input  += 8;
-            output += 8;
-            length -= 8;
-        }
-    }
-    else /* MBEDTLS_DES_DECRYPT */
-    {
-        while( length > 0 )
-        {
-            memcpy( temp, input, 8 );
-            mbedtls_des3_sw_crypt_ecb( ctx, input, output );
-
-            for( i = 0; i < 8; i++ )
-                output[i] = (unsigned char)( output[i] ^ iv[i] );
-
-            memcpy( iv, temp, 8 );
-
-            input  += 8;
-            output += 8;
-            length -= 8;
-        }
-    }
-
-    return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/**
- * \file des.h
- *
- * \brief DES block cipher
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_DES_ALT_SW_H
-#define MBEDTLS_DES_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          DES context structure
- */
-typedef struct
-{
-    uint32_t sk[32];            /*!<  DES subkeys       */
-}
-mbedtls_des_sw_context;
-
-/**
- * \brief          Triple-DES context structure
- */
-typedef struct
-{
-    uint32_t sk[96];            /*!<  3DES subkeys      */
-}
-mbedtls_des3_sw_context;
-
-/**
- * \brief          Initialize DES context
- *
- * \param ctx      DES context to be initialized
- */
-void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx );
-
-/**
- * \brief          Clear DES context
- *
- * \param ctx      DES context to be cleared
- */
-void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx );
-
-/**
- * \brief          Initialize Triple-DES context
- *
- * \param ctx      DES3 context to be initialized
- */
-void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx );
-
-/**
- * \brief          Clear Triple-DES context
- *
- * \param ctx      DES3 context to be cleared
- */
-void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx );
-
-/**
- * \brief          Set key parity on the given key to odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- */
-void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key parity on the given key is odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- *
- * \return         0 is parity was ok, 1 if parity was not correct.
- */
-int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key is not a weak or semi-weak DES key
- *
- * \param key      8-byte secret key
- *
- * \return         0 if no weak key was found, 1 if a weak key was identified.
- */
-int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, encryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- */
-int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, decryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- */
-int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          DES-ECB block encryption/decryption
- *
- * \param ctx      DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- */
-int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- */
-int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          3DES-ECB block encryption/decryption
- *
- * \param ctx      3DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- */
-int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
-                     const unsigned char input[8],
-                     unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          3DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      3DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
- */
-int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
-                     int mode,
-                     size_t length,
-                     unsigned char iv[8],
-                     const unsigned char *input,
-                     unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          Internal function for key expansion.
- *                 (Only exposed to allow overriding it,
- *                 see MBEDTLS_DES_SETKEY_ALT)
- *
- * \param SK       Round keys
- * \param key      Base key
- */
-void mbedtls_des_sw_setkey( uint32_t SK[32],
-                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
-
-#endif /* des.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,143 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "sha1_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "string.h"
-
-void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
-{
-    if (crypto_sha_acquire()) {
-        ctx->ishw = 1;
-        mbedtls_sha1_hw_init(&ctx->hw_ctx);
-    }
-    else {
-        ctx->ishw = 0;
-        mbedtls_sha1_sw_init(&ctx->sw_ctx);
-    }
-}
-
-void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    if (ctx->ishw) {
-        mbedtls_sha1_hw_free(&ctx->hw_ctx);
-        crypto_sha_release();
-    }
-    else {
-        mbedtls_sha1_sw_free(&ctx->sw_ctx);
-    }
-}
-
-void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
-                        const mbedtls_sha1_context *src)
-{
-    if (src->ishw) {
-        // Clone S/W ctx from H/W ctx
-        dst->ishw = 0;
-        dst->sw_ctx.total[0] = src->hw_ctx.total;
-        dst->sw_ctx.total[1] = 0;
-        {
-            unsigned char output[20];
-            crypto_sha_getinternstate(output, sizeof (output));
-            unsigned char *output_pos = output;
-            unsigned char *output_end = output + (sizeof (output) / sizeof (output[0]));
-            uint32_t *state_pos = (uint32_t *) &(dst->sw_ctx.state[0]);
-            while (output_pos != output_end) {
-                *state_pos ++ = nu_get32_be(output_pos);
-                output_pos += 4;
-            }
-        }
-        memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
-        if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
-            mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
-        }
-    }
-    else {
-        // Clone S/W ctx from S/W ctx
-        dst->sw_ctx = src->sw_ctx;
-    }
-}
-
-/*
- * SHA-1 context setup
- */
-void mbedtls_sha1_starts(mbedtls_sha1_context *ctx)
-{
-    if (ctx->ishw) {
-        mbedtls_sha1_hw_starts(&ctx->hw_ctx);
-    }
-    else {
-        mbedtls_sha1_sw_starts(&ctx->sw_ctx);
-    }
-}
-
-/*
- * SHA-1 process buffer
- */
-void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
-{
-    if (ctx->ishw) {
-        mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen);
-    }
-    else {
-        mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen);
-    }
-}
-
-/*
- * SHA-1 final digest
- */
-void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
-{
-    if (ctx->ishw) {
-        mbedtls_sha1_hw_finish(&ctx->hw_ctx, output);
-    }
-    else {
-        mbedtls_sha1_sw_finish(&ctx->sw_ctx, output);
-    }
-}
-
-void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
-{
-    if (ctx->ishw) {
-        mbedtls_sha1_hw_process(&ctx->hw_ctx, data);
-    }
-    else {
-        mbedtls_sha1_sw_process(&ctx->sw_ctx, data);
-    }
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA1_ALT_H
-#define MBEDTLS_SHA1_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "sha_alt_hw.h"
-#include "sha1_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct mbedtls_sha1_context_s;
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct mbedtls_sha1_context_s
-{
-    int ishw;
-    crypto_sha_context hw_ctx;
-    mbedtls_sha1_sw_context sw_ctx;
-}
-mbedtls_sha1_context;
-
-/**
- * \brief          Initialize SHA-1 context
- *
- * \param ctx      SHA-1 context to be initialized
- */
-void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          Clear SHA-1 context
- *
- * \param ctx      SHA-1 context to be cleared
- */
-void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          Clone (the state of) a SHA-1 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
-                         const mbedtls_sha1_context *src );
-
-/**
- * \brief          SHA-1 context setup
- *
- * \param ctx      context to be initialized
- */
-void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          SHA-1 process buffer
- *
- * \param ctx      SHA-1 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
-
-/**
- * \brief          SHA-1 final digest
- *
- * \param ctx      SHA-1 context
- * \param output   SHA-1 checksum result
- */
-void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
-
-/* Internal use */
-void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* sha1_alt.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,350 +0,0 @@
-/*
- *  FIPS-180-1 compliant SHA-1 implementation
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- *  The SHA-1 standard was published by NIST in 1993.
- *
- *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "mbedtls/sha1.h"
-
-#include <string.h>
-#if defined(MBEDTLS_SELF_TEST)
-#if defined(MBEDTLS_PLATFORM_C)
-#include "mbedtls/platform.h"
-#else
-#include <stdio.h>
-#define mbedtls_printf printf
-#endif /* MBEDTLS_PLATFORM_C */
-#endif /* MBEDTLS_SELF_TEST */
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i)                            \
-{                                                       \
-    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-        | ( (uint32_t) (b)[(i) + 3]       );            \
-}
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i)                            \
-{                                                       \
-    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-}
-#endif
-
-void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx )
-{
-    memset( ctx, 0, sizeof( mbedtls_sha1_sw_context ) );
-}
-
-void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx )
-{
-    if( ctx == NULL )
-        return;
-
-    mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_sw_context ) );
-}
-
-void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
-                         const mbedtls_sha1_sw_context *src )
-{
-    *dst = *src;
-}
-
-/*
- * SHA-1 context setup
- */
-void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx )
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    ctx->state[0] = 0x67452301;
-    ctx->state[1] = 0xEFCDAB89;
-    ctx->state[2] = 0x98BADCFE;
-    ctx->state[3] = 0x10325476;
-    ctx->state[4] = 0xC3D2E1F0;
-}
-
-void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] )
-{
-    uint32_t temp, W[16], A, B, C, D, E;
-
-    GET_UINT32_BE( W[ 0], data,  0 );
-    GET_UINT32_BE( W[ 1], data,  4 );
-    GET_UINT32_BE( W[ 2], data,  8 );
-    GET_UINT32_BE( W[ 3], data, 12 );
-    GET_UINT32_BE( W[ 4], data, 16 );
-    GET_UINT32_BE( W[ 5], data, 20 );
-    GET_UINT32_BE( W[ 6], data, 24 );
-    GET_UINT32_BE( W[ 7], data, 28 );
-    GET_UINT32_BE( W[ 8], data, 32 );
-    GET_UINT32_BE( W[ 9], data, 36 );
-    GET_UINT32_BE( W[10], data, 40 );
-    GET_UINT32_BE( W[11], data, 44 );
-    GET_UINT32_BE( W[12], data, 48 );
-    GET_UINT32_BE( W[13], data, 52 );
-    GET_UINT32_BE( W[14], data, 56 );
-    GET_UINT32_BE( W[15], data, 60 );
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define R(t)                                            \
-(                                                       \
-    temp = W[( t -  3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \
-           W[( t - 14 ) & 0x0F] ^ W[  t       & 0x0F],  \
-    ( W[t & 0x0F] = S(temp,1) )                         \
-)
-
-#define P(a,b,c,d,e,x)                                  \
-{                                                       \
-    e += S(a,5) + F(b,c,d) + K + x; b = S(b,30);        \
-}
-
-    A = ctx->state[0];
-    B = ctx->state[1];
-    C = ctx->state[2];
-    D = ctx->state[3];
-    E = ctx->state[4];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-#define K 0x5A827999
-
-    P( A, B, C, D, E, W[0]  );
-    P( E, A, B, C, D, W[1]  );
-    P( D, E, A, B, C, W[2]  );
-    P( C, D, E, A, B, W[3]  );
-    P( B, C, D, E, A, W[4]  );
-    P( A, B, C, D, E, W[5]  );
-    P( E, A, B, C, D, W[6]  );
-    P( D, E, A, B, C, W[7]  );
-    P( C, D, E, A, B, W[8]  );
-    P( B, C, D, E, A, W[9]  );
-    P( A, B, C, D, E, W[10] );
-    P( E, A, B, C, D, W[11] );
-    P( D, E, A, B, C, W[12] );
-    P( C, D, E, A, B, W[13] );
-    P( B, C, D, E, A, W[14] );
-    P( A, B, C, D, E, W[15] );
-    P( E, A, B, C, D, R(16) );
-    P( D, E, A, B, C, R(17) );
-    P( C, D, E, A, B, R(18) );
-    P( B, C, D, E, A, R(19) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0x6ED9EBA1
-
-    P( A, B, C, D, E, R(20) );
-    P( E, A, B, C, D, R(21) );
-    P( D, E, A, B, C, R(22) );
-    P( C, D, E, A, B, R(23) );
-    P( B, C, D, E, A, R(24) );
-    P( A, B, C, D, E, R(25) );
-    P( E, A, B, C, D, R(26) );
-    P( D, E, A, B, C, R(27) );
-    P( C, D, E, A, B, R(28) );
-    P( B, C, D, E, A, R(29) );
-    P( A, B, C, D, E, R(30) );
-    P( E, A, B, C, D, R(31) );
-    P( D, E, A, B, C, R(32) );
-    P( C, D, E, A, B, R(33) );
-    P( B, C, D, E, A, R(34) );
-    P( A, B, C, D, E, R(35) );
-    P( E, A, B, C, D, R(36) );
-    P( D, E, A, B, C, R(37) );
-    P( C, D, E, A, B, R(38) );
-    P( B, C, D, E, A, R(39) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) ((x & y) | (z & (x | y)))
-#define K 0x8F1BBCDC
-
-    P( A, B, C, D, E, R(40) );
-    P( E, A, B, C, D, R(41) );
-    P( D, E, A, B, C, R(42) );
-    P( C, D, E, A, B, R(43) );
-    P( B, C, D, E, A, R(44) );
-    P( A, B, C, D, E, R(45) );
-    P( E, A, B, C, D, R(46) );
-    P( D, E, A, B, C, R(47) );
-    P( C, D, E, A, B, R(48) );
-    P( B, C, D, E, A, R(49) );
-    P( A, B, C, D, E, R(50) );
-    P( E, A, B, C, D, R(51) );
-    P( D, E, A, B, C, R(52) );
-    P( C, D, E, A, B, R(53) );
-    P( B, C, D, E, A, R(54) );
-    P( A, B, C, D, E, R(55) );
-    P( E, A, B, C, D, R(56) );
-    P( D, E, A, B, C, R(57) );
-    P( C, D, E, A, B, R(58) );
-    P( B, C, D, E, A, R(59) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0xCA62C1D6
-
-    P( A, B, C, D, E, R(60) );
-    P( E, A, B, C, D, R(61) );
-    P( D, E, A, B, C, R(62) );
-    P( C, D, E, A, B, R(63) );
-    P( B, C, D, E, A, R(64) );
-    P( A, B, C, D, E, R(65) );
-    P( E, A, B, C, D, R(66) );
-    P( D, E, A, B, C, R(67) );
-    P( C, D, E, A, B, R(68) );
-    P( B, C, D, E, A, R(69) );
-    P( A, B, C, D, E, R(70) );
-    P( E, A, B, C, D, R(71) );
-    P( D, E, A, B, C, R(72) );
-    P( C, D, E, A, B, R(73) );
-    P( B, C, D, E, A, R(74) );
-    P( A, B, C, D, E, R(75) );
-    P( E, A, B, C, D, R(76) );
-    P( D, E, A, B, C, R(77) );
-    P( C, D, E, A, B, R(78) );
-    P( B, C, D, E, A, R(79) );
-
-#undef K
-#undef F
-
-    ctx->state[0] += A;
-    ctx->state[1] += B;
-    ctx->state[2] += C;
-    ctx->state[3] += D;
-    ctx->state[4] += E;
-}
-
-/*
- * SHA-1 process buffer
- */
-void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen )
-{
-    size_t fill;
-    uint32_t left;
-
-    if( ilen == 0 )
-        return;
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if( ctx->total[0] < (uint32_t) ilen )
-        ctx->total[1]++;
-
-    if( left && ilen >= fill )
-    {
-        memcpy( (void *) (ctx->buffer + left), input, fill );
-        mbedtls_sha1_sw_process( ctx, ctx->buffer );
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while( ilen >= 64 )
-    {
-        mbedtls_sha1_sw_process( ctx, input );
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if( ilen > 0 )
-        memcpy( (void *) (ctx->buffer + left), input, ilen );
-}
-
-static const unsigned char sha1_padding[64] =
-{
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-1 final digest
- */
-void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] )
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = ( ctx->total[0] >> 29 )
-         | ( ctx->total[1] <<  3 );
-    low  = ( ctx->total[0] <<  3 );
-
-    PUT_UINT32_BE( high, msglen, 0 );
-    PUT_UINT32_BE( low,  msglen, 4 );
-
-    last = ctx->total[0] & 0x3F;
-    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
-
-    mbedtls_sha1_sw_update( ctx, sha1_padding, padn );
-    mbedtls_sha1_sw_update( ctx, msglen, 8 );
-
-    PUT_UINT32_BE( ctx->state[0], output,  0 );
-    PUT_UINT32_BE( ctx->state[1], output,  4 );
-    PUT_UINT32_BE( ctx->state[2], output,  8 );
-    PUT_UINT32_BE( ctx->state[3], output, 12 );
-    PUT_UINT32_BE( ctx->state[4], output, 16 );
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/**
- * \file sha1.h
- *
- * \brief SHA-1 cryptographic hash function
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA1_ALT_SW_H
-#define MBEDTLS_SHA1_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[5];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-mbedtls_sha1_sw_context;
-
-/**
- * \brief          Initialize SHA-1 context
- *
- * \param ctx      SHA-1 context to be initialized
- */
-void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief          Clear SHA-1 context
- *
- * \param ctx      SHA-1 context to be cleared
- */
-void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief          Clone (the state of) a SHA-1 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
-                         const mbedtls_sha1_sw_context *src );
-
-/**
- * \brief          SHA-1 context setup
- *
- * \param ctx      context to be initialized
- */
-void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief          SHA-1 process buffer
- *
- * \param ctx      SHA-1 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen );
-
-/**
- * \brief          SHA-1 final digest
- *
- * \param ctx      SHA-1 context
- * \param output   SHA-1 checksum result
- */
-void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] );
-
-/* Internal use */
-void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* sha1_alt_sw.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "sha256_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "string.h"
-
-void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
-{
-    if (crypto_sha_acquire()) {
-        ctx->ishw = 1;
-        mbedtls_sha256_hw_init(&ctx->hw_ctx);
-    }
-    else {
-        ctx->ishw = 0;
-        mbedtls_sha256_sw_init(&ctx->sw_ctx);
-    }
-}
-
-void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    if (ctx->ishw) {
-        mbedtls_sha256_hw_free(&ctx->hw_ctx);
-        crypto_sha_release();
-    }
-    else {
-        mbedtls_sha256_sw_free(&ctx->sw_ctx);
-    }
-}
-
-void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
-                        const mbedtls_sha256_context *src)
-{
-    if (src->ishw) {
-        // Clone S/W ctx from H/W ctx
-        dst->ishw = 0;
-        dst->sw_ctx.total[0] = src->hw_ctx.total;
-        dst->sw_ctx.total[1] = 0;
-        {
-            unsigned char output[32];
-            crypto_sha_getinternstate(output, sizeof (output));
-            unsigned char *output_pos = output;
-            unsigned char *output_end = output + (sizeof (output) / sizeof (output[0]));
-            uint32_t *state_pos = (uint32_t *) &(dst->sw_ctx.state[0]);
-            while (output_pos != output_end) {
-                *state_pos ++ = nu_get32_be(output_pos);
-                output_pos += 4;
-            }
-        }
-        memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
-        dst->sw_ctx.is224 = src->hw_ctx.is224;
-        if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
-            mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
-        }
-    }
-    else {
-        // Clone S/W ctx from S/W ctx
-        dst->sw_ctx = src->sw_ctx;
-    }
-}
-
-/*
- * SHA-256 context setup
- */
-void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224)
-{   
-    if (ctx->ishw) {
-        mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224);
-    }
-    else {
-        mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224);
-    }
-}
-
-/*
- * SHA-256 process buffer
- */
-void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
-{
-    if (ctx->ishw) {
-        mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen);
-    }
-    else {
-        mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen);
-    }
-}
-
-/*
- * SHA-256 final digest
- */
-void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32])
-{
-    if (ctx->ishw) {
-        mbedtls_sha256_hw_finish(&ctx->hw_ctx, output);
-    }
-    else {
-        mbedtls_sha256_sw_finish(&ctx->sw_ctx, output);
-    }
-}
-
-void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
-{
-    if (ctx->ishw) {
-        mbedtls_sha256_hw_process(&ctx->hw_ctx, data);
-    }
-    else {
-        mbedtls_sha256_sw_process(&ctx->sw_ctx, data);
-    }
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA256_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,107 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA256_ALT_H
-#define MBEDTLS_SHA256_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "sha_alt_hw.h"
-#include "sha256_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct mbedtls_sha256_context_s;
-
-/**
- * \brief          SHA-256 context structure
- */
-typedef struct mbedtls_sha256_context_s
-{
-    int ishw;
-    crypto_sha_context hw_ctx;
-    mbedtls_sha256_sw_context sw_ctx;
-}
-mbedtls_sha256_context;
-
-/**
- * \brief          Initialize SHA-256 context
- *
- * \param ctx      SHA-256 context to be initialized
- */
-void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
-
-/**
- * \brief          Clear SHA-256 context
- *
- * \param ctx      SHA-256 context to be cleared
- */
-void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
-
-/**
- * \brief          Clone (the state of) a SHA-256 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
-                           const mbedtls_sha256_context *src );
-
-/**
- * \brief          SHA-256 context setup
- *
- * \param ctx      context to be initialized
- * \param is224    0 = use SHA256, 1 = use SHA224
- */
-void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
-
-/**
- * \brief          SHA-256 process buffer
- *
- * \param ctx      SHA-256 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
-                    size_t ilen );
-
-/**
- * \brief          SHA-256 final digest
- *
- * \param ctx      SHA-256 context
- * \param output   SHA-224/256 checksum result
- */
-void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
-
-/* Internal use */
-void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA256_C */
-
-#endif /* sha256_alt.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/*
- *  FIPS-180-2 compliant SHA-256 implementation
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- *  The SHA-256 Secure Hash Standard was published by NIST in 2002.
- *
- *  http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "mbedtls/sha256.h"
-
-#include <string.h>
-#if defined(MBEDTLS_SELF_TEST)
-#if defined(MBEDTLS_PLATFORM_C)
-#include "mbedtls/platform.h"
-#else
-#include <stdio.h>
-#include <stdlib.h>
-#define mbedtls_printf printf
-#define mbedtls_calloc    calloc
-#define mbedtls_free       free
-#endif /* MBEDTLS_PLATFORM_C */
-#endif /* MBEDTLS_SELF_TEST */
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
-    volatile unsigned char *p = v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i)                            \
-do {                                                    \
-    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-        | ( (uint32_t) (b)[(i) + 3]       );            \
-} while( 0 )
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i)                            \
-do {                                                    \
-    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-} while( 0 )
-#endif
-
-void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx )
-{
-    memset( ctx, 0, sizeof( mbedtls_sha256_sw_context ) );
-}
-
-void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx )
-{
-    if( ctx == NULL )
-        return;
-
-    mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_sw_context ) );
-}
-
-void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
-                           const mbedtls_sha256_sw_context *src )
-{
-    *dst = *src;
-}
-
-/*
- * SHA-256 context setup
- */
-void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 )
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    if( is224 == 0 )
-    {
-        /* SHA-256 */
-        ctx->state[0] = 0x6A09E667;
-        ctx->state[1] = 0xBB67AE85;
-        ctx->state[2] = 0x3C6EF372;
-        ctx->state[3] = 0xA54FF53A;
-        ctx->state[4] = 0x510E527F;
-        ctx->state[5] = 0x9B05688C;
-        ctx->state[6] = 0x1F83D9AB;
-        ctx->state[7] = 0x5BE0CD19;
-    }
-    else
-    {
-        /* SHA-224 */
-        ctx->state[0] = 0xC1059ED8;
-        ctx->state[1] = 0x367CD507;
-        ctx->state[2] = 0x3070DD17;
-        ctx->state[3] = 0xF70E5939;
-        ctx->state[4] = 0xFFC00B31;
-        ctx->state[5] = 0x68581511;
-        ctx->state[6] = 0x64F98FA7;
-        ctx->state[7] = 0xBEFA4FA4;
-    }
-
-    ctx->is224 = is224;
-}
-
-static const uint32_t K[] =
-{
-    0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
-    0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
-    0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
-    0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
-    0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
-    0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
-    0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
-    0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
-    0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
-    0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
-    0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
-    0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
-    0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
-    0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
-    0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
-    0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
-};
-
-#define  SHR(x,n) ((x & 0xFFFFFFFF) >> n)
-#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
-
-#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^  SHR(x, 3))
-#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^  SHR(x,10))
-
-#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
-#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
-
-#define F0(x,y,z) ((x & y) | (z & (x | y)))
-#define F1(x,y,z) (z ^ (x & (y ^ z)))
-
-#define R(t)                                    \
-(                                               \
-    W[t] = S1(W[t -  2]) + W[t -  7] +          \
-           S0(W[t - 15]) + W[t - 16]            \
-)
-
-#define P(a,b,c,d,e,f,g,h,x,K)                  \
-{                                               \
-    temp1 = h + S3(e) + F1(e,f,g) + K + x;      \
-    temp2 = S2(a) + F0(a,b,c);                  \
-    d += temp1; h = temp1 + temp2;              \
-}
-
-void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] )
-{
-    uint32_t temp1, temp2, W[64];
-    uint32_t A[8];
-    unsigned int i;
-
-    for( i = 0; i < 8; i++ )
-        A[i] = ctx->state[i];
-
-#if defined(MBEDTLS_SHA256_SMALLER)
-    for( i = 0; i < 64; i++ )
-    {
-        if( i < 16 )
-            GET_UINT32_BE( W[i], data, 4 * i );
-        else
-            R( i );
-
-        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] );
-
-        temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3];
-        A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1;
-    }
-#else /* MBEDTLS_SHA256_SMALLER */
-    for( i = 0; i < 16; i++ )
-        GET_UINT32_BE( W[i], data, 4 * i );
-
-    for( i = 0; i < 16; i += 8 )
-    {
-        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] );
-        P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] );
-        P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] );
-        P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i+3], K[i+3] );
-        P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i+4], K[i+4] );
-        P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i+5], K[i+5] );
-        P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i+6], K[i+6] );
-        P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] );
-    }
-
-    for( i = 16; i < 64; i += 8 )
-    {
-        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] );
-        P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] );
-        P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] );
-        P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i+3), K[i+3] );
-        P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i+4), K[i+4] );
-        P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i+5), K[i+5] );
-        P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i+6), K[i+6] );
-        P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i+7), K[i+7] );
-    }
-#endif /* MBEDTLS_SHA256_SMALLER */
-
-    for( i = 0; i < 8; i++ )
-        ctx->state[i] += A[i];
-}
-
-/*
- * SHA-256 process buffer
- */
-void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
-                    size_t ilen )
-{
-    size_t fill;
-    uint32_t left;
-
-    if( ilen == 0 )
-        return;
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if( ctx->total[0] < (uint32_t) ilen )
-        ctx->total[1]++;
-
-    if( left && ilen >= fill )
-    {
-        memcpy( (void *) (ctx->buffer + left), input, fill );
-        mbedtls_sha256_sw_process( ctx, ctx->buffer );
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while( ilen >= 64 )
-    {
-        mbedtls_sha256_sw_process( ctx, input );
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if( ilen > 0 )
-        memcpy( (void *) (ctx->buffer + left), input, ilen );
-}
-
-static const unsigned char sha256_padding[64] =
-{
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-256 final digest
- */
-void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] )
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = ( ctx->total[0] >> 29 )
-         | ( ctx->total[1] <<  3 );
-    low  = ( ctx->total[0] <<  3 );
-
-    PUT_UINT32_BE( high, msglen, 0 );
-    PUT_UINT32_BE( low,  msglen, 4 );
-
-    last = ctx->total[0] & 0x3F;
-    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
-
-    mbedtls_sha256_sw_update( ctx, sha256_padding, padn );
-    mbedtls_sha256_sw_update( ctx, msglen, 8 );
-
-    PUT_UINT32_BE( ctx->state[0], output,  0 );
-    PUT_UINT32_BE( ctx->state[1], output,  4 );
-    PUT_UINT32_BE( ctx->state[2], output,  8 );
-    PUT_UINT32_BE( ctx->state[3], output, 12 );
-    PUT_UINT32_BE( ctx->state[4], output, 16 );
-    PUT_UINT32_BE( ctx->state[5], output, 20 );
-    PUT_UINT32_BE( ctx->state[6], output, 24 );
-
-    if( ctx->is224 == 0 )
-        PUT_UINT32_BE( ctx->state[7], output, 28 );
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#endif /* MBEDTLS_SHA256_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/**
- * \file sha256.h
- *
- * \brief SHA-224 and SHA-256 cryptographic hash function
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA256_ALT_SW_H
-#define MBEDTLS_SHA256_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          SHA-256 context structure
- */
-typedef struct
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[8];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
-}
-mbedtls_sha256_sw_context;
-
-/**
- * \brief          Initialize SHA-256 context
- *
- * \param ctx      SHA-256 context to be initialized
- */
-void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx );
-
-/**
- * \brief          Clear SHA-256 context
- *
- * \param ctx      SHA-256 context to be cleared
- */
-void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx );
-
-/**
- * \brief          Clone (the state of) a SHA-256 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
-                           const mbedtls_sha256_sw_context *src );
-
-/**
- * \brief          SHA-256 context setup
- *
- * \param ctx      context to be initialized
- * \param is224    0 = use SHA256, 1 = use SHA224
- */
-void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 );
-
-/**
- * \brief          SHA-256 process buffer
- *
- * \param ctx      SHA-256 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
-                    size_t ilen );
-
-/**
- * \brief          SHA-256 final digest
- *
- * \param ctx      SHA-256 context
- * \param output   SHA-224/256 checksum result
- */
-void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] );
-
-/* Internal use */
-void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA256_C */
-
-#endif /* sha256_alt_sw.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,338 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* Compatible with mbed OS 2 which doesn't support mbedtls */
-#if MBED_CONF_RTOS_PRESENT
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
-
-#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
-
-#if defined(MBEDTLS_SHA1_ALT)
-#include "sha1_alt.h"
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-#include "sha256_alt.h"
-#endif /* MBEDTLS_SHA256_ALT */
-
-#if defined(MBEDTLS_SHA512_ALT)
-#include "sha512_alt.h"
-#endif /* MBEDTLS_SHA512_ALT */
-
-#include "nu_bitutil.h"
-#include "mbed_assert.h"
-#include "crypto-misc.h"
-
-#include <string.h>
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
-void crypto_sha_getinternstate(unsigned char output[], size_t olen);
-
-#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
-
-#if defined(MBEDTLS_SHA1_ALT)
-
-void mbedtls_sha1_hw_init(crypto_sha_context *ctx)
-{
-    crypto_init();
-    memset(ctx, 0, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha1_hw_free(crypto_sha_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    crypto_zeroize(ctx, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha1_hw_clone(crypto_sha_context *dst,
-                        const crypto_sha_context *src)
-{
-    *dst = *src;
-}
-
-void mbedtls_sha1_hw_starts(crypto_sha_context *ctx)
-{
-    // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
-    CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-    
-    ctx->total = 0;
-    ctx->buffer_left = 0;
-    ctx->blocksize = 64;
-    ctx->blocksize_mask = 0x3F;
-
-    SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP);
-    
-    // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
-    CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
-    
-    return;
-}
-
-void mbedtls_sha1_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
-    crypto_sha_update(ctx, input, ilen);
-}
-
-void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20])
-{
-    // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
-    if (ctx->total) {
-        crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
-        ctx->buffer_left = 0;
-        crypto_sha_getinternstate(output, 20);
-    
-        CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-    }
-    else {
-        mbedtls_sha1_sw_context ctx_sw;
-    
-        mbedtls_sha1_sw_init(&ctx_sw);
-        mbedtls_sha1_sw_starts(&ctx_sw);
-        mbedtls_sha1_sw_finish(&ctx_sw, output);
-        mbedtls_sha1_sw_free(&ctx_sw);
-    }
-}
-
-void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
-{
-    mbedtls_sha1_hw_update(ctx, data, 64);
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-void mbedtls_sha256_hw_init(crypto_sha_context *ctx)
-{
-    crypto_init();
-    memset(ctx, 0, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha256_hw_free(crypto_sha_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    crypto_zeroize(ctx, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha256_hw_clone(crypto_sha_context *dst,
-                        const crypto_sha_context *src)
-{
-    *dst = *src;
-}
-
-void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224)
-{
-    // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
-    CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-     
-    ctx->total = 0;
-    ctx->buffer_left = 0;
-    ctx->blocksize = 64;
-    ctx->blocksize_mask = 0x3F;
-    ctx->is224 = is224;
-
-    SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP);
-    
-    // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
-    CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
-    
-    return;
-}
-
-void mbedtls_sha256_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
-    crypto_sha_update(ctx, input, ilen);
-}
-
-void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32])
-{
-    // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
-    if (ctx->total) {
-        crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
-        ctx->buffer_left = 0;
-        crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32);
-    
-        CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-    }
-    else {
-        mbedtls_sha256_sw_context ctx_sw;
-    
-        mbedtls_sha256_sw_init(&ctx_sw);
-        mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224);
-        mbedtls_sha256_sw_finish(&ctx_sw, output);
-        mbedtls_sha256_sw_free(&ctx_sw);
-    }
-}
-
-void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
-{
-    mbedtls_sha256_hw_update(ctx, data, 64);
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
-    if (ilen == 0) {
-        return;
-    }
-    
-    size_t fill = ctx->blocksize - ctx->buffer_left;
-
-    ctx->total += (uint32_t) ilen;
-
-    if (ctx->buffer_left && ilen >= fill) {
-        memcpy((void *) (ctx->buffer + ctx->buffer_left), input, fill);
-        input += fill;
-        ilen  -= fill;
-        ctx->buffer_left += fill;
-        if (ilen) {
-            crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 0);
-            ctx->buffer_left = 0;
-        }
-    }
-    
-    while (ilen > ctx->blocksize) {
-        crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0);
-        input += ctx->blocksize;
-        ilen  -= ctx->blocksize;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *) (ctx->buffer + ctx->buffer_left), input, ilen);
-        ctx->buffer_left += ilen;
-    }
-}
-
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast)
-{
-    // Accept only:
-    // 1. Last block which may be incomplete
-    // 2. Non-last block which is complete
-    MBED_ASSERT(islast || ilen == ctx->blocksize);
-    
-    const unsigned char *in_pos = input;
-    int rmn = ilen;
-    uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
-    uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos;
-    uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old;
-    
-    while (rmn > 0) {
-        CRPT->SHA_CTL = sha_ctl_start;
-        
-        uint32_t data = nu_get32_be(in_pos);
-        if (rmn <= 4) { // Last word of a (in)complete block
-            if (islast) {
-                uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
-                if (lastblock_size == 0) {
-                    lastblock_size = ctx->blocksize;
-                }
-                CRPT->SHA_DMACNT = lastblock_size;
-                CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
-            }
-            else {
-                switch (sha_opmode) {
-                    case SHA_MODE_SHA256:
-                        DGST7_old = CRPT->SHA_DGST7;
-                    case SHA_MODE_SHA224:
-                        DGST5_old = CRPT->SHA_DGST5;
-                        DGST6_old = CRPT->SHA_DGST6;
-                    case SHA_MODE_SHA1:
-                        DGST0_old = CRPT->SHA_DGST0;
-                        DGST1_old = CRPT->SHA_DGST1;
-                        DGST2_old = CRPT->SHA_DGST2;
-                        DGST3_old = CRPT->SHA_DGST3;
-                        DGST4_old = CRPT->SHA_DGST4;
-                }
-
-                CRPT->SHA_CTL = sha_ctl_start;
-            }
-        }
-        else {  // Non-last word of a complete block
-            CRPT->SHA_CTL = sha_ctl_start;
-        }
-        while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
-        CRPT->SHA_DATIN = data;
-        
-        in_pos += 4;
-        rmn -= 4;
-    }
-    
-    if (islast) {   // Finish of last block
-        while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
-    }
-    else {  // Finish of non-last block
-        // No H/W flag to indicate finish of non-last block process.
-        // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement.
-        int isfinish = 0;
-        while (! isfinish) {
-            switch (sha_opmode) {
-                case SHA_MODE_SHA256:
-                    if (DGST7_old != CRPT->SHA_DGST7) {
-                        isfinish = 1;
-                        break;
-                    }
-                case SHA_MODE_SHA224:
-                    if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) {
-                        isfinish = 1;
-                        break;
-                    }
-                case SHA_MODE_SHA1:
-                    if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 ||
-                        DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) {
-                        isfinish = 1;
-                        break;
-                    }
-            }
-        }
-    }
-}
-
-void crypto_sha_getinternstate(unsigned char output[], size_t olen)
-{
-    uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0;
-    unsigned char *out_pos = output;
-    uint32_t rmn = olen;
-    
-    while (rmn) {
-        uint32_t val = *in_pos ++;
-        nu_set32_be(out_pos, val);
-        out_pos += 4;
-        rmn -= 4;
-    }
-}
-
-#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
-
-#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */
-
-#endif /* MBED_CONF_RTOS_PRESENT */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA_ALT_HW_H
-#define MBEDTLS_SHA_ALT_HW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          SHA context structure
- */
-typedef struct
-{
-    uint32_t total;                 /*!< number of bytes processed  */
-    unsigned char buffer[128];      /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */
-    uint16_t buffer_left;
-    uint16_t blocksize;             /*!< block size */
-    uint32_t blocksize_mask;        /*!< block size mask */
-    
-    int is224;                      /*!< 0 => SHA-256, else SHA-224 */
-}
-crypto_sha_context;
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
-void crypto_sha_getinternstate(unsigned char output[], size_t olen);
-
-#if defined(MBEDTLS_SHA1_ALT)
-
-void mbedtls_sha1_hw_init( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_free( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_clone( crypto_sha_context *dst,
-                         const crypto_sha_context *src );
-void mbedtls_sha1_hw_starts( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen );
-void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] );
-void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-void mbedtls_sha256_hw_init( crypto_sha_context *ctx );
-void mbedtls_sha256_hw_free( crypto_sha_context *ctx );
-void mbedtls_sha256_hw_clone( crypto_sha_context *dst,
-                           const crypto_sha_context *src );
-void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 );
-void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input,
-                    size_t ilen );
-void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] );
-void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C*/
-
-#endif /* sha_alt.h */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c	Thu Aug 31 17:27:04 2017 +0100
@@ -1,8 +1,8 @@
 /****************************************************************************//**
  * @file     spi.c
  * @version  V0.10
- * $Revision: 15 $
- * $Date: 14/09/30 1:10p $
+ * $Revision: 16 $
+ * $Date: 15/06/18 4:00p $
  * @brief    NUC472/NUC442 SPI driver source file
  *
  * @note
@@ -102,7 +102,7 @@
   */
 void SPI_DisableAutoSS(SPI_T *spi)
 {
-    spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
+    spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
 }
 
 /**
@@ -118,7 +118,7 @@
   */
 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
 {
-    spi->SSCTL |= (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
+    spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
 }
 
 /**
@@ -153,12 +153,15 @@
             u32ClkSrc = CLK_GetPLLClockFreq();
     }
 
+    if(u32BusClock > u32ClkSrc)
+        u32BusClock = u32ClkSrc;
 
     if(u32BusClock != 0 ) {
         u32Div = (u32ClkSrc / u32BusClock) - 1;
         if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
             u32Div = SPI_CLKDIV_DIVIDER_Msk;
-    }
+    } else
+        return 0;
 
     spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.h	Thu Aug 31 17:27:04 2017 +0100
@@ -1,8 +1,8 @@
 /****************************************************************************//**
  * @file     spi.h
  * @version  V1.00
- * $Revision: 18 $
- * $Date: 14/10/06 1:36p $
+ * $Revision: 21 $
+ * $Date: 15/06/18 4:12p $
  * @brief    NUC472/NUC442 SPI driver header file
  *
  * @note
@@ -31,8 +31,8 @@
 
 #define SPI_MODE_0        (SPI_CTL_TXNEG_Msk)                             /*!< CLKP=0; RX_NEG=0; TX_NEG=1 \hideinitializer */
 #define SPI_MODE_1        (SPI_CTL_RXNEG_Msk)                             /*!< CLKP=0; RX_NEG=1; TX_NEG=0 \hideinitializer */
-#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        /*!< CLKP=1; RX_NEG=1; TX_NEG=0 \hideinitializer */
-#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        /*!< CLKP=1; RX_NEG=0; TX_NEG=1 \hideinitializer */
+#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        /*!< CLKP=1; RX_NEG=1; TX_NEG=0 \hideinitializer */
+#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        /*!< CLKP=1; RX_NEG=0; TX_NEG=1 \hideinitializer */
 
 #define SPI_SLAVE         (SPI_CTL_SLAVE_Msk)                             /*!< Set as slave \hideinitializer */
 #define SPI_MASTER        (0x0)                                           /*!< Set as master \hideinitializer */
@@ -70,7 +70,7 @@
   * @return none
   * \hideinitializer
   */
-#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (u32TimeoutPeriod & 0xFFFF) )
+#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (((uint32_t)u32TimeoutPeriod & 0xFFFF) << SPI_SSCTL_SLVTOCNT_Pos) )
 
 /**
   * @brief  Enable time out clear function for FIFO mode.
@@ -194,56 +194,41 @@
 #define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
 
 /**
-  * @brief  Disable automatic slave select function and set SPI_SS pin to high state.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
+  * @brief      Set SPIn_SS0 pin to high state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode.
   * \hideinitializer
   */
-static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
-{
-    spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
-    spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
-    spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
-}
+#define SPI_SET_SS0_HIGH(spi)   ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)))
 
 /**
-  * @brief  Disable automatic slave select function and set SPI_SS pin to low state.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
+  * @brief      Set SPIn_SS0 pin to low state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode.
   * \hideinitializer
   */
-static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
-{
-    spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
-    spi->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
-    spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
-}
+#define SPI_SET_SS0_LOW(spi)   ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)) | SPI_SS0)
 
 /**
-  * @brief  Disable automatic slave select function and set SPI_SS pin to high state.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
+  * @brief      Set SPIn_SS1 pin to high state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode.
   * \hideinitializer
   */
-static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
-{
-    spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
-    spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
-    spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
-}
+#define SPI_SET_SS1_HIGH(spi)   ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)))
 
 /**
-  * @brief  Disable automatic slave select function and set SPI_SS pin to low state.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
+  * @brief      Set SPIn_SS1 pin to low state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode.
   * \hideinitializer
   */
-static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
-{
-    spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
-    spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
-    spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
-}
+#define SPI_SET_SS1_LOW(spi)   ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)) | SPI_SS1)
+
 
 /**
   * @brief Enable byte reorder function.
@@ -342,14 +327,6 @@
 #define SPI_DISABLE(spi) (  (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
 
 /**
-  * @brief  Enable SPI Dual IO function.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
-  * \hideinitializer
-  */
-#define SPI_ENABLE_DUAL_MODE(spi) ( (spi)->CTL |= SPI_CTL_DUALIOEN_Msk )
-
-/**
   * @brief  Disable SPI Dual IO function.
   * @param[in]  spi is the base address of SPI module.
   * @return none
@@ -358,28 +335,20 @@
 #define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk )
 
 /**
-  * @brief  Set SPI Dual IO direction to input.
+  * @brief  Enable Dual IO function and set SPI Dual IO direction to input.
   * @param[in]  spi is the base address of SPI module.
   * @return none
   * \hideinitializer
   */
-#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
+#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_DUALIOEN_Msk )
 
 /**
-  * @brief  Set SPI Dual IO direction to output.
+  * @brief  Enable Dual IO function and set SPI Dual IO direction to output.
   * @param[in]  spi is the base address of SPI module.
   * @return none
   * \hideinitializer
   */
-#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
-
-/**
-  * @brief  Enable SPI QUAD IO function.
-  * @param[in]  spi is the base address of SPI module.
-  * @return none
-  * \hideinitializer
-  */
-#define SPI_ENABLE_QUAD_MODE(spi) ( (spi)->CTL |= SPI_CTL_QUADIOEN_Msk )
+#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk )
 
 /**
   * @brief  Disable SPI Dual IO function.
@@ -395,7 +364,7 @@
   * @return none
   * \hideinitializer
   */
-#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
+#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_QUADIOEN_Msk )
 
 /**
   * @brief  Set SPI Quad IO direction to output.
@@ -403,7 +372,7 @@
   * @return none
   * \hideinitializer
   */
-#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
+#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk )
 
 /**
   * @brief  Trigger RX PDMA transfer.
@@ -489,3 +458,4 @@
 #endif //__SPI_H__
 
 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -9,9 +9,9 @@
 define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
 define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000 - 1;
 define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000;
-define symbol __ICFEDIT_region_XRAM_end__   = 0x60100000;
+define symbol __ICFEDIT_region_XRAM_end__   = 0x60100000 - 1;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x800;
 define symbol __ICFEDIT_size_heap__   = 0xC0000;

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -9,7 +9,7 @@
 define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
 define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000 - 1;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x800;
 define symbol __ICFEDIT_size_heap__   = 0x8000;

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c	Thu Aug 31 17:27:04 2017 +0100
@@ -63,12 +63,11 @@
 extern uint32_t __bss_extern_end__ WEAK;
 
 extern void uvisor_init(void);
-//#if defined(TOOLCHAIN_GCC_ARM)
-//extern void _start(void);
-//#endif
-extern void software_init_hook(void) __attribute__((weak));
-extern void __libc_init_array(void);
-extern int main(void);
+#if defined(TOOLCHAIN_GCC_ARM)
+extern void _start(void);
+#else
+#error("For GCC toolchain, only support GNU ARM Embedded")
+#endif
 #endif
 
 /* Default empty handler */
@@ -431,14 +430,15 @@
     /* Disable Power-on Reset function */
     SYS_DISABLE_POR();
     
-    /* Enable register write-protection function */
-    SYS_LockReg();
-    
     /**
-     * Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
+     * NOTE 1: Unlock is required for perhaps some register access in SystemInit().
+     * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
      */
     SystemInit();
     
+    /* Enable register write-protection function */
+    SYS_LockReg();
+
 #if defined(__CC_ARM)
     __main();
     
@@ -475,19 +475,7 @@
         }
     }
     
-    //uvisor_init();
-
-    if (software_init_hook) {
-        /**
-         * Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
-         * Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
-         */
-        software_init_hook();
-    }
-    else {
-        __libc_init_array();
-        main();
-    }
+    _start();
     
 #endif
     /* Infinite loop */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -58,23 +58,23 @@
 
 #define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
 
-#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
-#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0
 #endif
 
-#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
-#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
 #endif
 static PinName gpio_irq_debounce_arr[] = {
-    MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+    MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
 };
 
-#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
 #endif
 
-#ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
 #endif
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
@@ -94,15 +94,16 @@
     obj->irq_id = id;
 
     GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
     //gpio_set(pin);
     
     {
-#if MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
+#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
         // Suppress compiler warning
         (void) gpio_irq_debounce_arr;
 
         // Configure de-bounce clock source and sampling cycle time
-        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
         GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
 #else
         // Enable de-bounce if the pin is in the de-bounce enable list
@@ -119,7 +120,7 @@
             if (pin_index == pin_index_debunce &&
                 port_index == port_index_debounce) {
                 // Configure de-bounce clock source and sampling cycle time
-                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
                 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 break;
             }

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c	Thu Aug 31 17:27:04 2017 +0100
@@ -137,7 +137,7 @@
         while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
 
         // Add power-down compensation
-        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
     }
     while (0);
 }

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-{
-    "name": "NUC472",
-    "config": {
-        "gpio-irq-debounce-enable": {
-            "help": "Enable GPIO IRQ debounce",
-            "value": 0
-        },
-        "gpio-irq-debounce-enable-list": {
-            "help": "Comma separated pin list to enable GPIO IRQ debounce",
-            "value": "NC"
-        },
-        "gpio-irq-debounce-clock-source": {
-            "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
-            "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
-        },
-
-        "gpio-irq-debounce-sample-rate": {
-            "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
-            "value": "GPIO_DBCTL_DBCLKSEL_16"
-        }
-    }
-}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -26,31 +26,33 @@
 
 #define YEAR0       1900
 //#define EPOCH_YR    1970
-static int rtc_inited = 0;
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
 void rtc_init(void)
 {
-    if (rtc_inited) {
+    if (rtc_isenabled()) {
         return;
     }
-    rtc_inited = 1;
-    
-    // Enable IP clock
-    CLK_EnableModuleClock(rtc_modinit.clkidx);
     
     RTC_Open(NULL);
 }
 
 void rtc_free(void)
 {
-    // FIXME
+    // N/A
 }
 
 int rtc_isenabled(void)
 {
-    return rtc_inited;
+    // NOTE: To access (RTC) registers, clock must be enabled first.
+    if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
+        // Enable IP clock
+        CLK_EnableModuleClock(rtc_modinit.clkidx);
+    }
+    
+    // NOTE: Check RTC Init Active flag to support crossing reset cycle.
+    return !! (RTC->INIT & RTC_INIT_INIT_Active_Msk);
 }
 
 /*
@@ -68,7 +70,9 @@
 
 time_t rtc_read(void)
 {
-    if (! rtc_inited) {
+    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+    if (! rtc_isenabled()) {
         rtc_init();
     }
     
@@ -94,7 +98,7 @@
 
 void rtc_write(time_t t)
 {
-    if (! rtc_inited) {
+    if (! rtc_isenabled()) {
         rtc_init();
     }
     

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -299,7 +299,11 @@
     // Flush Tx FIFO. Otherwise, output data may get lost on this change.
     while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
     
-    // TODO: Assert for not supported parity and data bits
+    // Sanity check arguments    
+    MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+    
     obj->serial.databits = data_bits;
     obj->serial.parity = parity;
     obj->serial.stopbits = stop_bits;

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -566,7 +566,7 @@
     // Receive Time-Out
     if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
         spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
-        //event |= SPI_EVENT_ERROR;
+        // Not using this IF. Just clear it.
     }
     // Transmit FIFO Under-Run
     if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {

--- a/targets/TARGET_NUVOTON/mbed_rtx.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/mbed_rtx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -19,7 +19,7 @@
 
 #include <stdint.h>
 
-#if defined(TARGET_NUMAKER_PFM_NUC472)
+#if defined(TARGET_NUVOTON)
 
 #if defined(__CC_ARM)
     extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Base[];
@@ -45,32 +45,6 @@
     #error "no toolchain defined"
 #endif
 
-#elif defined(TARGET_NUMAKER_PFM_M453)
-
-#if defined(__CC_ARM)
-    extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Base[];
-    extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Length[];
-    extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Base[];
-    extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Length[];
-    #define HEAP_START            ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base)
-    #define HEAP_SIZE             ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length)
-    #define ISR_STACK_START       ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base)
-    #define ISR_STACK_SIZE        ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length)
-#elif defined(__GNUC__)
-    extern uint32_t               __StackTop[];
-    extern uint32_t               __StackLimit[];
-    extern uint32_t               __end__[];
-    extern uint32_t               __HeapLimit[];
-    #define HEAP_START            ((unsigned char*)__end__)
-    #define HEAP_SIZE             ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
-    #define ISR_STACK_START       ((unsigned char*)__StackLimit)
-    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
-#elif defined(__ICCARM__)
-    /* No region declarations needed */
-#else
-    #error "no toolchain defined"
-#endif
-
-#endif
+#endif  // TARGET_NUVOTON
 
 #endif  // MBED_MBED_RTX_H

--- a/targets/TARGET_NUVOTON/nu_modutil.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NUVOTON/nu_modutil.c	Thu Aug 31 17:27:04 2017 +0100
@@ -23,7 +23,7 @@
     MBED_ASSERT(modprop_tab != NULL);
     const struct nu_modinit_s *modprop_ind = modprop_tab;
     while (modprop_ind->modname != NC) {
-        if (modname == modprop_ind->modname) {
+        if ((int) modname == modprop_ind->modname) {
             return modprop_ind;
         }
         else {

--- a/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -110,7 +110,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -146,7 +146,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -76,7 +76,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -112,7 +112,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -112,7 +112,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -148,7 +148,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC13XX/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -104,7 +104,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -140,7 +140,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -98,7 +98,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -146,7 +146,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -118,7 +118,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -153,7 +153,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -98,7 +98,7 @@
 
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -133,7 +133,7 @@
             obj->spi->CPSR = prescaler;
 
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -117,7 +117,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -152,7 +152,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;

--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -73,9 +73,7 @@
             }
             ap.rssi = record->signal_strength;
             ap.channel = record->channel;
-            WiFiAccessPoint *accesspoint = new WiFiAccessPoint(ap);
-            memcpy(&scan_handler->ap_details[scan_handler->ap_num], accesspoint, sizeof(WiFiAccessPoint));
-            delete[] accesspoint;
+            scan_handler->ap_details[scan_handler->ap_num] = WiFiAccessPoint(ap);
         }
         scan_handler->ap_num++;
     } else{

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
 //  {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - Not present

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -49,6 +49,10 @@
     {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
     {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
     {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -49,6 +49,10 @@
     {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
     {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
     {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
 //  {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - Not present

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18

--- a/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -39,21 +39,30 @@
 int adc_inited = 0;
 
 void analogin_init(analogin_t *obj, PinName pin) {
-    // Get the peripheral name from the pin and assign it to the object
-    obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-
-    // Get the functions (adc channel) from the pin and assign it to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {NC,   NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {NC,   NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {NC,   NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -40,22 +40,30 @@
 void analogin_init(analogin_t *obj, PinName pin)
 {
     RCC_PeriphCLKInitTypeDef  PeriphClkInit;
+    uint32_t function = (uint32_t)NC;
 
-    // Get the peripheral name from the pin and assign it to the object
-    obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-
-    // Get the functions (adc channel) from the pin and assign it to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -57,6 +57,10 @@
     {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
 
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -51,6 +51,10 @@
     {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - ARDUINO D3
     {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - ARDUINO D6
 
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -95,6 +95,10 @@
     //{PF_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
     {PF_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
 
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -58,6 +58,10 @@
     {PC_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
     {PC_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
 
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -91,7 +91,10 @@
     //{PF_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
     {PF_2,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
     {PF_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {NC,    NC,    0}
+};
 
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -55,7 +55,10 @@
     {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PB_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
     {PB_15, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+    {NC,    NC,    0}
+};
 
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -62,7 +62,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
     {PC_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
     {PC_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+    {NC,    NC,    0}
+};
 
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
     {ADC_VREF1,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18

--- a/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -52,21 +52,30 @@
     static int adc4_inited = 0;
 #endif
 
-    // Get the peripheral name from the pin and assign it to the object
-    obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+    uint32_t function = (uint32_t)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/stm32f410xb.sct	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/stm32f410xb.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -36,8 +36,8 @@
    .ANY (+RO)
   }
 
-  ; Total: 112 vectors = 448 bytes (0x1C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x1C0) (0x8000-0x1C0)  {  ; RW data
+  ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1C8) (0x8000-0x1C8)  {  ; RW data
    .ANY (+RW +ZI)
   }
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/stm32f410xb.sct	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/stm32f410xb.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -36,8 +36,8 @@
    .ANY (+RO)
   }
 
-  ; Total: 112 vectors = 448 bytes (0x1C0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x1C0) (0x8000-0x1C0)  {  ; RW data
+  ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1C8) (0x8000-0x1C8)  {  ; RW data
    .ANY (+RW +ZI)
   }
 

--- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -51,8 +51,8 @@
 #endif
     // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
     //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be >= 0xF0
-    if (pin < 0xF0) {
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
         // Normal channels
         // Get the peripheral name from the pin and assign it to the object
         obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);

--- a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -51,8 +51,8 @@
 #endif
     // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
     //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be >= 0xF0
-    if (pin < 0xF0) {
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
         // Normal channels
         // Get the peripheral name from the pin and assign it to the object
         obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1   = (int)USART1_BASE,
-    UART_2   = (int)USART2_BASE,
-    LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_9
-#define STDIO_UART_RX  PA_10
-#define STDIO_UART     UART_1
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_21 = (int)TIM21_BASE,
-    PWM_22 = (int)TIM22_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
-    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
-    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
-    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
-    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
-    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
-    {NC,   NC,    0}
-};
-
-const PinMap PinMap_ADC_Internal[] = {
-    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
-    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
-    {ADC_VLCD, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
-    {NC,   NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM21 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1 - Warning: user_button is on this pin
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
-    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
-    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
-    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
-    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
-    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
-//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
-//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {NC,    NC,      0}
-};
-
-const PinMap PinMap_UART_RTS[] = {
-    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_CTS[] = {
-    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {NC,    NC,       0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PinNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // ADC internal channels
-    ADC_TEMP = 0xF0,
-    ADC_VREF = 0xF1,
-    ADC_VLCD = 0xF2,
-
-    // Arduino connector namings
-    // Note: The Arduino connector is not present on this board.
-    // We keep these definitions for compatibility with Nucleo code examples.
-    A0          = PA_1,
-    A1          = PA_2,
-    A2          = PA_3,
-    A3          = PA_4,
-    A4          = PB_0,
-    A5          = PB_1,
-    D0          = PA_10,
-    D1          = PA_9,
-    D2          = PA_8,
-    D3          = PA_6,
-    D4          = PA_13,
-    D5          = PA_7,
-    D6          = PB_11,
-    D7          = PC_13,
-    D8          = PC_14,
-    D9          = PA_15,
-    D10         = PA_5,
-    D11         = PB_15,
-    D12         = PB_14,
-    D13         = PB_13,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PB_4,
-    LED2        = PA_5,
-    LED3        = PB_4,
-    LED4        = PA_5,
-    USER_BUTTON = PA_0,
-    // Standardized button names
-    BUTTON1 = USER_BUTTON,
-    SERIAL_TX   = PA_9,
-    SERIAL_RX   = PA_10,
-    USBTX       = PA_9,
-    USBRX       = PA_10,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PB_15,
-    SPI_MISO    = PB_14,
-    SPI_SCK     = PB_13,
-    SPI_CS      = PB_12,
-    PWM_OUT     = PB_11,
-
-    //USB pins
-    USB_DM = PA_11,
-    USB_DP = PA_12,
-    USB_NOE = PA_13,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,239 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_ARM_MICRO/stm32l053c8.sct	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_ARM_STD/stm32l053c8.sct	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_ARM_STD/sys.cpp	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_GCC_ARM/STM32L053X8.ld	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
-  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 8K - 0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l053xx.s
-  * @author    MCD Application Team
-  * @version   V1.5.0
-  * @date      8-January-2016
-  * @brief     STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_IAR/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,326 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32L053xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0800FFFF;
-
-/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x20001FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x400;
-define symbol __size_heap__   = 0x800;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/cmsis.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/cmsis_nvic.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
-// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-#define NVIC_NUM_VECTORS        48
-#define NVIC_RAM_VECTOR_ADDRESS 0x20000000    // Vectors positioned at start of RAM
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/hal_tick.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,65 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l0xx.h"
-#include "stm32l0xx_ll_tim.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM21
-#define TIM_MST_IRQ  TIM21_IRQn
-#define TIM_MST_RCC  __TIM21_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
-
-#define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
-
-#define TIM_MST_PCLK  2 // Select the peripheral clock number (1 or 2)
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,7508 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l053xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l053xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l053xx
-  * @{
-  */
-    
-#ifndef __STM32L053xx_H
-#define __STM32L053xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l053xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
-#define FLASH_END              ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
-#define DATA_EEPROM_BASE       ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000U)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000U)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000U)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400U)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800U)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00U)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000U)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800U)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400U)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800U)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400U)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800U)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00U)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000U)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400U)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00U)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000U)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018U)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CU)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400U)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800U)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400U)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00U)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400U)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708U)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000U)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800U)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800U)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008U)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CU)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030U)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044U)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058U)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CU)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080U)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8U)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000U)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        ((uint32_t)0x1FF8007CU)        /*!< FLASH Size register base address */
-#define UID_BASE              ((uint32_t)0x1FF80050U)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000U)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000U)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000U)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400U)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800U)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00U)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00U)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)                                       
-#define ADC_ISR_EOCAL_Msk          (0x1U << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)                                        
-#define ADC_ISR_AWD_Msk            (0x1U << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)                                        
-#define ADC_ISR_OVR_Msk            (0x1U << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)                                        
-#define ADC_ISR_EOSEQ_Msk          (0x1U << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)                                        
-#define ADC_ISR_EOC_Msk            (0x1U << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)                                        
-#define ADC_ISR_EOSMP_Msk          (0x1U << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)                                        
-#define ADC_ISR_ADRDY_Msk          (0x1U << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)                                       
-#define ADC_IER_EOCALIE_Msk        (0x1U << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)                                        
-#define ADC_IER_AWDIE_Msk          (0x1U << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)                                        
-#define ADC_IER_OVRIE_Msk          (0x1U << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)                                        
-#define ADC_IER_EOSEQIE_Msk        (0x1U << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)                                        
-#define ADC_IER_EOCIE_Msk          (0x1U << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)                                        
-#define ADC_IER_EOSMPIE_Msk        (0x1U << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)                                        
-#define ADC_IER_ADRDYIE_Msk        (0x1U << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)                                       
-#define ADC_CR_ADCAL_Msk           (0x1U << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)                                       
-#define ADC_CR_ADVREGEN_Msk        (0x1U << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)                                        
-#define ADC_CR_ADSTP_Msk           (0x1U << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)                                        
-#define ADC_CR_ADSTART_Msk         (0x1U << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)                                        
-#define ADC_CR_ADDIS_Msk           (0x1U << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)                                        
-#define ADC_CR_ADEN_Msk            (0x1U << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)                                       
-#define ADC_CFGR1_AWDCH_Msk        (0x1FU << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)                                       
-#define ADC_CFGR1_AWDEN_Msk        (0x1U << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)                                       
-#define ADC_CFGR1_AWDSGL_Msk       (0x1U << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)                                       
-#define ADC_CFGR1_DISCEN_Msk       (0x1U << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)                                       
-#define ADC_CFGR1_AUTOFF_Msk       (0x1U << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)                                       
-#define ADC_CFGR1_WAIT_Msk         (0x1U << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)                                       
-#define ADC_CFGR1_CONT_Msk         (0x1U << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)                                       
-#define ADC_CFGR1_OVRMOD_Msk       (0x1U << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)                                       
-#define ADC_CFGR1_EXTEN_Msk        (0x3U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)                                        
-#define ADC_CFGR1_EXTSEL_Msk       (0x7U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)                                        
-#define ADC_CFGR1_ALIGN_Msk        (0x1U << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)                                        
-#define ADC_CFGR1_RES_Msk          (0x3U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)                                        
-#define ADC_CFGR1_SCANDIR_Msk      (0x1U << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)                                        
-#define ADC_CFGR1_DMACFG_Msk       (0x1U << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)                                        
-#define ADC_CFGR1_DMAEN_Msk        (0x1U << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)                                        
-#define ADC_CFGR2_TOVS_Msk         (0x400001U << ADC_CFGR2_TOVS_Pos)           /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)                                        
-#define ADC_CFGR2_OVSS_Msk         (0xFU << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)                                        
-#define ADC_CFGR2_OVSR_Msk         (0x7U << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)                                        
-#define ADC_CFGR2_OVSE_Msk         (0x1U << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)                                       
-#define ADC_CFGR2_CKMODE_Msk       (0x3U << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)                                        
-#define ADC_SMPR_SMP_Msk           (0x7U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)                                       
-#define ADC_TR_HT_Msk              (0xFFFU << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)                                        
-#define ADC_TR_LT_Msk              (0xFFFU << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)                                        
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFU << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)                                       
-#define ADC_CHSELR_CHSEL18_Msk     (0x1U << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)                                       
-#define ADC_CHSELR_CHSEL17_Msk     (0x1U << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)                                       
-#define ADC_CHSELR_CHSEL16_Msk     (0x1U << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)                                       
-#define ADC_CHSELR_CHSEL15_Msk     (0x1U << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)                                       
-#define ADC_CHSELR_CHSEL14_Msk     (0x1U << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)                                       
-#define ADC_CHSELR_CHSEL13_Msk     (0x1U << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)                                       
-#define ADC_CHSELR_CHSEL12_Msk     (0x1U << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)                                       
-#define ADC_CHSELR_CHSEL11_Msk     (0x1U << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)                                       
-#define ADC_CHSELR_CHSEL10_Msk     (0x1U << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)                                        
-#define ADC_CHSELR_CHSEL9_Msk      (0x1U << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)                                        
-#define ADC_CHSELR_CHSEL8_Msk      (0x1U << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)                                        
-#define ADC_CHSELR_CHSEL7_Msk      (0x1U << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)                                        
-#define ADC_CHSELR_CHSEL6_Msk      (0x1U << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)                                        
-#define ADC_CHSELR_CHSEL5_Msk      (0x1U << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)                                        
-#define ADC_CHSELR_CHSEL4_Msk      (0x1U << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)                                        
-#define ADC_CHSELR_CHSEL3_Msk      (0x1U << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)                                        
-#define ADC_CHSELR_CHSEL2_Msk      (0x1U << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)                                        
-#define ADC_CHSELR_CHSEL1_Msk      (0x1U << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)                                        
-#define ADC_CHSELR_CHSEL0_Msk      (0x1U << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)                                        
-#define ADC_DR_DATA_Msk            (0xFFFFU << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)                                        
-#define ADC_CALFACT_CALFACT_Msk    (0x7FU << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)                                       
-#define ADC_CCR_LFMEN_Msk          (0x1U << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)                                       
-#define ADC_CCR_VLCDEN_Msk         (0x1U << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)                                       
-#define ADC_CCR_TSEN_Msk           (0x1U << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)                                       
-#define ADC_CCR_VREFEN_Msk         (0x1U << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)                                       
-#define ADC_CCR_PRESC_Msk          (0xFU << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1U << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2U << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4U << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8U << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)                                    
-#define COMP_CSR_COMP1EN_Msk           (0x1U << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)                                    
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)                                    
-#define COMP_CSR_COMP1WM_Msk           (0x1U << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)                                   
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1U << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)                                   
-#define COMP_CSR_COMP1VALUE_Msk        (0x1U << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)                                   
-#define COMP_CSR_COMP1LOCK_Msk         (0x1U << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)                                    
-#define COMP_CSR_COMP2EN_Msk           (0x1U << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)                                    
-#define COMP_CSR_COMP2SPEED_Msk        (0x1U << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)                                    
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)                                    
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)                                   
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)                                   
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1U << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)                                   
-#define COMP_CSR_COMP2VALUE_Msk        (0x1U << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)                                   
-#define COMP_CSR_COMP2LOCK_Msk         (0x1U << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)                                    
-#define COMP_CSR_COMPxEN_Msk           (0x1U << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1U << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)                                   
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1U << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)                                   
-#define COMP_CSR_COMPxLOCK_Msk         (0x1U << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)                                          
-#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)                                          
-#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)                                          
-#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)                                          
-#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)                                          
-#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)                                          
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)                                          
-#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
-#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
-#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)                                         
-#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)                                         
-#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)                                         
-#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)                                         
-#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)                                         
-#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)                                         
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)                                        
-#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
-#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
-#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
-#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
-#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
-#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)                                         
-#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)                                         
-#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)                                         
-#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
-#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
-#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)                                        
-#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)                                        
-#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
-#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
-#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)                                         
-#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)                                         
-#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)                                       
-#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)                                       
-#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)                                       
-#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)                                       
-#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)                                       
-#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)                                       
-#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)                                      
-#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
-#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR           ((uint16_t)0x00000FFFU)                    /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)                                      
-#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7U << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)                                            
-#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)                                            
-#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)                                            
-#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)                                            
-#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)                                            
-#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)                                            
-#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)                                            
-#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)                                            
-#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)                                            
-#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)                                            
-#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)                                           
-#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)                                           
-#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)                                           
-#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)                                           
-#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)                                           
-#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)                                           
-#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)                                           
-#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)                                           
-#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)                                           
-#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)                                           
-#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)                                           
-#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)                                           
-#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)                                           
-#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)                                           
-#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)                                           
-#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)                                           
-#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)                                           
-#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)                                           
-#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)                                            
-#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
-#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
-#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
-#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)                                            
-#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
-#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
-#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
-#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)                                            
-#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
-#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
-#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
-#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)                                           
-#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
-#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
-#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
-#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)                                           
-#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
-#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
-#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
-#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)                                           
-#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
-#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
-#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
-#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)                                           
-#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
-#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
-#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
-#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)                                            
-#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)                                            
-#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)                                            
-#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)                                            
-#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)                                            
-#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)                                            
-#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)                                            
-#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)                                            
-#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)                                            
-#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)                                           
-#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)                                           
-#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
-#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)                                            
-#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)                                            
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)                                            
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)                                            
-#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)                                            
-#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)                                            
-#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)                                           
-#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)                                           
-#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)                                           
-#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)                                           
-#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)                                           
-#define EXTI_IMR_IM0_Msk        (0x1U << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)                                           
-#define EXTI_IMR_IM1_Msk        (0x1U << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)                                           
-#define EXTI_IMR_IM2_Msk        (0x1U << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)                                           
-#define EXTI_IMR_IM3_Msk        (0x1U << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)                                           
-#define EXTI_IMR_IM4_Msk        (0x1U << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)                                           
-#define EXTI_IMR_IM5_Msk        (0x1U << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)                                           
-#define EXTI_IMR_IM6_Msk        (0x1U << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)                                           
-#define EXTI_IMR_IM7_Msk        (0x1U << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)                                           
-#define EXTI_IMR_IM8_Msk        (0x1U << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)                                           
-#define EXTI_IMR_IM9_Msk        (0x1U << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)                                          
-#define EXTI_IMR_IM10_Msk       (0x1U << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)                                          
-#define EXTI_IMR_IM11_Msk       (0x1U << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)                                          
-#define EXTI_IMR_IM12_Msk       (0x1U << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)                                          
-#define EXTI_IMR_IM13_Msk       (0x1U << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)                                          
-#define EXTI_IMR_IM14_Msk       (0x1U << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)                                          
-#define EXTI_IMR_IM15_Msk       (0x1U << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)                                          
-#define EXTI_IMR_IM16_Msk       (0x1U << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)                                          
-#define EXTI_IMR_IM17_Msk       (0x1U << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)                                          
-#define EXTI_IMR_IM18_Msk       (0x1U << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)                                          
-#define EXTI_IMR_IM19_Msk       (0x1U << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)                                          
-#define EXTI_IMR_IM20_Msk       (0x1U << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)                                          
-#define EXTI_IMR_IM21_Msk       (0x1U << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)                                          
-#define EXTI_IMR_IM22_Msk       (0x1U << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)                                          
-#define EXTI_IMR_IM23_Msk       (0x1U << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)                                          
-#define EXTI_IMR_IM25_Msk       (0x1U << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)                                          
-#define EXTI_IMR_IM26_Msk       (0x1U << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)                                          
-#define EXTI_IMR_IM28_Msk       (0x1U << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)                                          
-#define EXTI_IMR_IM29_Msk       (0x1U << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)                                           
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)                                           
-#define EXTI_EMR_EM0_Msk        (0x1U << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)                                           
-#define EXTI_EMR_EM1_Msk        (0x1U << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)                                           
-#define EXTI_EMR_EM2_Msk        (0x1U << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)                                           
-#define EXTI_EMR_EM3_Msk        (0x1U << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)                                           
-#define EXTI_EMR_EM4_Msk        (0x1U << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)                                           
-#define EXTI_EMR_EM5_Msk        (0x1U << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)                                           
-#define EXTI_EMR_EM6_Msk        (0x1U << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)                                           
-#define EXTI_EMR_EM7_Msk        (0x1U << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)                                           
-#define EXTI_EMR_EM8_Msk        (0x1U << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)                                           
-#define EXTI_EMR_EM9_Msk        (0x1U << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)                                          
-#define EXTI_EMR_EM10_Msk       (0x1U << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)                                          
-#define EXTI_EMR_EM11_Msk       (0x1U << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)                                          
-#define EXTI_EMR_EM12_Msk       (0x1U << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)                                          
-#define EXTI_EMR_EM13_Msk       (0x1U << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)                                          
-#define EXTI_EMR_EM14_Msk       (0x1U << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)                                          
-#define EXTI_EMR_EM15_Msk       (0x1U << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)                                          
-#define EXTI_EMR_EM16_Msk       (0x1U << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)                                          
-#define EXTI_EMR_EM17_Msk       (0x1U << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)                                          
-#define EXTI_EMR_EM18_Msk       (0x1U << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)                                          
-#define EXTI_EMR_EM19_Msk       (0x1U << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)                                          
-#define EXTI_EMR_EM20_Msk       (0x1U << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)                                          
-#define EXTI_EMR_EM21_Msk       (0x1U << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)                                          
-#define EXTI_EMR_EM22_Msk       (0x1U << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)                                          
-#define EXTI_EMR_EM23_Msk       (0x1U << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)                                          
-#define EXTI_EMR_EM25_Msk       (0x1U << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)                                          
-#define EXTI_EMR_EM26_Msk       (0x1U << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)                                          
-#define EXTI_EMR_EM28_Msk       (0x1U << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)                                          
-#define EXTI_EMR_EM29_Msk       (0x1U << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)                                           
-#define EXTI_RTSR_RT0_Msk       (0x1U << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)                                           
-#define EXTI_RTSR_RT1_Msk       (0x1U << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)                                           
-#define EXTI_RTSR_RT2_Msk       (0x1U << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)                                           
-#define EXTI_RTSR_RT3_Msk       (0x1U << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)                                           
-#define EXTI_RTSR_RT4_Msk       (0x1U << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)                                           
-#define EXTI_RTSR_RT5_Msk       (0x1U << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)                                           
-#define EXTI_RTSR_RT6_Msk       (0x1U << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)                                           
-#define EXTI_RTSR_RT7_Msk       (0x1U << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)                                           
-#define EXTI_RTSR_RT8_Msk       (0x1U << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)                                           
-#define EXTI_RTSR_RT9_Msk       (0x1U << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)                                          
-#define EXTI_RTSR_RT10_Msk      (0x1U << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)                                          
-#define EXTI_RTSR_RT11_Msk      (0x1U << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)                                          
-#define EXTI_RTSR_RT12_Msk      (0x1U << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)                                          
-#define EXTI_RTSR_RT13_Msk      (0x1U << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)                                          
-#define EXTI_RTSR_RT14_Msk      (0x1U << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)                                          
-#define EXTI_RTSR_RT15_Msk      (0x1U << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)                                          
-#define EXTI_RTSR_RT16_Msk      (0x1U << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)                                          
-#define EXTI_RTSR_RT17_Msk      (0x1U << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)                                          
-#define EXTI_RTSR_RT19_Msk      (0x1U << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)                                          
-#define EXTI_RTSR_RT20_Msk      (0x1U << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)                                          
-#define EXTI_RTSR_RT21_Msk      (0x1U << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)                                          
-#define EXTI_RTSR_RT22_Msk      (0x1U << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)                                           
-#define EXTI_FTSR_FT0_Msk       (0x1U << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)                                           
-#define EXTI_FTSR_FT1_Msk       (0x1U << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)                                           
-#define EXTI_FTSR_FT2_Msk       (0x1U << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)                                           
-#define EXTI_FTSR_FT3_Msk       (0x1U << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)                                           
-#define EXTI_FTSR_FT4_Msk       (0x1U << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)                                           
-#define EXTI_FTSR_FT5_Msk       (0x1U << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)                                           
-#define EXTI_FTSR_FT6_Msk       (0x1U << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)                                           
-#define EXTI_FTSR_FT7_Msk       (0x1U << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)                                           
-#define EXTI_FTSR_FT8_Msk       (0x1U << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)                                           
-#define EXTI_FTSR_FT9_Msk       (0x1U << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)                                          
-#define EXTI_FTSR_FT10_Msk      (0x1U << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)                                          
-#define EXTI_FTSR_FT11_Msk      (0x1U << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)                                          
-#define EXTI_FTSR_FT12_Msk      (0x1U << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)                                          
-#define EXTI_FTSR_FT13_Msk      (0x1U << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)                                          
-#define EXTI_FTSR_FT14_Msk      (0x1U << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)                                          
-#define EXTI_FTSR_FT15_Msk      (0x1U << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)                                          
-#define EXTI_FTSR_FT16_Msk      (0x1U << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)                                          
-#define EXTI_FTSR_FT17_Msk      (0x1U << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)                                          
-#define EXTI_FTSR_FT19_Msk      (0x1U << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)                                          
-#define EXTI_FTSR_FT20_Msk      (0x1U << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)                                          
-#define EXTI_FTSR_FT21_Msk      (0x1U << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)                                          
-#define EXTI_FTSR_FT22_Msk      (0x1U << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)                                           
-#define EXTI_SWIER_SWI0_Msk     (0x1U << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)                                           
-#define EXTI_SWIER_SWI1_Msk     (0x1U << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)                                           
-#define EXTI_SWIER_SWI2_Msk     (0x1U << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)                                           
-#define EXTI_SWIER_SWI3_Msk     (0x1U << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)                                           
-#define EXTI_SWIER_SWI4_Msk     (0x1U << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)                                           
-#define EXTI_SWIER_SWI5_Msk     (0x1U << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)                                           
-#define EXTI_SWIER_SWI6_Msk     (0x1U << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)                                           
-#define EXTI_SWIER_SWI7_Msk     (0x1U << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)                                           
-#define EXTI_SWIER_SWI8_Msk     (0x1U << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)                                           
-#define EXTI_SWIER_SWI9_Msk     (0x1U << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)                                          
-#define EXTI_SWIER_SWI10_Msk    (0x1U << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)                                          
-#define EXTI_SWIER_SWI11_Msk    (0x1U << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)                                          
-#define EXTI_SWIER_SWI12_Msk    (0x1U << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)                                          
-#define EXTI_SWIER_SWI13_Msk    (0x1U << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)                                          
-#define EXTI_SWIER_SWI14_Msk    (0x1U << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)                                          
-#define EXTI_SWIER_SWI15_Msk    (0x1U << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)                                          
-#define EXTI_SWIER_SWI16_Msk    (0x1U << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)                                          
-#define EXTI_SWIER_SWI17_Msk    (0x1U << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)                                          
-#define EXTI_SWIER_SWI19_Msk    (0x1U << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)                                          
-#define EXTI_SWIER_SWI20_Msk    (0x1U << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)                                          
-#define EXTI_SWIER_SWI21_Msk    (0x1U << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)                                          
-#define EXTI_SWIER_SWI22_Msk    (0x1U << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)                                           
-#define EXTI_PR_PIF0_Msk        (0x1U << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)                                           
-#define EXTI_PR_PIF1_Msk        (0x1U << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)                                           
-#define EXTI_PR_PIF2_Msk        (0x1U << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)                                           
-#define EXTI_PR_PIF3_Msk        (0x1U << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)                                           
-#define EXTI_PR_PIF4_Msk        (0x1U << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)                                           
-#define EXTI_PR_PIF5_Msk        (0x1U << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)                                           
-#define EXTI_PR_PIF6_Msk        (0x1U << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)                                           
-#define EXTI_PR_PIF7_Msk        (0x1U << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)                                           
-#define EXTI_PR_PIF8_Msk        (0x1U << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)                                           
-#define EXTI_PR_PIF9_Msk        (0x1U << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)                                          
-#define EXTI_PR_PIF10_Msk       (0x1U << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)                                          
-#define EXTI_PR_PIF11_Msk       (0x1U << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)                                          
-#define EXTI_PR_PIF12_Msk       (0x1U << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)                                          
-#define EXTI_PR_PIF13_Msk       (0x1U << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)                                          
-#define EXTI_PR_PIF14_Msk       (0x1U << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)                                          
-#define EXTI_PR_PIF15_Msk       (0x1U << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)                                          
-#define EXTI_PR_PIF16_Msk       (0x1U << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)                                          
-#define EXTI_PR_PIF17_Msk       (0x1U << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)                                          
-#define EXTI_PR_PIF19_Msk       (0x1U << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)                                          
-#define EXTI_PR_PIF20_Msk       (0x1U << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)                                          
-#define EXTI_PR_PIF21_Msk       (0x1U << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)                                          
-#define EXTI_PR_PIF22_Msk       (0x1U << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)                                      
-#define FLASH_ACR_LATENCY_Msk        (0x1U << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)                                      
-#define FLASH_ACR_PRFTEN_Msk         (0x1U << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)                                      
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1U << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)                                      
-#define FLASH_ACR_RUN_PD_Msk         (0x1U << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)                                      
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1U << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)                                      
-#define FLASH_ACR_PRE_READ_Msk       (0x1U << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)                                      
-#define FLASH_PECR_PELOCK_Msk        (0x1U << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)                                      
-#define FLASH_PECR_PRGLOCK_Msk       (0x1U << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)                                      
-#define FLASH_PECR_OPTLOCK_Msk       (0x1U << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)                                      
-#define FLASH_PECR_PROG_Msk          (0x1U << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)                                      
-#define FLASH_PECR_DATA_Msk          (0x1U << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)                                      
-#define FLASH_PECR_FIX_Msk           (0x1U << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)                                      
-#define FLASH_PECR_ERASE_Msk         (0x1U << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)                                     
-#define FLASH_PECR_FPRG_Msk          (0x1U << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)                                     
-#define FLASH_PECR_EOPIE_Msk         (0x1U << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)                                     
-#define FLASH_PECR_ERRIE_Msk         (0x1U << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)                                     
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1U << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)                                     
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1U << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)                                      
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)                                      
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)                                      
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)                                      
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)                                      
-#define FLASH_SR_BSY_Msk             (0x1U << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)                                      
-#define FLASH_SR_EOP_Msk             (0x1U << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)                                      
-#define FLASH_SR_HVOFF_Msk           (0x1U << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)                                      
-#define FLASH_SR_READY_Msk           (0x1U << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)                                      
-#define FLASH_SR_WRPERR_Msk          (0x1U << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)                                      
-#define FLASH_SR_PGAERR_Msk          (0x1U << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)                                     
-#define FLASH_SR_SIZERR_Msk          (0x1U << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)                                     
-#define FLASH_SR_OPTVERR_Msk         (0x1U << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)                                     
-#define FLASH_SR_RDERR_Msk           (0x1U << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)                                     
-#define FLASH_SR_NOTZEROERR_Msk      (0x1U << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)                                     
-#define FLASH_SR_FWWERR_Msk          (0x1U << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)                                      
-#define FLASH_OPTR_RDPROT_Msk        (0xFFU << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)                                      
-#define FLASH_OPTR_WPRMOD_Msk        (0x1U << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)                                     
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFU << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)                                     
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1U << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)                                     
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1U << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)                                     
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1U << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)                                     
-#define FLASH_OPTR_USER_Msk          (0x7U << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)                                     
-#define FLASH_OPTR_BOOT1_Msk         (0x1U << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)                                      
-#define FLASH_WRPR_WRP_Msk           (0xFFFFU << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)                                   
-#define GPIO_MODER_MODE0_Msk            (0x3U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)                                   
-#define GPIO_MODER_MODE1_Msk            (0x3U << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)                                   
-#define GPIO_MODER_MODE2_Msk            (0x3U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)                                   
-#define GPIO_MODER_MODE3_Msk            (0x3U << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)                                   
-#define GPIO_MODER_MODE4_Msk            (0x3U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U)                                  
-#define GPIO_MODER_MODE5_Msk            (0x3U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U)                                  
-#define GPIO_MODER_MODE6_Msk            (0x3U << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1U << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2U << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U)                                  
-#define GPIO_MODER_MODE7_Msk            (0x3U << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1U << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2U << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U)                                  
-#define GPIO_MODER_MODE8_Msk            (0x3U << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1U << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2U << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U)                                  
-#define GPIO_MODER_MODE9_Msk            (0x3U << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1U << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2U << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U)                                  
-#define GPIO_MODER_MODE10_Msk           (0x3U << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1U << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2U << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U)                                  
-#define GPIO_MODER_MODE11_Msk           (0x3U << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1U << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2U << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U)                                  
-#define GPIO_MODER_MODE12_Msk           (0x3U << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1U << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2U << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U)                                  
-#define GPIO_MODER_MODE13_Msk           (0x3U << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1U << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2U << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U)                                  
-#define GPIO_MODER_MODE14_Msk           (0x3U << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1U << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2U << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U)                                  
-#define GPIO_MODER_MODE15_Msk           (0x3U << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1U << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2U << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)                                   
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)                                   
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)                                   
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)                                   
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)                                   
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U)                                  
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U)                                  
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U)                                  
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U)                                  
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U)                                  
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U)                                  
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U)                                  
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U)                                  
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U)                                  
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U)                                  
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U)                                  
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)                                   
-#define GPIO_PUPDR_PUPD0_Msk            (0x3U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)                                   
-#define GPIO_PUPDR_PUPD1_Msk            (0x3U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)                                   
-#define GPIO_PUPDR_PUPD2_Msk            (0x3U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)                                   
-#define GPIO_PUPDR_PUPD3_Msk            (0x3U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)                                   
-#define GPIO_PUPDR_PUPD4_Msk            (0x3U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U)                                  
-#define GPIO_PUPDR_PUPD5_Msk            (0x3U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U)                                  
-#define GPIO_PUPDR_PUPD6_Msk            (0x3U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U)                                  
-#define GPIO_PUPDR_PUPD7_Msk            (0x3U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U)                                  
-#define GPIO_PUPDR_PUPD8_Msk            (0x3U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U)                                  
-#define GPIO_PUPDR_PUPD9_Msk            (0x3U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U)                                  
-#define GPIO_PUPDR_PUPD10_Msk           (0x3U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U)                                  
-#define GPIO_PUPDR_PUPD11_Msk           (0x3U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U)                                  
-#define GPIO_PUPDR_PUPD12_Msk           (0x3U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U)                                  
-#define GPIO_PUPDR_PUPD13_Msk           (0x3U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U)                                  
-#define GPIO_PUPDR_PUPD14_Msk           (0x3U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U)                                  
-#define GPIO_PUPDR_PUPD15_Msk           (0x3U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)                                   
-#define GPIO_IDR_ID0_Msk                (0x1U << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)                                   
-#define GPIO_IDR_ID1_Msk                (0x1U << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)                                   
-#define GPIO_IDR_ID2_Msk                (0x1U << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)                                   
-#define GPIO_IDR_ID3_Msk                (0x1U << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)                                   
-#define GPIO_IDR_ID4_Msk                (0x1U << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)                                   
-#define GPIO_IDR_ID5_Msk                (0x1U << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)                                   
-#define GPIO_IDR_ID6_Msk                (0x1U << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)                                   
-#define GPIO_IDR_ID7_Msk                (0x1U << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)                                   
-#define GPIO_IDR_ID8_Msk                (0x1U << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)                                   
-#define GPIO_IDR_ID9_Msk                (0x1U << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U)                                  
-#define GPIO_IDR_ID10_Msk               (0x1U << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U)                                  
-#define GPIO_IDR_ID11_Msk               (0x1U << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U)                                  
-#define GPIO_IDR_ID12_Msk               (0x1U << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U)                                  
-#define GPIO_IDR_ID13_Msk               (0x1U << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U)                                  
-#define GPIO_IDR_ID14_Msk               (0x1U << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U)                                  
-#define GPIO_IDR_ID15_Msk               (0x1U << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)                                   
-#define GPIO_ODR_OD0_Msk                (0x1U << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)                                   
-#define GPIO_ODR_OD1_Msk                (0x1U << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)                                   
-#define GPIO_ODR_OD2_Msk                (0x1U << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)                                   
-#define GPIO_ODR_OD3_Msk                (0x1U << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)                                   
-#define GPIO_ODR_OD4_Msk                (0x1U << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)                                   
-#define GPIO_ODR_OD5_Msk                (0x1U << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)                                   
-#define GPIO_ODR_OD6_Msk                (0x1U << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)                                   
-#define GPIO_ODR_OD7_Msk                (0x1U << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)                                   
-#define GPIO_ODR_OD8_Msk                (0x1U << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)                                   
-#define GPIO_ODR_OD9_Msk                (0x1U << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U)                                  
-#define GPIO_ODR_OD10_Msk               (0x1U << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U)                                  
-#define GPIO_ODR_OD11_Msk               (0x1U << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U)                                  
-#define GPIO_ODR_OD12_Msk               (0x1U << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U)                                  
-#define GPIO_ODR_OD13_Msk               (0x1U << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U)                                  
-#define GPIO_ODR_OD14_Msk               (0x1U << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U)                                  
-#define GPIO_ODR_OD15_Msk               (0x1U << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)                                   
-#define GPIO_LCKR_LCK0_Msk              (0x1U << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)                                   
-#define GPIO_LCKR_LCK1_Msk              (0x1U << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)                                   
-#define GPIO_LCKR_LCK2_Msk              (0x1U << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)                                   
-#define GPIO_LCKR_LCK3_Msk              (0x1U << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)                                   
-#define GPIO_LCKR_LCK4_Msk              (0x1U << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)                                   
-#define GPIO_LCKR_LCK5_Msk              (0x1U << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)                                   
-#define GPIO_LCKR_LCK6_Msk              (0x1U << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)                                   
-#define GPIO_LCKR_LCK7_Msk              (0x1U << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)                                   
-#define GPIO_LCKR_LCK8_Msk              (0x1U << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)                                   
-#define GPIO_LCKR_LCK9_Msk              (0x1U << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U)                                  
-#define GPIO_LCKR_LCK10_Msk             (0x1U << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U)                                  
-#define GPIO_LCKR_LCK11_Msk             (0x1U << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U)                                  
-#define GPIO_LCKR_LCK12_Msk             (0x1U << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U)                                  
-#define GPIO_LCKR_LCK13_Msk             (0x1U << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U)                                  
-#define GPIO_LCKR_LCK14_Msk             (0x1U << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U)                                  
-#define GPIO_LCKR_LCK15_Msk             (0x1U << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U)                                  
-#define GPIO_LCKR_LCKK_Msk              (0x1U << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)                                      
-#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)                                      
-#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)                                      
-#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)                                      
-#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)                                      
-#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)                                      
-#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)                                      
-#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)                                      
-#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)                                      
-#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)                                     
-#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
-#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
-#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)                                     
-#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
-#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)                                     
-#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)                                     
-#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)                                     
-#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)                                     
-#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)                                     
-#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)                                     
-#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)                                      
-#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)                                     
-#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)                                     
-#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)                                     
-#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)                                     
-#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)                                     
-#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)                                     
-#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)                                     
-#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)                                     
-#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)                                     
-#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)                                     
-#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)                                      
-#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
-#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)                                     
-#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)                                      
-#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
-#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
-#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
-#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
-#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)                                     
-#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
-#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
-#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
-#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
-#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)                                      
-#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)                                      
-#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)                                      
-#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)                                      
-#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)                                      
-#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)                                      
-#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)                                      
-#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)                                      
-#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)                                      
-#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)                                      
-#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)                                     
-#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)                                     
-#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
-#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)                                     
-#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)                                     
-#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)                                     
-#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)                                     
-#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)                                      
-#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)                                      
-#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)                                      
-#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)                                      
-#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)                                      
-#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)                                     
-#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)                                     
-#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
-#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)                                     
-#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)                                      
-#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)                                      
-#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)                                      
-#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)                                              
-#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)                                              
-#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)                                              
-#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)                                              
-#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)                                              
-#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)                                              
-#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)                                              
-#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)                                       
-#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)                                       
-#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)                                       
-#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)                                       
-#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)                                       
-#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)                                       
-#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)                                       
-#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)                                       
-#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)                                       
-#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)                                       
-#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)                                      
-#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)                                      
-#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)                                      
-#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)                                      
-#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)                                      
-#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)                                       
-#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)                                       
-#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)                                       
-#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)                                       
-#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)                                       
-#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)                                       
-#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)                                       
-#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)                                       
-#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)                                       
-#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)                                       
-#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
-#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)                                       
-#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)                                       
-#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)                                       
-#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
-#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
-#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
-#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)                                       
-#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
-#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
-#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
-#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
-#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
-#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)                                       
-#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
-#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
-#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
-#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
-#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
-#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
-#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)                                      
-#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)                                       
-#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
-#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
-#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)                                       
-#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)                                       
-#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)                                       
-#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)                                              
-#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)                                              
-#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)                                              
-#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)                                              
-#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)                                              
-#define FW_VDSSA_ADD_Msk     (0x3FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)                                              
-#define FW_VDSL_LENG_Msk     (0x3FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)                                              
-#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)                                              
-#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)                                              
-#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)                                        
-#define PWR_CR_LPSDSR_Msk          (0x1U << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)                                        
-#define PWR_CR_PDDS_Msk            (0x1U << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)                                        
-#define PWR_CR_CWUF_Msk            (0x1U << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)                                        
-#define PWR_CR_CSBF_Msk            (0x1U << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)                                        
-#define PWR_CR_PVDE_Msk            (0x1U << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)                                        
-#define PWR_CR_PLS_Msk             (0x7U << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1U << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2U << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4U << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)                                        
-#define PWR_CR_DBP_Msk             (0x1U << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)                                        
-#define PWR_CR_ULP_Msk             (0x1U << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)                                       
-#define PWR_CR_FWU_Msk             (0x1U << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)                                       
-#define PWR_CR_VOS_Msk             (0x3U << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1U << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2U << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)                                       
-#define PWR_CR_DSEEKOFF_Msk        (0x1U << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)                                       
-#define PWR_CR_LPRUN_Msk           (0x1U << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)                                        
-#define PWR_CSR_WUF_Msk            (0x1U << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)                                        
-#define PWR_CSR_SBF_Msk            (0x1U << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)                                        
-#define PWR_CSR_PVDO_Msk           (0x1U << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)                                        
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1U << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)                                        
-#define PWR_CSR_VOSF_Msk           (0x1U << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)                                        
-#define PWR_CSR_REGLPF_Msk         (0x1U << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)                                        
-#define PWR_CSR_EWUP1_Msk          (0x1U << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)                                        
-#define PWR_CSR_EWUP2_Msk          (0x1U << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U)                                  
-#define RCC_CR_HSION_Msk                 (0x1U << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U)                                  
-#define RCC_CR_HSIKERON_Msk              (0x1U << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U)                                  
-#define RCC_CR_HSIRDY_Msk                (0x1U << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U)                                  
-#define RCC_CR_HSIDIVEN_Msk              (0x1U << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U)                                  
-#define RCC_CR_HSIDIVF_Msk               (0x1U << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U)                                  
-#define RCC_CR_MSION_Msk                 (0x1U << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U)                                  
-#define RCC_CR_MSIRDY_Msk                (0x1U << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)                                 
-#define RCC_CR_HSEON_Msk                 (0x1U << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)                                 
-#define RCC_CR_HSERDY_Msk                (0x1U << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)                                 
-#define RCC_CR_HSEBYP_Msk                (0x1U << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)                                 
-#define RCC_CR_CSSHSEON_Msk              (0x1U << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)                                 
-#define RCC_CR_RTCPRE_Msk                (0x3U << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1U << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2U << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)                                 
-#define RCC_CR_PLLON_Msk                 (0x1U << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)                                 
-#define RCC_CR_PLLRDY_Msk                (0x1U << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U)                                  
-#define RCC_ICSCR_HSICAL_Msk             (0xFFU << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U)                                  
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FU << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)                                 
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)                                 
-#define RCC_ICSCR_MSICAL_Msk             (0xFFU << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)                                 
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFU << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U)                                  
-#define RCC_CRRCR_HSI48ON_Msk            (0x1U << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U)                                  
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1U << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U)                                  
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFU << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFU << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1U << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1U << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3U << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U)                                  
-#define RCC_CIER_LSIRDYIE_Msk            (0x1U << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U)                                  
-#define RCC_CIER_LSERDYIE_Msk            (0x1U << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U)                                  
-#define RCC_CIER_HSIRDYIE_Msk            (0x1U << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U)                                  
-#define RCC_CIER_HSERDYIE_Msk            (0x1U << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U)                                  
-#define RCC_CIER_PLLRDYIE_Msk            (0x1U << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U)                                  
-#define RCC_CIER_MSIRDYIE_Msk            (0x1U << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U)                                  
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1U << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U)                                  
-#define RCC_CIER_CSSLSE_Msk              (0x1U << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U)                                  
-#define RCC_CIFR_LSIRDYF_Msk             (0x1U << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U)                                  
-#define RCC_CIFR_LSERDYF_Msk             (0x1U << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U)                                  
-#define RCC_CIFR_HSIRDYF_Msk             (0x1U << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U)                                  
-#define RCC_CIFR_HSERDYF_Msk             (0x1U << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U)                                  
-#define RCC_CIFR_PLLRDYF_Msk             (0x1U << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U)                                  
-#define RCC_CIFR_MSIRDYF_Msk             (0x1U << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U)                                  
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1U << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U)                                  
-#define RCC_CIFR_CSSLSEF_Msk             (0x1U << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U)                                  
-#define RCC_CIFR_CSSHSEF_Msk             (0x1U << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U)                                  
-#define RCC_CICR_LSIRDYC_Msk             (0x1U << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U)                                  
-#define RCC_CICR_LSERDYC_Msk             (0x1U << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U)                                  
-#define RCC_CICR_HSIRDYC_Msk             (0x1U << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U)                                  
-#define RCC_CICR_HSERDYC_Msk             (0x1U << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U)                                  
-#define RCC_CICR_PLLRDYC_Msk             (0x1U << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U)                                  
-#define RCC_CICR_MSIRDYC_Msk             (0x1U << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U)                                  
-#define RCC_CICR_HSI48RDYC_Msk           (0x1U << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U)                                  
-#define RCC_CICR_CSSLSEC_Msk             (0x1U << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U)                                  
-#define RCC_CICR_CSSHSEC_Msk             (0x1U << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U)                                  
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1U << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U)                                  
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1U << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U)                                  
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1U << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U)                                  
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1U << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U)                                  
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1U << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U)                                  
-#define RCC_AHBRSTR_DMARST_Msk           (0x1U << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U)                                  
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1U << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)                                 
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1U << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)                                 
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1U << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)                                 
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1U << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U)                                  
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U)                                  
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1U << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U)                                  
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1U << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U)                                  
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1U << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)                                 
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1U << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)                                 
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1U << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)                                 
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1U << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU clock reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)                                  
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1U << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)                                  
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1U << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)                                  
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1U << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)                                 
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1U << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)                                 
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1U << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)                                 
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1U << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)                                 
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)                                 
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1U << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)                                 
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1U << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)                                 
-#define RCC_APB1RSTR_USBRST_Msk          (0x1U << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)                                 
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1U << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)                                 
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1U << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)                                 
-#define RCC_APB1RSTR_DACRST_Msk          (0x1U << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC clock reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)                                 
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 clock reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U)                                  
-#define RCC_IOPENR_IOPAEN_Msk            (0x1U << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U)                                  
-#define RCC_IOPENR_IOPBEN_Msk            (0x1U << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U)                                  
-#define RCC_IOPENR_IOPCEN_Msk            (0x1U << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U)                                  
-#define RCC_IOPENR_IOPDEN_Msk            (0x1U << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U)                                  
-#define RCC_IOPENR_IOPHEN_Msk            (0x1U << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U)                                  
-#define RCC_AHBENR_DMAEN_Msk             (0x1U << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U)                                  
-#define RCC_AHBENR_MIFEN_Msk             (0x1U << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)                                 
-#define RCC_AHBENR_CRCEN_Msk             (0x1U << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)                                 
-#define RCC_AHBENR_TSCEN_Msk             (0x1U << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)                                 
-#define RCC_AHBENR_RNGEN_Msk             (0x1U << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U)                                  
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U)                                  
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1U << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U)                                  
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1U << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U)                                  
-#define RCC_APB2ENR_FWEN_Msk             (0x1U << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U)                                  
-#define RCC_APB2ENR_ADCEN_Msk            (0x1U << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)                                 
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1U << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)                                 
-#define RCC_APB2ENR_USART1EN_Msk         (0x1U << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)                                 
-#define RCC_APB2ENR_DBGEN_Msk            (0x1U << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U)                                  
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1U << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U)                                  
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1U << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U)                                  
-#define RCC_APB1ENR_LCDEN_Msk            (0x1U << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)                                 
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1U << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)                                 
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1U << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)                                 
-#define RCC_APB1ENR_USART2EN_Msk         (0x1U << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)                                 
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1U << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)                                 
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1U << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)                                 
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1U << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)                                 
-#define RCC_APB1ENR_USBEN_Msk            (0x1U << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)                                 
-#define RCC_APB1ENR_CRSEN_Msk            (0x1U << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)                                 
-#define RCC_APB1ENR_PWREN_Msk            (0x1U << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)                                 
-#define RCC_APB1ENR_DACEN_Msk            (0x1U << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)                                 
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U)                                  
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1U << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U)                                  
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U)                                  
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U)                                  
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U)                                  
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U)                                  
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1U << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U)                                  
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1U << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)                                  
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)                                 
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1U << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)                                 
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1U << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)                                 
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1U << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U)                                  
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U)                                  
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U)                                  
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U)                                  
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1U << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)                                 
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)                                 
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)                                 
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1U << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U)                                  
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U)                                  
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U)                                  
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1U << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)                                 
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)                                 
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)                                 
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)                                 
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)                                 
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)                                 
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)                                 
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1U << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)                                 
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1U << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)                                 
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1U << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)                                 
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1U << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)                                 
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U)                                  
-#define RCC_CCIPR_USART1SEL_Msk          (0x3U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U)                                  
-#define RCC_CCIPR_USART2SEL_Msk          (0x3U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)                                 
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)                                 
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)                                 
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)                                 
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1U << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U)                                  
-#define RCC_CSR_LSION_Msk                (0x1U << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U)                                  
-#define RCC_CSR_LSIRDY_Msk               (0x1U << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U)                                  
-#define RCC_CSR_LSEON_Msk                (0x1U << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U)                                  
-#define RCC_CSR_LSERDY_Msk               (0x1U << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)                                 
-#define RCC_CSR_LSEBYP_Msk               (0x1U << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)                                 
-#define RCC_CSR_LSEDRV_Msk               (0x3U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)                                 
-#define RCC_CSR_LSECSSON_Msk             (0x1U << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)                                 
-#define RCC_CSR_LSECSSD_Msk              (0x1U << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)                                 
-#define RCC_CSR_RTCSEL_Msk               (0x3U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)                                 
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1U << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)                                 
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1U << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)                                 
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3U << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)                                 
-#define RCC_CSR_RTCEN_Msk                (0x1U << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)                                 
-#define RCC_CSR_RTCRST_Msk               (0x1U << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)                                 
-#define RCC_CSR_RMVF_Msk                 (0x1U << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)                                 
-#define RCC_CSR_FWRSTF_Msk               (0x1U << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)                                 
-#define RCC_CSR_OBLRSTF_Msk              (0x1U << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)                                 
-#define RCC_CSR_PINRSTF_Msk              (0x1U << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)                                 
-#define RCC_CSR_PORRSTF_Msk              (0x1U << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)                                 
-#define RCC_CSR_SFTRSTF_Msk              (0x1U << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)                                 
-#define RCC_CSR_IWDGRSTF_Msk             (0x1U << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)                                 
-#define RCC_CSR_WWDGRSTF_Msk             (0x1U << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)                                 
-#define RCC_CSR_LPWRRSTF_Msk             (0x1U << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)                                               
-#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)                                               
-#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)                                               
-#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)                                               
-#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)                                               
-#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)                                               
-#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)                                               
-#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)                                   
-#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)                                   
-#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)                                   
-#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)                                   
-#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)                                    
-#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)                                    
-#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)                                    
-#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)                                   
-#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)                                   
-#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)                                   
-#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)                                   
-#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)                                    
-#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)                                    
-#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)                                    
-#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)                                   
-#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)                                   
-#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)                                   
-#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)                                   
-#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BCK_Pos                 (18U)                                   
-#define RTC_CR_BCK_Msk                 (0x1U << RTC_CR_BCK_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BCK                     RTC_CR_BCK_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)                                   
-#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)                                   
-#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)                                   
-#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)                                   
-#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)                                   
-#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)                                   
-#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)                                   
-#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)                                   
-#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)                                    
-#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)                                    
-#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)                                    
-#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)                                    
-#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)                                    
-#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)                                    
-#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)                                    
-#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)                                   
-#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)                                   
-#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)                                   
-#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)                                   
-#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)                                   
-#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)                                   
-#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)                                    
-#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)                                    
-#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)                                    
-#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)                                    
-#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)                                    
-#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)                                    
-#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)                                    
-#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)                                    
-#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)                                    
-#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)                                    
-#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
-#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)                                    
-#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
-#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
-#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)                                   
-#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)                                   
-#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
-#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)                                   
-#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)                                   
-#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)                                   
-#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
-#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)                                   
-#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)                                    
-#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
-#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)                                    
-#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)                                    
-#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
-#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
-#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)                                   
-#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)                                   
-#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
-#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)                                   
-#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)                                   
-#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)                                   
-#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
-#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)                                   
-#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)                                    
-#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
-#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)                                    
-#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)                                    
-#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)                                    
-#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)                                    
-#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
-#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)                                   
-#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)                                   
-#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)                                   
-#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)                                   
-#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)                                    
-#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)                                    
-#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)                                    
-#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)                                   
-#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)                                   
-#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)                                    
-#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)                                    
-#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)                                    
-#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)                                    
-#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)                                   
-#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)                                   
-#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)                                   
-#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)                                    
-#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)                                    
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)                                    
-#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)                                    
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)                                    
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)                                    
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)                                    
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)                                    
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)                                       
-#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)                                       
-#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)                                       
-#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)                                       
-#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)                                       
-#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
-#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)                                       
-#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)                                       
-#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)                                      
-#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)                                      
-#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
-#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)                                      
-#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)                                      
-#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
-#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
-#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
-#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)                                       
-#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)                                       
-#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)                                       
-#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)                                       
-#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)                                       
-#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)                                       
-#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)                                       
-#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)                                       
-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)                                       
-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)                                       
-#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)                                       
-#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)                                       
-#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)                                       
-#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)                                       
-#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)                                       
-#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
-#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)                                       
-#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
-#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x7U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x1U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x2U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x4U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
-    || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#endif	
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)                                         
-#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)                                         
-#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)                                         
-#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)                                         
-#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)                                         
-#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)                                         
-#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)                                         
-#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)                                         
-#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)                                         
-#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)                                         
-#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)                                         
-#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)                                         
-#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)                                         
-#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)                                         
-#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)                                         
-#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)                                         
-#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)                                        
-#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)                                        
-#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)                                        
-#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)                                         
-#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)                                         
-#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)                                         
-#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)                                         
-#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)                                         
-#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)                                         
-#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)                                         
-#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)                                         
-#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)                                        
-#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)                                        
-#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)                                        
-#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)                                        
-#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)                                         
-#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)                                         
-#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)                                         
-#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)                                         
-#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)                                         
-#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)                                         
-#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)                                         
-#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)                                        
-#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)                                        
-#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)                                        
-#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)                                         
-#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)                                         
-#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)                                         
-#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)                                         
-#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)                                         
-#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)                                         
-#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)                                         
-#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
-#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
-#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)                                         
-#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
-#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)                                         
-#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
-#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
-#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)                                        
-#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
-#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
-#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)                                         
-#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
-#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)                                        
-#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)                                         
-#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
-#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
-#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)                                         
-#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
-#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)                                         
-#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
-#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
-#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)                                        
-#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
-#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
-#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)                                         
-#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
-#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)                                        
-#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)                                         
-#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)                                         
-#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)                                         
-#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)                                         
-#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)                                         
-#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)                                         
-#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)                                         
-#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)                                         
-#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)                                        
-#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)                                        
-#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)                                        
-#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)                                        
-#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)                                         
-#define TIM_CNT_CNT_Msk           (0xFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)                                         
-#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)                                         
-#define TIM_ARR_ARR_Msk           (0xFFFFU << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)                                         
-#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)                                         
-#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)                                         
-#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)                                         
-#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)                                         
-#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)                                         
-#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)                                         
-#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)                                          
-#define TIM2_OR_ETR_RMP_Msk      (0x7U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)                                          
-#define TIM2_OR_TI4_RMP_Msk      (0x3U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)                                         
-#define TIM21_OR_ETR_RMP_Msk      (0x3U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)                                         
-#define TIM21_OR_TI1_RMP_Msk      (0x7U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)                                         
-#define TIM21_OR_TI2_RMP_Msk      (0x1U << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)                                         
-#define TIM22_OR_ETR_RMP_Msk      (0x3U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)                                         
-#define TIM22_OR_TI1_RMP_Msk      (0x3U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)                                          
-#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)                                          
-#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)                                          
-#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)                                          
-#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)                                          
-#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)                                          
-#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)                                         
-#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)                                         
-#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)                                         
-#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)                                         
-#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)                                         
-#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)                                         
-#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)                                          
-#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)                                          
-#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)                                          
-#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)                                          
-#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)                                          
-#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)                                          
-#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
-#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
-#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
-#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
-#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
-#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
-#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
-#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
-#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
-#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
-#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
-#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
-#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
-#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
-#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
-#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
-#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
-#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
-#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
-#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
-#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
-#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
-#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
-#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
-#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
-#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
-#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
-#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
-#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
-#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
-#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
-#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
-#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)                                          
-#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)                                          
-#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)                                          
-#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)                                          
-#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)                                          
-#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)                                          
-#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)                                          
-#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)                                          
-#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)                                         
-#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)                                         
-#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)                                         
-#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)                                         
-#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)                                         
-#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)                                         
-#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)                                         
-#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)                                         
-#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)                                          
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)                                     
-#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)                                     
-#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)                                     
-#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)                                     
-#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)                                     
-#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)                                     
-#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)                                     
-#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)                                     
-#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)                                     
-#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)                                     
-#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)                                    
-#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)                                    
-#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)                                    
-#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)                                    
-#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)                                    
-#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)                                    
-#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)                                    
-#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)                                    
-#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)                                    
-#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)                                    
-#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)                                    
-#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)                                    
-#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)                                     
-#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)                                     
-#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)                                     
-#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)                                     
-#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)                                     
-#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)                                    
-#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)                                    
-#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)                                    
-#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)                                    
-#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)                                    
-#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)                                    
-#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)                                    
-#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)                                    
-#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)                                    
-#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)                                    
-#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)                                    
-#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)                                    
-#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)                                    
-#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)                                     
-#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)                                     
-#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)                                     
-#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)                                     
-#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)                                     
-#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)                                     
-#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)                                     
-#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)                                     
-#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)                                     
-#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)                                     
-#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)                                    
-#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)                                    
-#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)                                    
-#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)                                    
-#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)                                    
-#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)                                    
-#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)                                    
-#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)                                    
-#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)                                    
-#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)                                    
-#define USART_CR3_UCESM_Msk           (0x1U << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
-#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)                                     
-#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)                                     
-#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)                                     
-#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)                                    
-#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)                                     
-#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)                                     
-#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)                                     
-#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)                                     
-#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)                                     
-#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)                                     
-#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)                                     
-#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)                                     
-#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)                                     
-#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)                                     
-#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)                                     
-#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)                                     
-#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)                                     
-#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)                                     
-#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)                                     
-#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)                                    
-#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)                                    
-#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)                                    
-#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)                                    
-#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)                                    
-#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)                                    
-#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)                                    
-#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)                                    
-#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)                                    
-#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)                                    
-#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)                                    
-#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)                                    
-#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)                                     
-#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)                                     
-#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)                                     
-#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)                                     
-#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)                                     
-#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)                                     
-#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)                                     
-#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)                                     
-#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)                                    
-#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)                                    
-#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)                                    
-#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)                                    
-#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)                                     
-#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)                                     
-#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)                                        
-#define USB_PMAADDR_Msk           (0x20003U << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)                                           
-#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)                                           
-#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)                                           
-#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)                                           
-#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)                                           
-#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)                                           
-#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : Advanced-control timers *****************/
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-													   
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == LPUART1))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L053xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l0xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L0xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral's registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx
-  * @{
-  */
-    
-#ifndef __STM32L0xx_H
-#define __STM32L0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L0)
-#define STM32L0
-#endif /* STM32L0 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
-    !defined (STM32L031xx) && !defined (STM32L041xx) && \
-    !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
-    !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
-    !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
-    !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
-  /* #define STM32L011xx */
-  /* #define STM32L021xx */
-  /* #define STM32L031xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
-  /* #define STM32L041xx */   /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
-  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
-  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
-  #define STM32L053xx   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
-  /* #define STM32L061xx */   /*!< */
-  /* #define STM32L062xx */   /*!< STM32L062K8 */
-  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
-  /* #define STM32L071xx */   /*!< */
-  /* #define STM32L072xx */   /*!< */
-  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
-  /* #define STM32L081xx */   /*!< */
-  /* #define STM32L082xx */   /*!< */
-  /* #define STM32L083xx */   /*!< */ 
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.7.0
-  */
-#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
-                                      |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
-                                      |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
-                                      |(__STM32L0xx_CMSIS_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-#if defined(STM32L011xx)
-  #include "stm32l011xx.h"
-#elif defined(STM32L021xx)
-  #include "stm32l021xx.h"
-#elif defined(STM32L031xx)
-  #include "stm32l031xx.h"
-#elif defined(STM32L041xx)
-  #include "stm32l041xx.h"
-#elif defined(STM32L051xx)
-  #include "stm32l051xx.h"
-#elif defined(STM32L052xx)
-  #include "stm32l052xx.h"
-#elif defined(STM32L053xx)
-  #include "stm32l053xx.h"
-#elif defined(STM32L062xx)
-  #include "stm32l062xx.h"
-#elif defined(STM32L063xx)
-  #include "stm32l063xx.h"
-#elif defined(STM32L061xx)
-  #include "stm32l061xx.h"
-#elif defined(STM32L071xx)
-  #include "stm32l071xx.h"
-#elif defined(STM32L072xx)
-  #include "stm32l072xx.h"
-#elif defined(STM32L073xx)
-  #include "stm32l073xx.h"
-#elif defined(STM32L082xx)
-  #include "stm32l082xx.h"
-#elif defined(STM32L083xx)
-  #include "stm32l083xx.h"
-#elif defined(STM32L081xx)
-  #include "stm32l081xx.h"
-#else
- #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l0xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L0xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_clock.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,245 +0,0 @@
-/* mbed Microcontroller Library
-* Copyright (c) 2006-2017 ARM Limited
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
-/**
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------
-  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
-  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
-  *                     | 3- USE_PLL_HSI (internal 16 MHz)
-  *-----------------------------------------------------------------
-  * SYSCLK(MHz)         | 32
-  * AHBCLK (MHz)        | 32
-  * APB1CLK (MHz)       | 32
-  * USB capable         | YES
-  *-----------------------------------------------------------------
-  */
-
-#include "stm32l0xx.h"
-#include "mbed_assert.h"
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x100. */
-
-#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
-#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
-#define USE_PLL_HSI          0x2  // Use HSI internal clock
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-    /*!< Set MSION bit */
-    RCC->CR |= (uint32_t)0x00000100U;
-
-    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-    RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-    RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-    /*!< Reset HSI48ON  bit */
-    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-    /*!< Reset HSEBYP bit */
-    RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-    /*!< Disable all interrupts */
-    RCC->CIER = 0x00000000U;
-
-    /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
-    /* 1- Try to start with HSE and external clock */
-    if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-    {
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
-        /* 2- If fail try to start with HSE and external xtal */
-        if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-        {
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-            /* 3- If fail start with HSI clock */
-            if (SetSysClock_PLL_HSI() == 0)
-#endif
-            {
-                while(1) {
-                    MBED_ASSERT(1);
-                }
-            }
-        }
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-
-    /* Used to gain time after DeepSleep in case HSI is used */
-    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
-        return 0;
-    }
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __PWR_CLK_ENABLE();
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-    if (bypass == 0) {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-    } else {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-    }
-    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Select HSI48 as USB clock source */
-    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //if (bypass == 0)
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-    //else
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-    return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __PWR_CLK_ENABLE();
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-    RCC_OscInitStruct.HSICalibrationValue = 16;
-    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-    return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L0XX_H
-#define __SYSTEM_STM32L0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L0xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-/*
-*/
-extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
-extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct trng_s {
-    RNG_HandleTypeDef handle;
-};
-
-#include "common_objects.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1   = (int)USART1_BASE,
-    UART_2   = (int)USART2_BASE,
-    LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_21 = (int)TIM21_BASE,
-    PWM_22 = (int)TIM22_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
-    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
-    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
-    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
-    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
-    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
-    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
-    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
-    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
-    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
-    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
-    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
-    {NC,   NC,    0}
-};
-
-const PinMap PinMap_ADC_Internal[] = {
-    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
-    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
-    {ADC_VLCD, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
-    {NC,   NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM21 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
-    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
-    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
-    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
-    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
-    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
-    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
-//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
-//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
-    {PC_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1
-    {PC_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PC_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PC_5,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {NC,    NC,      0}
-};
-
-const PinMap PinMap_UART_RTS[] = {
-    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PD_2,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_CTS[] = {
-    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {NC,    NC,       0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,160 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // ADC internal channels
-    ADC_TEMP = 0xF0,
-    ADC_VREF = 0xF1,
-    ADC_VLCD = 0xF2,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PA_5,
-    LED2        = PA_5,
-    LED3        = PA_5,
-    LED4        = PA_5,
-    USER_BUTTON = PC_13,
-    // Standardized button names
-    BUTTON1 = USER_BUTTON,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    //USB pins
-    USB_DM = PA_11,
-    USB_DP = PA_12,
-    USB_NOE_ALT = PA_13,
-    USB_NOE = PC_9,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,239 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_ARM_MICRO/stm32l053r8.sct	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_ARM_STD/stm32l053r8.sct	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_ARM_STD/sys.cpp	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_GCC_ARM/STM32L053X8.ld	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
-  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 8K - 0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l053xx.s
-  * @author    MCD Application Team
-  * @version   V1.5.0
-  * @date      8-January-2016
-  * @brief     STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
- 
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-  b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_IAR/startup_stm32l053xx.S	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,326 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32L053xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0800FFFF;
-
-/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x20001FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x400;
-define symbol __size_heap__   = 0x800;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/cmsis.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/cmsis_nvic.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
-// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-#define NVIC_NUM_VECTORS        48
-#define NVIC_RAM_VECTOR_ADDRESS 0x20000000    // Vectors positioned at start of RAM
-
-#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/hal_tick.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,65 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l0xx.h"
-#include "stm32l0xx_ll_tim.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM21
-#define TIM_MST_IRQ  TIM21_IRQn
-#define TIM_MST_RCC  __TIM21_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
-
-#define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
-
-#define TIM_MST_PCLK  2 // Select the peripheral clock number (1 or 2)
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,7508 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l053xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l053xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l053xx
-  * @{
-  */
-    
-#ifndef __STM32L053xx_H
-#define __STM32L053xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l053xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-
-/**
-* @brief CRC calculation unit
-*/
-
-typedef struct
-{
-__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
-__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
-uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
-uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
-__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
-uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
-__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
-__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FIREWALL_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
-  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
-  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE             ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
-#define FLASH_END              ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
-#define DATA_EEPROM_BASE       ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
-#define SRAM_SIZE_MAX          ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
-
-#define PERIPH_BASE            ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000U)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000U)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000U)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400U)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800U)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00U)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000U)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800U)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400U)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800U)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400U)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800U)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00U)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000U)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400U)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00U)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000U)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018U)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CU)
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400U)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800U)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400U)
-#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00U)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400U)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708U)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000U)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800U)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800U)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008U)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CU)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030U)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044U)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058U)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CU)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080U)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8U)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000U)        /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        ((uint32_t)0x1FF8007CU)        /*!< FLASH Size register base address */
-#define UID_BASE              ((uint32_t)0x1FF80050U)        /*!< Unique device ID register base address  */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000U)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000U)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000U)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400U)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800U)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00U)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00U)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL_Pos          (11U)                                       
-#define ADC_ISR_EOCAL_Msk          (0x1U << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
-#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
-#define ADC_ISR_AWD_Pos            (7U)                                        
-#define ADC_ISR_AWD_Msk            (0x1U << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
-#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
-#define ADC_ISR_OVR_Pos            (4U)                                        
-#define ADC_ISR_OVR_Msk            (0x1U << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
-#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
-#define ADC_ISR_EOSEQ_Pos          (3U)                                        
-#define ADC_ISR_EOSEQ_Msk          (0x1U << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
-#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
-#define ADC_ISR_EOC_Pos            (2U)                                        
-#define ADC_ISR_EOC_Msk            (0x1U << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
-#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
-#define ADC_ISR_EOSMP_Pos          (1U)                                        
-#define ADC_ISR_EOSMP_Msk          (0x1U << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
-#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
-#define ADC_ISR_ADRDY_Pos          (0U)                                        
-#define ADC_ISR_ADRDY_Msk          (0x1U << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
-#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE_Pos        (11U)                                       
-#define ADC_IER_EOCALIE_Msk        (0x1U << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
-#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE_Pos          (7U)                                        
-#define ADC_IER_AWDIE_Msk          (0x1U << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
-#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE_Pos          (4U)                                        
-#define ADC_IER_OVRIE_Msk          (0x1U << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
-#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE_Pos        (3U)                                        
-#define ADC_IER_EOSEQIE_Msk        (0x1U << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
-#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE_Pos          (2U)                                        
-#define ADC_IER_EOCIE_Msk          (0x1U << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
-#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE_Pos        (1U)                                        
-#define ADC_IER_EOSMPIE_Msk        (0x1U << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE_Pos        (0U)                                        
-#define ADC_IER_ADRDYIE_Msk        (0x1U << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL_Pos           (31U)                                       
-#define ADC_CR_ADCAL_Msk           (0x1U << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
-#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
-#define ADC_CR_ADVREGEN_Pos        (28U)                                       
-#define ADC_CR_ADVREGEN_Msk        (0x1U << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP_Pos           (4U)                                        
-#define ADC_CR_ADSTP_Msk           (0x1U << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
-#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART_Pos         (2U)                                        
-#define ADC_CR_ADSTART_Msk         (0x1U << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
-#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
-#define ADC_CR_ADDIS_Pos           (1U)                                        
-#define ADC_CR_ADDIS_Msk           (0x1U << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
-#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
-#define ADC_CR_ADEN_Pos            (0U)                                        
-#define ADC_CR_ADEN_Msk            (0x1U << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
-#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH_Pos        (26U)                                       
-#define ADC_CFGR1_AWDCH_Msk        (0x1FU << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
-#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0          (0x01U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
-#define ADC_CFGR1_AWDCH_1          (0x02U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
-#define ADC_CFGR1_AWDCH_2          (0x04U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
-#define ADC_CFGR1_AWDCH_3          (0x08U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
-#define ADC_CFGR1_AWDCH_4          (0x10U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR1_AWDEN_Pos        (23U)                                       
-#define ADC_CFGR1_AWDEN_Msk        (0x1U << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
-#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL_Pos       (22U)                                       
-#define ADC_CFGR1_AWDSGL_Msk       (0x1U << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
-#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN_Pos       (16U)                                       
-#define ADC_CFGR1_DISCEN_Msk       (0x1U << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF_Pos       (15U)                                       
-#define ADC_CFGR1_AUTOFF_Msk       (0x1U << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT_Pos         (14U)                                       
-#define ADC_CFGR1_WAIT_Msk         (0x1U << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT_Pos         (13U)                                       
-#define ADC_CFGR1_CONT_Msk         (0x1U << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
-#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD_Pos       (12U)                                       
-#define ADC_CFGR1_OVRMOD_Msk       (0x1U << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN_Pos        (10U)                                       
-#define ADC_CFGR1_EXTEN_Msk        (0x3U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0          (0x1U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1          (0x2U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
-#define ADC_CFGR1_EXTSEL_Pos       (6U)                                        
-#define ADC_CFGR1_EXTSEL_Msk       (0x7U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0         (0x1U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1         (0x2U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2         (0x4U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
-#define ADC_CFGR1_ALIGN_Pos        (5U)                                        
-#define ADC_CFGR1_ALIGN_Msk        (0x1U << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
-#define ADC_CFGR1_RES_Pos          (3U)                                        
-#define ADC_CFGR1_RES_Msk          (0x3U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
-#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0            (0x1U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1            (0x2U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
-#define ADC_CFGR1_SCANDIR_Pos      (2U)                                        
-#define ADC_CFGR1_SCANDIR_Msk      (0x1U << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG_Pos       (1U)                                        
-#define ADC_CFGR1_DMACFG_Msk       (0x1U << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN_Pos        (0U)                                        
-#define ADC_CFGR1_DMAEN_Msk        (0x1U << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS_Pos         (9U)                                        
-#define ADC_CFGR2_TOVS_Msk         (0x400001U << ADC_CFGR2_TOVS_Pos)           /*!< 0x80000200 */
-#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS_Pos         (5U)                                        
-#define ADC_CFGR2_OVSS_Msk         (0xFU << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0           (0x1U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1           (0x2U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2           (0x4U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3           (0x8U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
-#define ADC_CFGR2_OVSR_Pos         (2U)                                        
-#define ADC_CFGR2_OVSR_Msk         (0x7U << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0           (0x1U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1           (0x2U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2           (0x4U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
-#define ADC_CFGR2_OVSE_Pos         (0U)                                        
-#define ADC_CFGR2_OVSE_Msk         (0x1U << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE_Pos       (30U)                                       
-#define ADC_CFGR2_CKMODE_Msk       (0x3U << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0         (0x1U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
-#define ADC_CFGR2_CKMODE_1         (0x2U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP_Pos           (0U)                                        
-#define ADC_SMPR_SMP_Msk           (0x7U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
-#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0             (0x1U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
-#define ADC_SMPR_SMP_1             (0x2U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
-#define ADC_SMPR_SMP_2             (0x4U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
-
-/* Legacy defines */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT_Pos              (16U)                                       
-#define ADC_TR_HT_Msk              (0xFFFU << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
-#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
-#define ADC_TR_LT_Pos              (0U)                                        
-#define ADC_TR_LT_Msk              (0xFFFU << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL_Pos       (0U)                                        
-#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFU << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
-#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
-#define ADC_CHSELR_CHSEL18_Pos     (18U)                                       
-#define ADC_CHSELR_CHSEL18_Msk     (0x1U << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
-#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17_Pos     (17U)                                       
-#define ADC_CHSELR_CHSEL17_Msk     (0x1U << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16_Pos     (16U)                                       
-#define ADC_CHSELR_CHSEL16_Msk     (0x1U << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15_Pos     (15U)                                       
-#define ADC_CHSELR_CHSEL15_Msk     (0x1U << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14_Pos     (14U)                                       
-#define ADC_CHSELR_CHSEL14_Msk     (0x1U << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13_Pos     (13U)                                       
-#define ADC_CHSELR_CHSEL13_Msk     (0x1U << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12_Pos     (12U)                                       
-#define ADC_CHSELR_CHSEL12_Msk     (0x1U << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11_Pos     (11U)                                       
-#define ADC_CHSELR_CHSEL11_Msk     (0x1U << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10_Pos     (10U)                                       
-#define ADC_CHSELR_CHSEL10_Msk     (0x1U << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9_Pos      (9U)                                        
-#define ADC_CHSELR_CHSEL9_Msk      (0x1U << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8_Pos      (8U)                                        
-#define ADC_CHSELR_CHSEL8_Msk      (0x1U << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7_Pos      (7U)                                        
-#define ADC_CHSELR_CHSEL7_Msk      (0x1U << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6_Pos      (6U)                                        
-#define ADC_CHSELR_CHSEL6_Msk      (0x1U << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5_Pos      (5U)                                        
-#define ADC_CHSELR_CHSEL5_Msk      (0x1U << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4_Pos      (4U)                                        
-#define ADC_CHSELR_CHSEL4_Msk      (0x1U << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3_Pos      (3U)                                        
-#define ADC_CHSELR_CHSEL3_Msk      (0x1U << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2_Pos      (2U)                                        
-#define ADC_CHSELR_CHSEL2_Msk      (0x1U << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1_Pos      (1U)                                        
-#define ADC_CHSELR_CHSEL1_Msk      (0x1U << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0_Pos      (0U)                                        
-#define ADC_CHSELR_CHSEL0_Msk      (0x1U << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos            (0U)                                        
-#define ADC_DR_DATA_Msk            (0xFFFFU << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
-#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_Pos    (0U)                                        
-#define ADC_CALFACT_CALFACT_Msk    (0x7FU << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN_Pos          (25U)                                       
-#define ADC_CCR_LFMEN_Msk          (0x1U << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
-#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN_Pos         (24U)                                       
-#define ADC_CCR_VLCDEN_Msk         (0x1U << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
-#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
-#define ADC_CCR_TSEN_Pos           (23U)                                       
-#define ADC_CCR_TSEN_Msk           (0x1U << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN_Pos         (22U)                                       
-#define ADC_CCR_VREFEN_Msk         (0x1U << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
-#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
-#define ADC_CCR_PRESC_Pos          (18U)                                       
-#define ADC_CCR_PRESC_Msk          (0xFU << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
-#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0            (0x1U << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1            (0x2U << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2            (0x4U << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3            (0x8U << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN_Pos           (0U)                                    
-#define COMP_CSR_COMP1EN_Msk           (0x1U << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL_Pos       (4U)                                    
-#define COMP_CSR_COMP1INNSEL_Msk       (0x3U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
-#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0         (0x1U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP1INNSEL_1         (0x2U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP1WM_Pos           (8U)                                    
-#define COMP_CSR_COMP1WM_Msk           (0x1U << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
-#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)                                   
-#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMP1POLARITY_Msk     (0x1U << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE_Pos        (30U)                                   
-#define COMP_CSR_COMP1VALUE_Msk        (0x1U << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK_Pos         (31U)                                   
-#define COMP_CSR_COMP1LOCK_Msk         (0x1U << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN_Pos           (0U)                                    
-#define COMP_CSR_COMP2EN_Msk           (0x1U << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED_Pos        (3U)                                    
-#define COMP_CSR_COMP2SPEED_Msk        (0x1U << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
-#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL_Pos       (4U)                                    
-#define COMP_CSR_COMP2INNSEL_Msk       (0x7U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
-#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0         (0x1U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_COMP2INNSEL_1         (0x2U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
-#define COMP_CSR_COMP2INNSEL_2         (0x4U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
-#define COMP_CSR_COMP2INPSEL_Pos       (8U)                                    
-#define COMP_CSR_COMP2INPSEL_Msk       (0x7U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
-#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0         (0x1U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
-#define COMP_CSR_COMP2INPSEL_1         (0x2U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
-#define COMP_CSR_COMP2INPSEL_2         (0x4U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
-#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)                                   
-#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
-#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)                                   
-#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
-#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP2POLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMP2POLARITY_Msk     (0x1U << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE_Pos        (30U)                                   
-#define COMP_CSR_COMP2VALUE_Msk        (0x1U << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
-#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK_Pos         (31U)                                   
-#define COMP_CSR_COMP2LOCK_Msk         (0x1U << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN_Pos           (0U)                                    
-#define COMP_CSR_COMPxEN_Msk           (0x1U << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
-#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY_Pos     (15U)                                   
-#define COMP_CSR_COMPxPOLARITY_Msk     (0x1U << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
-#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)                                   
-#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1U << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
-#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK_Pos         (31U)                                   
-#define COMP_CSR_COMPxLOCK_Msk         (0x1U << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
-#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
-
-/* Reference defines */
-#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)                                          
-#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)                                          
-#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)                                          
-#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)                                          
-#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)                                          
-#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)                                          
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)                                          
-#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
-#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
-#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
-#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
-#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE_Pos          (2U)                                         
-#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
-#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE_Pos        (3U)                                         
-#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
-#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN_Pos            (5U)                                         
-#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
-#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
-#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
-#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC_Pos         (7U)                                         
-#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
-#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM_Pos           (8U)                                         
-#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
-#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD_Pos       (0U)                                         
-#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
-#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
-#define CRS_CFGR_FELIM_Pos        (16U)                                        
-#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
-#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
-#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
-#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
-#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
-#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
-
-#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
-#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
-#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
-#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
-
-#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
-#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
-#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
-#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
-#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
-#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
-#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
-#define CRS_ISR_ERRF_Pos          (2U)                                         
-#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
-#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
-#define CRS_ISR_ESYNCF_Pos        (3U)                                         
-#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
-#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR_Pos       (8U)                                         
-#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
-#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
-#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
-#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
-#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
-#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
-#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR_Pos         (15U)                                        
-#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
-#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
-#define CRS_ISR_FECAP_Pos         (16U)                                        
-#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
-#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
-#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
-#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
-#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
-#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC_Pos          (2U)                                         
-#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
-#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
-#define CRS_ICR_ESYNCC_Pos        (3U)                                         
-#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
-#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)                                       
-#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)                                       
-#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)                                       
-#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)                                       
-#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)                                       
-#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)                                       
-#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)                                      
-#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
-#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR           ((uint16_t)0x00000FFFU)                    /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)                                      
-#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
-#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
-#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_Pos                      (0U)                            
-#define DBGMCU_CR_DBG_Msk                      (0x7U << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
-#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
-#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
-#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)                                            
-#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1_Pos      (1U)                                            
-#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1_Pos      (2U)                                            
-#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1_Pos      (3U)                                            
-#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2_Pos       (4U)                                            
-#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2_Pos      (5U)                                            
-#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2_Pos      (6U)                                            
-#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2_Pos      (7U)                                            
-#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3_Pos       (8U)                                            
-#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3_Pos      (9U)                                            
-#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3_Pos      (10U)                                           
-#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3_Pos      (11U)                                           
-#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4_Pos       (12U)                                           
-#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4_Pos      (13U)                                           
-#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4_Pos      (14U)                                           
-#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4_Pos      (15U)                                           
-#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5_Pos       (16U)                                           
-#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5_Pos      (17U)                                           
-#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5_Pos      (18U)                                           
-#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5_Pos      (19U)                                           
-#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6_Pos       (20U)                                           
-#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)                                           
-#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)                                           
-#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)                                           
-#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)                                           
-#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)                                           
-#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)                                           
-#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)                                           
-#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)                                            
-#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
-#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
-#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
-#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2_Pos     (4U)                                            
-#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
-#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
-#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
-#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3_Pos     (8U)                                            
-#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
-#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
-#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
-#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4_Pos     (12U)                                           
-#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
-#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
-#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
-#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5_Pos     (16U)                                           
-#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
-#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
-#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
-#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6_Pos     (20U)                                           
-#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
-#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
-#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
-#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)                                           
-#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
-#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
-#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
-#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)                                            
-#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)                                            
-#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)                                            
-#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)                                            
-#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)                                            
-#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)                                            
-#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)                                            
-#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)                                            
-#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)                                            
-#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)                                           
-#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)                                           
-#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
-#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)                                            
-#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)                                            
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)                                            
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S_Pos      (0U)                                            
-#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
-#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S_Pos      (4U)                                            
-#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
-#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S_Pos      (8U)                                            
-#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
-#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S_Pos      (12U)                                           
-#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
-#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S_Pos      (16U)                                           
-#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
-#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S_Pos      (20U)                                           
-#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
-#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S_Pos      (24U)                                           
-#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
-#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0_Pos        (0U)                                           
-#define EXTI_IMR_IM0_Msk        (0x1U << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1_Pos        (1U)                                           
-#define EXTI_IMR_IM1_Msk        (0x1U << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2_Pos        (2U)                                           
-#define EXTI_IMR_IM2_Msk        (0x1U << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3_Pos        (3U)                                           
-#define EXTI_IMR_IM3_Msk        (0x1U << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4_Pos        (4U)                                           
-#define EXTI_IMR_IM4_Msk        (0x1U << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5_Pos        (5U)                                           
-#define EXTI_IMR_IM5_Msk        (0x1U << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6_Pos        (6U)                                           
-#define EXTI_IMR_IM6_Msk        (0x1U << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7_Pos        (7U)                                           
-#define EXTI_IMR_IM7_Msk        (0x1U << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8_Pos        (8U)                                           
-#define EXTI_IMR_IM8_Msk        (0x1U << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9_Pos        (9U)                                           
-#define EXTI_IMR_IM9_Msk        (0x1U << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10_Pos       (10U)                                          
-#define EXTI_IMR_IM10_Msk       (0x1U << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11_Pos       (11U)                                          
-#define EXTI_IMR_IM11_Msk       (0x1U << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12_Pos       (12U)                                          
-#define EXTI_IMR_IM12_Msk       (0x1U << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13_Pos       (13U)                                          
-#define EXTI_IMR_IM13_Msk       (0x1U << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14_Pos       (14U)                                          
-#define EXTI_IMR_IM14_Msk       (0x1U << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15_Pos       (15U)                                          
-#define EXTI_IMR_IM15_Msk       (0x1U << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16_Pos       (16U)                                          
-#define EXTI_IMR_IM16_Msk       (0x1U << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17_Pos       (17U)                                          
-#define EXTI_IMR_IM17_Msk       (0x1U << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18_Pos       (18U)                                          
-#define EXTI_IMR_IM18_Msk       (0x1U << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19_Pos       (19U)                                          
-#define EXTI_IMR_IM19_Msk       (0x1U << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20_Pos       (20U)                                          
-#define EXTI_IMR_IM20_Msk       (0x1U << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21_Pos       (21U)                                          
-#define EXTI_IMR_IM21_Msk       (0x1U << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22_Pos       (22U)                                          
-#define EXTI_IMR_IM22_Msk       (0x1U << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23_Pos       (23U)                                          
-#define EXTI_IMR_IM23_Msk       (0x1U << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25_Pos       (25U)                                          
-#define EXTI_IMR_IM25_Msk       (0x1U << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26_Pos       (26U)                                          
-#define EXTI_IMR_IM26_Msk       (0x1U << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28_Pos       (28U)                                          
-#define EXTI_IMR_IM28_Msk       (0x1U << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29_Pos       (29U)                                          
-#define EXTI_IMR_IM29_Msk       (0x1U << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
-
-#define EXTI_IMR_IM_Pos         (0U)                                           
-#define EXTI_IMR_IM_Msk         (0x36FFFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
-#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0_Pos        (0U)                                           
-#define EXTI_EMR_EM0_Msk        (0x1U << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
-#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1_Pos        (1U)                                           
-#define EXTI_EMR_EM1_Msk        (0x1U << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
-#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2_Pos        (2U)                                           
-#define EXTI_EMR_EM2_Msk        (0x1U << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
-#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3_Pos        (3U)                                           
-#define EXTI_EMR_EM3_Msk        (0x1U << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
-#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4_Pos        (4U)                                           
-#define EXTI_EMR_EM4_Msk        (0x1U << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
-#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5_Pos        (5U)                                           
-#define EXTI_EMR_EM5_Msk        (0x1U << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
-#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6_Pos        (6U)                                           
-#define EXTI_EMR_EM6_Msk        (0x1U << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
-#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7_Pos        (7U)                                           
-#define EXTI_EMR_EM7_Msk        (0x1U << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
-#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8_Pos        (8U)                                           
-#define EXTI_EMR_EM8_Msk        (0x1U << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
-#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9_Pos        (9U)                                           
-#define EXTI_EMR_EM9_Msk        (0x1U << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
-#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10_Pos       (10U)                                          
-#define EXTI_EMR_EM10_Msk       (0x1U << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
-#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11_Pos       (11U)                                          
-#define EXTI_EMR_EM11_Msk       (0x1U << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
-#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12_Pos       (12U)                                          
-#define EXTI_EMR_EM12_Msk       (0x1U << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
-#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13_Pos       (13U)                                          
-#define EXTI_EMR_EM13_Msk       (0x1U << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
-#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14_Pos       (14U)                                          
-#define EXTI_EMR_EM14_Msk       (0x1U << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
-#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15_Pos       (15U)                                          
-#define EXTI_EMR_EM15_Msk       (0x1U << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
-#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16_Pos       (16U)                                          
-#define EXTI_EMR_EM16_Msk       (0x1U << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
-#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17_Pos       (17U)                                          
-#define EXTI_EMR_EM17_Msk       (0x1U << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
-#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18_Pos       (18U)                                          
-#define EXTI_EMR_EM18_Msk       (0x1U << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
-#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19_Pos       (19U)                                          
-#define EXTI_EMR_EM19_Msk       (0x1U << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
-#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20_Pos       (20U)                                          
-#define EXTI_EMR_EM20_Msk       (0x1U << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
-#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21_Pos       (21U)                                          
-#define EXTI_EMR_EM21_Msk       (0x1U << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
-#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22_Pos       (22U)                                          
-#define EXTI_EMR_EM22_Msk       (0x1U << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
-#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23_Pos       (23U)                                          
-#define EXTI_EMR_EM23_Msk       (0x1U << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
-#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25_Pos       (25U)                                          
-#define EXTI_EMR_EM25_Msk       (0x1U << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
-#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26_Pos       (26U)                                          
-#define EXTI_EMR_EM26_Msk       (0x1U << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
-#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28_Pos       (28U)                                          
-#define EXTI_EMR_EM28_Msk       (0x1U << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
-#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29_Pos       (29U)                                          
-#define EXTI_EMR_EM29_Msk       (0x1U << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
-#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_RT0_Pos       (0U)                                           
-#define EXTI_RTSR_RT0_Msk       (0x1U << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_RT1_Pos       (1U)                                           
-#define EXTI_RTSR_RT1_Msk       (0x1U << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_RT2_Pos       (2U)                                           
-#define EXTI_RTSR_RT2_Msk       (0x1U << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_RT3_Pos       (3U)                                           
-#define EXTI_RTSR_RT3_Msk       (0x1U << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_RT4_Pos       (4U)                                           
-#define EXTI_RTSR_RT4_Msk       (0x1U << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_RT5_Pos       (5U)                                           
-#define EXTI_RTSR_RT5_Msk       (0x1U << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_RT6_Pos       (6U)                                           
-#define EXTI_RTSR_RT6_Msk       (0x1U << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_RT7_Pos       (7U)                                           
-#define EXTI_RTSR_RT7_Msk       (0x1U << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_RT8_Pos       (8U)                                           
-#define EXTI_RTSR_RT8_Msk       (0x1U << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_RT9_Pos       (9U)                                           
-#define EXTI_RTSR_RT9_Msk       (0x1U << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_RT10_Pos      (10U)                                          
-#define EXTI_RTSR_RT10_Msk      (0x1U << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_RT11_Pos      (11U)                                          
-#define EXTI_RTSR_RT11_Msk      (0x1U << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_RT12_Pos      (12U)                                          
-#define EXTI_RTSR_RT12_Msk      (0x1U << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_RT13_Pos      (13U)                                          
-#define EXTI_RTSR_RT13_Msk      (0x1U << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_RT14_Pos      (14U)                                          
-#define EXTI_RTSR_RT14_Msk      (0x1U << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_RT15_Pos      (15U)                                          
-#define EXTI_RTSR_RT15_Msk      (0x1U << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_RT16_Pos      (16U)                                          
-#define EXTI_RTSR_RT16_Msk      (0x1U << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_RT17_Pos      (17U)                                          
-#define EXTI_RTSR_RT17_Msk      (0x1U << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_RT19_Pos      (19U)                                          
-#define EXTI_RTSR_RT19_Msk      (0x1U << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_RT20_Pos      (20U)                                          
-#define EXTI_RTSR_RT20_Msk      (0x1U << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_RT21_Pos      (21U)                                          
-#define EXTI_RTSR_RT21_Msk      (0x1U << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_RT22_Pos      (22U)                                          
-#define EXTI_RTSR_RT22_Msk      (0x1U << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
-#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
-#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
-#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
-#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
-#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
-#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
-#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
-#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
-#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
-#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
-#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
-#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
-#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
-#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
-#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
-#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
-#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
-#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
-#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
-#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
-#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_FT0_Pos       (0U)                                           
-#define EXTI_FTSR_FT0_Msk       (0x1U << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
-#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_FT1_Pos       (1U)                                           
-#define EXTI_FTSR_FT1_Msk       (0x1U << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
-#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_FT2_Pos       (2U)                                           
-#define EXTI_FTSR_FT2_Msk       (0x1U << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
-#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_FT3_Pos       (3U)                                           
-#define EXTI_FTSR_FT3_Msk       (0x1U << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
-#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_FT4_Pos       (4U)                                           
-#define EXTI_FTSR_FT4_Msk       (0x1U << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
-#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_FT5_Pos       (5U)                                           
-#define EXTI_FTSR_FT5_Msk       (0x1U << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
-#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_FT6_Pos       (6U)                                           
-#define EXTI_FTSR_FT6_Msk       (0x1U << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
-#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_FT7_Pos       (7U)                                           
-#define EXTI_FTSR_FT7_Msk       (0x1U << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
-#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_FT8_Pos       (8U)                                           
-#define EXTI_FTSR_FT8_Msk       (0x1U << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
-#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_FT9_Pos       (9U)                                           
-#define EXTI_FTSR_FT9_Msk       (0x1U << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
-#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_FT10_Pos      (10U)                                          
-#define EXTI_FTSR_FT10_Msk      (0x1U << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
-#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_FT11_Pos      (11U)                                          
-#define EXTI_FTSR_FT11_Msk      (0x1U << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
-#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_FT12_Pos      (12U)                                          
-#define EXTI_FTSR_FT12_Msk      (0x1U << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
-#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_FT13_Pos      (13U)                                          
-#define EXTI_FTSR_FT13_Msk      (0x1U << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
-#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_FT14_Pos      (14U)                                          
-#define EXTI_FTSR_FT14_Msk      (0x1U << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
-#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_FT15_Pos      (15U)                                          
-#define EXTI_FTSR_FT15_Msk      (0x1U << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
-#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_FT16_Pos      (16U)                                          
-#define EXTI_FTSR_FT16_Msk      (0x1U << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
-#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_FT17_Pos      (17U)                                          
-#define EXTI_FTSR_FT17_Msk      (0x1U << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
-#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_FT19_Pos      (19U)                                          
-#define EXTI_FTSR_FT19_Msk      (0x1U << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
-#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_FT20_Pos      (20U)                                          
-#define EXTI_FTSR_FT20_Msk      (0x1U << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
-#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_FT21_Pos      (21U)                                          
-#define EXTI_FTSR_FT21_Msk      (0x1U << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
-#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_FT22_Pos      (22U)                                          
-#define EXTI_FTSR_FT22_Msk      (0x1U << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
-#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
-
-/* Legacy defines */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
-#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
-#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
-#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
-#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
-#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
-#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
-#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
-#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
-#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
-#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
-#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
-#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
-#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
-#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
-#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
-#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
-#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
-#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
-#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
-#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
-#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWI0_Pos     (0U)                                           
-#define EXTI_SWIER_SWI0_Msk     (0x1U << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
-#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWI1_Pos     (1U)                                           
-#define EXTI_SWIER_SWI1_Msk     (0x1U << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
-#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWI2_Pos     (2U)                                           
-#define EXTI_SWIER_SWI2_Msk     (0x1U << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
-#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWI3_Pos     (3U)                                           
-#define EXTI_SWIER_SWI3_Msk     (0x1U << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
-#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWI4_Pos     (4U)                                           
-#define EXTI_SWIER_SWI4_Msk     (0x1U << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
-#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWI5_Pos     (5U)                                           
-#define EXTI_SWIER_SWI5_Msk     (0x1U << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
-#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWI6_Pos     (6U)                                           
-#define EXTI_SWIER_SWI6_Msk     (0x1U << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
-#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWI7_Pos     (7U)                                           
-#define EXTI_SWIER_SWI7_Msk     (0x1U << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
-#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWI8_Pos     (8U)                                           
-#define EXTI_SWIER_SWI8_Msk     (0x1U << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
-#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWI9_Pos     (9U)                                           
-#define EXTI_SWIER_SWI9_Msk     (0x1U << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
-#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWI10_Pos    (10U)                                          
-#define EXTI_SWIER_SWI10_Msk    (0x1U << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
-#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWI11_Pos    (11U)                                          
-#define EXTI_SWIER_SWI11_Msk    (0x1U << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
-#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWI12_Pos    (12U)                                          
-#define EXTI_SWIER_SWI12_Msk    (0x1U << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
-#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWI13_Pos    (13U)                                          
-#define EXTI_SWIER_SWI13_Msk    (0x1U << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
-#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWI14_Pos    (14U)                                          
-#define EXTI_SWIER_SWI14_Msk    (0x1U << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
-#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWI15_Pos    (15U)                                          
-#define EXTI_SWIER_SWI15_Msk    (0x1U << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
-#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWI16_Pos    (16U)                                          
-#define EXTI_SWIER_SWI16_Msk    (0x1U << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
-#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWI17_Pos    (17U)                                          
-#define EXTI_SWIER_SWI17_Msk    (0x1U << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
-#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWI19_Pos    (19U)                                          
-#define EXTI_SWIER_SWI19_Msk    (0x1U << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
-#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWI20_Pos    (20U)                                          
-#define EXTI_SWIER_SWI20_Msk    (0x1U << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
-#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWI21_Pos    (21U)                                          
-#define EXTI_SWIER_SWI21_Msk    (0x1U << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
-#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWI22_Pos    (22U)                                          
-#define EXTI_SWIER_SWI22_Msk    (0x1U << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
-#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
-
-/* Legacy defines */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PIF0_Pos        (0U)                                           
-#define EXTI_PR_PIF0_Msk        (0x1U << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
-#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
-#define EXTI_PR_PIF1_Pos        (1U)                                           
-#define EXTI_PR_PIF1_Msk        (0x1U << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
-#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
-#define EXTI_PR_PIF2_Pos        (2U)                                           
-#define EXTI_PR_PIF2_Msk        (0x1U << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
-#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
-#define EXTI_PR_PIF3_Pos        (3U)                                           
-#define EXTI_PR_PIF3_Msk        (0x1U << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
-#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
-#define EXTI_PR_PIF4_Pos        (4U)                                           
-#define EXTI_PR_PIF4_Msk        (0x1U << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
-#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
-#define EXTI_PR_PIF5_Pos        (5U)                                           
-#define EXTI_PR_PIF5_Msk        (0x1U << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
-#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
-#define EXTI_PR_PIF6_Pos        (6U)                                           
-#define EXTI_PR_PIF6_Msk        (0x1U << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
-#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
-#define EXTI_PR_PIF7_Pos        (7U)                                           
-#define EXTI_PR_PIF7_Msk        (0x1U << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
-#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
-#define EXTI_PR_PIF8_Pos        (8U)                                           
-#define EXTI_PR_PIF8_Msk        (0x1U << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
-#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
-#define EXTI_PR_PIF9_Pos        (9U)                                           
-#define EXTI_PR_PIF9_Msk        (0x1U << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
-#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
-#define EXTI_PR_PIF10_Pos       (10U)                                          
-#define EXTI_PR_PIF10_Msk       (0x1U << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
-#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
-#define EXTI_PR_PIF11_Pos       (11U)                                          
-#define EXTI_PR_PIF11_Msk       (0x1U << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
-#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
-#define EXTI_PR_PIF12_Pos       (12U)                                          
-#define EXTI_PR_PIF12_Msk       (0x1U << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
-#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
-#define EXTI_PR_PIF13_Pos       (13U)                                          
-#define EXTI_PR_PIF13_Msk       (0x1U << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
-#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
-#define EXTI_PR_PIF14_Pos       (14U)                                          
-#define EXTI_PR_PIF14_Msk       (0x1U << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
-#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
-#define EXTI_PR_PIF15_Pos       (15U)                                          
-#define EXTI_PR_PIF15_Msk       (0x1U << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
-#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
-#define EXTI_PR_PIF16_Pos       (16U)                                          
-#define EXTI_PR_PIF16_Msk       (0x1U << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
-#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
-#define EXTI_PR_PIF17_Pos       (17U)                                          
-#define EXTI_PR_PIF17_Msk       (0x1U << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
-#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
-#define EXTI_PR_PIF19_Pos       (19U)                                          
-#define EXTI_PR_PIF19_Msk       (0x1U << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
-#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
-#define EXTI_PR_PIF20_Pos       (20U)                                          
-#define EXTI_PR_PIF20_Msk       (0x1U << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
-#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
-#define EXTI_PR_PIF21_Pos       (21U)                                          
-#define EXTI_PR_PIF21_Msk       (0x1U << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
-#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
-#define EXTI_PR_PIF22_Pos       (22U)                                          
-#define EXTI_PR_PIF22_Msk       (0x1U << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
-#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
-
-/* Legacy defines */
-#define EXTI_PR_PR0                         EXTI_PR_PIF0
-#define EXTI_PR_PR1                         EXTI_PR_PIF1
-#define EXTI_PR_PR2                         EXTI_PR_PIF2
-#define EXTI_PR_PR3                         EXTI_PR_PIF3
-#define EXTI_PR_PR4                         EXTI_PR_PIF4
-#define EXTI_PR_PR5                         EXTI_PR_PIF5
-#define EXTI_PR_PR6                         EXTI_PR_PIF6
-#define EXTI_PR_PR7                         EXTI_PR_PIF7
-#define EXTI_PR_PR8                         EXTI_PR_PIF8
-#define EXTI_PR_PR9                         EXTI_PR_PIF9
-#define EXTI_PR_PR10                        EXTI_PR_PIF10
-#define EXTI_PR_PR11                        EXTI_PR_PIF11
-#define EXTI_PR_PR12                        EXTI_PR_PIF12
-#define EXTI_PR_PR13                        EXTI_PR_PIF13
-#define EXTI_PR_PR14                        EXTI_PR_PIF14
-#define EXTI_PR_PR15                        EXTI_PR_PIF15
-#define EXTI_PR_PR16                        EXTI_PR_PIF16
-#define EXTI_PR_PR17                        EXTI_PR_PIF17
-#define EXTI_PR_PR19                        EXTI_PR_PIF19
-#define EXTI_PR_PR20                        EXTI_PR_PIF20
-#define EXTI_PR_PR21                        EXTI_PR_PIF21
-#define EXTI_PR_PR22                        EXTI_PR_PIF22
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos        (0U)                                      
-#define FLASH_ACR_LATENCY_Msk        (0x1U << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN_Pos         (1U)                                      
-#define FLASH_ACR_PRFTEN_Msk         (0x1U << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD_Pos       (3U)                                      
-#define FLASH_ACR_SLEEP_PD_Msk       (0x1U << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos         (4U)                                      
-#define FLASH_ACR_RUN_PD_Msk         (0x1U << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF_Pos      (5U)                                      
-#define FLASH_ACR_DISAB_BUF_Msk      (0x1U << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
-#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ_Pos       (6U)                                      
-#define FLASH_ACR_PRE_READ_Msk       (0x1U << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
-#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos        (0U)                                      
-#define FLASH_PECR_PELOCK_Msk        (0x1U << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos       (1U)                                      
-#define FLASH_PECR_PRGLOCK_Msk       (0x1U << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos       (2U)                                      
-#define FLASH_PECR_OPTLOCK_Msk       (0x1U << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos          (3U)                                      
-#define FLASH_PECR_PROG_Msk          (0x1U << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
-#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos          (4U)                                      
-#define FLASH_PECR_DATA_Msk          (0x1U << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
-#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
-#define FLASH_PECR_FIX_Pos           (8U)                                      
-#define FLASH_PECR_FIX_Msk           (0x1U << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
-#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos         (9U)                                      
-#define FLASH_PECR_ERASE_Msk         (0x1U << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
-#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos          (10U)                                     
-#define FLASH_PECR_FPRG_Msk          (0x1U << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
-#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos         (16U)                                     
-#define FLASH_PECR_EOPIE_Msk         (0x1U << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos         (17U)                                     
-#define FLASH_PECR_ERRIE_Msk         (0x1U << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)                                     
-#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1U << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY_Pos    (19U)                                     
-#define FLASH_PECR_HALF_ARRAY_Msk    (0x1U << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
-#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos      (0U)                                      
-#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos      (0U)                                      
-#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)                                      
-#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)                                      
-#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos             (0U)                                      
-#define FLASH_SR_BSY_Msk             (0x1U << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
-#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
-#define FLASH_SR_EOP_Pos             (1U)                                      
-#define FLASH_SR_EOP_Msk             (0x1U << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
-#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
-#define FLASH_SR_HVOFF_Pos           (2U)                                      
-#define FLASH_SR_HVOFF_Msk           (0x1U << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
-#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
-#define FLASH_SR_READY_Pos           (3U)                                      
-#define FLASH_SR_READY_Msk           (0x1U << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
-#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos          (8U)                                      
-#define FLASH_SR_WRPERR_Msk          (0x1U << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
-#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
-#define FLASH_SR_PGAERR_Pos          (9U)                                      
-#define FLASH_SR_PGAERR_Msk          (0x1U << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
-#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos          (10U)                                     
-#define FLASH_SR_SIZERR_Msk          (0x1U << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
-#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos         (11U)                                     
-#define FLASH_SR_OPTVERR_Msk         (0x1U << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
-#define FLASH_SR_RDERR_Pos           (13U)                                     
-#define FLASH_SR_RDERR_Msk           (0x1U << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
-#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR_Pos      (16U)                                     
-#define FLASH_SR_NOTZEROERR_Msk      (0x1U << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
-#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
-#define FLASH_SR_FWWERR_Pos          (17U)                                     
-#define FLASH_SR_FWWERR_Msk          (0x1U << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
-#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
-
-/* Legacy defines */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT_Pos        (0U)                                      
-#define FLASH_OPTR_RDPROT_Msk        (0xFFU << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
-#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD_Pos        (8U)                                      
-#define FLASH_OPTR_WPRMOD_Msk        (0x1U << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
-#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV_Pos       (16U)                                     
-#define FLASH_OPTR_BOR_LEV_Msk       (0xFU << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
-#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW_Pos       (20U)                                     
-#define FLASH_OPTR_IWDG_SW_Msk       (0x1U << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
-#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP_Pos     (21U)                                     
-#define FLASH_OPTR_nRST_STOP_Msk     (0x1U << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
-#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY_Pos    (22U)                                     
-#define FLASH_OPTR_nRST_STDBY_Msk    (0x1U << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
-#define FLASH_OPTR_USER_Pos          (20U)                                     
-#define FLASH_OPTR_USER_Msk          (0x7U << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
-#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1_Pos         (31U)                                     
-#define FLASH_OPTR_BOOT1_Msk         (0x1U << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
-#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP_Pos           (0U)                                      
-#define FLASH_WRPR_WRP_Msk           (0xFFFFU << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
-#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos            (0U)                                   
-#define GPIO_MODER_MODE0_Msk            (0x3U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
-#define GPIO_MODER_MODE0_0              (0x1U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1              (0x2U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos            (2U)                                   
-#define GPIO_MODER_MODE1_Msk            (0x3U << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
-#define GPIO_MODER_MODE1_0              (0x1U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1              (0x2U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos            (4U)                                   
-#define GPIO_MODER_MODE2_Msk            (0x3U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
-#define GPIO_MODER_MODE2_0              (0x1U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1              (0x2U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos            (6U)                                   
-#define GPIO_MODER_MODE3_Msk            (0x3U << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
-#define GPIO_MODER_MODE3_0              (0x1U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1              (0x2U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos            (8U)                                   
-#define GPIO_MODER_MODE4_Msk            (0x3U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
-#define GPIO_MODER_MODE4_0              (0x1U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1              (0x2U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos            (10U)                                  
-#define GPIO_MODER_MODE5_Msk            (0x3U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
-#define GPIO_MODER_MODE5_0              (0x1U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1              (0x2U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos            (12U)                                  
-#define GPIO_MODER_MODE6_Msk            (0x3U << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
-#define GPIO_MODER_MODE6_0              (0x1U << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1              (0x2U << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos            (14U)                                  
-#define GPIO_MODER_MODE7_Msk            (0x3U << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
-#define GPIO_MODER_MODE7_0              (0x1U << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1              (0x2U << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos            (16U)                                  
-#define GPIO_MODER_MODE8_Msk            (0x3U << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
-#define GPIO_MODER_MODE8_0              (0x1U << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1              (0x2U << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos            (18U)                                  
-#define GPIO_MODER_MODE9_Msk            (0x3U << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
-#define GPIO_MODER_MODE9_0              (0x1U << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1              (0x2U << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos           (20U)                                  
-#define GPIO_MODER_MODE10_Msk           (0x3U << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
-#define GPIO_MODER_MODE10_0             (0x1U << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1             (0x2U << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos           (22U)                                  
-#define GPIO_MODER_MODE11_Msk           (0x3U << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
-#define GPIO_MODER_MODE11_0             (0x1U << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1             (0x2U << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos           (24U)                                  
-#define GPIO_MODER_MODE12_Msk           (0x3U << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
-#define GPIO_MODER_MODE12_0             (0x1U << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1             (0x2U << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos           (26U)                                  
-#define GPIO_MODER_MODE13_Msk           (0x3U << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
-#define GPIO_MODER_MODE13_0             (0x1U << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1             (0x2U << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos           (28U)                                  
-#define GPIO_MODER_MODE14_Msk           (0x3U << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
-#define GPIO_MODER_MODE14_0             (0x1U << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1             (0x2U << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos           (30U)                                  
-#define GPIO_MODER_MODE15_Msk           (0x3U << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
-#define GPIO_MODER_MODE15_0             (0x1U << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1             (0x2U << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0                (0x00000001U)                          
-#define GPIO_OTYPER_OT_1                (0x00000002U)                          
-#define GPIO_OTYPER_OT_2                (0x00000004U)                          
-#define GPIO_OTYPER_OT_3                (0x00000008U)                          
-#define GPIO_OTYPER_OT_4                (0x00000010U)                          
-#define GPIO_OTYPER_OT_5                (0x00000020U)                          
-#define GPIO_OTYPER_OT_6                (0x00000040U)                          
-#define GPIO_OTYPER_OT_7                (0x00000080U)                          
-#define GPIO_OTYPER_OT_8                (0x00000100U)                          
-#define GPIO_OTYPER_OT_9                (0x00000200U)                          
-#define GPIO_OTYPER_OT_10               (0x00000400U)                          
-#define GPIO_OTYPER_OT_11               (0x00000800U)                          
-#define GPIO_OTYPER_OT_12               (0x00001000U)                          
-#define GPIO_OTYPER_OT_13               (0x00002000U)                          
-#define GPIO_OTYPER_OT_14               (0x00004000U)                          
-#define GPIO_OTYPER_OT_15               (0x00008000U)                          
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)                                   
-#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
-#define GPIO_OSPEEDER_OSPEED0_0         (0x1U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEED0_1         (0x2U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)                                   
-#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
-#define GPIO_OSPEEDER_OSPEED1_0         (0x1U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEED1_1         (0x2U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)                                   
-#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
-#define GPIO_OSPEEDER_OSPEED2_0         (0x1U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEED2_1         (0x2U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)                                   
-#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
-#define GPIO_OSPEEDER_OSPEED3_0         (0x1U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEED3_1         (0x2U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)                                   
-#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
-#define GPIO_OSPEEDER_OSPEED4_0         (0x1U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEED4_1         (0x2U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDER_OSPEED5_Pos       (10U)                                  
-#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
-#define GPIO_OSPEEDER_OSPEED5_0         (0x1U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEED5_1         (0x2U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDER_OSPEED6_Pos       (12U)                                  
-#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
-#define GPIO_OSPEEDER_OSPEED6_0         (0x1U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEED6_1         (0x2U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDER_OSPEED7_Pos       (14U)                                  
-#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
-#define GPIO_OSPEEDER_OSPEED7_0         (0x1U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEED7_1         (0x2U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDER_OSPEED8_Pos       (16U)                                  
-#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
-#define GPIO_OSPEEDER_OSPEED8_0         (0x1U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEED8_1         (0x2U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDER_OSPEED9_Pos       (18U)                                  
-#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
-#define GPIO_OSPEEDER_OSPEED9_0         (0x1U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEED9_1         (0x2U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDER_OSPEED10_Pos      (20U)                                  
-#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
-#define GPIO_OSPEEDER_OSPEED10_0        (0x1U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEED10_1        (0x2U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDER_OSPEED11_Pos      (22U)                                  
-#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
-#define GPIO_OSPEEDER_OSPEED11_0        (0x1U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEED11_1        (0x2U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDER_OSPEED12_Pos      (24U)                                  
-#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
-#define GPIO_OSPEEDER_OSPEED12_0        (0x1U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEED12_1        (0x2U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDER_OSPEED13_Pos      (26U)                                  
-#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
-#define GPIO_OSPEEDER_OSPEED13_0        (0x1U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEED13_1        (0x2U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDER_OSPEED14_Pos      (28U)                                  
-#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
-#define GPIO_OSPEEDER_OSPEED14_0        (0x1U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEED14_1        (0x2U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDER_OSPEED15_Pos      (30U)                                  
-#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
-#define GPIO_OSPEEDER_OSPEED15_0        (0x1U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEED15_1        (0x2U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0_Pos            (0U)                                   
-#define GPIO_PUPDR_PUPD0_Msk            (0x3U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
-#define GPIO_PUPDR_PUPD0_0              (0x1U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1              (0x2U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos            (2U)                                   
-#define GPIO_PUPDR_PUPD1_Msk            (0x3U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
-#define GPIO_PUPDR_PUPD1_0              (0x1U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1              (0x2U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos            (4U)                                   
-#define GPIO_PUPDR_PUPD2_Msk            (0x3U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
-#define GPIO_PUPDR_PUPD2_0              (0x1U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1              (0x2U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos            (6U)                                   
-#define GPIO_PUPDR_PUPD3_Msk            (0x3U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
-#define GPIO_PUPDR_PUPD3_0              (0x1U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1              (0x2U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos            (8U)                                   
-#define GPIO_PUPDR_PUPD4_Msk            (0x3U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
-#define GPIO_PUPDR_PUPD4_0              (0x1U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1              (0x2U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos            (10U)                                  
-#define GPIO_PUPDR_PUPD5_Msk            (0x3U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
-#define GPIO_PUPDR_PUPD5_0              (0x1U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1              (0x2U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos            (12U)                                  
-#define GPIO_PUPDR_PUPD6_Msk            (0x3U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
-#define GPIO_PUPDR_PUPD6_0              (0x1U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1              (0x2U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos            (14U)                                  
-#define GPIO_PUPDR_PUPD7_Msk            (0x3U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
-#define GPIO_PUPDR_PUPD7_0              (0x1U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1              (0x2U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos            (16U)                                  
-#define GPIO_PUPDR_PUPD8_Msk            (0x3U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
-#define GPIO_PUPDR_PUPD8_0              (0x1U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1              (0x2U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos            (18U)                                  
-#define GPIO_PUPDR_PUPD9_Msk            (0x3U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
-#define GPIO_PUPDR_PUPD9_0              (0x1U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1              (0x2U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos           (20U)                                  
-#define GPIO_PUPDR_PUPD10_Msk           (0x3U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
-#define GPIO_PUPDR_PUPD10_0             (0x1U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1             (0x2U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos           (22U)                                  
-#define GPIO_PUPDR_PUPD11_Msk           (0x3U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
-#define GPIO_PUPDR_PUPD11_0             (0x1U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1             (0x2U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos           (24U)                                  
-#define GPIO_PUPDR_PUPD12_Msk           (0x3U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
-#define GPIO_PUPDR_PUPD12_0             (0x1U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1             (0x2U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos           (26U)                                  
-#define GPIO_PUPDR_PUPD13_Msk           (0x3U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
-#define GPIO_PUPDR_PUPD13_0             (0x1U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1             (0x2U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos           (28U)                                  
-#define GPIO_PUPDR_PUPD14_Msk           (0x3U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
-#define GPIO_PUPDR_PUPD14_0             (0x1U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1             (0x2U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos           (30U)                                  
-#define GPIO_PUPDR_PUPD15_Msk           (0x3U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
-#define GPIO_PUPDR_PUPD15_0             (0x1U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1             (0x2U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                (0U)                                   
-#define GPIO_IDR_ID0_Msk                (0x1U << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
-#define GPIO_IDR_ID1_Pos                (1U)                                   
-#define GPIO_IDR_ID1_Msk                (0x1U << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
-#define GPIO_IDR_ID2_Pos                (2U)                                   
-#define GPIO_IDR_ID2_Msk                (0x1U << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
-#define GPIO_IDR_ID3_Pos                (3U)                                   
-#define GPIO_IDR_ID3_Msk                (0x1U << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
-#define GPIO_IDR_ID4_Pos                (4U)                                   
-#define GPIO_IDR_ID4_Msk                (0x1U << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
-#define GPIO_IDR_ID5_Pos                (5U)                                   
-#define GPIO_IDR_ID5_Msk                (0x1U << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
-#define GPIO_IDR_ID6_Pos                (6U)                                   
-#define GPIO_IDR_ID6_Msk                (0x1U << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
-#define GPIO_IDR_ID7_Pos                (7U)                                   
-#define GPIO_IDR_ID7_Msk                (0x1U << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
-#define GPIO_IDR_ID8_Pos                (8U)                                   
-#define GPIO_IDR_ID8_Msk                (0x1U << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
-#define GPIO_IDR_ID9_Pos                (9U)                                   
-#define GPIO_IDR_ID9_Msk                (0x1U << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
-#define GPIO_IDR_ID10_Pos               (10U)                                  
-#define GPIO_IDR_ID10_Msk               (0x1U << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
-#define GPIO_IDR_ID11_Pos               (11U)                                  
-#define GPIO_IDR_ID11_Msk               (0x1U << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
-#define GPIO_IDR_ID12_Pos               (12U)                                  
-#define GPIO_IDR_ID12_Msk               (0x1U << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
-#define GPIO_IDR_ID13_Pos               (13U)                                  
-#define GPIO_IDR_ID13_Msk               (0x1U << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
-#define GPIO_IDR_ID14_Pos               (14U)                                  
-#define GPIO_IDR_ID14_Msk               (0x1U << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
-#define GPIO_IDR_ID15_Pos               (15U)                                  
-#define GPIO_IDR_ID15_Msk               (0x1U << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0_Pos                (0U)                                   
-#define GPIO_ODR_OD0_Msk                (0x1U << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
-#define GPIO_ODR_OD1_Pos                (1U)                                   
-#define GPIO_ODR_OD1_Msk                (0x1U << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
-#define GPIO_ODR_OD2_Pos                (2U)                                   
-#define GPIO_ODR_OD2_Msk                (0x1U << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
-#define GPIO_ODR_OD3_Pos                (3U)                                   
-#define GPIO_ODR_OD3_Msk                (0x1U << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
-#define GPIO_ODR_OD4_Pos                (4U)                                   
-#define GPIO_ODR_OD4_Msk                (0x1U << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
-#define GPIO_ODR_OD5_Pos                (5U)                                   
-#define GPIO_ODR_OD5_Msk                (0x1U << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
-#define GPIO_ODR_OD6_Pos                (6U)                                   
-#define GPIO_ODR_OD6_Msk                (0x1U << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
-#define GPIO_ODR_OD7_Pos                (7U)                                   
-#define GPIO_ODR_OD7_Msk                (0x1U << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
-#define GPIO_ODR_OD8_Pos                (8U)                                   
-#define GPIO_ODR_OD8_Msk                (0x1U << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
-#define GPIO_ODR_OD9_Pos                (9U)                                   
-#define GPIO_ODR_OD9_Msk                (0x1U << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
-#define GPIO_ODR_OD10_Pos               (10U)                                  
-#define GPIO_ODR_OD10_Msk               (0x1U << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
-#define GPIO_ODR_OD11_Pos               (11U)                                  
-#define GPIO_ODR_OD11_Msk               (0x1U << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
-#define GPIO_ODR_OD12_Pos               (12U)                                  
-#define GPIO_ODR_OD12_Msk               (0x1U << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
-#define GPIO_ODR_OD13_Pos               (13U)                                  
-#define GPIO_ODR_OD13_Msk               (0x1U << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
-#define GPIO_ODR_OD14_Pos               (14U)                                  
-#define GPIO_ODR_OD14_Msk               (0x1U << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
-#define GPIO_ODR_OD15_Pos               (15U)                                  
-#define GPIO_ODR_OD15_Msk               (0x1U << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0                  (0x00000001U)                          
-#define GPIO_BSRR_BS_1                  (0x00000002U)                          
-#define GPIO_BSRR_BS_2                  (0x00000004U)                          
-#define GPIO_BSRR_BS_3                  (0x00000008U)                          
-#define GPIO_BSRR_BS_4                  (0x00000010U)                          
-#define GPIO_BSRR_BS_5                  (0x00000020U)                          
-#define GPIO_BSRR_BS_6                  (0x00000040U)                          
-#define GPIO_BSRR_BS_7                  (0x00000080U)                          
-#define GPIO_BSRR_BS_8                  (0x00000100U)                          
-#define GPIO_BSRR_BS_9                  (0x00000200U)                          
-#define GPIO_BSRR_BS_10                 (0x00000400U)                          
-#define GPIO_BSRR_BS_11                 (0x00000800U)                          
-#define GPIO_BSRR_BS_12                 (0x00001000U)                          
-#define GPIO_BSRR_BS_13                 (0x00002000U)                          
-#define GPIO_BSRR_BS_14                 (0x00004000U)                          
-#define GPIO_BSRR_BS_15                 (0x00008000U)                          
-#define GPIO_BSRR_BR_0                  (0x00010000U)                          
-#define GPIO_BSRR_BR_1                  (0x00020000U)                          
-#define GPIO_BSRR_BR_2                  (0x00040000U)                          
-#define GPIO_BSRR_BR_3                  (0x00080000U)                          
-#define GPIO_BSRR_BR_4                  (0x00100000U)                          
-#define GPIO_BSRR_BR_5                  (0x00200000U)                          
-#define GPIO_BSRR_BR_6                  (0x00400000U)                          
-#define GPIO_BSRR_BR_7                  (0x00800000U)                          
-#define GPIO_BSRR_BR_8                  (0x01000000U)                          
-#define GPIO_BSRR_BR_9                  (0x02000000U)                          
-#define GPIO_BSRR_BR_10                 (0x04000000U)                          
-#define GPIO_BSRR_BR_11                 (0x08000000U)                          
-#define GPIO_BSRR_BR_12                 (0x10000000U)                          
-#define GPIO_BSRR_BR_13                 (0x20000000U)                          
-#define GPIO_BSRR_BR_14                 (0x40000000U)                          
-#define GPIO_BSRR_BR_15                 (0x80000000U)                          
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos              (0U)                                   
-#define GPIO_LCKR_LCK0_Msk              (0x1U << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
-#define GPIO_LCKR_LCK1_Pos              (1U)                                   
-#define GPIO_LCKR_LCK1_Msk              (0x1U << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
-#define GPIO_LCKR_LCK2_Pos              (2U)                                   
-#define GPIO_LCKR_LCK2_Msk              (0x1U << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
-#define GPIO_LCKR_LCK3_Pos              (3U)                                   
-#define GPIO_LCKR_LCK3_Msk              (0x1U << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
-#define GPIO_LCKR_LCK4_Pos              (4U)                                   
-#define GPIO_LCKR_LCK4_Msk              (0x1U << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
-#define GPIO_LCKR_LCK5_Pos              (5U)                                   
-#define GPIO_LCKR_LCK5_Msk              (0x1U << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
-#define GPIO_LCKR_LCK6_Pos              (6U)                                   
-#define GPIO_LCKR_LCK6_Msk              (0x1U << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
-#define GPIO_LCKR_LCK7_Pos              (7U)                                   
-#define GPIO_LCKR_LCK7_Msk              (0x1U << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
-#define GPIO_LCKR_LCK8_Pos              (8U)                                   
-#define GPIO_LCKR_LCK8_Msk              (0x1U << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
-#define GPIO_LCKR_LCK9_Pos              (9U)                                   
-#define GPIO_LCKR_LCK9_Msk              (0x1U << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
-#define GPIO_LCKR_LCK10_Pos             (10U)                                  
-#define GPIO_LCKR_LCK10_Msk             (0x1U << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
-#define GPIO_LCKR_LCK11_Pos             (11U)                                  
-#define GPIO_LCKR_LCK11_Msk             (0x1U << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
-#define GPIO_LCKR_LCK12_Pos             (12U)                                  
-#define GPIO_LCKR_LCK12_Msk             (0x1U << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
-#define GPIO_LCKR_LCK13_Pos             (13U)                                  
-#define GPIO_LCKR_LCK13_Msk             (0x1U << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
-#define GPIO_LCKR_LCK14_Pos             (14U)                                  
-#define GPIO_LCKR_LCK14_Msk             (0x1U << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
-#define GPIO_LCKR_LCK15_Pos             (15U)                                  
-#define GPIO_LCKR_LCK15_Msk             (0x1U << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
-#define GPIO_LCKR_LCKK_Pos              (16U)                                  
-#define GPIO_LCKR_LCKK_Msk              (0x1U << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
-#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
-#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
-#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
-#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
-#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
-#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
-#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
-#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
-#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
-#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
-#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
-#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
-#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
-#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
-#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
-#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
-#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
-#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
-#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
-#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
-#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
-#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
-#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
-#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
-#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
-#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
-#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
-#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
-#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
-#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                   (0x00000001U)                          
-#define GPIO_BRR_BR_1                   (0x00000002U)                          
-#define GPIO_BRR_BR_2                   (0x00000004U)                          
-#define GPIO_BRR_BR_3                   (0x00000008U)                          
-#define GPIO_BRR_BR_4                   (0x00000010U)                          
-#define GPIO_BRR_BR_5                   (0x00000020U)                          
-#define GPIO_BRR_BR_6                   (0x00000040U)                          
-#define GPIO_BRR_BR_7                   (0x00000080U)                          
-#define GPIO_BRR_BR_8                   (0x00000100U)                          
-#define GPIO_BRR_BR_9                   (0x00000200U)                          
-#define GPIO_BRR_BR_10                  (0x00000400U)                          
-#define GPIO_BRR_BR_11                  (0x00000800U)                          
-#define GPIO_BRR_BR_12                  (0x00001000U)                          
-#define GPIO_BRR_BR_13                  (0x00002000U)                          
-#define GPIO_BRR_BR_14                  (0x00004000U)                          
-#define GPIO_BRR_BR_15                  (0x00008000U)                          
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)                                      
-#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)                                      
-#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)                                      
-#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)                                      
-#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)                                      
-#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)                                      
-#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)                                      
-#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)                                      
-#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)                                      
-#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)                                     
-#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
-#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
-#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)                                     
-#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
-#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)                                     
-#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)                                     
-#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)                                     
-#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)                                     
-#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)                                     
-#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)                                     
-#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)                                      
-#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)                                     
-#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)                                     
-#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)                                     
-#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)                                     
-#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)                                     
-#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)                                     
-#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)                                     
-#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)                                     
-#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)                                     
-#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)                                     
-#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)                                      
-#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
-#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)                                     
-#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)                                      
-#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
-#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
-#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
-#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
-#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
-#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
-#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
-#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)                                     
-#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
-#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
-#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
-#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
-#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)                                      
-#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)                                      
-#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)                                      
-#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)                                      
-#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)                                      
-#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)                                      
-#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)                                      
-#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)                                      
-#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)                                      
-#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)                                      
-#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)                                     
-#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)                                     
-#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
-#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)                                     
-#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)                                     
-#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)                                     
-#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)                                     
-#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)                                      
-#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)                                      
-#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)                                      
-#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)                                      
-#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)                                      
-#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)                                     
-#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)                                     
-#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
-#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)                                     
-#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)                                      
-#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)                                      
-#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)                                      
-#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)                                              
-#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)                                              
-#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)                                              
-#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)                                              
-#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)                                              
-#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)                                              
-#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)                                              
-#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos            (0U)                                       
-#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
-#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos             (1U)                                       
-#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
-#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos             (2U)                                       
-#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
-#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
-#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
-#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos             (5U)                                       
-#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
-#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
-#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos          (7U)                                       
-#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
-
-#define LCD_CR_BUFEN_Pos            (8U)
-#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
-#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos              (0U)                                       
-#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
-#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos           (1U)                                       
-#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
-#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos           (3U)                                       
-#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
-#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos             (4U)                                       
-#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
-#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
-#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
-#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos            (7U)                                       
-#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
-#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos              (10U)                                      
-#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
-#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
-#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
-#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos          (13U)                                      
-#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos           (16U)                                      
-#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
-#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos             (18U)                                      
-#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
-#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos              (22U)                                      
-#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
-#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos              (0U)                                       
-#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
-#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos              (1U)                                       
-#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
-#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos              (2U)                                       
-#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
-#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos              (3U)                                       
-#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
-#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos              (4U)                                       
-#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
-#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos            (5U)                                       
-#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
-#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos            (1U)                                       
-#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
-#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos            (3U)                                       
-#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
-#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
-#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)                                       
-#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)                                       
-#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
-#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)                                       
-#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)                                       
-#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)                                       
-#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
-#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
-#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
-#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)                                       
-#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
-#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
-#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
-#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
-#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
-#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)                                       
-#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
-#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
-#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
-#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
-#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
-#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
-#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)                                      
-#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)                                       
-#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
-#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
-#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)                                       
-#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)                                       
-#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)                                       
-#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD_Pos      (8U)                                              
-#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
-#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG_Pos      (8U)                                              
-#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
-#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD_Pos    (8U)                                              
-#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
-#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG_Pos    (8U)                                              
-#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
-#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD_Pos     (6U)                                              
-#define FW_VDSSA_ADD_Msk     (0x3FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG_Pos     (6U)                                              
-#define FW_VDSL_LENG_Msk     (0x3FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
-#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA_Pos        (0U)                                              
-#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
-#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS_Pos        (1U)                                              
-#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
-#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE_Pos        (2U)                                              
-#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
-#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos          (0U)                                        
-#define PWR_CR_LPSDSR_Msk          (0x1U << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
-#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos            (1U)                                        
-#define PWR_CR_PDDS_Msk            (0x1U << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
-#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos            (2U)                                        
-#define PWR_CR_CWUF_Msk            (0x1U << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
-#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos            (3U)                                        
-#define PWR_CR_CSBF_Msk            (0x1U << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
-#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos            (4U)                                        
-#define PWR_CR_PVDE_Msk            (0x1U << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
-#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos             (5U)                                        
-#define PWR_CR_PLS_Msk             (0x7U << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
-#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0               (0x1U << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
-#define PWR_CR_PLS_1               (0x2U << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
-#define PWR_CR_PLS_2               (0x4U << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos             (8U)                                        
-#define PWR_CR_DBP_Msk             (0x1U << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
-#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos             (9U)                                        
-#define PWR_CR_ULP_Msk             (0x1U << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
-#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos             (10U)                                       
-#define PWR_CR_FWU_Msk             (0x1U << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
-#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos             (11U)                                       
-#define PWR_CR_VOS_Msk             (0x3U << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
-#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0               (0x1U << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
-#define PWR_CR_VOS_1               (0x2U << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
-#define PWR_CR_DSEEKOFF_Pos        (13U)                                       
-#define PWR_CR_DSEEKOFF_Msk        (0x1U << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
-#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN_Pos           (14U)                                       
-#define PWR_CR_LPRUN_Msk           (0x1U << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
-#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos            (0U)                                        
-#define PWR_CSR_WUF_Msk            (0x1U << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
-#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos            (1U)                                        
-#define PWR_CSR_SBF_Msk            (0x1U << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
-#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos           (2U)                                        
-#define PWR_CSR_PVDO_Msk           (0x1U << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
-#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos    (3U)                                        
-#define PWR_CSR_VREFINTRDYF_Msk    (0x1U << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos           (4U)                                        
-#define PWR_CSR_VOSF_Msk           (0x1U << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
-#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos         (5U)                                        
-#define PWR_CSR_REGLPF_Msk         (0x1U << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
-#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos          (8U)                                        
-#define PWR_CSR_EWUP1_Msk          (0x1U << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
-#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos          (9U)                                        
-#define PWR_CSR_EWUP2_Msk          (0x1U << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
-#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
-#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                 (0U)                                  
-#define RCC_CR_HSION_Msk                 (0x1U << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
-#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON_Pos              (1U)                                  
-#define RCC_CR_HSIKERON_Msk              (0x1U << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                (2U)                                  
-#define RCC_CR_HSIRDY_Msk                (0x1U << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
-#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN_Pos              (3U)                                  
-#define RCC_CR_HSIDIVEN_Msk              (0x1U << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
-#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF_Pos               (4U)                                  
-#define RCC_CR_HSIDIVF_Msk               (0x1U << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
-#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION_Pos                 (8U)                                  
-#define RCC_CR_MSION_Msk                 (0x1U << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
-#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                (9U)                                  
-#define RCC_CR_MSIRDY_Msk                (0x1U << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON_Pos                 (16U)                                 
-#define RCC_CR_HSEON_Msk                 (0x1U << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
-#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                (17U)                                 
-#define RCC_CR_HSERDY_Msk                (0x1U << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
-#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                (18U)                                 
-#define RCC_CR_HSEBYP_Msk                (0x1U << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON_Pos              (19U)                                 
-#define RCC_CR_CSSHSEON_Msk              (0x1U << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
-#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE_Pos                (20U)                                 
-#define RCC_CR_RTCPRE_Msk                (0x3U << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
-#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                  (0x1U << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
-#define RCC_CR_RTCPRE_1                  (0x2U << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
-#define RCC_CR_PLLON_Pos                 (24U)                                 
-#define RCC_CR_PLLON_Msk                 (0x1U << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
-#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                (25U)                                 
-#define RCC_CR_PLLRDY_Msk                (0x1U << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
-
-/* Reference defines */
-#define RCC_CR_CSSON     RCC_CR_CSSHSEON
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos             (0U)                                  
-#define RCC_ICSCR_HSICAL_Msk             (0xFFU << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos            (8U)                                  
-#define RCC_ICSCR_HSITRIM_Msk            (0x1FU << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos           (13U)                                 
-#define RCC_ICSCR_MSIRANGE_Msk           (0x7U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0             (0x0U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1             (0x1U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2             (0x2U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3             (0x3U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4             (0x4U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5             (0x5U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6             (0x6U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos             (16U)                                 
-#define RCC_ICSCR_MSICAL_Msk             (0xFFU << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos            (24U)                                 
-#define RCC_ICSCR_MSITRIM_Msk            (0xFFU << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON_Pos            (0U)                                  
-#define RCC_CRRCR_HSI48ON_Msk            (0x1U << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
-#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY_Pos           (1U)                                  
-#define RCC_CRRCR_HSI48RDY_Msk           (0x1U << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
-#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL_Pos           (8U)                                  
-#define RCC_CRRCR_HSI48CAL_Msk           (0xFFU << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
-#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)                              
-#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)                              
-#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)                              
-#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)                              
-#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)                             
-#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
-#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
-#define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
-#define RCC_CFGR_PLLMUL_Msk                  (0xFU << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                    (0x1U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                    (0x2U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                    (0x4U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                    (0x8U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
-#define RCC_CFGR_PLLDIV_Msk                  (0x3U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                    (0x1U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                    (0x2U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
-
-#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV2_Msk                 (0x1U << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
-#define RCC_CFGR_PLLDIV3_Msk                 (0x1U << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
-#define RCC_CFGR_PLLDIV4_Msk                 (0x3U << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
-#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
-
-#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
-#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
-#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
-#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
-#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
-#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
-#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
-
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
-
-/* Legacy defines */
-#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
-#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
-#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
-#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
-#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
-#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
-#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
-#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
-#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
-
-#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE_Pos            (0U)                                  
-#define RCC_CIER_LSIRDYIE_Msk            (0x1U << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE_Pos            (1U)                                  
-#define RCC_CIER_LSERDYIE_Msk            (0x1U << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE_Pos            (2U)                                  
-#define RCC_CIER_HSIRDYIE_Msk            (0x1U << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
-#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE_Pos            (3U)                                  
-#define RCC_CIER_HSERDYIE_Msk            (0x1U << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
-#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE_Pos            (4U)                                  
-#define RCC_CIER_PLLRDYIE_Msk            (0x1U << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
-#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE_Pos            (5U)                                  
-#define RCC_CIER_MSIRDYIE_Msk            (0x1U << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
-#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE_Pos          (6U)                                  
-#define RCC_CIER_HSI48RDYIE_Msk          (0x1U << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
-#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_CSSLSE_Pos              (7U)                                  
-#define RCC_CIER_CSSLSE_Msk              (0x1U << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
-#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
-
-/* Reference defines */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF_Pos             (0U)                                  
-#define RCC_CIFR_LSIRDYF_Msk             (0x1U << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF_Pos             (1U)                                  
-#define RCC_CIFR_LSERDYF_Msk             (0x1U << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF_Pos             (2U)                                  
-#define RCC_CIFR_HSIRDYF_Msk             (0x1U << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
-#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF_Pos             (3U)                                  
-#define RCC_CIFR_HSERDYF_Msk             (0x1U << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
-#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF_Pos             (4U)                                  
-#define RCC_CIFR_PLLRDYF_Msk             (0x1U << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
-#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF_Pos             (5U)                                  
-#define RCC_CIFR_MSIRDYF_Msk             (0x1U << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
-#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF_Pos           (6U)                                  
-#define RCC_CIFR_HSI48RDYF_Msk           (0x1U << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
-#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_CSSLSEF_Pos             (7U)                                  
-#define RCC_CIFR_CSSLSEF_Msk             (0x1U << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
-#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSHSEF_Pos             (8U)                                  
-#define RCC_CIFR_CSSHSEF_Msk             (0x1U << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
-#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
-
-/* Reference defines */
-#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
-#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC_Pos             (0U)                                  
-#define RCC_CICR_LSIRDYC_Msk             (0x1U << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC_Pos             (1U)                                  
-#define RCC_CICR_LSERDYC_Msk             (0x1U << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC_Pos             (2U)                                  
-#define RCC_CICR_HSIRDYC_Msk             (0x1U << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
-#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC_Pos             (3U)                                  
-#define RCC_CICR_HSERDYC_Msk             (0x1U << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
-#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC_Pos             (4U)                                  
-#define RCC_CICR_PLLRDYC_Msk             (0x1U << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
-#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC_Pos             (5U)                                  
-#define RCC_CICR_MSIRDYC_Msk             (0x1U << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
-#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC_Pos           (6U)                                  
-#define RCC_CICR_HSI48RDYC_Msk           (0x1U << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
-#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_CSSLSEC_Pos             (7U)                                  
-#define RCC_CICR_CSSLSEC_Msk             (0x1U << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
-#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSHSEC_Pos             (8U)                                  
-#define RCC_CICR_CSSHSEC_Msk             (0x1U << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
-#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
-
-/* Reference defines */
-#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
-#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_IOPARST_Pos          (0U)                                  
-#define RCC_IOPRSTR_IOPARST_Msk          (0x1U << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
-#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
-#define RCC_IOPRSTR_IOPBRST_Pos          (1U)                                  
-#define RCC_IOPRSTR_IOPBRST_Msk          (0x1U << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
-#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
-#define RCC_IOPRSTR_IOPCRST_Pos          (2U)                                  
-#define RCC_IOPRSTR_IOPCRST_Msk          (0x1U << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
-#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
-#define RCC_IOPRSTR_IOPDRST_Pos          (3U)                                  
-#define RCC_IOPRSTR_IOPDRST_Msk          (0x1U << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
-#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
-#define RCC_IOPRSTR_IOPHRST_Pos          (7U)                                  
-#define RCC_IOPRSTR_IOPHRST_Msk          (0x1U << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
-#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
-
-/* Reference defines */
-#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
-
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMARST_Pos           (0U)                                  
-#define RCC_AHBRSTR_DMARST_Msk           (0x1U << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
-#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST_Pos           (8U)                                  
-#define RCC_AHBRSTR_MIFRST_Msk           (0x1U << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
-#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST_Pos           (12U)                                 
-#define RCC_AHBRSTR_CRCRST_Msk           (0x1U << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST_Pos           (16U)                                 
-#define RCC_AHBRSTR_TSCRST_Msk           (0x1U << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
-#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST_Pos           (20U)                                 
-#define RCC_AHBRSTR_RNGRST_Msk           (0x1U << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
-#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
-
-/* Reference defines */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U)                                  
-#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST_Pos        (2U)                                  
-#define RCC_APB2RSTR_TIM21RST_Msk        (0x1U << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST_Pos        (5U)                                  
-#define RCC_APB2RSTR_TIM22RST_Msk        (0x1U << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
-#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADCRST_Pos          (9U)                                  
-#define RCC_APB2RSTR_ADCRST_Msk          (0x1U << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST_Pos         (12U)                                 
-#define RCC_APB2RSTR_SPI1RST_Msk         (0x1U << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST_Pos       (14U)                                 
-#define RCC_APB2RSTR_USART1RST_Msk       (0x1U << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGRST_Pos          (22U)                                 
-#define RCC_APB2RSTR_DBGRST_Msk          (0x1U << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
-#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU clock reset */
-
-/* Reference defines */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos         (0U)                                  
-#define RCC_APB1RSTR_TIM2RST_Msk         (0x1U << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM6RST_Pos         (4U)                                  
-#define RCC_APB1RSTR_TIM6RST_Msk         (0x1U << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_LCDRST_Pos          (9U)                                  
-#define RCC_APB1RSTR_LCDRST_Msk          (0x1U << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST_Pos         (11U)                                 
-#define RCC_APB1RSTR_WWDGRST_Msk         (0x1U << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST_Pos         (14U)                                 
-#define RCC_APB1RSTR_SPI2RST_Msk         (0x1U << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST_Pos       (17U)                                 
-#define RCC_APB1RSTR_USART2RST_Msk       (0x1U << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)                                 
-#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_I2C1RST_Pos         (21U)                                 
-#define RCC_APB1RSTR_I2C1RST_Msk         (0x1U << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST_Pos         (22U)                                 
-#define RCC_APB1RSTR_I2C2RST_Msk         (0x1U << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST_Pos          (23U)                                 
-#define RCC_APB1RSTR_USBRST_Msk          (0x1U << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST_Pos          (27U)                                 
-#define RCC_APB1RSTR_CRSRST_Msk          (0x1U << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
-#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST_Pos          (28U)                                 
-#define RCC_APB1RSTR_PWRRST_Msk          (0x1U << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST_Pos          (29U)                                 
-#define RCC_APB1RSTR_DACRST_Msk          (0x1U << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC clock reset */
-#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)                                 
-#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
-#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 clock reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_IOPAEN_Pos            (0U)                                  
-#define RCC_IOPENR_IOPAEN_Msk            (0x1U << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
-#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
-#define RCC_IOPENR_IOPBEN_Pos            (1U)                                  
-#define RCC_IOPENR_IOPBEN_Msk            (0x1U << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
-#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
-#define RCC_IOPENR_IOPCEN_Pos            (2U)                                  
-#define RCC_IOPENR_IOPCEN_Msk            (0x1U << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
-#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
-#define RCC_IOPENR_IOPDEN_Pos            (3U)                                  
-#define RCC_IOPENR_IOPDEN_Msk            (0x1U << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
-#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
-#define RCC_IOPENR_IOPHEN_Pos            (7U)                                  
-#define RCC_IOPENR_IOPHEN_Msk            (0x1U << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
-#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
-
-/* Reference defines */
-#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMAEN_Pos             (0U)                                  
-#define RCC_AHBENR_DMAEN_Msk             (0x1U << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
-#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN_Pos             (8U)                                  
-#define RCC_AHBENR_MIFEN_Msk             (0x1U << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
-#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN_Pos             (12U)                                 
-#define RCC_AHBENR_CRCEN_Msk             (0x1U << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN_Pos             (16U)                                 
-#define RCC_AHBENR_TSCEN_Msk             (0x1U << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
-#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN_Pos             (20U)                                 
-#define RCC_AHBENR_RNGEN_Msk             (0x1U << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
-#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
-
-/* Reference defines */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN_Pos         (0U)                                  
-#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN_Pos          (2U)                                  
-#define RCC_APB2ENR_TIM21EN_Msk          (0x1U << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN_Pos          (5U)                                  
-#define RCC_APB2ENR_TIM22EN_Msk          (0x1U << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
-#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
-#define RCC_APB2ENR_FWEN_Pos             (7U)                                  
-#define RCC_APB2ENR_FWEN_Msk             (0x1U << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
-#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADCEN_Pos            (9U)                                  
-#define RCC_APB2ENR_ADCEN_Msk            (0x1U << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos           (12U)                                 
-#define RCC_APB2ENR_SPI1EN_Msk           (0x1U << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos         (14U)                                 
-#define RCC_APB2ENR_USART1EN_Msk         (0x1U << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGEN_Pos            (22U)                                 
-#define RCC_APB2ENR_DBGEN_Msk            (0x1U << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
-#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
-
-/* Reference defines */
-
-#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos           (0U)                                  
-#define RCC_APB1ENR_TIM2EN_Msk           (0x1U << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos           (4U)                                  
-#define RCC_APB1ENR_TIM6EN_Msk           (0x1U << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos            (9U)                                  
-#define RCC_APB1ENR_LCDEN_Msk            (0x1U << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos           (11U)                                 
-#define RCC_APB1ENR_WWDGEN_Msk           (0x1U << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos           (14U)                                 
-#define RCC_APB1ENR_SPI2EN_Msk           (0x1U << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos         (17U)                                 
-#define RCC_APB1ENR_USART2EN_Msk         (0x1U << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN_Pos        (18U)                                 
-#define RCC_APB1ENR_LPUART1EN_Msk        (0x1U << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos           (21U)                                 
-#define RCC_APB1ENR_I2C1EN_Msk           (0x1U << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos           (22U)                                 
-#define RCC_APB1ENR_I2C2EN_Msk           (0x1U << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos            (23U)                                 
-#define RCC_APB1ENR_USBEN_Msk            (0x1U << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN_Pos            (27U)                                 
-#define RCC_APB1ENR_CRSEN_Msk            (0x1U << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
-#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN_Pos            (28U)                                 
-#define RCC_APB1ENR_PWREN_Msk            (0x1U << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN_Pos            (29U)                                 
-#define RCC_APB1ENR_DACEN_Msk            (0x1U << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)                                 
-#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
-#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_IOPASMEN_Pos        (0U)                                  
-#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1U << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
-#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U)                                  
-#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
-#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U)                                  
-#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
-#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U)                                  
-#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
-#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U)                                  
-#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
-#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMASMEN_Pos         (0U)                                  
-#define RCC_AHBSMENR_DMASMEN_Msk         (0x1U << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN_Pos         (8U)                                  
-#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1U << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
-#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)                                  
-#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)                                 
-#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1U << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
-#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)                                 
-#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1U << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
-#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)                                 
-#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1U << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
-#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U)                                  
-#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U)                                  
-#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U)                                  
-#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADCSMEN_Pos        (9U)                                  
-#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1U << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)                                 
-#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)                                 
-#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)                                 
-#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1U << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
-#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
-
-/* Reference defines */
-#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U)                                  
-#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
-#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U)                                  
-#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
-#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN_Pos        (9U)                                  
-#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1U << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
-#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)                                 
-#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
-#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)                                 
-#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)                                 
-#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)                                 
-#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)                                 
-#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
-#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)                                 
-#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
-#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN_Pos        (23U)                                 
-#define RCC_APB1SMENR_USBSMEN_Msk        (0x1U << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
-#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)                                 
-#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1U << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
-#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)                                 
-#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1U << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
-#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN_Pos        (29U)                                 
-#define RCC_APB1SMENR_DACSMEN_Msk        (0x1U << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
-#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)                                 
-#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL_Pos          (0U)                                  
-#define RCC_CCIPR_USART1SEL_Msk          (0x3U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0            (0x1U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1            (0x2U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL_Pos          (2U)                                  
-#define RCC_CCIPR_USART2SEL_Msk          (0x3U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0            (0x1U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1            (0x2U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL_Pos         (10U)                                 
-#define RCC_CCIPR_LPUART1SEL_Msk         (0x3U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0           (0x1U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
-#define RCC_CCIPR_LPUART1SEL_1           (0x2U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL_Pos            (12U)                                 
-#define RCC_CCIPR_I2C1SEL_Msk            (0x3U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0              (0x1U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1              (0x2U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)                                 
-#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0            (0x1U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1            (0x2U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL_Pos           (26U)                                 
-#define RCC_CCIPR_HSI48SEL_Msk           (0x1U << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
-#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Legacy defines */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                (0U)                                  
-#define RCC_CSR_LSION_Msk                (0x1U << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
-#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos               (1U)                                  
-#define RCC_CSR_LSIRDY_Msk               (0x1U << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                (8U)                                  
-#define RCC_CSR_LSEON_Msk                (0x1U << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
-#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos               (9U)                                  
-#define RCC_CSR_LSERDY_Msk               (0x1U << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos               (10U)                                 
-#define RCC_CSR_LSEBYP_Msk               (0x1U << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV_Pos               (11U)                                 
-#define RCC_CSR_LSEDRV_Msk               (0x3U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
-#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                 (0x1U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
-#define RCC_CSR_LSEDRV_1                 (0x2U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
-                                             
-#define RCC_CSR_LSECSSON_Pos             (13U)                                 
-#define RCC_CSR_LSECSSON_Msk             (0x1U << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
-#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos              (14U)                                 
-#define RCC_CSR_LSECSSD_Msk              (0x1U << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
-#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL_Pos               (16U)                                 
-#define RCC_CSR_RTCSEL_Msk               (0x3U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                 (0x1U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                 (0x2U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos           (16U)                                 
-#define RCC_CSR_RTCSEL_LSE_Msk           (0x1U << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos           (17U)                                 
-#define RCC_CSR_RTCSEL_LSI_Msk           (0x1U << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos           (16U)                                 
-#define RCC_CSR_RTCSEL_HSE_Msk           (0x3U << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN_Pos                (18U)                                 
-#define RCC_CSR_RTCEN_Msk                (0x1U << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
-#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos               (19U)                                 
-#define RCC_CSR_RTCRST_Msk               (0x1U << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
-#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF_Pos                 (23U)                                 
-#define RCC_CSR_RMVF_Msk                 (0x1U << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
-#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF_Pos               (24U)                                 
-#define RCC_CSR_FWRSTF_Msk               (0x1U << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBLRSTF_Pos              (25U)                                 
-#define RCC_CSR_OBLRSTF_Msk              (0x1U << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF_Pos              (26U)                                 
-#define RCC_CSR_PINRSTF_Msk              (0x1U << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos              (27U)                                 
-#define RCC_CSR_PORRSTF_Msk              (0x1U << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos              (28U)                                 
-#define RCC_CSR_SFTRSTF_Msk              (0x1U << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos             (29U)                                 
-#define RCC_CSR_IWDGRSTF_Msk             (0x1U << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos             (30U)                                 
-#define RCC_CSR_WWDGRSTF_Msk             (0x1U << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos             (31U)                                 
-#define RCC_CSR_LPWRRSTF_Msk             (0x1U << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
-
-/* Reference defines */
-#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)                                               
-#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)                                               
-#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)                                               
-#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)                                               
-#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)                                               
-#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)                                               
-#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)                                               
-#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-#define RTC_TAMPER1_SUPPORT
-#define RTC_TAMPER2_SUPPORT
-#define RTC_WAKEUP_SUPPORT
-#define RTC_BACKUP_SUPPORT
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                  (22U)                                   
-#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
-#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
-#define RTC_TR_HT_Pos                  (20U)                                   
-#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
-#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
-#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
-#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                  (16U)                                   
-#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
-#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
-#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
-#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
-#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
-#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                 (12U)                                   
-#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
-#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
-#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
-#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
-#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                 (8U)                                    
-#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
-#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
-#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
-#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
-#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
-#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                  (4U)                                    
-#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
-#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
-#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
-#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
-#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                  (0U)                                    
-#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
-#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
-#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
-#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
-#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
-#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                  (20U)                                   
-#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
-#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
-#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
-#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
-#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
-#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                  (16U)                                   
-#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
-#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
-#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
-#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
-#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
-#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                 (13U)                                   
-#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
-#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
-#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
-#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
-#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                  (12U)                                   
-#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
-#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
-#define RTC_DR_MU_Pos                  (8U)                                    
-#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
-#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
-#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
-#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
-#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
-#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                  (4U)                                    
-#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
-#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
-#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
-#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                  (0U)                                    
-#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
-#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
-#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
-#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
-#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
-#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                 (23U)                                   
-#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
-#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
-#define RTC_CR_OSEL_Pos                (21U)                                   
-#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
-#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
-#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                 (20U)                                   
-#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
-#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
-#define RTC_CR_COSEL_Pos               (19U)                                   
-#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
-#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
-#define RTC_CR_BCK_Pos                 (18U)                                   
-#define RTC_CR_BCK_Msk                 (0x1U << RTC_CR_BCK_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BCK                     RTC_CR_BCK_Msk                          /*!<  */
-#define RTC_CR_SUB1H_Pos               (17U)                                   
-#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
-#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
-#define RTC_CR_ADD1H_Pos               (16U)                                   
-#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
-#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
-#define RTC_CR_TSIE_Pos                (15U)                                   
-#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
-#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
-#define RTC_CR_WUTIE_Pos               (14U)                                   
-#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
-#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
-#define RTC_CR_ALRBIE_Pos              (13U)                                   
-#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
-#define RTC_CR_ALRAIE_Pos              (12U)                                   
-#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
-#define RTC_CR_TSE_Pos                 (11U)                                   
-#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
-#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
-#define RTC_CR_WUTE_Pos                (10U)                                   
-#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
-#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
-#define RTC_CR_ALRBE_Pos               (9U)                                    
-#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
-#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
-#define RTC_CR_ALRAE_Pos               (8U)                                    
-#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
-#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
-#define RTC_CR_FMT_Pos                 (6U)                                    
-#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
-#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
-#define RTC_CR_BYPSHAD_Pos             (5U)                                    
-#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
-#define RTC_CR_REFCKON_Pos             (4U)                                    
-#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
-#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
-#define RTC_CR_TSEDGE_Pos              (3U)                                    
-#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
-#define RTC_CR_WUCKSEL_Pos             (0U)                                    
-#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
-#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos            (16U)                                   
-#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
-#define RTC_ISR_TAMP2F_Pos             (14U)                                   
-#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
-#define RTC_ISR_TAMP1F_Pos             (13U)                                   
-#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
-#define RTC_ISR_TSOVF_Pos              (12U)                                   
-#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
-#define RTC_ISR_TSF_Pos                (11U)                                   
-#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
-#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
-#define RTC_ISR_WUTF_Pos               (10U)                                   
-#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
-#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
-#define RTC_ISR_ALRBF_Pos              (9U)                                    
-#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
-#define RTC_ISR_ALRAF_Pos              (8U)                                    
-#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
-#define RTC_ISR_INIT_Pos               (7U)                                    
-#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
-#define RTC_ISR_INITF_Pos              (6U)                                    
-#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
-#define RTC_ISR_RSF_Pos                (5U)                                    
-#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
-#define RTC_ISR_INITS_Pos              (4U)                                    
-#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
-#define RTC_ISR_SHPF_Pos               (3U)                                    
-#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
-#define RTC_ISR_WUTWF_Pos              (2U)                                    
-#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
-#define RTC_ISR_ALRBWF_Pos             (1U)                                    
-#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
-#define RTC_ISR_ALRAWF_Pos             (0U)                                    
-#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
-#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
-#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
-#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos               (0U)                                    
-#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
-#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
-#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMAR_DT_Pos              (28U)                                   
-#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
-#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos              (24U)                                   
-#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
-#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
-#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMAR_PM_Pos              (22U)                                   
-#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_Pos              (20U)                                   
-#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
-#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos              (16U)                                   
-#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
-#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
-#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMAR_MNT_Pos             (12U)                                   
-#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
-#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos             (8U)                                    
-#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
-#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
-#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMAR_ST_Pos              (4U)                                    
-#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
-#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos              (0U)                                    
-#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
-#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
-#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
-#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
-#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
-#define RTC_ALRMBR_DT_Pos              (28U)                                   
-#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
-#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos              (24U)                                   
-#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
-#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
-#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
-#define RTC_ALRMBR_PM_Pos              (22U)                                   
-#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_Pos              (20U)                                   
-#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
-#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos              (16U)                                   
-#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
-#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
-#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
-#define RTC_ALRMBR_MNT_Pos             (12U)                                   
-#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
-#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos             (8U)                                    
-#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
-#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
-#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
-#define RTC_ALRMBR_ST_Pos              (4U)                                    
-#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
-#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos              (0U)                                    
-#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
-#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                (0U)                                    
-#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
-#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                 (0U)                                    
-#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
-#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
-#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
-#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
-#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                (22U)                                   
-#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
-#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
-#define RTC_TSTR_HT_Pos                (20U)                                   
-#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
-#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
-#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                (16U)                                   
-#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
-#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
-#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos               (12U)                                   
-#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
-#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
-#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos               (8U)                                    
-#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
-#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                (4U)                                    
-#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
-#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
-#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                (0U)                                    
-#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
-#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
-#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos               (13U)                                   
-#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
-#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                (12U)                                   
-#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
-#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
-#define RTC_TSDR_MU_Pos                (8U)                                    
-#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
-#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                (4U)                                    
-#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
-#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
-#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                (0U)                                    
-#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
-#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
-#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos               (0U)                                    
-#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos              (15U)                                   
-#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
-#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
-#define RTC_CALR_CALW8_Pos             (14U)                                   
-#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
-#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
-#define RTC_CALR_CALW16_Pos            (13U)                                   
-#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
-#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
-#define RTC_CALR_CALM_Pos              (0U)                                    
-#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
-#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
-#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
-
-/* Legacy defines */
-#define RTC_CAL_CALP     RTC_CALR_CALP 
-#define RTC_CAL_CALW8    RTC_CALR_CALW8  
-#define RTC_CAL_CALW16   RTC_CALR_CALW16 
-#define RTC_CAL_CALM     RTC_CALR_CALM 
-#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
-#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
-#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
-#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
-#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
-#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
-#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
-#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
-#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
-#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
-#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
-#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
-#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
-#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
-#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
-#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
-#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
-#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
-#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
-#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
-#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
-#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
-#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
-#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
-#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
-#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
-#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
-#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
-#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
-#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
-#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
-#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
-#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
-#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
-#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
-#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
-#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
-#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
-#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
-#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
-#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
-#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
-#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
-#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
-#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
-#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
-#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
-#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
-#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
-#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
-#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
-#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
-#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos            (0U)                                    
-#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
-#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
-#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
-#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP_Pos             (1U)                                    
-#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
-#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
-#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
-#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
-#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
-
-/* Legacy defines */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                  (0U)                                    
-#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                  (0U)                                    
-#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                  (0U)                                    
-#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                  (0U)                                    
-#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                  (0U)                                    
-#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-#define SPI_I2S_SUPPORT                       /*!< I2S support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)                                       
-#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos            (1U)                                       
-#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos            (2U)                                       
-#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
-#define SPI_CR1_BR_Pos              (3U)                                       
-#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-#define SPI_CR1_SPE_Pos             (6U)                                       
-#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
-#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
-#define SPI_CR1_SSI_Pos             (8U)                                       
-#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos             (9U)                                       
-#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos          (10U)                                      
-#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
-#define SPI_CR1_DFF_Pos             (11U)                                      
-#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
-#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos           (13U)                                      
-#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos          (14U)                                      
-#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
-#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
-#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
-#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)                                       
-#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos             (4U)                                       
-#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)                                       
-#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)                                       
-#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)                                       
-#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)                                       
-#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)                                       
-#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)                                       
-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)                                       
-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)                                       
-#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)                                       
-#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)                                       
-#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)                                       
-#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)                                       
-#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)                                       
-#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
-#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)                                       
-#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
-#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
-#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
-#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
-#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
-#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
-#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
-#define SYSCFG_CFGR2_CAPA_Msk                    (0x7U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
-#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                      (0x1U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
-#define SYSCFG_CFGR2_CAPA_1                      (0x2U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
-#define SYSCFG_CFGR2_CAPA_2                      (0x4U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
-#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
-#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
-#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
-#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
-#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
-#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
-#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
-#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
-#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
-#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
-#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
-#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
-#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
-#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
-#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
-#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
-#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
-#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
-#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
-#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
-#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
-#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
-#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
-#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
-#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
-#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
-#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
-#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
-#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
-#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
-#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
-#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
-#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
-
-/* Legacy defines */
-
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
-*/
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
-    || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#else
-#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
-#endif	
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)                                         
-#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)                                         
-#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)                                         
-#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)                                         
-#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)                                         
-#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)                                         
-#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)                                         
-#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)                                         
-#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos          (3U)                                         
-#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)                                         
-#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)                                         
-#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)                                         
-#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)                                         
-#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)                                         
-#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)                                         
-#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)                                         
-#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)                                        
-#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)                                        
-#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)                                        
-#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)                                         
-#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)                                         
-#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)                                         
-#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)                                         
-#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)                                         
-#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)                                         
-#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)                                         
-#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)                                         
-#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)                                        
-#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)                                        
-#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)                                        
-#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)                                        
-#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)                                         
-#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)                                         
-#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)                                         
-#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)                                         
-#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)                                         
-#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)                                         
-#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)                                         
-#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)                                        
-#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)                                        
-#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)                                        
-#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)                                         
-#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)                                         
-#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)                                         
-#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)                                         
-#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)                                         
-#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos            (6U)                                         
-#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)                                         
-#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
-#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
-#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)                                         
-#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
-#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)                                         
-#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
-#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
-#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)                                        
-#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
-#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
-#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)                                         
-#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
-#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)                                        
-#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)                                         
-#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
-#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
-#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)                                         
-#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
-#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)                                         
-#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
-#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
-#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)                                        
-#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
-#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
-#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)                                         
-#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
-#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)                                        
-#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)                                         
-#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)                                         
-#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos        (3U)                                         
-#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)                                         
-#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)                                         
-#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos        (7U)                                         
-#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)                                         
-#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)                                         
-#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos        (11U)                                        
-#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)                                        
-#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)                                        
-#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)                                        
-#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)                                         
-#define TIM_CNT_CNT_Msk           (0xFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)                                         
-#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)                                         
-#define TIM_ARR_ARR_Msk           (0xFFFFU << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)                                         
-#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)                                         
-#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)                                         
-#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)                                         
-#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)                                         
-#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)                                         
-#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)                                         
-#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP_Pos      (0U)                                          
-#define TIM2_OR_ETR_RMP_Msk      (0x7U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
-#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0        (0x1U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM2_OR_ETR_RMP_1        (0x2U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
-#define TIM2_OR_ETR_RMP_2        (0x4U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
-#define TIM2_OR_TI4_RMP_Pos      (3U)                                          
-#define TIM2_OR_TI4_RMP_Msk      (0x3U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
-#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0        (0x1U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
-#define TIM2_OR_TI4_RMP_1        (0x2U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
-
-#define TIM21_OR_ETR_RMP_Pos      (0U)                                         
-#define TIM21_OR_ETR_RMP_Msk      (0x3U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0        (0x1U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM21_OR_ETR_RMP_1        (0x2U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM21_OR_TI1_RMP_Pos      (2U)                                         
-#define TIM21_OR_TI1_RMP_Msk      (0x7U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
-#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0        (0x1U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM21_OR_TI1_RMP_1        (0x2U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-#define TIM21_OR_TI1_RMP_2        (0x4U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
-#define TIM21_OR_TI2_RMP_Pos      (5U)                                         
-#define TIM21_OR_TI2_RMP_Msk      (0x1U << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
-#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP_Pos      (0U)                                         
-#define TIM22_OR_ETR_RMP_Msk      (0x3U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
-#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0        (0x1U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
-#define TIM22_OR_ETR_RMP_1        (0x2U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
-#define TIM22_OR_TI1_RMP_Pos      (2U)                                         
-#define TIM22_OR_TI1_RMP_Msk      (0x3U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
-#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0        (0x1U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
-#define TIM22_OR_TI1_RMP_1        (0x2U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE_Pos          (0U)                                          
-#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
-#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
-#define TSC_CR_START_Pos         (1U)                                          
-#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
-#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
-#define TSC_CR_AM_Pos            (2U)                                          
-#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
-#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL_Pos       (3U)                                          
-#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
-#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF_Pos         (4U)                                          
-#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
-#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
-
-#define TSC_CR_MCV_Pos           (5U)                                          
-#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
-#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
-#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
-#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
-
-#define TSC_CR_PGPSC_Pos         (12U)                                         
-#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
-#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
-#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
-#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
-
-#define TSC_CR_SSPSC_Pos         (15U)                                         
-#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
-#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE_Pos           (16U)                                         
-#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
-#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD_Pos           (17U)                                         
-#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
-#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
-#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
-#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
-#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
-#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
-#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
-#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
-
-#define TSC_CR_CTPL_Pos          (24U)                                         
-#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
-#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
-#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
-#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
-#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
-
-#define TSC_CR_CTPH_Pos          (28U)                                         
-#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
-#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
-#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
-#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
-#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE_Pos        (0U)                                          
-#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
-#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE_Pos        (1U)                                          
-#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
-#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC_Pos        (0U)                                          
-#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
-#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC_Pos        (1U)                                          
-#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
-#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF_Pos         (0U)                                          
-#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
-#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
-#define TSC_ISR_MCEF_Pos         (1U)                                          
-#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
-#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
-#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
-#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
-#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
-#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
-#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
-#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
-#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
-#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
-#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
-#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
-#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
-#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
-#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
-#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
-#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
-#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
-#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
-#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
-#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
-#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
-#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
-#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
-#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
-#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
-#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
-#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
-#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
-#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
-#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
-#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
-#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
-#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
-#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
-#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
-#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
-#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
-#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
-#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
-#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
-#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
-#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
-#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
-#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
-#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
-#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
-#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
-#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
-#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
-#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
-#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
-#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
-#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
-#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
-#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
-#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
-#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
-#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
-#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
-#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
-#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
-#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
-#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
-#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
-#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
-#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
-#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
-#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
-#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
-#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
-#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
-#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
-#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
-#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
-#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
-#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
-#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
-#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
-#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
-#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
-#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
-#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
-#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
-#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
-#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
-#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
-#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
-#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
-#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
-#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
-#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
-#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
-#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
-#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
-#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
-#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
-#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
-#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
-#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
-#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
-#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
-#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
-#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
-#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
-#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
-#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
-#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
-#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
-#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
-#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
-#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
-#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
-#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
-#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
-#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
-#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
-#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
-#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
-#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
-#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
-#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
-#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
-#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
-#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
-#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
-#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
-#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
-#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
-#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E_Pos       (0U)                                          
-#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
-#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E_Pos       (1U)                                          
-#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
-#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E_Pos       (2U)                                          
-#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
-#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E_Pos       (3U)                                          
-#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
-#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E_Pos       (4U)                                          
-#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
-#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E_Pos       (5U)                                          
-#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
-#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E_Pos       (6U)                                          
-#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
-#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E_Pos       (7U)                                          
-#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
-#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S_Pos       (16U)                                         
-#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
-#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S_Pos       (17U)                                         
-#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
-#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S_Pos       (18U)                                         
-#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
-#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S_Pos       (19U)                                         
-#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
-#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S_Pos       (20U)                                         
-#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
-#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S_Pos       (21U)                                         
-#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
-#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S_Pos       (22U)                                         
-#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
-#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S_Pos       (23U)                                         
-#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
-#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT_Pos       (0U)                                          
-#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
-#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
- */
-/* Note: No specific macro feature on this device */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos              (0U)                                     
-#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
-#define USART_CR1_UESM_Pos            (1U)                                     
-#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos              (2U)                                     
-#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
-#define USART_CR1_TE_Pos              (3U)                                     
-#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos          (4U)                                     
-#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos          (5U)                                     
-#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos            (6U)                                     
-#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)                                     
-#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE_Pos            (8U)                                     
-#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos              (9U)                                     
-#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
-#define USART_CR1_PCE_Pos             (10U)                                    
-#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos            (11U)                                    
-#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos               (12U)                                    
-#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
-#define USART_CR1_M0_Pos              (12U)                                    
-#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos             (13U)                                    
-#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos            (14U)                                    
-#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos           (15U)                                    
-#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos            (16U)                                    
-#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos            (21U)                                    
-#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos           (26U)                                    
-#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos           (27U)                                    
-#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos              (28U)                                    
-#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7_Pos           (4U)                                     
-#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos            (5U)                                     
-#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos           (6U)                                     
-#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)                                     
-#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos            (9U)                                     
-#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos            (10U)                                    
-#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos           (11U)                                    
-#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
-#define USART_CR2_STOP_Pos            (12U)                                    
-#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos           (14U)                                    
-#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos            (15U)                                    
-#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos           (16U)                                    
-#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos           (17U)                                    
-#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos         (18U)                                    
-#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos        (19U)                                    
-#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos           (20U)                                    
-#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos         (21U)                                    
-#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos           (23U)                                    
-#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos             (24U)                                    
-#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)                                     
-#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos            (1U)                                     
-#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos            (2U)                                     
-#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos           (3U)                                     
-#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos            (4U)                                     
-#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos            (5U)                                     
-#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos            (6U)                                     
-#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos            (7U)                                     
-#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos            (8U)                                     
-#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos            (9U)                                     
-#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos           (10U)                                    
-#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos          (11U)                                    
-#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos          (12U)                                    
-#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos            (13U)                                    
-#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos             (14U)                                    
-#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos             (15U)                                    
-#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos         (17U)                                    
-#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos             (20U)                                    
-#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos           (22U)                                    
-#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM_Pos           (23U)                                    
-#define USART_CR3_UCESM_Msk           (0x1U << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
-#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
-#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
-#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)                                     
-#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos             (8U)                                     
-#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos            (0U)                                     
-#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos           (24U)                                    
-#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ_Pos           (0U)                                     
-#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
-#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ_Pos           (1U)                                     
-#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
-#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
-#define USART_RQR_MMRQ_Pos            (2U)                                     
-#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
-#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ_Pos           (3U)                                     
-#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
-#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ_Pos           (4U)                                     
-#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
-#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos              (0U)                                     
-#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
-#define USART_ISR_FE_Pos              (1U)                                     
-#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
-#define USART_ISR_NE_Pos              (2U)                                     
-#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos             (3U)                                     
-#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos            (4U)                                     
-#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
-#define USART_ISR_RXNE_Pos            (5U)                                     
-#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
-#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
-#define USART_ISR_TC_Pos              (6U)                                     
-#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
-#define USART_ISR_TXE_Pos             (7U)                                     
-#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
-#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
-#define USART_ISR_LBDF_Pos            (8U)                                     
-#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos           (9U)                                     
-#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos             (10U)                                    
-#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
-#define USART_ISR_RTOF_Pos            (11U)                                    
-#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos            (12U)                                    
-#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
-#define USART_ISR_ABRE_Pos            (14U)                                    
-#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos            (15U)                                    
-#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos            (16U)                                    
-#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
-#define USART_ISR_CMF_Pos             (17U)                                    
-#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos            (18U)                                    
-#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos             (19U)                                    
-#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos             (20U)                                    
-#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos           (21U)                                    
-#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos           (22U)                                    
-#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos            (0U)                                     
-#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos            (1U)                                     
-#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF_Pos             (2U)                                     
-#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
-#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF_Pos           (3U)                                     
-#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos          (4U)                                     
-#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF_Pos            (6U)                                     
-#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF_Pos           (8U)                                     
-#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos           (9U)                                     
-#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos           (11U)                                    
-#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos           (12U)                                    
-#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF_Pos            (17U)                                    
-#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos            (20U)                                    
-#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)                                     
-#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)                                     
-#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR_Pos           (13U)                                        
-#define USB_PMAADDR_Msk           (0x20003U << USB_PMAADDR_Pos)                /*!< 0x40006000 */
-#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
-#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
-#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
-#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
-#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
-#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
-#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
-#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
-#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
-#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)                                           
-#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0    WWDG_CR_T_0
-#define  WWDG_CR_T1    WWDG_CR_T_1
-#define  WWDG_CR_T2    WWDG_CR_T_2
-#define  WWDG_CR_T3    WWDG_CR_T_3
-#define  WWDG_CR_T4    WWDG_CR_T_4
-#define  WWDG_CR_T5    WWDG_CR_T_5
-#define  WWDG_CR_T6    WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)                                           
-#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)                                           
-#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0    WWDG_CFR_W_0
-#define  WWDG_CFR_W1    WWDG_CFR_W_1
-#define  WWDG_CFR_W2    WWDG_CFR_W_2
-#define  WWDG_CFR_W3    WWDG_CFR_W_3
-#define  WWDG_CFR_W4    WWDG_CFR_W_4
-#define  WWDG_CFR_W5    WWDG_CFR_W_5
-#define  WWDG_CFR_W6    WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)                                           
-#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)                                           
-#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)                                           
-#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
-
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting counting mode selection ********/ 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                             ((INSTANCE) == TIM21)  || \
-                                                             ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                        ((INSTANCE) == TIM21)  || \
-                                                        ((INSTANCE) == TIM22))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                                          ((INSTANCE) == TIM21)  || \
-                                                          ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : Advanced-control timers *****************/
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                                     ((INSTANCE) == TIM21)  || \
-                                                     ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) OCXEC register *****************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-													   
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == LPUART1))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L053xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L0xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral's registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx
-  * @{
-  */
-    
-#ifndef __STM32L0xx_H
-#define __STM32L0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L0)
-#define STM32L0
-#endif /* STM32L0 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
-    !defined (STM32L031xx) && !defined (STM32L041xx) && \
-    !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
-    !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
-    !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
-    !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
-  /* #define STM32L011xx */
-  /* #define STM32L021xx */
-  /* #define STM32L031xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
-  /* #define STM32L041xx */   /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
-  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
-  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
-  #define STM32L053xx   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
-  /* #define STM32L061xx */   /*!< */
-  /* #define STM32L062xx */   /*!< STM32L062K8 */
-  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
-  /* #define STM32L071xx */   /*!< */
-  /* #define STM32L072xx */   /*!< */
-  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
-  /* #define STM32L081xx */   /*!< */
-  /* #define STM32L082xx */   /*!< */
-  /* #define STM32L083xx */   /*!< */ 
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.7.0
-  */
-#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
-                                      |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
-                                      |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
-                                      |(__STM32L0xx_CMSIS_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-#if defined(STM32L011xx)
-  #include "stm32l011xx.h"
-#elif defined(STM32L021xx)
-  #include "stm32l021xx.h"
-#elif defined(STM32L031xx)
-  #include "stm32l031xx.h"
-#elif defined(STM32L041xx)
-  #include "stm32l041xx.h"
-#elif defined(STM32L051xx)
-  #include "stm32l051xx.h"
-#elif defined(STM32L052xx)
-  #include "stm32l052xx.h"
-#elif defined(STM32L053xx)
-  #include "stm32l053xx.h"
-#elif defined(STM32L062xx)
-  #include "stm32l062xx.h"
-#elif defined(STM32L063xx)
-  #include "stm32l063xx.h"
-#elif defined(STM32L061xx)
-  #include "stm32l061xx.h"
-#elif defined(STM32L071xx)
-  #include "stm32l071xx.h"
-#elif defined(STM32L072xx)
-  #include "stm32l072xx.h"
-#elif defined(STM32L073xx)
-  #include "stm32l073xx.h"
-#elif defined(STM32L082xx)
-  #include "stm32l082xx.h"
-#elif defined(STM32L083xx)
-  #include "stm32l083xx.h"
-#elif defined(STM32L081xx)
-  #include "stm32l081xx.h"
-#else
- #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l0xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L0xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_clock.c	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,244 +0,0 @@
-/* mbed Microcontroller Library
-* Copyright (c) 2006-2017 ARM Limited
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
-/**
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------
-  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
-  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
-  *                     | 3- USE_PLL_HSI (internal 16 MHz)
-  *-----------------------------------------------------------------
-  * SYSCLK(MHz)         | 32
-  * AHBCLK (MHz)        | 32
-  * APB1CLK (MHz)       | 32
-  * USB capable         | YES
-  *-----------------------------------------------------------------
-  */
-
-#include "stm32l0xx.h"
-#include "mbed_assert.h"
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x100. */
-
-#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
-#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
-#define USE_PLL_HSI          0x2  // Use HSI internal clock
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-    /*!< Set MSION bit */
-    RCC->CR |= (uint32_t)0x00000100U;
-
-    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-    RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-    RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-    /*!< Reset HSI48ON  bit */
-    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-    /*!< Reset HSEBYP bit */
-    RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-    /*!< Disable all interrupts */
-    RCC->CIER = 0x00000000U;
-
-    /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
-    /* 1- Try to start with HSE and external clock */
-    if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-    {
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
-        /* 2- If fail try to start with HSE and external xtal */
-        if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-        {
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-            /* 3- If fail start with HSI clock */
-            if (SetSysClock_PLL_HSI() == 0)
-#endif
-            {
-                while(1) {
-                    MBED_ASSERT(1);
-                }
-            }
-        }
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
-
-    /* Used to gain time after DeepSleep in case HSI is used */
-    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
-        return 0;
-    }
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __PWR_CLK_ENABLE();
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
-    if (bypass == 0) {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-    } else {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-    }
-    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //if (bypass == 0)
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-    //else
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-    return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __PWR_CLK_ENABLE();
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-    RCC_OscInitStruct.HSICalibrationValue = 16;
-    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-    return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L0XX_H
-#define __SYSTEM_STM32L0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L0xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-/*
-*/
-extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
-extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h	Wed Aug 16 18:27:13 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-#include "common_objects.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1   = (int)USART1_BASE,
+    UART_2   = (int)USART2_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_9
+#define STDIO_UART_RX  PA_10
+#define STDIO_UART     UART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_2  = (int)TIM2_BASE,
+    PWM_21 = (int)TIM21_BASE,
+    PWM_22 = (int)TIM22_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,180 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VLCD, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// TIM21 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+//  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1 - Warning: user_button is on this pin
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
+//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
+    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
+    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
+    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
+//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
+//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
+    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {NC,    NC,      0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {NC,    NC,       0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,146 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VLCD = 0xF2,
+
+    // Arduino connector namings
+    // Note: The Arduino connector is not present on this board.
+    // We keep these definitions for compatibility with Nucleo code examples.
+    A0          = PA_1,
+    A1          = PA_2,
+    A2          = PA_3,
+    A3          = PA_4,
+    A4          = PB_0,
+    A5          = PB_1,
+    D0          = PA_10,
+    D1          = PA_9,
+    D2          = PA_8,
+    D3          = PA_6,
+    D4          = PA_13,
+    D5          = PA_7,
+    D6          = PB_11,
+    D7          = PC_13,
+    D8          = PC_14,
+    D9          = PA_15,
+    D10         = PA_5,
+    D11         = PB_15,
+    D12         = PB_14,
+    D13         = PB_13,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PB_4,
+    LED2        = PA_5,
+    LED3        = PB_4,
+    LED4        = PA_5,
+    USER_BUTTON = PA_0,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PA_9,
+    SERIAL_RX   = PA_10,
+    USBTX       = PA_9,
+    USBRX       = PA_10,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PB_15,
+    SPI_MISO    = PB_14,
+    SPI_SCK     = PB_13,
+    SPI_CS      = PB_12,
+    PWM_OUT     = PB_11,
+
+    //USB pins
+    USB_DM = PA_11,
+    USB_DP = PA_12,
+    USB_NOE = PA_13,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select HSI48 as USB clock source */
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1   = (int)USART1_BASE,
+    UART_2   = (int)USART2_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_2  = (int)TIM2_BASE,
+    PWM_21 = (int)TIM21_BASE,
+    PWM_22 = (int)TIM22_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,195 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+    {ADC_VLCD, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// TIM21 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
+//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
+    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
+    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
+    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
+//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
+//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
+    {PC_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1
+    {PC_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
+    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PC_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PC_5,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
+    {NC,    NC,      0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PD_2,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PA_11, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {NC,    NC,       0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VLCD = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PA_5,
+    LED2        = PA_5,
+    LED3        = PA_5,
+    LED4        = PA_5,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PA_2,
+    SERIAL_RX   = PA_3,
+    USBTX       = PA_2,
+    USBRX       = PA_3,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PB_6,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_DM = PA_11,
+    USB_DP = PA_12,
+    USB_NOE_ALT = PA_13,
+    USB_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select HSI48 as USB clock source */
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,239 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l053xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.5.0
+;* Date               : 8-January-2016
+;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20002000 ; Top of RAM
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TSC
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     LPTIM1_IRQHandler              ; LPTIM1
+                DCD     0                              ; Reserved
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     0                              ; Reserved
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     TIM21_IRQHandler               ; TIM21
+                DCD     0                              ; Reserved
+                DCD     TIM22_IRQHandler               ; TIM22
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
+                DCD     LCD_IRQHandler                 ; LCD
+                DCD     USB_IRQHandler                 ; USB
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_IRQHandler                 [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_CRS_IRQHandler             [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  TSC_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
+                EXPORT  LPTIM1_IRQHandler              [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
+                EXPORT  TIM21_IRQHandler               [WEAK]
+                EXPORT  TIM22_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler                 [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+ADC1_COMP_IRQHandler
+LPTIM1_IRQHandler
+TIM2_IRQHandler
+TIM6_DAC_IRQHandler
+TIM21_IRQHandler
+TIM22_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+RNG_LPUART1_IRQHandler
+LCD_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_MICRO/stm32l053x8.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+LR_IROM1 0x08000000 0x10000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,212 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l053xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.5.0
+;* Date               : 8-January-2016
+;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+__initial_sp    EQU     0x20002000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TSC
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     LPTIM1_IRQHandler              ; LPTIM1
+                DCD     0                              ; Reserved
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     0                              ; Reserved
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     TIM21_IRQHandler               ; TIM21
+                DCD     0                              ; Reserved
+                DCD     TIM22_IRQHandler               ; TIM22
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
+                DCD     LCD_IRQHandler                 ; LCD
+                DCD     USB_IRQHandler                 ; USB
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_IRQHandler                 [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_CRS_IRQHandler             [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  TSC_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
+                EXPORT  LPTIM1_IRQHandler              [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
+                EXPORT  TIM21_IRQHandler               [WEAK]
+                EXPORT  TIM22_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler                 [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+ADC1_COMP_IRQHandler
+LPTIM1_IRQHandler
+TIM2_IRQHandler
+TIM6_DAC_IRQHandler
+TIM21_IRQHandler
+TIM22_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+RNG_LPUART1_IRQHandler
+LCD_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/stm32l053x8.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+LR_IROM1 0x08000000 0x10000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/STM32L053X8.ld	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
+  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 8K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,279 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l053xx.s
+  * @author    MCD Application Team
+  * @version   V1.5.0
+  * @date      8-January-2016
+  * @brief     STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0+ processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0plus
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  bl _start
+
+LoopForever:
+    b LoopForever
+
+
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
+  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
+  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word     TSC_IRQHandler                     /* TSC                           */
+  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
+  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     0                                 /* Reserved                     */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     0                                 /* Reserved                     */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
+  .word     0               				          /* Reserved                     */
+  .word     0              					          /* Reserved                     */
+  .word     TIM21_IRQHandler                  /* TIM21                        */
+  .word     0                                 /* Reserved                     */
+  .word     TIM22_IRQHandler                  /* TIM22                        */
+  .word     I2C1_IRQHandler                   /* I2C1                         */
+  .word     I2C2_IRQHandler                   /* I2C2                         */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
+  .word     LCD_IRQHandler                    /* LCD                          */
+  .word     USB_IRQHandler                    /* USB                          */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_CRS_IRQHandler
+   .thumb_set RCC_CRS_IRQHandler,Default_Handler
+
+   .weak      EXTI0_1_IRQHandler
+   .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_3_IRQHandler
+   .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_15_IRQHandler
+   .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+   .weak      TSC_IRQHandler
+   .thumb_set TSC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_3_IRQHandler
+   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_5_6_7_IRQHandler
+   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
+
+   .weak      ADC1_COMP_IRQHandler
+   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM21_IRQHandler
+   .thumb_set TIM21_IRQHandler,Default_Handler
+
+   .weak      TIM22_IRQHandler
+   .thumb_set TIM22_IRQHandler,Default_Handler
+
+   .weak      I2C1_IRQHandler
+   .thumb_set I2C1_IRQHandler,Default_Handler
+
+   .weak      I2C2_IRQHandler
+   .thumb_set I2C2_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      RNG_LPUART1_IRQHandler
+   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
+
+   .weak      LCD_IRQHandler
+   .thumb_set LCD_IRQHandler,Default_Handler
+
+   .weak      USB_IRQHandler
+   .thumb_set USB_IRQHandler,Default_Handler
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_IAR/startup_stm32l053xx.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,326 @@
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l053xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.5.0
+;* Date               : 8-January-2016
+;* Description        : STM32L053xx Ultra Low Power Devices vector 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Configure the system clock
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TSC
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     LPTIM1_IRQHandler              ; LPTIM1
+                DCD     0                              ; Reserved
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     0                              ; Reserved
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     TIM21_IRQHandler                ; TIM21
+                DCD     0                              ; Reserved
+                DCD     TIM22_IRQHandler               ; TIM22
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
+                DCD     LCD_IRQHandler                 ; LCD
+                DCD     USB_IRQHandler                 ; USB
+                
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+       
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+                
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+                
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+                
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+                
+        PUBWEAK RCC_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_CRS_IRQHandler
+        B RCC_CRS_IRQHandler
+        
+                
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+        
+                
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+        
+                
+        PUBWEAK EXTI4_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+        B EXTI4_15_IRQHandler
+        
+                
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+        B DMA1_Channel2_3_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_6_7_IRQHandler
+        B DMA1_Channel4_5_6_7_IRQHandler
+        
+                
+        PUBWEAK ADC1_COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_COMP_IRQHandler
+        B ADC1_COMP_IRQHandler
+        
+                 
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+        
+                
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+                
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+        
+        PUBWEAK TIM21_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM21_IRQHandler
+        B TIM21_IRQHandler
+
+        PUBWEAK TIM22_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM22_IRQHandler
+        B TIM22_IRQHandler
+        
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+        
+                
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+        
+                
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+                
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+                
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+                
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+
+        PUBWEAK RNG_LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_LPUART1_IRQHandler
+        B RNG_LPUART1_IRQHandler
+        
+        
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,30 @@
+/* [ROM = 64kb = 0x10000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x0800FFFF;
+
+/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x200000C0;
+define symbol __region_RAM_end__      = 0x20001FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__   = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/cmsis.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l0xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/cmsis_nvic.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
+// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+#define NVIC_NUM_VECTORS        48
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000    // Vectors positioned at start of RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,65 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l0xx.h"
+#include "stm32l0xx_ll_tim.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM21
+#define TIM_MST_IRQ  TIM21_IRQn
+#define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
+
+#define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  2 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l053xx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,7508 @@
+/**
+  ******************************************************************************
+  * @file    stm32l053xx.h
+  * @author  MCD Application Team
+  * @version V1.7.0
+  * @date    31-May-2016
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for stm32l053xx devices.  
+  *          
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l053xx
+  * @{
+  */
+    
+#ifndef __STM32L053xx_H
+#define __STM32L053xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+/**
+  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
+  */
+#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */
+#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
+#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/**
+  * @}
+  */
+   
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+   
+/**
+ * @brief stm32l053xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
+
+/******  STM32L-0 specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
+  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
+  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
+  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
+  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
+  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
+  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
+  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
+__IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
+uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
+uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
+__IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
+uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
+__IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
+__IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System 
+  */
+
+typedef struct 
+{
+__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
+  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
+  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} DMA_TypeDef;                                                                  
+                                                                                
+typedef struct                                                                  
+{                                                                               
+  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
+} DMA_Request_TypeDef;                                                          
+                                                                                
+/**                                                                             
+  * @brief External Interrupt/Event Controller                                  
+  */                                                                            
+                                                                                
+typedef struct                                                                  
+{                                                                               
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
+  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
+  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
+  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
+  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
+  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
+  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
+  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
+  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
+  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
+  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
+} OB_TypeDef;
+  
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
+  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
+  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
+  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/** 
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
+  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
+  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
+       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
+  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
+} SYSCFG_TypeDef;
+
+
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/** 
+  * @brief LCD
+  */
+typedef struct
+{
+  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/** 
+  * @brief MIFARE Firewall
+  */
+typedef struct
+{
+  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
+  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
+  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
+  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
+ 
+} FIREWALL_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
+  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
+  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
+  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
+  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
+  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
+  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
+  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
+  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
+  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
+  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
+  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
+  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
+  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
+  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
+  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Random numbers generator
+  */
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
+  __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
+  __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
+  __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
+  __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
+  __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
+  __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
+  __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
+  __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
+  __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
+  __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
+  __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
+  uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
+  __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
+  __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
+  __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
+  __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
+  uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
+  __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
+  __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
+  __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Universal Serial Bus Full Speed Device
+  */
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
+  __IO uint16_t RESERVED0;       /*!< Reserved */     
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */       
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */       
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
+  __IO uint16_t RESERVED3;       /*!< Reserved */       
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */       
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */       
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */       
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */       
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */       
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */       
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */       
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */       
+  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
+  __IO uint16_t RESERVEDD;       /*!< Reserved */       
+  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
+  __IO uint16_t RESERVEDE;       /*!< Reserved */       
+} USB_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE             ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
+#define FLASH_END              ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
+#define DATA_EEPROM_BASE       ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END        ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE              ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX          ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE            ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)
+#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000U)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000U)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000U)
+#define LCD_BASE              (APBPERIPH_BASE + 0x00002400U)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800U)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000U)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800U)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400U)
+#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800U)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400U)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800U)
+#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00U)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000U)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00007400U)
+#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00U)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000U)
+#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018U)
+#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CU)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400U)
+#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800U)
+#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400U)
+#define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00U)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400U)
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708U)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000U)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800U)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800U)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8U)
+
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FF80000U)        /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FF8007CU)        /*!< FLASH Size register base address */
+#define UID_BASE              ((uint32_t)0x1FF80050U)        /*!< Unique device ID register base address  */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000U)
+#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000U)
+
+#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000U)
+#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400U)
+#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800U)
+#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00U)
+#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00U)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC                 ADC1_COMMON
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB                 ((USB_TypeDef *) USB_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_EOCAL_Pos          (11U)                                       
+#define ADC_ISR_EOCAL_Msk          (0x1U << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
+#define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos            (7U)                                        
+#define ADC_ISR_AWD_Msk            (0x1U << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
+#define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos            (4U)                                        
+#define ADC_ISR_OVR_Msk            (0x1U << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
+#define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos          (3U)                                        
+#define ADC_ISR_EOSEQ_Msk          (0x1U << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos            (2U)                                        
+#define ADC_ISR_EOC_Msk            (0x1U << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
+#define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos          (1U)                                        
+#define ADC_ISR_EOSMP_Msk          (0x1U << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
+#define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos          (0U)                                        
+#define ADC_ISR_ADRDY_Msk          (0x1U << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
+#define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_EOCALIE_Pos        (11U)                                       
+#define ADC_IER_EOCALIE_Msk        (0x1U << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
+#define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos          (7U)                                        
+#define ADC_IER_AWDIE_Msk          (0x1U << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
+#define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos          (4U)                                        
+#define ADC_IER_OVRIE_Msk          (0x1U << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
+#define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos        (3U)                                        
+#define ADC_IER_EOSEQIE_Msk        (0x1U << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos          (2U)                                        
+#define ADC_IER_EOCIE_Msk          (0x1U << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
+#define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos        (1U)                                        
+#define ADC_IER_EOSMPIE_Msk        (0x1U << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos        (0U)                                        
+#define ADC_IER_ADRDYIE_Msk        (0x1U << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL_Pos           (31U)                                       
+#define ADC_CR_ADCAL_Msk           (0x1U << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
+#define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos        (28U)                                       
+#define ADC_CR_ADVREGEN_Msk        (0x1U << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos           (4U)                                        
+#define ADC_CR_ADSTP_Msk           (0x1U << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
+#define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos         (2U)                                        
+#define ADC_CR_ADSTART_Msk         (0x1U << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
+#define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos           (1U)                                        
+#define ADC_CR_ADDIS_Msk           (0x1U << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
+#define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos            (0U)                                        
+#define ADC_CR_ADEN_Msk            (0x1U << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
+#define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define ADC_CFGR1_AWDCH_Pos        (26U)                                       
+#define ADC_CFGR1_AWDCH_Msk        (0x1FU << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0          (0x01U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1          (0x02U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2          (0x04U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3          (0x08U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4          (0x10U << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos        (23U)                                       
+#define ADC_CFGR1_AWDEN_Msk        (0x1U << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos       (22U)                                       
+#define ADC_CFGR1_AWDSGL_Msk       (0x1U << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
+#define ADC_CFGR1_DISCEN_Pos       (16U)                                       
+#define ADC_CFGR1_DISCEN_Msk       (0x1U << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos       (15U)                                       
+#define ADC_CFGR1_AUTOFF_Msk       (0x1U << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos         (14U)                                       
+#define ADC_CFGR1_WAIT_Msk         (0x1U << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos         (13U)                                       
+#define ADC_CFGR1_CONT_Msk         (0x1U << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
+#define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos       (12U)                                       
+#define ADC_CFGR1_OVRMOD_Msk       (0x1U << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos        (10U)                                       
+#define ADC_CFGR1_EXTEN_Msk        (0x3U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0          (0x1U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1          (0x2U << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos       (6U)                                        
+#define ADC_CFGR1_EXTSEL_Msk       (0x7U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0         (0x1U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1         (0x2U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2         (0x4U << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos        (5U)                                        
+#define ADC_CFGR1_ALIGN_Msk        (0x1U << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos          (3U)                                        
+#define ADC_CFGR1_RES_Msk          (0x3U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
+#define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0            (0x1U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1            (0x2U << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos      (2U)                                        
+#define ADC_CFGR1_SCANDIR_Msk      (0x1U << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos       (1U)                                        
+#define ADC_CFGR1_DMACFG_Msk       (0x1U << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos        (0U)                                        
+#define ADC_CFGR1_DMAEN_Msk        (0x1U << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_TOVS_Pos         (9U)                                        
+#define ADC_CFGR2_TOVS_Msk         (0x400001U << ADC_CFGR2_TOVS_Pos)           /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos         (5U)                                        
+#define ADC_CFGR2_OVSS_Msk         (0xFU << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0           (0x1U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1           (0x2U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2           (0x4U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3           (0x8U << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos         (2U)                                        
+#define ADC_CFGR2_OVSR_Msk         (0x7U << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0           (0x1U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1           (0x2U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2           (0x4U << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos         (0U)                                        
+#define ADC_CFGR2_OVSE_Msk         (0x1U << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos       (30U)                                       
+#define ADC_CFGR2_CKMODE_Msk       (0x3U << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0         (0x1U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1         (0x2U << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
+
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define ADC_SMPR_SMP_Pos           (0U)                                        
+#define ADC_SMPR_SMP_Msk           (0x7U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
+#define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0             (0x1U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1             (0x2U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2             (0x4U << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
+
+/*******************  Bit definition for ADC_TR register  ********************/
+#define ADC_TR_HT_Pos              (16U)                                       
+#define ADC_TR_HT_Msk              (0xFFFU << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
+#define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos              (0U)                                        
+#define ADC_TR_LT_Msk              (0xFFFU << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
+#define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define ADC_CHSELR_CHSEL_Pos       (0U)                                        
+#define ADC_CHSELR_CHSEL_Msk       (0x7FFFFU << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos     (18U)                                       
+#define ADC_CHSELR_CHSEL18_Msk     (0x1U << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos     (17U)                                       
+#define ADC_CHSELR_CHSEL17_Msk     (0x1U << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16_Pos     (16U)                                       
+#define ADC_CHSELR_CHSEL16_Msk     (0x1U << ADC_CHSELR_CHSEL16_Pos)            /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16         ADC_CHSELR_CHSEL16_Msk                      /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15_Pos     (15U)                                       
+#define ADC_CHSELR_CHSEL15_Msk     (0x1U << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos     (14U)                                       
+#define ADC_CHSELR_CHSEL14_Msk     (0x1U << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos     (13U)                                       
+#define ADC_CHSELR_CHSEL13_Msk     (0x1U << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos     (12U)                                       
+#define ADC_CHSELR_CHSEL12_Msk     (0x1U << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos     (11U)                                       
+#define ADC_CHSELR_CHSEL11_Msk     (0x1U << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos     (10U)                                       
+#define ADC_CHSELR_CHSEL10_Msk     (0x1U << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos      (9U)                                        
+#define ADC_CHSELR_CHSEL9_Msk      (0x1U << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos      (8U)                                        
+#define ADC_CHSELR_CHSEL8_Msk      (0x1U << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos      (7U)                                        
+#define ADC_CHSELR_CHSEL7_Msk      (0x1U << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos      (6U)                                        
+#define ADC_CHSELR_CHSEL6_Msk      (0x1U << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos      (5U)                                        
+#define ADC_CHSELR_CHSEL5_Msk      (0x1U << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos      (4U)                                        
+#define ADC_CHSELR_CHSEL4_Msk      (0x1U << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos      (3U)                                        
+#define ADC_CHSELR_CHSEL3_Msk      (0x1U << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos      (2U)                                        
+#define ADC_CHSELR_CHSEL2_Msk      (0x1U << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos      (1U)                                        
+#define ADC_CHSELR_CHSEL1_Msk      (0x1U << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos      (0U)                                        
+#define ADC_CHSELR_CHSEL0_Msk      (0x1U << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_DATA_Pos            (0U)                                        
+#define ADC_DR_DATA_Msk            (0xFFFFU << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
+#define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_Pos    (0U)                                        
+#define ADC_CALFACT_CALFACT_Msk    (0x7FU << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_LFMEN_Pos          (25U)                                       
+#define ADC_CCR_LFMEN_Msk          (0x1U << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
+#define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN_Pos         (24U)                                       
+#define ADC_CCR_VLCDEN_Msk         (0x1U << ADC_CCR_VLCDEN_Pos)                /*!< 0x01000000 */
+#define ADC_CCR_VLCDEN             ADC_CCR_VLCDEN_Msk                          /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN_Pos           (23U)                                       
+#define ADC_CCR_TSEN_Msk           (0x1U << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
+#define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos         (22U)                                       
+#define ADC_CCR_VREFEN_Msk         (0x1U << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
+#define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos          (18U)                                       
+#define ADC_CCR_PRESC_Msk          (0xFU << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
+#define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0            (0x1U << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1            (0x2U << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2            (0x4U << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3            (0x8U << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos           (0U)                                    
+#define COMP_CSR_COMP1EN_Msk           (0x1U << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos       (4U)                                    
+#define COMP_CSR_COMP1INNSEL_Msk       (0x3U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0         (0x1U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1         (0x2U << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos           (8U)                                    
+#define COMP_CSR_COMP1WM_Msk           (0x1U << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)                                   
+#define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos     (15U)                                   
+#define COMP_CSR_COMP1POLARITY_Msk     (0x1U << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos        (30U)                                   
+#define COMP_CSR_COMP1VALUE_Msk        (0x1U << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos         (31U)                                   
+#define COMP_CSR_COMP1LOCK_Msk         (0x1U << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos           (0U)                                    
+#define COMP_CSR_COMP2EN_Msk           (0x1U << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos        (3U)                                    
+#define COMP_CSR_COMP2SPEED_Msk        (0x1U << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos       (4U)                                    
+#define COMP_CSR_COMP2INNSEL_Msk       (0x7U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0         (0x1U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1         (0x2U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2         (0x4U << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos       (8U)                                    
+#define COMP_CSR_COMP2INPSEL_Msk       (0x7U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0         (0x1U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1         (0x2U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2         (0x4U << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)                                   
+#define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)                                   
+#define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos     (15U)                                   
+#define COMP_CSR_COMP2POLARITY_Msk     (0x1U << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos        (30U)                                   
+#define COMP_CSR_COMP2VALUE_Msk        (0x1U << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos         (31U)                                   
+#define COMP_CSR_COMP2LOCK_Msk         (0x1U << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
+
+/**********************  Bit definition for COMP_CSR register common  ****************/
+#define COMP_CSR_COMPxEN_Pos           (0U)                                    
+#define COMP_CSR_COMPxEN_Msk           (0x1U << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos     (15U)                                   
+#define COMP_CSR_COMPxPOLARITY_Msk     (0x1U << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos     (30U)                                   
+#define COMP_CSR_COMPxOUTVALUE_Msk     (0x1U << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos         (31U)                                   
+#define COMP_CSR_COMPxLOCK_Msk         (0x1U << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
+#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
+#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
+#define CRS_CR_ERRIE_Pos          (2U)                                         
+#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
+#define CRS_CR_ESYNCIE_Pos        (3U)                                         
+#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos            (5U)                                         
+#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
+#define CRS_CR_SWSYNC_Pos         (7U)                                         
+#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
+#define CRS_CR_TRIM_Pos           (8U)                                         
+#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)                                         
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
+#define CRS_CFGR_FELIM_Pos        (16U)                                        
+#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
+#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
+#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
+#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
+#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
+#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
+  
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
+#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
+#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
+#define CRS_ISR_ERRF_Pos          (2U)                                         
+#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
+#define CRS_ISR_ESYNCF_Pos        (3U)                                         
+#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
+#define CRS_ISR_SYNCERR_Pos       (8U)                                         
+#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
+#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
+#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
+#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
+#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)                                        
+#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
+#define CRS_ISR_FECAP_Pos         (16U)                                        
+#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
+#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
+#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
+#define CRS_ICR_ERRC_Pos          (2U)                                         
+#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
+#define CRS_ICR_ESYNCC_Pos        (3U)                                         
+#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos            (1U)                                       
+#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR           ((uint16_t)0x00000FFFU)                    /*!< DAC channel1 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0                 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1                 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2                 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3                 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4                 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5                 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6                 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7                 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8                 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9                 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10                (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11                (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12                (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13                (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14                (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15                (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define DBGMCU_CR_DBG_Pos                      (0U)                            
+#define DBGMCU_CR_DBG_Msk                      (0x7U << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
+#define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)                            
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)                            
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)                           
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)                           
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)                           
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)                           
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)                           
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)                           
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)                            
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)                            
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */ 
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */ 
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */ 
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */ 
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */ 
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */ 
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_IM0_Pos        (0U)                                           
+#define EXTI_IMR_IM0_Msk        (0x1U << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
+#define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
+#define EXTI_IMR_IM1_Pos        (1U)                                           
+#define EXTI_IMR_IM1_Msk        (0x1U << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
+#define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
+#define EXTI_IMR_IM2_Pos        (2U)                                           
+#define EXTI_IMR_IM2_Msk        (0x1U << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
+#define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
+#define EXTI_IMR_IM3_Pos        (3U)                                           
+#define EXTI_IMR_IM3_Msk        (0x1U << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
+#define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
+#define EXTI_IMR_IM4_Pos        (4U)                                           
+#define EXTI_IMR_IM4_Msk        (0x1U << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
+#define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
+#define EXTI_IMR_IM5_Pos        (5U)                                           
+#define EXTI_IMR_IM5_Msk        (0x1U << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
+#define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
+#define EXTI_IMR_IM6_Pos        (6U)                                           
+#define EXTI_IMR_IM6_Msk        (0x1U << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
+#define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
+#define EXTI_IMR_IM7_Pos        (7U)                                           
+#define EXTI_IMR_IM7_Msk        (0x1U << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
+#define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
+#define EXTI_IMR_IM8_Pos        (8U)                                           
+#define EXTI_IMR_IM8_Msk        (0x1U << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
+#define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
+#define EXTI_IMR_IM9_Pos        (9U)                                           
+#define EXTI_IMR_IM9_Msk        (0x1U << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
+#define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
+#define EXTI_IMR_IM10_Pos       (10U)                                          
+#define EXTI_IMR_IM10_Msk       (0x1U << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
+#define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos       (11U)                                          
+#define EXTI_IMR_IM11_Msk       (0x1U << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
+#define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos       (12U)                                          
+#define EXTI_IMR_IM12_Msk       (0x1U << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
+#define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos       (13U)                                          
+#define EXTI_IMR_IM13_Msk       (0x1U << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
+#define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos       (14U)                                          
+#define EXTI_IMR_IM14_Msk       (0x1U << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
+#define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos       (15U)                                          
+#define EXTI_IMR_IM15_Msk       (0x1U << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
+#define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos       (16U)                                          
+#define EXTI_IMR_IM16_Msk       (0x1U << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
+#define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos       (17U)                                          
+#define EXTI_IMR_IM17_Msk       (0x1U << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
+#define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos       (18U)                                          
+#define EXTI_IMR_IM18_Msk       (0x1U << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
+#define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos       (19U)                                          
+#define EXTI_IMR_IM19_Msk       (0x1U << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
+#define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos       (20U)                                          
+#define EXTI_IMR_IM20_Msk       (0x1U << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
+#define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos       (21U)                                          
+#define EXTI_IMR_IM21_Msk       (0x1U << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
+#define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos       (22U)                                          
+#define EXTI_IMR_IM22_Msk       (0x1U << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
+#define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos       (23U)                                          
+#define EXTI_IMR_IM23_Msk       (0x1U << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
+#define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos       (25U)                                          
+#define EXTI_IMR_IM25_Msk       (0x1U << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
+#define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos       (26U)                                          
+#define EXTI_IMR_IM26_Msk       (0x1U << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
+#define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos       (28U)                                          
+#define EXTI_IMR_IM28_Msk       (0x1U << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
+#define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos       (29U)                                          
+#define EXTI_IMR_IM29_Msk       (0x1U << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
+#define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos         (0U)                                           
+#define EXTI_IMR_IM_Msk         (0x36FFFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define EXTI_EMR_EM0_Pos        (0U)                                           
+#define EXTI_EMR_EM0_Msk        (0x1U << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
+#define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
+#define EXTI_EMR_EM1_Pos        (1U)                                           
+#define EXTI_EMR_EM1_Msk        (0x1U << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
+#define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
+#define EXTI_EMR_EM2_Pos        (2U)                                           
+#define EXTI_EMR_EM2_Msk        (0x1U << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
+#define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
+#define EXTI_EMR_EM3_Pos        (3U)                                           
+#define EXTI_EMR_EM3_Msk        (0x1U << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
+#define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
+#define EXTI_EMR_EM4_Pos        (4U)                                           
+#define EXTI_EMR_EM4_Msk        (0x1U << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
+#define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
+#define EXTI_EMR_EM5_Pos        (5U)                                           
+#define EXTI_EMR_EM5_Msk        (0x1U << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
+#define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
+#define EXTI_EMR_EM6_Pos        (6U)                                           
+#define EXTI_EMR_EM6_Msk        (0x1U << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
+#define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
+#define EXTI_EMR_EM7_Pos        (7U)                                           
+#define EXTI_EMR_EM7_Msk        (0x1U << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
+#define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
+#define EXTI_EMR_EM8_Pos        (8U)                                           
+#define EXTI_EMR_EM8_Msk        (0x1U << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
+#define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
+#define EXTI_EMR_EM9_Pos        (9U)                                           
+#define EXTI_EMR_EM9_Msk        (0x1U << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
+#define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
+#define EXTI_EMR_EM10_Pos       (10U)                                          
+#define EXTI_EMR_EM10_Msk       (0x1U << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
+#define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos       (11U)                                          
+#define EXTI_EMR_EM11_Msk       (0x1U << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
+#define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos       (12U)                                          
+#define EXTI_EMR_EM12_Msk       (0x1U << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
+#define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos       (13U)                                          
+#define EXTI_EMR_EM13_Msk       (0x1U << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
+#define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos       (14U)                                          
+#define EXTI_EMR_EM14_Msk       (0x1U << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
+#define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos       (15U)                                          
+#define EXTI_EMR_EM15_Msk       (0x1U << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
+#define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos       (16U)                                          
+#define EXTI_EMR_EM16_Msk       (0x1U << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
+#define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos       (17U)                                          
+#define EXTI_EMR_EM17_Msk       (0x1U << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
+#define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos       (18U)                                          
+#define EXTI_EMR_EM18_Msk       (0x1U << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
+#define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos       (19U)                                          
+#define EXTI_EMR_EM19_Msk       (0x1U << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
+#define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos       (20U)                                          
+#define EXTI_EMR_EM20_Msk       (0x1U << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
+#define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos       (21U)                                          
+#define EXTI_EMR_EM21_Msk       (0x1U << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
+#define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos       (22U)                                          
+#define EXTI_EMR_EM22_Msk       (0x1U << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
+#define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos       (23U)                                          
+#define EXTI_EMR_EM23_Msk       (0x1U << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
+#define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos       (25U)                                          
+#define EXTI_EMR_EM25_Msk       (0x1U << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
+#define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos       (26U)                                          
+#define EXTI_EMR_EM26_Msk       (0x1U << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
+#define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos       (28U)                                          
+#define EXTI_EMR_EM28_Msk       (0x1U << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
+#define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos       (29U)                                          
+#define EXTI_EMR_EM29_Msk       (0x1U << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
+#define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define EXTI_RTSR_RT0_Pos       (0U)                                           
+#define EXTI_RTSR_RT0_Msk       (0x1U << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
+#define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos       (1U)                                           
+#define EXTI_RTSR_RT1_Msk       (0x1U << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
+#define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos       (2U)                                           
+#define EXTI_RTSR_RT2_Msk       (0x1U << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
+#define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos       (3U)                                           
+#define EXTI_RTSR_RT3_Msk       (0x1U << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
+#define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos       (4U)                                           
+#define EXTI_RTSR_RT4_Msk       (0x1U << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
+#define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos       (5U)                                           
+#define EXTI_RTSR_RT5_Msk       (0x1U << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
+#define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos       (6U)                                           
+#define EXTI_RTSR_RT6_Msk       (0x1U << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
+#define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos       (7U)                                           
+#define EXTI_RTSR_RT7_Msk       (0x1U << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
+#define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos       (8U)                                           
+#define EXTI_RTSR_RT8_Msk       (0x1U << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
+#define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos       (9U)                                           
+#define EXTI_RTSR_RT9_Msk       (0x1U << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
+#define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos      (10U)                                          
+#define EXTI_RTSR_RT10_Msk      (0x1U << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
+#define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos      (11U)                                          
+#define EXTI_RTSR_RT11_Msk      (0x1U << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
+#define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos      (12U)                                          
+#define EXTI_RTSR_RT12_Msk      (0x1U << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
+#define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos      (13U)                                          
+#define EXTI_RTSR_RT13_Msk      (0x1U << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
+#define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos      (14U)                                          
+#define EXTI_RTSR_RT14_Msk      (0x1U << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
+#define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos      (15U)                                          
+#define EXTI_RTSR_RT15_Msk      (0x1U << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
+#define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos      (16U)                                          
+#define EXTI_RTSR_RT16_Msk      (0x1U << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
+#define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos      (17U)                                          
+#define EXTI_RTSR_RT17_Msk      (0x1U << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
+#define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos      (19U)                                          
+#define EXTI_RTSR_RT19_Msk      (0x1U << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
+#define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos      (20U)                                          
+#define EXTI_RTSR_RT20_Msk      (0x1U << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
+#define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos      (21U)                                          
+#define EXTI_RTSR_RT21_Msk      (0x1U << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
+#define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos      (22U)                                          
+#define EXTI_RTSR_RT22_Msk      (0x1U << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
+#define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos       (0U)                                           
+#define EXTI_FTSR_FT0_Msk       (0x1U << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
+#define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos       (1U)                                           
+#define EXTI_FTSR_FT1_Msk       (0x1U << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
+#define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos       (2U)                                           
+#define EXTI_FTSR_FT2_Msk       (0x1U << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
+#define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos       (3U)                                           
+#define EXTI_FTSR_FT3_Msk       (0x1U << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
+#define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos       (4U)                                           
+#define EXTI_FTSR_FT4_Msk       (0x1U << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
+#define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos       (5U)                                           
+#define EXTI_FTSR_FT5_Msk       (0x1U << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
+#define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos       (6U)                                           
+#define EXTI_FTSR_FT6_Msk       (0x1U << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
+#define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos       (7U)                                           
+#define EXTI_FTSR_FT7_Msk       (0x1U << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
+#define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos       (8U)                                           
+#define EXTI_FTSR_FT8_Msk       (0x1U << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
+#define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos       (9U)                                           
+#define EXTI_FTSR_FT9_Msk       (0x1U << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
+#define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos      (10U)                                          
+#define EXTI_FTSR_FT10_Msk      (0x1U << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
+#define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos      (11U)                                          
+#define EXTI_FTSR_FT11_Msk      (0x1U << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
+#define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos      (12U)                                          
+#define EXTI_FTSR_FT12_Msk      (0x1U << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
+#define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos      (13U)                                          
+#define EXTI_FTSR_FT13_Msk      (0x1U << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
+#define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos      (14U)                                          
+#define EXTI_FTSR_FT14_Msk      (0x1U << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
+#define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos      (15U)                                          
+#define EXTI_FTSR_FT15_Msk      (0x1U << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
+#define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos      (16U)                                          
+#define EXTI_FTSR_FT16_Msk      (0x1U << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
+#define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos      (17U)                                          
+#define EXTI_FTSR_FT17_Msk      (0x1U << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
+#define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos      (19U)                                          
+#define EXTI_FTSR_FT19_Msk      (0x1U << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
+#define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos      (20U)                                          
+#define EXTI_FTSR_FT20_Msk      (0x1U << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
+#define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos      (21U)                                          
+#define EXTI_FTSR_FT21_Msk      (0x1U << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
+#define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos      (22U)                                          
+#define EXTI_FTSR_FT22_Msk      (0x1U << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
+#define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos     (0U)                                           
+#define EXTI_SWIER_SWI0_Msk     (0x1U << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
+#define EXTI_SWIER_SWI1_Pos     (1U)                                           
+#define EXTI_SWIER_SWI1_Msk     (0x1U << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
+#define EXTI_SWIER_SWI2_Pos     (2U)                                           
+#define EXTI_SWIER_SWI2_Msk     (0x1U << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
+#define EXTI_SWIER_SWI3_Pos     (3U)                                           
+#define EXTI_SWIER_SWI3_Msk     (0x1U << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
+#define EXTI_SWIER_SWI4_Pos     (4U)                                           
+#define EXTI_SWIER_SWI4_Msk     (0x1U << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
+#define EXTI_SWIER_SWI5_Pos     (5U)                                           
+#define EXTI_SWIER_SWI5_Msk     (0x1U << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
+#define EXTI_SWIER_SWI6_Pos     (6U)                                           
+#define EXTI_SWIER_SWI6_Msk     (0x1U << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
+#define EXTI_SWIER_SWI7_Pos     (7U)                                           
+#define EXTI_SWIER_SWI7_Msk     (0x1U << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
+#define EXTI_SWIER_SWI8_Pos     (8U)                                           
+#define EXTI_SWIER_SWI8_Msk     (0x1U << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
+#define EXTI_SWIER_SWI9_Pos     (9U)                                           
+#define EXTI_SWIER_SWI9_Msk     (0x1U << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
+#define EXTI_SWIER_SWI10_Pos    (10U)                                          
+#define EXTI_SWIER_SWI10_Msk    (0x1U << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos    (11U)                                          
+#define EXTI_SWIER_SWI11_Msk    (0x1U << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos    (12U)                                          
+#define EXTI_SWIER_SWI12_Msk    (0x1U << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos    (13U)                                          
+#define EXTI_SWIER_SWI13_Msk    (0x1U << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos    (14U)                                          
+#define EXTI_SWIER_SWI14_Msk    (0x1U << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos    (15U)                                          
+#define EXTI_SWIER_SWI15_Msk    (0x1U << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos    (16U)                                          
+#define EXTI_SWIER_SWI16_Msk    (0x1U << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos    (17U)                                          
+#define EXTI_SWIER_SWI17_Msk    (0x1U << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos    (19U)                                          
+#define EXTI_SWIER_SWI19_Msk    (0x1U << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos    (20U)                                          
+#define EXTI_SWIER_SWI20_Msk    (0x1U << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos    (21U)                                          
+#define EXTI_SWIER_SWI21_Msk    (0x1U << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos    (22U)                                          
+#define EXTI_SWIER_SWI22_Msk    (0x1U << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define EXTI_PR_PIF0_Pos        (0U)                                           
+#define EXTI_PR_PIF0_Msk        (0x1U << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
+#define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
+#define EXTI_PR_PIF1_Pos        (1U)                                           
+#define EXTI_PR_PIF1_Msk        (0x1U << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
+#define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
+#define EXTI_PR_PIF2_Pos        (2U)                                           
+#define EXTI_PR_PIF2_Msk        (0x1U << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
+#define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
+#define EXTI_PR_PIF3_Pos        (3U)                                           
+#define EXTI_PR_PIF3_Msk        (0x1U << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
+#define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
+#define EXTI_PR_PIF4_Pos        (4U)                                           
+#define EXTI_PR_PIF4_Msk        (0x1U << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
+#define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
+#define EXTI_PR_PIF5_Pos        (5U)                                           
+#define EXTI_PR_PIF5_Msk        (0x1U << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
+#define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
+#define EXTI_PR_PIF6_Pos        (6U)                                           
+#define EXTI_PR_PIF6_Msk        (0x1U << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
+#define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
+#define EXTI_PR_PIF7_Pos        (7U)                                           
+#define EXTI_PR_PIF7_Msk        (0x1U << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
+#define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
+#define EXTI_PR_PIF8_Pos        (8U)                                           
+#define EXTI_PR_PIF8_Msk        (0x1U << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
+#define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
+#define EXTI_PR_PIF9_Pos        (9U)                                           
+#define EXTI_PR_PIF9_Msk        (0x1U << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
+#define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
+#define EXTI_PR_PIF10_Pos       (10U)                                          
+#define EXTI_PR_PIF10_Msk       (0x1U << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
+#define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos       (11U)                                          
+#define EXTI_PR_PIF11_Msk       (0x1U << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
+#define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos       (12U)                                          
+#define EXTI_PR_PIF12_Msk       (0x1U << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
+#define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos       (13U)                                          
+#define EXTI_PR_PIF13_Msk       (0x1U << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
+#define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos       (14U)                                          
+#define EXTI_PR_PIF14_Msk       (0x1U << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
+#define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos       (15U)                                          
+#define EXTI_PR_PIF15_Msk       (0x1U << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
+#define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos       (16U)                                          
+#define EXTI_PR_PIF16_Msk       (0x1U << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
+#define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos       (17U)                                          
+#define EXTI_PR_PIF17_Msk       (0x1U << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
+#define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos       (19U)                                          
+#define EXTI_PR_PIF19_Msk       (0x1U << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
+#define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos       (20U)                                          
+#define EXTI_PR_PIF20_Msk       (0x1U << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
+#define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos       (21U)                                          
+#define EXTI_PR_PIF21_Msk       (0x1U << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
+#define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos       (22U)                                          
+#define EXTI_PR_PIF22_Msk       (0x1U << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
+#define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0                         EXTI_PR_PIF0
+#define EXTI_PR_PR1                         EXTI_PR_PIF1
+#define EXTI_PR_PR2                         EXTI_PR_PIF2
+#define EXTI_PR_PR3                         EXTI_PR_PIF3
+#define EXTI_PR_PR4                         EXTI_PR_PIF4
+#define EXTI_PR_PR5                         EXTI_PR_PIF5
+#define EXTI_PR_PR6                         EXTI_PR_PIF6
+#define EXTI_PR_PR7                         EXTI_PR_PIF7
+#define EXTI_PR_PR8                         EXTI_PR_PIF8
+#define EXTI_PR_PR9                         EXTI_PR_PIF9
+#define EXTI_PR_PR10                        EXTI_PR_PIF10
+#define EXTI_PR_PR11                        EXTI_PR_PIF11
+#define EXTI_PR_PR12                        EXTI_PR_PIF12
+#define EXTI_PR_PR13                        EXTI_PR_PIF13
+#define EXTI_PR_PR14                        EXTI_PR_PIF14
+#define EXTI_PR_PR15                        EXTI_PR_PIF15
+#define EXTI_PR_PR16                        EXTI_PR_PIF16
+#define EXTI_PR_PR17                        EXTI_PR_PIF17
+#define EXTI_PR_PR19                        EXTI_PR_PIF19
+#define EXTI_PR_PR20                        EXTI_PR_PIF20
+#define EXTI_PR_PR21                        EXTI_PR_PIF21
+#define EXTI_PR_PR22                        EXTI_PR_PIF22
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define FLASH_ACR_LATENCY_Pos        (0U)                                      
+#define FLASH_ACR_LATENCY_Msk        (0x1U << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos         (1U)                                      
+#define FLASH_ACR_PRFTEN_Msk         (0x1U << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos       (3U)                                      
+#define FLASH_ACR_SLEEP_PD_Msk       (0x1U << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos         (4U)                                      
+#define FLASH_ACR_RUN_PD_Msk         (0x1U << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos      (5U)                                      
+#define FLASH_ACR_DISAB_BUF_Msk      (0x1U << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos       (6U)                                      
+#define FLASH_ACR_PRE_READ_Msk       (0x1U << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
+
+/*******************  Bit definition for FLASH_PECR register  ******************/
+#define FLASH_PECR_PELOCK_Pos        (0U)                                      
+#define FLASH_PECR_PELOCK_Msk        (0x1U << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos       (1U)                                      
+#define FLASH_PECR_PRGLOCK_Msk       (0x1U << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos       (2U)                                      
+#define FLASH_PECR_OPTLOCK_Msk       (0x1U << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos          (3U)                                      
+#define FLASH_PECR_PROG_Msk          (0x1U << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
+#define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos          (4U)                                      
+#define FLASH_PECR_DATA_Msk          (0x1U << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
+#define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos           (8U)                                      
+#define FLASH_PECR_FIX_Msk           (0x1U << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
+#define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos         (9U)                                      
+#define FLASH_PECR_ERASE_Msk         (0x1U << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
+#define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos          (10U)                                     
+#define FLASH_PECR_FPRG_Msk          (0x1U << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
+#define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos         (16U)                                     
+#define FLASH_PECR_EOPIE_Msk         (0x1U << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */ 
+#define FLASH_PECR_ERRIE_Pos         (17U)                                     
+#define FLASH_PECR_ERRIE_Msk         (0x1U << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */ 
+#define FLASH_PECR_OBL_LAUNCH_Pos    (18U)                                     
+#define FLASH_PECR_OBL_LAUNCH_Msk    (0x1U << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos    (19U)                                     
+#define FLASH_PECR_HALF_ARRAY_Msk    (0x1U << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
+
+/******************  Bit definition for FLASH_PDKEYR register  ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos      (0U)                                      
+#define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PEKEYR register  ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos      (0U)                                      
+#define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PRGKEYR register  ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)                                      
+#define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
+
+/******************  Bit definition for FLASH_OPTKEYR register  ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)                                      
+#define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define FLASH_SR_BSY_Pos             (0U)                                      
+#define FLASH_SR_BSY_Msk             (0x1U << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
+#define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
+#define FLASH_SR_EOP_Pos             (1U)                                      
+#define FLASH_SR_EOP_Msk             (0x1U << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
+#define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos           (2U)                                      
+#define FLASH_SR_HVOFF_Msk           (0x1U << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
+#define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
+#define FLASH_SR_READY_Pos           (3U)                                      
+#define FLASH_SR_READY_Msk           (0x1U << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
+#define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos          (8U)                                      
+#define FLASH_SR_WRPERR_Msk          (0x1U << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
+#define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos          (9U)                                      
+#define FLASH_SR_PGAERR_Msk          (0x1U << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
+#define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos          (10U)                                     
+#define FLASH_SR_SIZERR_Msk          (0x1U << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
+#define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos         (11U)                                     
+#define FLASH_SR_OPTVERR_Msk         (0x1U << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos           (13U)                                     
+#define FLASH_SR_RDERR_Msk           (0x1U << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
+#define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos      (16U)                                     
+#define FLASH_SR_NOTZEROERR_Msk      (0x1U << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos          (17U)                                     
+#define FLASH_SR_FWWERR_Msk          (0x1U << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
+#define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
+#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
+
+/******************  Bit definition for FLASH_OPTR register  *******************/
+#define FLASH_OPTR_RDPROT_Pos        (0U)                                      
+#define FLASH_OPTR_RDPROT_Msk        (0xFFU << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos        (8U)                                      
+#define FLASH_OPTR_WPRMOD_Msk        (0x1U << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos       (16U)                                     
+#define FLASH_OPTR_BOR_LEV_Msk       (0xFU << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos       (20U)                                     
+#define FLASH_OPTR_IWDG_SW_Msk       (0x1U << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos     (21U)                                     
+#define FLASH_OPTR_nRST_STOP_Msk     (0x1U << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos    (22U)                                     
+#define FLASH_OPTR_nRST_STDBY_Msk    (0x1U << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos          (20U)                                     
+#define FLASH_OPTR_USER_Msk          (0x7U << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
+#define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos         (31U)                                     
+#define FLASH_OPTR_BOOT1_Msk         (0x1U << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define FLASH_WRPR_WRP_Pos           (0U)                                      
+#define FLASH_WRPR_WRP_Msk           (0xFFFFU << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos            (0U)                                   
+#define GPIO_MODER_MODE0_Msk            (0x3U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk                   
+#define GPIO_MODER_MODE0_0              (0x1U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1              (0x2U << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos            (2U)                                   
+#define GPIO_MODER_MODE1_Msk            (0x3U << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk                   
+#define GPIO_MODER_MODE1_0              (0x1U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1              (0x2U << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos            (4U)                                   
+#define GPIO_MODER_MODE2_Msk            (0x3U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk                   
+#define GPIO_MODER_MODE2_0              (0x1U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1              (0x2U << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos            (6U)                                   
+#define GPIO_MODER_MODE3_Msk            (0x3U << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk                   
+#define GPIO_MODER_MODE3_0              (0x1U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1              (0x2U << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos            (8U)                                   
+#define GPIO_MODER_MODE4_Msk            (0x3U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk                   
+#define GPIO_MODER_MODE4_0              (0x1U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1              (0x2U << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos            (10U)                                  
+#define GPIO_MODER_MODE5_Msk            (0x3U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk                   
+#define GPIO_MODER_MODE5_0              (0x1U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1              (0x2U << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos            (12U)                                  
+#define GPIO_MODER_MODE6_Msk            (0x3U << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk                   
+#define GPIO_MODER_MODE6_0              (0x1U << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1              (0x2U << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos            (14U)                                  
+#define GPIO_MODER_MODE7_Msk            (0x3U << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk                   
+#define GPIO_MODER_MODE7_0              (0x1U << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1              (0x2U << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos            (16U)                                  
+#define GPIO_MODER_MODE8_Msk            (0x3U << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk                   
+#define GPIO_MODER_MODE8_0              (0x1U << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1              (0x2U << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos            (18U)                                  
+#define GPIO_MODER_MODE9_Msk            (0x3U << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk                   
+#define GPIO_MODER_MODE9_0              (0x1U << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1              (0x2U << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos           (20U)                                  
+#define GPIO_MODER_MODE10_Msk           (0x3U << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk                  
+#define GPIO_MODER_MODE10_0             (0x1U << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1             (0x2U << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos           (22U)                                  
+#define GPIO_MODER_MODE11_Msk           (0x3U << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk                  
+#define GPIO_MODER_MODE11_0             (0x1U << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1             (0x2U << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos           (24U)                                  
+#define GPIO_MODER_MODE12_Msk           (0x3U << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk                  
+#define GPIO_MODER_MODE12_0             (0x1U << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1             (0x2U << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos           (26U)                                  
+#define GPIO_MODER_MODE13_Msk           (0x3U << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk                  
+#define GPIO_MODER_MODE13_0             (0x1U << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1             (0x2U << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos           (28U)                                  
+#define GPIO_MODER_MODE14_Msk           (0x3U << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk                  
+#define GPIO_MODER_MODE14_0             (0x1U << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1             (0x2U << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos           (30U)                                  
+#define GPIO_MODER_MODE15_Msk           (0x3U << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk                  
+#define GPIO_MODER_MODE15_0             (0x1U << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1             (0x2U << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0                (0x00000001U)                          
+#define GPIO_OTYPER_OT_1                (0x00000002U)                          
+#define GPIO_OTYPER_OT_2                (0x00000004U)                          
+#define GPIO_OTYPER_OT_3                (0x00000008U)                          
+#define GPIO_OTYPER_OT_4                (0x00000010U)                          
+#define GPIO_OTYPER_OT_5                (0x00000020U)                          
+#define GPIO_OTYPER_OT_6                (0x00000040U)                          
+#define GPIO_OTYPER_OT_7                (0x00000080U)                          
+#define GPIO_OTYPER_OT_8                (0x00000100U)                          
+#define GPIO_OTYPER_OT_9                (0x00000200U)                          
+#define GPIO_OTYPER_OT_10               (0x00000400U)                          
+#define GPIO_OTYPER_OT_11               (0x00000800U)                          
+#define GPIO_OTYPER_OT_12               (0x00001000U)                          
+#define GPIO_OTYPER_OT_13               (0x00002000U)                          
+#define GPIO_OTYPER_OT_14               (0x00004000U)                          
+#define GPIO_OTYPER_OT_15               (0x00008000U)                          
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos       (0U)                                   
+#define GPIO_OSPEEDER_OSPEED0_Msk       (0x3U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk              
+#define GPIO_OSPEEDER_OSPEED0_0         (0x1U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1         (0x2U << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos       (2U)                                   
+#define GPIO_OSPEEDER_OSPEED1_Msk       (0x3U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk              
+#define GPIO_OSPEEDER_OSPEED1_0         (0x1U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1         (0x2U << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos       (4U)                                   
+#define GPIO_OSPEEDER_OSPEED2_Msk       (0x3U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk              
+#define GPIO_OSPEEDER_OSPEED2_0         (0x1U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1         (0x2U << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos       (6U)                                   
+#define GPIO_OSPEEDER_OSPEED3_Msk       (0x3U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk              
+#define GPIO_OSPEEDER_OSPEED3_0         (0x1U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1         (0x2U << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos       (8U)                                   
+#define GPIO_OSPEEDER_OSPEED4_Msk       (0x3U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk              
+#define GPIO_OSPEEDER_OSPEED4_0         (0x1U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1         (0x2U << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos       (10U)                                  
+#define GPIO_OSPEEDER_OSPEED5_Msk       (0x3U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk              
+#define GPIO_OSPEEDER_OSPEED5_0         (0x1U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1         (0x2U << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos       (12U)                                  
+#define GPIO_OSPEEDER_OSPEED6_Msk       (0x3U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk              
+#define GPIO_OSPEEDER_OSPEED6_0         (0x1U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1         (0x2U << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos       (14U)                                  
+#define GPIO_OSPEEDER_OSPEED7_Msk       (0x3U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk              
+#define GPIO_OSPEEDER_OSPEED7_0         (0x1U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1         (0x2U << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos       (16U)                                  
+#define GPIO_OSPEEDER_OSPEED8_Msk       (0x3U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk              
+#define GPIO_OSPEEDER_OSPEED8_0         (0x1U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1         (0x2U << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos       (18U)                                  
+#define GPIO_OSPEEDER_OSPEED9_Msk       (0x3U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk              
+#define GPIO_OSPEEDER_OSPEED9_0         (0x1U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1         (0x2U << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos      (20U)                                  
+#define GPIO_OSPEEDER_OSPEED10_Msk      (0x3U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk             
+#define GPIO_OSPEEDER_OSPEED10_0        (0x1U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1        (0x2U << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos      (22U)                                  
+#define GPIO_OSPEEDER_OSPEED11_Msk      (0x3U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk             
+#define GPIO_OSPEEDER_OSPEED11_0        (0x1U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1        (0x2U << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos      (24U)                                  
+#define GPIO_OSPEEDER_OSPEED12_Msk      (0x3U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk             
+#define GPIO_OSPEEDER_OSPEED12_0        (0x1U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1        (0x2U << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos      (26U)                                  
+#define GPIO_OSPEEDER_OSPEED13_Msk      (0x3U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk             
+#define GPIO_OSPEEDER_OSPEED13_0        (0x1U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1        (0x2U << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos      (28U)                                  
+#define GPIO_OSPEEDER_OSPEED14_Msk      (0x3U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk             
+#define GPIO_OSPEEDER_OSPEED14_0        (0x1U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1        (0x2U << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos      (30U)                                  
+#define GPIO_OSPEEDER_OSPEED15_Msk      (0x3U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk             
+#define GPIO_OSPEEDER_OSPEED15_0        (0x1U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1        (0x2U << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos            (0U)                                   
+#define GPIO_PUPDR_PUPD0_Msk            (0x3U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk                   
+#define GPIO_PUPDR_PUPD0_0              (0x1U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1              (0x2U << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos            (2U)                                   
+#define GPIO_PUPDR_PUPD1_Msk            (0x3U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk                   
+#define GPIO_PUPDR_PUPD1_0              (0x1U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1              (0x2U << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos            (4U)                                   
+#define GPIO_PUPDR_PUPD2_Msk            (0x3U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk                   
+#define GPIO_PUPDR_PUPD2_0              (0x1U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1              (0x2U << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos            (6U)                                   
+#define GPIO_PUPDR_PUPD3_Msk            (0x3U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk                   
+#define GPIO_PUPDR_PUPD3_0              (0x1U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1              (0x2U << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos            (8U)                                   
+#define GPIO_PUPDR_PUPD4_Msk            (0x3U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk                   
+#define GPIO_PUPDR_PUPD4_0              (0x1U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1              (0x2U << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos            (10U)                                  
+#define GPIO_PUPDR_PUPD5_Msk            (0x3U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk                   
+#define GPIO_PUPDR_PUPD5_0              (0x1U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1              (0x2U << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos            (12U)                                  
+#define GPIO_PUPDR_PUPD6_Msk            (0x3U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk                   
+#define GPIO_PUPDR_PUPD6_0              (0x1U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1              (0x2U << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos            (14U)                                  
+#define GPIO_PUPDR_PUPD7_Msk            (0x3U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk                   
+#define GPIO_PUPDR_PUPD7_0              (0x1U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1              (0x2U << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos            (16U)                                  
+#define GPIO_PUPDR_PUPD8_Msk            (0x3U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk                   
+#define GPIO_PUPDR_PUPD8_0              (0x1U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1              (0x2U << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos            (18U)                                  
+#define GPIO_PUPDR_PUPD9_Msk            (0x3U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk                   
+#define GPIO_PUPDR_PUPD9_0              (0x1U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1              (0x2U << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos           (20U)                                  
+#define GPIO_PUPDR_PUPD10_Msk           (0x3U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk                  
+#define GPIO_PUPDR_PUPD10_0             (0x1U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1             (0x2U << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos           (22U)                                  
+#define GPIO_PUPDR_PUPD11_Msk           (0x3U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk                  
+#define GPIO_PUPDR_PUPD11_0             (0x1U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1             (0x2U << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos           (24U)                                  
+#define GPIO_PUPDR_PUPD12_Msk           (0x3U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk                  
+#define GPIO_PUPDR_PUPD12_0             (0x1U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1             (0x2U << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos           (26U)                                  
+#define GPIO_PUPDR_PUPD13_Msk           (0x3U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk                  
+#define GPIO_PUPDR_PUPD13_0             (0x1U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1             (0x2U << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos           (28U)                                  
+#define GPIO_PUPDR_PUPD14_Msk           (0x3U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk                  
+#define GPIO_PUPDR_PUPD14_0             (0x1U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1             (0x2U << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos           (30U)                                  
+#define GPIO_PUPDR_PUPD15_Msk           (0x3U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk                  
+#define GPIO_PUPDR_PUPD15_0             (0x1U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1             (0x2U << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos                (0U)                                   
+#define GPIO_IDR_ID0_Msk                (0x1U << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk                       
+#define GPIO_IDR_ID1_Pos                (1U)                                   
+#define GPIO_IDR_ID1_Msk                (0x1U << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk                       
+#define GPIO_IDR_ID2_Pos                (2U)                                   
+#define GPIO_IDR_ID2_Msk                (0x1U << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk                       
+#define GPIO_IDR_ID3_Pos                (3U)                                   
+#define GPIO_IDR_ID3_Msk                (0x1U << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk                       
+#define GPIO_IDR_ID4_Pos                (4U)                                   
+#define GPIO_IDR_ID4_Msk                (0x1U << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk                       
+#define GPIO_IDR_ID5_Pos                (5U)                                   
+#define GPIO_IDR_ID5_Msk                (0x1U << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk                       
+#define GPIO_IDR_ID6_Pos                (6U)                                   
+#define GPIO_IDR_ID6_Msk                (0x1U << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk                       
+#define GPIO_IDR_ID7_Pos                (7U)                                   
+#define GPIO_IDR_ID7_Msk                (0x1U << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk                       
+#define GPIO_IDR_ID8_Pos                (8U)                                   
+#define GPIO_IDR_ID8_Msk                (0x1U << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk                       
+#define GPIO_IDR_ID9_Pos                (9U)                                   
+#define GPIO_IDR_ID9_Msk                (0x1U << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk                       
+#define GPIO_IDR_ID10_Pos               (10U)                                  
+#define GPIO_IDR_ID10_Msk               (0x1U << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk                      
+#define GPIO_IDR_ID11_Pos               (11U)                                  
+#define GPIO_IDR_ID11_Msk               (0x1U << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk                      
+#define GPIO_IDR_ID12_Pos               (12U)                                  
+#define GPIO_IDR_ID12_Msk               (0x1U << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk                      
+#define GPIO_IDR_ID13_Pos               (13U)                                  
+#define GPIO_IDR_ID13_Msk               (0x1U << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk                      
+#define GPIO_IDR_ID14_Pos               (14U)                                  
+#define GPIO_IDR_ID14_Msk               (0x1U << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk                      
+#define GPIO_IDR_ID15_Pos               (15U)                                  
+#define GPIO_IDR_ID15_Msk               (0x1U << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk                      
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_OD0_Pos                (0U)                                   
+#define GPIO_ODR_OD0_Msk                (0x1U << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk                       
+#define GPIO_ODR_OD1_Pos                (1U)                                   
+#define GPIO_ODR_OD1_Msk                (0x1U << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk                       
+#define GPIO_ODR_OD2_Pos                (2U)                                   
+#define GPIO_ODR_OD2_Msk                (0x1U << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk                       
+#define GPIO_ODR_OD3_Pos                (3U)                                   
+#define GPIO_ODR_OD3_Msk                (0x1U << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk                       
+#define GPIO_ODR_OD4_Pos                (4U)                                   
+#define GPIO_ODR_OD4_Msk                (0x1U << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk                       
+#define GPIO_ODR_OD5_Pos                (5U)                                   
+#define GPIO_ODR_OD5_Msk                (0x1U << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk                       
+#define GPIO_ODR_OD6_Pos                (6U)                                   
+#define GPIO_ODR_OD6_Msk                (0x1U << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk                       
+#define GPIO_ODR_OD7_Pos                (7U)                                   
+#define GPIO_ODR_OD7_Msk                (0x1U << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk                       
+#define GPIO_ODR_OD8_Pos                (8U)                                   
+#define GPIO_ODR_OD8_Msk                (0x1U << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk                       
+#define GPIO_ODR_OD9_Pos                (9U)                                   
+#define GPIO_ODR_OD9_Msk                (0x1U << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk                       
+#define GPIO_ODR_OD10_Pos               (10U)                                  
+#define GPIO_ODR_OD10_Msk               (0x1U << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk                      
+#define GPIO_ODR_OD11_Pos               (11U)                                  
+#define GPIO_ODR_OD11_Msk               (0x1U << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk                      
+#define GPIO_ODR_OD12_Pos               (12U)                                  
+#define GPIO_ODR_OD12_Msk               (0x1U << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk                      
+#define GPIO_ODR_OD13_Pos               (13U)                                  
+#define GPIO_ODR_OD13_Msk               (0x1U << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk                      
+#define GPIO_ODR_OD14_Pos               (14U)                                  
+#define GPIO_ODR_OD14_Msk               (0x1U << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk                      
+#define GPIO_ODR_OD15_Pos               (15U)                                  
+#define GPIO_ODR_OD15_Msk               (0x1U << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk                      
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0                  (0x00000001U)                          
+#define GPIO_BSRR_BS_1                  (0x00000002U)                          
+#define GPIO_BSRR_BS_2                  (0x00000004U)                          
+#define GPIO_BSRR_BS_3                  (0x00000008U)                          
+#define GPIO_BSRR_BS_4                  (0x00000010U)                          
+#define GPIO_BSRR_BS_5                  (0x00000020U)                          
+#define GPIO_BSRR_BS_6                  (0x00000040U)                          
+#define GPIO_BSRR_BS_7                  (0x00000080U)                          
+#define GPIO_BSRR_BS_8                  (0x00000100U)                          
+#define GPIO_BSRR_BS_9                  (0x00000200U)                          
+#define GPIO_BSRR_BS_10                 (0x00000400U)                          
+#define GPIO_BSRR_BS_11                 (0x00000800U)                          
+#define GPIO_BSRR_BS_12                 (0x00001000U)                          
+#define GPIO_BSRR_BS_13                 (0x00002000U)                          
+#define GPIO_BSRR_BS_14                 (0x00004000U)                          
+#define GPIO_BSRR_BS_15                 (0x00008000U)                          
+#define GPIO_BSRR_BR_0                  (0x00010000U)                          
+#define GPIO_BSRR_BR_1                  (0x00020000U)                          
+#define GPIO_BSRR_BR_2                  (0x00040000U)                          
+#define GPIO_BSRR_BR_3                  (0x00080000U)                          
+#define GPIO_BSRR_BR_4                  (0x00100000U)                          
+#define GPIO_BSRR_BR_5                  (0x00200000U)                          
+#define GPIO_BSRR_BR_6                  (0x00400000U)                          
+#define GPIO_BSRR_BR_7                  (0x00800000U)                          
+#define GPIO_BSRR_BR_8                  (0x01000000U)                          
+#define GPIO_BSRR_BR_9                  (0x02000000U)                          
+#define GPIO_BSRR_BR_10                 (0x04000000U)                          
+#define GPIO_BSRR_BR_11                 (0x08000000U)                          
+#define GPIO_BSRR_BR_12                 (0x10000000U)                          
+#define GPIO_BSRR_BR_13                 (0x20000000U)                          
+#define GPIO_BSRR_BR_14                 (0x40000000U)                          
+#define GPIO_BSRR_BR_15                 (0x80000000U)                          
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0_Pos              (0U)                                   
+#define GPIO_LCKR_LCK0_Msk              (0x1U << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
+#define GPIO_LCKR_LCK1_Pos              (1U)                                   
+#define GPIO_LCKR_LCK1_Msk              (0x1U << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
+#define GPIO_LCKR_LCK2_Pos              (2U)                                   
+#define GPIO_LCKR_LCK2_Msk              (0x1U << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
+#define GPIO_LCKR_LCK3_Pos              (3U)                                   
+#define GPIO_LCKR_LCK3_Msk              (0x1U << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
+#define GPIO_LCKR_LCK4_Pos              (4U)                                   
+#define GPIO_LCKR_LCK4_Msk              (0x1U << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
+#define GPIO_LCKR_LCK5_Pos              (5U)                                   
+#define GPIO_LCKR_LCK5_Msk              (0x1U << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
+#define GPIO_LCKR_LCK6_Pos              (6U)                                   
+#define GPIO_LCKR_LCK6_Msk              (0x1U << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
+#define GPIO_LCKR_LCK7_Pos              (7U)                                   
+#define GPIO_LCKR_LCK7_Msk              (0x1U << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
+#define GPIO_LCKR_LCK8_Pos              (8U)                                   
+#define GPIO_LCKR_LCK8_Msk              (0x1U << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
+#define GPIO_LCKR_LCK9_Pos              (9U)                                   
+#define GPIO_LCKR_LCK9_Msk              (0x1U << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
+#define GPIO_LCKR_LCK10_Pos             (10U)                                  
+#define GPIO_LCKR_LCK10_Msk             (0x1U << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
+#define GPIO_LCKR_LCK11_Pos             (11U)                                  
+#define GPIO_LCKR_LCK11_Msk             (0x1U << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
+#define GPIO_LCKR_LCK12_Pos             (12U)                                  
+#define GPIO_LCKR_LCK12_Msk             (0x1U << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
+#define GPIO_LCKR_LCK13_Pos             (13U)                                  
+#define GPIO_LCKR_LCK13_Msk             (0x1U << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
+#define GPIO_LCKR_LCK14_Pos             (14U)                                  
+#define GPIO_LCKR_LCK14_Msk             (0x1U << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
+#define GPIO_LCKR_LCK15_Pos             (15U)                                  
+#define GPIO_LCKR_LCK15_Msk             (0x1U << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
+#define GPIO_LCKR_LCKK_Pos              (16U)                                  
+#define GPIO_LCKR_LCKK_Msk              (0x1U << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0_Pos             (0U)                                   
+#define GPIO_AFRL_AFRL0_Msk             (0xFU << GPIO_AFRL_AFRL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFRL0_Msk                    
+#define GPIO_AFRL_AFRL1_Pos             (4U)                                   
+#define GPIO_AFRL_AFRL1_Msk             (0xFU << GPIO_AFRL_AFRL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFRL1_Msk                    
+#define GPIO_AFRL_AFRL2_Pos             (8U)                                   
+#define GPIO_AFRL_AFRL2_Msk             (0xFU << GPIO_AFRL_AFRL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFRL2_Msk                    
+#define GPIO_AFRL_AFRL3_Pos             (12U)                                  
+#define GPIO_AFRL_AFRL3_Msk             (0xFU << GPIO_AFRL_AFRL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFRL3_Msk                    
+#define GPIO_AFRL_AFRL4_Pos             (16U)                                  
+#define GPIO_AFRL_AFRL4_Msk             (0xFU << GPIO_AFRL_AFRL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFRL4_Msk                    
+#define GPIO_AFRL_AFRL5_Pos             (20U)                                  
+#define GPIO_AFRL_AFRL5_Msk             (0xFU << GPIO_AFRL_AFRL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFRL5_Msk                    
+#define GPIO_AFRL_AFRL6_Pos             (24U)                                  
+#define GPIO_AFRL_AFRL6_Msk             (0xFU << GPIO_AFRL_AFRL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFRL6_Msk                    
+#define GPIO_AFRL_AFRL7_Pos             (28U)                                  
+#define GPIO_AFRL_AFRL7_Msk             (0xFU << GPIO_AFRL_AFRL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFRL7_Msk                    
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0_Pos             (0U)                                   
+#define GPIO_AFRH_AFRH0_Msk             (0xFU << GPIO_AFRH_AFRH0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFRH0_Msk                    
+#define GPIO_AFRH_AFRH1_Pos             (4U)                                   
+#define GPIO_AFRH_AFRH1_Msk             (0xFU << GPIO_AFRH_AFRH1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFRH1_Msk                    
+#define GPIO_AFRH_AFRH2_Pos             (8U)                                   
+#define GPIO_AFRH_AFRH2_Msk             (0xFU << GPIO_AFRH_AFRH2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFRH2_Msk                    
+#define GPIO_AFRH_AFRH3_Pos             (12U)                                  
+#define GPIO_AFRH_AFRH3_Msk             (0xFU << GPIO_AFRH_AFRH3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFRH3_Msk                    
+#define GPIO_AFRH_AFRH4_Pos             (16U)                                  
+#define GPIO_AFRH_AFRH4_Msk             (0xFU << GPIO_AFRH_AFRH4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFRH4_Msk                    
+#define GPIO_AFRH_AFRH5_Pos             (20U)                                  
+#define GPIO_AFRH_AFRH5_Msk             (0xFU << GPIO_AFRH_AFRH5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFRH5_Msk                    
+#define GPIO_AFRH_AFRH6_Pos             (24U)                                  
+#define GPIO_AFRH_AFRH6_Msk             (0xFU << GPIO_AFRH_AFRH6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFRH6_Msk                    
+#define GPIO_AFRH_AFRH7_Pos             (28U)                                  
+#define GPIO_AFRH_AFRH7_Msk             (0xFU << GPIO_AFRH_AFRH7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFRH7_Msk                    
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0                   (0x00000001U)                          
+#define GPIO_BRR_BR_1                   (0x00000002U)                          
+#define GPIO_BRR_BR_2                   (0x00000004U)                          
+#define GPIO_BRR_BR_3                   (0x00000008U)                          
+#define GPIO_BRR_BR_4                   (0x00000010U)                          
+#define GPIO_BRR_BR_5                   (0x00000020U)                          
+#define GPIO_BRR_BR_6                   (0x00000040U)                          
+#define GPIO_BRR_BR_7                   (0x00000080U)                          
+#define GPIO_BRR_BR_8                   (0x00000100U)                          
+#define GPIO_BRR_BR_9                   (0x00000200U)                          
+#define GPIO_BRR_BR_10                  (0x00000400U)                          
+#define GPIO_BRR_BR_11                  (0x00000800U)                          
+#define GPIO_BRR_BR_12                  (0x00001000U)                          
+#define GPIO_BRR_BR_13                  (0x00002000U)                          
+#define GPIO_BRR_BR_14                  (0x00004000U)                          
+#define GPIO_BRR_BR_15                  (0x00008000U)                          
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos            (0U)                                       
+#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
+#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos             (1U)                                       
+#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
+#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos             (2U)                                       
+#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
+#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
+#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
+#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos             (5U)                                       
+#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
+#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
+#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos          (7U)                                       
+#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
+
+#define LCD_CR_BUFEN_Pos            (8U)
+#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
+#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable Bit */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos              (0U)                                       
+#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
+#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos           (1U)                                       
+#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
+#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos           (3U)                                       
+#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
+#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos             (4U)                                       
+#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
+#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
+#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
+#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos            (7U)                                       
+#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
+#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos              (10U)                                      
+#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
+#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
+#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
+#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos          (13U)                                      
+#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos           (16U)                                      
+#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
+#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos             (18U)                                      
+#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
+#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos              (22U)                                      
+#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
+#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos              (0U)                                       
+#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
+#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos              (1U)                                       
+#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
+#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos              (2U)                                       
+#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
+#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos              (3U)                                       
+#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
+#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos              (4U)                                       
+#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
+#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos            (5U)                                       
+#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
+#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos            (1U)                                       
+#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
+#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos            (3U)                                       
+#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
+#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
+#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            MIFARE   Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */ 
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */  
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */ 
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */ 
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x3FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */ 
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x3FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */ 
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/ 
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/ 
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/ 
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPSDSR_Pos          (0U)                                        
+#define PWR_CR_LPSDSR_Msk          (0x1U << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
+#define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos            (1U)                                        
+#define PWR_CR_PDDS_Msk            (0x1U << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
+#define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos            (2U)                                        
+#define PWR_CR_CWUF_Msk            (0x1U << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
+#define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos            (3U)                                        
+#define PWR_CR_CSBF_Msk            (0x1U << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
+#define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos            (4U)                                        
+#define PWR_CR_PVDE_Msk            (0x1U << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
+#define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos             (5U)                                        
+#define PWR_CR_PLS_Msk             (0x7U << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
+#define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0               (0x1U << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
+#define PWR_CR_PLS_1               (0x2U << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
+#define PWR_CR_PLS_2               (0x4U << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos             (8U)                                        
+#define PWR_CR_DBP_Msk             (0x1U << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
+#define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos             (9U)                                        
+#define PWR_CR_ULP_Msk             (0x1U << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
+#define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos             (10U)                                       
+#define PWR_CR_FWU_Msk             (0x1U << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
+#define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos             (11U)                                       
+#define PWR_CR_VOS_Msk             (0x3U << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
+#define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0               (0x1U << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
+#define PWR_CR_VOS_1               (0x2U << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos        (13U)                                       
+#define PWR_CR_DSEEKOFF_Msk        (0x1U << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos           (14U)                                       
+#define PWR_CR_LPRUN_Msk           (0x1U << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
+#define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos            (0U)                                        
+#define PWR_CSR_WUF_Msk            (0x1U << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
+#define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos            (1U)                                        
+#define PWR_CSR_SBF_Msk            (0x1U << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
+#define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos           (2U)                                        
+#define PWR_CSR_PVDO_Msk           (0x1U << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
+#define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos    (3U)                                        
+#define PWR_CSR_VREFINTRDYF_Msk    (0x1U << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos           (4U)                                        
+#define PWR_CSR_VOSF_Msk           (0x1U << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
+#define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos         (5U)                                        
+#define PWR_CSR_REGLPF_Msk         (0x1U << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
+#define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos          (8U)                                        
+#define PWR_CSR_EWUP1_Msk          (0x1U << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
+#define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos          (9U)                                        
+#define PWR_CSR_EWUP2_Msk          (0x1U << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
+#define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                 (0U)                                  
+#define RCC_CR_HSION_Msk                 (0x1U << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
+#define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos              (1U)                                  
+#define RCC_CR_HSIKERON_Msk              (0x1U << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                (2U)                                  
+#define RCC_CR_HSIRDY_Msk                (0x1U << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos              (3U)                                  
+#define RCC_CR_HSIDIVEN_Msk              (0x1U << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos               (4U)                                  
+#define RCC_CR_HSIDIVF_Msk               (0x1U << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos                 (8U)                                  
+#define RCC_CR_MSION_Msk                 (0x1U << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
+#define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos                (9U)                                  
+#define RCC_CR_MSIRDY_Msk                (0x1U << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
+#define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos                 (16U)                                 
+#define RCC_CR_HSEON_Msk                 (0x1U << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
+#define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                (17U)                                 
+#define RCC_CR_HSERDY_Msk                (0x1U << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
+#define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos                (18U)                                 
+#define RCC_CR_HSEBYP_Msk                (0x1U << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos              (19U)                                 
+#define RCC_CR_CSSHSEON_Msk              (0x1U << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos                (20U)                                 
+#define RCC_CR_RTCPRE_Msk                (0x3U << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
+#define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0                  (0x1U << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1                  (0x2U << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos                 (24U)                                 
+#define RCC_CR_PLLON_Msk                 (0x1U << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
+#define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos                (25U)                                 
+#define RCC_CR_PLLRDY_Msk                (0x1U << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON     RCC_CR_CSSHSEON
+
+/********************  Bit definition for RCC_ICSCR register  *****************/
+#define RCC_ICSCR_HSICAL_Pos             (0U)                                  
+#define RCC_ICSCR_HSICAL_Msk             (0xFFU << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos            (8U)                                  
+#define RCC_ICSCR_HSITRIM_Msk            (0x1FU << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos           (13U)                                 
+#define RCC_ICSCR_MSIRANGE_Msk           (0x7U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0             (0x0U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1             (0x1U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2             (0x2U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3             (0x3U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4             (0x4U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5             (0x5U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6             (0x6U << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos             (16U)                                 
+#define RCC_ICSCR_MSICAL_Msk             (0xFFU << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos            (24U)                                 
+#define RCC_ICSCR_MSITRIM_Msk            (0xFFU << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+#define RCC_CRRCR_HSI48ON_Pos            (0U)                                  
+#define RCC_CRRCR_HSI48ON_Msk            (0x1U << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos           (1U)                                  
+#define RCC_CRRCR_HSI48RDY_Msk           (0x1U << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL_Pos           (8U)                                  
+#define RCC_CRRCR_HSI48CAL_Msk           (0xFFU << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos                  (16U)                             
+#define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos                  (18U)                             
+#define RCC_CFGR_PLLMUL_Msk                  (0xFU << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0                    (0x1U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1                    (0x2U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2                    (0x4U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3                    (0x8U << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos                  (22U)                             
+#define RCC_CFGR_PLLDIV_Msk                  (0x3U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0                    (0x1U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1                    (0x2U << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos                 (22U)                             
+#define RCC_CFGR_PLLDIV2_Msk                 (0x1U << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos                 (23U)                             
+#define RCC_CFGR_PLLDIV3_Msk                 (0x1U << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos                 (22U)                             
+#define RCC_CFGR_PLLDIV4_Msk                 (0x3U << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)                             
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos              (25U)                             
+#define RCC_CFGR_MCOSEL_HSI_Msk              (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos              (24U)                             
+#define RCC_CFGR_MCOSEL_MSI_Msk              (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos              (26U)                             
+#define RCC_CFGR_MCOSEL_HSE_Msk              (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos              (24U)                             
+#define RCC_CFGR_MCOSEL_PLL_Msk              (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos              (25U)                             
+#define RCC_CFGR_MCOSEL_LSI_Msk              (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos              (24U)                             
+#define RCC_CFGR_MCOSEL_LSE_Msk              (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)                             
+#define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK   
+#define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK    
+#define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI       
+#define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI       
+#define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE       
+#define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL       
+#define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI       
+#define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE       
+#define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48   
+
+#define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
+
+/*!<******************  Bit definition for RCC_CIER register  ********************/
+#define RCC_CIER_LSIRDYIE_Pos            (0U)                                  
+#define RCC_CIER_LSIRDYIE_Msk            (0x1U << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos            (1U)                                  
+#define RCC_CIER_LSERDYIE_Msk            (0x1U << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos            (2U)                                  
+#define RCC_CIER_HSIRDYIE_Msk            (0x1U << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos            (3U)                                  
+#define RCC_CIER_HSERDYIE_Msk            (0x1U << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos            (4U)                                  
+#define RCC_CIER_PLLRDYIE_Msk            (0x1U << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos            (5U)                                  
+#define RCC_CIER_MSIRDYIE_Msk            (0x1U << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos          (6U)                                  
+#define RCC_CIER_HSI48RDYIE_Msk          (0x1U << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos              (7U)                                  
+#define RCC_CIER_CSSLSE_Msk              (0x1U << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
+
+/*!<******************  Bit definition for RCC_CIFR register  ********************/
+#define RCC_CIFR_LSIRDYF_Pos             (0U)                                  
+#define RCC_CIFR_LSIRDYF_Msk             (0x1U << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos             (1U)                                  
+#define RCC_CIFR_LSERDYF_Msk             (0x1U << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos             (2U)                                  
+#define RCC_CIFR_HSIRDYF_Msk             (0x1U << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos             (3U)                                  
+#define RCC_CIFR_HSERDYF_Msk             (0x1U << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos             (4U)                                  
+#define RCC_CIFR_PLLRDYF_Msk             (0x1U << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos             (5U)                                  
+#define RCC_CIFR_MSIRDYF_Msk             (0x1U << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos           (6U)                                  
+#define RCC_CIFR_HSI48RDYF_Msk           (0x1U << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos             (7U)                                  
+#define RCC_CIFR_CSSLSEF_Msk             (0x1U << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos             (8U)                                  
+#define RCC_CIFR_CSSHSEF_Msk             (0x1U << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
+
+/*!<******************  Bit definition for RCC_CICR register  ********************/
+#define RCC_CICR_LSIRDYC_Pos             (0U)                                  
+#define RCC_CICR_LSIRDYC_Msk             (0x1U << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos             (1U)                                  
+#define RCC_CICR_LSERDYC_Msk             (0x1U << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos             (2U)                                  
+#define RCC_CICR_HSIRDYC_Msk             (0x1U << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos             (3U)                                  
+#define RCC_CICR_HSERDYC_Msk             (0x1U << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos             (4U)                                  
+#define RCC_CICR_PLLRDYC_Msk             (0x1U << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos             (5U)                                  
+#define RCC_CICR_MSIRDYC_Msk             (0x1U << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos           (6U)                                  
+#define RCC_CICR_HSI48RDYC_Msk           (0x1U << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos             (7U)                                  
+#define RCC_CICR_CSSLSEC_Msk             (0x1U << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos             (8U)                                  
+#define RCC_CICR_CSSHSEC_Msk             (0x1U << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
+/*****************  Bit definition for RCC_IOPRSTR register  ******************/
+#define RCC_IOPRSTR_IOPARST_Pos          (0U)                                  
+#define RCC_IOPRSTR_IOPARST_Msk          (0x1U << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos          (1U)                                  
+#define RCC_IOPRSTR_IOPBRST_Msk          (0x1U << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos          (2U)                                  
+#define RCC_IOPRSTR_IOPCRST_Msk          (0x1U << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos          (3U)                                  
+#define RCC_IOPRSTR_IOPDRST_Msk          (0x1U << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos          (7U)                                  
+#define RCC_IOPRSTR_IOPHRST_Msk          (0x1U << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
+
+
+/******************  Bit definition for RCC_AHBRST register  ******************/
+#define RCC_AHBRSTR_DMARST_Pos           (0U)                                  
+#define RCC_AHBRSTR_DMARST_Msk           (0x1U << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos           (8U)                                  
+#define RCC_AHBRSTR_MIFRST_Msk           (0x1U << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset reset */
+#define RCC_AHBRSTR_CRCRST_Pos           (12U)                                 
+#define RCC_AHBRSTR_CRCRST_Msk           (0x1U << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos           (16U)                                 
+#define RCC_AHBRSTR_TSCRST_Msk           (0x1U << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos           (20U)                                 
+#define RCC_AHBRSTR_RNGRST_Msk           (0x1U << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos       (0U)                                  
+#define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_TIM21RST_Pos        (2U)                                  
+#define RCC_APB2RSTR_TIM21RST_Msk        (0x1U << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 clock reset */
+#define RCC_APB2RSTR_TIM22RST_Pos        (5U)                                  
+#define RCC_APB2RSTR_TIM22RST_Msk        (0x1U << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 clock reset */
+#define RCC_APB2RSTR_ADCRST_Pos          (9U)                                  
+#define RCC_APB2RSTR_ADCRST_Msk          (0x1U << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_SPI1RST_Pos         (12U)                                 
+#define RCC_APB2RSTR_SPI1RST_Msk         (0x1U << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST_Pos       (14U)                                 
+#define RCC_APB2RSTR_USART1RST_Msk       (0x1U << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 clock reset */
+#define RCC_APB2RSTR_DBGRST_Pos          (22U)                                 
+#define RCC_APB2RSTR_DBGRST_Msk          (0x1U << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU clock reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU clock reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos         (0U)                                  
+#define RCC_APB1RSTR_TIM2RST_Msk         (0x1U << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM6RST_Pos         (4U)                                  
+#define RCC_APB1RSTR_TIM6RST_Msk         (0x1U << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_LCDRST_Pos          (9U)                                  
+#define RCC_APB1RSTR_LCDRST_Msk          (0x1U << RCC_APB1RSTR_LCDRST_Pos)     /*!< 0x00000200 */
+#define RCC_APB1RSTR_LCDRST              RCC_APB1RSTR_LCDRST_Msk               /*!< LCD clock reset */
+#define RCC_APB1RSTR_WWDGRST_Pos         (11U)                                 
+#define RCC_APB1RSTR_WWDGRST_Msk         (0x1U << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST_Pos         (14U)                                 
+#define RCC_APB1RSTR_SPI2RST_Msk         (0x1U << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST_Pos       (17U)                                 
+#define RCC_APB1RSTR_USART2RST_Msk       (0x1U << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos      (18U)                                 
+#define RCC_APB1RSTR_LPUART1RST_Msk      (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 clock reset */
+#define RCC_APB1RSTR_I2C1RST_Pos         (21U)                                 
+#define RCC_APB1RSTR_I2C1RST_Msk         (0x1U << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST_Pos         (22U)                                 
+#define RCC_APB1RSTR_I2C2RST_Msk         (0x1U << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST_Pos          (23U)                                 
+#define RCC_APB1RSTR_USBRST_Msk          (0x1U << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB clock reset */
+#define RCC_APB1RSTR_CRSRST_Pos          (27U)                                 
+#define RCC_APB1RSTR_CRSRST_Msk          (0x1U << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST_Pos          (28U)                                 
+#define RCC_APB1RSTR_PWRRST_Msk          (0x1U << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST_Pos          (29U)                                 
+#define RCC_APB1RSTR_DACRST_Msk          (0x1U << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC clock reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)                                 
+#define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 clock reset */
+
+/*****************  Bit definition for RCC_IOPENR register  ******************/
+#define RCC_IOPENR_IOPAEN_Pos            (0U)                                  
+#define RCC_IOPENR_IOPAEN_Msk            (0x1U << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos            (1U)                                  
+#define RCC_IOPENR_IOPBEN_Msk            (0x1U << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos            (2U)                                  
+#define RCC_IOPENR_IOPCEN_Msk            (0x1U << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos            (3U)                                  
+#define RCC_IOPENR_IOPDEN_Msk            (0x1U << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos            (7U)                                  
+#define RCC_IOPENR_IOPHEN_Msk            (0x1U << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
+
+/*****************  Bit definition for RCC_AHBENR register  ******************/
+#define RCC_AHBENR_DMAEN_Pos             (0U)                                  
+#define RCC_AHBENR_DMAEN_Msk             (0x1U << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos             (8U)                                  
+#define RCC_AHBENR_MIFEN_Msk             (0x1U << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos             (12U)                                 
+#define RCC_AHBENR_CRCEN_Msk             (0x1U << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos             (16U)                                 
+#define RCC_AHBENR_TSCEN_Msk             (0x1U << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos             (20U)                                 
+#define RCC_AHBENR_RNGEN_Msk             (0x1U << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos         (0U)                                  
+#define RCC_APB2ENR_SYSCFGEN_Msk         (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos          (2U)                                  
+#define RCC_APB2ENR_TIM21EN_Msk          (0x1U << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos          (5U)                                  
+#define RCC_APB2ENR_TIM22EN_Msk          (0x1U << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos             (7U)                                  
+#define RCC_APB2ENR_FWEN_Msk             (0x1U << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos            (9U)                                  
+#define RCC_APB2ENR_ADCEN_Msk            (0x1U << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos           (12U)                                 
+#define RCC_APB2ENR_SPI1EN_Msk           (0x1U << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos         (14U)                                 
+#define RCC_APB2ENR_USART1EN_Msk         (0x1U << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos            (22U)                                 
+#define RCC_APB2ENR_DBGEN_Msk            (0x1U << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define RCC_APB1ENR_TIM2EN_Pos           (0U)                                  
+#define RCC_APB1ENR_TIM2EN_Msk           (0x1U << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos           (4U)                                  
+#define RCC_APB1ENR_TIM6EN_Msk           (0x1U << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_LCDEN_Pos            (9U)                                  
+#define RCC_APB1ENR_LCDEN_Msk            (0x1U << RCC_APB1ENR_LCDEN_Pos)       /*!< 0x00000200 */
+#define RCC_APB1ENR_LCDEN                RCC_APB1ENR_LCDEN_Msk                 /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos           (11U)                                 
+#define RCC_APB1ENR_WWDGEN_Msk           (0x1U << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos           (14U)                                 
+#define RCC_APB1ENR_SPI2EN_Msk           (0x1U << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos         (17U)                                 
+#define RCC_APB1ENR_USART2EN_Msk         (0x1U << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos        (18U)                                 
+#define RCC_APB1ENR_LPUART1EN_Msk        (0x1U << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos           (21U)                                 
+#define RCC_APB1ENR_I2C1EN_Msk           (0x1U << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos           (22U)                                 
+#define RCC_APB1ENR_I2C2EN_Msk           (0x1U << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos            (23U)                                 
+#define RCC_APB1ENR_USBEN_Msk            (0x1U << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos            (27U)                                 
+#define RCC_APB1ENR_CRSEN_Msk            (0x1U << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos            (28U)                                 
+#define RCC_APB1ENR_PWREN_Msk            (0x1U << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos            (29U)                                 
+#define RCC_APB1ENR_DACEN_Msk            (0x1U << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos         (31U)                                 
+#define RCC_APB1ENR_LPTIM1EN_Msk         (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
+
+/******************  Bit definition for RCC_IOPSMENR register  ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos        (0U)                                  
+#define RCC_IOPSMENR_IOPASMEN_Msk        (0x1U << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos        (1U)                                  
+#define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos        (2U)                                  
+#define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos        (3U)                                  
+#define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos        (7U)                                  
+#define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_AHBSMENR register  ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos         (0U)                                  
+#define RCC_AHBSMENR_DMASMEN_Msk         (0x1U << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos         (8U)                                  
+#define RCC_AHBSMENR_MIFSMEN_Msk         (0x1U << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)                                  
+#define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos         (12U)                                 
+#define RCC_AHBSMENR_CRCSMEN_Msk         (0x1U << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos         (16U)                                 
+#define RCC_AHBSMENR_TSCSMEN_Msk         (0x1U << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos         (20U)                                 
+#define RCC_AHBSMENR_RNGSMEN_Msk         (0x1U << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_APB2SMENR register  ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U)                                  
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos      (2U)                                  
+#define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos      (5U)                                  
+#define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos        (9U)                                  
+#define RCC_APB2SMENR_ADCSMEN_Msk        (0x1U << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)                                 
+#define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos     (14U)                                 
+#define RCC_APB2SMENR_USART1SMEN_Msk     (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos        (22U)                                 
+#define RCC_APB2SMENR_DBGSMEN_Msk        (0x1U << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_APB1SMENR register  ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos       (0U)                                  
+#define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos       (4U)                                  
+#define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN_Pos        (9U)                                  
+#define RCC_APB1SMENR_LCDSMEN_Msk        (0x1U << RCC_APB1SMENR_LCDSMEN_Pos)   /*!< 0x00000200 */
+#define RCC_APB1SMENR_LCDSMEN            RCC_APB1SMENR_LCDSMEN_Msk             /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)                                 
+#define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)                                 
+#define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos     (17U)                                 
+#define RCC_APB1SMENR_USART2SMEN_Msk     (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)                                 
+#define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)                                 
+#define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)                                 
+#define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos        (23U)                                 
+#define RCC_APB1SMENR_USBSMEN_Msk        (0x1U << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos        (27U)                                 
+#define RCC_APB1SMENR_CRSSMEN_Msk        (0x1U << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos        (28U)                                 
+#define RCC_APB1SMENR_PWRSMEN_Msk        (0x1U << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos        (29U)                                 
+#define RCC_APB1SMENR_DACSMEN_Msk        (0x1U << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)                                 
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
+
+/*******************  Bit definition for RCC_CCIPR register  *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos          (0U)                                  
+#define RCC_CCIPR_USART1SEL_Msk          (0x3U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0            (0x1U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1            (0x2U << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos          (2U)                                  
+#define RCC_CCIPR_USART2SEL_Msk          (0x3U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0            (0x1U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1            (0x2U << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */ 
+#define RCC_CCIPR_LPUART1SEL_Pos         (10U)                                 
+#define RCC_CCIPR_LPUART1SEL_Msk         (0x3U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0           (0x1U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1           (0x2U << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos            (12U)                                 
+#define RCC_CCIPR_I2C1SEL_Msk            (0x3U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0              (0x1U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1              (0x2U << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */ 
+#define RCC_CCIPR_LPTIM1SEL_Pos          (18U)                                 
+#define RCC_CCIPR_LPTIM1SEL_Msk          (0x3U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0            (0x1U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1            (0x2U << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */ 
+#define RCC_CCIPR_HSI48SEL_Pos           (26U)                                 
+#define RCC_CCIPR_HSI48SEL_Msk           (0x1U << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
+
+/*******************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                (0U)                                  
+#define RCC_CSR_LSION_Msk                (0x1U << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
+#define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos               (1U)                                  
+#define RCC_CSR_LSIRDY_Msk               (0x1U << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos                (8U)                                  
+#define RCC_CSR_LSEON_Msk                (0x1U << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
+#define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos               (9U)                                  
+#define RCC_CSR_LSERDY_Msk               (0x1U << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
+#define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos               (10U)                                 
+#define RCC_CSR_LSEBYP_Msk               (0x1U << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
+                                             
+#define RCC_CSR_LSEDRV_Pos               (11U)                                 
+#define RCC_CSR_LSEDRV_Msk               (0x3U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0                 (0x1U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1                 (0x2U << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
+                                             
+#define RCC_CSR_LSECSSON_Pos             (13U)                                 
+#define RCC_CSR_LSECSSON_Msk             (0x1U << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos              (14U)                                 
+#define RCC_CSR_LSECSSD_Msk              (0x1U << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
+                                             
+/*!< RTC congiguration */                    
+#define RCC_CSR_RTCSEL_Pos               (16U)                                 
+#define RCC_CSR_RTCSEL_Msk               (0x3U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0                 (0x1U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1                 (0x2U << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
+                                             
+#define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos           (16U)                                 
+#define RCC_CSR_RTCSEL_LSE_Msk           (0x1U << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos           (17U)                                 
+#define RCC_CSR_RTCSEL_LSI_Msk           (0x1U << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos           (16U)                                 
+#define RCC_CSR_RTCSEL_HSE_Msk           (0x3U << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
+                                             
+#define RCC_CSR_RTCEN_Pos                (18U)                                 
+#define RCC_CSR_RTCEN_Msk                (0x1U << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
+#define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos               (19U)                                 
+#define RCC_CSR_RTCRST_Msk               (0x1U << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
+#define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
+
+#define RCC_CSR_RMVF_Pos                 (23U)                                 
+#define RCC_CSR_RMVF_Msk                 (0x1U << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
+#define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos               (24U)                                 
+#define RCC_CSR_FWRSTF_Msk               (0x1U << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos              (25U)                                 
+#define RCC_CSR_OBLRSTF_Msk              (0x1U << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos              (26U)                                 
+#define RCC_CSR_PINRSTF_Msk              (0x1U << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos              (27U)                                 
+#define RCC_CSR_PORRSTF_Msk              (0x1U << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos              (28U)                                 
+#define RCC_CSR_SFTRSTF_Msk              (0x1U << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos             (29U)                                 
+#define RCC_CSR_IWDGRSTF_Msk             (0x1U << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos             (30U)                                 
+#define RCC_CSR_WWDGRSTF_Msk             (0x1U << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos             (31U)                                 
+#define RCC_CSR_LPWRRSTF_Msk             (0x1U << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
+#define RTC_CR_BCK_Pos                 (18U)                                   
+#define RTC_CR_BCK_Msk                 (0x1U << RTC_CR_BCK_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BCK                     RTC_CR_BCK_Msk                          /*!<  */
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP     RTC_CALR_CALP 
+#define RTC_CAL_CALW8    RTC_CALR_CALW8  
+#define RTC_CAL_CALW16   RTC_CALR_CALW16 
+#define RTC_CAL_CALM     RTC_CALR_CALM 
+#define RTC_CAL_CALM_0   RTC_CALR_CALM_0 
+#define RTC_CAL_CALM_1   RTC_CALR_CALM_1 
+#define RTC_CAL_CALM_2   RTC_CALR_CALM_2 
+#define RTC_CAL_CALM_3   RTC_CALR_CALM_3 
+#define RTC_CAL_CALM_4   RTC_CALR_CALM_4 
+#define RTC_CAL_CALM_5   RTC_CALR_CALM_5 
+#define RTC_CAL_CALM_6   RTC_CALR_CALM_6 
+#define RTC_CAL_CALM_7   RTC_CALR_CALM_7 
+#define RTC_CAL_CALM_8   RTC_CALR_CALM_8 
+
+/********************  Bits definition for RTC_TAMPCR register  ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_OR register  ****************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT                       /*!< I2S support */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)                                       
+#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos            (1U)                                       
+#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos            (2U)                                       
+#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
+#define SPI_CR1_BR_Pos              (3U)                                       
+#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos             (6U)                                       
+#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
+#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
+#define SPI_CR1_SSI_Pos             (8U)                                       
+#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos             (9U)                                       
+#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos          (10U)                                      
+#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
+#define SPI_CR1_DFF_Pos             (11U)                                      
+#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
+#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
+#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos           (13U)                                      
+#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos          (14U)                                      
+#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
+#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
+#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
+#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos            (2U)                                       
+#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos             (4U)                                       
+#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos           (5U)                                       
+#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos          (6U)                                       
+#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)                                       
+#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)                                       
+#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)                                       
+#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos           (2U)                                       
+#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
+#define SPI_SR_UDR_Pos              (3U)                                       
+#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos           (4U)                                       
+#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos             (5U)                                       
+#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
+#define SPI_SR_OVR_Pos              (6U)                                       
+#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
+#define SPI_SR_BSY_Pos              (7U)                                       
+#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
+#define SPI_SR_FRE_Pos              (8U)                                       
+#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)                                       
+#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
+#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos           (8U)                                       
+#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
+#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)                          
+#define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0                  (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1                  (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)                          
+#define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)                          
+#define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA_Pos                    (1U)                          
+#define SYSCFG_CFGR2_CAPA_Msk                    (0x7U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
+#define SYSCFG_CFGR2_CAPA                        SYSCFG_CFGR2_CAPA_Msk         /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0                      (0x1U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_CAPA_1                      (0x2U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_CAPA_2                      (0x4U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)                          
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)                          
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)                         
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)                         
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)                         
+#define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)                         
+#define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)                          
+#define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)                          
+#define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)                          
+#define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)                         
+#define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)                          
+#define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)                          
+#define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)                          
+#define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)                         
+#define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)                          
+#define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)                          
+#define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos                (8U)                          
+#define SYSCFG_EXTICR3_EXTI10_Msk                (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos                (12U)                         
+#define SYSCFG_EXTICR3_EXTI11_Msk                (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos                (0U)                          
+#define SYSCFG_EXTICR4_EXTI12_Msk                (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos                (4U)                          
+#define SYSCFG_EXTICR4_EXTI13_Msk                (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos                (8U)                          
+#define SYSCFG_EXTICR4_EXTI14_Msk                (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos                (12U)                         
+#define SYSCFG_EXTICR4_EXTI15_Msk                (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
+
+
+/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
+#define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)                          
+#define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0                  (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1                  (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)                          
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)                          
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)                         
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)                         
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)                         
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)                         
+#define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+    || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT       /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
+#endif	
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFU << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM2_OR_ETR_RMP_Pos      (0U)                                          
+#define TIM2_OR_ETR_RMP_Msk      (0x7U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0        (0x1U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1        (0x2U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2        (0x4U << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos      (3U)                                          
+#define TIM2_OR_TI4_RMP_Msk      (0x3U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0        (0x1U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1        (0x2U << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos      (0U)                                         
+#define TIM21_OR_ETR_RMP_Msk      (0x3U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0        (0x1U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1        (0x2U << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos      (2U)                                         
+#define TIM21_OR_TI1_RMP_Msk      (0x7U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0        (0x1U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1        (0x2U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2        (0x4U << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos      (5U)                                         
+#define TIM21_OR_TI2_RMP_Msk      (0x1U << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos      (0U)                                         
+#define TIM22_OR_ETR_RMP_Msk      (0x3U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0        (0x1U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1        (0x2U << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos      (2U)                                         
+#define TIM22_OR_TI1_RMP_Msk      (0x3U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0        (0x1U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1        (0x2U << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos           (23U)                                    
+#define USART_CR3_UCESM_Msk           (0x1U << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
+#define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */ 
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         USB Device General registers                       */
+/*                                                                            */
+/******************************************************************************/
+#define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos           (13U)                                        
+#define USB_PMAADDR_Msk           (0x20003U << USB_PMAADDR_Pos)                /*!< 0x40006000 */
+#define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
+                                             
+#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
+#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
+#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
+#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
+#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
+#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
+#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
+
+/****************************  ISTR interrupt events  *************************/
+#define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
+#define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
+#define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
+
+#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
+#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
+#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
+#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
+/*************************  CNTR control register bits definitions  ***********/
+#define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
+#define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
+#define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
+#define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
+#define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
+#define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
+#define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
+#define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
+/*************************  BCDR control register bits definitions  ***********/
+#define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */  
+#define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */  
+#define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */  
+#define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */ 
+#define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */ 
+#define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */ 
+#define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */  
+#define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
+/***************************  LPM register bits definitions  ******************/
+#define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */ 
+#define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
+/********************  FNR Frame Number Register bit definitions   ************/
+#define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
+#define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
+#define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
+#define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
+#define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
+/********************  DADDR Device ADDRess bit definitions    ****************/
+#define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
+#define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
+/******************************  Endpoint register    *************************/
+#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
+#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
+#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
+#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
+#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
+#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
+#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
+#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
+/* bit positions */ 
+#define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
+#define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
+#define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+                                                                 
+#define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CR_T0    WWDG_CR_T_0
+#define  WWDG_CR_T1    WWDG_CR_T_1
+#define  WWDG_CR_T2    WWDG_CR_T_2
+#define  WWDG_CR_T3    WWDG_CR_T_3
+#define  WWDG_CR_T4    WWDG_CR_T_4
+#define  WWDG_CR_T5    WWDG_CR_T_5
+#define  WWDG_CR_T6    WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CFR_W0    WWDG_CFR_W_0
+#define  WWDG_CFR_W1    WWDG_CFR_W_1
+#define  WWDG_CFR_W2    WWDG_CFR_W_2
+#define  WWDG_CFR_W3    WWDG_CFR_W_3
+#define  WWDG_CFR_W4    WWDG_CFR_W_4
+#define  WWDG_CFR_W5    WWDG_CFR_W_5
+#define  WWDG_CFR_W6    WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM21)  || \
+                                         ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/ 
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
+                                                             ((INSTANCE) == TIM21)  || \
+                                                             ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
+                                                        ((INSTANCE) == TIM21)  || \
+                                                        ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
+                                                          ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
+                                                          ((INSTANCE) == TIM21)  || \
+                                                          ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
+                                                          ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
+                                                          ((INSTANCE) == TIM21)  || \
+                                                          ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM21) || \
+                                         ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
+                                        ((INSTANCE) == TIM21) || \
+                                        ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
+                                            ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM21) || \
+                                            ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM21) || \
+                                            ((INSTANCE) == TIM22))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM21) || \
+                                            ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM21)  || \
+                                         ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                                     ((INSTANCE) == TIM21)  || \
+                                                     ((INSTANCE) == TIM22))
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
+													   
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM21) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+       ((CHANNEL) == TIM_CHANNEL_2)))          \
+     ||                                        \
+     (((INSTANCE) == TIM22) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+       ((CHANNEL) == TIM_CHANNEL_2))))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == LPUART1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == LPUART1))
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/**
+  * @}
+  */
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L0xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L0 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn                   RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
+#define TIM6_IRQn                      TIM6_DAC_IRQn
+#define RCC_IRQn                       RCC_CRS_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
+#define RCC_IRQHandler                 RCC_CRS_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L053xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l0xx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx.h
+  * @author  MCD Application Team
+  * @version V1.7.0
+  * @date    31-May-2016
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32L0xx devices.            
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx
+  * @{
+  */
+    
+#ifndef __STM32L0xx_H
+#define __STM32L0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L0)
+#define STM32L0
+#endif /* STM32L0 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
+    !defined (STM32L031xx) && !defined (STM32L041xx) && \
+    !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
+    !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
+    !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
+    !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
+  /* #define STM32L011xx */
+  /* #define STM32L021xx */
+  /* #define STM32L031xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
+  /* #define STM32L041xx */   /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
+  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
+  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
+  #define STM32L053xx   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
+  /* #define STM32L061xx */   /*!< */
+  /* #define STM32L062xx */   /*!< STM32L062K8 */
+  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
+  /* #define STM32L071xx */   /*!< */
+  /* #define STM32L072xx */   /*!< */
+  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
+  /* #define STM32L081xx */   /*!< */
+  /* #define STM32L082xx */   /*!< */
+  /* #define STM32L083xx */   /*!< */ 
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.7.0
+  */
+#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
+                                      |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
+                                      |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
+                                      |(__STM32L0xx_CMSIS_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32L011xx)
+  #include "stm32l011xx.h"
+#elif defined(STM32L021xx)
+  #include "stm32l021xx.h"
+#elif defined(STM32L031xx)
+  #include "stm32l031xx.h"
+#elif defined(STM32L041xx)
+  #include "stm32l041xx.h"
+#elif defined(STM32L051xx)
+  #include "stm32l051xx.h"
+#elif defined(STM32L052xx)
+  #include "stm32l052xx.h"
+#elif defined(STM32L053xx)
+  #include "stm32l053xx.h"
+#elif defined(STM32L062xx)
+  #include "stm32l062xx.h"
+#elif defined(STM32L063xx)
+  #include "stm32l063xx.h"
+#elif defined(STM32L061xx)
+  #include "stm32l061xx.h"
+#elif defined(STM32L071xx)
+  #include "stm32l071xx.h"
+#elif defined(STM32L072xx)
+  #include "stm32l072xx.h"
+#elif defined(STM32L073xx)
+  #include "stm32l073xx.h"
+#elif defined(STM32L082xx)
+  #include "stm32l082xx.h"
+#elif defined(STM32L083xx)
+  #include "stm32l083xx.h"
+#elif defined(STM32L081xx)
+  #include "stm32l081xx.h"
+#else
+ #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/system_stm32l0xx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,128 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.h
+  * @author  MCD Application Team
+  * @version V1.7.0
+  * @date    31-May-2016
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L0XX_H
+#define __SYSTEM_STM32L0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L0xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L0xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+/*
+*/
+extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
+extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L0XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/objects.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -45,8 +45,8 @@
 
     // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
     //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be >= 0xF0
-    if (pin < 0xF0) {
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
         // Normal channels
         // Get the peripheral name from the pin and assign it to the object
         obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -59,6 +59,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {NC,    NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -59,6 +59,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {NC,    NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -59,6 +59,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {NC,    NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralPins.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralPins.c	Thu Aug 31 17:27:04 2017 +0100
@@ -49,6 +49,10 @@
     {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19
     {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20
     {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {NC,    NC,    0}

--- a/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -41,22 +41,30 @@
 void analogin_init(analogin_t *obj, PinName pin)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct;
+    uint32_t function = (uint32_t)NC;
 
-    // Get the peripheral name from the pin and assign it to the object
-    obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/can_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/can_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -180,10 +180,10 @@
     }
 
     if (hit) {
-        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
-              | ((timing_pts[bits][0] << 16) & 0x000F0000)
-              | ((psjw                << 24) & 0x0000C000)
-              | ((brp                 <<  0) & 0x000003FF);
+        btr = ((timing_pts[bits][1] << CAN_BTR_TS2_Pos) & CAN_BTR_TS2) |
+              ((timing_pts[bits][0] << CAN_BTR_TS1_Pos) & CAN_BTR_TS1) |
+              ((psjw                << CAN_BTR_SJW_Pos) & CAN_BTR_SJW) |
+              ((brp                 << CAN_BTR_BRP_Pos) & CAN_BTR_BRP);
     } else {
         btr = 0xFFFFFFFF;
     }

--- a/targets/TARGET_STM/mbed_rtx.h	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/mbed_rtx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -37,6 +37,7 @@
 #define INITIAL_SP              (0x20004000UL)
 
 #elif (defined(TARGET_STM32F103RB) ||\
+       defined(TARGET_STM32F103C8) ||\
        defined(TARGET_STM32L072CZ) ||\
        defined(TARGET_STM32L073RZ))
 #define INITIAL_SP              (0x20005000UL)

--- a/targets/TARGET_STM/sleep.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_STM/sleep.c	Thu Aug 31 17:27:04 2017 +0100
@@ -34,23 +34,32 @@
 #include "sleep_api.h"
 #include "rtc_api_hal.h"
 #include "hal_tick.h"
+#include "mbed_critical.h"
 
 extern void HAL_SuspendTick(void);
 extern void HAL_ResumeTick(void);
 
 void hal_sleep(void)
 {
+    // Disable IRQs
+    core_util_critical_section_enter();
+
     // Stop HAL tick to avoid to exit sleep in 1ms
     HAL_SuspendTick();
     // Request to enter SLEEP mode
     HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
-
     // Restart HAL tick
     HAL_ResumeTick();
+
+    // Enable IRQs
+    core_util_critical_section_exit();
 }
 
 void hal_deepsleep(void)
 {
+    // Disable IRQs
+    core_util_critical_section_enter();
+
     // Stop HAL tick
     HAL_SuspendTick();
     uint32_t EnterTimeUS = us_ticker_read();
@@ -82,6 +91,9 @@
     // Restart HAL tick
     HAL_ResumeTick();
 
+    // Enable IRQs
+    core_util_critical_section_exit();
+
     // After wake-up from STOP reconfigure the PLL
     SetSysClock();
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,207 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_adc.h
+ * @brief   This file provides all the functions prototypes for ADC driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_ADC_H
+#define __TMPM066_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_ADC_H)
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+#define ADC_CONVERSION_35_CLOCK         ((uint32_t)0x00000000)  /* 35.5 conversion clock */
+#define ADC_CONVERSION_42_CLOCK         ((uint32_t)0x00000040)  /* 42 conversion clock */
+#define ADC_CONVERSION_68_CLOCK         ((uint32_t)0x00000080)  /* 68 conversion clock */
+#define ADC_CONVERSION_81_CLOCK         ((uint32_t)0x000000C0)  /* 81 conversion clock */
+#define IS_ADC_CONVERSION_TIME(param)   (((param) == ADC_CONVERSION_35_CLOCK) || \
+                                         ((param) == ADC_CONVERSION_42_CLOCK) || \
+                                         ((param) == ADC_CONVERSION_68_CLOCK) || \
+                                         ((param) == ADC_CONVERSION_81_CLOCK))
+
+#define ADC_FC_DIVIDE_LEVEL_1           ((uint32_t)0x00000000)
+#define ADC_FC_DIVIDE_LEVEL_2           ((uint32_t)0x00000001)
+#define ADC_FC_DIVIDE_LEVEL_4           ((uint32_t)0x00000002)
+#define ADC_FC_DIVIDE_LEVEL_6           ((uint32_t)0x00000008)
+#define ADC_FC_DIVIDE_LEVEL_8           ((uint32_t)0x00000003)
+#define ADC_FC_DIVIDE_LEVEL_12          ((uint32_t)0x00000009)
+#define ADC_FC_DIVIDE_LEVEL_16          ((uint32_t)0x00000004)
+#define ADC_FC_DIVIDE_LEVEL_24          ((uint32_t)0x0000000A)
+#define ADC_FC_DIVIDE_LEVEL_48          ((uint32_t)0x0000000B)
+#define ADC_FC_DIVIDE_LEVEL_96          ((uint32_t)0x0000000C)
+#define IS_ADC_PRESCALER(param)         (((param) == ADC_FC_DIVIDE_LEVEL_1) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_2) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_4) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_6) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_8) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_12) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_16) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_24) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_48) || \
+                                         ((param) == ADC_FC_DIVIDE_LEVEL_96))
+
+#define ADC_INT_SINGLE                  ((uint32_t)0x00000000)
+#define ADC_INT_CONVERSION_4            ((uint32_t)0x00000008)
+#define ADC_INT_CONVERSION_8            ((uint32_t)0x00000010)
+#define IS_ADC_INT_MODE(param)          (((param) == ADC_INT_SINGLE) || \
+                                         ((param) == ADC_INT_CONVERSION_4) || \
+                                         ((param) == ADC_INT_CONVERSION_8))
+
+#define ADC_AN_0                        ((uint32_t)0x00000000)
+#define ADC_AN_1                        ((uint32_t)0x00000001)
+#define ADC_AN_2                        ((uint32_t)0x00000002)
+#define ADC_AN_3                        ((uint32_t)0x00000003)
+#define ADC_AN_4                        ((uint32_t)0x00000004)
+#define ADC_AN_5                        ((uint32_t)0x00000005)
+#define ADC_AN_6                        ((uint32_t)0x00000006)
+#define ADC_AN_7                        ((uint32_t)0x00000007)
+
+#define IS_ADC_INPUT_CH(param)          (((param) == ADC_AN_0) || \
+                                         ((param) == ADC_AN_1) || \
+                                         ((param) == ADC_AN_2) || \
+                                         ((param) == ADC_AN_3) || \
+                                         ((param) == ADC_AN_4) || \
+                                         ((param) == ADC_AN_5) || \
+                                         ((param) == ADC_AN_6) || \
+                                         ((param) == ADC_AN_7))
+
+
+#define ADC_CMP_0                       ((uint8_t)0x00)
+#define ADC_CMP_1                       ((uint8_t)0x01)
+#define IS_ADC_CMP(param)               (((param) == ADC_CMP_0) || \
+                                         ((param) == ADC_CMP_1))
+
+#define ADC_REG_0                       ((uint32_t)0x00000000)
+#define ADC_REG_1                       ((uint32_t)0x00000001)
+#define ADC_REG_2                       ((uint32_t)0x00000002)
+#define ADC_REG_3                       ((uint32_t)0x00000003)
+#define ADC_REG_4                       ((uint32_t)0x00000004)
+#define ADC_REG_5                       ((uint32_t)0x00000005)
+#define ADC_REG_6                       ((uint32_t)0x00000006)
+#define ADC_REG_7                       ((uint32_t)0x00000007)
+#define ADC_REG_SP                      ((uint32_t)0x00000008)
+#define IS_ADC_REG(param)               ((param) <= ADC_REG_SP)
+
+#define IS_ADC_RESULT_CMP_REG(param)    ((param) <= ADC_REG_SP)
+
+#define ADC_EXT_TRG                     ((uint32_t)0x00000000)
+#define ADC_MATCH_TB_0                  ((uint32_t)0x00000020)
+#define IS_ADC_HW_TRG_NORMAL(param)     (((param) == ADC_EXT_TRG) || \
+                                         ((param) == ADC_MATCH_TB_0))
+
+#define ADC_MATCH_TB_1                  ((uint32_t)0x00000080)
+#define IS_ADC_HW_TRG_TOP(param)        (((param) == ADC_EXT_TRG) || \
+                                         ((param) == ADC_MATCH_TB_1))
+
+#define IS_ADC_CMP_VALUE(param)         ((param) <= (uint16_t)0x03ff)
+
+    typedef enum {
+        ADC_NO_OVERRUN = 0U,
+        ADC_OVERRUN = 1U
+    } ADC_OverrunState;
+
+    typedef enum {
+        ADC_SCAN_4CH = 0U,
+        ADC_SCAN_8CH = 1U
+    } ADC_ChannelScanMode;
+#define IS_ADC_CH_SCAN_MODE(param)      (((param) == ADC_SCAN_4CH) || \
+                                         ((param) == ADC_SCAN_8CH))
+
+    typedef enum {
+        ADC_COMPARISON_SMALLER = 0U,
+        ADC_COMPARISON_LARGER = 1U
+    } ADC_ComparisonState;
+#define IS_ADC_CMP_INT(param)           (((param) == ADC_COMPARISON_SMALLER) || \
+                                         ((param) == ADC_COMPARISON_LARGER))
+
+    typedef struct {
+        WorkState ADCResultStored;      /*!< ADC result storage flag    */
+        ADC_OverrunState ADCOverrunState;       /*!< ADC overrun flag           */
+        uint16_t ADCResultValue;        /*!< ADC result value           */
+    } ADC_ResultTypeDef;
+
+#define ADC_DMA_REQ_NORMAL              ((uint8_t)0x00)
+#define ADC_DMA_REQ_TOP                 ((uint8_t)0x01)
+#define ADC_DMA_REQ_MONITOR1            ((uint8_t)0x02)
+#define ADC_DMA_REQ_MONITOR2            ((uint8_t)0x03)
+#define IS_ADC_DMA_REQ(param)           ((param) <= ADC_DMA_REQ_MONITOR2)
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t NormalBusy:1;      /*!< bit0, Normal A/D conversion busy flag (MOD0<ADBFN>) */
+            uint32_t NormalComplete:1;  /*!< bit1, Normal AD conversion complete flag (MOD0<EOCFN>) */
+            uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (MOD2<ADBFHP>) */
+            uint32_t TopComplete:1;     /*!< bit3, Top-priority AD conversion complete flag (MOD2<EOCFHP>) */
+            uint32_t Reserved:28;       /*!< bit4 to bit 31, reserved */
+        } Bit;
+    } ADC_State;
+
+/** @} */
+/* End of group ADC_Exported_Types */
+
+/** @defgroup ADC_Exported_FunctionPrototypes
+  * @{
+  */
+    void ADC_SWReset(void);
+    void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output);
+    void ADC_Start(void);
+    void ADC_SetScanMode(FunctionalState NewState);
+    void ADC_SetRepeatMode(FunctionalState NewState);
+    void ADC_SetINTMode(uint32_t INTMode);
+    ADC_State ADC_GetConvertState(void);
+    void ADC_SetInputChannel(uint32_t InputChannel);
+    void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode);
+    void ADC_SetIdleMode(FunctionalState NewState);
+    void ADC_SetVref(FunctionalState NewState);
+    void ADC_SetInputChannelTop(uint32_t TopInputChannel);
+    void ADC_StartTopConvert(void);
+    void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState);
+    void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison);
+    void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState);
+    void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState);
+    void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState);
+    ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx);
+    void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value);
+    void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState);
+
+/** @} */
+/* End of group ADC_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group ADC */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* (__TMPM066_ADC_H) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM066_ADC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,180 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_cg.h
+ * @brief   This file provides all the functions prototypes for CG driver.
+ * @version V2.0.2.1
+ * @date    2015/09/29
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_CG_H
+#define __TMPM066_CG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup CG
+  * @{
+  */
+
+/** @addtogroup CG_Exported_types
+  * @{
+  */
+
+    typedef enum {
+        CG_DIVIDE_1 = 0U,
+        CG_DIVIDE_2 = 1U,
+        CG_DIVIDE_4 = 2U,
+        CG_DIVIDE_8 = 3U,
+        CG_DIVIDE_16 = 4U,
+        CG_DIVIDE_32 = 5U,
+        CG_DIVIDE_64 = 6U,
+        CG_DIVIDE_128 = 7U,
+        CG_DIVIDE_256 = 8U,
+        CG_DIVIDE_512 = 9U,
+        CG_DIVIDE_UNKNOWN = 10U,
+        CG_DIVIDE_MAX = 16U
+    } CG_DivideLevel;
+#define IS_CG_GEAR_DIVIDE_LEVEL(param)  (((param) == CG_DIVIDE_1) || \
+                                         ((param) == CG_DIVIDE_2) || \
+                                         ((param) == CG_DIVIDE_4) || \
+                                         ((param) == CG_DIVIDE_8) || \
+                                         ((param) == CG_DIVIDE_16))
+
+#define IS_CG_DIVIDE_FC_LEVEL(param)    (((param) == CG_DIVIDE_1) || \
+                                         ((param) == CG_DIVIDE_2) || \
+                                         ((param) == CG_DIVIDE_4) || \
+                                         ((param) == CG_DIVIDE_8) || \
+                                         ((param) == CG_DIVIDE_16) || \
+                                         ((param) == CG_DIVIDE_32) || \
+                                         ((param) == CG_DIVIDE_64)|| \
+                                         ((param) == CG_DIVIDE_128) || \
+                                         ((param) == CG_DIVIDE_256) || \
+                                         ((param) == CG_DIVIDE_512))
+
+    typedef enum {
+        CG_FOSC_OSC_INT = 0U,
+        CG_FOSC_OSC_EXT = 1U,
+        CG_FOSC_CLKIN_EXT = 2U
+    } CG_FoscSrc;
+#define IS_CG_FOSC_SRC(param)           (((param) == CG_FOSC_OSC_EXT) || \
+                                         ((param) == CG_FOSC_OSC_INT) || \
+                                         ((param) == CG_FOSC_CLKIN_EXT))
+
+#define IS_CG_FOSC_STATE(param)         (((param) == CG_FOSC_OSC_EXT) || \
+                                         ((param) == CG_FOSC_OSC_INT) )
+
+    typedef enum {
+        CG_WARM_UP_SRC_OSC_INT_HIGH = 0U,
+        CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U,
+    } CG_WarmUpSrc;
+#define IS_CG_WARM_UP_SRC(param)        (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \
+                                         ((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH))
+
+    typedef enum {
+        CG_FC_SRC_FOSC = 0U,
+        CG_FC_SRC_FPLL = 1U
+    } CG_FcSrc;
+#define IS_CG_FC_SRC(param)    (((param) == CG_FC_SRC_FOSC) || \
+                                ((param) == CG_FC_SRC_FPLL))
+
+#define CG_8M_MUL_12_FPLL       (0x00C60B00UL<<8U)      /* 12 fold,  input 8MHz, output 96MHz */
+#define CG_10M_MUL_8_FPLL       (0x00C60700UL<<8U)      /* 10 fold,  input 10MHz, output 80MHz */
+#define CG_12M_MUL_8_FPLL       (0x00C60700UL<<8U)      /* 12 fold,  input 12MHz, output 96MHz */
+#define CG_16M_MUL_6_FPLL       (0x00C60500UL<<8U)      /* 16 fold,  input 16MHz, output 96MHz */
+
+#define IS_CG_FPLL_VALUE(param)        (((param) == CG_8M_MUL_12_FPLL) || \
+                                        ((param) == CG_10M_MUL_8_FPLL) || \
+                                        ((param) == CG_12M_MUL_8_FPLL) || \
+                                        ((param) == CG_16M_MUL_6_FPLL))
+    typedef enum {
+        CG_STBY_MODE_IDLE = 0U,
+        CG_STBY_MODE_STOP1 = 1U,
+        CG_STBY_MODE_UNKNOWN = 2U,
+        CG_STBY_MODE_MAX = 4U
+    } CG_STBYMode;
+#define IS_CG_STBY_MODE(param)         (((param) == CG_STBY_MODE_STOP1) || \
+                                        ((param) == CG_STBY_MODE_IDLE))
+#define CG_FC_PERIPH_PORTH          (0x00000001U << 7U)
+#define CG_FC_PERIPH_PORTJ          (0x00000001U << 8U)
+#define CG_FC_PERIPH_TMRB0_3        (0x00000001U << 9U)
+#define CG_FC_PERIPH_TMRB4_6        (0x00000001U << 10U)
+#define CG_FC_PERIPH_TMR16A         (0x00000001U << 11U)
+#define CG_FC_PERIPH_I2C0           (0x00000001U << 12U)
+#define CG_FC_PERIPH_SIO0           (0x00000001U << 13U)
+#define CG_FC_PERIPH_TSPI           (0x00000001U << 14U)
+#define CG_FC_PERIPH_DMAC           (0x00000001U << 15U)
+#define CG_FC_PERIPH_ADC            (0x00000001U << 16U)
+#define CG_FC_PERIPH_USBD           (0x00000001U << 17U)
+#define CG_FC_PERIPH_TMRD           (0x00000001U << 18U)
+#define CG_FC_PERIPHA_ALL           (0xFFFFFFFFU)
+#define IS_CG_FC_PERIPHA(param)     ( ((param) >= CG_FC_PERIPH_PORTH) && ((param) <= CG_FC_PERIPH_TMRD ))
+
+#define CG_FC_PERIPH_TMRB7          (0x00000001U << 28U)
+#define CG_FC_PERIPH_SIO1           (0x00000001U << 29U)
+#define CG_FC_PERIPH_WDT            (0x00000001U << 30U)
+#define CG_FC_PERIPH_I2C1           (0x00000001U << 31U)
+#define CG_FC_PERIPHB_ALL           (0xFFFFFFFFU)
+#define IS_CG_FC_PERIPHB(param)     (((param) >= CG_FC_PERIPH_TMRB7))
+
+#define CG_FPLL_PERIPH_TMRD          (0x00000001U << 5U)
+#define CG_EHCLKSEL_8_24_48MHZ       (0x00000001U << 4U)
+#define CG_USBSEL_PLL_CLOCKIN        (0x00000001U << 1U)
+#define CG_USBENA_USB                (0x00000001U)
+#define CG_FPLL_OPTIONAL_ALL         (0x0FFFFFFFU)
+#define IS_CG_FPLL_OPTIONAL(param)   (((param) > 0U) && ((param) <= CG_FPLL_OPTIONAL_ALL))
+
+/** @} */
+/* End of group CG_Exported_types */
+
+/** @defgroup CG_Exported_FunctionPrototypes
+  * @{
+  */
+    void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc);
+    CG_DivideLevel CG_GetFgearLevel(void);
+    Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc);
+    CG_DivideLevel CG_GetPhiT0Level(void);
+    void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time);
+    void CG_StartWarmUp(void);
+    WorkState CG_GetWarmUpState(void);
+    Result CG_SetFPLLValue(uint32_t NewValue);
+    uint32_t CG_GetFPLLValue(void);
+    Result CG_SetPLL(FunctionalState NewState);
+    FunctionalState CG_GetPLLState(void);
+    void CG_SetFoscSrc(CG_FoscSrc Source);
+    CG_FoscSrc CG_GetFoscSrc(void);
+    void CG_SetSTBYMode(CG_STBYMode Mode);
+    CG_STBYMode CG_GetSTBYMode(void);
+    void CG_SetFcSrc(CG_FcSrc Source);
+    CG_FcSrc CG_GetFcSrc(void);
+    void CG_SetProtectCtrl(FunctionalState NewState);
+    void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState);
+    void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState);
+    void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState);
+    void CG_SetADCClkSupply(FunctionalState NewState);
+
+/** @} */
+/* End of group CG_Exported_FunctionPrototype */
+
+/** @} */
+/* End of group CG */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_CG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,229 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_gpio.h
+ * @brief   This file provides all the functions prototypes for GPIO driver.
+ * @version V2.0.2.1
+ * @date    2015/09/29
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_GPIO_H
+#define __TMPM066_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_GPIO_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+/** @addtogroup GPIO
+  * @{
+  */
+/** @addtogroup  GPIO_Parameter_Definition
+  * @{
+  */
+
+
+/** @brief :The maximum number of the Function Register
+  * Note for porting:
+  * If functiong register 2 is the maximum number in 
+  * all the GPIO port,then define FRMAX (2U)
+  */
+#define FRMAX  (2U)             /* the max number of Port I/O function register is 2 */
+
+
+/** @brief: define for function register
+  * Note for porting:
+  * If the maximum number of the function Register is 2,
+  * then you need to define 2 GPIO_FUNC_REG_x ,
+  * the value should be increased from 0 to 1
+  */
+#define GPIO_FUNC_REG_1                 ((uint8_t)0x00)
+#define GPIO_FUNC_REG_2                 ((uint8_t)0x01)
+
+/** @brief :The GPIO_Port enum
+  * Note for porting:
+  * the port value order from low to high with '1' step
+  * and begin with "0".
+  */
+    typedef enum {
+        GPIO_PA = 0U,
+        GPIO_PB = 1U,        
+        GPIO_PC = 2U,
+        GPIO_PD = 3U,
+        GPIO_PE = 4U,
+        GPIO_PF = 5U,
+        GPIO_PG = 6U,
+        GPIO_PH = 7U,
+        GPIO_PJ = 8U          
+    } GPIO_Port;
+
+#define IS_GPIO_PORT(param)             ((param) <= GPIO_PJ)    /*parameter checking for port number */
+
+#define IS_GPIO_PORT_INPUT_VOLTAGE(param)             (((param) == GPIO_PC) || \
+                                                      ((param) == GPIO_PD) || \
+                                                      ((param) == GPIO_PG))
+
+#define RESER  (8U-(FRMAX))
+
+    typedef struct {
+        __IO uint32_t DATA;
+        __IO uint32_t CR;
+        __IO uint32_t FR[FRMAX];
+        uint32_t RESERVED0[RESER];
+        __IO uint32_t OD;
+        __IO uint32_t PUP;
+        __IO uint32_t PDN;
+        __IO uint32_t SEL;
+        __IO uint32_t IE;
+    } TSB_Port_TypeDef;
+
+    typedef struct {
+        uint8_t PinDATA;
+        uint8_t PinCR;
+        uint8_t PinFR[FRMAX];
+        uint8_t PinOD;
+        uint8_t PinPUP;
+        uint8_t PinPDN;
+        uint8_t PinSEL;
+        uint8_t PinIE;
+    } GPIO_RegTypeDef;
+
+    typedef struct {
+        uint8_t IOMode;         /* Set the port input or output mode       */
+        uint8_t PullUp;         /* Enable or disable Pullup function       */
+        uint8_t OpenDrain;      /* Enable or disable open drain function */
+        uint8_t PullDown;       /* Enable or disable Pulldown function */
+        uint8_t InputVoltage;   /* Enable or disable Input Voltage function */
+    } GPIO_InitTypeDef;
+
+#define GPIO_INPUT_MODE                 ((uint8_t)0x00)
+#define GPIO_OUTPUT_MODE                ((uint8_t)0x01)
+#define GPIO_IO_MODE_NONE               ((uint8_t)0x02)
+#define IS_GPIO_IO_MODE_STATE(param)    (((param) == GPIO_INPUT_MODE) || \
+                                         ((param) == GPIO_OUTPUT_MODE) || \
+                                         ((param) == GPIO_IO_MODE_NONE))
+
+#define GPIO_PULLUP_DISABLE             ((uint8_t)0x00)
+#define GPIO_PULLUP_ENABLE              ((uint8_t)0x01)
+#define GPIO_PULLUP_NONE                ((uint8_t)0x02)
+#define IS_GPIO_PULLUP_STATE(param)     (((param) == GPIO_PULLUP_ENABLE) || \
+                                         ((param) == GPIO_PULLUP_DISABLE) || \
+                                         ((param) == GPIO_PULLUP_NONE))
+
+#define GPIO_PULLDOWN_DISABLE           ((uint8_t)0x00)
+#define GPIO_PULLDOWN_ENABLE            ((uint8_t)0x01)
+#define GPIO_PULLDOWN_NONE              ((uint8_t)0x02)
+#define IS_GPIO_PULLDOWN_STATE(param)   (((param) == GPIO_PULLDOWN_ENABLE) || \
+                                         ((param) == GPIO_PULLDOWN_DISABLE) || \
+                                         ((param) == GPIO_PULLDOWN_NONE))
+
+#define GPIO_OPEN_DRAIN_DISABLE          ((uint8_t)0x00)
+#define GPIO_OPEN_DRAIN_ENABLE           ((uint8_t)0x01)
+#define GPIO_OPEN_DRAIN_NONE             ((uint8_t)0x02)
+#define IS_GPIO_OPEN_DRAIN_STATE(param)  (((param) == GPIO_OPEN_DRAIN_ENABLE) || \
+                                          ((param) == GPIO_OPEN_DRAIN_DISABLE) || \
+                                          ((param) == GPIO_OPEN_DRAIN_NONE))
+
+#define GPIO_INPUT_VOLTAGE_3V          ((uint8_t)0x00)
+#define GPIO_INPUT_VOLTAGE_1V8           ((uint8_t)0x01)
+#define GPIO_INPUT_VOLTAGE_NONE             ((uint8_t)0x02)
+#define IS_GPIO_INPUT_VOLTAGE_STATE(param)  (((param) == GPIO_INPUT_VOLTAGE_3V) || \
+                                            ((param) == GPIO_INPUT_VOLTAGE_1V8) || \
+                                            ((param) == GPIO_INPUT_VOLTAGE_NONE))
+
+#define GPIO_BIT_VALUE_1                ((uint8_t)0x01)
+#define GPIO_BIT_VALUE_0                ((uint8_t)0x00)
+
+#define IS_GPIO_BIT_VALUE(BitValue)     (((BitValue) == GPIO_BIT_VALUE_1)|| \
+                                         ((BitValue) == GPIO_BIT_VALUE_0))
+
+#define GPIO_BIT_0                      ((uint8_t)0x01)
+#define GPIO_BIT_1                      ((uint8_t)0x02)
+#define GPIO_BIT_2                      ((uint8_t)0x04)
+#define GPIO_BIT_3                      ((uint8_t)0x08)
+#define GPIO_BIT_4                      ((uint8_t)0x10)
+#define GPIO_BIT_5                      ((uint8_t)0x20)
+#define GPIO_BIT_6                      ((uint8_t)0x40)
+#define GPIO_BIT_7                      ((uint8_t)0x80)
+#define GPIO_BIT_ALL                    ((uint8_t)0xFF)
+
+#define IS_GPIO_WRITE(GPIO_x)                       (GPIO_SFRs[(GPIO_x)].PinCR)
+
+#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x)              ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\
+                                                    (!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x)))))
+
+#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x)))))
+
+#define IS_GPIO_BIT_IN(GPIO_x,Bit_x)                (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x)))))
+
+#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x)))))
+
+#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x)))))
+
+#define IS_GPIO_BIT_OD(GPIO_x,Bit_x)                (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x)))))
+
+#define IS_GPIO_BIT_SEL(GPIO_x,Bit_x)                (((GPIO_SFRs[(GPIO_x)].PinSEL &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinSEL)&(Bit_x)))))
+
+#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x)      (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x)))))
+
+
+#define IS_GPIO_FUNCTION_REG(param)     ((param) < (FRMAX))
+
+#define IS_GPIO_BIT(param)              (((param) == GPIO_BIT_0)|| \
+                                         ((param) == GPIO_BIT_1)|| \
+                                         ((param) == GPIO_BIT_2)|| \
+                                         ((param) == GPIO_BIT_3)|| \
+                                         ((param) == GPIO_BIT_4)|| \
+                                         ((param) == GPIO_BIT_5)|| \
+                                         ((param) == GPIO_BIT_6)|| \
+                                         ((param) == GPIO_BIT_7))
+/** @} */
+/* End of group GPIO_Bit_Define */
+
+/** @defgroup GPIO_Exported_FunctionPrototypes
+  * @{
+  */
+    uint8_t GPIO_ReadData(GPIO_Port GPIO_x);
+    uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data);
+    void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
+    void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct);
+    void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
+    void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
+    void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
+/** @} */
+/* End of group GPIO_Exported_FunctionPrototypes */
+/** @} */
+/* End of group GPIO */
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* defined(__TMPM066_GPIO_H) */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM066_GPIO_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,203 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_i2c.h
+ * @brief   This file provides all the functions prototypes for I2C driver.
+ * @version V2.0.2.1
+ * @date    2015/09/10
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_I2C_H
+#define __TMPM066_I2C_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /*__cplusplus*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_I2C_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+    typedef struct {
+        uint32_t I2CSelfAddr;   /*!< Specify self-address of the I2C channel in I2C mode */
+        uint32_t I2CDataLen;    /*!< Specify data length of the I2C channel in I2C mode */
+        FunctionalState I2CACKState;    /*!< Enable or disable the generation of ACK clock */
+        uint32_t I2CClkDiv;     /*!< Select the division of the prescaler clock for generating the serial clock */
+        uint32_t PrescalerClkDiv;       /* Select the division of fsys for generating the fprsck */
+    } I2C_InitTypeDef;
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t LastRxBit:1;
+            uint32_t GeneralCall:1;
+            uint32_t SlaveAddrMatch:1;
+            uint32_t ArbitrationLost:1;
+            uint32_t INTReq:1;
+            uint32_t BusState:1;
+            uint32_t TRx:1;
+            uint32_t MasterSlave:1;
+        } Bit;
+    } I2C_State;
+
+#define I2C_CHANNEL_NUMBER              2U
+#define IS_I2C_PERIPH(param)      (((param) == TSB_I2C0) || \
+                                   ((param) == TSB_I2C1))
+
+
+
+
+#define I2C_DATA_LEN_8              ((uint32_t)0x00000000)
+#define I2C_DATA_LEN_1              ((uint32_t)0x00000001)
+#define I2C_DATA_LEN_2              ((uint32_t)0x00000002)
+#define I2C_DATA_LEN_3              ((uint32_t)0x00000003)
+#define I2C_DATA_LEN_4              ((uint32_t)0x00000004)
+#define I2C_DATA_LEN_5              ((uint32_t)0x00000005)
+#define I2C_DATA_LEN_6              ((uint32_t)0x00000006)
+#define I2C_DATA_LEN_7              ((uint32_t)0x00000007)
+
+#define I2C_SCK_CLK_DIV_20              ((uint32_t)0x00000000)
+#define I2C_SCK_CLK_DIV_24              ((uint32_t)0x00000001)
+#define I2C_SCK_CLK_DIV_32              ((uint32_t)0x00000002)
+#define I2C_SCK_CLK_DIV_48              ((uint32_t)0x00000003)
+#define I2C_SCK_CLK_DIV_80              ((uint32_t)0x00000004)
+#define I2C_SCK_CLK_DIV_144             ((uint32_t)0x00000005)
+#define I2C_SCK_CLK_DIV_272             ((uint32_t)0x00000006)
+#define I2C_SCK_CLK_DIV_528             ((uint32_t)0x00000007)
+#define IS_I2C_SCK_CLK_DIV(param)       (((param) == I2C_SCK_CLK_DIV_20) || \
+                                         ((param) == I2C_SCK_CLK_DIV_24) || \
+                                         ((param) == I2C_SCK_CLK_DIV_32) || \
+                                         ((param) == I2C_SCK_CLK_DIV_48) || \
+                                         ((param) == I2C_SCK_CLK_DIV_80) || \
+                                         ((param) == I2C_SCK_CLK_DIV_144) || \
+                                         ((param) == I2C_SCK_CLK_DIV_272) || \
+                                         ((param) == I2C_SCK_CLK_DIV_528))
+
+#define I2C_PRESCALER_DIV_1              ((uint32_t)0x00000001)
+#define I2C_PRESCALER_DIV_2              ((uint32_t)0x00000002)
+#define I2C_PRESCALER_DIV_3              ((uint32_t)0x00000003)
+#define I2C_PRESCALER_DIV_4              ((uint32_t)0x00000004)
+#define I2C_PRESCALER_DIV_5              ((uint32_t)0x00000005)
+#define I2C_PRESCALER_DIV_6              ((uint32_t)0x00000006)
+#define I2C_PRESCALER_DIV_7              ((uint32_t)0x00000007)
+#define I2C_PRESCALER_DIV_8              ((uint32_t)0x00000008)
+#define I2C_PRESCALER_DIV_9              ((uint32_t)0x00000009)
+#define I2C_PRESCALER_DIV_10             ((uint32_t)0x0000000A)
+#define I2C_PRESCALER_DIV_11             ((uint32_t)0x0000000B)
+#define I2C_PRESCALER_DIV_12             ((uint32_t)0x0000000C)
+#define I2C_PRESCALER_DIV_13             ((uint32_t)0x0000000D)
+#define I2C_PRESCALER_DIV_14             ((uint32_t)0x0000000E)
+#define I2C_PRESCALER_DIV_15             ((uint32_t)0x0000000F)
+#define I2C_PRESCALER_DIV_16             ((uint32_t)0x00000010)
+#define I2C_PRESCALER_DIV_17             ((uint32_t)0x00000011)
+#define I2C_PRESCALER_DIV_18             ((uint32_t)0x00000012)
+#define I2C_PRESCALER_DIV_19             ((uint32_t)0x00000013)
+#define I2C_PRESCALER_DIV_20             ((uint32_t)0x00000014)
+#define I2C_PRESCALER_DIV_21             ((uint32_t)0x00000015)
+#define I2C_PRESCALER_DIV_22             ((uint32_t)0x00000016)
+#define I2C_PRESCALER_DIV_23             ((uint32_t)0x00000017)
+#define I2C_PRESCALER_DIV_24             ((uint32_t)0x00000018)
+#define I2C_PRESCALER_DIV_25             ((uint32_t)0x00000019)
+#define I2C_PRESCALER_DIV_26             ((uint32_t)0x0000001A)
+#define I2C_PRESCALER_DIV_27             ((uint32_t)0x0000001B)
+#define I2C_PRESCALER_DIV_28             ((uint32_t)0x0000001C)
+#define I2C_PRESCALER_DIV_29             ((uint32_t)0x0000001D)
+#define I2C_PRESCALER_DIV_30             ((uint32_t)0x0000001E)
+#define I2C_PRESCALER_DIV_31             ((uint32_t)0x0000001F)
+#define I2C_PRESCALER_DIV_32             ((uint32_t)0x00000020)
+
+/** @} */
+/* End of group I2C_Exported_Types */
+
+/** @defgroup I2C_Exported_Macros 
+  * @{
+  */
+#define IS_PRESCALER_CLK_VALID(param1, param2)     (((param1) >= I2C_PRESCALER_DIV_1) && \
+                                                    ((param1) <= I2C_PRESCALER_DIV_32) && \
+                                                    (((param2) / (param1)) > 666666U) && \
+                                                    (((param2) / (param1)) < 20000000U))
+
+#define IS_I2C_DATA(param)              ((param) <= (uint32_t)0x000000FF)
+
+#define IS_I2C_BIT_NUM(param)           ((param) <= (uint32_t)0x00000007)
+
+#define IS_I2C_ADDR(param)              (((param) < (uint32_t)0x000000FF) && \
+                                         (!((param) & (uint32_t)0x00000001)))
+
+/** @} */
+/* End of group I2C_Exported_Macros */
+
+/** @defgroup I2C_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct);
+    void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum);
+    void I2C_SWReset(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx);
+    void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx);
+    void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx);
+    I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data);
+    uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock);
+
+    void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+
+    FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx);
+    FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx);
+    FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx);
+    FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx);
+
+    void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTI2COutput(TSB_I2C_TypeDef * I2Cx);
+
+    void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx);
+
+
+/** @} */
+/* End of group I2C_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group I2C */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* defined(__TMPM066_I2C_H) */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_I2C_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,100 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_intifao.h
+ * @brief   This file provides all the functions prototypes for INTIFAO driver.
+ * @version V2.0.2.1
+ * @date    2015/10/19
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_INTIFAO_H
+#define __TMPM066_INTIFAO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup INTIFAO
+  * @{
+  */
+
+/** @addtogroup INTIFAO_Exported_types
+  * @{
+  */
+    typedef struct {
+        uint32_t All;
+    } INTIFAO_IntFlag1Factor;
+
+    typedef enum {
+        INTIFAO_INT_SRC_0 = 0U,
+        INTIFAO_INT_SRC_1 = 1U,
+        INTIFAO_INT_SRC_2 = 2U,
+        INTIFAO_INT_SRC_3 = 3U,
+        INTIFAO_INT_SRC_4 = 4U,
+        INTIFAO_INT_SRC_5 = 5U,
+        INTIFAO_INT_SRC_I2CS = 6U,
+        INTIFAO_INT_SRC_USBWKUP = 7U
+     } INTIFAO_INTSrc;
+     
+#define IS_INTIFAO_INT_SRC(param)    (((param) == INTIFAO_INT_SRC_0) || \
+                                 ((param) == INTIFAO_INT_SRC_1) || \
+                                 ((param) == INTIFAO_INT_SRC_2) || \
+                                 ((param) == INTIFAO_INT_SRC_3) || \
+                                 ((param) == INTIFAO_INT_SRC_4) || \
+                                 ((param) == INTIFAO_INT_SRC_5) || \
+                                 ((param) == INTIFAO_INT_SRC_I2CS) || \
+                                 ((param) == INTIFAO_INT_SRC_USBWKUP))
+
+    typedef enum {
+        INTIFAO_INT_ACTIVE_STATE_L = 0x0U,
+        INTIFAO_INT_ACTIVE_STATE_H = 0x1U,
+        INTIFAO_INT_ACTIVE_STATE_FALLING = 0x2U,
+        INTIFAO_INT_ACTIVE_STATE_RISING = 0x3U,
+        INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES = 0x4U,
+        INTIFAO_INT_ACTIVE_STATE_INVALID = 0x5U
+    } INTIFAO_INTActiveState;
+#define IS_INTIFAO_INT_ACTIVE_STATE(param)        (((param) == INTIFAO_INT_ACTIVE_STATE_L) || \
+                                              ((param) == INTIFAO_INT_ACTIVE_STATE_H) || \
+                                              ((param) == INTIFAO_INT_ACTIVE_STATE_FALLING) || \
+                                              ((param) == INTIFAO_INT_ACTIVE_STATE_RISING) || \
+                                              ((param) == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES))
+
+#define IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(param)  ((param) == INTIFAO_INT_ACTIVE_STATE_RISING)
+               
+/** @} */
+/* End of group INTIFAO_Exported_types */
+
+/** @defgroup INTIFAO_Exported_FunctionPrototypes
+  * @{
+  */
+    void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource,                                     
+                                 INTIFAO_INTActiveState ActiveState, FunctionalState NewState);
+    INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource);                     
+    void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource);   
+
+    INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void);
+
+/** @} */
+/* End of group INTIFAO_Exported_FunctionPrototype */
+
+/** @} */
+/* End of group INTIFAO */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_INTIFAO_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,228 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_intifsd.h
+ * @brief   This file provides all the functions prototypes for INTIFSD driver.
+ * @version V2.0.2.2
+ * @date    2016/02/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_INTIFSD_H
+#define __TMPM066_INTIFSD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup INTIFSD
+  * @{
+  */
+
+/** @addtogroup INTIFSD_Exported_types
+  * @{
+  */                                      
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t Reserved1:16;
+            uint32_t DetectLowVoltage:1;           
+            uint32_t DetectOverVoltage:1;  
+            uint32_t WDT:1;
+            uint32_t Reserved2:13;
+        } Bit;
+    } INTIFSD_NMIFactor;   
+
+    typedef struct {
+        uint32_t All;
+    } INTIFSD_IntFlag3Factor;
+
+    typedef struct {
+        uint32_t All;
+    } INTIFSD_IntFlag4Factor;
+
+    typedef struct {
+        uint32_t All;
+    } INTIFSD_IntFlag5Factor;
+
+    typedef enum {
+        INTIFSD_INT_SRC_LVD_PSFD = 0U,
+        INTIFSD_INT_SRC_LVD_PRD = 1U,
+        INTIFSD_INT_SRC_WDT = 2U,
+        INTIFSD_INT_SRC_DMAC_0 = 3U,
+        INTIFSD_INT_SRC_DMAC_1 = 4U,
+        INTIFSD_INT_SRC_DMAC_2 = 5U,
+        INTIFSD_INT_SRC_DMAC_3 = 6U,
+        INTIFSD_INT_SRC_DMAC_4 = 7U,
+        INTIFSD_INT_SRC_DMAC_5 = 8U,
+        INTIFSD_INT_SRC_DMAC_6 = 9U,
+        INTIFSD_INT_SRC_DMAC_7 = 10U,
+        INTIFSD_INT_SRC_DMAC_8 = 11U,
+        INTIFSD_INT_SRC_DMAC_9 = 12U,
+        INTIFSD_INT_SRC_DMAC_10 = 13U,
+        INTIFSD_INT_SRC_DMAC_11 = 14U,
+        INTIFSD_INT_SRC_DMAC_12 = 15U,
+        INTIFSD_INT_SRC_DMAC_13 = 16U,
+        INTIFSD_INT_SRC_DMAC_14 = 17U,
+        INTIFSD_INT_SRC_DMAC_15 = 18U,
+        INTIFSD_INT_SRC_DMAC_16 = 19U,
+        INTIFSD_INT_SRC_DMAC_17 = 20U,
+        INTIFSD_INT_SRC_DMAC_18 = 21U,
+        INTIFSD_INT_SRC_DMAC_19 = 22U,
+        INTIFSD_INT_SRC_DMAC_20 = 23U,
+        INTIFSD_INT_SRC_DMAC_21 = 24U,
+        INTIFSD_INT_SRC_DMAC_22 = 25U,
+        INTIFSD_INT_SRC_DMAC_23 = 26U,
+        INTIFSD_INT_SRC_DMAC_24 = 27U,
+        INTIFSD_INT_SRC_DMAC_25 = 28U,
+        INTIFSD_INT_SRC_DMAC_26 = 29U,
+        INTIFSD_INT_SRC_DMAC_27 = 30U,
+        INTIFSD_INT_SRC_DMAC_28 = 31U,
+        INTIFSD_INT_SRC_DMAC_29 = 32U,
+        INTIFSD_INT_SRC_DMAC_30 = 33U,
+        INTIFSD_INT_SRC_DMAC_31 = 34U,
+        INTIFSD_INT_SRC_DMAC_ERR = 35U,
+        INTIFSD_INT_SRC_TMRB_0_MDOVF = 36U,
+        INTIFSD_INT_SRC_TMRB_0_CAP0 = 37U,
+        INTIFSD_INT_SRC_TMRB_0_CAP1 = 38U,
+        INTIFSD_INT_SRC_TMRB_1_MDOVF = 39U,
+        INTIFSD_INT_SRC_TMRB_1_CAP0 = 40U,
+        INTIFSD_INT_SRC_TMRB_1_CAP1 = 41U,
+        INTIFSD_INT_SRC_TMRB_2_MDOVF = 42U,
+        INTIFSD_INT_SRC_TMRB_2_CAP0 = 43U,
+        INTIFSD_INT_SRC_TMRB_2_CAP1 = 44U,
+        INTIFSD_INT_SRC_TMRB_3_MDOVF = 45U,
+        INTIFSD_INT_SRC_TMRB_3_CAP0 = 46U,
+        INTIFSD_INT_SRC_TMRB_3_CAP1 = 47U,
+        INTIFSD_INT_SRC_TMRB_4_MDOVF = 48U,
+        INTIFSD_INT_SRC_TMRB_4_CAP0 = 49U,
+        INTIFSD_INT_SRC_TMRB_4_CAP1 = 50U,
+        INTIFSD_INT_SRC_TMRB_5_MDOVF = 51U,
+        INTIFSD_INT_SRC_TMRB_5_CAP0 = 52U,
+        INTIFSD_INT_SRC_TMRB_5_CAP1 = 53U,
+        INTIFSD_INT_SRC_TMRB_6_MDOVF = 54U,
+        INTIFSD_INT_SRC_TMRB_6_CAP0 = 55U,
+        INTIFSD_INT_SRC_TMRB_6_CAP1 = 56U,
+        INTIFSD_INT_SRC_TMRB_7_MDOVF = 57U,
+        INTIFSD_INT_SRC_TMRB_7_CAP0 = 58U,
+        INTIFSD_INT_SRC_TMRB_7_CAP1 = 59U,
+        INTIFSD_INT_SRC_TMRD_00 = 60U,
+        INTIFSD_INT_SRC_TMRD_01 = 61U,
+        INTIFSD_INT_SRC_TMRD_02 = 62U,
+        INTIFSD_INT_SRC_TMRD_03 = 63U,
+        INTIFSD_INT_SRC_TMRD_04 = 64U,
+        INTIFSD_INT_SRC_TMRD_10 = 65U,
+        INTIFSD_INT_SRC_TMRD_11 = 66U,
+        INTIFSD_INT_SRC_TMRD_12 = 67U,
+        INTIFSD_INT_SRC_TMRD_13 = 68U,
+        INTIFSD_INT_SRC_TMRD_14 = 69U
+     } INTIFSD_INTSrc;
+
+#define IS_INTIFSD_INT_SRC(param)   (((param) == INTIFSD_INT_SRC_LVD_PSFD) || \
+                                    ((param) == INTIFSD_INT_SRC_LVD_PRD) || \
+                                    ((param) == INTIFSD_INT_SRC_WDT) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_2) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_3) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_4) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_5) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_6) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_7) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_8) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_9) ||  \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_10) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_11) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_12) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_13) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_14) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_15) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_16) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_17) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_18) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_19) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_20) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_21) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_22) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_23) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_24) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_25) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_26) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_27) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_28) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_29) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_30) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_31) || \
+                                    ((param) == INTIFSD_INT_SRC_DMAC_ERR) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_0_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_0_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_0_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_1_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_1_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_1_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_2_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_2_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_2_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_3_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_3_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_3_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_4_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_4_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_4_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_5_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_5_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_5_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_6_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_6_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_6_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_7_MDOVF) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_7_CAP0) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRB_7_CAP1) ||  \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_00) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_01) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_02) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_03) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_04) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_10) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_11) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_12) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_13) || \
+                                    ((param) == INTIFSD_INT_SRC_TMRD_14))
+
+/** @} */
+/* End of group INTIFSD_Exported_types */
+
+/** @defgroup INTIFSD_Exported_FunctionPrototypes
+  * @{
+  */
+    INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void);
+
+    void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource);
+
+    INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void);
+    INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void);
+    INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void);
+
+/** @} */
+/* End of group INTIFSD_Exported_FunctionPrototype */
+
+/** @} */
+/* End of group INTIFSD */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_INTIFSD_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,108 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_tmr16a.h
+ * @brief   This file provides all the functions prototypes for TMR16A driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_TMR16A_H
+#define __TMPM066_TMR16A_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_TMR16A_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup TMR16A
+  * @{
+  */
+
+/** @defgroup TMR16A_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief TMR16A Flip-flop Structure definition
+  */
+
+    typedef struct {
+        uint32_t TMR16AFlipflopCtrl;    /*!< Select TMR16A flip-flop output level */
+        uint32_t TMR16AFlipflopReverseTrg;      /*!< Specify TMR16A flip-flop reverse trigger */
+    } TMR16A_FFOutputTypeDef;
+
+/** @} */
+/* End of group TMR16A_Exported_Types */
+
+/** @defgroup TMR16A_Exported_Constants
+  * @{
+  */
+#define IS_TMR16A_ALL_PERIPH(param)    (((param) == TSB_T16A0) || \
+                                        ((param) == TSB_T16A1))
+
+
+
+#define TMR16A_SYSCK                    ((uint32_t)0x00000000)
+#define TMR16A_PRCK                     ((uint32_t)0x00000001)
+#define IS_TMR16A_SRCCLK(param)         (((param) == TMR16A_SYSCK) || ((param) == TMR16A_PRCK))
+
+#define TMR16A_RUN                      ((uint32_t)0x00000001)
+#define TMR16A_STOP                     ((uint32_t)0x00000000)
+#define IS_TMR16A_CMD(param)            (((param) == TMR16A_RUN) || ((param) == TMR16A_STOP))
+
+#define TMR16A_RUNNING_IN_CORE_HALT        ((uint8_t)0x00)
+#define TMR16A_STOP_IN_CORE_HALT           ((uint8_t)0x02)
+#define IS_TMR16A_CLK_IN_CORE_HALT(param)  (((param) == TMR16A_RUNNING_IN_CORE_HALT) || \
+                                           ((param) == TMR16A_STOP_IN_CORE_HALT))
+
+#define TMR16A_FLIPFLOP_INVERT         ((uint32_t)0x00000000)
+#define TMR16A_FLIPFLOP_SET            ((uint32_t)0x00000001)
+#define TMR16A_FLIPFLOP_CLEAR          ((uint32_t)0x00000002)
+#define IS_TMR16A_FLIPFLOP_CTRL(param) (((param) == TMR16A_FLIPFLOP_INVERT) || \
+                                        ((param) == TMR16A_FLIPFLOP_SET) || \
+                                        ((param) == TMR16A_FLIPFLOP_CLEAR))
+
+#define TMR16A_DISABLE_FLIPFLOP        ((uint32_t)0x00000000)
+#define TMR16A_FLIPFLOP_MATCH_CYCLE    ((uint32_t)0x00000080)
+#define IS_TMR16A_FLIPFLOP_TRG(param)  (((param) == TMR16A_DISABLE_FLIPFLOP) || \
+                                        ((param) == TMR16A_FLIPFLOP_MATCH_CYCLE))
+
+#define IS_TMR16A_VALUE(param)          ((param) <= 0x0000FFFFU)
+#define IS_TMR16A_VALID_DUTY(param1, param2) ((param1) <= (param2))
+
+/* End of group TMR16A_Exported_Constants */
+/** @defgroup TMR16A_Exported_FunctionPrototypes
+  * @{
+  */
+    void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState);
+    void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd);
+    void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk);
+    void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct);
+    void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle);
+    uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax);
+/** @} */
+/* End of group TMR16A_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group TMR16A */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* defined(__TMPM066_TMR16A_H) */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_TMR16A_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,259 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_tmrb.h
+ * @brief   This file provides all the functions prototypes for TMRB driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_TMRB_H
+#define __TMPM066_TMRB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_TMRB_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+/** @addtogroup TMRB
+  * @{
+  */
+/** @defgroup TMRB_Exported_Types
+  * @{
+  */
+/**
+  * @brief TMRB Init Structure definition
+  */
+    typedef struct {
+        uint32_t Mode;          /*!< Select TMRB mode between internal interval
+                                   timer mode and external event counter */
+        uint32_t ClkDiv;        /*!< Select the division for TMRB source clock */
+        uint32_t TrailingTiming;        /*!< Specify the trailingtiming value to be written 
+                                           into TBnRG1 */
+        uint32_t UpCntCtrl;     /*!< Select up-counter work mode between 
+                                   freerun and auto-reload */
+        uint32_t LeadingTiming; /*!< Specify the leadingtiming value to be written 
+                                   into TBnRG0 */
+    } TMRB_InitTypeDef;
+
+/**
+  * @brief TMRB Flip-flop Structure definition
+  */
+
+    typedef struct {
+        uint32_t FlipflopCtrl;  /*!< Select TMRB flip-flop output level */
+        uint32_t FlipflopReverseTrg;    /*!< Specify TMRB flip-flop reverse trigger */
+    } TMRB_FFOutputTypeDef;
+
+/**
+  * @brief TMRB Interrupt factor Union definition
+  */
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t MatchLeadingTiming:1;
+            uint32_t MatchTrailingTiming:1;
+            uint32_t OverFlow:1;
+            uint32_t Reserverd:29;
+        } Bit;
+    } TMRB_INTFactor;
+
+/**                                              
+  * @brief TMRB Interrupt masked Union definition
+  */
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t MatchLeadingTimingMask:1;
+            uint32_t MatchTrailingTimingMask:1;
+            uint32_t OverFlowMask:1;
+            uint32_t Reserverd:29;
+        } Bit;
+    } TMRB_INTMask;
+
+/** @} */
+/* End of group TMRB_Exported_Types */
+
+/** @defgroup TMRB_Exported_Constants
+  * @{
+  */
+#define IS_TMRB_ALL_PERIPH(param)    (((param) == TSB_TB0) || \
+                                      ((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB4) || \
+                                      ((param) == TSB_TB5) || \
+                                      ((param) == TSB_TB6) || \
+                                      ((param) == TSB_TB7))
+
+#define IS_TMRB_SYNC_PERIPH(param)   (((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB5) || \
+                                      ((param) == TSB_TB6) || \
+                                      ((param) == TSB_TB7))
+
+#define IS_TMRB_CAP_PERIPH(param)    (((param) == TSB_TB0) || \
+                                      ((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB4) || \
+                                      ((param) == TSB_TB5))
+
+#define TMRB_INTERVAL_TIMER          ((uint32_t)0x00000001)
+#define TMRB_EVENT_CNT               ((uint32_t)0x00000000)
+#define IS_TMRB_MODE(param)          (((param) == TMRB_INTERVAL_TIMER) || \
+                                      ((param) == TMRB_EVENT_CNT))
+
+#define TMRB_CLK_DIV_2               ((uint32_t)0x00000001)
+#define TMRB_CLK_DIV_8               ((uint32_t)0x00000002)
+#define TMRB_CLK_DIV_32              ((uint32_t)0x00000003)
+#define TMRB_CLK_DIV_64              ((uint32_t)0x00000004)
+#define TMRB_CLK_DIV_128             ((uint32_t)0x00000005)
+#define TMRB_CLK_DIV_256             ((uint32_t)0x00000006)
+#define TMRB_CLK_DIV_512             ((uint32_t)0x00000007)
+#define IS_TMRB_CLK_DIV(param)       (((param) == TMRB_CLK_DIV_2) || \
+                                      ((param) == TMRB_CLK_DIV_8) || \
+                                      ((param) == TMRB_CLK_DIV_32) || \
+                                      ((param) == TMRB_CLK_DIV_64) || \
+                                      ((param) == TMRB_CLK_DIV_128) || \
+                                      ((param) == TMRB_CLK_DIV_256) || \
+                                      ((param) == TMRB_CLK_DIV_512))
+
+#define TMRB_FREE_RUN                ((uint32_t)0x00000000)
+#define TMRB_AUTO_CLEAR              ((uint32_t)0x00000008)
+#define IS_TMRB_UC_CTRL(param)       (((param) == TMRB_FREE_RUN) || \
+                                      ((param) == TMRB_AUTO_CLEAR))
+
+#define TMRB_FLIPFLOP_INVERT         ((uint32_t)0x00000000)
+#define TMRB_FLIPFLOP_SET            ((uint32_t)0x00000001)
+#define TMRB_FLIPFLOP_CLEAR          ((uint32_t)0x00000002)
+#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \
+                                      ((param) == TMRB_FLIPFLOP_SET) || \
+                                      ((param) == TMRB_FLIPFLOP_CLEAR))
+
+#define TMRB_DISABLE_FLIPFLOP        ((uint32_t)0x00000000)
+#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010)
+#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020)
+#define TMRB_FLIPFLOP_MATCH_TRAILINGTIMING    ((uint32_t)0x00000008)
+#define TMRB_FLIPFLOP_MATCH_LEADINGTIMING     ((uint32_t)0x00000004)
+#define IS_TMRB_FLIPFLOP_TRG(param)  (((param) == TMRB_DISABLE_FLIPFLOP) || \
+                                      ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \
+                                      ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \
+                                      ((param) == TMRB_FLIPFLOP_MATCH_TRAILINGTIMING) || \
+                                      ((param) == TMRB_FLIPFLOP_MATCH_LEADINGTIMING) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)))
+
+#define TMRB_DISABLE_CAPTURE                ((uint32_t)0x00000000)
+#define TMRB_CAPTURE_IN_RISING_FALLING      ((uint32_t)0x00000020)
+#define TMRB_CAPTURE_FF_RISING_FALLING      ((uint32_t)0x00000030)
+#define IS_TMRB_CAPTURE_TIMING(param)       (((param) == TMRB_DISABLE_CAPTURE) || \
+                                             ((param) == TMRB_CAPTURE_IN_RISING_FALLING) || \
+                                             ((param) == TMRB_CAPTURE_FF_RISING_FALLING))
+
+#define TMRB_RUN                      ((uint32_t)0x00000005)
+#define TMRB_STOP                     ((uint32_t)0x00000000)
+#define IS_TMRB_CMD(param)            (((param) == TMRB_RUN) || ((param) == TMRB_STOP))
+
+#define TMRB_REG_0                ((uint8_t)0x00)
+#define TMRB_REG_1                ((uint8_t)0x01)
+#define IS_TMRB_REG(param)    (((param) == TMRB_REG_0) || ((param) == TMRB_REG_1))
+
+#define TMRB_CAPTURE_0                ((uint8_t)0x00)
+#define TMRB_CAPTURE_1                ((uint8_t)0x01)
+#define IS_TMRB_CAPTURE_REG(param)    (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1))
+
+#define TMRB_NO_INT_MASK              ((uint32_t)0x00000000)
+#define TMRB_MASK_MATCH_LEADINGTIMING_INT      ((uint32_t)0x00000001)
+#define TMRB_MASK_MATCH_TRAILINGTIMING_INT     ((uint32_t)0x00000002)
+#define TMRB_MASK_OVERFLOW_INT        ((uint32_t)0x00000004)
+#define IS_TMRB_INT_MASK(param)       (((param) == TMRB_NO_INT_MASK) || \
+                                       ((param) == TMRB_MASK_MATCH_LEADINGTIMING_INT) || \
+                                       ((param) == TMRB_MASK_MATCH_TRAILINGTIMING_INT) || \
+                                       ((param) == TMRB_MASK_OVERFLOW_INT) || \
+                                       ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT)) || \
+                                       ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
+                                       ((param) == (TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
+                                       ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)))
+
+#define TMRB_TRG_EDGE_RISING          ((uint8_t)0x00)
+#define TMRB_TRG_EDGE_FALLING         ((uint8_t)0x02)
+#define IS_TMRB_TRG_EDGE(param)       (((param) == TMRB_TRG_EDGE_RISING) || \
+                                       ((param) == TMRB_TRG_EDGE_FALLING))
+
+#define TMRB_RUNNING_IN_CORE_HALT        ((uint8_t)0x00)
+#define TMRB_STOP_IN_CORE_HALT           ((uint8_t)0x40)
+#define IS_TMRB_CLK_IN_CORE_HALT(param)  (((param) == TMRB_RUNNING_IN_CORE_HALT) || \
+                                          ((param) == TMRB_STOP_IN_CORE_HALT))
+
+#define TMRB_NO_INT                   ((uint32_t)0x00000000)
+#define IS_TMRB_VALUE(param)          ((param) <= 0x0000FFFFU)
+#define IS_VALID_LEADINGTIMING(param1, param2) ((param1) <= (param2))
+
+#define TMRB_DMA_REQ_CMP_MATCH                   ((uint32_t)0x000000004)
+#define TMRB_DMA_REQ_CAPTURE_1                   ((uint32_t)0x000000002)
+#define TMRB_DMA_REQ_CAPTURE_0                   ((uint32_t)0x000000001)
+#define IS_TMRB_DMA_REQ(param)                   (((param) == TMRB_DMA_REQ_CMP_MATCH) || \
+                                                  ((param) == TMRB_DMA_REQ_CAPTURE_1) || \
+                                                  ((param) == TMRB_DMA_REQ_CAPTURE_0))
+
+/** @} */
+/* End of group TMRB_Exported_Constants */
+/** @defgroup TMRB_Exported_FunctionPrototypes
+  * @{
+  */
+    void TMRB_Enable(TSB_TB_TypeDef * TBx);
+    void TMRB_Disable(TSB_TB_TypeDef * TBx);
+    void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd);
+    void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct);
+    void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming);
+    void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct);
+    TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx);
+    TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx);
+    void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask);
+    void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming);
+    void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming);
+    uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg);
+    uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx);
+    uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg);
+    void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx);
+    void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
+    void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState);
+    void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode);
+    void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState);
+    void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq);
+
+/** @} */
+/* End of group TMRB_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group TMRB */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* defined(__TMPM066_TMRB_H) */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM066_TMRB_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,381 @@
+/** 
+ *******************************************************************************
+ * @file    tmpm066_uart.h
+ * @brief   This file provides all the functions prototypes for UART driver.
+ * @version V2.0.2.1
+ * @date    2015/09/10
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM066_UART_H
+#define __TMPM066_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM066.h"
+#include "tx00_common.h"
+
+#if defined(__TMPM066_UART_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/** @defgroup UART_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  UART Init Structure definition
+  */
+
+    typedef struct {
+        uint32_t BaudRate;      /*!< This member configures the UART communication
+                                   baud rate. */
+        uint32_t DataBits;      /*!< Specifies UART transfer mode, which could be 
+                                   7-bit mode, 8-bit mode or 9-bit mode. */
+        uint32_t StopBits;      /*!< Specifies the length of stop bit transmission
+                                   in UART mode. */
+        uint32_t Parity;        /*!< Specifies the parity mode which could be odd 
+                                   parity, even parity or no parity. */
+        uint32_t Mode;          /*!< Enables or disables Receive, Transmit or 
+                                   both. */
+        uint32_t FlowCtrl;      /*!< Specifies wether the hardware flow control 
+                                   mode is enabled or disabled. */
+    } UART_InitTypeDef;
+
+    typedef struct {
+        uint32_t InputClkEdge;  /*!< Select the input clock edge.on the SCLK output mode
+                                   this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */
+        uint32_t TIDLE;         /*!< The status of TXDx pin after output of the
+                                   last bit */
+        uint32_t TXDEMP;        /*!< The status of TXDx pin when an under run error 
+                                   is  occured in SCLK input mode */
+        uint32_t EHOLDTime;     /*!< The last bit hold time of TXDx pin in SCLK
+                                   input mode */
+        uint32_t IntervalTime;  /*!< Setting interval time of continuous transmission which 
+                                   could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK.
+                                   this bit is valid only for SCLK output mode and double 
+                                   buffer is enabled. */
+        uint32_t TransferMode;  /*!< Setting transfer mode which could be transfer prohibited, 
+                                   half duplex(Receive),half duplex(Transmit) or full duplex. */
+        uint32_t TransferDir;   /*!< Setting transfer direction which could be
+                                   LSB_FRIST or MSB_FRIST. */
+        uint32_t Mode;          /*!< Enables or disables Receive, Transmit or both. */
+        uint32_t DoubleBuffer;  /*!< Double Buffer mode is enabled or disabled. */
+        uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */
+        uint32_t Divider;       /*!< Division ratio "N" */
+    } SIO_InitTypeDef;
+
+/** @} */
+/* End of group UART_Exported_Types */
+
+/** @defgroup UART_Exported_Constants
+  * @{
+  */
+
+#define UART0  TSB_SC0
+#define UART1  TSB_SC1
+
+#define IS_UART_PERIPH(param)       (((param) == UART0)  || \
+                                     ((param) == UART1))
+
+#define SIO0  TSB_SC0
+#define SIO1  TSB_SC1
+
+#define IS_SIO_PERIPH(param)       (((param) == SIO0)  || \
+                                    ((param) == SIO1))
+
+#define UART_DATA_BITS_7            ((uint32_t)0x00000004)
+#define UART_DATA_BITS_8            ((uint32_t)0x00000008)
+#define UART_DATA_BITS_9            ((uint32_t)0x0000000C)
+#define IS_UART_DATA_BITS(param)    (((param) == UART_DATA_BITS_7) || \
+                                     ((param) == UART_DATA_BITS_8) || \
+                                     ((param) == UART_DATA_BITS_9))
+
+#define UART_STOP_BITS_1            ((uint32_t)0x00000000)
+#define UART_STOP_BITS_2            ((uint32_t)0x00000010)
+#define IS_UART_STOPBITS(param)     (((param) == UART_STOP_BITS_1) || \
+                                     ((param) == UART_STOP_BITS_2))
+
+#define UART_NO_PARITY              ((uint32_t)0x00000000)
+#define UART_EVEN_PARITY            ((uint32_t)0x00000060)
+#define UART_ODD_PARITY             ((uint32_t)0x00000020)
+#define IS_UART_PARITY(param)       (((param) == UART_NO_PARITY) || \
+                                     ((param) == UART_EVEN_PARITY) || \
+                                     ((param) == UART_ODD_PARITY))
+
+#define SIO_CLK_SCLKOUTPUT            ((uint32_t)0x00000000)
+#define SIO_CLK_SCLKINPUT           ((uint32_t)0x00000001)
+#define IS_SIO_CLK_SEL(param)       (((param) == SIO_CLK_SCLKOUTPUT) || \
+                                     ((param) == SIO_CLK_SCLKINPUT))
+
+#define SIO_SCLKS_TXDF_RXDR         ((uint32_t)0x00000000)
+#define SIO_SCLKS_TXDR_RXDF         ((uint32_t)0x00000002)
+#define IS_SIO_SCLKS_TRXD(param)    (((param) == SIO_SCLKS_TXDF_RXDR) || \
+                                     ((param) == SIO_SCLKS_TXDR_RXDF))
+
+#define SIO_TIDLE_LOW               ((uint32_t)0x00000000)
+#define SIO_TIDLE_HIGH              ((uint32_t)0x00000100)
+#define SIO_TIDLE_LAST              ((uint32_t)0x00000200)
+#define IS_SIO_TIDLE_LEVEL(param)   (((param) == SIO_TIDLE_LOW) || \
+                                     ((param) == SIO_TIDLE_HIGH) || \
+                                     ((param) == SIO_TIDLE_LAST))
+
+#define SIO_TXDEMP_LOW               ((uint32_t)0x00000000)
+#define SIO_TXDEMP_HIGH              ((uint32_t)0x00000400)
+#define IS_SIO_TXDEMP_LEVEL(param)  (((param) == SIO_TXDEMP_LOW) || \
+                                     ((param) == SIO_TXDEMP_HIGH))
+
+#define SIO_EHOLD_FC_2               ((uint32_t)0x00000000)
+#define SIO_EHOLD_FC_4               ((uint32_t)0x00001000)
+#define SIO_EHOLD_FC_8               ((uint32_t)0x00002000)
+#define SIO_EHOLD_FC_16              ((uint32_t)0x00003000)
+#define SIO_EHOLD_FC_32              ((uint32_t)0x00004000)
+#define SIO_EHOLD_FC_64              ((uint32_t)0x00005000)
+#define SIO_EHOLD_FC_128             ((uint32_t)0x00006000)
+#define IS_SIO_EHOLD_TIME(param)    (((param) == SIO_EHOLD_FC_2) ||   \
+                                     ((param) == SIO_EHOLD_FC_4) || \
+                                     ((param) == SIO_EHOLD_FC_8) || \
+                                     ((param) == SIO_EHOLD_FC_16) || \
+                                     ((param) == SIO_EHOLD_FC_32) || \
+                                     ((param) == SIO_EHOLD_FC_64) || \
+                                     ((param) == SIO_EHOLD_FC_128))
+
+#define SIO_SINT_TIME_NONE           ((uint32_t)0x00000000)
+#define SIO_SINT_TIME_SCLK_1         ((uint32_t)0x00000002)
+#define SIO_SINT_TIME_SCLK_2         ((uint32_t)0x00000004)
+#define SIO_SINT_TIME_SCLK_4         ((uint32_t)0x00000006)
+#define SIO_SINT_TIME_SCLK_8         ((uint32_t)0x00000008)
+#define SIO_SINT_TIME_SCLK_16        ((uint32_t)0x0000000A)
+#define SIO_SINT_TIME_SCLK_32        ((uint32_t)0x0000000C)
+#define SIO_SINT_TIME_SCLK_64        ((uint32_t)0x0000000E)
+#define IS_SIO_SINT_TIME(param)     (((param) == SIO_SINT_TIME_NONE) ||   \
+                                     ((param) == SIO_SINT_TIME_SCLK_1) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_2) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_4) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_8) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_16) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_32) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_64))
+
+#define SIO_TRANSFER_PROHIBIT        ((uint32_t)0x00000000)
+#define SIO_TRANSFER_HALFDPX_RX      ((uint32_t)0x00000020)
+#define SIO_TRANSFER_HALFDPX_TX      ((uint32_t)0x00000040)
+#define SIO_TRANSFER_FULLDPX         ((uint32_t)0x00000060)
+#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \
+                                     ((param) == SIO_TRANSFER_HALFDPX_RX) || \
+                                     ((param) == SIO_TRANSFER_HALFDPX_TX) || \
+                                     ((param) == SIO_TRANSFER_FULLDPX))
+
+#define SIO_ENABLE_RX              ((uint32_t)0x00000020)
+#define SIO_ENABLE_TX              ((uint32_t)0x00000010)
+#define IS_SIO_MODE(param)         (((param) == SIO_ENABLE_RX) || \
+                                     ((param) == SIO_ENABLE_TX) || \
+                                     ((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX)))
+
+#define SIO_LSB_FRIST              ((uint32_t)0x00000000)
+#define SIO_MSB_FRIST              ((uint32_t)0x00000008)
+#define IS_SIO_TRANS_DIR(param)     (((param) == SIO_LSB_FRIST) || \
+                                     ((param) == SIO_MSB_FRIST))
+
+#define SIO_WBUF_DISABLE             ((uint32_t)0x00000000)
+#define SIO_WBUF_ENABLE              ((uint32_t)0x00000004)
+#define IS_SIO_WBUF_SET(param)      (((param) == SIO_WBUF_DISABLE) || \
+                                     ((param) == SIO_WBUF_ENABLE))
+
+#define SIO_BR_CLOCK_TS0             ((uint32_t)0x00000000)
+#define SIO_BR_CLOCK_TS2             ((uint32_t)0x00000010)
+#define SIO_BR_CLOCK_TS8             ((uint32_t)0x00000020)
+#define SIO_BR_CLOCK_TS32            ((uint32_t)0x00000030)
+#define IS_SIO_BR_CLOCK(param)      (((param) == SIO_BR_CLOCK_TS0) || \
+                                     ((param) == SIO_BR_CLOCK_TS2) || \
+                                     ((param) == SIO_BR_CLOCK_TS8) || \
+                                     ((param) == SIO_BR_CLOCK_TS32))
+
+#define SIO_BR_DIVIDER_16            ((uint32_t)0x00000000)
+#define SIO_BR_DIVIDER_1             ((uint32_t)0x00000001)
+#define SIO_BR_DIVIDER_2             ((uint32_t)0x00000002)
+#define SIO_BR_DIVIDER_3             ((uint32_t)0x00000003)
+#define SIO_BR_DIVIDER_4             ((uint32_t)0x00000004)
+#define SIO_BR_DIVIDER_5             ((uint32_t)0x00000005)
+#define SIO_BR_DIVIDER_6             ((uint32_t)0x00000006)
+#define SIO_BR_DIVIDER_7             ((uint32_t)0x00000007)
+#define SIO_BR_DIVIDER_8             ((uint32_t)0x00000008)
+#define SIO_BR_DIVIDER_9             ((uint32_t)0x00000009)
+#define SIO_BR_DIVIDER_10            ((uint32_t)0x0000000A)
+#define SIO_BR_DIVIDER_11            ((uint32_t)0x0000000B)
+#define SIO_BR_DIVIDER_12            ((uint32_t)0x0000000C)
+#define SIO_BR_DIVIDER_13            ((uint32_t)0x0000000D)
+#define SIO_BR_DIVIDER_14            ((uint32_t)0x0000000E)
+#define SIO_BR_DIVIDER_15            ((uint32_t)0x0000000F)
+#define IS_SIO_BR_DIVIDER(param)    ((param) <= SIO_BR_DIVIDER_15)
+
+#define IS_SIO_DATA(param)          ((param) <= 0xFFU)
+
+#define SIO_CLOCK_T0_HALF           ((uint32_t)0x00000000)
+#define SIO_CLOCK_T0                ((uint32_t)0x00000002)
+#define IS_SIO_CLOCK(param)        (((param) == SIO_CLOCK_T0_HALF) || \
+                                    ((param) == SIO_CLOCK_T0))
+
+#define UART_ENABLE_RX              ((uint32_t)0x00000020)
+#define UART_ENABLE_TX              ((uint32_t)0x00000010)
+#define IS_UART_MODE(param)         (((param) == UART_ENABLE_RX) || \
+                                     ((param) == UART_ENABLE_TX) || \
+                                     ((param) == (UART_ENABLE_TX | UART_ENABLE_RX)))
+
+#define UART_NONE_FLOW_CTRL         ((uint32_t)0x00000000)
+#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL)
+
+#define IS_UART_BAUDRATE(param)     (((param) >= 2400U) && \
+                                     ((param) <= 115200U))
+
+#define IS_UART_DATA(param)         ((param) <= 0x01FFU)
+
+#define IS_UART_CLOCK(param)        ((param) <= ((uint32_t)0x00000001))
+#define IS_UART_TIME(param)         ((param) <= ((uint32_t)0x00000006))
+#define UART_RX                     ((uint32_t)0x00000020)
+#define UART_TX                     ((uint32_t)0x00000040)
+#define IS_UART_TRX(param)          (((param) == UART_RX) || \
+                                     ((param) == UART_TX))
+
+#define UART_TRANSFER_PROHIBIT               ((uint32_t)0x00000000)
+#define UART_TRANSFER_HALFDPX_RX             ((uint32_t)0x00000020)
+#define UART_TRANSFER_HALFDPX_TX             ((uint32_t)0x00000040)
+#define UART_TRANSFER_FULLDPX                ((uint32_t)0x00000060)
+#define IS_UART_TRANSFER_MODE(param)        (((param) == UART_TRANSFER_PROHIBIT) || \
+                                             ((param) == UART_TRANSFER_HALFDPX_RX) || \
+                                             ((param) == UART_TRANSFER_HALFDPX_TX) || \
+                                             ((param) == UART_TRANSFER_FULLDPX))
+
+#define UART_RXFIFO_MAX                      ((uint32_t)0x00000000)
+#define UART_RXFIFO_RXFLEVEL                 ((uint32_t)0x00000010)
+#define IS_UATR_RXFIFO_BYTESUSED(param)     (((param) == UART_RXFIFO_MAX) || \
+                                             ((param) == UART_RXFIFO_RXFLEVEL))
+
+#define UART_RXFIFO4B_FLEVLE_4_2B              ((uint32_t)0x00000000)
+#define UART_RXFIFO4B_FLEVLE_1_1B              ((uint32_t)0x00000001)
+#define UART_RXFIFO4B_FLEVLE_2_2B              ((uint32_t)0x00000002)
+#define UART_RXFIFO4B_FLEVLE_3_1B              ((uint32_t)0x00000003)
+#define IS_UART_RXFIFO4B_FLEVLE(param)        (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_3_1B))
+
+#define UART_RFIS_REACH_FLEVEL               ((uint32_t)0x00000000)
+#define UART_RFIS_REACH_EXCEED_FLEVEL        ((uint32_t)0x00000040)
+#define IS_UATR_RFIS_CONDITION(param)       (((param) == UART_RFIS_REACH_FLEVEL) || \
+                                             ((param) == UART_RFIS_REACH_EXCEED_FLEVEL))
+
+#define UART_TXFIFO4B_FLEVLE_0_0B              ((uint32_t)0x00000000)
+#define UART_TXFIFO4B_FLEVLE_1_1B              ((uint32_t)0x00000001)
+#define UART_TXFIFO4B_FLEVLE_2_0B              ((uint32_t)0x00000002)
+#define UART_TXFIFO4B_FLEVLE_3_1B              ((uint32_t)0x00000003)
+#define IS_UART_TXFIFO4B_FLEVLE(param)        (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_3_1B))
+
+#define UART_TRXFIFO_EMPTY         ((uint32_t)0x00000000)
+#define UART_TRXFIFO_1B            ((uint32_t)0x00000001)
+#define UART_TRXFIFO_2B            ((uint32_t)0x00000002)
+#define UART_TRXFIFO_3B            ((uint32_t)0x00000003)
+#define UART_TRXFIFO_4B            ((uint32_t)0x00000004)
+
+#define UART_TFIS_REACH_FLEVEL               ((uint32_t)0x00000000)
+#define UART_TFIS_REACH_NOREACH_FLEVEL       ((uint32_t)0x00000040)
+#define IS_UATR_TFIS_CONDITION(param)       (((param) == UART_TFIS_REACH_FLEVEL) || \
+                                             ((param) == UART_TFIS_REACH_NOREACH_FLEVEL))
+
+#define UART_RXFIFO_OVERRUN                  ((uint32_t)0x00000001)
+
+#define UART_TXFIFO_UNDERRUN                 ((uint32_t)0x00000001)
+
+/** @} */
+/* End of group UART_Exported_Constants */
+
+/** @addtogroup UART_Exported_Types
+  * @{
+  */
+    typedef enum {
+        UART_NO_ERR = 0U,
+        UART_OVERRUN = 1U,
+        UART_PARITY_ERR = 2U,
+        UART_FRAMING_ERR = 3U,
+        UART_ERRS = 4U
+    } UART_Err;
+
+    typedef enum {
+        UART_RXTXCNT_NONE = 0U,
+        UART_RXTXCNT_AUTODISABLE = 1U
+    } UART_TRxDisable;
+#define IS_UATR_TRX_AUTODISABLE(param)  (((param) == UART_RXTXCNT_NONE) || \
+                                         ((param) == UART_RXTXCNT_AUTODISABLE))
+
+/** @} */
+/* End of group UART_Exported_Types */
+
+/** @defgroup UART_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void UART_Enable(TSB_SC_TypeDef * UARTx);
+    void UART_Disable(TSB_SC_TypeDef * UARTx);
+    WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction);
+    void UART_SWReset(TSB_SC_TypeDef * UARTx);
+    void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct);
+    uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx);
+    void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data);
+    void UART_DefaultConfig(TSB_SC_TypeDef * UARTx);
+    UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx);
+    void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock);
+    void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode);
+    void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable);
+    void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed);
+    void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel);
+    void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition);
+    void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx);
+    void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel);
+    void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition);
+    void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx);
+    void UART_TxBufferClear(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx);
+    void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock);
+    void SIO_Enable(TSB_SC_TypeDef * SIOx);
+    void SIO_Disable(TSB_SC_TypeDef * SIOx);
+    uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx);
+    void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data);
+    void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct);
+/** @} */
+/* End of group UART_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group UART */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* defined(__TMPM066_UART_H)  */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM066_UART_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,47 @@
+/**
+ *******************************************************************************
+ * @file    tx00_common.h
+ * @brief   All common macro and definition for TX00 peripheral drivers
+ * @version V2.1.1
+ * @date    2014/11/22
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TX00_COMMON_H
+#define __TX00_COMMON_H
+
+typedef enum {
+    SUCCESS = 0U,
+    ERROR = 1U
+} Result;
+
+typedef enum {
+    BUSY = 0U,
+    DONE = 1U
+} WorkState;
+
+typedef enum {
+    DISABLE = 0U,
+    ENABLE = 1U
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0)
+
+/* 
+ * To report the name of the source file and source line number where the
+ * assert_param error has occurred, "DEBUG" must be defined. And detailed
+ * definition of assert_failed() is needed to be implemented, which can be
+ * done, for example, in the main.c file.
+ */
+#ifdef DEBUG
+void assert_failed(char *file, int32_t line);
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
+#else
+#define assert_param(expr)
+#endif                          /* DEBUG */
+
+#endif                          /* __TX00_COMMON_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,571 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_adc.c
+ * @brief   This file provides API functions for ADC driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_adc.h"
+
+#if defined(__TMPM066_ADC_H)
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+#define MOD0_ADS_SET            ((uint32_t)0x00000001)
+#define MOD0_SCAN_MASK          ((uint32_t)0xFFFFFFFD)
+#define MOD0_REPEAT_MASK        ((uint32_t)0xFFFFFFFB)
+#define MOD0_ITM_CLEAR          ((uint32_t)0xFFFFFFE7)
+#define MOD0_ADBFN_EOCFN_MASK   ((uint32_t)0x000000C0)
+
+#define MOD1_ADCH_CLEAR         ((uint32_t)0xFFFFFFF0)
+#define MOD1_ADSCN_CLEAR        ((uint32_t)0xFFFFFFCF)
+
+#define MOD2_HPADCH_CLEAR       ((uint32_t)0xFFFFFFF0)
+#define MOD2_HPADCE_SET         ((uint32_t)0x00000020)
+#define MOD2_ADBFHP_EOCFHP_MASK ((uint32_t)0x000000C0)
+
+#define MOD4_ADHTG_CLEAR        ((uint32_t)0xFFFFFFEF)
+#define MOD4_ADHTG_SET          ((uint32_t)0x00000010)
+#define MOD4_ADHS_CLEAR         ((uint32_t)0xFFFFFFDF)
+#define MOD4_HADHTG_CLEAR       ((uint32_t)0xFFFFFFBF)
+#define MOD4_HADHTG_SET         ((uint32_t)0x00000040)
+#define MOD4_HADHS_CLEAR        ((uint32_t)0xFFFFFF7F)
+#define MOD4_ADRST_MASK         ((uint32_t)0xFFFFFFFC)
+#define MOD4_ADRST_10           ((uint32_t)0x00000002)
+#define MOD4_ADRST_01           ((uint32_t)0x00000001)
+
+#define ADC_CMPREG_CLEAR        ((uint32_t)0xFFFFFF21)
+#define ADC_REGx_ADRxRF_MASK    ((uint32_t)0x00000001)
+#define ADC_REGx_OVRx_MASK      ((uint32_t)0x00000002)
+#define ADC_REGx_RESULT_MASK    ((uint32_t)0x0000FFC0)
+
+/** @} */
+/* End of group ADC_Private_Defines */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group ADC_Private_FunctionPrototypes */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group ADC_Private_Functions */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Software reset ADC function.
+  * @param  None.
+  * @retval None.
+  */
+void ADC_SWReset(void)
+{
+    /* Set MOD4<ADRST[1:0]> = 0b10, 0b01 to reset ADC */
+    TSB_AD->MOD4 = MOD4_ADRST_10;
+    TSB_AD->MOD4 = MOD4_ADRST_01;
+}
+
+/**
+  * @brief  Set A/D conversion time and prescaler output.
+  * @param  Conversion_Time: Select the A/D conversion time.
+  *   This parameter can be one of the following values:
+  *   ADC_CONVERSION_35_CLOCK, ADC_CONVERSION_42_CLOCK,
+  *   ADC_CONVERSION_68_CLOCK, ADC_CONVERSION_81_CLOCK
+  * @param  Prescaler_Output: Select the A/D prescaler output.
+  *   This parameter can be one of the following values:
+  *   ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2, ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_6,
+  *   ADC_FC_DIVIDE_LEVEL_8, ADC_FC_DIVIDE_LEVEL_12, ADC_FC_DIVIDE_LEVEL_16,
+  *   ADC_FC_DIVIDE_LEVEL_24, ADC_FC_DIVIDE_LEVEL_48, ADC_FC_DIVIDE_LEVEL_96.
+  * @retval None.
+  */
+void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_CONVERSION_TIME(Conversion_Time));
+    assert_param(IS_ADC_PRESCALER(Prescaler_Output));
+    /* Set ADCLK */
+    TSB_AD->CLK = Conversion_Time + Prescaler_Output;
+}
+
+/**
+  * @brief  Start ADC function.
+  * @param  None.
+  * @retval None.
+  */
+void ADC_Start(void)
+{
+    /* Set ADMOD0<ADS> = 1 to start ADC */
+    TSB_AD->MOD0 |= MOD0_ADS_SET;
+}
+
+/**
+  * @brief  Set ADC scan mode.
+  * @param  NewState: Specify ADC scan mode.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetScanMode(FunctionalState NewState)
+{
+    /* read MOD0, and clear bit1 which is "ADMOD0<SCAN>" */
+    uint32_t tmp = TSB_AD->MOD0 & MOD0_SCAN_MASK;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    /* Set ADMOD0<SCAN> */
+    tmp |= (uint32_t) NewState << 1U;
+    TSB_AD->MOD0 = tmp;
+}
+
+/**
+  * @brief  Set ADC repeat mode.
+  * @param  NewState: Specify ADC repeat mode.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetRepeatMode(FunctionalState NewState)
+{
+    /* read MOD0, and clear bit2 which is "ADMOD0<REPEAT>" */
+    uint32_t tmp = TSB_AD->MOD0 & MOD0_REPEAT_MASK;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD0<REPEAT> */
+    tmp |= (uint32_t) NewState << 2U;
+    TSB_AD->MOD0 = tmp;
+}
+
+/**
+  * @brief  Set ADC interrupt mode in fixed channel repeat conversion mode.
+  * @param  INTMode: Specify AD conversion interrupt mode.
+  *   This parameter can be one of the following values:
+  *   ADC_INT_SINGLE, ADC_INT_CONVERSION_4 or ADC_INT_CONVERSION_8.
+  * @retval None.
+  */
+void ADC_SetINTMode(uint32_t INTMode)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_INT_MODE(INTMode));
+    /* Set ADMOD0<ITM[1:0]> */
+    tmp = TSB_AD->MOD0;
+    tmp &= MOD0_ITM_CLEAR;
+    tmp |= INTMode;
+    TSB_AD->MOD0 = tmp;
+}
+
+/**
+  * @brief  Read AD conversion completion/busy flag (normal and top-priority).
+  * @param  None
+  * @retval A union with the state of AD conversion.
+  */
+ADC_State ADC_GetConvertState(void)
+{
+    uint32_t tmpmod0 = TSB_AD->MOD0;
+    uint32_t tmpmod2 = TSB_AD->MOD2;
+    ADC_State retval = { 0U };
+
+    tmpmod0 &= MOD0_ADBFN_EOCFN_MASK;
+    tmpmod2 &= MOD2_ADBFHP_EOCFHP_MASK;
+    retval.All = (tmpmod0 >> 6U) | (tmpmod2 >> 4U);
+    return retval;
+}
+
+/**
+  * @brief  Set ADC input channel.
+  * @param  InputChannel: Analog input channel, it also related with other settings.
+  *   This parameter can be one of the following values:
+  *   ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3,
+  *   ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7.  
+  * @retval None.
+  */
+void ADC_SetInputChannel(uint32_t InputChannel)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_INPUT_CH(InputChannel));
+    /* Set ADMOD1<ADCH[3:0]> */
+    tmp = TSB_AD->MOD1;
+    tmp &= MOD1_ADCH_CLEAR;
+    tmp |= InputChannel;
+    TSB_AD->MOD1 = tmp;
+}
+
+/**
+  * @brief  Set ADC operation for scanning.
+  * @param  ScanMode: Spcifiy operation mode for channel scanning.
+  *   This parameter can be one of the following values:
+  *   ADC_SCAN_4CH, ADC_SCAN_8CH.
+  * @retval None.
+  */
+void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_CH_SCAN_MODE(ScanMode));
+    tmp = TSB_AD->MOD1;
+    tmp &= MOD1_ADSCN_CLEAR;
+    tmp |= ((uint32_t) ScanMode << 4U);
+    TSB_AD->MOD1 = tmp;
+}
+
+/**
+  * @brief  Set ADC in IDLE mode.
+  * @param  NewState: Specify AD conversion in IDLE mode.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetIdleMode(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    /* Set ADMOD1<I2AD> */
+    TSB_AD_MOD1_I2AD = NewState;
+}
+
+/**
+  * @brief  Set ADC VREF application.
+  * @param  NewState: Specify ADC Vref application.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetVref(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    /* Set ADMOD1<VREFON> */
+    TSB_AD_MOD1_VREFON = NewState;
+}
+
+/**
+  * @brief  Set ADC top-priority conversion analog input channel select.
+  * @param  TopInputChannel: Analog input channel for top-priority conversion.
+  *   This parameter can be one of the following values:
+  *   ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3,
+  *   ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7.
+  * @retval None.
+  */
+void ADC_SetInputChannelTop(uint32_t TopInputChannel)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_INPUT_CH(TopInputChannel));
+    /* Set ADMOD2<HPADCH[3:0]> */
+    tmp = TSB_AD->MOD2;
+    tmp &= MOD2_HPADCH_CLEAR;
+    tmp |= TopInputChannel;
+    TSB_AD->MOD2 = tmp;
+}
+
+/**
+  * @brief  Start top-priority ADC.
+  * @param  None.
+  * @retval None.
+  */
+void ADC_StartTopConvert(void)
+{
+    /* Set ADMOD2<HPADCE> = 1 to start top-priority ADC */
+    TSB_AD->MOD2 |= MOD2_HPADCE_SET;
+}
+
+/**
+  * @brief  Set ADC monitor function.
+  * @param  ADCMPx: Select ADC compare register.
+  *   This parameter can be one of the following values:
+  *   ADC_CMP_0 or ADC_CMP_1.
+  * @param  NewState: Specify ADC monitor function.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_CMP(ADCMPx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (ADCMPx == ADC_CMP_0) {
+        /* Set ADMOD3<ADOBSV0> */
+        TSB_AD_MOD3_ADOBSV0 = NewState;
+    } else {
+        /* Set ADMOD5<ADOBSV1> */
+        TSB_AD_MOD5_ADOBSV1 = NewState;
+    }
+}
+
+/**
+  * @brief  Set ADC result output register or comparison register.
+  * @param  ADCMPx: Select AD compare register.
+  *   This parameter can be one of the following values:
+  *   ADC_CMP_0 or ADC_CMP_1.
+  * @param  ResultComparison: Set AD conversion result storage register or
+  *   comparison register if ADC monitor function is enabled.
+  *   This parameter can be one of the following values:
+  *   ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3,
+  *   ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP.
+  * @retval None.
+  */
+void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_CMP(ADCMPx));
+    assert_param(IS_ADC_RESULT_CMP_REG(ResultComparison));
+    if (ADC_CMP_0 == ADCMPx) {
+        /* Set ADMOD3<REGS0[3:0]> */
+        tmp = TSB_AD->MOD3;
+        tmp &= ADC_CMPREG_CLEAR;
+        tmp |= ResultComparison;
+        TSB_AD->MOD3 = tmp;
+    } else {
+        /* Set ADMOD5<REGS1[3:0]> */
+        tmp = TSB_AD->MOD5;
+        tmp &= ADC_CMPREG_CLEAR;
+        tmp |= ResultComparison;
+        TSB_AD->MOD5 = tmp;
+    }
+}
+
+/**
+  * @brief  Set ADC monitor interrupt.
+  * @param  ADCMPx: Select ADC compare register.
+  *   This parameter can be one of the following values:
+  *   ADC_CMP_0 or ADC_CMP_1.
+  * @param   NewState: Specify ADC monitor function.
+  *   This parameter can be one of the following values:
+  *   ADC_COMPARISON_SMALLER or ADC_COMPARISON_LARGER.
+  * @retval None.
+  */
+void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_CMP(ADCMPx));
+    assert_param(IS_ADC_CMP_INT(NewState));
+    if (ADCMPx == ADC_CMP_0) {
+        /* Set ADMOD3<ADOBIC0> */
+        TSB_AD_MOD3_ADOBIC0 = NewState;
+    } else {
+        /* Set ADMOD5<ADOBIC1> */
+        TSB_AD_MOD5_ADOBIC1 = NewState;
+    }
+}
+
+/**
+  * @brief  Set hardware trigger for normal ADC function.
+  * @param  HwSource: HW source for activating normal ADC.
+  *   This parameter can be one of the following values:
+  *   ADC_EXT_TRG or ADC_MATCH_TB_0.
+  * @param   NewState: Specify HW for activating normal ADC.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_HW_TRG_NORMAL(HwSource));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    /* Set ADMOD4<ADHS> */
+    tmp = TSB_AD->MOD4;
+    tmp &= MOD4_ADHS_CLEAR;
+    tmp |= HwSource;
+    /* Set ADMOD4<ADHTG> */
+    if (NewState == ENABLE) {
+        tmp |= MOD4_ADHTG_SET;
+    } else {
+        tmp &= MOD4_ADHTG_CLEAR;
+    }
+    TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK;
+}
+
+/**
+  * @brief  Set hardware trigger for top-priority ADC function.
+  * @param  HwSource: HW source for activating top-priority ADC.
+  *   This parameter can be one of the following values:
+  *   ADC_EXT_TRG or ADC_MATCH_TB_1.
+  * @param   NewState: Specify HW for activating top-priority ADC.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_HW_TRG_TOP(HwSource));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    /* Set ADMOD4<HADHS> */
+    tmp = TSB_AD->MOD4;
+    tmp &= MOD4_HADHS_CLEAR;
+    tmp |= HwSource;
+    /* Set ADMOD4<HADHTG> */
+    if (NewState == ENABLE) {
+        tmp |= MOD4_HADHTG_SET;
+    } else {
+        tmp &= MOD4_HADHTG_CLEAR;
+    }
+    TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK;
+}
+
+/**
+  * @brief  Read ADC result.
+  * @param  ADREGx: ADC result register.
+  *   This parameter can be one of the following values:
+  *   ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3,
+  *   ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP.
+  * @retval ADC result.
+  */
+ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx)
+{
+    uint32_t tmp = 0U;
+    ADC_ResultTypeDef retval = { BUSY, ADC_NO_OVERRUN, 0U };
+
+    /* Check the parameters */
+    assert_param(IS_ADC_REG(ADREGx));
+    /* Read ADREGx<ADRx[9:0]> to get ADC result */
+    switch (ADREGx) {
+    case ADC_REG_0:
+        tmp = TSB_AD->REG0;
+        break;
+    case ADC_REG_1:
+        tmp = TSB_AD->REG1;
+        break;
+    case ADC_REG_2:
+        tmp = TSB_AD->REG2;
+        break;
+    case ADC_REG_3:
+        tmp = TSB_AD->REG3;
+        break;
+    case ADC_REG_4:
+        tmp = TSB_AD->REG4;
+        break;
+    case ADC_REG_5:
+        tmp = TSB_AD->REG5;
+        break;
+    case ADC_REG_6:
+        tmp = TSB_AD->REG6;
+        break;
+    case ADC_REG_7:
+        tmp = TSB_AD->REG7;
+        break;
+    case ADC_REG_SP:
+        tmp = TSB_AD->REGSP;
+        break;
+    default:                   /* Do nothing */
+        break;
+    }
+
+    if ((tmp & ADC_REGx_ADRxRF_MASK) == 0U) {
+        retval.ADCResultStored = BUSY;
+    } else {
+        retval.ADCResultStored = DONE;
+    }
+
+    if ((tmp & ADC_REGx_OVRx_MASK) == 0U) {
+        retval.ADCOverrunState = ADC_NO_OVERRUN;
+    } else {
+        retval.ADCOverrunState = ADC_OVERRUN;
+    }
+
+    retval.ADCResultValue = (uint16_t) tmp & ADC_REGx_RESULT_MASK;
+    retval.ADCResultValue >>= 6U;
+
+    return retval;
+}
+
+/**
+  * @brief  Set ADC comparison register value.
+  * @param  ADCMPx: Select AD compare register.
+  *   This parameter can be one of the following values:
+  *   ADC_CMP_0 or ADC_CMP_1.
+  * @param  value: The value setting to ADC comparison register.
+  * @retval None.
+  */
+void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value)
+{
+
+    /* Check the parameters */
+    assert_param(IS_ADC_CMP(ADCMPx));
+    assert_param(IS_ADC_CMP_VALUE(value));
+    value <<= 6U;
+    if (ADCMPx == ADC_CMP_0) {
+        /* Set ADCMP0<ADCOM0[9:0]> */
+        TSB_AD->CMP0 = value;
+    } else {
+        /* Set ADCMP1<ADCOM1[9:0]> */
+        TSB_AD->CMP1 = value;
+    }
+}
+
+/**
+  * @breif  Enable or disable DMA activation factor for normal or top-priority AD conversion.
+  * @param  DMAReq: Specify AD conversion DMA request type.
+  *   This parameter can be one of the following values:
+  *   ADC_DMA_REQ_NORMAL, ADC_DMA_REQ_TOP,
+  *   ADC_DMA_REQ_MONITOR1, ADC_DMA_REQ_MONITOR2.
+  * @param  NewState: Specify AD conversion DMA activation factor.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_DMA_REQ(DMAReq));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    switch (DMAReq) {
+    case ADC_DMA_REQ_NORMAL:
+        TSB_AD_MOD6_ADDMA = NewState;
+        break;
+    case ADC_DMA_REQ_TOP:
+        TSB_AD_MOD6_ADHPDMA = NewState;
+        break;
+    case ADC_DMA_REQ_MONITOR1:
+        TSB_AD_MOD6_ADM0DMA = NewState;
+        break;
+    case ADC_DMA_REQ_MONITOR2:
+        TSB_AD_MOD6_ADM1DMA = NewState;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/** @} */
+/* End of group ADC_Exported_Functions */
+
+/** @} */
+/* End of group ADC */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_ADC_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,698 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_cg.c
+ * @brief   This file provides API functions for CG driver 
+ * @version V2.0.2.1    
+ * @date    2015/09/22
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_cg.h"
+
+#if defined(__TMPM066_CG_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup CG
+  * @brief CG driver modules
+  * @{
+  */
+
+/** @defgroup CG_Private_Defines
+  * @{
+  */
+
+#define CG_FC_GEAR_MASK                      ((uint32_t)0xFFFFFFF8)
+#define CG_PRCK_MASK                         ((uint32_t)0xFFFFF0FF)
+#define CG_WUP_TIME_MASK                     ((uint32_t)0x000FFFFF)
+#define CG_WUP_COUNTER_MASK                  ((uint32_t)0xFFFFFEFF)
+#define CG_WUP_START_SET                     ((uint32_t)0x00000001)
+#define CG_WUEF_VALUE_MASK                   ((uint32_t)0x00000002)
+#define CG_OSCCR_IOSCEN_SET                  ((uint32_t)0x00000001)
+#define CG_OSCCR_IOSCEN_CLEAR                ((uint32_t)0xFFFFFFFE)
+#define CG_OSCCR_EOSCEN_EHOSC                ((uint32_t)0x00000002)
+#define CG_OSCCR_EOSCEN_NOUSE                ((uint32_t)0xFFFFFFF9)
+#define CG_OSCCR_EOSCEN_MASK                 ((uint32_t)0x00000006)
+#define CG_OSCCR_EOSCEN_CLKIN                ((uint32_t)0x00000004)
+#define CG_OSCCR_OSCSEL_SET                  ((uint32_t)0x00000100)
+#define CG_OSCCR_OSCSEL_CLEAR                ((uint32_t)0xFFFFFEFF)
+#define CG_OSCCR_OSCF_SET                    ((uint32_t)0x00000200)
+#define CG_OSCCR_WUPT_MASK                   ((uint32_t)0x00FFFFFF)
+
+#define CG_PLL0SEL_PLL0ON_SET                ((uint32_t)0x00000001)
+#define CG_PLL0SEL_PLL0ON_CLEAR              ((uint32_t)0xFFFFFFFE)
+#define CG_PLL0SEL_PLL0SEL_SET               ((uint32_t)0x00000002)
+#define CG_PLL0SEL_PLL0SEL_CLEAR             ((uint32_t)0xFFFFFFFD)
+#define CG_PLL0SEL_PLLST_SET                 ((uint32_t)0x00000004)
+
+#define CG_PLL0SET_VALUE_MASK                 ((uint32_t)0xFFFFFF00)
+#define CG_PLL0SEL_PLL0SET_MASK               ((uint32_t)0xFFFFFF00)
+
+#define CG_STBY_MODE_MASK                    ((uint32_t)0xFFFFFFFC)
+//#define CG_NMIFLG_MASK                       ((uint32_t)0xFFF8FFFF)
+
+#define FC_GEAR_1_1                          ((uint32_t)0x00000000)
+#define FC_GEAR_1_2                          ((uint32_t)0x00000001)
+#define FC_GEAR_1_4                          ((uint32_t)0x00000002)
+#define FC_GEAR_1_8                          ((uint32_t)0x00000003)
+#define FC_GEAR_1_16                         ((uint32_t)0x00000004)
+
+#define WARM_UP_SEL_OSC_INT_HIGH             ((uint32_t)0xFFFFFEFF)
+#define WARM_UP_SEL_OSC_EXT_HIGH             ((uint32_t)0x00000100)
+
+#define CG_PROTECT_SET                       ((uint32_t)0x000000C1)
+#define CG_PROTECT_CLEAR                     ((uint32_t)0x0000003E)
+
+//#define INT_NCLR_PCLR_CLEAR                  ((uint8_t)0x01)
+#define ADC_MOD0_BUSY_MASK                   ((uint32_t)0x00000040)
+#define CG_SPCLKEN_ADCKEN_CLEAR                ((uint32_t)0xFFFEFFFF)
+#define CG_SPCLKEN_ADCKEN_SET                  ((uint32_t)0x00010000)
+
+
+static CG_DivideLevel numToDivideLevel_table[CG_DIVIDE_MAX] = {
+    CG_DIVIDE_1,
+    CG_DIVIDE_2,
+    CG_DIVIDE_4,
+    CG_DIVIDE_8,
+    CG_DIVIDE_16,
+    CG_DIVIDE_32,
+    CG_DIVIDE_64,
+    CG_DIVIDE_128,
+    CG_DIVIDE_256,
+    CG_DIVIDE_512,
+    CG_DIVIDE_UNKNOWN,
+};
+
+static CG_STBYMode numToSTBYMode_table[CG_STBY_MODE_MAX] = {
+    CG_STBY_MODE_IDLE,
+    CG_STBY_MODE_STOP1,
+    CG_STBY_MODE_UNKNOWN,
+    CG_STBY_MODE_UNKNOWN,
+};
+
+/** @} */
+/* End of group CG_Private_Defines */
+
+/** @defgroup CG_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group CG_Private_FunctionPrototypes */
+
+/** @defgroup CG_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group CG_Private_Functions */
+
+/** @defgroup CG_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set dividing level between clock fgear and fc.
+  * @param  DivideFgearFromFc: Dividing level between fgear and fc.
+  *   This parameter can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, CG_DIVIDE_16
+  * @retval None
+  */
+void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc)
+{
+    uint32_t gear = FC_GEAR_1_1;
+    uint32_t regval = TSB_CG->SYSCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_GEAR_DIVIDE_LEVEL(DivideFgearFromFc));
+
+    /* Set the value of fgear */
+    switch (DivideFgearFromFc) {
+    case CG_DIVIDE_1:
+        gear = FC_GEAR_1_1;
+        break;
+    case CG_DIVIDE_2:
+        gear = FC_GEAR_1_2;
+        break;
+    case CG_DIVIDE_4:
+        gear = FC_GEAR_1_4;
+        break;
+    case CG_DIVIDE_8:
+        gear = FC_GEAR_1_8;
+        break;
+    case CG_DIVIDE_16:
+        gear = FC_GEAR_1_16;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    regval &= CG_FC_GEAR_MASK;
+    regval |= gear;
+    TSB_CG->SYSCR = regval;
+}
+
+/**
+  * @brief  Get dividing level between clock fgear and fc.
+  * @param  None
+  * @retval The dividing level between clock fgear and fc
+  *   The value returned can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4,
+  *   CG_DIVIDE_8, CG_DIVIDE_16 or CG_DIVIDE_UNKNOWN
+  */
+CG_DivideLevel CG_GetFgearLevel(void)
+{
+    CG_DivideLevel DivideFgearFromFc = CG_DIVIDE_UNKNOWN;
+    uint32_t syscr = TSB_CG->SYSCR;
+    syscr &= (~CG_FC_GEAR_MASK);
+
+    switch (syscr) {
+    case FC_GEAR_1_1:
+        DivideFgearFromFc = CG_DIVIDE_1;
+        break;
+    case FC_GEAR_1_2:
+        DivideFgearFromFc = CG_DIVIDE_2;
+        break;
+    case FC_GEAR_1_4:
+        DivideFgearFromFc = CG_DIVIDE_4;
+        break;
+    case FC_GEAR_1_8:
+        DivideFgearFromFc = CG_DIVIDE_8;
+        break;
+    case FC_GEAR_1_16:
+        DivideFgearFromFc = CG_DIVIDE_16;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    return DivideFgearFromFc;
+}
+
+/**
+  * @brief  Set dividing level between clock PhiT0 and fc.
+  * @param  DividePhiT0FromFc: Dividing level between PhiT0 and fc.
+  *   This parameter can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
+  *   CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
+  *   CG_DIVIDE_256 or CG_DIVIDE_512
+  * @retval  Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc)
+{
+    uint32_t fprclk = 0U;
+    Result retval = ERROR;
+    uint32_t regval = TSB_CG->SYSCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_DIVIDE_FC_LEVEL(DividePhiT0FromFc));
+  
+    fprclk = (uint32_t) DividePhiT0FromFc;
+    regval &= CG_PRCK_MASK;
+    fprclk <<= 8U;
+    regval |= fprclk;
+    TSB_CG->SYSCR = regval;
+    retval = SUCCESS;
+    
+    return retval;
+}
+
+/**
+  * @brief  Get dividing level between clock phiT0 and fc.
+  * @param  None
+  * @retval The divide level between clock phiT0 and fc
+  *   The value returned can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
+  *   CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
+  *   CG_DIVIDE_256, CG_DIVIDE_512 or CG_DIVIDE_UNKNOWN
+  */
+CG_DivideLevel CG_GetPhiT0Level(void)
+{
+    uint32_t fprclk = 0U;
+    CG_DivideLevel phiT0Level = CG_DIVIDE_UNKNOWN;
+
+    fprclk = TSB_CG->SYSCR & (~CG_PRCK_MASK);
+    fprclk = (uint32_t) (fprclk >> 8U);
+
+    phiT0Level = numToDivideLevel_table[fprclk];
+    
+    return phiT0Level;
+}
+
+/**
+  * @brief  Set the warm up time 
+  * @param  Source: Select source of warm-up counter
+  *   This parameter can be one of the following values:
+  *   CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WARM_UP_SRC_OSC_EXT_HIGH.
+  *   Warm-up function is not necessary when using stable external clock.
+  * @param  Time: Set number of warm-up cycle. It is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time)
+{
+    uint32_t wupt = 0U;
+    uint32_t regval = TSB_CG->WUPHCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_WARM_UP_SRC(Source));
+
+    /* Get high 12 bits of warm-up time */
+    wupt = (((uint32_t) Time) & CG_OSCCR_WUPT_MASK) << 20U;
+
+    regval &= CG_WUP_TIME_MASK;
+    regval &= CG_WUP_COUNTER_MASK;
+
+    switch (Source) {
+    case CG_WARM_UP_SRC_OSC_INT_HIGH:
+        regval |= wupt;
+        regval &= WARM_UP_SEL_OSC_INT_HIGH;
+        break;
+    case CG_WARM_UP_SRC_OSC_EXT_HIGH:
+        regval |= wupt;
+        regval |= WARM_UP_SEL_OSC_EXT_HIGH;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    TSB_CG->WUPHCR = regval;
+}
+
+/**
+  * @brief  Start operation of warm up timer for oscillator.
+  * @param  None
+  * @retval None
+  */
+void CG_StartWarmUp(void)
+{
+    uint32_t regval = TSB_CG->WUPHCR;
+    regval |= CG_WUP_START_SET;
+    TSB_CG->WUPHCR = regval;
+}
+
+/**
+  * @brief Check whether warm up is completed or not.
+  * @param  None
+  * @retval The state of warm-up
+  *   The value returned can be one of the following values:
+  *   DONE or BUSY
+  */
+WorkState CG_GetWarmUpState(void)
+{
+    WorkState state = BUSY;
+    uint32_t wuef = 0U;
+    uint32_t regval = TSB_CG->WUPHCR;
+
+    wuef = regval & CG_WUEF_VALUE_MASK;
+    if (wuef == 0U) {
+        state = DONE;
+    } else {
+        /* Do nothing */
+    }
+
+    return state;
+}
+
+/**
+  * @brief  Set PLL multiplying value
+  * @param  NewValue: PLL multiplying value
+  *   This parameter can be one of the following values:
+  *   CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL,
+  *   CG_16M_MUL_6_FPLL.
+  * @retval Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetFPLLValue(uint32_t NewValue)
+{
+    Result retval = SUCCESS;
+
+    /* read PLL0SEL and clear PLL0SET(bit14:0) */
+    uint32_t tmp = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0SET_MASK;
+
+    /* Check the parameters */
+    assert_param(IS_CG_FPLL_VALUE(NewValue));
+
+    /* Don't use the PLL when internal high-speed oscillator (IHOSC) is used as system clock */
+    /* When PLL is on, don't change the PLL setting value */
+    if (CG_FOSC_OSC_INT == CG_GetFoscSrc()) {
+        retval = ERROR;
+    } else if (ENABLE == CG_GetPLLState()) {
+        retval = ERROR;
+    } else {
+        tmp |= NewValue;
+        TSB_CG->PLL0SEL = tmp;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the value of PLL setting
+  * @param  None
+  * @retval Get the value of PLL setting.  
+  *   CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL,
+  *   CG_16M_MUL_6_FPLL.
+  */
+uint32_t CG_GetFPLLValue(void)
+{
+    uint32_t PLL0SEL = TSB_CG->PLL0SEL & CG_PLL0SET_VALUE_MASK;
+
+    return PLL0SEL;
+}
+
+/**
+  * @brief  Enable PLL or disable it.
+  * @param  NewState: New state of PLL
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetPLL(FunctionalState NewState)
+{
+    Result retval = ERROR;
+    uint32_t regval = TSB_CG->PLL0SEL;
+    CG_FcSrc fcsrc = CG_FC_SRC_FPLL;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        regval |= CG_PLL0SEL_PLL0ON_SET;
+        retval = SUCCESS;
+    } else {
+        fcsrc = CG_GetFcSrc();
+        if (fcsrc == CG_FC_SRC_FOSC) {  /* PLL is not used. So it can be shut off */
+            /* Set register to disable PLL */
+            regval &= CG_PLL0SEL_PLL0ON_CLEAR;
+            retval = SUCCESS;
+        } else {                /*fcsrc == CG_FC_SRC_FPLL. PLL is in use, so disabling it should be invalid */
+            /* Do nothing */
+        }
+    }
+    TSB_CG->PLL0SEL = regval;
+    return retval;
+}
+
+/**
+  * @brief  Get the status of PLL operation
+  * @param  None
+  * @retval Run or stop
+  *   The value returned can be one of the following values:
+  *   ENABLE or DISABLE
+  */
+FunctionalState CG_GetPLLState(void)
+{
+    FunctionalState pllstate = DISABLE;
+    uint32_t regval = TSB_CG->PLL0SEL;
+
+    regval &= CG_PLL0SEL_PLL0ON_SET;
+    if (regval == CG_PLL0SEL_PLL0ON_SET) {
+        pllstate = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+
+    return pllstate;
+}
+
+
+/**
+  * @brief  Set the source of high-speed oscillator (fosc)
+  * @param  Source: Select clock source for fosc
+  *   This parameter can be one of the following values:
+  *   CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
+  * @retval None
+  */
+void CG_SetFoscSrc(CG_FoscSrc Source)
+{
+    /* Check the parameters */
+    assert_param(IS_CG_FOSC_SRC(Source));
+
+    if (Source == CG_FOSC_OSC_INT) {
+        /*Selects internal high-speed oscillator */
+        TSB_CG->OSCCR |= CG_OSCCR_IOSCEN_SET;
+        TSB_CG->OSCCR &= CG_OSCCR_OSCSEL_CLEAR;        
+    } else {
+        /*Selects external high-speed oscillator */
+        TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+        TSB_CG->OSCCR &= CG_OSCCR_IOSCEN_CLEAR | CG_OSCCR_EOSCEN_NOUSE;
+        if (Source == CG_FOSC_OSC_EXT) {
+            /*Selects external high-speed oscillator */
+            TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_EHOSC;
+        } else {
+            /*Selects an external clock input */
+            TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_CLKIN;
+        }
+    }
+}
+
+/**
+  * @brief  Get the source of high-speed oscillator (fosc)
+  * @param  None
+  * @retval Source of fosc
+  *   The value returned can be one of the following values:
+  *   CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
+  */
+CG_FoscSrc CG_GetFoscSrc(void)
+{
+    uint32_t regval = TSB_CG->OSCCR;
+    uint32_t oscf = 0U;
+    uint32_t hoscon = 0U;
+    CG_FoscSrc fosc_src = CG_FOSC_CLKIN_EXT;
+
+    oscf = regval & CG_OSCCR_OSCF_SET;
+    hoscon = regval & CG_OSCCR_EOSCEN_MASK;
+    if (oscf == 0U) {
+        fosc_src = CG_FOSC_OSC_INT;
+    } else {
+        if (hoscon == CG_OSCCR_EOSCEN_EHOSC) {
+            fosc_src = CG_FOSC_OSC_EXT;
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    return fosc_src;
+}
+
+/**
+  * @brief  Set to the specified low-power mode
+  * @param  Low power mode
+  *   The value can be one of the following values:
+  *   CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE.
+  * @retval None
+  */
+void CG_SetSTBYMode(CG_STBYMode Mode)
+{
+    uint32_t regval = TSB_CG->STBYCR;
+
+    /* Check the parameter */
+    assert_param(IS_CG_STBY_MODE(Mode));
+
+    regval &= CG_STBY_MODE_MASK;
+    regval |= (uint32_t) Mode;
+
+    TSB_CG->STBYCR = regval;
+}
+
+/**
+  * @brief  Get the low-power consumption mode
+  * @param  None
+  * @retval Low power mode
+  *   The value returned can be one of the following values:
+  *   CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE, CG_STBY_MODE_UNKNOWN. 
+  */
+CG_STBYMode CG_GetSTBYMode(void)
+{
+    CG_STBYMode stby_mode = CG_STBY_MODE_UNKNOWN;
+    uint8_t regval = (uint8_t) (TSB_CG->STBYCR & (~CG_STBY_MODE_MASK));
+
+    stby_mode = numToSTBYMode_table[regval];
+
+    return stby_mode;
+}
+
+/**
+  * @brief  Set the source of fc
+  * @param  Source:  The source of fc
+  *   This parameter can be one of the following values:
+  *   CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
+  * @retval None
+  */
+void CG_SetFcSrc(CG_FcSrc Source)
+{
+    uint32_t regval = TSB_CG->PLL0SEL;
+
+    /* Check the parameters */
+    assert_param(IS_CG_FC_SRC(Source));
+
+    if (Source == CG_FC_SRC_FOSC) {
+       regval &= CG_PLL0SEL_PLL0SEL_CLEAR;
+    } else {
+       regval |= CG_PLL0SEL_PLL0SEL_SET;
+    }
+    TSB_CG->PLL0SEL = regval;
+}
+
+/**
+  * @brief  Get the source of fc
+  * @param  None
+  * @retval The source of fc
+  *   The value returned can be one of the following values:
+  *   CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
+  */
+CG_FcSrc CG_GetFcSrc(void)
+{
+    uint32_t regval = TSB_CG->PLL0SEL;
+    CG_FcSrc fcsrc = CG_FC_SRC_FOSC;
+
+    regval &= CG_PLL0SEL_PLLST_SET;
+    if (regval == CG_PLL0SEL_PLLST_SET) {
+        fcsrc = CG_FC_SRC_FPLL;
+    } else {
+        /* Do nothing */
+    }
+
+    return fcsrc;
+}
+
+/**
+  * @brief  Enable or disable to protect CG registers
+  * @param  NewState: New state of the CG protect register
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void CG_SetProtectCtrl(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        TSB_CG->PROTECT = CG_PROTECT_SET;
+    } else {
+        TSB_CG->PROTECT = CG_PROTECT_CLEAR;
+    }
+}
+
+/**
+   * @brief  Enable or disable supplying clock fsys to peripheries
+   * @param  Periph: The target peripheral of CG supplies clock
+   *   This parameter can be one of the following values or their combination:
+   *   CG_FC_PERIPH_PORTH,  CG_FC_PERIPH_PORTJ,  CG_FC_PERIPH_TMRB0_3,          
+   *   CG_FC_PERIPH_TMRB4_6,  CG_FC_PERIPH_TMR16A,  CG_FC_PERIPH_I2C0,         
+   *   CG_FC_PERIPH_SIO0,  CG_FC_PERIPH_TSPI,  CG_FC_PERIPH_DMAC,          
+   *   CG_FC_PERIPH_ADC,  CG_FC_PERIPH_USBD,  CG_FC_PERIPH_TMRD,
+   *   CG_FC_PERIPHA_ALL.      
+   * @param  NewState: New state of clock supply setting.
+   *   This parameter can be one of the following values:
+   *   DISABLE or ENABLE
+   * @retval None
+   */
+void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState)
+{
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FC_PERIPHA(Periph));
+    if (NewState == ENABLE) {   /* write '1' to enable */
+        TSB_CG->FSYSENA |= Periph;
+    } else {                    /* clear to '0' to disable */
+        TSB_CG->FSYSENA &= ~Periph;
+    }
+}
+
+ /**
+   * @brief  Enable or disable supplying clock fsys to peripheries
+   * @param  Periph: The target peripheral of CG supplies clock
+   *   This parameter can be one of the following values or their combination:   
+   *   CG_FC_PERIPH_TMRB7, CG_FC_PERIPH_SIO1, CG_FC_PERIPH_WDT,      
+   *   CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL.                  
+   * @param  NewState: New state of clock supply setting.
+   *   This parameter can be one of the following values:
+   *   DISABLE or ENABLE
+   * @retval None
+   */
+void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState)
+{
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FC_PERIPHB(Periph));
+    if (NewState == ENABLE) {   /* write '1' to enable */
+        TSB_CG->FSYSENB |= Periph;
+    } else {                    /* clear to '0' to disable */
+        TSB_CG->FSYSENB &= ~Periph;
+    }
+}
+
+ /**
+   * @brief  Enable or disable supplying clock fsys to peripheries
+   * @param  Periph: The target peripheral of CG supplies clock
+   *   This parameter can be one of the following values or their combination:   
+   *   CG_FPLL_PERIPH_TMRD, CG_EHCLKSEL_8_24_48MHZ, CG_USBSEL_PLL_CLOCKIN,
+   *   CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL.  
+   * @param  NewState: New state of clock supply setting.
+   *   This parameter can be one of the following values:
+   *   DISABLE or ENABLE
+   * @retval None
+   */
+void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState)
+{
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FPLL_OPTIONAL(Periph));
+    if (NewState == ENABLE) {   /* write '1' to enable */
+        TSB_CG->EXTENDO0 |= Periph;
+    } else {                    /* clear to '0' to disable */
+        TSB_CG->EXTENDO0 &= ~Periph;
+    }
+}
+
+/**
+  * @brief  Enable or disable supplying clock fsys for ADC.
+  * @param  NewState: New state of clock fsys supply setting for ADC.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void CG_SetADCClkSupply(FunctionalState NewState)
+{
+    volatile uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Check ADC is not during conversion */
+    do {
+        tmp = TSB_AD->MOD0 & ADC_MOD0_BUSY_MASK;
+    }
+    while (tmp);
+
+    /* Set CGSPCLKEN<ADCKEN>  */
+    tmp = TSB_CG->SPCLKEN;
+    if (NewState == ENABLE) {
+        tmp |= CG_SPCLKEN_ADCKEN_SET;        
+    } else {
+        tmp &= CG_SPCLKEN_ADCKEN_CLEAR;
+    }
+    TSB_CG->SPCLKEN = tmp;
+}
+
+/** @} */
+/* End of group CG_Exported_Functions */
+
+/** @} */
+/* End of group CG */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_CG_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,696 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_gpio.c
+ * @brief   This file provides API functions for GPIO driver.
+ * @version V2.0.2.1
+ * @date    2015/09/08
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_gpio.h"
+
+#if defined(__TMPM066_GPIO_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+#define GPIO_NUM (9U)          /*total number of gpio */
+/**
+  * @brief the base address of GPIO port.
+  */
+const uint32_t GPIO_Base[GPIO_NUM] = {
+    TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE,
+    TSB_PD_BASE, TSB_PE_BASE, TSB_PF_BASE,
+    TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE
+};
+
+/**
+  * @brief:Information of gpio port.
+  * Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means:
+  *          '0': that bit is not available
+  *          '1': that bit is availabe
+  * For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are avaiable;
+*/
+const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = {
+/*        DATA    CR      FR1    FR2    OD     PUP    PDN    SEL    IE  */
+/* PA */ {0xFFU, 0xFFU, {0x80U, 0x00U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PB */ {0x0FU, 0x0FU, {0x00U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU},
+/* PC */ {0x3FU, 0x3FU, {0x3FU, 0x00U}, 0x3FU, 0x3FU, 0x3FU, 0x03U, 0x3FU},
+/* PD */ {0x3FU, 0x3FU, {0x1FU, 0x0FU}, 0x3FU, 0x3FU, 0x3FU, 0x30U, 0x3FU},
+/* PE */ {0x3FU, 0x3FU, {0x3FU, 0x02U}, 0x3FU, 0x3FU, 0x3FU, 0x00U, 0x3FU},
+/* PF */ {0xFFU, 0xFFU, {0x3FU, 0x01U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PG */ {0x03U, 0x03U, {0x03U, 0x00U}, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U},
+/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU},
+/* PJ */ {0x0FU, 0x0FU, {0x03U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x0FU, 0x0FU}
+};
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Read GPIO Data register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @retval Data:The value of DATA register.
+  */
+uint8_t GPIO_ReadData(GPIO_Port GPIO_x)
+{
+    uint8_t Data = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    Data = (uint8_t) PORT->DATA;
+    return Data;
+}
+
+/**
+  * @brief  Read Bit of GPIO Data register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7.
+  * @retval BitValue:The value of specified Bit.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
+  */
+uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t Data = 0U;
+    uint8_t tmp = 0U;
+    uint8_t BitValue = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_BIT(Bit_x));
+    assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    Data = (uint8_t) PORT->DATA;
+    tmp = (uint8_t) (Data & Bit_x);
+    if (tmp) {
+        BitValue = GPIO_BIT_VALUE_1;
+    } else {
+        BitValue = GPIO_BIT_VALUE_0;
+    }
+    return (BitValue);
+
+}
+
+/**
+  * @brief  Write specified value to GPIO DATA register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Data: specified value will be written to GPIO DATA register.
+  * @retval None
+  */
+void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data)
+{
+
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_WRITE(GPIO_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    PORT->DATA = Data;
+
+}
+
+/**
+  * @brief  Write to specified Bit of GPIO DATA register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin,which can set as output.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param BitValue:The value of specified Bit.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
+  * @retval None
+  */
+void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
+{
+    uint8_t tmp = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_BIT_VALUE(BitValue));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = GPIO_ReadData(GPIO_x);
+    if (BitValue) {
+        tmp |= Bit_x;
+    } else {
+        Bit_x = (~Bit_x);
+        tmp &= Bit_x;
+    }
+    PORT->DATA = tmp;
+}
+
+/**
+  * @brief  Initialize the specified GPIO pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  GPIO_InitStruct: The structure containing basic GPIO configuration.
+  * @retval None
+  */
+void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct));
+    assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode));
+    assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp));
+    assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown));
+    assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain));
+
+    if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) {
+        assert_param(IS_GPIO_INPUT_VOLTAGE_STATE(GPIO_InitStruct->InputVoltage));
+    }
+    tmp = GPIO_InitStruct->IOMode;
+    switch (tmp) {
+    case GPIO_INPUT_MODE:
+        GPIO_SetInput(GPIO_x, Bit_x);
+        break;
+    case GPIO_OUTPUT_MODE:
+        GPIO_SetOutput(GPIO_x, Bit_x);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->PullUp;
+    switch (tmp) {
+    case GPIO_PULLUP_ENABLE:
+        GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_PULLUP_DISABLE:
+        GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->PullDown;
+    switch (tmp) {
+    case GPIO_PULLDOWN_ENABLE:
+        GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_PULLDOWN_DISABLE:
+        GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->OpenDrain;
+    switch (tmp) {
+    case GPIO_OPEN_DRAIN_ENABLE:
+        GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_OPEN_DRAIN_DISABLE:
+        GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) {
+        tmp = GPIO_InitStruct->InputVoltage;
+        switch (tmp) {
+        case GPIO_INPUT_VOLTAGE_3V:
+            GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_0);
+            break;
+        case GPIO_INPUT_VOLTAGE_1V8:
+            GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_1);
+            break;
+        default:
+            /* Do nothing */
+            break;
+        }
+    }
+}
+
+/**
+  * @brief  Set specified GPIO Pin as output port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t tmp = 0U;
+    uint32_t i;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = (~Bit_x);
+    for (i = 0U; i < FRMAX; i++) {
+        if (GPIO_SFRs[GPIO_x].PinFR[i]) {
+            PORT->FR[i] &= tmp;
+        } else {
+            /* Do nothing */
+        }
+    }
+    if (GPIO_SFRs[GPIO_x].PinIE) {
+        PORT->IE &= tmp;
+    } else {
+        /* Do nothing */
+    }
+    PORT->CR |= Bit_x;
+}
+
+/**
+  * @brief  Set specified GPIO Pin as input port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t tmp = 0U;
+    uint32_t i;
+    TSB_Port_TypeDef *PORT = 0U;
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinIE;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = (~Bit_x);
+    for (i = 0U; i < FRMAX; i++) {
+        if (GPIO_SFRs[GPIO_x].PinFR[i]) {
+            PORT->FR[i] &= tmp;
+        } else {
+            /* Do nothing */
+        }
+    }
+    if (GPIO_SFRs[GPIO_x].PinCR) {
+        PORT->CR &= tmp;
+    } else {
+        /* Do nothing */
+    }
+    PORT->IE |= Bit_x;
+
+}
+
+/**
+  * @brief  Set or clear the bit setting in output control register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param NewState: The output state of the pin.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    if (NewState == ENABLE) {
+        PORT->CR |= Bit_x;
+    } else {
+        PORT->CR &= (~(uint32_t) Bit_x);
+    }
+
+}
+
+/**
+  * @brief  Set or clear the bit setting in input control register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param NewState: The input state of the pin.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinIE;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (NewState == ENABLE) {
+        PORT->IE |= Bit_x;
+    } else {
+        PORT->IE &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable or Disable pull-up function of specified GPIO Pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  NewState: New state of the Pull-Up function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinPUP;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (NewState == ENABLE) {
+        PORT->PUP |= Bit_x;
+    } else {
+        PORT->PUP &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable or Disable pull-down function of specified GPIO Pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  NewState: New state of the Pull-Down function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinPDN;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (NewState == ENABLE) {
+        PORT->PDN |= Bit_x;
+    } else {
+        PORT->PDN &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Set specified GPIO Pin as open drain port or CMOS port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, 
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  NewState: New state of the Open Drian function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinOD;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (NewState == ENABLE) {
+        PORT->OD |= Bit_x;
+    } else {
+        PORT->OD &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief Input voltage selection function of specified GPIO Pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PC, GPIO_PD, GPIO_PG.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param BitValue:The value of specified Bit.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
+  * @retval None
+  */
+void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT_INPUT_VOLTAGE(GPIO_x));
+    assert_param(IS_GPIO_BIT_VALUE(BitValue));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinSEL;
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_SEL(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (BitValue) {
+        PORT->SEL |= Bit_x;
+    } else {
+        PORT->SEL &= (~(uint8_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable specified GPIO Function register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  FuncReg_x: Select Function register of GPIO.
+  *   This parameter can be one of the following values:
+  *   GPIO_FUNC_REG_1, GPIO_FUNC_REG_2.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    PORT->FR[FuncReg_x] |= Bit_x;
+}
+
+/**
+  * @brief  Disable specified GPIO Function register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG,
+  *   GPIO_PH, GPIO_PJ. 
+  * @param  FuncReg_x: Select Function register of GPIO.
+  *   This parameter can be one of the following values:
+  *   GPIO_FUNC_REG_1, GPIO_FUNC_REG_2.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
+    } else {
+        /* Do nothing */
+    }
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x);
+}
+
+/** @} */
+/* End of group GPIO_Exported_Functions */
+/** @} */
+/* End of group GPIO */
+/** @} */
+/* End of group TX00_Periph_Driver */
+#endif                          /* (__TMPM066_GPIO_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,931 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_i2c.c
+ * @brief   This file provides API functions for I2C driver.
+ * @version V2.0.2.1
+ * @date    2015/09/10
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_i2c.h"
+
+#if defined(__TMPM066_I2C_H)
+
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */
+
+/** @defgroup I2C_Private_Defines
+  * @{
+  */
+
+#define I2CCR1_BC_MASK                  ((uint32_t)0x0000001F)
+#define I2CCR1_ACK_SET                  ((uint32_t)0x00000010)
+#define I2CCR1_ACK_CLEAR                ((uint32_t)0x000000EF)
+#define I2CCR1_SCK_MASK                 ((uint32_t)0x000000F8)
+#define I2CCR1_NOACK_MASK               ((uint32_t)0x00000008)
+#define I2CCR1_NOACK_ENABLE             ((uint32_t)0x00000000)
+
+#define I2CCR2_PIN_SET                  ((uint32_t)0x00000010)
+#define I2CCR2_I2CM_I2C                 ((uint32_t)0x00000008)
+#define I2CCR2_SWRST_MASK               ((uint32_t)0xFFFFFFFC)
+#define I2CCR2_SWRST_CMD1               ((uint32_t)0x00000002)
+#define I2CCR2_SWRST_CMD2               ((uint32_t)0x00000001)
+#define I2CCR2_START_CONDITION          ((uint32_t)0x000000F0)
+#define I2CCR2_STOP_CONDITION           ((uint32_t)0x000000D0)
+
+
+#define I2CAR_SA_MASK                ((uint32_t)0x000000FE)
+#define I2CAR_ALS_SET                ((uint32_t)0x00000001)
+#define I2CAR_ALS_CLEAR              ((uint32_t)0xFFFFFFFE)
+#define I2C_DATA_MASK                ((uint32_t)0x000000FF)
+
+#define I2CIE_IE_SELPINCD_SET        ((uint32_t)0x00000040)
+#define I2CIE_IE_DMARI2CTX_SET       ((uint32_t)0x00000020)
+#define I2CIE_IE_DMARI2CRX_SET       ((uint32_t)0x00000010)
+#define I2CIE_IE_INTNACK_SET         ((uint32_t)0x00000008)
+#define I2CIE_IE_INTI2CBF_SET        ((uint32_t)0x00000004)
+#define I2CIE_IE_INTI2CAL_SET        ((uint32_t)0x00000002)
+#define I2CIE_IE_INTI2C_SET         ((uint32_t)0x00000001)
+
+
+#define I2CIE_IE_SELPINCD_CLEAR       ((uint32_t)0xFFFFFFBF)
+#define I2CIE_IE_DMARI2CTX_CLEAR      ((uint32_t)0xFFFFFFDF)
+#define I2CIE_IE_DMARI2CRX_CLEAR      ((uint32_t)0xFFFFFFEF)
+#define I2CIE_IE_INTNACK_CLEAR        ((uint32_t)0xFFFFFFF7)
+#define I2CIE_IE_INTI2CBF_CLEAR       ((uint32_t)0xFFFFFFFB)
+#define I2CIE_IE_INTI2CAL_CLEAR       ((uint32_t)0xFFFFFFFD)
+#define I2CIE_IE_NTI2C_CLEAR         ((uint32_t)0xFFFFFFFE)
+
+#define I2CST_NACK_MASK              ((uint32_t)0x00000008)
+#define I2CST_I2CBF_MASK             ((uint32_t)0x00000004)
+#define I2CST_I2CAL_MASK             ((uint32_t)0x00000002)
+#define I2CST_I2C_MASK               ((uint32_t)0x00000001)
+
+#define I2CST_NACK_SET               ((uint32_t)0x00000008)
+#define I2CST_I2CBF_SET              ((uint32_t)0x00000004)
+#define I2CST_I2CAL_SET              ((uint32_t)0x00000002)
+#define I2CST_I2C_SET                ((uint32_t)0x00000001)
+
+#define I2COP_GCDI_ON               ((uint32_t)0x000000FB)
+#define I2COP_GCDI_OFF              ((uint32_t)0x00000004)
+
+#define I2COP_RSTA_SET              ((uint32_t)0x00000008)
+#define I2COP_RSTA_CLEAR            ((uint32_t)0xFFFFFFF7)
+
+#define I2COP_MFACK_NACK            ((uint32_t)0x00000001)
+#define I2COP_MFACK_ACK             ((uint32_t)0xFFFFFFFE)
+
+#define I2COP_SREN_SET              ((uint32_t)0x00000002)
+#define I2COP_SREN_CLEAR            ((uint32_t)0xFFFFFFFD)
+
+#define I2CAR2_SA2EN_USE             ((uint32_t)0x00000001)
+#define I2CAR2_SA2EN_NOUSE           ((uint32_t)0x000000FE)
+
+/** @} */
+/* End of group I2C_Private_Defines */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable or disable the generation of ACK clock. 
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of ACK clock.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = I2Cx->CR1;
+    if (NewState == ENABLE) {
+        /* Set I2CxCR1<ACK> to enable generation of ACK clock */
+        tmp |= I2CCR1_ACK_SET;
+    } else {
+        /* Clear I2CxCR1<ACK> to disable generation of ACK clock */
+        tmp &= I2CCR1_ACK_CLEAR;
+    }
+    I2Cx->CR1 = tmp;
+
+}
+
+/**
+  * @brief  Initialize the specified I2C channel in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  InitI2CStruct: The structure containing I2C in I2C mode configuration.
+  * @retval None
+  */
+void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_POINTER_NOT_NULL(InitI2CStruct));
+    assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr));
+    assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen));
+    assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv));
+    assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState));
+
+    /* Get the system clock frequency */
+    SystemCoreClockUpdate();
+
+    /* Check the prescaler clock in the range between 50ns and 150ns */
+    assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock));
+
+    /* Set prescaler clock */
+    I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32;
+
+    /* Set selfaddress for I2Cx */
+    I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK;
+
+    /* Set I2C bit length of transfer data  */
+    tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
+    tmp |= (InitI2CStruct->I2CDataLen << 5U);
+    /* Set I2C clock division */
+    tmp &= I2CCR1_SCK_MASK;
+    tmp |= InitI2CStruct->I2CClkDiv;
+    if (InitI2CStruct->I2CACKState) {
+        /* Set I2CxCR1<ACK> to enable generation of ACK clock */
+        tmp |= I2CCR1_ACK_SET;
+    } else {
+        /* Clear I2CxCR1<ACK> to disable generation of ACK clock */
+        tmp &= I2CCR1_ACK_CLEAR;
+    }
+    I2Cx->CR1 = tmp;
+
+    /* Intilize I2C to I2C Slave-Rx mode  */
+    I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Specify the number of bits per transfer.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  I2CBitNum: Specify the number of bits.
+  *   This parameter can be one of the following values:
+  *   I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3,
+  *   I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7.
+  * @retval None
+  */
+void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_BIT_NUM(I2CBitNum));
+
+    /* Write number of bits per transfer into I2CxCR1<BC> */
+    tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
+    tmp |= ((uint32_t) I2CBitNum << 5U);
+
+    I2Cx->CR1 = tmp;
+}
+
+/**
+  * @brief  Reset the state of the specified I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_SWReset(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK;
+    I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1;
+    I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2;
+}
+
+/**
+  * @brief  Clear I2C interrupt request in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<PIN> to clear request, and Set I2CxCR2<I2CM> to enable  I2C operation */
+    tmp = I2Cx->SR;
+    tmp &= (uint32_t) 0x000000E0;
+    tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C);
+    I2Cx->CR2 = tmp;
+}
+
+/**
+  * @brief  Set I2c bus to Master mode and Generate start condition in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<MST>, <TRX>, <BB> and <PIN> to generate start condition */
+    I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Set I2c bus to Master mode and Generate stop condition in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<MST>, <TRX>, <PIN> and clear <BB> to generate stop condition */
+    I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Get the I2C channel state in I2C mode
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval The state of the I2C channel in I2C bus.
+  */
+I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx)
+{
+    I2C_State state;
+    state.All = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    state.All = I2Cx->SR;
+    state.All &= I2C_DATA_MASK;
+    return state;
+}
+
+
+/**
+  * @brief  Set data to be sent and MCU starts transmission.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  Data: The data to be sent, max 0xFF.
+  * @retval None
+  */
+void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_DATA(Data));
+
+    /* Write data into I2CxDBR */
+    I2Cx->DBR = Data;
+}
+
+/**
+  * @brief  Get data having been received.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval The data having been received
+  */
+uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t retval = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Save the received data */
+    retval = I2Cx->DBR;
+    retval &= I2C_DATA_MASK;
+
+    return retval;
+}
+
+/**
+  * @brief  Enable or disable I2C free data mode of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2CAR<ALS> to use free data mode transfer in I2C mode */
+        I2Cx->AR |= I2CAR_ALS_SET;
+    } else {
+        /* Clear I2CxI2CAR<ALS> to not use free data mode transfer in I2C mode */
+        I2Cx->AR &= I2CAR_ALS_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get slave address match detection state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK;
+    if (tmp == I2CCR1_NOACK_ENABLE) {
+        /* the slave address match or general call detection are enabled. */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Set prescaler clock of the specified I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  PrescalerClock: the prescaler clock value.
+  *   This parameter can be one of the following values:
+  *   I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32
+  * @retval None
+  */
+void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Get the system clock frequency */
+    SystemCoreClockUpdate();
+
+    /* Check the prescaler clock in the range between 50ns and 150ns */
+    assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock));
+
+    /* Write prescaler clock into I2CxPRS<PRSCK> */
+    I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32;
+}
+
+/**
+  * @brief  Enable or disable open condition of the pin.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<SELPINCD> to enable pin open by reading DBR */
+        I2Cx->IE |= I2CIE_IE_SELPINCD_SET;
+    } else {
+        /* Clear I2CxIE<SELPINCD> to disable pin open by reading DBR */
+        I2Cx->IE &= I2CIE_IE_SELPINCD_CLEAR;
+    }
+}
+
+
+/**
+  * @brief  Enable or disable a DMAC transmisstion request output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<DMARI2CTX> to enable a DMAC transmisstion request */
+        I2Cx->IE |= I2CIE_IE_DMARI2CTX_SET;
+    } else {
+        /* Clear I2CxIE<DMARI2CTX> to disable a DMAC transmisstion request */
+        I2Cx->IE &= I2CIE_IE_DMARI2CTX_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable a DMAC reception request output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<DMARI2CRX> to enable a DMAC reception request */
+        I2Cx->IE |= I2CIE_IE_DMARI2CRX_SET;
+    } else {
+        /* Clear I2CxIE<DMARI2CRX> to disable a DMAC reception request */
+        I2Cx->IE &= I2CIE_IE_DMARI2CRX_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable NACK detection interrupt of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<INTNACK> to enable NACK detection interrupt */
+        I2Cx->IE |= I2CIE_IE_INTNACK_SET;
+    } else {
+        /* Clear I2CxIE<INTNACK> to disable NACK detection interrupt */
+        I2Cx->IE &= I2CIE_IE_INTNACK_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable bus-free interrupt of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<INTNACK> to enable bus-free interrupt */
+        I2Cx->IE |= I2CIE_IE_INTI2CBF_SET;
+    } else {
+        /* Clear I2CxIE<INTNACK> to disable bus-free interrupt */
+        I2Cx->IE &= I2CIE_IE_INTI2CBF_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable AL interrupt of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<INTNACK> to enable AL interrupt */
+        I2Cx->IE |= I2CIE_IE_INTI2CAL_SET;
+    } else {
+        /* Clear I2CxIE<INTNACK> to disable AL interrupt */
+        I2Cx->IE &= I2CIE_IE_INTI2CAL_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable I2C interrupt request of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<IE> to enable I2C interrupt request */
+        I2Cx->IE |= I2CIE_IE_INTI2C_SET;
+    } else {
+        /* Clear I2CxIE<IE> to disable I2C interrupt request */
+        I2Cx->IE &= I2CIE_IE_NTI2C_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get NACK interrupt generation state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->ST & I2CST_NACK_MASK;
+    if (tmp == I2CST_NACK_SET) {
+        /* the NACK interrupt has been generated */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Get I2CBF interrupt generation state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->ST & I2CST_I2CBF_MASK;
+    if (tmp == I2CST_I2CBF_SET) {
+        /* the I2CBF interrupt has been generated */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Get I2CAL interrupt generation state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->ST & I2CST_I2CAL_MASK;
+    if (tmp == I2CST_I2CAL_SET) {
+        /* the I2CAL interrupt has been generated */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Get I2C interrupt generation state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->ST & I2CST_I2C_MASK;
+    if (tmp == I2CST_I2C_SET) {
+        /* the I2C interrupt has been generated */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Clear the NACK interrupt output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxST<NACK> to clear the NACK interrupt output(INTI2Cx) */
+    I2Cx->ST = I2CST_NACK_SET;
+}
+
+/**
+  * @brief  Clear the I2CBF interrupt output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxST<I2CBF> to clear the I2CBF interrupt output(INTI2Cx) */
+    I2Cx->ST = I2CST_I2CBF_SET;
+}
+
+/**
+  * @brief  Clear the I2CAL interrupt output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxST<I2CAL> to clear the I2CAL interrupt output(INTI2Cx) */
+    I2Cx->ST = I2CST_I2CAL_SET;
+}
+
+/**
+  * @brief  Clear the I2C interrupt output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval None
+  */
+void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxST<I2C> to clear the I2C interrupt output(INTI2Cx) */
+    I2Cx->ST = I2CST_I2C_SET;
+}
+
+/**
+  * @brief  Enable or disable general-call detection. 
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of general call detection.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = I2Cx->OP;
+    if (NewState == ENABLE) {
+        /* Clear I2CxOP<GCDI>, general-call detection is ON */
+        tmp &= I2COP_GCDI_ON;
+    } else {
+        /* Set I2CxOP<GCDI>, general-call detection is OFF */
+        tmp |= I2COP_GCDI_OFF;
+    }
+    I2Cx->OP = tmp;
+
+}
+
+/**
+  * @brief Detect or not a repeated start of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2COP<RSTA> to detect a repeated start */
+        I2Cx->OP |= I2COP_RSTA_SET;
+    } else {
+        /* Clear I2CxI2COP<RSTA> to not detect a repeated start */
+        I2Cx->OP &= I2COP_RSTA_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get repeated start detection state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->OP & I2COP_RSTA_SET;
+    if (tmp == I2COP_RSTA_SET) {
+        /* the repeated start detection are enabled. */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief Select an ACK output of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2COP<MFACK> to select NACK output */
+        I2Cx->OP |= I2COP_MFACK_NACK;
+    } else {
+        /* Clear I2CxI2COP<MFACK> to select ACK output */
+        I2Cx->OP &= I2COP_MFACK_ACK;
+    }
+}
+
+/**
+  * @brief  Enable or disable repeat start of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2COP<SREN> to enable repeat start output */
+        I2Cx->OP |= I2COP_SREN_SET;
+    } else {
+        /* Clear I2CxI2COP<SREN> to disable repeat start output */
+        I2Cx->OP &= I2COP_SREN_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get repeated start state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @retval BUSY or DONE.
+  */
+WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    WorkState retval = BUSY;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->OP & I2COP_SREN_SET;
+    if (tmp == I2COP_SREN_SET) {
+        /* the repeated start detection has completed. */
+        retval = DONE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Enable or disable using 2nd slave address of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Set2ndSlaveAddress(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2CAR2<SA2EN> to using 2nd slave address */
+        I2Cx->AR2 |= I2CAR2_SA2EN_USE;
+    } else {
+        /* Clear I2CxI2CAR2<SA2EN> to not using 2nd slave address */
+        I2Cx->AR2 &= I2CAR2_SA2EN_NOUSE;
+    }
+}
+
+/** @} */
+/* End of group I2C_Exported_Functions */
+
+/** @} */
+/* End of group I2C */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /*   defined(__TMPM066_I2C_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,284 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_intifao.c
+ * @brief   This file provides API functions for INTIFAO driver 
+ * @version V2.0.2.2
+ * @date    2016/02/15
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_intifao.h"
+
+#if defined(__TMPM066_INTIFAO_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup INTIFAO
+  * @brief INTIFAO driver modules
+  * @{
+  */
+
+/** @defgroup INTIFAO_Private_Defines
+  * @{
+  */
+#define INT_NCLR_PCLR_CLEAR                  ((uint8_t)0x01)
+#define INT_EN_MODE_MASK                     ((uint8_t)0xF0)
+#define INT_MODE_MASK                        ((uint8_t)0x0E)
+
+#define INTIFAO_INTFLAG1_MASK                ((uint32_t)0xFFFFFF00)
+
+/** @} */
+/* End of group INTIFAO_Private_Defines */
+
+/** @defgroup INTIFAO_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group INTIFAO_Private_FunctionPrototypes */
+
+/** @defgroup INTIFAO_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group INTIFAO_Private_Functions */
+
+/** @defgroup INTIFAO_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the INT source for releasing low power mode.
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:  
+  *   INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
+  *   INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
+  * @param  ActiveState: select the active state for release trigger
+  *   This parameter can be one of the following values:
+  *   INTIFAO_INT_ACTIVE_STATE_L, 
+  *   INTIFAO_INT_ACTIVE_STATE_H, 
+  *   INTIFAO_INT_ACTIVE_STATE_FALLING, 
+  *   INTIFAO_INT_ACTIVE_STATE_RISING or 
+  *   INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES.
+  * @param  NewState: Enable or disable this release trigger
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource,
+                             INTIFAO_INTActiveState ActiveState, FunctionalState NewState)
+{
+    uint8_t num = 0U;
+    uint32_t regval;
+    
+    /* Check the parameters */
+    assert_param(IS_INTIFAO_INT_SRC(INTSource));
+    assert_param(IS_INTIFAO_INT_ACTIVE_STATE(ActiveState));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if ((INTSource == INTIFAO_INT_SRC_I2CS) || (INTSource == INTIFAO_INT_SRC_USBWKUP)) {
+        assert_param(IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(ActiveState));
+    } else {
+        /* Do nothing */
+    }
+
+    num = (uint32_t) INTSource;
+
+    switch (num) {
+    case 0U:                   /* STOP2INT_032 */
+      regval =	TSB_INTIFAO ->STOP2INT_032;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_032 = regval;
+        break;
+    case 1U:                   /* STOP2INT_033 */
+      regval =	TSB_INTIFAO ->STOP2INT_033;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_033 = regval;
+        break;
+    case 2U:                   /* STOP2INT_034 */ 
+      regval =	TSB_INTIFAO ->STOP2INT_034;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_034 = regval;
+        break;
+    case 3U:                   /* STOP2INT_035 */
+      regval =	TSB_INTIFAO ->STOP2INT_035;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_035 = regval;
+        break;
+    case 4U:                   /* STOP2INT_036 */
+      regval =	TSB_INTIFAO ->STOP2INT_036;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_036 = regval;
+        break;
+    case 5U:                   /* STOP2INT_037 */
+      regval =	TSB_INTIFAO ->STOP2INT_037;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_037 = regval;    
+        break;
+    case 6U:                   /* STOP2INT_038 */
+      regval =	TSB_INTIFAO ->STOP2INT_038;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_038 = regval;   	
+        break;
+    case 7U:                   /* STOP2INT_039 */
+      regval =	TSB_INTIFAO ->STOP2INT_039;
+      regval &= INT_EN_MODE_MASK;
+      regval |= NewState;
+      regval |= ActiveState << 1;
+      TSB_INTIFAO ->STOP2INT_039 = regval;  	
+        break; 
+    default:
+        /* Do nothing */
+        break;  
+    }   
+}       
+        
+/**
+  * @brief  Get the active state of INT source standby clear request
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:  
+  *   INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
+  *   INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
+  * @retval Active state of the input INT
+  *   The value returned can be one of the following values:
+  *   INTIFAO_INT_ACTIVE_STATE_FALLING, INTIFAO_INT_ACTIVE_STATE_RISING,
+  *   INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES or INTIFAO_INT_ACTIVE_STATE_INVALID
+  */
+INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource)
+{
+    INTIFAO_INTActiveState int_active_state = INTIFAO_INT_ACTIVE_STATE_INVALID;    
+    uint8_t tmp = 0U;
+    uint8_t num = 0U;
+    uint8_t regval[8] = {0};
+
+    /* Check the parameters */
+    assert_param(IS_INTIFAO_INT_SRC(INTSource));
+     
+    regval[0] = TSB_INTIFAO ->STOP2INT_032 & INT_MODE_MASK;
+    regval[1] = TSB_INTIFAO ->STOP2INT_033 & INT_MODE_MASK;
+    regval[2] = TSB_INTIFAO ->STOP2INT_034 & INT_MODE_MASK;   
+    regval[3] = TSB_INTIFAO ->STOP2INT_035 & INT_MODE_MASK;
+    regval[4] = TSB_INTIFAO ->STOP2INT_036 & INT_MODE_MASK;
+    regval[5] = TSB_INTIFAO ->STOP2INT_037 & INT_MODE_MASK;
+    regval[6] = TSB_INTIFAO ->STOP2INT_038 & INT_MODE_MASK;   
+    regval[7] = TSB_INTIFAO ->STOP2INT_039 & INT_MODE_MASK;
+
+    num = (uint32_t) INTSource;
+    tmp = regval[num];
+    tmp = tmp >>1;
+    switch (tmp) {
+    case 3U:
+        int_active_state = INTIFAO_INT_ACTIVE_STATE_RISING;
+        break;
+    case 2U:
+        int_active_state = INTIFAO_INT_ACTIVE_STATE_FALLING;
+        break;
+    case 4U:
+        int_active_state = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    return (int_active_state);
+}
+
+/**
+  * @brief  Clears the input INT request.
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:
+  *   INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3,
+  *   INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP.
+  * @retval None
+  */
+void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource)
+{
+    uint8_t num = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_INTIFAO_INT_SRC(INTSource));
+    
+    num = (uint32_t) INTSource;
+    switch (num) {
+    case 0U:                   /* STOP2INT_032 */
+      TSB_INTIFAO_STOP2INT_032_INT032PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_032_INT032NCLR = INT_NCLR_PCLR_CLEAR;
+        break;      
+     case 1U:                   /* STOP2INT_033 */     
+      TSB_INTIFAO_STOP2INT_033_INT033PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_033_INT033NCLR = INT_NCLR_PCLR_CLEAR;
+        break;   
+    case 2U:                   /* STOP2INT_034 */   
+      TSB_INTIFAO_STOP2INT_034_INT034PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_034_INT034NCLR = INT_NCLR_PCLR_CLEAR;
+        break;   
+    case 3U:                   /* STOP2INT_035 */  
+      TSB_INTIFAO_STOP2INT_035_INT035PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_035_INT035NCLR = INT_NCLR_PCLR_CLEAR;
+        break;  
+    case 4U:                   /* STOP2INT_036 */ 
+      TSB_INTIFAO_STOP2INT_036_INT036PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_036_INT036NCLR = INT_NCLR_PCLR_CLEAR;
+        break;  
+    case 5U:                   /* STOP2INT_037 */
+      TSB_INTIFAO_STOP2INT_037_INT037PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_037_INT037NCLR = INT_NCLR_PCLR_CLEAR;
+        break;  
+    case 6U:                   /* STOP2INT_038 */
+      TSB_INTIFAO_STOP2INT_038_INT038PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_038_INT038NCLR = INT_NCLR_PCLR_CLEAR;
+        break;  
+    case 7U:                   /* STOP2INT_039 */
+      TSB_INTIFAO_STOP2INT_039_INT039PCLR = INT_NCLR_PCLR_CLEAR; 
+      TSB_INTIFAO_STOP2INT_039_INT039NCLR = INT_NCLR_PCLR_CLEAR;
+        break; 
+    default:
+        /* Do nothing */
+        break;  
+    } 
+}
+
+/**
+  * @brief  Get the INTFLAG1.
+  * @param  None
+  * @retval INTFLAG1 flag
+  */
+INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void)
+{
+    INTIFAO_IntFlag1Factor intifao_intflag1_factor = { 0U };
+
+    intifao_intflag1_factor.All = TSB_INTIFSD->FLAG1 & (~INTIFAO_INTFLAG1_MASK);
+
+    return intifao_intflag1_factor;
+}
+
+/** @} */
+/* End of group INTIFAO_Exported_Functions */
+
+/** @} */
+/* End of group INTIFAO */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_INTIFAO_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,368 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_intifsd.c
+ * @brief   This file provides API functions for INTIFSD driver 
+ * @version V2.0.2.1    
+ * @date    2015/10/19
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_intifsd.h"
+
+#if defined(__TMPM066_INTIFSD_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup INTIFSD
+  * @brief INTIFSD driver modules
+  * @{
+  */
+
+/** @defgroup INTIFSD_Private_Defines
+  * @{
+  */
+#define INTIFSD_NMIFLG_MASK                       ((uint32_t)0xFFF8FFFF)
+
+#define INTIFSD_INTFLAG4_MASK                     ((uint32_t)0xE0000000)
+#define INTIFSD_INTFLAG5_MASK                     ((uint32_t)0xFFFFFC00)
+
+/** @} */
+/* End of group INTIFSD_Private_Defines */
+
+/** @defgroup INTIFSD_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group INTIFSD_Private_FunctionPrototypes */
+
+/** @defgroup INTIFSD_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group INTIFSD_Private_Functions */
+
+/** @defgroup INTIFSD_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Get the NMI flag that shows who triggered NMI.
+  * @param  None
+  * @retval NMI flag
+  */
+INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void)
+{
+    INTIFSD_NMIFactor intifsd_nmi_factor = { 0U };
+
+    intifsd_nmi_factor.All = TSB_INTIFSD->FLAG0 & (~INTIFSD_NMIFLG_MASK);
+
+    return intifsd_nmi_factor;
+}
+
+/**
+  * @brief  Get the INTFLAG3.
+  * @param  None
+  * @retval INTFLAG3 flag
+  */
+INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void)
+{
+    INTIFSD_IntFlag3Factor intifsd_intflag3_factor = { 0U };
+
+    intifsd_intflag3_factor.All = TSB_INTIFSD->FLAG3;
+
+    return intifsd_intflag3_factor;
+}
+
+/**
+  * @brief  Get the INTFLAG4.
+  * @param  None
+  * @retval INTFLAG4 flag
+  */
+INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void)
+{
+    INTIFSD_IntFlag4Factor intifsd_intflag4_factor = { 0U };
+
+    intifsd_intflag4_factor.All = TSB_INTIFSD->FLAG4 & (~INTIFSD_INTFLAG4_MASK);
+
+    return intifsd_intflag4_factor;
+}
+
+/**
+  * @brief  Get the INTFLAG5.
+  * @param  None
+  * @retval INTFLAG5 flag
+  */
+INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void)
+{
+    INTIFSD_IntFlag5Factor intifsd_intflag5_factor = { 0U };
+
+    intifsd_intflag5_factor.All = TSB_INTIFSD->FLAG5 & (~INTIFSD_INTFLAG5_MASK);
+
+    return intifsd_intflag5_factor;
+}
+
+/**
+  * @brief  Clears the input INT request.
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:
+  *   INTIFSD_INT_SRC_LVD_PSFD, INTIFSD_INT_SRC_LVD_PRD, INTIFSD_INT_SRC_WDT, INTIFSD_INT_SRC_DMAC_0,
+  *   INTIFSD_INT_SRC_DMAC_1, INTIFSD_INT_SRC_DMAC_2, INTIFSD_INT_SRC_DMAC_3, INTIFSD_INT_SRC_DMAC_4,
+  *   INTIFSD_INT_SRC_DMAC_5, INTIFSD_INT_SRC_DMAC_6, INTIFSD_INT_SRC_DMAC_7, INTIFSD_INT_SRC_DMAC_8,
+  *   INTIFSD_INT_SRC_DMAC_9, INTIFSD_INT_SRC_DMAC_10, INTIFSD_INT_SRC_DMAC_11, INTIFSD_INT_SRC_DMAC_12,
+  *   INTIFSD_INT_SRC_DMAC_13, INTIFSD_INT_SRC_DMAC_14, INTIFSD_INT_SRC_DMAC_15, INTIFSD_INT_SRC_DMAC_16,
+  *   INTIFSD_INT_SRC_DMAC_17, INTIFSD_INT_SRC_DMAC_18, INTIFSD_INT_SRC_DMAC_19, INTIFSD_INT_SRC_DMAC_20,
+  *   INTIFSD_INT_SRC_DMAC_21, INTIFSD_INT_SRC_DMAC_22, INTIFSD_INT_SRC_DMAC_23, INTIFSD_INT_SRC_DMAC_24,
+  *   INTIFSD_INT_SRC_DMAC_25, INTIFSD_INT_SRC_DMAC_26, INTIFSD_INT_SRC_DMAC_27, INTIFSD_INT_SRC_DMAC_28,
+  *   INTIFSD_INT_SRC_DMAC_29, INTIFSD_INT_SRC_DMAC_30, INTIFSD_INT_SRC_DMAC_31, INTIFSD_INT_SRC_DMAC_ERR,
+  *   INTIFSD_INT_SRC_TMRB_0_MDOVF, INTIFSD_INT_SRC_TMRB_0_CAP0, INTIFSD_INT_SRC_TMRB_0_CAP1, INTIFSD_INT_SRC_TMRB_1_MDOVF,
+  *   INTIFSD_INT_SRC_TMRB_1_CAP0, INTIFSD_INT_SRC_TMRB_1_CAP1, INTIFSD_INT_SRC_TMRB_2_MDOVF, INTIFSD_INT_SRC_TMRB_2_CAP0,
+  *   INTIFSD_INT_SRC_TMRB_2_CAP1, INTIFSD_INT_SRC_TMRB_3_MDOVF, INTIFSD_INT_SRC_TMRB_3_CAP0, INTIFSD_INT_SRC_TMRB_3_CAP1,
+  *   INTIFSD_INT_SRC_TMRB_4_MDOVF,INTIFSD_INT_SRC_TMRB_4_CAP0, INTIFSD_INT_SRC_TMRB_4_CAP1, INTIFSD_INT_SRC_TMRB_5_MDOVF,
+  *   INTIFSD_INT_SRC_TMRB_5_CAP0, INTIFSD_INT_SRC_TMRB_5_CAP1, INTIFSD_INT_SRC_TMRB_6_MDOVF, INTIFSD_INT_SRC_TMRB_6_CAP0,
+  *   INTIFSD_INT_SRC_TMRB_6_CAP1, INTIFSD_INT_SRC_TMRB_7_MDOVF, INTIFSD_INT_SRC_TMRB_7_CAP0, INTIFSD_INT_SRC_TMRB_7_CAP1,
+  *   INTIFSD_INT_SRC_TMRD_00, INTIFSD_INT_SRC_TMRD_01, INTIFSD_INT_SRC_TMRD_02, INTIFSD_INT_SRC_TMRD_03,
+  *   INTIFSD_INT_SRC_TMRD_04, INTIFSD_INT_SRC_TMRD_10, INTIFSD_INT_SRC_TMRD_11, INTIFSD_INT_SRC_TMRD_12,
+  *   INTIFSD_INT_SRC_TMRD_13, INTIFSD_INT_SRC_TMRD_14.
+  * @retval None
+  */
+void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource)
+{
+    uint8_t num = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_INTIFSD_INT_SRC(INTSource));
+
+    num = (uint32_t) INTSource;
+    switch (num) {
+    case 0U:                   /* STOP1INT_016 */
+        TSB_INTIFSD->STOP1INT_016 |= 0xC0;
+        break;
+    case 1U:                   /* STOP1INT_017 */
+        TSB_INTIFSD->STOP1INT_017 |= 0xC0;
+        break;
+    case 2U:                   /* IDLEINT_018 */
+        TSB_INTIFSD->IDLEINT_018 |= 0xC0;
+        break;
+    case 3U:                   /* IDLEINT_096 */
+        TSB_INTIFSD->IDLEINT_096 |= 0xC0;
+        break;
+    case 4U:                   /* IDLEINT_097 */
+        TSB_INTIFSD->IDLEINT_097 |= 0xC0;
+        break;
+    case 5U:                   /* IDLEINT_098 */
+        TSB_INTIFSD->IDLEINT_098 |= 0xC0;
+        break;
+    case 6U:                   /* IDLEINT_099 */
+        TSB_INTIFSD->IDLEINT_099 |= 0xC0;
+        break;
+    case 7U:                   /* IDLEINT_100 */
+        TSB_INTIFSD->IDLEINT_100 |= 0xC0;
+        break;
+    case 8U:                   /* IDLEINT_101 */
+        TSB_INTIFSD->IDLEINT_101 |= 0xC0;
+        break;
+    case 9U:                   /* IDLEINT_102 */
+        TSB_INTIFSD->IDLEINT_102 |= 0xC0;
+        break;
+    case 10U:                  /* IDLEINT_103 */
+        TSB_INTIFSD->IDLEINT_103 |= 0xC0;
+        break;
+    case 11U:                  /* IDLEINT_104 */
+        TSB_INTIFSD->IDLEINT_104 |= 0xC0;
+        break;
+    case 12U:                  /* IDLEINT_105 */
+        TSB_INTIFSD->IDLEINT_105 |= 0xC0;
+        break;
+    case 13U:                  /* IDLEINT_106 */
+        TSB_INTIFSD->IDLEINT_106 |= 0xC0;
+        break;
+    case 14U:                  /* IDLEINT_107 */
+        TSB_INTIFSD->IDLEINT_107 |= 0xC0;
+        break;
+    case 15U:                  /* IDLEINT_108 */
+        TSB_INTIFSD->IDLEINT_108 |= 0xC0;
+        break;
+    case 16U:                  /* IDLEINT_109 */
+        TSB_INTIFSD->IDLEINT_109 |= 0xC0;
+        break;
+    case 17U:                  /* IDLEINT_110 */
+        TSB_INTIFSD->IDLEINT_110 |= 0xC0;
+        break;
+    case 18U:                  /* IDLEINT_111 */
+        TSB_INTIFSD->IDLEINT_111 |= 0xC0;
+        break;
+    case 19U:                  /* IDLEINT_112 */
+        TSB_INTIFSD->IDLEINT_112 |= 0xC0;
+        break;
+    case 20U:                  /* IDLEINT_113 */
+        TSB_INTIFSD->IDLEINT_113 |= 0xC0;
+        break;
+    case 21U:                  /* IDLEINT_114 */
+        TSB_INTIFSD->IDLEINT_114 |= 0xC0;
+        break;
+    case 22U:                  /* IDLEINT_115 */
+        TSB_INTIFSD->IDLEINT_115 |= 0xC0;
+        break;
+    case 23U:                  /* IDLEINT_116 */
+        TSB_INTIFSD->IDLEINT_116 |= 0xC0;
+        break;
+    case 24U:                  /* IDLEINT_117 */
+        TSB_INTIFSD->IDLEINT_117 |= 0xC0;
+        break;
+    case 25U:                  /* IDLEINT_118 */
+        TSB_INTIFSD->IDLEINT_118 |= 0xC0;
+        break;
+    case 26U:                  /* IDLEINT_119 */
+        TSB_INTIFSD->IDLEINT_119 |= 0xC0;
+        break;
+    case 27U:                  /* IDLEINT_120 */
+        TSB_INTIFSD->IDLEINT_120 |= 0xC0;
+        break;
+    case 28U:                  /* IDLEINT_121 */
+        TSB_INTIFSD->IDLEINT_121 |= 0xC0;
+        break;
+    case 29U:                  /* IDLEINT_122 */
+        TSB_INTIFSD->IDLEINT_122 |= 0xC0;
+        break;
+    case 30U:                  /* IDLEINT_123 */
+        TSB_INTIFSD->IDLEINT_123 |= 0xC0;
+        break;
+    case 31U:                  /* IDLEINT_124 */
+        TSB_INTIFSD->IDLEINT_124 |= 0xC0;
+        break;
+    case 32U:                  /* IDLEINT_125 */
+        TSB_INTIFSD->IDLEINT_125 |= 0xC0;
+        break;
+    case 33U:                  /* IDLEINT_126 */
+        TSB_INTIFSD->IDLEINT_126 |= 0xC0;
+        break;
+    case 34U:                  /* IDLEINT_127 */
+        TSB_INTIFSD->IDLEINT_127 |= 0xC0;
+        break;
+    case 35U:                  /* IDLEINT_128 */
+        TSB_INTIFSD->IDLEINT_128 |= 0xC0;
+        break;
+    case 36U:                  /* IDLEINT_129 */
+        TSB_INTIFSD->IDLEINT_129 |= 0xC0;
+        break;
+    case 37U:                  /* IDLEINT_130 */
+        TSB_INTIFSD->IDLEINT_130 |= 0xC0;
+        break;
+    case 38U:                  /* IDLEINT_131 */
+        TSB_INTIFSD->IDLEINT_131 |= 0xC0;
+        break;
+    case 39U:                  /* IDLEINT_132 */
+        TSB_INTIFSD->IDLEINT_132 |= 0xC0;
+        break;
+    case 40U:                  /* IDLEINT_133 */
+        TSB_INTIFSD->IDLEINT_133 |= 0xC0;
+        break;
+    case 41U:                  /* IDLEINT_134 */
+        TSB_INTIFSD->IDLEINT_134 |= 0xC0;
+        break;
+    case 42U:                  /* IDLEINT_135 */
+        TSB_INTIFSD->IDLEINT_135 |= 0xC0;
+        break;
+    case 43U:                  /* IDLEINT_136 */
+        TSB_INTIFSD->IDLEINT_136 |= 0xC0;
+        break;
+    case 44U:                  /* IDLEINT_137 */
+        TSB_INTIFSD->IDLEINT_137 |= 0xC0;
+        break;
+    case 45U:                  /* IDLEINT_138 */
+        TSB_INTIFSD->IDLEINT_138 |= 0xC0;
+        break;
+    case 46U:                  /* IDLEINT_139 */
+        TSB_INTIFSD->IDLEINT_139 |= 0xC0;
+        break;
+    case 47U:                  /* IDLEINT_140 */
+        TSB_INTIFSD->IDLEINT_140 |= 0xC0;
+        break;
+    case 48U:                  /* IDLEINT_141 */
+        TSB_INTIFSD->IDLEINT_141 |= 0xC0;
+        break;
+    case 49U:                  /* IDLEINT_142 */
+        TSB_INTIFSD->IDLEINT_142 |= 0xC0;
+        break;
+    case 50U:                  /* IDLEINT_143 */
+        TSB_INTIFSD->IDLEINT_143 |= 0xC0;
+        break;
+    case 51U:                  /* IDLEINT_144 */
+        TSB_INTIFSD->IDLEINT_144 |= 0xC0;
+        break;
+    case 52U:                  /* IDLEINT_145 */
+        TSB_INTIFSD->IDLEINT_145 |= 0xC0;
+        break;
+    case 53U:                  /* IDLEINT_146 */
+        TSB_INTIFSD->IDLEINT_146 |= 0xC0;
+        break;
+    case 54U:                  /* IDLEINT_147 */
+        TSB_INTIFSD->IDLEINT_147 |= 0xC0;
+        break;
+    case 55U:                  /* IDLEINT_148 */
+        TSB_INTIFSD->IDLEINT_148 |= 0xC0;
+        break;
+    case 56U:                  /* IDLEINT_149 */
+        TSB_INTIFSD->IDLEINT_149 |= 0xC0;
+        break;
+    case 57U:                  /* IDLEINT_150 */
+        TSB_INTIFSD->IDLEINT_150 |= 0xC0;
+        break;
+    case 58U:                  /* IDLEINT_151 */
+        TSB_INTIFSD->IDLEINT_151 |= 0xC0;
+        break;
+    case 59U:                  /* IDLEINT_152 */
+        TSB_INTIFSD->IDLEINT_152 |= 0xC0;
+        break;
+    case 60U:                  /* IDLEINT_160 */
+        TSB_INTIFSD->IDLEINT_160 |= 0xC0;
+        break;
+    case 61U:                  /* IDLEINT_161 */
+        TSB_INTIFSD->IDLEINT_161 |= 0xC0;
+        break;
+    case 62U:                  /* IDLEINT_162 */
+        TSB_INTIFSD->IDLEINT_162 |= 0xC0;
+        break;
+    case 63U:                  /* IDLEINT_163 */
+        TSB_INTIFSD->IDLEINT_163 |= 0xC0;
+        break;
+    case 64U:                  /* IDLEINT_164 */
+        TSB_INTIFSD->IDLEINT_164 |= 0xC0;
+        break;
+    case 65U:                  /* IDLEINT_165 */
+        TSB_INTIFSD->IDLEINT_165 |= 0xC0;
+        break;
+    case 66U:                  /* IDLEINT_166 */
+        TSB_INTIFSD->IDLEINT_166 |= 0xC0;
+        break;
+    case 67U:                  /* IDLEINT_167 */
+        TSB_INTIFSD->IDLEINT_167 |= 0xC0;
+        break;
+    case 68U:                  /* IDLEINT_168 */
+        TSB_INTIFSD->IDLEINT_168 |= 0xC0;
+        break;
+    case 69U:                  /* IDLEINT_169 */
+        TSB_INTIFSD->IDLEINT_169 |= 0xC0;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/** @} */
+/* End of group INTIFSD_Exported_Functions */
+
+/** @} */
+/* End of group INTIFSD */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_INTIFSD_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,195 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_tmr16a.c
+ * @brief   This file provides API functions for TMR16A driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_tmr16a.h"
+
+#if defined(__TMPM066_TMR16A_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup TMR16A
+  * @brief TMR16A driver modules
+  * @{
+  */
+
+/** @defgroup TMR16A_Private_Defines
+  * @{
+  */
+#define CR_CLK_SYSCK        ((uint32_t)0xFFFFFFFE)
+#define CR_CLK_PRCK         ((uint32_t)0x00000001)
+#define CR_FF_MASK          ((uint32_t)0xFFFFFF4F)
+
+#define CP_CP_CLEAR         ((uint32_t)0xFFFF0000)
+/** @} */
+/* End of group TMR16A_Private_Defines */
+
+/** @defgroup TMR16A_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group TMR16A_Private_FunctionPrototypes */
+
+/** @defgroup TMR16A_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group TMR16A_Private_Functions */
+
+/** @defgroup TMR16A_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Start or stop counter of the specified TMR16A channel.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @param  Cmd: The command for the counter.
+  *   This parameter can be TMR16A_RUN or TMR16A_STOP.
+  * @retval None
+  */
+void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+    assert_param(IS_TMR16A_CMD(Cmd));
+
+    /* Write command into RUN register */
+    T16Ax->RUN = Cmd;
+}
+
+/**
+  * @brief  Specifies a source clock.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @param  SrcClk: The command for the counter.
+  *   This parameter can be TMR16A_SYSCK or TMR16A_PRCK.
+  * @retval None
+  */
+void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+    assert_param(IS_TMR16A_SRCCLK(SrcClk));
+
+    tmp = T16Ax->CR;
+    /* Write Sorce clock into  register */
+    if (SrcClk == TMR16A_PRCK) {
+        /* Set T16AxCR<CLK>  Source clock to PRCK */
+        tmp |= CR_CLK_PRCK;
+    } else {
+        /* Clear T16AxCR<CLK> Source clock to SYSCK */
+        tmp &= CR_CLK_SYSCK;
+    }
+    T16Ax->CR = tmp;
+}
+
+/**
+  * @brief  Configure the flip-flop function.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @param FFStruct: The structure containing TMR16A flip-flop configuration
+  * @retval None
+  */
+void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(FFStruct));
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+    assert_param(IS_TMR16A_FLIPFLOP_CTRL(FFStruct->TMR16AFlipflopCtrl));
+    assert_param(IS_TMR16A_FLIPFLOP_TRG(FFStruct->TMR16AFlipflopReverseTrg));
+
+    /* Configure the flip-flop function of T16Ax */
+    tmp = T16Ax->CR;
+    tmp &= CR_FF_MASK;
+    tmp |= (FFStruct->TMR16AFlipflopCtrl | FFStruct->TMR16AFlipflopReverseTrg);
+    T16Ax->CR = tmp;
+}
+
+/**
+  * @brief  Change cycle value of T16Ax.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @param  Cycle: New cycle value, max 0xFFFF.
+  * @retval None
+  */
+void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle)
+{
+    /* Check the parameters */
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+    assert_param(IS_TMR16A_VALUE(Cycle));
+
+    /* Write cycle into RG1 */
+    T16Ax->RG = Cycle;
+}
+
+/**
+  * @brief  Get TMR16A capture value of T16Ax.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @retval Capture value of T16Ax
+  */
+uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax)
+{
+    uint16_t CapVal;
+
+    /* Check the parameters */
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+
+    CapVal = (uint16_t) T16Ax->CP;
+
+    return CapVal;
+}
+
+/**
+  * @brief  Enable or disable clock operation during debug HALT.
+  * @param  T16Ax: Select the TMR16A channel.
+  *   This parameter can be one of the following values:
+  *   TSB_T16A0, TSB_T16A1.
+  * @param  ClkState: Timer state in HALT mode.
+  *   This parameter can be TMR16A_RUNNING_IN_CORE_HALT or TMR16A_STOP_IN_CORE_HALT.
+  * @retval None
+  */
+void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState)
+{
+    /* Check the parameters */
+    assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
+    assert_param(IS_TMR16A_CLK_IN_CORE_HALT(ClkState));
+
+    if (ClkState == TMR16A_STOP_IN_CORE_HALT) {
+        /* Set T16AEN<T16AHALT> */
+        T16Ax->EN |= (uint32_t) TMR16A_STOP_IN_CORE_HALT;
+    } else {
+        /* Clear T16AEN<T16AHALT> */
+        T16Ax->EN &= ~(uint32_t) TMR16A_STOP_IN_CORE_HALT;
+    }
+}
+
+/** @} */
+/* End of group TMR16A_Exported_Functions */
+
+/** @} */
+/* End of group TMR16A */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_TMR16A_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,555 @@
+/**
+ *******************************************************************************
+ * @file    tmpm066_tmrb.c
+ * @brief   This file provides API functions for TMRB driver.
+ * @version V2.0.2.1
+ * @date    2015/10/09
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_tmrb.h"
+
+#if defined (__TMPM066_TMRB_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup TMRB
+  * @brief TMRB driver modules
+  * @{
+  */
+
+/** @defgroup TMRB_Private_Defines
+  * @{
+  */
+
+#define EN_TBEN_SET           ((uint32_t)0x00000080)
+#define EN_TBEN_CLEAR         ((uint32_t)0xFFFFFF7F)
+
+#define CR_TBSYNC_SET         ((uint32_t)0x00000020)
+#define CR_TBSYNC_CLEAR       ((uint32_t)0xFFFFFFDF)
+#define CR_TBWBF_SET          ((uint32_t)0x00000080)
+#define CR_TBWBF_CLEAR        ((uint32_t)0xFFFFFF7F)
+#define CR_CSSEL_SET          ((uint32_t)0x00000001)
+#define CR_CSSEL_CLEAR        ((uint32_t)0xFFFFFFFE)
+#define CR_TRGSEL_CLEAR       ((uint32_t)0xFFFFFFFD)
+#define CR_BIT6_CLEAR         ((uint32_t)0xFFFFFFBF)
+
+#define MOD_BIT7_CLEAR        ((uint32_t)0xFFFFFF7F)
+#define MOD_CLK_CLE_CLEAR     ((uint32_t)0xFFFFFFF0)
+#define MOD_TBCPM_CLEAR       ((uint32_t)0xFFFFFF8F)
+#define MOD_TBCP_SET          ((uint32_t)0x00000040)
+#define MOD_TBCP_CLEAR        ((uint32_t)0xFFFFFFBF)
+
+#define TB_ST_MASK            ((uint32_t)0x00000007)
+#define TB_IM_MASK            ((uint32_t)0x00000007)
+
+/** @} */
+/* End of group TMRB_Private_Defines */
+
+/** @defgroup TMRB_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group TMRB_Private_FunctionPrototypes */
+
+/** @defgroup TMRB_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group TMRB_Private_Functions */
+
+/** @defgroup TMRB_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.  
+  * @retval None
+  */
+void TMRB_Enable(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    /* Set TBxEN<TBEN> to enable TBx */
+    TBx->EN |= EN_TBEN_SET;
+}
+
+/**
+  * @brief  Disable the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @retval None
+  */
+void TMRB_Disable(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    /* Clear TBxEN<TBEN> to disable TBx */
+    TBx->EN &= EN_TBEN_CLEAR;
+}
+
+/**
+  * @brief  Start or stop counter of the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  Cmd: The command for the counter.
+  *   This parameter can be TMRB_RUN or TMRB_STOP.
+  * @retval None
+  */
+void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_CMD(Cmd));
+
+    /* Write command into RUN register */
+    TBx->RUN = Cmd;
+}
+
+/**
+  * @brief  Initialize the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  InitStruct: The structure containing basic TMRB configuration.
+  * @retval None
+  */
+void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_MODE(InitStruct->Mode));
+    if (InitStruct->Mode != 0U) {
+        assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv));
+    } else {
+        /* Do nothing */
+    }
+    assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming));
+    assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl));
+    assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming));
+    assert_param(IS_VALID_LEADINGTIMING(InitStruct->LeadingTiming, InitStruct->TrailingTiming));
+
+    /* Configure source clock for TBx */
+    tmp = TBx->MOD;
+    tmp &= MOD_BIT7_CLEAR;
+    tmp &= MOD_CLK_CLE_CLEAR;
+    if (InitStruct->Mode != 0U) {
+        /* Use internal clock, set the prescaler */
+        tmp |= InitStruct->ClkDiv;
+    } else {
+        /* Use external clock */
+        tmp |= InitStruct->Mode;
+    }
+    /* Set up-counter running mode */
+    tmp |= InitStruct->UpCntCtrl;
+    tmp |= MOD_TBCP_SET;
+    TBx->MOD = tmp;
+
+    /* Write leadingtiming into RG0 */
+    TBx->RG0 = InitStruct->LeadingTiming;
+
+    /* Write trailingtiminginto RG1 */
+    TBx->RG1 = InitStruct->TrailingTiming;
+}
+
+/**
+  * @brief  Configure the capture timing.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5.
+  * @param  CaptureTiming: Specify TMRB capture timing.
+  *    This parameter can be one of the following values:
+  *    TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_IN_RISING_FALLING, TMRB_CAPTURE_FF_RISING_FALLING.
+  * @retval None
+  */
+void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_CAP_PERIPH(TBx));
+    assert_param(IS_TMRB_CAPTURE_TIMING(CaptureTiming));
+
+    /* Configure capture timing */
+    tmp = TBx->MOD;
+    tmp &= MOD_BIT7_CLEAR;
+    tmp &= MOD_TBCPM_CLEAR;
+    tmp |= CaptureTiming;
+    tmp |= MOD_TBCP_SET;
+    TBx->MOD = tmp;
+}
+
+/**
+  * @brief  Configure the flip-flop function.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. 
+  * @param FFStruct: The structure containing TMRB flip-flop configuration
+  * @retval None
+  */
+void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(FFStruct));
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl));
+    assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg));
+
+    /* Configure the flip-flop function of TBx */
+    TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg);
+}
+
+/**
+  * @brief  Indicate what causes the interrupt.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @retval The interrupt factor of TBx.
+  */
+TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx)
+{
+    TMRB_INTFactor retval = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    retval.All = TBx->ST & TB_ST_MASK;
+    return retval;
+}
+
+/**
+  * @brief  Indicate what interrupt cause source be masked.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @retval The masked interrupt cause source of TBx.
+  */
+TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx)
+{
+    TMRB_INTMask retval = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    retval.All = TBx->IM & TB_IM_MASK;
+    return retval;
+}
+
+/**
+  * @brief  Mask some TMRB interrupts.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  INTMask: Select the mask of TMRB interrupt.
+  *   This parameter can be one of the following values:
+  *   TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADINGTIMING_INT, TMRB_MASK_MATCH_TRAILINGTIMING_INT,
+  *   or TMRB_MASK_OVERFLOW_INT.
+  * @retval None
+  */
+void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_INT_MASK(INTMask));
+
+    /* Mask the specified interrupt */
+    TBx->IM = INTMask;
+}
+
+/**
+  * @brief  Change leadingtiming value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  LeadingTiming: New leadingtiming value, max 0xFFFF.
+  * @retval None
+  */
+void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_VALUE(LeadingTiming));
+    assert_param(IS_VALID_LEADINGTIMING(LeadingTiming, TBx->RG1));
+
+    /* Write leadingtiming into RG0 */
+    TBx->RG0 = LeadingTiming;
+}
+
+/**
+  * @brief  Change trailingtiming value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  TrailingTiming: New trailingtiming value, max 0xFFFF.
+  * @retval None
+  */
+void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_VALUE(TrailingTiming));
+    assert_param(IS_VALID_LEADINGTIMING(TBx->RG0, TrailingTiming));
+
+    /* Write trailingtiming into RG1 */
+    TBx->RG1 = TrailingTiming;
+}
+
+/**
+  * @brief  Get TMRB register value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param Reg: Select the timer register to read.
+  *   This parameter can be: TMRB_REG_0 or TMRB_REG_1.
+  * @retval Register value of TBx
+  */
+uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_REG(Reg));
+
+    return Reg ? (uint16_t) TBx->RG1 : (uint16_t) TBx->RG0;
+}
+
+/**
+  * @brief  Get up-counter value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @retval Up-counter value of TBx
+  */
+uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    /* Return up-counter value */
+    return (uint16_t) TBx->UC;
+}
+
+/**
+  * @brief  Get TMRB capture value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5.
+  * @param  CapReg: Select the capture register to read.
+  *   This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1.
+  * @retval Capture value of TBx
+  */
+uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_CAP_PERIPH(TBx));
+    assert_param(IS_TMRB_CAPTURE_REG(CapReg));
+
+    return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0;
+}
+
+/**
+  * @brief  Capture counter by software and take them into capture register 0.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5.
+  * @retval None
+  */
+void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_CAP_PERIPH(TBx));
+
+    /* Set software capture */
+    tmp = TBx->MOD;
+    tmp &= MOD_BIT7_CLEAR;
+    TBx->MOD = tmp & MOD_TBCP_CLEAR;
+}
+
+/**
+  * @brief  Enable or disable the synchronous mode of specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  NewState: New state of TBx synchronous mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_SYNC_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = TBx->CR;
+    tmp &= CR_BIT6_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set TBxCR<TBSYNC> to make TBx running in synchronous mode */
+        TBx->CR = tmp | CR_TBSYNC_SET;
+    } else {
+        /* Clear TBxCR<TBSYNC> to make TBx running in individual mode */
+        TBx->CR = tmp & CR_TBSYNC_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable double buffer of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. 
+  * @param  NewState: New state of TBx double buffer.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = TBx->CR;
+    tmp &= CR_BIT6_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set TBxCR<TBWBF> to enable TBx double buffer */
+        TBx->CR = tmp | CR_TBWBF_SET;
+    } else {
+        /* Clear TBxCR<TBWBF> to disable TBx double buffer */
+        TBx->CR = tmp & CR_TBWBF_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable external trigger to start count and set the active edge.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. 
+  * @param  NewState: New state of external trigger.
+  *   This parameter can be ENABLE or DISABLE.
+  * @param  TrgMode: Active edge of the external trigger signal.
+  *   This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING.
+  * @retval None
+  */
+void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_TMRB_TRG_EDGE(TrgMode));
+
+    tmp = TBx->CR;
+    tmp &= CR_BIT6_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set TBxCR<CSSEL> to choose external trigger */
+        tmp |= CR_CSSEL_SET;
+    } else {
+        /* Clear TBxCR<CSSEL> to choose software start */
+        tmp &= CR_CSSEL_CLEAR;
+    }
+
+    /* external trigger selection */
+    tmp &= CR_TRGSEL_CLEAR;
+    tmp |= (uint32_t) TrgMode;
+    TBx->CR = tmp;
+}
+
+/**
+  * @brief  Enable or disable clock operation during debug HALT.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. 
+  * @param  ClkState: Timer state in HALT mode.
+  *   This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT.
+  * @retval None
+  */
+void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState));
+
+    if (ClkState == TMRB_STOP_IN_CORE_HALT) {
+        /* Set TBxEN<TBHALT> */
+        TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT;
+    } else {
+        /* Clear TBxEN<TBHALT> */
+        TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT;
+    }
+}
+
+/**
+  * @brief  Enable or disable DMA request.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, 
+  *   TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. 
+  * @param  NewState: New state of DMA request.
+  *   This parameter can be ENABLE or DISABLE.
+  * @param  DMAReq: DMA request.
+  *   This parameter can be TMRB_DMA_REQ_CMP_MATCH, TMRB_DMA_REQ_CAPTURE_1 or TMRB_DMA_REQ_CAPTURE_0.
+  * @retval None
+  */
+void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_TMRB_DMA_REQ(DMAReq));
+
+    if (NewState == ENABLE) {
+        /* set TBxDMA<TBDMAENn>(n can be 0,1,2) */
+        TBx->DMA |= (uint32_t) DMAReq;
+    } else {
+        /* clear TBxDMA<TBDMAENn>(n can be 0,1,2) */
+        TBx->DMA &= ~((uint32_t) DMAReq);
+    }
+}
+
+
+/** @} */
+/* End of group TMRB_Exported_Functions */
+
+/** @} */
+/* End of group TMRB */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_TMRB_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,1198 @@
+
+/**
+ *******************************************************************************
+ * @file    tmpm066_uart.c
+ * @brief   This file provides API functions for UART driver.
+ * @version V2.0.2.1
+ * @date    2015/09/10
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm066_uart.h"
+
+#if defined(__TMPM066_UART_H)
+/** @addtogroup TX00_Periph_Driver
+  * @{
+  */
+
+/** @defgroup UART
+  * @brief UART driver modules
+  * @{
+  */
+
+/** @defgroup UART_Private_Defines
+  * @{
+  */
+#define EN_SIOE_SET            ((uint32_t)0x00000001)
+#define EN_SIOE_CLEAR          ((uint32_t)0xFFFFFFFE)
+#define EN_BRCKSEL_MASK        ((uint32_t)0xFFFFFFFD)
+
+#define CR_PARITY_MASK         ((uint32_t)0x0000779F)
+#define CR_ERROR_MASK          ((uint32_t)0x0000001C)
+#define CR_OERR_FLAG           ((uint8_t)0x10)
+#define CR_PERR_FLAG           ((uint8_t)0x08)
+#define CR_FERR_FLAG           ((uint8_t)0x04)
+#define CR_IOC_MASK            ((uint32_t)0x000077FE)
+#define CR_SCLKS_MASK          ((uint32_t)0x000077FD)
+#define CR_TIDLE_MASK          ((uint32_t)0x000074FF)
+#define CR_TXDEMP_MASK         ((uint32_t)0x000073FF)
+#define CR_EHOLD_MASK          ((uint32_t)0x000007FF)
+
+#define MOD0_CTSE_MASK         ((uint32_t)0x000000BF)
+#define MOD0_RXE_CLEAR         ((uint32_t)0x000000DF)
+#define MOD0_WU_SET            ((uint32_t)0x00000010)
+#define MOD0_WU_CLEAR          ((uint32_t)0x000000EF)
+#define MOD0_SM_MASK           ((uint32_t)0x000000F3)
+#define MOD0_SC_MASK           ((uint32_t)0x000000FC)
+#define MOD0_SC_BRG            ((uint32_t)0x00000001)
+
+#define MOD1_I2SC_SET          ((uint32_t)0x00000080)
+#define MOD1_I2SC_CLEAR        ((uint32_t)0x0000007F)
+#define MOD1_TXE_CLEAR         ((uint32_t)0x000000EF)
+#define MOD1_CLEAR             ((uint32_t)0x000000FE)
+#define MOD1_FDPX_CLEAR        ((uint32_t)0x0000009F)
+#define MOD1_SINT_MASK         ((uint32_t)0x000000F1)
+
+#define MOD2_BUF_MASK          ((uint32_t)0x000000C0)
+#define MOD2_TBEMP_FLAG        ((uint8_t)0x80)
+#define MOD2_RBFLL_FLAG        ((uint8_t)0x40)
+#define MOD2_SBLEN_MASK        ((uint32_t)0x000000EF)
+#define MOD2_DRCHG_MASK        ((uint32_t)0x000000F7)
+#define MOD2_WBUF_SET          ((uint32_t)0x00000004)
+#define MOD2_WBUF_MASK         ((uint32_t)0x000000FB)
+#define MOD2_SWRST_MASK        ((uint32_t)0x000000FC)
+#define MOD2_SWRST_CMD1        ((uint32_t)0x00000002)
+#define MOD2_SWRST_CMD2        ((uint32_t)0x00000001)
+
+#define BRCR_BRADDE_SET        ((uint32_t)0x00000040)
+#define BRCR_BRCK_MASK         ((uint32_t)0x000000CF)
+#define BRCR_BRS_MASK          ((uint32_t)0x000000F0)
+#define BRCR_CLEAR             ((uint32_t)0x0000007F)
+
+#define BRADD_BRK_MASK         ((uint32_t)0x00000000)
+
+#define FCNF_BIT567_CLEAR      ((uint32_t)0x0000001F)
+#define FCNF_RFST_CLEAR        ((uint32_t)0x000000EF)
+#define FCNF_TFIE_SET          ((uint32_t)0x00000008)
+#define FCNF_TFIE_CLEAR        ((uint32_t)0x00000017)
+#define FCNF_RFIE_SET          ((uint32_t)0x00000004)
+#define FCNF_RFIE_CLEAR        ((uint32_t)0x0000001B)
+#define FCNF_RXTXCNT_SET       ((uint32_t)0x00000002)
+#define FCNF_RXTXCNT_CLEAR     ((uint32_t)0x0000001D)
+#define FCNF_CNFG_SET          ((uint32_t)0x00000001)
+#define FCNF_CNFG_CLEAR        ((uint32_t)0x0000001E)
+
+#define RFC_4B_RIL_CLEAR       ((uint32_t)0x000000FC)
+#define TFC_4B_TIL_CLEAR       ((uint32_t)0x000001FC)
+#define RFC_RFIS_CLEAR         ((uint32_t)0x000000BF)
+#define TFC_TFIS_CLEAR         ((uint32_t)0x000001BF)
+#define TRFC_TRFCS_SET         ((uint32_t)0x00000080)
+#define TFC_TBCLR_SET          ((uint32_t)0x00000100)
+
+#define TRXST_TUR_ROR_MASK     ((uint32_t)0x00000080)
+#define TRXST_4B_TRLVL_MASK    ((uint32_t)0x00000007)
+
+#define DMA_EN0_SET              ((uint32_t)0x00000001)
+#define DMA_EN0_CLEAR            ((uint32_t)0x00000002)
+
+#define DMA_EN1_SET              ((uint32_t)0x00000002)
+#define DMA_EN1_CLEAR            ((uint32_t)0x00000001)
+
+/** @} */
+/* End of group UART_Private_Defines */
+
+/** @defgroup UART_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group UART_Private_FunctionPrototypes */
+
+/** @defgroup UART_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group UART_Private_Functions */
+
+/** @defgroup UART_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_Enable(TSB_SC_TypeDef * UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    /* Set SCxEN<SIOE> to enable UARTx */
+    UARTx->EN |= EN_SIOE_SET;
+}
+
+/**
+  * @brief  Disable the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_Disable(TSB_SC_TypeDef * UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    /* Clear SCxEN<SIOE> to disable UARTx */
+    UARTx->EN &= EN_SIOE_CLEAR;
+}
+
+/**
+  * @brief  Indicate whether the transfer buffer is full or not.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  Direction: Select the direction of transfer.
+  *   This parameter can be UART_RX or UART_TX.
+  * @retval The transfer buffer status.
+  *   The value returned can be one of the followings:
+  *   BUSY or DONE.
+  */
+WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction)
+{
+    uint8_t tmp = 0U;
+    WorkState retval = BUSY;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TRX(Direction));
+
+    tmp = ((uint8_t) (UARTx->MOD2 & MOD2_BUF_MASK));
+    switch (Direction) {
+    case UART_TX:
+        if ((tmp & MOD2_TBEMP_FLAG) == MOD2_TBEMP_FLAG) {
+            /* Return Tx buffer empty if the flag is set */
+            retval = DONE;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    case UART_RX:
+        if ((tmp & MOD2_RBFLL_FLAG) == MOD2_RBFLL_FLAG) {
+            /* Return Rx buffer full if the flag is set */
+            retval = DONE;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    default:                   /* Do nothing */
+        break;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Reset the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_SWReset(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Write software-reset command */
+    tmp = UARTx->MOD2;
+    tmp &= MOD2_SWRST_MASK;
+    UARTx->MOD2 = tmp | MOD2_SWRST_CMD1;
+    tmp &= MOD2_SWRST_MASK;
+    UARTx->MOD2 = tmp | MOD2_SWRST_CMD2;
+}
+
+/**
+  * @brief  Initialize the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  InitStruct: The structure containing basic UART configuration.
+  * @retval None
+  * @note UART_SetInputClock need to use before UART_Init.
+  */
+void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct)
+{
+    uint32_t T0 = 0U;
+    uint32_t T = 0U;
+    uint32_t t = 0U;
+    uint32_t N = 0U;
+    uint32_t K = 0U;
+    uint32_t tmp = 0U;
+    uint32_t divider = 0U;
+    const uint32_t a = 1U;
+    const uint32_t b = 4U;
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_BAUDRATE(InitStruct->BaudRate));
+    assert_param(IS_UART_DATA_BITS(InitStruct->DataBits));
+    assert_param(IS_UART_STOPBITS(InitStruct->StopBits));
+    assert_param(IS_UART_PARITY(InitStruct->Parity));
+    assert_param(IS_UART_MODE(InitStruct->Mode));
+    assert_param(IS_UART_FLOW_CONTROL(InitStruct->FlowCtrl));
+
+    /* Configure the flow control */
+    tmp = UARTx->MOD0;
+    tmp &= MOD0_SM_MASK;
+    tmp &= MOD0_CTSE_MASK;
+    tmp &= MOD0_SC_MASK;
+    tmp |= (InitStruct->DataBits | InitStruct->FlowCtrl);
+    /* Use baud rate generator */
+    tmp |= MOD0_SC_BRG;
+    UARTx->MOD0 = tmp;
+
+    /* Set the stop bit */
+    tmp = UARTx->MOD2;
+    tmp &= MOD2_SBLEN_MASK;
+    tmp |= InitStruct->StopBits;
+    tmp |= MOD2_WBUF_SET;
+    UARTx->MOD2 = tmp;
+
+    /* Enable or disable parity check */
+    tmp = UARTx->CR;
+    tmp &= CR_PARITY_MASK;
+    tmp |= InitStruct->Parity;
+    UARTx->CR = tmp;
+
+    /* Get the peripheral I/O clock frequency */
+    SystemCoreClockUpdate();
+    T0 = SystemCoreClock / (a << ((TSB_CG->SYSCR >> 8U) & 0xFU));
+    if (UARTx->EN & (0x1U << 1)) {
+        T0 *= 2U;
+    } else {
+        /* Do nothing */
+    }
+    /* Baud rate setting */
+    while ((divider < 200U) || (divider > 1600U)) {
+        if (t == 0U) {
+            T = 2U;
+        } else {
+            if (T < 128U) {
+                T = T * b;
+            } else {
+                /* Do nothing */
+            }
+        }
+        divider = (100U * (T0 >> 4U)) / (InitStruct->BaudRate * T);
+        t++;
+    }
+    N = divider / 100U;
+    /* K value<BRK> setting */
+    if ((divider - (N * 100U)) == 0) {
+        /* Do nothing */
+    } else {
+        K = (16U * (100U - (divider - (N * 100U)))) / 100U;
+        if (K < 1U) {
+            K = 1U;
+        } else {
+            /* Do nothing */
+        }
+        tmp = UARTx->BRADD;
+        tmp &= BRADD_BRK_MASK;
+        tmp |= (K & 0x0FU);
+        UARTx->BRADD = tmp;
+    }
+    /* N value<BRS>, <BRCK>, <BRADDE> setting */
+    /*  */
+    tmp = UARTx->BRCR;
+    if ((divider - (N * 100U)) == 0) {
+        tmp &= ~BRCR_BRADDE_SET;
+    } else {
+        tmp |= BRCR_BRADDE_SET;
+    }
+    tmp &= BRCR_BRCK_MASK;
+    tmp &= BRCR_BRS_MASK;
+    tmp |= (((t - 1U) & 3U) << 4U);
+    tmp |= (N & 0x0FU);
+    tmp &= BRCR_CLEAR;
+    UARTx->BRCR = tmp;
+
+    tmp = UARTx->MOD1;
+    /* Enable or disable transmission or reception */
+    switch (InitStruct->Mode) {
+    case UART_ENABLE_RX:
+        UARTx->MOD0 |= InitStruct->Mode;
+        tmp &= MOD1_TXE_CLEAR;
+        break;
+    case UART_ENABLE_TX:
+        tmp |= InitStruct->Mode;
+        UARTx->MOD0 &= MOD0_RXE_CLEAR;
+        break;
+    default:
+        UARTx->MOD0 |= UART_ENABLE_RX;
+        tmp |= UART_ENABLE_TX;
+        break;
+    }
+    tmp &= MOD1_CLEAR;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Get received data of the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval The received data
+  */
+uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t retval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Return received data */
+    retval = (UARTx->CR & 0x80U) << 1U;
+    retval = retval | (UARTx->BUF & 0xFFU);
+
+    return retval;
+}
+
+/**
+  * @brief  Set data to be sent and start transmitting via the specified
+      UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  Data: the data to be sent.
+  * @retval None
+  */
+void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data)
+{
+    uint32_t tmp = UARTx->MOD0 & 0x7FU;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_DATA(Data));
+
+    /* Write MSB to SCxMOD0<TB8> at first if in 9-bit mode */
+    tmp |= ((Data & 0x100U) >> 1U);
+    UARTx->MOD0 = tmp;
+
+    UARTx->BUF = Data & 0xFFU;
+}
+
+/**
+  * @brief  Initialize the specified UART channel in default configuration.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_DefaultConfig(TSB_SC_TypeDef * UARTx)
+{
+    UART_InitTypeDef uartdefault;
+    uartdefault.BaudRate = 115200U;
+    uartdefault.DataBits = UART_DATA_BITS_8;
+    uartdefault.StopBits = UART_STOP_BITS_1;
+    uartdefault.Parity = UART_NO_PARITY;
+    uartdefault.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
+    uartdefault.FlowCtrl = UART_NONE_FLOW_CTRL;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Enable the selected UART channel */
+    UART_Enable(UARTx);
+    /* Select baud rate generator as UART source clcok */
+    /* Set baud rate as 115200bps */
+    /* Select 8-bit UART mode */
+    /* Select 1-bit stop */
+    /* No parity check */
+    /* No flow control */
+    /* Enable both transmission and reception */
+    UART_Init(UARTx, &uartdefault);
+}
+
+/**
+  * @brief  Indicate UART transfer error.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval The error flag.
+  *   The value returned can be one of the followings:
+  *   UART_NO_ERR, UART_OVERRUN, UART_PARITY_ERR, UART_FRAMING_ERR or UART_ERRS.
+  */
+UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx)
+{
+    uint8_t tmp = 0U;
+    UART_Err retval = UART_NO_ERR;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = ((uint8_t) (UARTx->CR & CR_ERROR_MASK));
+    switch (tmp) {
+    case CR_OERR_FLAG:         /* Check overrun flag */
+        retval = UART_OVERRUN;
+        break;
+    case CR_PERR_FLAG:         /* Check parity flag */
+        retval = UART_PARITY_ERR;
+        break;
+    case CR_FERR_FLAG:         /* Check framing flag */
+        retval = UART_FRAMING_ERR;
+        break;
+    default:
+        if (tmp != 0U) {
+            /* more than one error */
+            retval = UART_ERRS;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    }
+    return retval;
+}
+
+/**
+  * @brief  Enable or disable the wake-up function in 9-bit UART mode
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of this function.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set SCxMOD0<WU> to enable wake-up function */
+        UARTx->MOD0 |= MOD0_WU_SET;
+    } else {
+        /* Clear SCxMOD0<WU> to disable wake-up function */
+        UARTx->MOD0 &= MOD0_WU_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified UART channel when system is in IDLE
+      mode. 
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of the UART channel in IDLE.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->MOD1;
+    if (NewState == ENABLE) {
+        /* Set SCxMOD1<I2SC> to enable UARTx running in IDLE */
+        tmp |= MOD1_I2SC_SET;
+    } else {
+        /* Clear SCxMOD1<I2SC> to disable UARTx running in IDLE */
+        tmp &= MOD1_I2SC_CLEAR;
+    }
+    tmp &= MOD1_CLEAR;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Selects input clock for prescaler.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  clock: Selects input clock for prescaler as PhiT0/2 or PhiT0.
+  *   This parameter can be: 
+  *         0: PhiT0/2 
+  *         1: PhiT0
+  * @retval None
+  * @note UART_SetInputClock need to use before UART_Init.
+  */
+void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock)
+{
+    uint32_t tmp = 0U;
+
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_CLOCK(clock));
+
+    tmp = UARTx->EN;
+    tmp &= EN_BRCKSEL_MASK;
+    tmp |= (uint32_t) (clock << 1U);
+    UARTx->EN = tmp;
+}
+
+/**
+  * @brief  Enable or disable the FIFO of specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of the UART FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<CNFG> to enable UARTx FIFO */
+        UARTx->FCNF = tmp | FCNF_CNFG_SET;
+    } else {
+        /* Clear SCxFCNF<CNFG> to disable UARTx FIFO */
+        UARTx->FCNF = tmp & FCNF_CNFG_CLEAR;
+    }
+}
+
+/**
+  * @brief  Transfer mode setting.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  TransferMode: Transfer mode.
+  *   This parameter can be: UART_TRANSFER_PROHIBIT, UART_TRANSFER_HALFDPX_RX,
+  *   UART_TRANSFER_HALFDPX_TX or UART_TRANSFER_FULLDPX.
+  * @retval None
+  */
+void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TRANSFER_MODE(TransferMode));
+
+    tmp = UARTx->MOD1;
+    tmp &= MOD1_FDPX_CLEAR;
+    tmp |= TransferMode;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Controls automatic disabling of transmission and reception.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  TRxAutoDisable: Disabling transmission and reception or not.
+  *   This parameter can be: UART_RXTXCNT_NONE or UART_RXTXCNT_AUTODISABLE .
+  * @retval None
+  */
+void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_TRX_AUTODISABLE(TRxAutoDisable));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (TRxAutoDisable == UART_RXTXCNT_AUTODISABLE) {
+        /* Set SCxFCNF<RXCXCNT> to automatic disabling of transmission and reception */
+        UARTx->FCNF = tmp | FCNF_RXTXCNT_SET;
+    } else {
+        /* Clear SCxFCNF<RXCXCNT> to do none */
+        UARTx->FCNF = tmp & FCNF_RXTXCNT_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable receive interrupt for receive FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of receive interrupt for receive FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<RFIE> to enable receive FIFO interrupt */
+        UARTx->FCNF = tmp | FCNF_RFIE_SET;
+    } else {
+        /* Clear SCxFCNF<RFIE> to disable receive FIFO interrupt */
+        UARTx->FCNF = tmp & FCNF_RFIE_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable transmit interrupt for transmit FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of transmit interrupt for transmit FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<TFIE> to enable transmit FIFO interrupt */
+        UARTx->FCNF = tmp | FCNF_TFIE_SET;
+    } else {
+        /* Clear SCxFCNF<TFIE> to disable transmit FIFO interrupt */
+        UARTx->FCNF = tmp & FCNF_TFIE_CLEAR;
+    }
+}
+
+/**
+  * @brief  Bytes used in receive FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  BytesUsed: Bytes used in receive FIFO.
+  *   This parameter can be: UART_RXFIFO_MAX or UART_RXFIFO_RXFLEVEL.
+  * @retval None
+  */
+void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_RXFIFO_BYTESUSED(BytesUsed));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    tmp &= FCNF_RFST_CLEAR;
+    tmp |= BytesUsed;
+    UARTx->FCNF = tmp;
+}
+
+/**
+  * @brief  Receive FIFO fill level to generate receive interrupts.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1. 
+  * @param  RxFIFOLevel: Receive FIFO fill level. 
+  *   This parameter can be one of the following values:
+  *   UART_RXFIFO4B_FLEVLE_4_2B, UART_RXFIFO4B_FLEVLE_1_1B,
+  *   UART_RXFIFO4B_FLEVLE_2_2B or UART_RXFIFO4B_FLEVLE_3_1B.
+  * @retval None
+  */
+void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_RXFIFO4B_FLEVLE(RxFIFOLevel));
+
+    tmp = UARTx->RFC;
+    tmp &= RFC_4B_RIL_CLEAR;
+    tmp |= RxFIFOLevel;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Select RX interrupt generation condition.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  RxINTCondition: RX interrupt generation condition.
+  *   This parameter can be: UART_RFIS_REACH_FLEVEL or UART_RFIS_REACH_EXCEED_FLEVEL.
+  * @retval None
+  */
+void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_RFIS_CONDITION(RxINTCondition));
+
+    tmp = UARTx->RFC;
+    tmp &= RFC_RFIS_CLEAR;
+    tmp |= RxINTCondition;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Receive FIFO clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RFC;
+    tmp |= TRFC_TRFCS_SET;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Transmit FIFO fill level to generate transmit interrupts.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  TxFIFOLevel: Transmit FIFO fill level.
+  *   This parameter can be one of the following values:
+  *   UART_TXFIFO4B_FLEVLE_0_0B, UART_TXFIFO4B_FLEVLE_1_1B,
+  *   UART_TXFIFO4B_FLEVLE_2_0B or UART_TXFIFO4B_FLEVLE_3_1B.
+  * @retval None
+  */
+void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TXFIFO4B_FLEVLE(TxFIFOLevel));
+
+
+    tmp = UARTx->TFC;
+    tmp &= TFC_4B_TIL_CLEAR;
+    tmp |= TxFIFOLevel;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Select TX interrupt generation condition.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  TxINTCondition: TX interrupt generation condition.
+  *   This parameter can be: UART_TFIS_REACH_FLEVEL or UART_TFIS_REACH_NOREACH_FLEVEL.
+  * @retval None
+  */
+void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_TFIS_CONDITION(TxINTCondition));
+
+    tmp = UARTx->TFC;
+    tmp &= TFC_TFIS_CLEAR;
+    tmp |= TxINTCondition;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Transmit FIFO clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TFC;
+    tmp |= TRFC_TRFCS_SET;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Transmit buffer clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval None
+  */
+void UART_TxBufferClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TFC;
+    tmp |= TFC_TBCLR_SET;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Status of receive FIFO fill level.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval Receive FIFO fill level status.
+  */
+uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RST;
+    tmp &= TRXST_4B_TRLVL_MASK;
+    /* Return the value */
+    return tmp;
+}
+
+/**
+  * @brief  Receive FIFO overrun.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval Receive FIFO overrun status.
+  */
+uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    uint32_t regval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RST;
+    if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) {
+        regval = UART_RXFIFO_OVERRUN;
+    } else {
+        /* Do nothing */
+    }
+    /* Return the value */
+    return regval;
+}
+
+/**
+  * @brief  Status of transmit FIFO fill level.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval Transmit FIFO fill level status.
+  */
+uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TST;
+    tmp &= TRXST_4B_TRLVL_MASK;
+    /* Return the value */
+    return tmp;
+}
+
+/**
+  * @brief  Transmit FIFO under run.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @retval Transmit FIFO under run status.
+  */
+uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    uint32_t regval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TST;
+    if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) {
+        regval = UART_TXFIFO_UNDERRUN;
+    } else {
+        /* Do nothing */
+    }
+    /* Return the value */
+    return regval;
+}
+
+/**
+  * @brief  Enable or disable the specified UART channel DMA Request By 
+      receive interrupt INTRX
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of the UART channel in IDLE.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set SCxDMA<DMAEN1> to enable UARTx DMA Request */
+        UARTx->DMA |= DMA_EN1_SET;
+    } else {
+        /* Clear SCxDMA<DMAEN1> to disable UARTx DMA Request */
+        UARTx->DMA &= DMA_EN1_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified UART channel DMA Request By 
+      receive interrupt INTTX
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0,UART1.
+  * @param  NewState: New state of the UART channel in IDLE.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set SCxDMA<DMAEN0> to enable UARTx DMA Request */
+        UARTx->DMA |= DMA_EN0_SET;
+    } else {
+        /* Clear SCxDMA<DMAEN0> to disable UARTx DMA Request */
+        UARTx->DMA &= DMA_EN0_CLEAR;
+    }
+}
+
+/**
+  * @brief  Selects input clock for prescaler.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @param  clock: Selects input clock for prescaler as PhiT0/2 or PhiT0.
+  *   This parameter can be: 
+  *   SIO_CLOCK_T0_HALF (PhiT0/2)or SIO_CLOCK_T0(PhiT0)
+  * @retval None
+  * @note SIO_SetInputClock need to use before SIO_Init.
+  */
+void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock)
+{
+    uint32_t tmp = 0U;
+    assert_param(IS_SIO_PERIPH(SIOx));
+    assert_param(IS_SIO_CLOCK(Clock));
+
+    tmp = SIOx->EN;
+    tmp &= EN_BRCKSEL_MASK;
+    tmp |= Clock;
+    SIOx->EN = tmp;
+}
+
+/**
+  * @brief  Enable the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @retval None
+  */
+void SIO_Enable(TSB_SC_TypeDef * SIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+    /* Set SCxEN<SIOE> to enable SIOx */
+    SIOx->EN |= EN_SIOE_SET;
+}
+
+/**
+  * @brief  Disable the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @retval None
+  */
+void SIO_Disable(TSB_SC_TypeDef * SIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+    /* Clear SCxEN<SIOE> to disable SIOx */
+    SIOx->EN &= EN_SIOE_CLEAR;
+}
+
+/**
+  * @brief  Get received data of the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @retval The received data
+  */
+uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx)
+{
+    uint8_t retval = 0U;
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+
+    /* Return received data */
+    retval = (uint8_t) SIOx->BUF;
+
+    return retval;
+}
+
+/**
+  * @brief  Set data to be sent and start transmitting via the specified
+      SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @param  Data: the data to be sent.
+  * @retval None
+  */
+void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+
+    SIOx->BUF = (uint32_t) Data;
+}
+
+/**
+  * @brief  Initialize the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0,SIO1.
+  * @param  IOClkSel: Selecting clock. 
+  *   This parameter can be one of the following values:  
+  *   SIO_CLK_SCLKOUTPUT or SIO_CLK_SCLKINPUT.  
+  * @param  InitStruct: The structure containing basic SIO configuration.  
+  * @retval None
+  * @note SIO_SetInputClock need to use before SIO_Init.
+  */
+void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_SIO_PERIPH(SIOx));
+    assert_param(IS_SIO_CLK_SEL(IOClkSel));
+    assert_param(IS_SIO_SCLKS_TRXD(InitStruct->InputClkEdge));
+    assert_param(IS_SIO_TIDLE_LEVEL(InitStruct->TIDLE));
+    assert_param(IS_SIO_TRANSFER_MODE(InitStruct->TransferMode));
+    assert_param(IS_SIO_TRANS_DIR(InitStruct->TransferDir));
+    assert_param(IS_SIO_MODE(InitStruct->Mode));
+    assert_param(IS_SIO_WBUF_SET(InitStruct->DoubleBuffer));
+    if (IOClkSel == SIO_CLK_SCLKINPUT) {
+        /* Only used for SCLK pin input mode */
+        assert_param(IS_SIO_TXDEMP_LEVEL(InitStruct->TXDEMP));
+        assert_param(IS_SIO_EHOLD_TIME(InitStruct->EHOLDTime));
+    } else {
+        /* Only used for baud rate generator(SCLK pin output) mode */
+        assert_param(IS_SIO_SINT_TIME(InitStruct->IntervalTime));
+        assert_param(IS_SIO_BR_CLOCK(InitStruct->BaudRateClock));
+        assert_param(IS_SIO_BR_DIVIDER(InitStruct->Divider));
+    }
+
+    /* Configure the transfer mode to I/O interface mode */
+    tmp = SIOx->MOD0;
+    tmp &= MOD0_SM_MASK;
+    SIOx->MOD0 = tmp;
+
+    /* Selecting the clock(SCLK input or output),input clock edge
+       for I/O interface mode */
+    tmp = SIOx->CR;
+    tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK);
+    tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE);
+
+    /* Set status of TXDx pin when an under run error is occured
+       and The last bit hold time of TXDx pin in SCLK input mode */
+    if (IOClkSel == SIO_CLK_SCLKINPUT) {
+        tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK);
+        tmp |= (InitStruct->TXDEMP | InitStruct->EHOLDTime);
+    } else {
+        /* Do nothing */
+    }
+    SIOx->CR = tmp;
+
+    /* Set the transfer mode and interval time */
+    tmp = SIOx->MOD1;
+    tmp &= MOD1_FDPX_CLEAR;
+    tmp |= InitStruct->TransferMode;
+    /* Set the interval time that valid only for SCLK output mode and double 
+       buffer is enabled */
+    if ((IOClkSel == SIO_CLK_SCLKOUTPUT) && (InitStruct->DoubleBuffer == SIO_WBUF_ENABLE)) {
+        tmp &= MOD1_SINT_MASK;
+        tmp |= InitStruct->IntervalTime;
+    } else {
+        /* Do nothing */
+    }
+    tmp &= MOD1_CLEAR;
+    SIOx->MOD1 = tmp;
+
+    /* Set the transfer direction and double buffer */
+    tmp = SIOx->MOD2;
+    tmp &= MOD2_DRCHG_MASK;
+    tmp &= MOD2_WBUF_MASK;
+    tmp |= (InitStruct->TransferDir | InitStruct->DoubleBuffer);
+    SIOx->MOD2 = tmp;
+
+    /* Select the input clock for baud rate generator and setting
+       Division ratio "N"  */
+    tmp = SIOx->BRCR;
+    if (IOClkSel == SIO_CLK_SCLKOUTPUT) {
+        tmp &= BRCR_BRCK_MASK;
+        tmp &= BRCR_BRS_MASK;
+        tmp |= (InitStruct->BaudRateClock | InitStruct->Divider);
+    } else {
+        /* Do nothing */
+    }
+    tmp &= BRCR_CLEAR;
+    SIOx->BRCR = tmp;
+
+    /* Enable or disable transmission or reception and both */
+    tmp = SIOx->MOD1;
+    switch (InitStruct->Mode) {
+    case SIO_ENABLE_RX:
+        SIOx->MOD0 |= InitStruct->Mode;
+        tmp &= MOD1_TXE_CLEAR;
+        break;
+    case SIO_ENABLE_TX:
+        tmp |= InitStruct->Mode;
+        SIOx->MOD0 &= MOD0_RXE_CLEAR;
+        break;
+    default:
+        SIOx->MOD0 |= SIO_ENABLE_RX;
+        tmp |= SIO_ENABLE_TX;
+        break;
+    }
+    tmp &= MOD1_CLEAR;
+    SIOx->MOD1 = tmp;
+}
+
+/** @} */
+/* End of group UART_Exported_Functions */
+
+/** @} */
+/* End of group UART */
+
+/** @} */
+/* End of group TX00_Periph_Driver */
+
+#endif                          /* defined(__TMPM066_UART_H)) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SERIAL_0 = 0,
+    SERIAL_1,
+    INVALID_SERIAL = (int)NC
+} UARTName;
+
+typedef enum {
+    ADC_A0 = 0,
+    ADC_A1,
+    ADC_A2,
+    ADC_A3,
+    ADC_A4,
+    ADC_A5,
+    ADC_A6,
+    ADC_A7,
+    INVALID_ADC = (int)NC
+} ADCName;
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1,
+    INVALID_I2C = (int)NC
+} I2CName;
+
+typedef enum {
+    PWM_0 = 0,
+    PWM_1,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    INVALID_PWM = (int)NC
+} PWMName;
+
+typedef enum {
+    GPIO_IRQ_0 = 0,
+    GPIO_IRQ_1,
+    GPIO_IRQ_2,
+    GPIO_IRQ_3,
+    GPIO_IRQ_4,
+    GPIO_IRQ_5,
+    INVALID_GPIO_IRQ = (int)NC
+} GPIO_IRQName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        SERIAL_0
+
+#define MBED_UART0        PC2, PC3
+#define MBED_UART1        PE2, PE1
+#define MBED_UARTUSB      USBTX, USBRX
+
+#define MBED_I2C0         PC1, PC0
+#define MBED_I2C1         PG1, PG0
+
+#define MBED_ANALOGIN0    A0
+#define MBED_ANALOGIN1    A1
+#define MBED_ANALOGIN2    A2
+#define MBED_ANALOGIN3    A3
+#define MBED_ANALOGIN4    A4
+#define MBED_ANALOGIN5    A5
+
+#define MBED_PWMOUT0      PD1
+#define MBED_PWMOUT1      PD2
+#define MBED_PWMOUT2      PD3
+#define MBED_PWMOUT3      PF4
+#define MBED_PWMOUT4      PF5
+#define MBED_PWMOUT5      PJ0
+#define MBED_PWMOUT6      PJ1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_PORT(X)         (((uint32_t)(X) >> 3) & 0xF)
+#define PIN_POS(X)          ((uint32_t)(X) & 0x7)
+
+// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
+#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
+#define PIN_FUNC(X)         (((X) & 0xffff0000) >> 16)
+#define PIN_DIR(X)          ((X) & 0xffff)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT,
+    PIN_INOUT
+} PinDirection;
+
+typedef enum {
+    // TMPM066 Pin Names
+    PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PB0 = 1 << 3, PB1, PB2, PB3,
+    PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5,
+    PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5,
+    PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5,
+    PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PG0 = 6 << 3, PG1,
+    PH0 = 7 << 3, PH1, PH2, PH3,
+    PJ0 = 8 << 3, PJ1, PJ2, PJ3,
+
+    // Other mbed Pin Names
+    LED1 = PB0,
+    LED2 = PB1,
+    LED3 = LED1,
+    LED4 = LED2,
+
+    // External data bus Pin Names
+    D0 = PE1,
+    D1 = PE2,
+    D2 = PE0,
+    D3 = PD1,
+    D4 = PJ1,
+    D5 = PD2,
+    D6 = PD3,
+    D7 = PJ2,
+    D8 = PJ3,
+    D9 = PF4,
+    D10 = PF0,
+    D11 = PF1,
+    D12 = PF2,
+    D13 = PF3,
+    D14 = PC1,
+    D15 = PC0,
+
+    // Analogue out pins
+    A0 = PA2,
+    A1 = PA3,
+    A2 = PA4,
+    A3 = PA5,
+    A4 = PA6,
+    A5 = PA7,
+
+    // DAP_UART
+    USBTX = PC2,
+    USBRX = PC3,
+    MBEDIF_TXD = USBTX,
+    MBEDIF_RXD = USBRX,
+
+    // Switches
+    SW1 = PB2,
+    SW2 = PB3,
+
+    // I2C pins
+    SDA = PC1,
+    SCL = PC0,
+    I2C_SDA = SDA,
+    I2C_SCL = SCL,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown,
+    PullNone,
+    OpenDrain,
+    PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB,
+    PortC,
+    PortD,
+    PortE,
+    PortF,
+    PortG,
+    PortH,
+    PortJ
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_wait_api.h"
+
+static uint8_t adc_reset_init = 0;  // Is ADC Reset happened yet?
+#define ADC_10BIT_RANGE        0x3FF
+
+static const PinMap PinMap_ADC[] = {
+    {PA0, ADC_A0, PIN_DATA(0, 0)},
+    {PA1, ADC_A1, PIN_DATA(0, 0)},
+    {PA2, ADC_A2, PIN_DATA(0, 0)},
+    {PA3, ADC_A3, PIN_DATA(0, 0)},
+    {PA4, ADC_A4, PIN_DATA(0, 0)},
+    {PA5, ADC_A5, PIN_DATA(0, 0)},
+    {PA6, ADC_A6, PIN_DATA(0, 0)},
+    {PA7, ADC_A7, PIN_DATA(0, 0)},
+    {NC,  NC,     0}
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    // Check that pin belong to ADC module
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    // enable clock supply to ADC
+    CG_SetFcPeriphA(CG_FC_PERIPH_ADC, ENABLE);
+    CG_SetADCClkSupply(ENABLE);
+    // Set pin function as ADC
+    pinmap_pinout(pin, PinMap_ADC);
+    if (!adc_reset_init) {
+        // Software reset ADC
+        ADC_SWReset();
+        adc_reset_init = 1;
+    }
+    // Set sample hold time and pre-scale clock
+    ADC_SetClk(ADC_CONVERSION_81_CLOCK, ADC_FC_DIVIDE_LEVEL_8);
+    // Set input channel
+    ADC_SetInputChannel(obj->adc);
+    // Turn VREF on
+    ADC_SetVref(ENABLE);
+    // Use fixed-channel single conversion mode
+    ADC_SetRepeatMode(DISABLE);
+    ADC_SetScanMode(DISABLE);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    ADC_ResultTypeDef ret;
+
+    // Assert that ADC channel is valid
+    MBED_ASSERT(obj->adc != (ADCName) NC);
+
+    // Set input channel
+    ADC_SetInputChannel(obj->adc);
+    // Enable Vref
+    ADC_SetVref(ENABLE);
+    // Wait at least 3us to ensure the voltage is stable
+    wait_us(10U);
+    // Start ADC conversion
+    ADC_Start();
+    // Wait until AD conversion complete
+    while (ADC_GetConvertState().Bit.NormalComplete != 1) {
+        // Do nothing
+    }
+    // Convert result
+    ret = ADC_GetConvertResult(obj->adc);
+    // Disable Vref to go into standby mode
+    ADC_SetVref(DISABLE);
+    return (uint16_t)ret.ADCResultValue;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)(value * (1.0f / (float)ADC_10BIT_RANGE));
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_ID_LENGTH    32
+
+#include "objects.h"
+#include <stddef.h>
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,2287 @@
+/**
+ *******************************************************************************
+ * @file    TMPM066.h
+ * @brief   CMSIS Cortex-M0 Core Peripheral Access Layer Header File for the
+ *          TOSHIBA 'TMPM066' Device Series
+ * @version V2.0.2.2 (Tentative)
+ * @date    2016/02/15
+ *
+ *(C)Copyright TOSHIBA CORPORATION 2016 All rights reserved
+ *******************************************************************************
+ */
+
+/** @addtogroup TOSHIBA_TX00_MICROCONTROLLER
+  * @{
+  */
+
+/** @addtogroup TMPM066
+  * @{
+  */
+
+#ifndef __TMPM066_H__
+#define __TMPM066_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/** Interrupt Number Definition */
+    typedef enum IRQn {
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************************/
+        NonMaskableInt_IRQn = -14,      /*!< 2 Non Maskable Interrupt                                    */
+        HardFault_IRQn = -13,   /*!< 3 Cortex-M0 Hard Fault Interrupt                            */
+        SVCall_IRQn = -5,       /*!< 11 Cortex-M0 SV Call Interrupt                              */
+        PendSV_IRQn = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt                              */
+        SysTick_IRQn = -1,      /*!< 15 Cortex-M0 System Tick Interrupt                          */
+
+/******  TMPM066 Specific Interrupt Numbers *******************************************************************/
+        INT0_IRQn = 0,          /*!< Interrupt Pin0                                              */
+        INT1_IRQn = 1,          /*!< Interrupt Pin1                                              */
+        INT2_IRQn = 2,          /*!< Interrupt Pin2                                              */
+        INT3_IRQn = 3,          /*!< Interrupt Pin3                                              */
+        INT4_IRQn = 4,          /*!< Interrupt Pin4                                              */
+        INT5_IRQn = 5,          /*!< Interrupt Pin5                                              */
+        INTRX0_IRQn = 6,        /*!< Serial reception interrupt(channel0)                        */
+        INTTX0_IRQn = 7,        /*!< Serial transmission interrupt(channel0)                     */
+        INTRX1_IRQn = 8,        /*!< Serial reception interrupt(channel1)                        */
+        INTTX1_IRQn = 9,        /*!< Serial transmission interrupt(channel1)                     */
+        INTSPIRX_IRQn = 10,     /*!< SPI serial reception interrupt                              */
+        INTSPITX_IRQn = 11,     /*!< SPI serial transmission interrupt                           */
+        INTSPIERR_IRQn = 12,    /*!< SPI serial error interrupt                                  */
+        INTI2C0_IRQn = 13,      /*!< Serial bus interface (channel.0)                            */
+        INTI2C1_IRQn = 14,      /*!< Serial bus interface (channel.1)                            */
+        INTDMA_IRQn = 15,       /*!< DMAC interrupt                                              */
+        INT16A0_IRQn = 16,      /*!< 16-bit TMR16A match detection (channel.0)                   */
+        INT16A1_IRQn = 17,      /*!< 16-bit TMR16A match detection (channel.1)                   */
+        INTTB0_IRQn = 18,       /*!< 16-bit TMRB interrupt(channel.0)                            */
+        INTTB1_IRQn = 19,       /*!< 16-bit TMRB interrupt(channel.1)                            */
+        INTTB2_IRQn = 20,       /*!< 16-bit TMRB interrupt(channel.2)                            */
+        INTTB3_IRQn = 21,       /*!< 16-bit TMRB interrupt(channel.3)                            */
+        INTTB4_IRQn = 22,       /*!< 16-bit TMRB interrupt(channel.4)                            */
+        INTTB5_IRQn = 23,       /*!< 16-bit TMRB interrupt(channel.5)                            */
+        INTTB6_IRQn = 24,       /*!< 16-bit TMRB interrupt(channel.6)                            */
+        INTTB7_IRQn = 25,       /*!< 16-bit TMRB interrupt(channel.7)                            */
+        INTI2CS_IRQn = 26,      /*!< Serial bus interface for Wakeup(channel.1)                  */
+        INTTMRD_IRQn = 27,      /*!< TMRD interrupt                                              */
+        INTUSB_IRQn = 28,       /*!< USB interrupt                                               */
+        INTUSBWKUP_IRQn = 29,   /*!< USB wakeup interrupt                                        */
+        INTADHP_IRQn = 30,      /*!< High Priority A/D conversion interrupt                      */
+        INTAD_IRQn = 31         /*!< Normal A/D conversion completion interrupt                  */
+    } IRQn_Type;
+
+/** Processor and Core Peripheral Section */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM0_REV              0x0000   /*!< Cortex-M0 Core Revision                           */
+#define __MPU_PRESENT             0     /*!< MPU present or not                                */
+#define __NVIC_PRIO_BITS          2     /*!< Number of Bits used for Priority Levels           */
+#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used      */
+
+    /** @} *//* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h"           /* Cortex-M0 processor and core peripherals            */
+#include "system_TMPM066.h"     /* TMPM066 System                                      */
+
+/** @addtogroup Device_Peripheral_registers
+  * @{
+  */
+
+/** Device Specific Peripheral registers structures */
+
+/**
+  * @brief UDC2 AHB Bridge
+  */
+    typedef struct {
+        __IO uint32_t INTSTS;   /*!< Interrupt Status Register                    */
+        __IO uint32_t INTENB;   /*!< Interrupt Enable Register                    */
+        __IO uint32_t MWTOUT;   /*!< Master Write Timeout Register                */
+        __IO uint32_t C2STSET;  /*!< UDC2 setting                                 */
+        __IO uint32_t MSTSET;   /*!< DMAC setting                                 */
+        __IO uint32_t DMACRDREQ;        /*!< DMAC Read request                            */
+        __I uint32_t DMACRDVL;  /*!< DMAC Read Value                              */
+        __IO uint32_t UDC2RDREQ;        /*!< UDC2 Read Request                            */
+        __I uint32_t UDC2RDVL;  /*!< UDC2 Read Value                              */
+        uint32_t RESERVED0[6];
+        __IO uint32_t ARBTSET;  /*!< Arbiter Setting                              */
+        __IO uint32_t MWSADR;   /*!< Master Write Start Address                   */
+        __IO uint32_t MWEADR;   /*!< Master Write End Address                     */
+        __I uint32_t MWCADR;    /*!< Master Write Current Address                 */
+        __I uint32_t MWAHBADR;  /*!< Master Write AHB Address                     */
+        __IO uint32_t MRSADR;   /*!< Master Read Start Address                    */
+        __IO uint32_t MREADR;   /*!< Master Read End Address                      */
+        __I uint32_t MRCADR;    /*!< Master Read Current Address                  */
+        __I uint32_t MRAHBADR;  /*!< Master Read AHB Address                      */
+        uint32_t RESERVED1[8];
+        __IO uint32_t PWCTL;    /*!< Power Detect Control                         */
+        __I uint32_t MSTSTS;    /*!< Master Status                                */
+        __I uint32_t TOUTCNT;   /*!< Timeout Count                                */
+    } TSB_UDFS_TypeDef;
+
+/**
+  * @brief UDC2(USB -Spec2.0 Device contoller)
+  */
+    typedef struct {
+        __IO uint32_t ADR;      /*!< UDC2 Address State                           */
+        __IO uint32_t FRM;      /*!< UDC2 Frame                                   */
+        uint32_t RESERVED0;
+        __IO uint32_t CMD;      /*!< UDC2 Command                                 */
+        __I uint32_t BRQ;       /*!< UDC2 bRequest-bmRequest Type                 */
+        __I uint32_t WVL;       /*!< UDC2 wValue                                  */
+        __I uint32_t WIDX;      /*!< UDC2 wIndex                                  */
+        __I uint32_t WLGTH;     /*!< UDC2 wLength                                 */
+        __IO uint32_t INT;      /*!< UDC2 INT                                     */
+        __IO uint32_t INTEP;    /*!< UDC2 INT_EP                                  */
+        __IO uint32_t INTEPMSK; /*!< UDC2 INT_EP_MASK                             */
+        __IO uint32_t INTRX0;   /*!< UDC2 INT RX DATA0                            */
+        __IO uint32_t EP0MSZ;   /*!< UDC2 EP0 Max Packet Size                     */
+        __I uint32_t EP0STS;    /*!< UDC2 EP0 Status                              */
+        __I uint32_t EP0DSZ;    /*!< UDC2 EP0 Data Size                           */
+        __IO uint32_t EP0FIFO;  /*!< UDC2 EP0 FIFO                                */
+        __IO uint32_t EP1MSZ;   /*!< UDC2 EP1 Max Packet Size                     */
+        __IO uint32_t EP1STS;   /*!< UDC2 EP1 Status                              */
+        __I uint32_t EP1DSZ;    /*!< UDC2 EP1 Data Size                           */
+        __IO uint32_t EP1FIFO;  /*!< UDC2 EP1 FIFO                                */
+        __IO uint32_t EP2MSZ;   /*!< UDC2 EP2 Max Packet Size                     */
+        __IO uint32_t EP2STS;   /*!< UDC2 EP2 Status                              */
+        __I uint32_t EP2DSZ;    /*!< UDC2 EP2 Data Size                           */
+        __IO uint32_t EP2FIFO;  /*!< UDC2 EP2 FIFO                                */
+        __IO uint32_t EP3MSZ;   /*!< UDC2 EP3 Max Packet Size                     */
+        __IO uint32_t EP3STS;   /*!< UDC2 EP3 Status                              */
+        __I uint32_t EP3DSZ;    /*!< UDC2 EP3 Data Size                           */
+        __IO uint32_t EP3FIFO;  /*!< UDC2 EP3 FIFO                                */
+        __IO uint32_t EP4MSZ;   /*!< UDC2 EP4 Max Packet Size                     */
+        __IO uint32_t EP4STS;   /*!< UDC2 EP4 Status                              */
+        __I uint32_t EP4DSZ;    /*!< UDC2 EP4 Data Size                           */
+        __IO uint32_t EP4FIFO;  /*!< UDC2 EP4 FIFO                                */
+        uint32_t RESERVED1[44];
+        __IO uint32_t INTNAK;   /*!< UDC2 INT NAK                                 */
+        __IO uint32_t INTNAKMSK;        /*!< UDC2 INT NAK MASK                            */
+    } TSB_UDFS2_TypeDef;
+
+/**
+  * @brief AO Area register1
+  */
+    typedef struct {
+        uint8_t RESERVED0[32];
+        __IO uint8_t STOP2INT_032;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_033;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_034;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_035;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_036;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_037;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_038;      /*!< STOP2INT I/F Control Register in AO Area     */
+        __IO uint8_t STOP2INT_039;      /*!< STOP2INT I/F Control Register in AO Area     */
+    } TSB_INTIFAO_TypeDef;
+
+/**
+  * @brief AO Area register2
+  */
+    typedef struct {
+        uint8_t RESERVED0[2];
+        __IO uint8_t RSTFLG;    /*!< Reset Flag register                          */
+        __IO uint8_t RSTFLG1;   /*!< Reset Flag1 register                         */
+    } TSB_AOREG_TypeDef;
+
+/**
+  * @brief I2C Wakeup I/F register
+  */
+    typedef struct {
+        __IO uint8_t WUPCR1;    /*!< I2C Wakeup control register1                 */
+        __IO uint8_t WUPCR2;    /*!< I2C Wakeup control register2                 */
+        __IO uint8_t WUPCR3;    /*!< I2C Wakeup control register3                 */
+        __I uint8_t WUPSL;      /*!< I2C Wakeup Status register                   */
+    } TSB_I2CS_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+    typedef struct {
+        __I uint32_t STATUS;    /*!< DMA Status Register                          */
+        __O uint32_t CFG;       /*!< DMA Configuration Register                   */
+        __IO uint32_t CTRLBASEPTR;      /*!< DMA Control Data Base Pointer Register       */
+        __I uint32_t ALTCTRLBASEPTR;    /*!< DMA Channel Alternate Control Data Base 
+                                           Pointer Register */
+        uint32_t RESERVED0;
+        __O uint32_t CHNLSWREQUEST;     /*!< DMA Channel Software Request Register        */
+        __IO uint32_t CHNLUSEBURSTSET;  /*!< DMA Channel Useburst Set Register            */
+        __O uint32_t CHNLUSEBURSTCLR;   /*!< DMA Channel Useburst Clear Register          */
+        __IO uint32_t CHNLREQMASKSET;   /*!< DMA Channel Request Mask Set Register        */
+        __O uint32_t CHNLREQMASKCLR;    /*!< DMA Channel Request Mask Clear Register      */
+        __IO uint32_t CHNLENABLESET;    /*!< DMA Channel Enable Set Register              */
+        __O uint32_t CHNLENABLECLR;     /*!< DMA Channel Enable Clear Register            */
+        __IO uint32_t CHNLPRIALTSET;    /*!< DMA Channel Primary-Alternate Set Register   */
+        __O uint32_t CHNLPRIALTCLR;     /*!< DMA Channel Primary-Alternate Clear Register */
+        __IO uint32_t CHNLPRIORITYSET;  /*!< DMA Channel Priority Set Register            */
+        __O uint32_t CHNLPRIORITYCLR;   /*!< DMA Channel Priority Clear Register          */
+        uint32_t RESERVED1[3];
+        __IO uint32_t ERRCLR;   /*!< DMA Bus Error Clear Register                 */
+    } TSB_DMA_TypeDef;
+
+/**
+  * @brief Timer D (Unit0)
+  */
+    typedef struct {
+        __O uint32_t RUN;       /*!< Timer Run Register (Unit0)                   */
+        __IO uint32_t CR;       /*!< Timer Control Register (Unit0)               */
+        __IO uint32_t MOD;      /*!< Timer Mode Register (Unit0)                  */
+        __IO uint32_t DMA;      /*!< DMA Request Enable Register (Unit0)          */
+        uint32_t RESERVED0;
+        __IO uint32_t RG0;      /*!< Timer Register0 (Unit0)                      */
+        __IO uint32_t RG1;      /*!< Timer Register1 (Unit0)                      */
+        __IO uint32_t RG2;      /*!< Timer Register2 (Unit0)                      */
+        __IO uint32_t RG3;      /*!< Timer Register3 (Unit0)                      */
+        __IO uint32_t RG4;      /*!< Timer Register4 (Unit0)                      */
+        __IO uint32_t RG5;      /*!< Timer Register5 (Unit0)                      */
+        uint32_t RESERVED1[13];
+        __IO uint32_t HSWB0;    /*!< H-SW Control Circuit Register Buffer0 (Unit0) */
+        __IO uint32_t HSWB1;    /*!< H-SW Control Circuit Register Buffer1 (Unit0) */
+        uint32_t RESERVED2[43];
+        __I uint32_t CP0;       /*!< Compare Register0 (Unit0)                    */
+        __I uint32_t CP1;       /*!< Compare Register1 (Unit0)                    */
+        __I uint32_t CP2;       /*!< Compare Register2 (Unit0)                    */
+        __I uint32_t CP3;       /*!< Compare Register3 (Unit0)                    */
+        __I uint32_t CP4;       /*!< Compare Register4 (Unit0)                    */
+        __I uint32_t CP5;       /*!< Compare Register5 (Unit0)                    */
+        uint32_t RESERVED3[13];
+        __I uint32_t HSW0;      /*!< H-SW Control Circuit Register (Unit0)        */
+        __I uint32_t HSW1;      /*!< H-SW Control Circuit Register (Unit0)        */
+    } TSB_TD0_TypeDef;
+
+/**
+  * @brief Timer D common
+  */
+    typedef struct {
+        __IO uint32_t BCR;      /*!< Update Flag Setting Register                 */
+        uint32_t RESERVED0[3];
+        __IO uint32_t EN;       /*!< Timer Enable Register                        */
+        __IO uint32_t CONF;     /*!< Timer Configuration Register                 */
+    } TSB_TD_TypeDef;
+
+/**
+  * @brief Timer D (Unit1)
+  */
+    typedef struct {
+        __IO uint32_t RG0;      /*!< Timer Register0 (Unit1)                      */
+        __IO uint32_t RG1;      /*!< Timer Register1 (Unit1)                      */
+        __IO uint32_t RG2;      /*!< Timer Register2 (Unit1)                      */
+        __IO uint32_t RG3;      /*!< Timer Register3 (Unit1)                      */
+        __IO uint32_t RG4;      /*!< Timer Register4 (Unit1)                      */
+        uint32_t RESERVED0[10];
+        __IO uint32_t HSWB0;    /*!< H-SW Control Circuit Register Buffer0 (Unit1) */
+        __IO uint32_t HSWB1;    /*!< H-SW Control Circuit Register Buffer1 (Unit1) */
+        uint32_t RESERVED1[36];
+        __O uint32_t RUN;       /*!< Timer Run Register (Unit1)                   */
+        __IO uint32_t CR;       /*!< Timer Control Register (Unit1)               */
+        __IO uint32_t MOD;      /*!< Timer Mode Register (Unit1)                  */
+        __IO uint32_t DMA;      /*!< DMA Request Enable Register (Unit1)          */
+        uint32_t RESERVED2[7];
+        __I uint32_t CP0;       /*!< Compare Register0 (Unit1)                    */
+        __I uint32_t CP1;       /*!< Compare Register1 (Unit1)                    */
+        __I uint32_t CP2;       /*!< Compare Register2 (Unit1)                    */
+        __I uint32_t CP3;       /*!< Compare Register3 (Unit1)                    */
+        __I uint32_t CP4;       /*!< Compare Register4 (Unit1)                    */
+        uint32_t RESERVED3[10];
+        __I uint32_t HSW0;      /*!< H-SW Control Circuit Register (Unit1)        */
+        __I uint32_t HSW1;      /*!< H-SW Control Circuit Register (Unit1)        */
+    } TSB_TD1_TypeDef;
+
+/**
+  * @brief 16-bit TimerA
+  */
+    typedef struct {
+        __IO uint32_t EN;       /*!< Enable Register                              */
+        __IO uint32_t RUN;      /*!< RUN Register                                 */
+        __IO uint32_t CR;       /*!< Control Register                             */
+        __IO uint32_t RG;       /*!< Timer Register                               */
+        __I uint32_t CP;        /*!< Capture Register                             */
+    } TSB_T16A_TypeDef;
+
+/**
+  * @brief Serial Interface (TSPI)
+  */
+    typedef struct {
+        __IO uint32_t CR0;      /*!< TSPI Control Register 0                      */
+        __IO uint32_t CR1;      /*!< TSPI Control Register 1                      */
+        __IO uint32_t CR2;      /*!< TSPI Control Register 2                      */
+        __IO uint32_t CR3;      /*!< TSPI Control Register 3                      */
+        __IO uint32_t BR;       /*!< TSPI Baud Rate Generator Control Register    */
+        __IO uint32_t FMTR0;    /*!< TSPI Format Control Register 0               */
+        __IO uint32_t FMTR1;    /*!< TSPI Format Control Register 1               */
+        uint32_t RESERVED0[57];
+        __IO uint32_t DR;       /*!< TSPI Data Register                           */
+        uint32_t RESERVED1[63];
+        __IO uint32_t SR;       /*!< TSPI Status Register                         */
+        __IO uint32_t ERR;      /*!< TSPI Parity Error Flag Register              */
+    } TSB_TSPI_TypeDef;
+
+#if defined ( __CC_ARM   )      /* RealView Compiler */
+#pragma anon_unions
+#elif (defined (__ICCARM__))    /*  ICC Compiler     */
+#pragma language=extended
+#endif
+
+/**
+  * @brief I2C 
+  */
+    typedef struct {
+        __IO uint32_t CR1;      /*!< I2C Control Register 1                       */
+        __IO uint32_t DBR;      /*!< Data Buffer Register                         */
+        __IO uint32_t AR;       /*!< Bus address Register                         */
+        union {
+            __O uint32_t CR2;   /*!< Control Register 2                           */
+            __I uint32_t SR;    /*!< Status Register                              */
+        };
+        __IO uint32_t PRS;      /*!< Prescaler clcok setting Register             */
+        __IO uint32_t IE;       /*!< Interrupt Enable Register                    */
+        __IO uint32_t ST;       /*!< Interrupt Register                           */
+        __IO uint32_t OP;       /*!< Optiononal Function register                 */
+        __I uint32_t PM;        /*!< Bus Monitor register                         */
+        __IO uint32_t AR2;      /*!< Second Slave address register                */
+    } TSB_I2C_TypeDef;
+
+/**
+  * @brief Port A
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PA Data Register                             */
+        __IO uint32_t CR;       /*!< PA Control Register                          */
+        __IO uint32_t FR1;      /*!< PA Function Register 1                       */
+        uint32_t RESERVED0[7];
+        __IO uint32_t OD;       /*!< PA Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PA Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PA Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PA Input Enable Control Register             */
+    } TSB_PA_TypeDef;
+
+/**
+  * @brief Port B
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PB Data Register                             */
+        __IO uint32_t CR;       /*!< PB Control Register                          */
+        uint32_t RESERVED0[8];
+        __IO uint32_t OD;       /*!< PB Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PB Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PB Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PB Input Enable Control Register             */
+    } TSB_PB_TypeDef;
+
+/**
+  * @brief Port C
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PC Data Register                             */
+        __IO uint32_t CR;       /*!< PC Control Register                          */
+        __IO uint32_t FR1;      /*!< PC Function Register 1                       */
+        uint32_t RESERVED0[7];
+        __IO uint32_t OD;       /*!< PC Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PC Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PC Pull-Down Control Register                */
+        __IO uint32_t SEL;      /*!< PC input voltage selection Register          */
+        __IO uint32_t IE;       /*!< PC Input Enable Control Register             */
+    } TSB_PC_TypeDef;
+
+/**
+  * @brief Port D
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PD Data Register                             */
+        __IO uint32_t CR;       /*!< PD Control Register                          */
+        __IO uint32_t FR1;      /*!< PD Function Register 1                       */
+        __IO uint32_t FR2;      /*!< PD Function Register 2                       */
+        uint32_t RESERVED0[6];
+        __IO uint32_t OD;       /*!< PD Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PD Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PD Pull-Down Control Register                */
+        __IO uint32_t SEL;      /*!< PD input voltage selection Register          */
+        __IO uint32_t IE;       /*!< PD Input Enable Control Register             */
+    } TSB_PD_TypeDef;
+
+/**
+  * @brief Port E
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PE Data Register                             */
+        __IO uint32_t CR;       /*!< PE Control Register                          */
+        __IO uint32_t FR1;      /*!< PE Function Register 1                       */
+        __IO uint32_t FR2;      /*!< PE Function Register 2                       */
+        uint32_t RESERVED0[6];
+        __IO uint32_t OD;       /*!< PE Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PE Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PE Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PE Input Enable Control Register             */
+    } TSB_PE_TypeDef;
+
+/**
+  * @brief Port F 
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PF Data Register                             */
+        __IO uint32_t CR;       /*!< PF Control Register                          */
+        __IO uint32_t FR1;      /*!< PF Function Register 1                       */
+        __IO uint32_t FR2;      /*!< PF Function Register 2                       */
+        uint32_t RESERVED0[6];
+        __IO uint32_t OD;       /*!< PF Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PF Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PF Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PF Input Enable Control Register             */
+    } TSB_PF_TypeDef;
+
+/**
+  * @brief Port G
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PG Data Register                             */
+        __IO uint32_t CR;       /*!< PG Control Register                          */
+        __IO uint32_t FR1;      /*!< PG Function Register 1                       */
+        uint32_t RESERVED0[7];
+        __IO uint32_t OD;       /*!< PG Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PG Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PG Pull-Down Control Register                */
+        __IO uint32_t SEL;      /*!< PG input voltage selection Register          */
+        __IO uint32_t IE;       /*!< PG Input Enable Control Register             */
+    } TSB_PG_TypeDef;
+
+/**
+  * @brief Port H
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PH Data Register                             */
+        __IO uint32_t CR;       /*!< PH Control Register                          */
+        __IO uint32_t FR1;      /*!< PF Function Register 1                       */
+        uint32_t RESERVED0[7];
+        __IO uint32_t OD;       /*!< PH Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PH Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PH Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PH Input Enable Control Register             */
+    } TSB_PH_TypeDef;
+
+/**
+  * @brief Port J
+  */
+    typedef struct {
+        __IO uint32_t DATA;     /*!< PJ Data Register                             */
+        __IO uint32_t CR;       /*!< PJ Control Register                          */
+        __IO uint32_t FR1;      /*!< PJ Function Register 1                       */
+        uint32_t RESERVED0[7];
+        __IO uint32_t OD;       /*!< PJ Open Drain Control Register               */
+        __IO uint32_t PUP;      /*!< PJ Pull-up Control Register                  */
+        __IO uint32_t PDN;      /*!< PJ Pull-Down Control Register                */
+        uint32_t RESERVED1;
+        __IO uint32_t IE;       /*!< PJ Input Enable Control Register             */
+    } TSB_PJ_TypeDef;
+
+/**
+  * @brief 16-bit Timer/Event Counter (TB)
+  */
+    typedef struct {
+        __IO uint32_t EN;       /*!< TB Enable Register                           */
+        __IO uint32_t RUN;      /*!< TB RUN Register                              */
+        __IO uint32_t CR;       /*!< TB Control Register                          */
+        __IO uint32_t MOD;      /*!< TB Mode Register                             */
+        __IO uint32_t FFCR;     /*!< TB Flip-Flop Control Register                */
+        __I uint32_t ST;        /*!< TB Status Register                           */
+        __IO uint32_t IM;       /*!< TB Interrupt Mask Register                   */
+        __I uint32_t UC;        /*!< TB Read Capture Register                     */
+        __IO uint32_t RG0;      /*!< TB RG0 Timer Register                        */
+        __IO uint32_t RG1;      /*!< TB RG1 Timer Register                        */
+        __I uint32_t CP0;       /*!< TB CP0 Capture Register                      */
+        __I uint32_t CP1;       /*!< TB CP1 Capture Register                      */
+        __IO uint32_t DMA;      /*!< TB DMA Enable Register                       */
+    } TSB_TB_TypeDef;
+
+/**
+  * @brief SC
+  */
+    typedef struct {
+        __IO uint32_t EN;       /*!< SC Enable Register                           */
+        __IO uint32_t BUF;      /*!< SC Buffer Register                           */
+        __IO uint32_t CR;       /*!< SC Control Register                          */
+        __IO uint32_t MOD0;     /*!< SC Mode Control Register 0                   */
+        __IO uint32_t BRCR;     /*!< SC Baud Rate Generator Control Register      */
+        __IO uint32_t BRADD;    /*!< SC Baud Rate Generator Control Register 2    */
+        __IO uint32_t MOD1;     /*!< SC Mode Control Register 1                   */
+        __IO uint32_t MOD2;     /*!< SC Mode Control Register 2                   */
+        __IO uint32_t RFC;      /*!< SC RX FIFO Configuration Register            */
+        __IO uint32_t TFC;      /*!< SC TX FIFO Configuration Register            */
+        __I uint32_t RST;       /*!< SC RX FIFO Status Register                   */
+        __I uint32_t TST;       /*!< SC TX FIFO Status Register                   */
+        __IO uint32_t FCNF;     /*!< SC FIFO Configuration Register               */
+        __IO uint32_t DMA;      /*!< SC DMA Request Register                      */
+    } TSB_SC_TypeDef;
+
+/**
+  * @brief WDT
+  */
+    typedef struct {
+        __IO uint32_t MOD;      /*!< WD Mode Register                             */
+        __O uint32_t CR;        /*!< WD Control Register                          */
+        __I uint32_t FLG;       /*!< WD Flag Register                             */
+    } TSB_WD_TypeDef;
+
+/**
+  * @brief CG
+  */
+    typedef struct {
+        __IO uint32_t PROTECT;  /*!< Protect Register                             */
+        __IO uint32_t OSCCR;    /*!< Oscillation Control Register                 */
+        __IO uint32_t SYSCR;    /*!< System clock control register                */
+        __IO uint32_t STBYCR;   /*!< Standby Control Register                     */
+        uint32_t RESERVED0[4];
+        __IO uint32_t PLL0SEL;  /*!< PLL select register for fsys                 */
+        uint32_t RESERVED1[3];
+        __IO uint32_t WUPHCR;   /*!< Warmup register for HOSC                     */
+        uint32_t RESERVED2[7];
+        __IO uint32_t FSYSENA;  /*!< output control register A  for fsys clock    */
+        __O uint32_t FSYSENB;   /*!< output control register B  for fsys clock    */
+        uint32_t RESERVED3;
+        __IO uint32_t SPCLKEN;  /*!< Output control register for ADC and TRACE CLOCK */
+        __IO uint32_t EXTENDO0; /*!< Optional Function setting Register           */
+    } TSB_CG_TypeDef;
+
+/**
+  * @brief LVD
+  */
+    typedef struct {
+        __IO uint32_t CR0;      /*!< LVD Control register0                        */
+        __IO uint32_t CR1;      /*!< LVD Control register1                        */
+    } TSB_LVD_TypeDef;
+
+/**
+  * @brief SD Area register1
+  */
+    typedef struct {
+        uint8_t RESERVED0[16];
+        __IO uint8_t STOP1INT_016;      /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */
+        __IO uint8_t STOP1INT_017;      /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */
+        __IO uint8_t IDLEINT_018;       /*!< ILDEINT(NMI_WDT) I/F Control Register in SD Area */
+        uint8_t RESERVED1[77];
+        __IO uint8_t IDLEINT_096;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_097;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_098;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_099;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_100;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_101;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_102;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_103;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_104;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_105;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_106;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_107;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_108;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_109;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_110;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_111;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_112;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_113;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_114;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_115;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_116;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_117;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_118;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_119;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_120;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_121;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_122;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_123;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_124;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_125;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_126;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_127;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_128;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_129;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_130;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_131;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_132;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_133;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_134;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_135;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_136;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_137;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_138;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_139;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_140;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_141;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_142;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_143;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_144;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_145;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_146;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_147;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_148;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_149;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_150;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_151;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_152;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_153;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_154;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_155;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_156;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_157;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_158;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_159;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_160;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_161;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_162;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_163;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_164;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_165;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_166;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_167;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_168;       /*!< IDLEINT I/F Control Register in SD Area      */
+        __IO uint8_t IDLEINT_169;       /*!< IDLEINT I/F Control Register in SD Area      */
+        uint32_t RESERVED2[21];
+        __I uint32_t FLAG0;     /*!< NMI interrupt status flag register           */
+        __I uint32_t FLAG1;     /*!< interrupt status flag register1 for AO area  */
+        uint32_t RESERVED3;
+        __I uint32_t FLAG3;     /*!< interrupt status flag register3 for SD area  */
+        __I uint32_t FLAG4;     /*!< interrupt status flag register4 for SD area  */
+        __I uint32_t FLAG5;     /*!< interrupt status flag register5 for SD area  */
+    } TSB_INTIFSD_TypeDef;
+
+/**
+  * @brief ADC
+  */
+    typedef struct {
+        __IO uint32_t CLK;      /*!< AD Conversion Clock Setting Register         */
+        __IO uint32_t MOD0;     /*!< AD Mode Control Register 0                   */
+        __IO uint32_t MOD1;     /*!< AD Mode Control Register 1                   */
+        __IO uint32_t MOD2;     /*!< AD Mode Control Register 2                   */
+        __IO uint32_t MOD3;     /*!< AD Mode Control Register 3                   */
+        __IO uint32_t MOD4;     /*!< AD Mode Control Register 4                   */
+        __IO uint32_t MOD5;     /*!< AD Mode Control Register 5                   */
+        __IO uint32_t MOD6;     /*!< AD Mode Control Register 6                   */
+        uint32_t RESERVED0[4];
+        __I uint32_t REG0;      /*!< AD Conversion Result Register 0              */
+        __I uint32_t REG1;      /*!< AD Conversion Result Register 1              */
+        __I uint32_t REG2;      /*!< AD Conversion Result Register 2              */
+        __I uint32_t REG3;      /*!< AD Conversion Result Register 3              */
+        __I uint32_t REG4;      /*!< AD Conversion Result Register 4              */
+        __I uint32_t REG5;      /*!< AD Conversion Result Register 5              */
+        __I uint32_t REG6;      /*!< AD Conversion Result Register 6              */
+        __I uint32_t REG7;      /*!< AD Conversion Result Register 7              */
+        uint32_t RESERVED1[4];
+        __I uint32_t REGSP;     /*!< AD Conversion Result Register SP             */
+        __IO uint32_t CMP0;     /*!< AD Conversion Result comparing register0     */
+        __IO uint32_t CMP1;     /*!< AD Conversion result comparing register1     */
+    } TSB_AD_TypeDef;
+
+/**
+  * @brief FC
+  */
+    typedef struct {
+        uint32_t RESERVED0[4];
+        __IO uint32_t SECBIT;   /*!< FC Security Bit Register                     */
+        uint32_t RESERVED1[3];
+        __I uint32_t SR;        /*!< FC Flash Status Register                     */
+        uint32_t RESERVED2[3];
+        __I uint32_t PSRA;      /*!< FC Protect status register                   */
+        uint32_t RESERVED3;
+        __IO uint32_t PMRA;     /*!< FC Protect Mask register                     */
+    } TSB_FC_TypeDef;
+
+
+/* Memory map */
+#define FLASH_BASE            (0x00000000UL)
+#define RAM_BASE              (0x20000000UL)
+#define PERI_BASE             (0x40000000UL)
+
+
+#define TSB_UDFS_BASE              (PERI_BASE  + 0x0008000UL)
+#define TSB_UDFS2_BASE             (PERI_BASE  + 0x0008200UL)
+#define TSB_INTIFAO_BASE           (PERI_BASE  + 0x0038000UL)
+#define TSB_AOREG_BASE             (PERI_BASE  + 0x0038400UL)
+#define TSB_I2CS_BASE              (PERI_BASE  + 0x0038800UL)
+#define TSB_DMA_BASE               (PERI_BASE  + 0x004C000UL)
+#define TSB_TD0_BASE               (PERI_BASE  + 0x0058000UL)
+#define TSB_TD_BASE                (PERI_BASE  + 0x0058040UL)
+#define TSB_TD1_BASE               (PERI_BASE  + 0x005802CUL)
+#define TSB_T16A0_BASE             (PERI_BASE  + 0x008D000UL)
+#define TSB_T16A1_BASE             (PERI_BASE  + 0x008E000UL)
+#define TSB_TSPI0_BASE             (PERI_BASE  + 0x0098000UL)
+#define TSB_I2C0_BASE              (PERI_BASE  + 0x00A0000UL)
+#define TSB_I2C1_BASE              (PERI_BASE  + 0x00A1000UL)
+#define TSB_PA_BASE                (PERI_BASE  + 0x00C0000UL)
+#define TSB_PB_BASE                (PERI_BASE  + 0x00C0100UL)
+#define TSB_PC_BASE                (PERI_BASE  + 0x00C0200UL)
+#define TSB_PD_BASE                (PERI_BASE  + 0x00C0300UL)
+#define TSB_PE_BASE                (PERI_BASE  + 0x00C0400UL)
+#define TSB_PF_BASE                (PERI_BASE  + 0x00C0500UL)
+#define TSB_PG_BASE                (PERI_BASE  + 0x00C0600UL)
+#define TSB_PH_BASE                (PERI_BASE  + 0x00C0700UL)
+#define TSB_PJ_BASE                (PERI_BASE  + 0x00C0800UL)
+#define TSB_TB0_BASE               (PERI_BASE  + 0x00C4000UL)
+#define TSB_TB1_BASE               (PERI_BASE  + 0x00C4100UL)
+#define TSB_TB2_BASE               (PERI_BASE  + 0x00C4200UL)
+#define TSB_TB3_BASE               (PERI_BASE  + 0x00C4300UL)
+#define TSB_TB4_BASE               (PERI_BASE  + 0x00C4400UL)
+#define TSB_TB5_BASE               (PERI_BASE  + 0x00C4500UL)
+#define TSB_TB6_BASE               (PERI_BASE  + 0x00C4600UL)
+#define TSB_TB7_BASE               (PERI_BASE  + 0x00C4700UL)
+#define TSB_SC0_BASE               (PERI_BASE  + 0x00E1000UL)
+#define TSB_SC1_BASE               (PERI_BASE  + 0x00E1100UL)
+#define TSB_WD_BASE                (PERI_BASE  + 0x00F2000UL)
+#define TSB_CG_BASE                (PERI_BASE  + 0x00F3000UL)
+#define TSB_LVD_BASE               (PERI_BASE  + 0x00F4000UL)
+#define TSB_INTIFSD_BASE           (PERI_BASE  + 0x00F4E00UL)
+#define TSB_AD_BASE                (PERI_BASE  + 0x00FC000UL)
+#define TSB_FC_BASE                (PERI_BASE  + 0x1FFF000UL)
+
+
+/* Peripheral declaration */
+#define TSB_UDFS                   ((   TSB_UDFS_TypeDef *)  TSB_UDFS_BASE)
+#define TSB_UDFS2                  ((  TSB_UDFS2_TypeDef *) TSB_UDFS2_BASE)
+#define TSB_INTIFAO                ((TSB_INTIFAO_TypeDef *)TSB_INTIFAO_BASE)
+#define TSB_AOREG                  ((  TSB_AOREG_TypeDef *) TSB_AOREG_BASE)
+#define TSB_I2CS                   ((   TSB_I2CS_TypeDef *)  TSB_I2CS_BASE)
+#define TSB_DMA                    ((    TSB_DMA_TypeDef *)   TSB_DMA_BASE)
+#define TSB_TD0                    ((    TSB_TD0_TypeDef *)   TSB_TD0_BASE)
+#define TSB_TD                     ((     TSB_TD_TypeDef *)    TSB_TD_BASE)
+#define TSB_TD1                    ((    TSB_TD1_TypeDef *)   TSB_TD1_BASE)
+#define TSB_T16A0                  ((   TSB_T16A_TypeDef *) TSB_T16A0_BASE)
+#define TSB_T16A1                  ((   TSB_T16A_TypeDef *) TSB_T16A1_BASE)
+#define TSB_TSPI0                  ((   TSB_TSPI_TypeDef *) TSB_TSPI0_BASE)
+#define TSB_I2C0                   ((    TSB_I2C_TypeDef *)  TSB_I2C0_BASE)
+#define TSB_I2C1                   ((    TSB_I2C_TypeDef *)  TSB_I2C1_BASE)
+#define TSB_PA                     ((     TSB_PA_TypeDef *)    TSB_PA_BASE)
+#define TSB_PB                     ((     TSB_PB_TypeDef *)    TSB_PB_BASE)
+#define TSB_PC                     ((     TSB_PC_TypeDef *)    TSB_PC_BASE)
+#define TSB_PD                     ((     TSB_PD_TypeDef *)    TSB_PD_BASE)
+#define TSB_PE                     ((     TSB_PE_TypeDef *)    TSB_PE_BASE)
+#define TSB_PF                     ((     TSB_PF_TypeDef *)    TSB_PF_BASE)
+#define TSB_PG                     ((     TSB_PG_TypeDef *)    TSB_PG_BASE)
+#define TSB_PH                     ((     TSB_PH_TypeDef *)    TSB_PH_BASE)
+#define TSB_PJ                     ((     TSB_PJ_TypeDef *)    TSB_PJ_BASE)
+#define TSB_TB0                    ((     TSB_TB_TypeDef *)   TSB_TB0_BASE)
+#define TSB_TB1                    ((     TSB_TB_TypeDef *)   TSB_TB1_BASE)
+#define TSB_TB2                    ((     TSB_TB_TypeDef *)   TSB_TB2_BASE)
+#define TSB_TB3                    ((     TSB_TB_TypeDef *)   TSB_TB3_BASE)
+#define TSB_TB4                    ((     TSB_TB_TypeDef *)   TSB_TB4_BASE)
+#define TSB_TB5                    ((     TSB_TB_TypeDef *)   TSB_TB5_BASE)
+#define TSB_TB6                    ((     TSB_TB_TypeDef *)   TSB_TB6_BASE)
+#define TSB_TB7                    ((     TSB_TB_TypeDef *)   TSB_TB7_BASE)
+#define TSB_SC0                    ((     TSB_SC_TypeDef *)   TSB_SC0_BASE)
+#define TSB_SC1                    ((     TSB_SC_TypeDef *)   TSB_SC1_BASE)
+#define TSB_WD                     ((     TSB_WD_TypeDef *)    TSB_WD_BASE)
+#define TSB_CG                     ((     TSB_CG_TypeDef *)    TSB_CG_BASE)
+#define TSB_LVD                    ((    TSB_LVD_TypeDef *)   TSB_LVD_BASE)
+#define TSB_INTIFSD                ((TSB_INTIFSD_TypeDef *)TSB_INTIFSD_BASE)
+#define TSB_AD                     ((     TSB_AD_TypeDef *)    TSB_AD_BASE)
+#define TSB_FC                     ((     TSB_FC_TypeDef *)    TSB_FC_BASE)
+
+
+/* Bit-Band for Device Specific Peripheral Registers */
+#define BITBAND_OFFSET (0x02000000UL)
+#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET)
+#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2))
+
+
+
+/* UDC2 AHB Bridge */
+#define TSB_UDFS_INTSTS_INT_SETUP                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,0)))
+#define TSB_UDFS_INTSTS_INT_STATUS_NAK            (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,1)))
+#define TSB_UDFS_INTSTS_INT_STATUS                (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,2)))
+#define TSB_UDFS_INTSTS_INT_RX_ZERO               (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,3)))
+#define TSB_UDFS_INTSTS_INT_SOF                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,4)))
+#define TSB_UDFS_INTSTS_INT_EP0                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,5)))
+#define TSB_UDFS_INTSTS_INT_EP                    (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,6)))
+#define TSB_UDFS_INTSTS_INT_NAK                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,7)))
+#define TSB_UDFS_INTSTS_INT_SUSPEND_RESUME        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,8)))
+#define TSB_UDFS_INTSTS_INT_USB_RESET             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,9)))
+#define TSB_UDFS_INTSTS_INT_USB_RESET_END         (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,10)))
+#define TSB_UDFS_INTSTS_INT_MW_SET_ADD            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,17)))
+#define TSB_UDFS_INTSTS_INT_MW_END_ADD            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,18)))
+#define TSB_UDFS_INTSTS_INT_MW_TIMEOUT            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,19)))
+#define TSB_UDFS_INTSTS_INT_MW_AHBERR             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,20)))
+#define TSB_UDFS_INTSTS_INT_MR_END_ADD            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,21)))
+#define TSB_UDFS_INTSTS_INT_MR_EP_DSET            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,22)))
+#define TSB_UDFS_INTSTS_INT_MR_AHBERR             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,23)))
+#define TSB_UDFS_INTSTS_INT_UDC2_REGINT__RD       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,24)))
+#define TSB_UDFS_INTSTS_INT_DMAC_REG_RD           (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,25)))
+#define TSB_UDFS_INTSTS_INT_POWERDETECT           (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,28)))
+#define TSB_UDFS_INTSTS_INT_MW_RERROR             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,29)))
+#define TSB_UDFS_INTENB_SUSPEND_RESUME_EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,8)))
+#define TSB_UDFS_INTENB_RESET_EN                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,9)))
+#define TSB_UDFS_INTENB_RESET_END_EN              (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,10)))
+#define TSB_UDFS_INTENB_MW_SET_ADD_EN             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,17)))
+#define TSB_UDFS_INTENB_MW_END_ADD_EN             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,18)))
+#define TSB_UDFS_INTENB_MW_TIMEOUT                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,19)))
+#define TSB_UDFS_INTENB_MW_AHBERR                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,20)))
+#define TSB_UDFS_INTENB_MR_END_ADD_EN             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,21)))
+#define TSB_UDFS_INTENB_MR_EP_DSET_EN             (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,22)))
+#define TSB_UDFS_INTENB_MR_AHBERR                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,23)))
+#define TSB_UDFS_INTENB_UDC2_REG_RD               (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,24)))
+#define TSB_UDFS_INTENB_DMAC_REG_RD_EN            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,25)))
+#define TSB_UDFS_INTENB_POWER_DETECT_EN           (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,28)))
+#define TSB_UDFS_INTENB_MW_RERROR_EN              (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,29)))
+#define TSB_UDFS_MWTOUT_TIMEOUT_EN                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->MWTOUT,0)))
+#define TSB_UDFS_C2STSET_TX0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,0)))
+#define TSB_UDFS_C2STSET_EOPB_ENABLE              (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,4)))
+#define TSB_UDFS_DMACRDREQ_DMARDCLR               (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,30)))
+#define TSB_UDFS_DMACRDREQ_DMARDREQ               (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,31)))
+#define TSB_UDFS_UDC2RDREQ_UDC2RDCLR              (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,30)))
+#define TSB_UDFS_UDC2RDREQ_UDC2RDREQ              (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,31)))
+#define TSB_UDFS_ARBTSET_ABTMOD                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,28)))
+#define TSB_UDFS_ARBTSET_ABT_EN                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,31)))
+#define TSB_UDFS_PWCTL_USB_RESET                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,0)))
+#define TSB_UDFS_PWCTL_PW_RESETB                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,1)))
+#define TSB_UDFS_PWCTL_PW_DETECT                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,2)))
+#define TSB_UDFS_PWCTL_PHY_SUSPEND                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,3)))
+#define TSB_UDFS_PWCTL_SUSPEND_X                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,4)))
+#define TSB_UDFS_PWCTL_PHY_RESETB                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,5)))
+#define TSB_UDFS_PWCTL_PHY_REMOTE_WKUP            (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,6)))
+#define TSB_UDFS_PWCTL_WAKEUP_EN                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,7)))
+#define TSB_UDFS_MSTSTS_MWEPDSET                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,0)))
+#define TSB_UDFS_MSTSTS_MREPDSET                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,1)))
+#define TSB_UDFS_MSTSTS_MWBFEMP                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,2)))
+#define TSB_UDFS_MSTSTS_MRBFEMP                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,3)))
+#define TSB_UDFS_MSTSTS_MREPEMPTY                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,4)))
+
+
+/* UDC2(USB -Spec2.0 Device contoller) */
+#define TSB_UDFS2_ADR_SUSPEND                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,11)))
+#define TSB_UDFS2_ADR_EP_BI_MODE                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,14)))
+#define TSB_UDFS2_ADR_STAGE_ERR                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,15)))
+#define TSB_UDFS2_FRM_CREATE_SOF                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->FRM,15)))
+#define TSB_UDFS2_CMD_INT_TOGGLE                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->CMD,15)))
+#define TSB_UDFS2_BRQ_DIR                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->BRQ,7)))
+#define TSB_UDFS2_INT_I_SETUP                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,0)))
+#define TSB_UDFS2_INT_I_STATUS_NAK                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,1)))
+#define TSB_UDFS2_INT_I_STATUS                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,2)))
+#define TSB_UDFS2_INT_I_RX_DATA0                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,3)))
+#define TSB_UDFS2_INT_I_SOF                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,4)))
+#define TSB_UDFS2_INT_I_EP0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,5)))
+#define TSB_UDFS2_INT_I_EP                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,6)))
+#define TSB_UDFS2_INT_I_NAK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,7)))
+#define TSB_UDFS2_INT_M_SETUP                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,8)))
+#define TSB_UDFS2_INT_M_STATUS_NAK                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,9)))
+#define TSB_UDFS2_INT_M_STATUS                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,10)))
+#define TSB_UDFS2_INT_M_RX_DATA0                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,11)))
+#define TSB_UDFS2_INT_M_SOF                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,12)))
+#define TSB_UDFS2_INT_M_EP0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,13)))
+#define TSB_UDFS2_INT_M_EP                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,14)))
+#define TSB_UDFS2_INT_M_NAK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,15)))
+#define TSB_UDFS2_INTEP_I_EP1                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,1)))
+#define TSB_UDFS2_INTEP_I_EP2                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,2)))
+#define TSB_UDFS2_INTEP_I_EP3                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,3)))
+#define TSB_UDFS2_INTEP_I_EP4                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,4)))
+#define TSB_UDFS2_INTEPMSK_M_EP0                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,0)))
+#define TSB_UDFS2_INTEPMSK_M_EP1                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,1)))
+#define TSB_UDFS2_INTEPMSK_M_EP2                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,2)))
+#define TSB_UDFS2_INTEPMSK_M_EP3                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,3)))
+#define TSB_UDFS2_INTEPMSK_M_EP4                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,4)))
+#define TSB_UDFS2_INTRX0_RX_D0_EP0                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,0)))
+#define TSB_UDFS2_INTRX0_RX_D0_EP1                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,1)))
+#define TSB_UDFS2_INTRX0_RX_D0_EP2                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,2)))
+#define TSB_UDFS2_INTRX0_RX_D0_EP3                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,3)))
+#define TSB_UDFS2_INTRX0_RX_D0_EP4                (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,4)))
+#define TSB_UDFS2_EP0MSZ_DSET                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,12)))
+#define TSB_UDFS2_EP0MSZ_TX_0DATA                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,15)))
+#define TSB_UDFS2_EP0STS_EP0_MASK                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0STS,15)))
+#define TSB_UDFS2_EP1MSZ_DSET                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,12)))
+#define TSB_UDFS2_EP1MSZ_TX_0DATA                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,15)))
+#define TSB_UDFS2_EP1STS_DIR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,7)))
+#define TSB_UDFS2_EP1STS_DISABLE                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,8)))
+#define TSB_UDFS2_EP1STS_BUS_SEL                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,14)))
+#define TSB_UDFS2_EP1STS_PKT_MODE                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,15)))
+#define TSB_UDFS2_EP2MSZ_DSET                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,12)))
+#define TSB_UDFS2_EP2MSZ_TX_0DATA                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,15)))
+#define TSB_UDFS2_EP2STS_DIR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,7)))
+#define TSB_UDFS2_EP2STS_DISABLE                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,8)))
+#define TSB_UDFS2_EP2STS_BUS_SEL                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,14)))
+#define TSB_UDFS2_EP2STS_PKT_MODE                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,15)))
+#define TSB_UDFS2_EP3MSZ_DSET                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,12)))
+#define TSB_UDFS2_EP3MSZ_TX_0DATA                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,15)))
+#define TSB_UDFS2_EP3STS_DIR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,7)))
+#define TSB_UDFS2_EP3STS_DISABLE                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,8)))
+#define TSB_UDFS2_EP3STS_BUS_SEL                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,14)))
+#define TSB_UDFS2_EP3STS_PKT_MODE                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,15)))
+#define TSB_UDFS2_EP4MSZ_DSET                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,12)))
+#define TSB_UDFS2_EP4MSZ_TX_0DATA                 (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,15)))
+#define TSB_UDFS2_EP4STS_DIR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,7)))
+#define TSB_UDFS2_EP4STS_DISABLE                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,8)))
+#define TSB_UDFS2_EP4STS_BUS_SEL                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,14)))
+#define TSB_UDFS2_EP4STS_PKT_MODE                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,15)))
+#define TSB_UDFS2_INTNAK_I_EP1                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,1)))
+#define TSB_UDFS2_INTNAK_I_EP2                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,2)))
+#define TSB_UDFS2_INTNAK_I_EP3                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,3)))
+#define TSB_UDFS2_INTNAKMSK_M_EP1                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,1)))
+#define TSB_UDFS2_INTNAKMSK_M_EP2                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,2)))
+#define TSB_UDFS2_INTNAKMSK_M_EP3                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,3)))
+
+
+/* AO Area register1 */
+#define TSB_INTIFAO_STOP2INT_032_INT032EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,0)))
+#define TSB_INTIFAO_STOP2INT_032_INT032PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,4)))
+#define TSB_INTIFAO_STOP2INT_032_INT032NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,5)))
+#define TSB_INTIFAO_STOP2INT_032_INT032PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,6)))
+#define TSB_INTIFAO_STOP2INT_032_INT032NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,7)))
+#define TSB_INTIFAO_STOP2INT_033_INT033EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,0)))
+#define TSB_INTIFAO_STOP2INT_033_INT033PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,4)))
+#define TSB_INTIFAO_STOP2INT_033_INT033NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,5)))
+#define TSB_INTIFAO_STOP2INT_033_INT033PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,6)))
+#define TSB_INTIFAO_STOP2INT_033_INT033NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,7)))
+#define TSB_INTIFAO_STOP2INT_034_INT034EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,0)))
+#define TSB_INTIFAO_STOP2INT_034_INT034PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,4)))
+#define TSB_INTIFAO_STOP2INT_034_INT034NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,5)))
+#define TSB_INTIFAO_STOP2INT_034_INT034PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,6)))
+#define TSB_INTIFAO_STOP2INT_034_INT034NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,7)))
+#define TSB_INTIFAO_STOP2INT_035_INT035EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,0)))
+#define TSB_INTIFAO_STOP2INT_035_INT035PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,4)))
+#define TSB_INTIFAO_STOP2INT_035_INT035NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,5)))
+#define TSB_INTIFAO_STOP2INT_035_INT035PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,6)))
+#define TSB_INTIFAO_STOP2INT_035_INT035NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,7)))
+#define TSB_INTIFAO_STOP2INT_036_INT036EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,0)))
+#define TSB_INTIFAO_STOP2INT_036_INT036PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,4)))
+#define TSB_INTIFAO_STOP2INT_036_INT036NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,5)))
+#define TSB_INTIFAO_STOP2INT_036_INT036PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,6)))
+#define TSB_INTIFAO_STOP2INT_036_INT036NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,7)))
+#define TSB_INTIFAO_STOP2INT_037_INT037EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,0)))
+#define TSB_INTIFAO_STOP2INT_037_INT037PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,4)))
+#define TSB_INTIFAO_STOP2INT_037_INT037NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,5)))
+#define TSB_INTIFAO_STOP2INT_037_INT037PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,6)))
+#define TSB_INTIFAO_STOP2INT_037_INT037NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,7)))
+#define TSB_INTIFAO_STOP2INT_038_INT038EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,0)))
+#define TSB_INTIFAO_STOP2INT_038_INT038PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,4)))
+#define TSB_INTIFAO_STOP2INT_038_INT038NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,5)))
+#define TSB_INTIFAO_STOP2INT_038_INT038PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,6)))
+#define TSB_INTIFAO_STOP2INT_038_INT038NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,7)))
+#define TSB_INTIFAO_STOP2INT_039_INT039EN         (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,0)))
+#define TSB_INTIFAO_STOP2INT_039_INT039PFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,4)))
+#define TSB_INTIFAO_STOP2INT_039_INT039NFLG       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,5)))
+#define TSB_INTIFAO_STOP2INT_039_INT039PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,6)))
+#define TSB_INTIFAO_STOP2INT_039_INT039NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,7)))
+
+
+/* AO Area register2 */
+#define TSB_AOREG_RSTFLG_PORF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,0)))
+#define TSB_AOREG_RSTFLG_PINRSTF                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,3)))
+#define TSB_AOREG_RSTFLG_LVDRSTF                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,5)))
+#define TSB_AOREG_RSTFLG1_SYSRSTF                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,0)))
+#define TSB_AOREG_RSTFLG1_WDTRSTF                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,2)))
+
+
+/* I2C Wakeup I/F register */
+#define TSB_I2CS_WUPCR1_INTEND                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,0)))
+#define TSB_I2CS_WUPCR1_GC                        (*((uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,1)))
+#define TSB_I2CS_WUPCR1_RW                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,3)))
+#define TSB_I2CS_WUPCR1_I2RES                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,4)))
+#define TSB_I2CS_WUPCR1_ACK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,5)))
+#define TSB_I2CS_WUPCR1_SGCDI                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,6)))
+#define TSB_I2CS_WUPCR1_BUSY                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,7)))
+#define TSB_I2CS_WUPCR3_WUPSA2EN                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR3,0)))
+#define TSB_I2CS_WUPSL_WUPSA                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,1)))
+#define TSB_I2CS_WUPSL_WUPSA2                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,2)))
+
+
+/* DMA Controller */
+#define TSB_DMA_STATUS_MASTER_ENABLE              (*((__I  uint32_t *)BITBAND_PERI(&TSB_DMA->STATUS,0)))
+#define TSB_DMA_CFG_MASTER_ENABLE                 (*((__O  uint32_t *)BITBAND_PERI(&TSB_DMA->CFG,0)))
+#define TSB_DMA_ERRCLR_ERR_CLR                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMA->ERRCLR,0)))
+
+
+/* Timer D (Unit0) */
+#define TSB_TD0_RUN_TDRUN                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_TD0->RUN,0)))
+#define TSB_TD0_CR_TDRDE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,2)))
+#define TSB_TD0_CR_TDMDPT00                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,4)))
+#define TSB_TD0_CR_TDMDPT01                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,8)))
+#define TSB_TD0_MOD_TDCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,4)))
+#define TSB_TD0_MOD_TDIV0                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,6)))
+#define TSB_TD0_MOD_TDIV1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,7)))
+#define TSB_TD0_DMA_DMAEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->DMA,0)))
+#define TSB_TD0_RG2_DIR                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG2,31)))
+#define TSB_TD0_RG4_DIR                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG4,31)))
+#define TSB_TD0_HSWB0_OUTV0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB0,2)))
+#define TSB_TD0_HSWB1_OUTV1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB1,2)))
+#define TSB_TD0_CP2_DIR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD0->CP2,31)))
+#define TSB_TD0_CP4_DIR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD0->CP4,31)))
+#define TSB_TD0_HSW0_OUTV0                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD0->HSW0,2)))
+#define TSB_TD0_HSW1_OUTV1                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD0->HSW1,2)))
+
+
+/* Timer D common */
+#define TSB_TD_BCR_TDSFT00                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,0)))
+#define TSB_TD_BCR_TDSFT01                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,1)))
+#define TSB_TD_BCR_TDSFT10                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,2)))
+#define TSB_TD_BCR_TDSFT11                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,3)))
+#define TSB_TD_BCR_PHSCHG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,4)))
+#define TSB_TD_EN_TDHALT                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,5)))
+#define TSB_TD_EN_TDEN0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,6)))
+#define TSB_TD_EN_TDEN1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,7)))
+
+
+/* Timer D (Unit1) */
+#define TSB_TD1_RG2_DIR                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG2,31)))
+#define TSB_TD1_RG4_DIR                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG4,31)))
+#define TSB_TD1_HSWB0_OUTV0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB0,2)))
+#define TSB_TD1_HSWB1_OUTV1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB1,2)))
+#define TSB_TD1_RUN_TDRUN                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_TD1->RUN,0)))
+#define TSB_TD1_CR_TDRDE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,2)))
+#define TSB_TD1_CR_TDMDPT10                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,4)))
+#define TSB_TD1_CR_TDMDPT11                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,8)))
+#define TSB_TD1_MOD_TDCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,4)))
+#define TSB_TD1_MOD_TDIV0                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,6)))
+#define TSB_TD1_MOD_TDIV1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,7)))
+#define TSB_TD1_DMA_DMAEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->DMA,0)))
+#define TSB_TD1_CP2_DIR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD1->CP2,31)))
+#define TSB_TD1_CP4_DIR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD1->CP4,31)))
+#define TSB_TD1_HSW0_OUTV0                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD1->HSW0,2)))
+#define TSB_TD1_HSW1_OUTV1                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TD1->HSW1,2)))
+
+
+/* 16-bit TimerA */
+#define TSB_T16A0_EN_HALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->EN,1)))
+#define TSB_T16A0_RUN_RUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->RUN,0)))
+#define TSB_T16A0_CR_CLK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,0)))
+#define TSB_T16A0_CR_FFEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,7)))
+
+#define TSB_T16A1_EN_HALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->EN,1)))
+#define TSB_T16A1_RUN_RUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->RUN,0)))
+#define TSB_T16A1_CR_CLK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,0)))
+#define TSB_T16A1_CR_FFEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,7)))
+
+
+/* Serial Interface (TSPI) */
+#define TSB_TSPI0_CR0_TSPIE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0)))
+#define TSB_TSPI0_CR1_CSSEL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,8)))
+#define TSB_TSPI0_CR1_MSTR                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12)))
+#define TSB_TSPI0_CR1_TSPIMS                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13)))
+#define TSB_TSPI0_CR1_TRXE                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14)))
+#define TSB_TSPI0_CR2_DMARE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0)))
+#define TSB_TSPI0_CR2_DMATE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1)))
+#define TSB_TSPI0_CR2_INTERR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2)))
+#define TSB_TSPI0_CR2_INTRXWE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4)))
+#define TSB_TSPI0_CR2_INTRXFE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5)))
+#define TSB_TSPI0_CR2_INTTXWE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6)))
+#define TSB_TSPI0_CR2_INTTXFE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7)))
+#define TSB_TSPI0_CR2_TXDEMP                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21)))
+#define TSB_TSPI0_CR3_RFFLLCLR                    (*((__O  uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0)))
+#define TSB_TSPI0_CR3_TFEMPCLR                    (*((__O  uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1)))
+#define TSB_TSPI0_FMTR0_CS0POL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,8)))
+#define TSB_TSPI0_FMTR0_CKPOL                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14)))
+#define TSB_TSPI0_FMTR0_DIR                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31)))
+#define TSB_TSPI0_FMTR1_VPM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0)))
+#define TSB_TSPI0_FMTR1_VPE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1)))
+#define TSB_TSPI0_SR_RFFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4)))
+#define TSB_TSPI0_SR_INTRXFF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5)))
+#define TSB_TSPI0_SR_RXEND                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6)))
+#define TSB_TSPI0_SR_RXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7)))
+#define TSB_TSPI0_SR_TFEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20)))
+#define TSB_TSPI0_SR_INTTXFF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21)))
+#define TSB_TSPI0_SR_TXEND                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22)))
+#define TSB_TSPI0_SR_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23)))
+#define TSB_TSPI0_SR_TSPISUE                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31)))
+#define TSB_TSPI0_ERR_PERR                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,9)))
+#define TSB_TSPI0_ERR_OVRERR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,10)))
+#define TSB_TSPI0_ERR_UDRERR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,11)))
+
+
+/* I2C  */
+#define TSB_I2C0_CR1_NOACK                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3)))
+#define TSB_I2C0_CR1_ACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4)))
+#define TSB_I2C0_AR_ALS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0)))
+#define TSB_I2C0_CR2_I2CM                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3)))
+#define TSB_I2C0_CR2_PIN                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4)))
+#define TSB_I2C0_CR2_BB                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5)))
+#define TSB_I2C0_CR2_TRX                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6)))
+#define TSB_I2C0_CR2_MST                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7)))
+#define TSB_I2C0_SR_LRB                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0)))
+#define TSB_I2C0_SR_ADO                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1)))
+#define TSB_I2C0_SR_AAS                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2)))
+#define TSB_I2C0_SR_AL                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3)))
+#define TSB_I2C0_SR_PIN                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4)))
+#define TSB_I2C0_SR_BB                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5)))
+#define TSB_I2C0_SR_TRX                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6)))
+#define TSB_I2C0_SR_MST                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7)))
+#define TSB_I2C0_IE_INTI2C                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0)))
+#define TSB_I2C0_IE_INTI2CAL                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1)))
+#define TSB_I2C0_IE_INTI2CBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2)))
+#define TSB_I2C0_IE_INTNACK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3)))
+#define TSB_I2C0_IE_DMARI2CRX                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4)))
+#define TSB_I2C0_IE_DMARI2CTX                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5)))
+#define TSB_I2C0_IE_SELPINCD                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6)))
+#define TSB_I2C0_ST_I2C                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0)))
+#define TSB_I2C0_ST_I2CAL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1)))
+#define TSB_I2C0_ST_I2CBF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2)))
+#define TSB_I2C0_ST_NACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3)))
+#define TSB_I2C0_OP_MFACK                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0)))
+#define TSB_I2C0_OP_SREN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1)))
+#define TSB_I2C0_OP_GCDI                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2)))
+#define TSB_I2C0_OP_RSTA                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3)))
+#define TSB_I2C0_OP_NFSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4)))
+#define TSB_I2C0_OP_SAST                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5)))
+#define TSB_I2C0_OP_SA2ST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6)))
+#define TSB_I2C0_PM_SCL                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0)))
+#define TSB_I2C0_PM_SDA                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1)))
+#define TSB_I2C0_AR2_SA2EN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0)))
+
+#define TSB_I2C1_CR1_NOACK                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3)))
+#define TSB_I2C1_CR1_ACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4)))
+#define TSB_I2C1_AR_ALS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0)))
+#define TSB_I2C1_CR2_I2CM                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3)))
+#define TSB_I2C1_CR2_PIN                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4)))
+#define TSB_I2C1_CR2_BB                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5)))
+#define TSB_I2C1_CR2_TRX                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6)))
+#define TSB_I2C1_CR2_MST                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7)))
+#define TSB_I2C1_SR_LRB                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0)))
+#define TSB_I2C1_SR_ADO                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1)))
+#define TSB_I2C1_SR_AAS                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2)))
+#define TSB_I2C1_SR_AL                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3)))
+#define TSB_I2C1_SR_PIN                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4)))
+#define TSB_I2C1_SR_BB                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5)))
+#define TSB_I2C1_SR_TRX                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6)))
+#define TSB_I2C1_SR_MST                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7)))
+#define TSB_I2C1_IE_INTI2C                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0)))
+#define TSB_I2C1_IE_INTI2CAL                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1)))
+#define TSB_I2C1_IE_INTI2CBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2)))
+#define TSB_I2C1_IE_INTNACK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3)))
+#define TSB_I2C1_IE_DMARI2CRX                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4)))
+#define TSB_I2C1_IE_DMARI2CTX                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5)))
+#define TSB_I2C1_IE_SELPINCD                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6)))
+#define TSB_I2C1_ST_I2C                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0)))
+#define TSB_I2C1_ST_I2CAL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1)))
+#define TSB_I2C1_ST_I2CBF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2)))
+#define TSB_I2C1_ST_NACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3)))
+#define TSB_I2C1_OP_MFACK                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0)))
+#define TSB_I2C1_OP_SREN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1)))
+#define TSB_I2C1_OP_GCDI                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2)))
+#define TSB_I2C1_OP_RSTA                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3)))
+#define TSB_I2C1_OP_NFSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4)))
+#define TSB_I2C1_OP_SAST                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5)))
+#define TSB_I2C1_OP_SA2ST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6)))
+#define TSB_I2C1_PM_SCL                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0)))
+#define TSB_I2C1_PM_SDA                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1)))
+#define TSB_I2C1_AR2_SA2EN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0)))
+
+
+/* Port A */
+#define TSB_PA_DATA_PA0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0)))
+#define TSB_PA_DATA_PA1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1)))
+#define TSB_PA_DATA_PA2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2)))
+#define TSB_PA_DATA_PA3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3)))
+#define TSB_PA_DATA_PA4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4)))
+#define TSB_PA_DATA_PA5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5)))
+#define TSB_PA_DATA_PA6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6)))
+#define TSB_PA_DATA_PA7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7)))
+#define TSB_PA_CR_PA0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0)))
+#define TSB_PA_CR_PA1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1)))
+#define TSB_PA_CR_PA2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2)))
+#define TSB_PA_CR_PA3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3)))
+#define TSB_PA_CR_PA4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4)))
+#define TSB_PA_CR_PA5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5)))
+#define TSB_PA_CR_PA6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6)))
+#define TSB_PA_CR_PA7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7)))
+#define TSB_PA_FR1_PA7F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7)))
+#define TSB_PA_OD_PA0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0)))
+#define TSB_PA_OD_PA1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1)))
+#define TSB_PA_OD_PA2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2)))
+#define TSB_PA_OD_PA3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3)))
+#define TSB_PA_OD_PA4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4)))
+#define TSB_PA_OD_PA5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5)))
+#define TSB_PA_OD_PA6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6)))
+#define TSB_PA_OD_PA7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7)))
+#define TSB_PA_PUP_PA0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0)))
+#define TSB_PA_PUP_PA1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1)))
+#define TSB_PA_PUP_PA2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2)))
+#define TSB_PA_PUP_PA3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3)))
+#define TSB_PA_PUP_PA4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4)))
+#define TSB_PA_PUP_PA5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5)))
+#define TSB_PA_PUP_PA6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6)))
+#define TSB_PA_PUP_PA7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7)))
+#define TSB_PA_PDN_PA0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0)))
+#define TSB_PA_PDN_PA1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1)))
+#define TSB_PA_PDN_PA2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2)))
+#define TSB_PA_PDN_PA3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3)))
+#define TSB_PA_PDN_PA4DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4)))
+#define TSB_PA_PDN_PA5DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5)))
+#define TSB_PA_PDN_PA6DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6)))
+#define TSB_PA_PDN_PA7DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7)))
+#define TSB_PA_IE_PA0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0)))
+#define TSB_PA_IE_PA1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1)))
+#define TSB_PA_IE_PA2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2)))
+#define TSB_PA_IE_PA3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3)))
+#define TSB_PA_IE_PA4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4)))
+#define TSB_PA_IE_PA5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5)))
+#define TSB_PA_IE_PA6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6)))
+#define TSB_PA_IE_PA7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7)))
+
+
+/* Port B */
+#define TSB_PB_DATA_PB0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0)))
+#define TSB_PB_DATA_PB1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1)))
+#define TSB_PB_DATA_PB2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2)))
+#define TSB_PB_DATA_PB3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3)))
+#define TSB_PB_CR_PB0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0)))
+#define TSB_PB_CR_PB1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1)))
+#define TSB_PB_CR_PB2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2)))
+#define TSB_PB_CR_PB3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3)))
+#define TSB_PB_OD_PB0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0)))
+#define TSB_PB_OD_PB1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1)))
+#define TSB_PB_OD_PB2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2)))
+#define TSB_PB_OD_PB3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3)))
+#define TSB_PB_PUP_PB0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0)))
+#define TSB_PB_PUP_PB1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1)))
+#define TSB_PB_PUP_PB2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2)))
+#define TSB_PB_PUP_PB3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3)))
+#define TSB_PB_PDN_PB0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0)))
+#define TSB_PB_PDN_PB1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1)))
+#define TSB_PB_PDN_PB2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2)))
+#define TSB_PB_PDN_PB3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3)))
+#define TSB_PB_IE_PB0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0)))
+#define TSB_PB_IE_PB1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1)))
+#define TSB_PB_IE_PB2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2)))
+#define TSB_PB_IE_PB3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3)))
+
+
+/* Port C */
+#define TSB_PC_DATA_PC0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0)))
+#define TSB_PC_DATA_PC1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1)))
+#define TSB_PC_DATA_PC2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2)))
+#define TSB_PC_DATA_PC3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3)))
+#define TSB_PC_DATA_PC4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4)))
+#define TSB_PC_DATA_PC5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5)))
+#define TSB_PC_CR_PC0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0)))
+#define TSB_PC_CR_PC1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1)))
+#define TSB_PC_CR_PC2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2)))
+#define TSB_PC_CR_PC3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3)))
+#define TSB_PC_CR_PC4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4)))
+#define TSB_PC_CR_PC5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5)))
+#define TSB_PC_FR1_PC0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0)))
+#define TSB_PC_FR1_PC1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1)))
+#define TSB_PC_FR1_PC2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2)))
+#define TSB_PC_FR1_PC3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3)))
+#define TSB_PC_FR1_PC4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4)))
+#define TSB_PC_FR1_PC5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5)))
+#define TSB_PC_OD_PC0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0)))
+#define TSB_PC_OD_PC1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1)))
+#define TSB_PC_OD_PC2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2)))
+#define TSB_PC_OD_PC3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3)))
+#define TSB_PC_OD_PC4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4)))
+#define TSB_PC_OD_PC5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5)))
+#define TSB_PC_PUP_PC0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0)))
+#define TSB_PC_PUP_PC1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1)))
+#define TSB_PC_PUP_PC2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2)))
+#define TSB_PC_PUP_PC3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3)))
+#define TSB_PC_PUP_PC4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4)))
+#define TSB_PC_PUP_PC5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5)))
+#define TSB_PC_PDN_PC0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0)))
+#define TSB_PC_PDN_PC1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1)))
+#define TSB_PC_PDN_PC2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2)))
+#define TSB_PC_PDN_PC3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3)))
+#define TSB_PC_PDN_PC4DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4)))
+#define TSB_PC_PDN_PC5DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5)))
+#define TSB_PC_SEL_PC0SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,0)))
+#define TSB_PC_SEL_PC1SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,1)))
+#define TSB_PC_IE_PC0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0)))
+#define TSB_PC_IE_PC1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1)))
+#define TSB_PC_IE_PC2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2)))
+#define TSB_PC_IE_PC3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3)))
+#define TSB_PC_IE_PC4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4)))
+#define TSB_PC_IE_PC5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5)))
+
+
+/* Port D */
+#define TSB_PD_DATA_PD0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0)))
+#define TSB_PD_DATA_PD1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1)))
+#define TSB_PD_DATA_PD2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2)))
+#define TSB_PD_DATA_PD3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3)))
+#define TSB_PD_DATA_PD4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4)))
+#define TSB_PD_DATA_PD5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5)))
+#define TSB_PD_CR_PD0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0)))
+#define TSB_PD_CR_PD1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1)))
+#define TSB_PD_CR_PD2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2)))
+#define TSB_PD_CR_PD3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3)))
+#define TSB_PD_CR_PD4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4)))
+#define TSB_PD_CR_PD5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5)))
+#define TSB_PD_FR1_PD0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0)))
+#define TSB_PD_FR1_PD1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1)))
+#define TSB_PD_FR1_PD2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2)))
+#define TSB_PD_FR1_PD3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3)))
+#define TSB_PD_FR1_PD4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4)))
+#define TSB_PD_FR2_PD0F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0)))
+#define TSB_PD_FR2_PD1F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1)))
+#define TSB_PD_FR2_PD2F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,2)))
+#define TSB_PD_FR2_PD3F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3)))
+#define TSB_PD_OD_PD0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0)))
+#define TSB_PD_OD_PD1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1)))
+#define TSB_PD_OD_PD2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2)))
+#define TSB_PD_OD_PD3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3)))
+#define TSB_PD_OD_PD4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4)))
+#define TSB_PD_OD_PD5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5)))
+#define TSB_PD_PUP_PD0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0)))
+#define TSB_PD_PUP_PD1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1)))
+#define TSB_PD_PUP_PD2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2)))
+#define TSB_PD_PUP_PD3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3)))
+#define TSB_PD_PUP_PD4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4)))
+#define TSB_PD_PUP_PD5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5)))
+#define TSB_PD_PDN_PD0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0)))
+#define TSB_PD_PDN_PD1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1)))
+#define TSB_PD_PDN_PD2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2)))
+#define TSB_PD_PDN_PD3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3)))
+#define TSB_PD_PDN_PD4DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4)))
+#define TSB_PD_PDN_PD5DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5)))
+#define TSB_PD_SEL_PD4SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,4)))
+#define TSB_PD_SEL_PD5SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,5)))
+#define TSB_PD_IE_PD0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0)))
+#define TSB_PD_IE_PD1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1)))
+#define TSB_PD_IE_PD2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2)))
+#define TSB_PD_IE_PD3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3)))
+#define TSB_PD_IE_PD4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4)))
+#define TSB_PD_IE_PD5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5)))
+
+
+/* Port E */
+#define TSB_PE_DATA_PE0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0)))
+#define TSB_PE_DATA_PE1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1)))
+#define TSB_PE_DATA_PE2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2)))
+#define TSB_PE_DATA_PE3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3)))
+#define TSB_PE_DATA_PE4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4)))
+#define TSB_PE_DATA_PE5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5)))
+#define TSB_PE_CR_PE0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0)))
+#define TSB_PE_CR_PE1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1)))
+#define TSB_PE_CR_PE2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2)))
+#define TSB_PE_CR_PE3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3)))
+#define TSB_PE_CR_PE4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4)))
+#define TSB_PE_CR_PE5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5)))
+#define TSB_PE_FR1_PE0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0)))
+#define TSB_PE_FR1_PE1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1)))
+#define TSB_PE_FR1_PE2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2)))
+#define TSB_PE_FR1_PE3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3)))
+#define TSB_PE_FR1_PE4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4)))
+#define TSB_PE_FR1_PE5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5)))
+#define TSB_PE_FR2_PE1F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,1)))
+#define TSB_PE_OD_PE0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0)))
+#define TSB_PE_OD_PE1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1)))
+#define TSB_PE_OD_PE2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2)))
+#define TSB_PE_OD_PE3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3)))
+#define TSB_PE_OD_PE4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4)))
+#define TSB_PE_OD_PE5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5)))
+#define TSB_PE_PUP_PE0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0)))
+#define TSB_PE_PUP_PE1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1)))
+#define TSB_PE_PUP_PE2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2)))
+#define TSB_PE_PUP_PE3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3)))
+#define TSB_PE_PUP_PE4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4)))
+#define TSB_PE_PUP_PE5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5)))
+#define TSB_PE_PDN_PE0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0)))
+#define TSB_PE_PDN_PE1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1)))
+#define TSB_PE_PDN_PE2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2)))
+#define TSB_PE_PDN_PE3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3)))
+#define TSB_PE_PDN_PE4DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4)))
+#define TSB_PE_PDN_PE5DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5)))
+#define TSB_PE_IE_PE0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0)))
+#define TSB_PE_IE_PE1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1)))
+#define TSB_PE_IE_PE2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2)))
+#define TSB_PE_IE_PE3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3)))
+#define TSB_PE_IE_PE4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4)))
+#define TSB_PE_IE_PE5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5)))
+
+
+/* Port F  */
+#define TSB_PF_DATA_PF0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0)))
+#define TSB_PF_DATA_PF1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1)))
+#define TSB_PF_DATA_PF2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2)))
+#define TSB_PF_DATA_PF3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3)))
+#define TSB_PF_DATA_PF4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4)))
+#define TSB_PF_DATA_PF5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5)))
+#define TSB_PF_DATA_PF6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6)))
+#define TSB_PF_DATA_PF7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7)))
+#define TSB_PF_CR_PF0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0)))
+#define TSB_PF_CR_PF1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1)))
+#define TSB_PF_CR_PF2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2)))
+#define TSB_PF_CR_PF3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3)))
+#define TSB_PF_CR_PF4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4)))
+#define TSB_PF_CR_PF5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5)))
+#define TSB_PF_CR_PF6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6)))
+#define TSB_PF_CR_PF7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7)))
+#define TSB_PF_FR1_PF0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0)))
+#define TSB_PF_FR1_PF1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1)))
+#define TSB_PF_FR1_PF2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,2)))
+#define TSB_PF_FR1_PF3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3)))
+#define TSB_PF_FR1_PF4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4)))
+#define TSB_PF_FR1_PF5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5)))
+#define TSB_PF_FR2_PF0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0)))
+#define TSB_PF_OD_PF0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0)))
+#define TSB_PF_OD_PF1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1)))
+#define TSB_PF_OD_PF2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2)))
+#define TSB_PF_OD_PF3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3)))
+#define TSB_PF_OD_PF4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4)))
+#define TSB_PF_OD_PF5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5)))
+#define TSB_PF_OD_PF6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6)))
+#define TSB_PF_OD_PF7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7)))
+#define TSB_PF_PUP_PF0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0)))
+#define TSB_PF_PUP_PF1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1)))
+#define TSB_PF_PUP_PF2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2)))
+#define TSB_PF_PUP_PF3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3)))
+#define TSB_PF_PUP_PF4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4)))
+#define TSB_PF_PUP_PF5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5)))
+#define TSB_PF_PUP_PF6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6)))
+#define TSB_PF_PUP_PF7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7)))
+#define TSB_PF_PDN_PF0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0)))
+#define TSB_PF_PDN_PF1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1)))
+#define TSB_PF_PDN_PF2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2)))
+#define TSB_PF_PDN_PF3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3)))
+#define TSB_PF_PDN_PF4DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4)))
+#define TSB_PF_PDN_PF5DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5)))
+#define TSB_PF_PDN_PF6DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6)))
+#define TSB_PF_PDN_PF7DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7)))
+#define TSB_PF_IE_PF0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0)))
+#define TSB_PF_IE_PF1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1)))
+#define TSB_PF_IE_PF2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2)))
+#define TSB_PF_IE_PF3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3)))
+#define TSB_PF_IE_PF4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4)))
+#define TSB_PF_IE_PF5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5)))
+#define TSB_PF_IE_PF6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6)))
+#define TSB_PF_IE_PF7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7)))
+
+
+/* Port G */
+#define TSB_PG_DATA_PG0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0)))
+#define TSB_PG_DATA_PG1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1)))
+#define TSB_PG_CR_PG0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0)))
+#define TSB_PG_CR_PG1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1)))
+#define TSB_PG_FR1_PG0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0)))
+#define TSB_PG_FR1_PG1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1)))
+#define TSB_PG_OD_PG0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0)))
+#define TSB_PG_OD_PG1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1)))
+#define TSB_PG_PUP_PG0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0)))
+#define TSB_PG_PUP_PG1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1)))
+#define TSB_PG_PDN_PG0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0)))
+#define TSB_PG_PDN_PG1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1)))
+#define TSB_PG_SEL_PG0SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,0)))
+#define TSB_PG_SEL_PG1SEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,1)))
+#define TSB_PG_IE_PG0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0)))
+#define TSB_PG_IE_PG1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1)))
+
+
+/* Port H */
+#define TSB_PH_DATA_PH0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0)))
+#define TSB_PH_DATA_PH1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1)))
+#define TSB_PH_DATA_PH2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2)))
+#define TSB_PH_DATA_PH3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3)))
+#define TSB_PH_CR_PH0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0)))
+#define TSB_PH_CR_PH1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1)))
+#define TSB_PH_CR_PH2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2)))
+#define TSB_PH_CR_PH3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3)))
+#define TSB_PH_FR1_PH0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0)))
+#define TSB_PH_FR1_PH1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1)))
+#define TSB_PH_FR1_PH2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2)))
+#define TSB_PH_FR1_PH3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3)))
+#define TSB_PH_OD_PH0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0)))
+#define TSB_PH_OD_PH1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1)))
+#define TSB_PH_OD_PH2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2)))
+#define TSB_PH_OD_PH3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3)))
+#define TSB_PH_PUP_PH0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0)))
+#define TSB_PH_PUP_PH1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1)))
+#define TSB_PH_PUP_PH2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2)))
+#define TSB_PH_PUP_PH3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3)))
+#define TSB_PH_PDN_PH0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0)))
+#define TSB_PH_PDN_PH1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1)))
+#define TSB_PH_PDN_PH2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2)))
+#define TSB_PH_PDN_PH3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3)))
+#define TSB_PH_IE_PH0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0)))
+#define TSB_PH_IE_PH1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1)))
+#define TSB_PH_IE_PH2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2)))
+#define TSB_PH_IE_PH3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3)))
+
+
+/* Port J */
+#define TSB_PJ_DATA_PJ0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0)))
+#define TSB_PJ_DATA_PJ1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1)))
+#define TSB_PJ_DATA_PJ2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2)))
+#define TSB_PJ_DATA_PJ3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3)))
+#define TSB_PJ_CR_PJ0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0)))
+#define TSB_PJ_CR_PJ1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1)))
+#define TSB_PJ_CR_PJ2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2)))
+#define TSB_PJ_CR_PJ3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3)))
+#define TSB_PJ_FR1_PJ0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0)))
+#define TSB_PJ_FR1_PJ1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1)))
+#define TSB_PJ_OD_PJ0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0)))
+#define TSB_PJ_OD_PJ1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1)))
+#define TSB_PJ_OD_PJ2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2)))
+#define TSB_PJ_OD_PJ3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3)))
+#define TSB_PJ_PUP_PJ0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0)))
+#define TSB_PJ_PUP_PJ1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1)))
+#define TSB_PJ_PUP_PJ2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2)))
+#define TSB_PJ_PUP_PJ3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3)))
+#define TSB_PJ_PDN_PJ0DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0)))
+#define TSB_PJ_PDN_PJ1DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1)))
+#define TSB_PJ_PDN_PJ2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2)))
+#define TSB_PJ_PDN_PJ3DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3)))
+#define TSB_PJ_IE_PJ0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0)))
+#define TSB_PJ_IE_PJ1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1)))
+#define TSB_PJ_IE_PJ2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2)))
+#define TSB_PJ_IE_PJ3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3)))
+
+
+/* 16-bit Timer/Event Counter (TB) */
+#define TSB_TB0_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,6)))
+#define TSB_TB0_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,7)))
+#define TSB_TB0_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,0)))
+#define TSB_TB0_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,2)))
+#define TSB_TB0_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,0)))
+#define TSB_TB0_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,1)))
+#define TSB_TB0_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,5)))
+#define TSB_TB0_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,7)))
+#define TSB_TB0_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,3)))
+#define TSB_TB0_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,6)))
+#define TSB_TB0_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,2)))
+#define TSB_TB0_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,3)))
+#define TSB_TB0_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,4)))
+#define TSB_TB0_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,5)))
+#define TSB_TB0_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,0)))
+#define TSB_TB0_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,1)))
+#define TSB_TB0_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,2)))
+#define TSB_TB0_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,0)))
+#define TSB_TB0_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,1)))
+#define TSB_TB0_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,2)))
+
+#define TSB_TB1_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,6)))
+#define TSB_TB1_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,7)))
+#define TSB_TB1_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,0)))
+#define TSB_TB1_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,2)))
+#define TSB_TB1_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,0)))
+#define TSB_TB1_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,1)))
+#define TSB_TB1_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,5)))
+#define TSB_TB1_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,7)))
+#define TSB_TB1_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,3)))
+#define TSB_TB1_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,6)))
+#define TSB_TB1_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,2)))
+#define TSB_TB1_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,3)))
+#define TSB_TB1_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,4)))
+#define TSB_TB1_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,5)))
+#define TSB_TB1_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,0)))
+#define TSB_TB1_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,1)))
+#define TSB_TB1_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,2)))
+#define TSB_TB1_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,0)))
+#define TSB_TB1_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,1)))
+#define TSB_TB1_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,2)))
+
+#define TSB_TB2_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,6)))
+#define TSB_TB2_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,7)))
+#define TSB_TB2_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,0)))
+#define TSB_TB2_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,2)))
+#define TSB_TB2_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,0)))
+#define TSB_TB2_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,1)))
+#define TSB_TB2_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,5)))
+#define TSB_TB2_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,7)))
+#define TSB_TB2_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,3)))
+#define TSB_TB2_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,6)))
+#define TSB_TB2_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,2)))
+#define TSB_TB2_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,3)))
+#define TSB_TB2_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,4)))
+#define TSB_TB2_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,5)))
+#define TSB_TB2_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,0)))
+#define TSB_TB2_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,1)))
+#define TSB_TB2_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,2)))
+#define TSB_TB2_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,0)))
+#define TSB_TB2_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,1)))
+#define TSB_TB2_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,2)))
+
+#define TSB_TB3_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,6)))
+#define TSB_TB3_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,7)))
+#define TSB_TB3_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,0)))
+#define TSB_TB3_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,2)))
+#define TSB_TB3_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,0)))
+#define TSB_TB3_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,1)))
+#define TSB_TB3_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,5)))
+#define TSB_TB3_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,7)))
+#define TSB_TB3_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,3)))
+#define TSB_TB3_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,6)))
+#define TSB_TB3_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,2)))
+#define TSB_TB3_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,3)))
+#define TSB_TB3_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,4)))
+#define TSB_TB3_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,5)))
+#define TSB_TB3_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,0)))
+#define TSB_TB3_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,1)))
+#define TSB_TB3_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,2)))
+#define TSB_TB3_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,0)))
+#define TSB_TB3_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,1)))
+#define TSB_TB3_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,2)))
+
+#define TSB_TB4_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,6)))
+#define TSB_TB4_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,7)))
+#define TSB_TB4_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,0)))
+#define TSB_TB4_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,2)))
+#define TSB_TB4_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,0)))
+#define TSB_TB4_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,1)))
+#define TSB_TB4_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,5)))
+#define TSB_TB4_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,7)))
+#define TSB_TB4_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,3)))
+#define TSB_TB4_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,6)))
+#define TSB_TB4_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,2)))
+#define TSB_TB4_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,3)))
+#define TSB_TB4_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,4)))
+#define TSB_TB4_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,5)))
+#define TSB_TB4_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,0)))
+#define TSB_TB4_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,1)))
+#define TSB_TB4_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,2)))
+#define TSB_TB4_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,0)))
+#define TSB_TB4_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,1)))
+#define TSB_TB4_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,2)))
+
+#define TSB_TB5_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,6)))
+#define TSB_TB5_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,7)))
+#define TSB_TB5_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,0)))
+#define TSB_TB5_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,2)))
+#define TSB_TB5_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,0)))
+#define TSB_TB5_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,1)))
+#define TSB_TB5_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,5)))
+#define TSB_TB5_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,7)))
+#define TSB_TB5_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,3)))
+#define TSB_TB5_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,6)))
+#define TSB_TB5_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,2)))
+#define TSB_TB5_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,3)))
+#define TSB_TB5_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,4)))
+#define TSB_TB5_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,5)))
+#define TSB_TB5_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,0)))
+#define TSB_TB5_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,1)))
+#define TSB_TB5_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,2)))
+#define TSB_TB5_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,0)))
+#define TSB_TB5_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,1)))
+#define TSB_TB5_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,2)))
+
+#define TSB_TB6_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,6)))
+#define TSB_TB6_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,7)))
+#define TSB_TB6_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,0)))
+#define TSB_TB6_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,2)))
+#define TSB_TB6_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,0)))
+#define TSB_TB6_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,1)))
+#define TSB_TB6_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,5)))
+#define TSB_TB6_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,7)))
+#define TSB_TB6_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,3)))
+#define TSB_TB6_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,6)))
+#define TSB_TB6_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,2)))
+#define TSB_TB6_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,3)))
+#define TSB_TB6_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,4)))
+#define TSB_TB6_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,5)))
+#define TSB_TB6_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,0)))
+#define TSB_TB6_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,1)))
+#define TSB_TB6_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,2)))
+#define TSB_TB6_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,0)))
+#define TSB_TB6_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,1)))
+#define TSB_TB6_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,2)))
+
+#define TSB_TB7_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,6)))
+#define TSB_TB7_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,7)))
+#define TSB_TB7_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,0)))
+#define TSB_TB7_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,2)))
+#define TSB_TB7_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,0)))
+#define TSB_TB7_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,1)))
+#define TSB_TB7_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,5)))
+#define TSB_TB7_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,7)))
+#define TSB_TB7_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,3)))
+#define TSB_TB7_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,6)))
+#define TSB_TB7_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,2)))
+#define TSB_TB7_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,3)))
+#define TSB_TB7_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,4)))
+#define TSB_TB7_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,5)))
+#define TSB_TB7_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,0)))
+#define TSB_TB7_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,1)))
+#define TSB_TB7_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,2)))
+#define TSB_TB7_DMA_TBDMAEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,0)))
+#define TSB_TB7_DMA_TBDMAEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,1)))
+#define TSB_TB7_DMA_TBDMAEN2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,2)))
+
+
+/* SC */
+#define TSB_SC0_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,0)))
+#define TSB_SC0_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,1)))
+#define TSB_SC0_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,4)))
+#define TSB_SC0_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,5)))
+#define TSB_SC0_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,6)))
+#define TSB_SC0_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,7)))
+#define TSB_SC0_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->BRCR,6)))
+#define TSB_SC0_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,4)))
+#define TSB_SC0_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,2)))
+#define TSB_SC0_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,3)))
+#define TSB_SC0_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,4)))
+#define TSB_SC0_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,5)))
+#define TSB_SC0_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,6)))
+#define TSB_SC0_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,7)))
+#define TSB_SC0_RST_ROR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->RST,7)))
+#define TSB_SC0_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->TST,7)))
+#define TSB_SC0_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,0)))
+#define TSB_SC0_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,1)))
+#define TSB_SC0_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,2)))
+#define TSB_SC0_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,3)))
+#define TSB_SC0_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,4)))
+#define TSB_SC0_DMA_DMAEN0                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,0)))
+#define TSB_SC0_DMA_DMAEN1                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,1)))
+
+#define TSB_SC1_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,0)))
+#define TSB_SC1_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,1)))
+#define TSB_SC1_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,4)))
+#define TSB_SC1_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,5)))
+#define TSB_SC1_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,6)))
+#define TSB_SC1_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,7)))
+#define TSB_SC1_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->BRCR,6)))
+#define TSB_SC1_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,4)))
+#define TSB_SC1_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,2)))
+#define TSB_SC1_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,3)))
+#define TSB_SC1_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,4)))
+#define TSB_SC1_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,5)))
+#define TSB_SC1_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,6)))
+#define TSB_SC1_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,7)))
+#define TSB_SC1_RST_ROR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->RST,7)))
+#define TSB_SC1_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->TST,7)))
+#define TSB_SC1_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,0)))
+#define TSB_SC1_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,1)))
+#define TSB_SC1_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,2)))
+#define TSB_SC1_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,3)))
+#define TSB_SC1_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,4)))
+#define TSB_SC1_DMA_DMAEN0                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,0)))
+#define TSB_SC1_DMA_DMAEN1                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,1)))
+
+
+/* WDT */
+#define TSB_WD_MOD_RESCR                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,1)))
+#define TSB_WD_MOD_WDTE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,7)))
+#define TSB_WD_FLG_FLG                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_WD->FLG,0)))
+
+
+/* CG */
+#define TSB_CG_OSCCR_IOSCEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0)))
+#define TSB_CG_OSCCR_OSCSEL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8)))
+#define TSB_CG_OSCCR_OSCF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9)))
+#define TSB_CG_PLL0SEL_PLL0ON                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0)))
+#define TSB_CG_PLL0SEL_PPL0SEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1)))
+#define TSB_CG_PLL0SEL_PLL0ST                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2)))
+#define TSB_CG_WUPHCR_WUON                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0)))
+#define TSB_CG_WUPHCR_WUEF                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1)))
+#define TSB_CG_WUPHCR_WUCLK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8)))
+#define TSB_CG_FSYSENA_IPENA07                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7)))
+#define TSB_CG_FSYSENA_IPENA08                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8)))
+#define TSB_CG_FSYSENA_IPENA09                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9)))
+#define TSB_CG_FSYSENA_IPENA10                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10)))
+#define TSB_CG_FSYSENA_IPENA11                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11)))
+#define TSB_CG_FSYSENA_IPENA12                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12)))
+#define TSB_CG_FSYSENA_IPENA13                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13)))
+#define TSB_CG_FSYSENA_IPENA14                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14)))
+#define TSB_CG_FSYSENA_IPENA15                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15)))
+#define TSB_CG_FSYSENA_IPENA16                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16)))
+#define TSB_CG_FSYSENA_IPENA17                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17)))
+#define TSB_CG_FSYSENA_IPENA18                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18)))
+#define TSB_CG_FSYSENB_IPENB28                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,28)))
+#define TSB_CG_FSYSENB_IPENB29                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,29)))
+#define TSB_CG_FSYSENB_IPENB30                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,30)))
+#define TSB_CG_FSYSENB_IPENB31                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31)))
+#define TSB_CG_SPCLKEN_ADCKEN                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16)))
+#define TSB_CG_EXTENDO0_USBENA                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,0)))
+#define TSB_CG_EXTENDO0_USBSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,1)))
+#define TSB_CG_EXTENDO0_EHCLKSEL                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,4)))
+#define TSB_CG_EXTENDO0_DCLKEN                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,5)))
+
+
+/* LVD */
+#define TSB_LVD_CR0_EN                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,0)))
+#define TSB_LVD_CR0_INTSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,4)))
+#define TSB_LVD_CR0_INTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,5)))
+#define TSB_LVD_CR0_RSTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,6)))
+#define TSB_LVD_CR0_ST                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,7)))
+#define TSB_LVD_CR1_EN                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0)))
+#define TSB_LVD_CR1_INTSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4)))
+#define TSB_LVD_CR1_INTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,5)))
+#define TSB_LVD_CR1_RSTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,6)))
+#define TSB_LVD_CR1_ST                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,7)))
+
+
+/* SD Area register1 */
+#define TSB_INTIFSD_STOP1INT_016_INT016EN         (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,0)))
+#define TSB_INTIFSD_STOP1INT_016_INT016PFLG       (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,4)))
+#define TSB_INTIFSD_STOP1INT_016_INT016NFLG       (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,5)))
+#define TSB_INTIFSD_STOP1INT_016_INT016PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,6)))
+#define TSB_INTIFSD_STOP1INT_016_INT016NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,7)))
+#define TSB_INTIFSD_STOP1INT_017_INT017EN         (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,0)))
+#define TSB_INTIFSD_STOP1INT_017_INT017PFLG       (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,4)))
+#define TSB_INTIFSD_STOP1INT_017_INT017NFLG       (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,5)))
+#define TSB_INTIFSD_STOP1INT_017_INT017PCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,6)))
+#define TSB_INTIFSD_STOP1INT_017_INT017NCLR       (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,7)))
+#define TSB_INTIFSD_IDLEINT_018_INT018EN          (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,0)))
+#define TSB_INTIFSD_IDLEINT_018_INT018PFLG        (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,4)))
+#define TSB_INTIFSD_IDLEINT_018_INT018NFLG        (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,5)))
+#define TSB_INTIFSD_IDLEINT_018_INT018PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,6)))
+#define TSB_INTIFSD_IDLEINT_018_INT018NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,7)))
+#define TSB_INTIFSD_IDLEINT_096_INT096EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,0)))
+#define TSB_INTIFSD_IDLEINT_096_INT096PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,4)))
+#define TSB_INTIFSD_IDLEINT_096_INT096NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,5)))
+#define TSB_INTIFSD_IDLEINT_096_INT096PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,6)))
+#define TSB_INTIFSD_IDLEINT_096_INT096NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,7)))
+#define TSB_INTIFSD_IDLEINT_097_INT097EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,0)))
+#define TSB_INTIFSD_IDLEINT_097_INT097PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,4)))
+#define TSB_INTIFSD_IDLEINT_097_INT097NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,5)))
+#define TSB_INTIFSD_IDLEINT_097_INT097PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,6)))
+#define TSB_INTIFSD_IDLEINT_097_INT097NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,7)))
+#define TSB_INTIFSD_IDLEINT_098_INT098EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,0)))
+#define TSB_INTIFSD_IDLEINT_098_INT098PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,4)))
+#define TSB_INTIFSD_IDLEINT_098_INT098NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,5)))
+#define TSB_INTIFSD_IDLEINT_098_INT098PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,6)))
+#define TSB_INTIFSD_IDLEINT_098_INT098NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,7)))
+#define TSB_INTIFSD_IDLEINT_099_INT099EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,0)))
+#define TSB_INTIFSD_IDLEINT_099_INT099PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,4)))
+#define TSB_INTIFSD_IDLEINT_099_INT099NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,5)))
+#define TSB_INTIFSD_IDLEINT_099_INT099PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,6)))
+#define TSB_INTIFSD_IDLEINT_099_INT099NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,7)))
+#define TSB_INTIFSD_IDLEINT_100_INT100EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,0)))
+#define TSB_INTIFSD_IDLEINT_100_INT100PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,4)))
+#define TSB_INTIFSD_IDLEINT_100_INT100NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,5)))
+#define TSB_INTIFSD_IDLEINT_100_INT100PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,6)))
+#define TSB_INTIFSD_IDLEINT_100_INT100NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,7)))
+#define TSB_INTIFSD_IDLEINT_101_INT101EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,0)))
+#define TSB_INTIFSD_IDLEINT_101_INT101PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,4)))
+#define TSB_INTIFSD_IDLEINT_101_INT101NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,5)))
+#define TSB_INTIFSD_IDLEINT_101_INT101PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,6)))
+#define TSB_INTIFSD_IDLEINT_101_INT101NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,7)))
+#define TSB_INTIFSD_IDLEINT_102_INT102EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,0)))
+#define TSB_INTIFSD_IDLEINT_102_INT102PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,4)))
+#define TSB_INTIFSD_IDLEINT_102_INT102NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,5)))
+#define TSB_INTIFSD_IDLEINT_102_INT102PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,6)))
+#define TSB_INTIFSD_IDLEINT_102_INT102NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,7)))
+#define TSB_INTIFSD_IDLEINT_103_INT103EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,0)))
+#define TSB_INTIFSD_IDLEINT_103_INT103PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,4)))
+#define TSB_INTIFSD_IDLEINT_103_INT103NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,5)))
+#define TSB_INTIFSD_IDLEINT_103_INT103PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,6)))
+#define TSB_INTIFSD_IDLEINT_103_INT103NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,7)))
+#define TSB_INTIFSD_IDLEINT_104_INT104EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,0)))
+#define TSB_INTIFSD_IDLEINT_104_INT104PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,4)))
+#define TSB_INTIFSD_IDLEINT_104_INT104NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,5)))
+#define TSB_INTIFSD_IDLEINT_104_INT104PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,6)))
+#define TSB_INTIFSD_IDLEINT_104_INT104NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,7)))
+#define TSB_INTIFSD_IDLEINT_105_INT105EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,0)))
+#define TSB_INTIFSD_IDLEINT_105_INT105PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,4)))
+#define TSB_INTIFSD_IDLEINT_105_INT105NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,5)))
+#define TSB_INTIFSD_IDLEINT_105_INT105PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,6)))
+#define TSB_INTIFSD_IDLEINT_105_INT105NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,7)))
+#define TSB_INTIFSD_IDLEINT_106_INT106EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,0)))
+#define TSB_INTIFSD_IDLEINT_106_INT106PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,4)))
+#define TSB_INTIFSD_IDLEINT_106_INT106NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,5)))
+#define TSB_INTIFSD_IDLEINT_106_INT106PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,6)))
+#define TSB_INTIFSD_IDLEINT_106_INT106NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,7)))
+#define TSB_INTIFSD_IDLEINT_107_INT107EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,0)))
+#define TSB_INTIFSD_IDLEINT_107_INT107PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,4)))
+#define TSB_INTIFSD_IDLEINT_107_INT107NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,5)))
+#define TSB_INTIFSD_IDLEINT_107_INT107PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,6)))
+#define TSB_INTIFSD_IDLEINT_107_INT107NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,7)))
+#define TSB_INTIFSD_IDLEINT_108_INT108EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,0)))
+#define TSB_INTIFSD_IDLEINT_108_INT108PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,4)))
+#define TSB_INTIFSD_IDLEINT_108_INT108NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,5)))
+#define TSB_INTIFSD_IDLEINT_108_INT108PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,6)))
+#define TSB_INTIFSD_IDLEINT_108_INT108NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,7)))
+#define TSB_INTIFSD_IDLEINT_109_INT109EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,0)))
+#define TSB_INTIFSD_IDLEINT_109_INT109PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,4)))
+#define TSB_INTIFSD_IDLEINT_109_INT109NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,5)))
+#define TSB_INTIFSD_IDLEINT_109_INT109PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,6)))
+#define TSB_INTIFSD_IDLEINT_109_INT109NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,7)))
+#define TSB_INTIFSD_IDLEINT_110_INT110EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,0)))
+#define TSB_INTIFSD_IDLEINT_110_INT110PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,4)))
+#define TSB_INTIFSD_IDLEINT_110_INT110NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,5)))
+#define TSB_INTIFSD_IDLEINT_110_INT110PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,6)))
+#define TSB_INTIFSD_IDLEINT_110_INT110NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,7)))
+#define TSB_INTIFSD_IDLEINT_111_INT111EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,0)))
+#define TSB_INTIFSD_IDLEINT_111_INT111PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,4)))
+#define TSB_INTIFSD_IDLEINT_111_INT111NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,5)))
+#define TSB_INTIFSD_IDLEINT_111_INT111PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,6)))
+#define TSB_INTIFSD_IDLEINT_111_INT111NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,7)))
+#define TSB_INTIFSD_IDLEINT_112_INT112EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,0)))
+#define TSB_INTIFSD_IDLEINT_112_INT112PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,4)))
+#define TSB_INTIFSD_IDLEINT_112_INT112NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,5)))
+#define TSB_INTIFSD_IDLEINT_112_INT112PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,6)))
+#define TSB_INTIFSD_IDLEINT_112_INT112NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,7)))
+#define TSB_INTIFSD_IDLEINT_113_INT113EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,0)))
+#define TSB_INTIFSD_IDLEINT_113_INT113PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,4)))
+#define TSB_INTIFSD_IDLEINT_113_INT113NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,5)))
+#define TSB_INTIFSD_IDLEINT_113_INT113PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,6)))
+#define TSB_INTIFSD_IDLEINT_113_INT113NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,7)))
+#define TSB_INTIFSD_IDLEINT_114_INT114EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,0)))
+#define TSB_INTIFSD_IDLEINT_114_INT114PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,4)))
+#define TSB_INTIFSD_IDLEINT_114_INT114NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,5)))
+#define TSB_INTIFSD_IDLEINT_114_INT114PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,6)))
+#define TSB_INTIFSD_IDLEINT_114_INT114NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,7)))
+#define TSB_INTIFSD_IDLEINT_115_INT115EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,0)))
+#define TSB_INTIFSD_IDLEINT_115_INT115PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,4)))
+#define TSB_INTIFSD_IDLEINT_115_INT115NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,5)))
+#define TSB_INTIFSD_IDLEINT_115_INT115PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,6)))
+#define TSB_INTIFSD_IDLEINT_115_INT115NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,7)))
+#define TSB_INTIFSD_IDLEINT_116_INT116EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,0)))
+#define TSB_INTIFSD_IDLEINT_116_INT116PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,4)))
+#define TSB_INTIFSD_IDLEINT_116_INT116NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,5)))
+#define TSB_INTIFSD_IDLEINT_116_INT116PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,6)))
+#define TSB_INTIFSD_IDLEINT_116_INT116NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,7)))
+#define TSB_INTIFSD_IDLEINT_117_INT117EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,0)))
+#define TSB_INTIFSD_IDLEINT_117_INT117PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,4)))
+#define TSB_INTIFSD_IDLEINT_117_INT117NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,5)))
+#define TSB_INTIFSD_IDLEINT_117_INT117PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,6)))
+#define TSB_INTIFSD_IDLEINT_117_INT117NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,7)))
+#define TSB_INTIFSD_IDLEINT_118_INT118EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,0)))
+#define TSB_INTIFSD_IDLEINT_118_INT118PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,4)))
+#define TSB_INTIFSD_IDLEINT_118_INT118NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,5)))
+#define TSB_INTIFSD_IDLEINT_118_INT118PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,6)))
+#define TSB_INTIFSD_IDLEINT_118_INT118NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,7)))
+#define TSB_INTIFSD_IDLEINT_119_INT119EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,0)))
+#define TSB_INTIFSD_IDLEINT_119_INT119PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,4)))
+#define TSB_INTIFSD_IDLEINT_119_INT119NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,5)))
+#define TSB_INTIFSD_IDLEINT_119_INT119PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,6)))
+#define TSB_INTIFSD_IDLEINT_119_INT119NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,7)))
+#define TSB_INTIFSD_IDLEINT_120_INT120EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,0)))
+#define TSB_INTIFSD_IDLEINT_120_INT120PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,4)))
+#define TSB_INTIFSD_IDLEINT_120_INT120NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,5)))
+#define TSB_INTIFSD_IDLEINT_120_INT120PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,6)))
+#define TSB_INTIFSD_IDLEINT_120_INT120NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,7)))
+#define TSB_INTIFSD_IDLEINT_121_INT121EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,0)))
+#define TSB_INTIFSD_IDLEINT_121_INT121PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,4)))
+#define TSB_INTIFSD_IDLEINT_121_INT121NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,5)))
+#define TSB_INTIFSD_IDLEINT_121_INT121PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,6)))
+#define TSB_INTIFSD_IDLEINT_121_INT121NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,7)))
+#define TSB_INTIFSD_IDLEINT_122_INT122EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,0)))
+#define TSB_INTIFSD_IDLEINT_122_INT122PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,4)))
+#define TSB_INTIFSD_IDLEINT_122_INT122NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,5)))
+#define TSB_INTIFSD_IDLEINT_122_INT122PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,6)))
+#define TSB_INTIFSD_IDLEINT_122_INT122NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,7)))
+#define TSB_INTIFSD_IDLEINT_123_INT123EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,0)))
+#define TSB_INTIFSD_IDLEINT_123_INT123PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,4)))
+#define TSB_INTIFSD_IDLEINT_123_INT123NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,5)))
+#define TSB_INTIFSD_IDLEINT_123_INT123PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,6)))
+#define TSB_INTIFSD_IDLEINT_123_INT123NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,7)))
+#define TSB_INTIFSD_IDLEINT_124_INT124EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,0)))
+#define TSB_INTIFSD_IDLEINT_124_INT124PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,4)))
+#define TSB_INTIFSD_IDLEINT_124_INT124NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,5)))
+#define TSB_INTIFSD_IDLEINT_124_INT124PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,6)))
+#define TSB_INTIFSD_IDLEINT_124_INT124NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,7)))
+#define TSB_INTIFSD_IDLEINT_125_INT125EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,0)))
+#define TSB_INTIFSD_IDLEINT_125_INT125PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,4)))
+#define TSB_INTIFSD_IDLEINT_125_INT125NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,5)))
+#define TSB_INTIFSD_IDLEINT_125_INT125PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,6)))
+#define TSB_INTIFSD_IDLEINT_125_INT125NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,7)))
+#define TSB_INTIFSD_IDLEINT_126_INT126EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,0)))
+#define TSB_INTIFSD_IDLEINT_126_INT126PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,4)))
+#define TSB_INTIFSD_IDLEINT_126_INT126NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,5)))
+#define TSB_INTIFSD_IDLEINT_126_INT126PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,6)))
+#define TSB_INTIFSD_IDLEINT_126_INT126NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,7)))
+#define TSB_INTIFSD_IDLEINT_127_INT127EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,0)))
+#define TSB_INTIFSD_IDLEINT_127_INT127PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,4)))
+#define TSB_INTIFSD_IDLEINT_127_INT127NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,5)))
+#define TSB_INTIFSD_IDLEINT_127_INT127PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,6)))
+#define TSB_INTIFSD_IDLEINT_127_INT127NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,7)))
+#define TSB_INTIFSD_IDLEINT_128_INT128EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,0)))
+#define TSB_INTIFSD_IDLEINT_128_INT128PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,4)))
+#define TSB_INTIFSD_IDLEINT_128_INT128NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,5)))
+#define TSB_INTIFSD_IDLEINT_128_INT128PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,6)))
+#define TSB_INTIFSD_IDLEINT_128_INT128NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,7)))
+#define TSB_INTIFSD_IDLEINT_129_INT129EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,0)))
+#define TSB_INTIFSD_IDLEINT_129_INT129PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,4)))
+#define TSB_INTIFSD_IDLEINT_129_INT129NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,5)))
+#define TSB_INTIFSD_IDLEINT_129_INT129PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,6)))
+#define TSB_INTIFSD_IDLEINT_129_INT129NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,7)))
+#define TSB_INTIFSD_IDLEINT_130_INT130EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,0)))
+#define TSB_INTIFSD_IDLEINT_130_INT130PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,4)))
+#define TSB_INTIFSD_IDLEINT_130_INT130NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,5)))
+#define TSB_INTIFSD_IDLEINT_130_INT130PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,6)))
+#define TSB_INTIFSD_IDLEINT_130_INT130NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,7)))
+#define TSB_INTIFSD_IDLEINT_131_INT131EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,0)))
+#define TSB_INTIFSD_IDLEINT_131_INT131PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,4)))
+#define TSB_INTIFSD_IDLEINT_131_INT131NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,5)))
+#define TSB_INTIFSD_IDLEINT_131_INT131PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,6)))
+#define TSB_INTIFSD_IDLEINT_131_INT131NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,7)))
+#define TSB_INTIFSD_IDLEINT_132_INT132EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,0)))
+#define TSB_INTIFSD_IDLEINT_132_INT132PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,4)))
+#define TSB_INTIFSD_IDLEINT_132_INT132NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,5)))
+#define TSB_INTIFSD_IDLEINT_132_INT132PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,6)))
+#define TSB_INTIFSD_IDLEINT_132_INT132NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,7)))
+#define TSB_INTIFSD_IDLEINT_133_INT133EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,0)))
+#define TSB_INTIFSD_IDLEINT_133_INT133PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,4)))
+#define TSB_INTIFSD_IDLEINT_133_INT133NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,5)))
+#define TSB_INTIFSD_IDLEINT_133_INT133PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,6)))
+#define TSB_INTIFSD_IDLEINT_133_INT133NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,7)))
+#define TSB_INTIFSD_IDLEINT_134_INT134EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,0)))
+#define TSB_INTIFSD_IDLEINT_134_INT134PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,4)))
+#define TSB_INTIFSD_IDLEINT_134_INT134NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,5)))
+#define TSB_INTIFSD_IDLEINT_134_INT134PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,6)))
+#define TSB_INTIFSD_IDLEINT_134_INT134NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,7)))
+#define TSB_INTIFSD_IDLEINT_135_INT135EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,0)))
+#define TSB_INTIFSD_IDLEINT_135_INT135PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,4)))
+#define TSB_INTIFSD_IDLEINT_135_INT135NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,5)))
+#define TSB_INTIFSD_IDLEINT_135_INT135PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,6)))
+#define TSB_INTIFSD_IDLEINT_135_INT135NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,7)))
+#define TSB_INTIFSD_IDLEINT_136_INT136EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,0)))
+#define TSB_INTIFSD_IDLEINT_136_INT136PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,4)))
+#define TSB_INTIFSD_IDLEINT_136_INT136NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,5)))
+#define TSB_INTIFSD_IDLEINT_136_INT136PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,6)))
+#define TSB_INTIFSD_IDLEINT_136_INT136NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,7)))
+#define TSB_INTIFSD_IDLEINT_137_INT137EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,0)))
+#define TSB_INTIFSD_IDLEINT_137_INT137PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,4)))
+#define TSB_INTIFSD_IDLEINT_137_INT137NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,5)))
+#define TSB_INTIFSD_IDLEINT_137_INT137PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,6)))
+#define TSB_INTIFSD_IDLEINT_137_INT137NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,7)))
+#define TSB_INTIFSD_IDLEINT_138_INT138EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,0)))
+#define TSB_INTIFSD_IDLEINT_138_INT138PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,4)))
+#define TSB_INTIFSD_IDLEINT_138_INT138NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,5)))
+#define TSB_INTIFSD_IDLEINT_138_INT138PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,6)))
+#define TSB_INTIFSD_IDLEINT_138_INT138NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,7)))
+#define TSB_INTIFSD_IDLEINT_139_INT139EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,0)))
+#define TSB_INTIFSD_IDLEINT_139_INT139PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,4)))
+#define TSB_INTIFSD_IDLEINT_139_INT139NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,5)))
+#define TSB_INTIFSD_IDLEINT_139_INT139PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,6)))
+#define TSB_INTIFSD_IDLEINT_139_INT139NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,7)))
+#define TSB_INTIFSD_IDLEINT_140_INT140EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,0)))
+#define TSB_INTIFSD_IDLEINT_140_INT140PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,4)))
+#define TSB_INTIFSD_IDLEINT_140_INT140NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,5)))
+#define TSB_INTIFSD_IDLEINT_140_INT140PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,6)))
+#define TSB_INTIFSD_IDLEINT_140_INT140NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,7)))
+#define TSB_INTIFSD_IDLEINT_141_INT141EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,0)))
+#define TSB_INTIFSD_IDLEINT_141_INT141PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,4)))
+#define TSB_INTIFSD_IDLEINT_141_INT141NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,5)))
+#define TSB_INTIFSD_IDLEINT_141_INT141PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,6)))
+#define TSB_INTIFSD_IDLEINT_141_INT141NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,7)))
+#define TSB_INTIFSD_IDLEINT_142_INT142EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,0)))
+#define TSB_INTIFSD_IDLEINT_142_INT142PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,4)))
+#define TSB_INTIFSD_IDLEINT_142_INT142NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,5)))
+#define TSB_INTIFSD_IDLEINT_142_INT142PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,6)))
+#define TSB_INTIFSD_IDLEINT_142_INT142NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,7)))
+#define TSB_INTIFSD_IDLEINT_143_INT143EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,0)))
+#define TSB_INTIFSD_IDLEINT_143_INT143PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,4)))
+#define TSB_INTIFSD_IDLEINT_143_INT143NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,5)))
+#define TSB_INTIFSD_IDLEINT_143_INT143PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,6)))
+#define TSB_INTIFSD_IDLEINT_143_INT143NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,7)))
+#define TSB_INTIFSD_IDLEINT_144_INT144EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,0)))
+#define TSB_INTIFSD_IDLEINT_144_INT144PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,4)))
+#define TSB_INTIFSD_IDLEINT_144_INT144NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,5)))
+#define TSB_INTIFSD_IDLEINT_144_INT144PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,6)))
+#define TSB_INTIFSD_IDLEINT_144_INT144NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,7)))
+#define TSB_INTIFSD_IDLEINT_145_INT145EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,0)))
+#define TSB_INTIFSD_IDLEINT_145_INT145PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,4)))
+#define TSB_INTIFSD_IDLEINT_145_INT145NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,5)))
+#define TSB_INTIFSD_IDLEINT_145_INT145PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,6)))
+#define TSB_INTIFSD_IDLEINT_145_INT145NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,7)))
+#define TSB_INTIFSD_IDLEINT_146_INT146EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,0)))
+#define TSB_INTIFSD_IDLEINT_146_INT146PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,4)))
+#define TSB_INTIFSD_IDLEINT_146_INT146NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,5)))
+#define TSB_INTIFSD_IDLEINT_146_INT146PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,6)))
+#define TSB_INTIFSD_IDLEINT_146_INT146NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,7)))
+#define TSB_INTIFSD_IDLEINT_147_INT147EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,0)))
+#define TSB_INTIFSD_IDLEINT_147_INT147PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,4)))
+#define TSB_INTIFSD_IDLEINT_147_INT147NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,5)))
+#define TSB_INTIFSD_IDLEINT_147_INT147PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,6)))
+#define TSB_INTIFSD_IDLEINT_147_INT147NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,7)))
+#define TSB_INTIFSD_IDLEINT_148_INT148EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,0)))
+#define TSB_INTIFSD_IDLEINT_148_INT148PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,4)))
+#define TSB_INTIFSD_IDLEINT_148_INT148NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,5)))
+#define TSB_INTIFSD_IDLEINT_148_INT148PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,6)))
+#define TSB_INTIFSD_IDLEINT_148_INT148NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,7)))
+#define TSB_INTIFSD_IDLEINT_149_INT149EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,0)))
+#define TSB_INTIFSD_IDLEINT_149_INT149PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,4)))
+#define TSB_INTIFSD_IDLEINT_149_INT149NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,5)))
+#define TSB_INTIFSD_IDLEINT_149_INT149PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,6)))
+#define TSB_INTIFSD_IDLEINT_149_INT149NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,7)))
+#define TSB_INTIFSD_IDLEINT_150_INT150EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,0)))
+#define TSB_INTIFSD_IDLEINT_150_INT150PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,4)))
+#define TSB_INTIFSD_IDLEINT_150_INT150NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,5)))
+#define TSB_INTIFSD_IDLEINT_150_INT150PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,6)))
+#define TSB_INTIFSD_IDLEINT_150_INT150NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,7)))
+#define TSB_INTIFSD_IDLEINT_151_INT151EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,0)))
+#define TSB_INTIFSD_IDLEINT_151_INT151PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,4)))
+#define TSB_INTIFSD_IDLEINT_151_INT151NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,5)))
+#define TSB_INTIFSD_IDLEINT_151_INT151PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,6)))
+#define TSB_INTIFSD_IDLEINT_151_INT151NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,7)))
+#define TSB_INTIFSD_IDLEINT_152_INT152EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,0)))
+#define TSB_INTIFSD_IDLEINT_152_INT152PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,4)))
+#define TSB_INTIFSD_IDLEINT_152_INT152NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,5)))
+#define TSB_INTIFSD_IDLEINT_152_INT152PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,6)))
+#define TSB_INTIFSD_IDLEINT_152_INT152NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,7)))
+#define TSB_INTIFSD_IDLEINT_153_INT153EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,0)))
+#define TSB_INTIFSD_IDLEINT_153_INT153PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,4)))
+#define TSB_INTIFSD_IDLEINT_153_INT153NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,5)))
+#define TSB_INTIFSD_IDLEINT_153_INT153PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,6)))
+#define TSB_INTIFSD_IDLEINT_153_INT153NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,7)))
+#define TSB_INTIFSD_IDLEINT_154_INT154EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,0)))
+#define TSB_INTIFSD_IDLEINT_154_INT154PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,4)))
+#define TSB_INTIFSD_IDLEINT_154_INT154NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,5)))
+#define TSB_INTIFSD_IDLEINT_154_INT154PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,6)))
+#define TSB_INTIFSD_IDLEINT_154_INT154NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,7)))
+#define TSB_INTIFSD_IDLEINT_155_INT155EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,0)))
+#define TSB_INTIFSD_IDLEINT_155_INT155PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,4)))
+#define TSB_INTIFSD_IDLEINT_155_INT155NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,5)))
+#define TSB_INTIFSD_IDLEINT_155_INT155PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,6)))
+#define TSB_INTIFSD_IDLEINT_155_INT155NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,7)))
+#define TSB_INTIFSD_IDLEINT_156_INT156EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,0)))
+#define TSB_INTIFSD_IDLEINT_156_INT156PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,4)))
+#define TSB_INTIFSD_IDLEINT_156_INT156NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,5)))
+#define TSB_INTIFSD_IDLEINT_156_INT156PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,6)))
+#define TSB_INTIFSD_IDLEINT_156_INT156NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,7)))
+#define TSB_INTIFSD_IDLEINT_157_INT157EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,0)))
+#define TSB_INTIFSD_IDLEINT_157_INT157PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,4)))
+#define TSB_INTIFSD_IDLEINT_157_INT157NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,5)))
+#define TSB_INTIFSD_IDLEINT_157_INT157PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,6)))
+#define TSB_INTIFSD_IDLEINT_157_INT157NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,7)))
+#define TSB_INTIFSD_IDLEINT_158_INT158EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,0)))
+#define TSB_INTIFSD_IDLEINT_158_INT158PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,4)))
+#define TSB_INTIFSD_IDLEINT_158_INT158NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,5)))
+#define TSB_INTIFSD_IDLEINT_158_INT158PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,6)))
+#define TSB_INTIFSD_IDLEINT_158_INT158NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,7)))
+#define TSB_INTIFSD_IDLEINT_159_INT159EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,0)))
+#define TSB_INTIFSD_IDLEINT_159_INT159PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,4)))
+#define TSB_INTIFSD_IDLEINT_159_INT159NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,5)))
+#define TSB_INTIFSD_IDLEINT_159_INT159PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,6)))
+#define TSB_INTIFSD_IDLEINT_159_INT159NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,7)))
+#define TSB_INTIFSD_IDLEINT_160_INT160EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,0)))
+#define TSB_INTIFSD_IDLEINT_160_INT160PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,4)))
+#define TSB_INTIFSD_IDLEINT_160_INT160NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,5)))
+#define TSB_INTIFSD_IDLEINT_160_INT160PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,6)))
+#define TSB_INTIFSD_IDLEINT_160_INT160NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,7)))
+#define TSB_INTIFSD_IDLEINT_161_INT161EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,0)))
+#define TSB_INTIFSD_IDLEINT_161_INT161PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,4)))
+#define TSB_INTIFSD_IDLEINT_161_INT161NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,5)))
+#define TSB_INTIFSD_IDLEINT_161_INT161PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,6)))
+#define TSB_INTIFSD_IDLEINT_161_INT161NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,7)))
+#define TSB_INTIFSD_IDLEINT_162_INT162EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,0)))
+#define TSB_INTIFSD_IDLEINT_162_INT162PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,4)))
+#define TSB_INTIFSD_IDLEINT_162_INT162NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,5)))
+#define TSB_INTIFSD_IDLEINT_162_INT162PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,6)))
+#define TSB_INTIFSD_IDLEINT_162_INT162NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,7)))
+#define TSB_INTIFSD_IDLEINT_163_INT163EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,0)))
+#define TSB_INTIFSD_IDLEINT_163_INT163PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,4)))
+#define TSB_INTIFSD_IDLEINT_163_INT163NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,5)))
+#define TSB_INTIFSD_IDLEINT_163_INT163PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,6)))
+#define TSB_INTIFSD_IDLEINT_163_INT163NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,7)))
+#define TSB_INTIFSD_IDLEINT_164_INT164EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,0)))
+#define TSB_INTIFSD_IDLEINT_164_INT164PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,4)))
+#define TSB_INTIFSD_IDLEINT_164_INT164NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,5)))
+#define TSB_INTIFSD_IDLEINT_164_INT164PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,6)))
+#define TSB_INTIFSD_IDLEINT_164_INT164NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,7)))
+#define TSB_INTIFSD_IDLEINT_165_INT165EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,0)))
+#define TSB_INTIFSD_IDLEINT_165_INT165PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,4)))
+#define TSB_INTIFSD_IDLEINT_165_INT165NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,5)))
+#define TSB_INTIFSD_IDLEINT_165_INT165PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,6)))
+#define TSB_INTIFSD_IDLEINT_165_INT165NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,7)))
+#define TSB_INTIFSD_IDLEINT_166_INT166EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,0)))
+#define TSB_INTIFSD_IDLEINT_166_INT166PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,4)))
+#define TSB_INTIFSD_IDLEINT_166_INT166NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,5)))
+#define TSB_INTIFSD_IDLEINT_166_INT166PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,6)))
+#define TSB_INTIFSD_IDLEINT_166_INT166NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,7)))
+#define TSB_INTIFSD_IDLEINT_167_INT167EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,0)))
+#define TSB_INTIFSD_IDLEINT_167_INT167PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,4)))
+#define TSB_INTIFSD_IDLEINT_167_INT167NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,5)))
+#define TSB_INTIFSD_IDLEINT_167_INT167PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,6)))
+#define TSB_INTIFSD_IDLEINT_167_INT167NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,7)))
+#define TSB_INTIFSD_IDLEINT_168_INT168EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,0)))
+#define TSB_INTIFSD_IDLEINT_168_INT168PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,4)))
+#define TSB_INTIFSD_IDLEINT_168_INT168NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,5)))
+#define TSB_INTIFSD_IDLEINT_168_INT168PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,6)))
+#define TSB_INTIFSD_IDLEINT_168_INT168NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,7)))
+#define TSB_INTIFSD_IDLEINT_169_INT169EN          (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,0)))
+#define TSB_INTIFSD_IDLEINT_169_INT169PFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,4)))
+#define TSB_INTIFSD_IDLEINT_169_INT169NFLG        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,5)))
+#define TSB_INTIFSD_IDLEINT_169_INT169PCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,6)))
+#define TSB_INTIFSD_IDLEINT_169_INT169NCLR        (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,7)))
+#define TSB_INTIFSD_FLAG0_INT16FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,16)))
+#define TSB_INTIFSD_FLAG0_INT17FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,17)))
+#define TSB_INTIFSD_FLAG0_INT18FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,18)))
+#define TSB_INTIFSD_FLAG1_INT32FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,0)))
+#define TSB_INTIFSD_FLAG1_INT33FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,1)))
+#define TSB_INTIFSD_FLAG1_INT34FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,2)))
+#define TSB_INTIFSD_FLAG1_INT35FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,3)))
+#define TSB_INTIFSD_FLAG1_INT36FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,4)))
+#define TSB_INTIFSD_FLAG1_INT37FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,5)))
+#define TSB_INTIFSD_FLAG1_INT38FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,6)))
+#define TSB_INTIFSD_FLAG1_INT39FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,7)))
+#define TSB_INTIFSD_FLAG3_INT96FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,0)))
+#define TSB_INTIFSD_FLAG3_INT97FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,1)))
+#define TSB_INTIFSD_FLAG3_INT98FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,2)))
+#define TSB_INTIFSD_FLAG3_INT99FLG                (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,3)))
+#define TSB_INTIFSD_FLAG3_INT100FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,4)))
+#define TSB_INTIFSD_FLAG3_INT101FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,5)))
+#define TSB_INTIFSD_FLAG3_INT102FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,6)))
+#define TSB_INTIFSD_FLAG3_INT103FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,7)))
+#define TSB_INTIFSD_FLAG3_INT104FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,8)))
+#define TSB_INTIFSD_FLAG3_INT105FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,9)))
+#define TSB_INTIFSD_FLAG3_INT106FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,10)))
+#define TSB_INTIFSD_FLAG3_INT107FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,11)))
+#define TSB_INTIFSD_FLAG3_INT108FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,12)))
+#define TSB_INTIFSD_FLAG3_INT109FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,13)))
+#define TSB_INTIFSD_FLAG3_INT110FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,14)))
+#define TSB_INTIFSD_FLAG3_INT111FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,15)))
+#define TSB_INTIFSD_FLAG3_INT112FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,16)))
+#define TSB_INTIFSD_FLAG3_INT113FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,17)))
+#define TSB_INTIFSD_FLAG3_INT114FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,18)))
+#define TSB_INTIFSD_FLAG3_INT115FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,19)))
+#define TSB_INTIFSD_FLAG3_INT116FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,20)))
+#define TSB_INTIFSD_FLAG3_INT117FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,21)))
+#define TSB_INTIFSD_FLAG3_INT118FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,22)))
+#define TSB_INTIFSD_FLAG3_INT119FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,23)))
+#define TSB_INTIFSD_FLAG3_INT120FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,24)))
+#define TSB_INTIFSD_FLAG3_INT121FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,25)))
+#define TSB_INTIFSD_FLAG3_INT122FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,26)))
+#define TSB_INTIFSD_FLAG3_INT123FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,27)))
+#define TSB_INTIFSD_FLAG3_INT124FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,28)))
+#define TSB_INTIFSD_FLAG3_INT125FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,29)))
+#define TSB_INTIFSD_FLAG3_INT126FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,30)))
+#define TSB_INTIFSD_FLAG3_INT127FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,31)))
+#define TSB_INTIFSD_FLAG4_INT128FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,0)))
+#define TSB_INTIFSD_FLAG4_INT129FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,1)))
+#define TSB_INTIFSD_FLAG4_INT130FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,2)))
+#define TSB_INTIFSD_FLAG4_INT131FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,3)))
+#define TSB_INTIFSD_FLAG4_INT132FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,4)))
+#define TSB_INTIFSD_FLAG4_INT133FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,5)))
+#define TSB_INTIFSD_FLAG4_INT134FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,6)))
+#define TSB_INTIFSD_FLAG4_INT135FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,7)))
+#define TSB_INTIFSD_FLAG4_INT136FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,8)))
+#define TSB_INTIFSD_FLAG4_INT137FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,9)))
+#define TSB_INTIFSD_FLAG4_INT138FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,10)))
+#define TSB_INTIFSD_FLAG4_INT139FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,11)))
+#define TSB_INTIFSD_FLAG4_INT140FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,12)))
+#define TSB_INTIFSD_FLAG4_INT141FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,13)))
+#define TSB_INTIFSD_FLAG4_INT142FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,14)))
+#define TSB_INTIFSD_FLAG4_INT143FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,15)))
+#define TSB_INTIFSD_FLAG4_INT144FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,16)))
+#define TSB_INTIFSD_FLAG4_INT145FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,17)))
+#define TSB_INTIFSD_FLAG4_INT146FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,18)))
+#define TSB_INTIFSD_FLAG4_INT147FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,19)))
+#define TSB_INTIFSD_FLAG4_INT148FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,20)))
+#define TSB_INTIFSD_FLAG4_INT149FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,21)))
+#define TSB_INTIFSD_FLAG4_INT150FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,22)))
+#define TSB_INTIFSD_FLAG4_INT151FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,23)))
+#define TSB_INTIFSD_FLAG4_INT152FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,24)))
+#define TSB_INTIFSD_FLAG5_INT160FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,0)))
+#define TSB_INTIFSD_FLAG5_INT161FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,1)))
+#define TSB_INTIFSD_FLAG5_INT162FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,2)))
+#define TSB_INTIFSD_FLAG5_INT163FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,3)))
+#define TSB_INTIFSD_FLAG5_INT164FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,4)))
+#define TSB_INTIFSD_FLAG5_INT165FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,5)))
+#define TSB_INTIFSD_FLAG5_INT166FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,6)))
+#define TSB_INTIFSD_FLAG5_INT167FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,7)))
+#define TSB_INTIFSD_FLAG5_INT168FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,8)))
+#define TSB_INTIFSD_FLAG5_INT169FLG               (*((__I  uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,9)))
+
+
+/* ADC */
+#define TSB_AD_MOD1_I2AD                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,6)))
+#define TSB_AD_MOD1_VREFON                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,7)))
+#define TSB_AD_MOD3_ADOBSV0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,0)))
+#define TSB_AD_MOD3_ADOBIC0                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,5)))
+#define TSB_AD_MOD4_ADHTG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,4)))
+#define TSB_AD_MOD4_ADHS                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,5)))
+#define TSB_AD_MOD4_HADHTG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,6)))
+#define TSB_AD_MOD4_HADHS                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,7)))
+#define TSB_AD_MOD5_ADOBSV1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,0)))
+#define TSB_AD_MOD5_ADOBIC1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,5)))
+#define TSB_AD_MOD6_ADDMA                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,0)))
+#define TSB_AD_MOD6_ADHPDMA                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,1)))
+#define TSB_AD_MOD6_ADM0DMA                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,2)))
+#define TSB_AD_MOD6_ADM1DMA                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,3)))
+
+    /** @} *//* End of group Device_Peripheral_registers */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM066_H__ */
+
+/** @} *//* End of group TMPM066 */
+/** @} *//* End of group TOSHIBA_TX00_MICROCONTROLLER */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,190 @@
+;/**
+; *******************************************************************************
+; * @file    startup_TMPM066.S
+; * @brief   CMSIS Cortex-M0 Core Device Startup File for the
+; *          TOSHIBA 'TMPM066' Device Series
+; * @version V2.0.2.1 (Tentative)
+; * @date    2015/08/05
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+; *******************************************************************************
+; */
+
+__initial_sp    EQU     0x20004000 ; Top of RAM (16KB)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     INT0_IRQHandler           ; 0:	Interrupt Pin0
+                DCD     INT1_IRQHandler           ; 1:	Interrupt Pin1
+                DCD     INT2_IRQHandler           ; 2:	Interrupt Pin2
+                DCD     INT3_IRQHandler           ; 3:	Interrupt Pin3
+                DCD     INT4_IRQHandler           ; 4:	Interrupt Pin4
+                DCD     INT5_IRQHandler           ; 5:	Interrupt Pin5
+                DCD     INTRX0_IRQHandler         ; 6:	Serial reception interrupt(channel0)
+                DCD     INTTX0_IRQHandler         ; 7:	Serial transmission interrupt(channel0)
+                DCD     INTRX1_IRQHandler         ; 8:	Serial reception interrupt(channel1)
+                DCD     INTTX1_IRQHandler         ; 9:	Serial transmission interrupt(channel1)
+                DCD     INTSPIRX_IRQHandler       ; 10:	SPI serial reception interrupt
+                DCD     INTSPITX_IRQHandler       ; 11:	SPI serial transmission interrupt
+                DCD     INTSPIERR_IRQHandler      ; 12:	SPI serial error interrupt
+                DCD     INTI2C0_IRQHandler        ; 13:	Serial bus interface (channel.0)
+                DCD     INTI2C1_IRQHandler        ; 14:	Serial bus interface (channel.1)
+                DCD     INTDMA_IRQHandler         ; 15:	DMAC interrupt
+                DCD     INT16A0_IRQHandler        ; 16:	16-bit TMR16A match detection (channel.0)
+                DCD     INT16A1_IRQHandler        ; 17:	16-bit TMR16A match detection (channel.1)
+                DCD     INTTB0_IRQHandler         ; 18:	16-bit TMRB interrupt(channel.0)
+                DCD     INTTB1_IRQHandler         ; 19:	16-bit TMRB interrupt(channel.1)
+                DCD     INTTB2_IRQHandler         ; 20:	16-bit TMRB interrupt(channel.2)
+                DCD     INTTB3_IRQHandler         ; 21:	16-bit TMRB interrupt(channel.3)
+                DCD     INTTB4_IRQHandler         ; 22:	16-bit TMRB interrupt(channel.4)
+                DCD     INTTB5_IRQHandler         ; 23:	16-bit TMRB interrupt(channel.5)
+                DCD     INTTB6_IRQHandler         ; 24:	16-bit TMRB interrupt(channel.6)
+                DCD     INTTB7_IRQHandler         ; 25:	16-bit TMRB interrupt(channel.7)
+                DCD     INTI2CS_IRQHandler        ; 26:	Serial bus interface for Wakeup(channel.1)
+                DCD     INTTMRD_IRQHandler        ; 27:	TMRD interrupt
+                DCD     INTUSB_IRQHandler         ; 28:	USB interrupt
+                DCD     INTUSBWKUP_IRQHandler     ; 29:	USB wakeup interrupt
+                DCD     INTADHP_IRQHandler        ; 30:	High Priority A/D conversion interrupt
+                DCD     INTAD_IRQHandler          ; 31:	Normal A/D conversion completion interrupt
+
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  INT0_IRQHandler           [WEAK]
+                EXPORT  INT1_IRQHandler           [WEAK]
+                EXPORT  INT2_IRQHandler           [WEAK]
+                EXPORT  INT3_IRQHandler           [WEAK]
+                EXPORT  INT4_IRQHandler           [WEAK]
+                EXPORT  INT5_IRQHandler           [WEAK]
+                EXPORT  INTRX0_IRQHandler         [WEAK]
+                EXPORT  INTTX0_IRQHandler         [WEAK]
+                EXPORT  INTRX1_IRQHandler         [WEAK]
+                EXPORT  INTTX1_IRQHandler         [WEAK]
+                EXPORT  INTSPIRX_IRQHandler       [WEAK]
+                EXPORT  INTSPITX_IRQHandler       [WEAK]
+                EXPORT  INTSPIERR_IRQHandler      [WEAK]
+                EXPORT  INTI2C0_IRQHandler        [WEAK]
+                EXPORT  INTI2C1_IRQHandler        [WEAK]
+                EXPORT  INTDMA_IRQHandler         [WEAK]
+                EXPORT  INT16A0_IRQHandler        [WEAK]
+                EXPORT  INT16A1_IRQHandler        [WEAK]
+                EXPORT  INTTB0_IRQHandler         [WEAK]
+                EXPORT  INTTB1_IRQHandler         [WEAK]
+                EXPORT  INTTB2_IRQHandler         [WEAK]
+                EXPORT  INTTB3_IRQHandler         [WEAK]
+                EXPORT  INTTB4_IRQHandler         [WEAK]
+                EXPORT  INTTB5_IRQHandler         [WEAK]
+                EXPORT  INTTB6_IRQHandler         [WEAK]
+                EXPORT  INTTB7_IRQHandler         [WEAK]
+                EXPORT  INTI2CS_IRQHandler        [WEAK]
+                EXPORT  INTTMRD_IRQHandler        [WEAK]
+                EXPORT  INTUSB_IRQHandler         [WEAK]
+                EXPORT  INTUSBWKUP_IRQHandler     [WEAK]
+                EXPORT  INTADHP_IRQHandler        [WEAK]
+                EXPORT  INTAD_IRQHandler          [WEAK]
+
+INT0_IRQHandler
+INT1_IRQHandler
+INT2_IRQHandler
+INT3_IRQHandler
+INT4_IRQHandler
+INT5_IRQHandler
+INTRX0_IRQHandler
+INTTX0_IRQHandler
+INTRX1_IRQHandler
+INTTX1_IRQHandler
+INTSPIRX_IRQHandler
+INTSPITX_IRQHandler
+INTSPIERR_IRQHandler
+INTI2C0_IRQHandler
+INTI2C1_IRQHandler
+INTDMA_IRQHandler
+INT16A0_IRQHandler
+INT16A1_IRQHandler
+INTTB0_IRQHandler
+INTTB1_IRQHandler
+INTTB2_IRQHandler
+INTTB3_IRQHandler
+INTTB4_IRQHandler
+INTTB5_IRQHandler
+INTTB6_IRQHandler
+INTTB7_IRQHandler
+INTI2CS_IRQHandler
+INTTMRD_IRQHandler
+INTUSB_IRQHandler
+INTUSBWKUP_IRQHandler
+INTADHP_IRQHandler
+INTAD_IRQHandler
+
+                B       .
+
+                ENDP
+
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,32 @@
+;;  TMPM066FWUG scatter file
+
+;;  Vector table starts at 0
+;;    Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
+;;               or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
+;;    Initial PC == &__main (with LSB set to indicate Thumb)
+;;    These two values are provided by the library
+;;    Other vectors must be provided by the user
+;;  Code starts after the last possible vector
+;;  Data starts at 0x20000000
+;;    Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
+;;    Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
+
+;; Compatible with ISSM model
+
+LR_IROM1 0x00000000 0x20000
+{
+  ER_IROM1 0x00000000 0x20000
+  {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    *.o (+RO-CODE)
+    .ANY2 (+RO-DATA)
+    .ANY (+RO)
+  }
+
+  /* 8_byte_aligned(32 + 16 vect * 4 bytes) =  8_byte_aligned(0xC0) */
+  RW_IRAM1 0x200000C0 (0x4000 - 0xC0)
+  {
+    .ANY (+RW, +ZI)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,220 @@
+/**
+ *******************************************************************************
+ * @file    startup_TMPM066.S
+ * @brief   CMSIS Cortex-M0 Core Device Startup File for the
+ *          TOSHIBA 'TMPM066' Device Series
+ * @version V2.0.2.1 (Tentative)
+ * @date    2015/08/05
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+.syntax unified
+.arch armv6-m
+
+.section .stack
+.align 3
+
+/*
+// <h> Stack Configuration
+//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+.section .stack
+.align 3
+#ifdef __STACK_SIZE
+.equ    Stack_Size, __STACK_SIZE
+#else
+.equ    Stack_Size, 0x400
+#endif
+.globl    __StackTop
+.globl    __StackLimit
+__StackLimit:
+.space    Stack_Size
+.size __StackLimit, . - __StackLimit
+__StackTop:
+.size __StackTop, . - __StackTop
+
+/*
+// <h> Heap Configuration
+//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+.section .heap
+.align 3
+#ifdef __HEAP_SIZE
+.equ    Heap_Size, __HEAP_SIZE
+#else
+.equ    Heap_Size, 0
+#endif
+.globl    __HeapBase
+.globl    __HeapLimit
+__HeapBase:
+.if    Heap_Size
+.space    Heap_Size
+.endif
+.size __HeapBase, . - __HeapBase
+__HeapLimit:
+.size __HeapLimit, . - __HeapLimit
+
+/* Vector Table */
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                  /* Top of Stack                  */
+    .long   Reset_Handler               /* Reset Handler                 */
+    .long   NMI_Handler                 /* NMI Handler                   */
+    .long   HardFault_Handler           /* Hard Fault Handler            */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   0                           /* Reserved                      */
+    .long   SVC_Handler                 /* SVCall Handler                */
+    .long   0                           /* Debug Monitor Handler         */
+    .long   0                           /* Reserved                      */
+    .long   PendSV_Handler              /* PendSV Handler                */
+    .long   SysTick_Handler             /* SysTick Handler               */
+
+    /* External Interrupts */
+    .long     INT0_IRQHandler           // 0:	Interrupt Pin0
+    .long     INT1_IRQHandler           // 1:	Interrupt Pin1
+    .long     INT2_IRQHandler           // 2:	Interrupt Pin2
+    .long     INT3_IRQHandler           // 3:	Interrupt Pin3
+    .long     INT4_IRQHandler           // 4:	Interrupt Pin4
+    .long     INT5_IRQHandler           // 5:	Interrupt Pin5
+    .long     INTRX0_IRQHandler         // 6:	Serial reception interrupt(channel0)
+    .long     INTTX0_IRQHandler         // 7:	Serial transmission interrupt(channel0)
+    .long     INTRX1_IRQHandler         // 8:	Serial reception interrupt(channel1)
+    .long     INTTX1_IRQHandler         // 9:	Serial transmission interrupt(channel1)
+    .long     INTSPIRX_IRQHandler       // 10:	SPI serial reception interrupt
+    .long     INTSPITX_IRQHandler       // 11:	SPI serial transmission interrupt
+    .long     INTSPIERR_IRQHandler      // 12:	SPI serial error interrupt
+    .long     INTI2C0_IRQHandler        // 13:	Serial bus interface (channel.0)
+    .long     INTI2C1_IRQHandler        // 14:	Serial bus interface (channel.1)
+    .long     INTDMA_IRQHandler         // 15:	DMAC interrupt
+    .long     INT16A0_IRQHandler        // 16:	16-bit TMR16A match detection (channel.0)
+    .long     INT16A1_IRQHandler        // 17:	16-bit TMR16A match detection (channel.1)
+    .long     INTTB0_IRQHandler         // 18:	16-bit TMRB interrupt(channel.0)
+    .long     INTTB1_IRQHandler         // 19:	16-bit TMRB interrupt(channel.1)
+    .long     INTTB2_IRQHandler         // 20:	16-bit TMRB interrupt(channel.2)
+    .long     INTTB3_IRQHandler         // 21:	16-bit TMRB interrupt(channel.3)
+    .long     INTTB4_IRQHandler         // 22:	16-bit TMRB interrupt(channel.4)
+    .long     INTTB5_IRQHandler         // 23:	16-bit TMRB interrupt(channel.5)
+    .long     INTTB6_IRQHandler         // 24:	16-bit TMRB interrupt(channel.6)
+    .long     INTTB7_IRQHandler         // 25:	16-bit TMRB interrupt(channel.7)
+    .long     INTI2CS_IRQHandler        // 26:	Serial bus interface for Wakeup(channel.1)
+    .long     INTTMRD_IRQHandler        // 27:	TMRD interrupt
+    .long     INTUSB_IRQHandler         // 28:	USB interrupt
+    .long     INTUSBWKUP_IRQHandler     // 29:	USB wakeup interrupt
+    .long     INTADHP_IRQHandler        // 30:	High Priority A/D conversion interrupt
+    .long     INTAD_IRQHandler          // 31:	Normal A/D conversion completion interrupt
+    .size    __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+    Reset_Handler:
+    /*     Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      __etext: End of code section, i.e., begin of data sections to copy from.
+     *      __data_start__/__data_end__: RAM address range that data should be
+     *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+        ldr    r1, =__etext
+        ldr    r2, =__data_start__
+        ldr    r3, =__data_end__
+
+        subs    r3, r2
+        ble    .Lflash_to_ram_loop_end
+
+        movs    r4, 0
+    .Lflash_to_ram_loop:
+        ldr    r0, [r1,r4]
+        str    r0, [r2,r4]
+        adds    r4, 4
+        cmp    r4, r3
+        blt    .Lflash_to_ram_loop
+    .Lflash_to_ram_loop_end:
+
+        ldr    r0, =SystemInit
+        blx    r0
+        ldr    r0, =_start
+        bx    r0
+        .pool
+        .size Reset_Handler, . - Reset_Handler
+
+        .text
+    /*    Macro to define default handlers. Default handler
+     *    will be weak symbol and just dead loops. They can be
+     *    overwritten by other handlers */
+
+        .macro    def_default_handler    handler_name
+        .align 1
+        .thumb_func
+        .weak    \handler_name
+        .type    \handler_name, %function
+    \handler_name :
+        b    .
+        .size    \handler_name, . - \handler_name
+        .endm
+
+        def_default_handler     NMI_Handler
+        def_default_handler     HardFault_Handler
+        def_default_handler     SVC_Handler
+        def_default_handler     PendSV_Handler
+        def_default_handler     SysTick_Handler
+        def_default_handler     Default_Handler
+
+        .macro    def_irq_default_handler    handler_name
+        .weak     \handler_name
+        .set      \handler_name, Default_Handler
+        .endm
+
+        def_irq_default_handler        INT0_IRQHandler
+        def_irq_default_handler        INT1_IRQHandler
+        def_irq_default_handler        INT2_IRQHandler
+        def_irq_default_handler        INT3_IRQHandler
+        def_irq_default_handler        INT4_IRQHandler
+        def_irq_default_handler        INT5_IRQHandler
+        def_irq_default_handler        INTRX0_IRQHandler
+        def_irq_default_handler        INTTX0_IRQHandler
+        def_irq_default_handler        INTRX1_IRQHandler
+        def_irq_default_handler        INTTX1_IRQHandler
+        def_irq_default_handler        INTSPIRX_IRQHandler
+        def_irq_default_handler        INTSPITX_IRQHandler
+        def_irq_default_handler        INTSPIERR_IRQHandler
+        def_irq_default_handler        INTI2C0_IRQHandler
+        def_irq_default_handler        INTI2C1_IRQHandler
+        def_irq_default_handler        INTDMA_IRQHandler
+        def_irq_default_handler        INT16A0_IRQHandler
+        def_irq_default_handler        INT16A1_IRQHandler
+        def_irq_default_handler        INTTB0_IRQHandler
+        def_irq_default_handler        INTTB1_IRQHandler
+        def_irq_default_handler        INTTB2_IRQHandler
+        def_irq_default_handler        INTTB3_IRQHandler
+        def_irq_default_handler        INTTB4_IRQHandler
+        def_irq_default_handler        INTTB5_IRQHandler
+        def_irq_default_handler        INTTB6_IRQHandler
+        def_irq_default_handler        INTTB7_IRQHandler
+        def_irq_default_handler        INTI2CS_IRQHandler
+        def_irq_default_handler        INTTMRD_IRQHandler
+        def_irq_default_handler        INTUSB_IRQHandler
+        def_irq_default_handler        INTUSBWKUP_IRQHandler
+        def_irq_default_handler        INTADHP_IRQHandler
+        def_irq_default_handler        INTAD_IRQHandler
+
+        .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,150 @@
+/* Linker script for Toshiba TMPM066 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        Image$$RW_IRAM1$$Base = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$RW_IRAM1$$ZI$$Limit = . ;
+    } > RAM
+
+
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,281 @@
+;/**
+; *******************************************************************************
+; * @file    startup_TMPM066.S
+; * @brief   CMSIS Cortex-M0 Core Device Startup File for the
+; *          TOSHIBA 'TMPM066' Device Series
+; * @version V2.0.2.1 (Tentative)
+; * @date    2015/08/05
+; *
+; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+; *******************************************************************************
+; */
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; Cortex-M version
+;
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)
+                DCD     Reset_Handler
+
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     INT0_IRQHandler           ; 0:	Interrupt Pin0
+                DCD     INT1_IRQHandler           ; 1:	Interrupt Pin1
+                DCD     INT2_IRQHandler           ; 2:	Interrupt Pin2
+                DCD     INT3_IRQHandler           ; 3:	Interrupt Pin3
+                DCD     INT4_IRQHandler           ; 4:	Interrupt Pin4
+                DCD     INT5_IRQHandler           ; 5:	Interrupt Pin5
+                DCD     INTRX0_IRQHandler         ; 6:	Serial reception interrupt(channel0)
+                DCD     INTTX0_IRQHandler         ; 7:	Serial transmission interrupt(channel0)
+                DCD     INTRX1_IRQHandler         ; 8:	Serial reception interrupt(channel1)
+                DCD     INTTX1_IRQHandler         ; 9:	Serial transmission interrupt(channel1)
+                DCD     INTSPIRX_IRQHandler       ; 10:	SPI serial reception interrupt
+                DCD     INTSPITX_IRQHandler       ; 11:	SPI serial transmission interrupt
+                DCD     INTSPIERR_IRQHandler      ; 12:	SPI serial error interrupt
+                DCD     INTI2C0_IRQHandler        ; 13:	Serial bus interface (channel.0)
+                DCD     INTI2C1_IRQHandler        ; 14:	Serial bus interface (channel.1)
+                DCD     INTDMA_IRQHandler         ; 15:	DMAC interrupt
+                DCD     INT16A0_IRQHandler        ; 16:	16-bit TMR16A match detection (channel.0)
+                DCD     INT16A1_IRQHandler        ; 17:	16-bit TMR16A match detection (channel.1)
+                DCD     INTTB0_IRQHandler         ; 18:	16-bit TMRB interrupt(channel.0)
+                DCD     INTTB1_IRQHandler         ; 19:	16-bit TMRB interrupt(channel.1)
+                DCD     INTTB2_IRQHandler         ; 20:	16-bit TMRB interrupt(channel.2)
+                DCD     INTTB3_IRQHandler         ; 21:	16-bit TMRB interrupt(channel.3)
+                DCD     INTTB4_IRQHandler         ; 22:	16-bit TMRB interrupt(channel.4)
+                DCD     INTTB5_IRQHandler         ; 23:	16-bit TMRB interrupt(channel.5)
+                DCD     INTTB6_IRQHandler         ; 24:	16-bit TMRB interrupt(channel.6)
+                DCD     INTTB7_IRQHandler         ; 25:	16-bit TMRB interrupt(channel.7)
+                DCD     INTI2CS_IRQHandler        ; 26:	Serial bus interface for Wakeup(channel.1)
+                DCD     INTTMRD_IRQHandler        ; 27:	TMRD interrupt
+                DCD     INTUSB_IRQHandler         ; 28:	USB interrupt
+                DCD     INTUSBWKUP_IRQHandler     ; 29:	USB wakeup interrupt
+                DCD     INTADHP_IRQHandler        ; 30:	High Priority A/D conversion interrupt
+                DCD     INTAD_IRQHandler          ; 31:	Normal A/D conversion completion interrupt
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+                B       SVC_Handler
+
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+                B       PendSV_Handler
+
+                PUBWEAK SysTick_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+                B       SysTick_Handler
+
+                PUBWEAK INT0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT0_IRQHandler
+                B       INT0_IRQHandler
+
+                PUBWEAK INT1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT1_IRQHandler
+                B       INT1_IRQHandler
+
+                PUBWEAK INT2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT2_IRQHandler
+                B       INT2_IRQHandler
+
+                PUBWEAK INT3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT3_IRQHandler
+                B       INT3_IRQHandler
+
+                PUBWEAK INT4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT4_IRQHandler
+                B       INT4_IRQHandler
+
+                PUBWEAK INT5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT5_IRQHandler
+                B       INT5_IRQHandler
+
+                PUBWEAK INTRX0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX0_IRQHandler
+                B       INTRX0_IRQHandler
+
+                PUBWEAK INTTX0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX0_IRQHandler
+                B       INTTX0_IRQHandler
+
+                PUBWEAK INTRX1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX1_IRQHandler
+                B       INTRX1_IRQHandler
+
+                PUBWEAK INTTX1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX1_IRQHandler
+                B       INTTX1_IRQHandler
+
+                PUBWEAK INTSPIRX_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSPIRX_IRQHandler
+                B       INTSPIRX_IRQHandler
+
+                PUBWEAK INTSPITX_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSPITX_IRQHandler
+                B       INTSPITX_IRQHandler
+
+                PUBWEAK INTSPIERR_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSPIERR_IRQHandler
+                B       INTSPIERR_IRQHandler
+
+                PUBWEAK INTI2C0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2C0_IRQHandler
+                B       INTI2C0_IRQHandler
+
+                PUBWEAK INTI2C1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2C1_IRQHandler
+                B       INTI2C1_IRQHandler
+
+                PUBWEAK INTDMA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMA_IRQHandler
+                B       INTDMA_IRQHandler
+
+                PUBWEAK INT16A0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT16A0_IRQHandler
+                B       INT16A0_IRQHandler
+
+                PUBWEAK INT16A1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT16A1_IRQHandler
+                B       INT16A1_IRQHandler
+
+                PUBWEAK INTTB0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB0_IRQHandler
+                B       INTTB0_IRQHandler
+
+                PUBWEAK INTTB1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB1_IRQHandler
+                B       INTTB1_IRQHandler
+
+                PUBWEAK INTTB2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB2_IRQHandler
+                B       INTTB2_IRQHandler
+
+                PUBWEAK INTTB3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB3_IRQHandler
+                B       INTTB3_IRQHandler
+
+                PUBWEAK INTTB4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB4_IRQHandler
+                B       INTTB4_IRQHandler
+
+                PUBWEAK INTTB5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB5_IRQHandler
+                B       INTTB5_IRQHandler
+
+                PUBWEAK INTTB6_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB6_IRQHandler
+                B       INTTB6_IRQHandler
+
+                PUBWEAK INTTB7_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB7_IRQHandler
+                B       INTTB7_IRQHandler
+
+                PUBWEAK INTI2CS_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2CS_IRQHandler
+                B       INTI2CS_IRQHandler
+
+                PUBWEAK INTTMRD_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTMRD_IRQHandler
+                B       INTTMRD_IRQHandler
+
+                PUBWEAK INTUSB_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTUSB_IRQHandler
+                B       INTUSB_IRQHandler
+
+                PUBWEAK INTUSBWKUP_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTUSBWKUP_IRQHandler
+                B       INTUSBWKUP_IRQHandler
+
+                PUBWEAK INTADHP_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTADHP_IRQHandler
+                B       INTADHP_IRQHandler
+
+                PUBWEAK INTAD_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTAD_IRQHandler
+                B       INTAD_IRQHandler
+
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ 	= 0x200;
+define symbol __ICFEDIT_size_heap__   	= 0x1400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,12 @@
+/* mbed Microcontroller Library - CMSIS for TMPM066
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in TMPM066 specifics
+ */
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "TMPM066.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library - cmsis_nvic for TMPM066
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS      (0x20000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS    (0x00000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    static int vector_copied = 0;
+    uint32_t *vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (vector_copied == 0) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
+        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        vector_copied = 1;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library - cmsis_nvic for TMPM066
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
+// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+#define NVIC_NUM_VECTORS            (16 + 32)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET        16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Set the ISR for IRQn
+ *
+ * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
+ * the first time this function is called
+ * @param[in] IRQn   The Interrupt Request number for which a vector will be registered
+ * @param[in] vector The ISR vector to register for IRQn
+ */
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+
+/** Get the ISR registered for IRQn
+ *
+ * Reads the Interrupt Service Routine currently registered for IRQn
+ * @param[in] IRQn   The Interrupt Request number the vector of which will be read
+ * @return           Returns the ISR registered for IRQn
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,301 @@
+/**
+ *******************************************************************************
+ * @file    system_TMPM066.c
+ * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Source File for the
+ *          TOSHIBA 'TMPM066' Device Series
+ * @version V2.0.2.1
+ * @date    2015/10/22
+ *
+ * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved
+ *******************************************************************************
+ */
+
+#include "TMPM066.h"
+
+/*-------- <<< Start of configuration section >>> ----------------------------*/
+
+/* Watchdog Timer (WD) Configuration */
+#define WD_SETUP                (1U)
+#define WDMOD_Val               (0x00000000UL)
+#define WDCR_Val                (0x000000B1UL)
+
+/* Clock Generator (CG) Configuration */
+#define CLOCK_SETUP             (1U)
+#define SYSCR_Val               (0x00000000UL)
+#define OSCCR_Val               (0x00000102UL)  /* OSCCR<OSCSEL> = 1, OSCCR<EOSCEN> = 01 */
+
+#define STBYCR_Val              (0x00000000UL)
+
+#define CG_8M_MUL_12_FPLL        (0x00C60B00UL<<8U)
+
+#define CG_10M_MUL_8_FPLL        (0x00C60700UL<<8U)
+
+#define CG_12M_MUL_8_FPLL        (0x00C60700UL<<8U)
+
+#define CG_16M_MUL_6_FPLL        (0x00C60500UL<<8U)
+
+
+#define CG_PLL0SEL_PLL0ON_SET                  ((uint32_t)0x00000001)
+#define CG_PLL0SEL_PLL0ON_CLEAR                ((uint32_t)0xFFFFFFFE)
+#define CG_PLL0SEL_PLL0SEL_SET                 ((uint32_t)0x00000002)
+#define CG_PLL0SEL_PLL0ST_MASK                 ((uint32_t)0x00000004)
+
+#define CG_OSCCR_IOSCEN_CLEAR                  ((uint32_t)0xFFFFFFFE)
+#define CG_OSCCR_EOSCEN_SET                    ((uint32_t)0x00000002)
+#define CG_OSCCR_OSCSEL_SET                    ((uint32_t)0x00000100)
+#define CG_OSCCR_OSCF_MASK                     ((uint32_t)0x00000200)
+
+#define CG_WUON_START_SET                     ((uint32_t)0x00000001)
+#define CG_WUEF_VALUE_MASK                    ((uint32_t)0x00000002)
+#define CG_WUPHCR_WUCLK_SET                   ((uint32_t)0x00000100)
+
+#define WD_MOD_WDTE_SET                      ((uint32_t)0x00000080)
+
+#define PLLSEL_Ready            CG_12M_MUL_8_FPLL
+
+#define PLLSEL_Val              (PLLSEL_Ready|0x00000003UL)
+#define PLLSEL_MASK             (0xFFFFFF00UL)
+
+/*-------- <<< End of configuration section >>> ------------------------------*/
+
+/*-------- DEFINES -----------------------------------------------------------*/
+/* Define clocks */
+#define OSC_8M                  ( 8000000UL)
+#define OSC_10M                 (10000000UL)
+#define OSC_12M                 (12000000UL)
+#define OSC_16M                 (16000000UL)
+#define EXTALH                  OSC_12M /* External high-speed oscillator freq */
+#define XTALH                   OSC_10M /* Internal high-speed oscillator freq */
+
+/* Configure Warm-up time */
+#define HZ_1M                  (1000000UL)
+#define WU_TIME_EXT            (5000UL) /* warm-up time for EXT is 5ms   */
+#define WU_TIME_PLL            (100UL)  /* warm-up time for PLL is 100us */
+#define WUPHCR_WUPT_MASK        (0x000FFFFFUL)
+#define WUPHCR_WUPT_EXT         ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U))    /* WUPHCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
+#define WUPHCR_WUPT_PLL         ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U)
+
+#if (CLOCK_SETUP)               /* Clock(external) Setup */
+/* Determine core clock frequency according to settings */
+/* System clock is high-speed clock*/
+#if (OSCCR_Val & (1U<<8U))
+#define CORE_TALH (EXTALH)
+#else
+#define CORE_TALH (XTALH)
+#endif
+
+#if ((PLLSEL_Val & (1U<<1U)) && (PLLSEL_Val & (1U<<0U)))      /* If PLL selected and enabled */
+#if (CORE_TALH == OSC_8M)       /* If input is 8MHz */
+#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL))
+#define __CORE_CLK   ((CORE_TALH * 12U) / 4U) /* output clock is 24MHz */
+#else                           /* fc -> reserved */
+#define __CORE_CLK   (0U)
+#endif                          /* End input is 8MHz */
+#elif (CORE_TALH == OSC_10M)    /* If input is 10MHz */
+#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL))
+#define __CORE_CLK   ((CORE_TALH * 8U) / 4U)  /* output clock is 20MHz */
+#else                           /* fc -> reserved */
+#define __CORE_CLK   (0U)
+#endif                          /* End input is 10MHz */
+#elif (CORE_TALH == OSC_12M)    /* If input is 12MHz */
+#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL)
+#define __CORE_CLK   ((CORE_TALH * 8U) / 4U)  /* output clock is 24MHz */
+#else                           /* fc -> reserved */
+#define __CORE_CLK   (0U)
+#endif                          /* End input is 12MHz */
+#elif (CORE_TALH == OSC_16M)    /* If input is 16MHz */
+#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_6_FPLL)
+#define __CORE_CLK   ((CORE_TALH * 6U) / 4U)  /* output clock is 24MHz */
+#else                           /* fc -> reserved        */
+#define __CORE_CLK   (0U)
+#endif                          /* End input is 16MHz    */
+#else                           /* input clock not known */
+#define __CORE_CLK   (0U)
+#error "Core Oscillator Frequency invalid!"
+#endif                          /* End switch input clock */
+#else
+#define __CORE_CLK   (CORE_TALH)
+#endif
+
+#if   ((SYSCR_Val & 7U) == 0U)  /* Gear -> fc             */
+#define __CORE_SYS   (__CORE_CLK)
+#elif ((SYSCR_Val & 7U) == 1U)  /* Gear -> fc/2           */
+#define __CORE_SYS   (__CORE_CLK / 2U)
+#elif ((SYSCR_Val & 7U) == 2U)  /* Gear -> fc/4           */
+#define __CORE_SYS   (__CORE_CLK / 4U)
+#elif ((SYSCR_Val & 7U) == 3U)  /* Gear -> fc/8           */
+#define __CORE_SYS   (__CORE_CLK / 8U)
+#elif ((SYSCR_Val & 7U) == 4U)  /* Gear -> fc/16          */
+#define __CORE_SYS   (__CORE_CLK / 16U)
+#else                           /* Gear -> reserved       */
+#define __CORE_SYS   (0U)
+#endif
+
+#else
+#define __CORE_SYS   (XTALH)
+
+#endif                          /* clock Setup */
+
+/* Clock Variable definitions */
+uint32_t SystemCoreClock = __CORE_SYS;  /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Update SystemCoreClock according register values.
+ */
+void SystemCoreClockUpdate(void)
+{                               /* Get Core Clock Frequency */
+    uint32_t CoreClock = 0U;
+    uint32_t CoreClockInput = 0U;
+    uint32_t regval = 0U;
+    uint32_t oscsel = 0U;
+    uint32_t pllsel = 0U;
+    uint32_t pllon = 0U;
+    /* Determine clock frequency according to clock register values */
+    /* System clock is high-speed clock */
+    regval = TSB_CG->OSCCR;
+    oscsel = regval & CG_OSCCR_OSCSEL_SET;
+    if (oscsel) {               /* If system clock is External high-speed oscillator freq */
+        CoreClock = EXTALH;
+    } else {                    /* If system clock is Internal high-speed oscillator freq */
+        CoreClock = XTALH;
+    }
+    regval = TSB_CG->PLL0SEL;
+    pllsel = regval & CG_PLL0SEL_PLL0SEL_SET;
+    pllon = regval & CG_PLL0SEL_PLL0ON_SET;
+    if (pllsel && pllon) {      /* If PLL enabled  */
+        if (CoreClock == OSC_8M) {      /* If input is 8MHz */
+            if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) {
+                CoreClockInput = (CoreClock * 12U) / 4U;       /* output clock is 24MHz */
+            } else {
+                CoreClockInput = 0U;    /* fc -> reserved            */
+            }
+        } else if (CoreClock == OSC_10M) {      /* If input is 10MHz */
+            if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) {
+                CoreClockInput = (CoreClock * 8U) / 4U;        /* output clock is 20MHz */
+            } else {
+                CoreClockInput = 0U;    /* fc -> reserved */
+            }
+        } else if (CoreClock == OSC_12M) {      /* If input is 12MHz */
+            if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) {
+                CoreClockInput = (CoreClock * 8U) / 4U;        /* output clock is 24MHz */
+            } else {
+                CoreClockInput = 0U;    /* fc -> reserved */
+            }
+        } else if (CoreClock == OSC_16M) {      /* If input is 16MHz */
+            if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) {
+                CoreClockInput = (CoreClock * 6U) / 4U;        /* output clock is 24MHz */
+            } else {
+                CoreClockInput = 0U;    /* fc -> reserved        */
+            }
+        } else {
+            CoreClockInput = 0U;
+        }
+    } else {
+        CoreClockInput = CoreClock;
+    }
+    switch (TSB_CG->SYSCR & 7U) {
+    case 0U:
+        SystemCoreClock = CoreClockInput;       /* Gear -> fc      */
+        break;
+    case 1U:                   /* Gear -> fc/2     */
+        SystemCoreClock = CoreClockInput / 2U;
+        break;
+    case 2U:                   /* Gear -> fc/4     */
+        SystemCoreClock = CoreClockInput / 4U;
+        break;
+    case 3U:                   /* Gear -> fc/8     */
+        SystemCoreClock = CoreClockInput / 8U;
+        break;
+    case 4U:                   /* Gear -> fc/16     */
+        if (CoreClockInput >= OSC_16M) {
+            SystemCoreClock = CoreClockInput / 16U;
+        } else {
+            SystemCoreClock = 0U;
+        }
+        break;
+    default:
+        SystemCoreClock = 0U;
+        break;
+    }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit(void)
+{
+    uint32_t regval = 0U;
+    volatile uint32_t pllst = 0U;
+    volatile uint32_t wuef = 0U;  
+    volatile uint32_t oscf = 0U;
+    uint32_t wdte = 0U;
+
+#if (WD_SETUP)                  /* Watchdog Setup */
+    while (TSB_WD->FLG != 0U) {
+    }                /* When writing to WDMOD or WDCR, confirm "0" of WDFLG<FLG>. */
+    TSB_WD->MOD = WDMOD_Val;
+    regval = TSB_WD->MOD;
+    wdte = regval & WD_MOD_WDTE_SET;
+    if (!wdte) {     /* If watchdog is to be disabled */
+        TSB_WD->CR = WDCR_Val;
+    } else {
+        /*Do nothing*/
+    }
+#endif
+
+#if (CLOCK_SETUP)               /* Clock(external) Setup */
+    TSB_CG->SYSCR = SYSCR_Val;
+    TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
+    TSB_CG->WUPHCR |= WUPHCR_WUPT_EXT;    
+    TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;    
+    TSB_CG->WUPHCR |= CG_WUPHCR_WUCLK_SET;   
+    TSB_CG->WUPHCR |= CG_WUON_START_SET;
+    wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+    while (wuef) {
+        wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+    }                           /* Warm-up */
+    TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+    oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
+    while (oscf != CG_OSCCR_OSCF_MASK) {
+        oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
+    }                           /* Confirm CGOSCCR<OSCF>="1" */
+
+    TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
+    TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL;
+    TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
+    TSB_CG->PLL0SEL = PLLSEL_Ready;
+    TSB_CG->WUPHCR |= CG_WUON_START_SET;
+    wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+    while (wuef) {
+        wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+    }                           /* Warm-up */
+
+    TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK;
+    TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL;
+    TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET;   /* PLL enabled */
+    TSB_CG->STBYCR = STBYCR_Val;
+    TSB_CG->WUPHCR |= CG_WUON_START_SET;
+    wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+   while (wuef) {
+        wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK;
+   }                           /* Warm-up */
+    TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
+   pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK;
+   while (pllst != CG_PLL0SEL_PLL0ST_MASK) {
+        pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK;
+    }                           /*Confirm CGPLLSEL<PLLST> = "1" */
+
+#endif
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,49 @@
+/**
+ *****************************************************************************
+ * @file     system_TMPM066.h
+ * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File for the
+ *           TOSHIBA 'TMPM066' Device Series 
+ * @version  V2.0.2.1 (Tentative)
+ * @date     2015/8/13
+ *
+ * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved
+ *****************************************************************************
+ */
+
+#include <stdint.h>
+
+#ifndef __SYSTEM_TMPM066_H
+#define __SYSTEM_TMPM066_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+    extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+    extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define GPIO_DATA PIN_DATA(0, 3)
+extern const PinMap PinMap_GPIO_IRQ[];
+
+uint32_t gpio_set(PinName pin)
+{
+    // Check that pin is valid
+    MBED_ASSERT(pin != (PinName)NC);
+
+    // Checking pin name is not interrupt pins
+    if (pinmap_find_peripheral(pin, PinMap_GPIO_IRQ) == (uint32_t) NC) {
+        // Set pin function as GPIO pin
+        pin_function(pin, GPIO_DATA);
+    }
+
+    // Return pin mask
+    return (1 << (pin & 0x07));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    // Store above pin mask, pin name into GPIO object
+    obj->pin      = pin;
+    obj->mask     = gpio_set(pin);
+    obj->port     = (GPIO_Port) (pin >> 3);
+    if ((PortName)obj->port == PortH) {
+        CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
+    }
+    if ((PortName)obj->port == PortJ) {
+        CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    // Set pin mode
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    // Set direction
+    switch (direction) {
+        case PIN_INPUT:
+            // Set pin input
+            GPIO_SetInput(obj->port, obj->mask);
+            break;
+        case PIN_OUTPUT:
+            // Set pin output
+            GPIO_SetOutput(obj->port, obj->mask);
+            break;
+        case PIN_INOUT:
+            // Set pin both input and output
+            GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
+            GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE);
+            break;
+        default:
+            error("Invalid direction\n");
+            break;
+    }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    // Write gpio object pin data
+    if ((value == 0) || (value == 1)) {
+        GPIO_WriteDataBit(obj->port, obj->mask, value);
+    } else {
+        error("Invalid value\n");
+    }
+}
+
+int gpio_read(gpio_t *obj)
+{
+    // Read gpio object pin data
+    return GPIO_ReadDataBit(obj->port, obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,234 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_critical.h"
+
+#define CHANNEL_NUM        6
+
+const PinMap PinMap_GPIO_IRQ[] = {
+    {PD5, GPIO_IRQ_0, PIN_DATA(0, 0)},
+    {PA5, GPIO_IRQ_1, PIN_DATA(0, 0)},
+    {PA6, GPIO_IRQ_2, PIN_DATA(0, 0)},
+    {PF1, GPIO_IRQ_3, PIN_DATA(0, 0)},
+    {PC5, GPIO_IRQ_4, PIN_DATA(0, 0)},
+    {PF0, GPIO_IRQ_5, PIN_DATA(0, 0)},
+    {NC,  NC,         0}
+};
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
+
+static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index)
+{
+    uint32_t val;
+    GPIO_Port port;
+    uint32_t mask;
+    INTIFAO_INTActiveState ActiveState;
+    port = (GPIO_Port)(pin >> 3);
+    mask = 0x01 << (pin & 0x07);
+    // Clear interrupt request
+    INTIFAO_ClearINTReq((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
+    // Clear gpio pending interrupt
+    NVIC_ClearPendingIRQ((IRQn_Type)irq_id);
+    ActiveState = INTIFAO_GetSTBYReleaseINTState((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index));
+    INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
+                                 ActiveState, DISABLE);
+    // Get pin value
+    val = GPIO_ReadDataBit(port, mask);
+    switch (val) {
+        // Falling edge detection
+        case 0:
+            hal_irq_handler[index](channel_ids[index], IRQ_FALL);
+            break;
+        // Rising edge detection
+        case 1:
+            hal_irq_handler[index](channel_ids[index], IRQ_RISE);
+            break;
+        default:
+            break;
+    }
+
+    // Enable interrupt request
+    INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index),
+                                 ActiveState, ENABLE);
+}
+
+void INT0_IRQHandler(void)
+{
+    INT_IRQHandler(PD5, GPIO_IRQ_0, 0);
+}
+
+void INT1_IRQHandler(void)
+{
+    INT_IRQHandler(PA5, GPIO_IRQ_1, 1);
+}
+
+void INT2_IRQHandler(void)
+{
+    INT_IRQHandler(PA6, GPIO_IRQ_2, 2);
+}
+
+void INT3_IRQHandler(void)
+{
+    INT_IRQHandler(PF1, GPIO_IRQ_3, 3);
+}
+
+void INT4_IRQHandler(void)
+{
+    INT_IRQHandler(PC5, GPIO_IRQ_4, 4);
+}
+
+void INT5_IRQHandler(void)
+{
+    INT_IRQHandler(PF0, GPIO_IRQ_5, 5);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    // Get gpio interrupt ID
+    obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
+    core_util_critical_section_enter();
+    // Get pin mask
+    obj->mask = (uint32_t)(1 << (pin & 0x07));
+    // Get GPIO port
+    obj->port = (GPIO_Port)(pin >> 3);
+    // Set pin level as LOW
+    GPIO_WriteDataBit(obj->port, obj->mask, 0);
+    // Enable gpio interrupt function
+    pinmap_pinout(pin, PinMap_GPIO_IRQ);
+
+    // Get GPIO irq source
+    switch (obj->irq_id) {
+        case GPIO_IRQ_0:
+            obj->irq_src = INTIFAO_INT_SRC_0;
+            break;
+        case GPIO_IRQ_1:
+            obj->irq_src = INTIFAO_INT_SRC_1;
+            break;
+        case GPIO_IRQ_2:
+            obj->irq_src = INTIFAO_INT_SRC_2;
+            break;
+        case GPIO_IRQ_3:
+            obj->irq_src = INTIFAO_INT_SRC_3;
+            break;
+        case GPIO_IRQ_4:
+            obj->irq_src = INTIFAO_INT_SRC_4;
+            break;
+        case GPIO_IRQ_5:
+            obj->irq_src = INTIFAO_INT_SRC_5;
+            break;
+        default:
+            break;
+    }
+
+    // Save irq handler
+    hal_irq_handler[obj->irq_src] = handler;
+    // Save irq id
+    channel_ids[obj->irq_src] = id;
+    // Initialize interrupt event as both edges detection
+    obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
+    // Set interrupt event and enable INTx clear
+    INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
+    // Clear gpio pending interrupt
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    core_util_critical_section_exit();;
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    // Clear gpio_irq
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    // Reset interrupt handler
+    hal_irq_handler[obj->irq_src] = NULL;
+    // Reset interrupt id
+    channel_ids[obj->irq_src] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    //Disable GPIO interrupt on obj
+    gpio_irq_disable(obj);
+    if (enable) {
+        // Get gpio interrupt event
+        if (event == IRQ_RISE) {
+            if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
+                    (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
+            } else {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
+            }
+        } else if (event == IRQ_FALL) {
+            if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
+                    (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES;
+            } else {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
+            }
+        } else {
+            error("Not supported event\n");
+        }
+    } else {
+        // Get gpio interrupt event
+        if (event == IRQ_RISE) {
+            if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) ||
+                    (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
+            } else {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING;
+            }
+        } else if (event == IRQ_FALL) {
+            if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) ||
+                    (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID;
+            } else {
+                obj->event = INTIFAO_INT_ACTIVE_STATE_RISING;
+            }
+        } else {
+            error("Not supported event\n");
+        }
+    }
+
+    if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID) {
+        // Set interrupt event and enable INTx clear
+        INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE);
+        GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE);
+    } else {
+        GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
+    }
+
+    // Clear interrupt request
+    INTIFAO_ClearINTReq(obj->irq_src);
+    // Enable GPIO interrupt on obj
+    gpio_irq_enable(obj);
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    // Clear and Enable gpio_irq object
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    // Disable gpio_irq object
+    NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    uint32_t mask;
+    GPIO_Port port;
+} gpio_t;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return (obj->pin != (PinName)NC);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,343 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+
+#define I2C_NACK                (0)
+#define I2C_ACK                 (1)
+#define I2C_NO_DATA             (0)
+#define I2C_READ_ADDRESSED      (1)
+#define I2C_WRITE_GENERAL       (2)
+#define I2C_WRITE_ADDRESSED     (3)
+#define SELF_ADDR               (0xE0)
+#define I2C_TIMEOUT             (100000)
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {PC1, I2C_0, PIN_DATA(1, 2)},
+    {PG1, I2C_1, PIN_DATA(1, 2)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {PC0, I2C_0, PIN_DATA(1, 2)},
+    {PG0, I2C_1, PIN_DATA(1, 2)},
+    {NC,  NC,    0}
+};
+
+void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx);
+// Clock setting structure definition
+typedef struct {
+    uint32_t sck;
+    uint32_t prsck;
+} I2C_clock_setting_t;
+
+static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {20, 24, 32, 48, 80, 144, 272, 528};  // SCK Divider value table
+static uint32_t start_flag = 0;
+I2C_clock_setting_t clk;
+I2C_State status;
+
+static int32_t wait_status(i2c_t *obj)
+{
+    volatile int32_t timeout = I2C_TIMEOUT;
+
+    while (I2C_GetINTI2CStatus(obj->i2c) == DISABLE) {
+        if ((timeout--) == 0) {
+            return (-1);
+        }
+    }
+    return (0);
+}
+
+// Initialize the I2C peripheral. It sets the default parameters for I2C
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    MBED_ASSERT(obj != NULL);
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)i2c_name != NC);
+
+    switch (i2c_name) {
+        case I2C_0:
+            CG_SetFcPeriphA(CG_FC_PERIPH_I2C0, ENABLE);
+            obj->i2c = TSB_I2C0;
+            obj->IRQn = INTI2C0_IRQn;
+            break;
+        case I2C_1:
+            CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE);
+            obj->i2c = TSB_I2C1;
+            obj->IRQn = INTI2C1_IRQn;
+            break;
+        default:
+            error("I2C is not available");
+            break;
+    }
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pin_mode(sda, OpenDrain);
+    pin_mode(sda, PullUp);
+
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    pin_mode(scl, OpenDrain);
+    pin_mode(scl, PullUp);
+
+    NVIC_DisableIRQ(obj->IRQn);
+
+    i2c_reset(obj);
+    i2c_frequency(obj, 100000);
+}
+
+// Configure the I2C frequency
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    uint64_t sck, tmp_sck;
+    uint64_t prsck, tmp_prsck;
+    uint64_t fscl, tmp_fscl;
+    uint64_t fx;
+
+    SystemCoreClockUpdate();
+
+    if (hz <= 1000000) {
+        sck   = tmp_sck   = 0;
+        prsck = tmp_prsck = 1;
+        fscl  = tmp_fscl  = 0;
+        for (prsck = 1; prsck <= 32; prsck++) {
+            fx = ((uint64_t)SystemCoreClock / prsck);
+            if ((fx < 40000000U) && (fx > 6666666U)) {
+                for (sck = 0; sck <= 7; sck++) {
+                    fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
+                    if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
+                        tmp_fscl = fscl;
+                        tmp_sck = sck;
+                        tmp_prsck = (prsck < 32)? prsck: 0;
+                    }
+                }
+            }
+        }
+        clk.sck = (uint32_t)tmp_sck;
+        clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck) : 0;
+    }
+    obj->myi2c.I2CSelfAddr = SELF_ADDR;
+    obj->myi2c.I2CDataLen = I2C_DATA_LEN_8;
+    obj->myi2c.I2CACKState = ENABLE;
+    obj->myi2c.I2CClkDiv = clk.sck;
+    obj->myi2c.PrescalerClkDiv = clk.prsck;
+
+    I2C_Init(obj->i2c, &obj->myi2c);
+    NVIC_DisableIRQ(obj->IRQn);
+}
+
+int i2c_start(i2c_t *obj)
+{
+    start_flag = 1;
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    I2C_GenerateStop(obj->i2c);
+    return 0;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    I2C_SWReset(obj->i2c);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    int32_t result = 0;
+    int32_t count = 0;
+
+    if (length > 0) {
+        start_flag = 1;  // Start Condition
+        if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) {
+            while (count < length) {
+                int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1));
+                if (pdata < 0) {
+                    break;
+                }
+                data[count++] = (uint8_t)pdata;
+            }
+            result = count;
+        } else {
+            stop = 1;
+            result = I2C_ERROR_NO_SLAVE;
+        }
+
+        if (stop) {  // Stop Condition
+            i2c_stop(obj);
+        }
+    }
+    return (result);
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)  // Blocking sending data
+{
+    int32_t result = 0;
+    int32_t count = 0;
+
+    start_flag = 1; // Start Condition
+    if (i2c_byte_write(obj, address) == I2C_ACK) {
+        while (count < length) {
+            if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
+                break;
+            }
+        }
+        result = count;
+    } else {
+        stop = 1;
+        result = I2C_ERROR_NO_SLAVE;
+    }
+
+    if (stop) {  // Stop Condition
+        i2c_stop(obj);
+    }
+    return (result);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    int32_t result;
+
+    I2C_ClearINTOutput(obj->i2c);
+
+    if (last) {
+        I2C_SelectACKoutput(obj->i2c, ENABLE);
+    } else {
+        I2C_SelectACKoutput(obj->i2c, DISABLE);
+    }
+    I2C_SetSendData(obj->i2c, 0x00);
+
+    if (wait_status(obj) < 0) {
+        result = -1;
+    } else {
+        result = (int32_t)I2C_GetReceiveData(obj->i2c);
+    }
+    return (result);
+}
+
+void I2C_Start_Condition(i2c_t *p_obj, uint32_t data)
+{
+    status = I2C_GetState(p_obj->i2c);
+    if (status.Bit.BusState) {
+        I2C_SetRepeatStart(p_obj->i2c, ENABLE);
+    }
+    I2C_SetSendData(p_obj->i2c, (uint32_t)data);
+    I2C_GenerateStart(p_obj->i2c);
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    int32_t result;
+
+    I2C_ClearINTOutput(obj->i2c);
+
+    if (start_flag == 1) {
+        I2C_Start_Condition(obj, (uint32_t)data);
+        start_flag = 0;
+    } else {
+        I2C_SetSendData(obj->i2c, (uint32_t)data);
+    }
+
+    if (wait_status(obj) < 0) {
+        return (-1);
+    }
+
+    status = I2C_GetState(obj->i2c);
+    if (!status.Bit.LastRxBit) {
+        result = 1;
+    } else {
+        result = 0;
+    }
+    return (result);
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+    i2c_reset(obj);
+
+    obj->myi2c.I2CDataLen = I2C_DATA_LEN_8;
+    obj->myi2c.I2CACKState = ENABLE;
+    obj->myi2c.I2CClkDiv = clk.sck;
+    obj->myi2c.PrescalerClkDiv = clk.prsck;
+
+    if (enable_slave) {
+        obj->myi2c.I2CSelfAddr = obj->address;
+        I2C_SetINTI2CReq(obj->i2c, ENABLE);
+    } else {
+        obj->myi2c.I2CSelfAddr = SELF_ADDR;
+        NVIC_DisableIRQ(obj->IRQn);
+        I2C_ClearINTOutput(obj->i2c);
+    }
+    I2C_Init(obj->i2c, &obj->myi2c);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+    int32_t result = I2C_NO_DATA;
+
+    if  ((I2C_GetINTI2CStatus(obj->i2c)) && (I2C_GetSlaveAddrMatchState(obj->i2c))) {
+        status = I2C_GetState(obj->i2c);
+        if (!status.Bit.TRx) {
+            result = I2C_WRITE_ADDRESSED;
+        } else {
+            result = I2C_READ_ADDRESSED;
+        }
+    }
+    return (result);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+    int32_t count = 0;
+
+    while (count < length) {
+        int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1));
+        status = I2C_GetState(obj->i2c);
+        if (status.Bit.TRx) {
+            return (count);
+        } else {
+            if (pdata < 0) {
+                break;
+            }
+            data[count++] = (uint8_t)pdata;
+        }
+    }
+    i2c_slave_mode(obj, 1);
+    return (count);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+    int32_t count = 0;
+
+    while (count < length) {
+        if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
+            break;
+        }
+    }
+    i2c_slave_mode(obj, 1);
+    return (count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+    obj->address = address & 0xFE;
+    i2c_slave_mode(obj, 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "tmpm066_gpio.h"
+#include "tmpm066_uart.h"
+#include "tmpm066_cg.h"
+#include "tmpm066_intifao.h"
+#include "tmpm066_i2c.h"
+#include "tmpm066_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t mask;
+    GPIO_Port port;
+    uint32_t irq_id;
+    INTIFAO_INTActiveState event;
+    INTIFAO_INTSrc irq_src;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    PinName pin;
+    TSB_TB_TypeDef *channel;
+    uint16_t trailing_timing;
+    uint16_t leading_timing;
+    uint16_t divisor;
+    float period;
+};
+
+struct serial_s {
+    PinName pin;
+    uint32_t index;
+    TSB_SC_TypeDef *UARTx;
+    UART_InitTypeDef uart_config;
+};
+
+struct analogin_s {
+    PinName pin;
+    ADCName adc;
+    TSB_AD_TypeDef *obj;
+};
+
+struct i2c_s {
+    uint32_t address;
+    IRQn_Type IRQn;
+    TSB_I2C_TypeDef *i2c;
+    I2C_InitTypeDef myi2c;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "tmpm066_gpio.h"
+
+#define PIN_FUNC_MAX        6
+
+void pin_function(PinName pin, int function)
+{
+    uint32_t port = 0;
+    uint8_t bit = 0;
+    uint8_t i = 0;
+    uint8_t func = 0;
+    uint8_t dir = 0;
+
+    // Assert that pin is valid
+    MBED_ASSERT(pin != NC);
+
+    // Calculate pin function and pin direction
+    func = PIN_FUNC(function);
+    dir  = PIN_DIR(function);
+    // Calculate port and pin position
+    port = PIN_PORT(pin);
+    bit  = PIN_POS(pin);
+    // Set function if function is in range
+    if (func <= PIN_FUNC_MAX) {
+        // Disable other functions
+        for (i = 0; i < PIN_FUNC_MAX; i++) {
+            if (i != (func - 1)) {
+                GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit));
+            }
+        }
+        // Set pin function
+        if (func) {
+            GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit));
+        }
+    }
+
+    // Set direction if direction is in range
+    switch (dir) {
+        case PIN_INPUT:
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PIN_OUTPUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PIN_INOUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    uint32_t port = 0;
+    uint8_t bit = 0;
+
+    // Assert that pin is valid
+    MBED_ASSERT(pin != NC);
+
+    // Check if function is in range
+    if (mode > OpenDrain) {
+        return;
+    }
+    // Calculate port and pin position
+    port = PIN_PORT(pin);
+    bit = PIN_POS(pin);
+    // Set pin mode
+    switch (mode) {
+        case PullNone:
+            GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE);
+            GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE);
+            GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PullUp:
+            GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        case PullDown:
+            GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        case OpenDrain:
+            GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        default:
+            break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+
+#define PORT_PIN_NUM        8
+
+PinName port_pin(PortName port, int pin_n)
+{
+    PinName pin = NC;
+    pin = (PinName)((port << 3) | pin_n);
+    return pin;
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    uint8_t i = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(port <= PortJ);
+
+    // Store port and port mask for future use
+    obj->port = port;
+    obj->mask = mask;
+
+    if ((PortName)obj->port == PortH) {
+        CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
+    }
+    if ((PortName)obj->port == PortJ) {
+        CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
+    }
+
+    // Set port function and port direction
+    for (i = 0; i < PORT_PIN_NUM; i++) {
+        // If the pin is used
+        if (obj->mask & (1 << i)) {
+            pin_function(port_pin(obj->port, i), dir);
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint8_t i = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortJ);
+
+    // Set mode for masked pins
+    for (i = 0; i < PORT_PIN_NUM; i++) {
+        // If the pin is used
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortJ);
+
+    // Set direction for masked pins
+    switch (dir) {
+        case PIN_INPUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        case PIN_OUTPUT:
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        case PIN_INOUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    uint8_t port_data = 0;
+    uint8_t data = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortJ);
+
+    // Get current data of port
+    port_data = GPIO_ReadData((GPIO_Port)obj->port);
+    // Calculate data to write to masked pins
+    data = (port_data & ~obj->mask) | (value & obj->mask);
+    // Write data to masked pins of the port
+    GPIO_WriteData((GPIO_Port)obj->port, data);
+}
+
+int port_read(port_t *obj)
+{
+    uint8_t port_data = 0;
+    uint8_t data = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortJ);
+
+    // Get current data of port
+    port_data = GPIO_ReadData((GPIO_Port)obj->port);
+    // Calculate data of masked pins
+    data = port_data & obj->mask;
+    return data;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "tmpm066_tmrb.h"
+
+#define CLOCK_FREQUENCY         SystemCoreClock // input source clock
+#define MAX_COUNTER_16B         0xFFFF
+#define DEFAULT_CLOCK_DIVISION  32
+#define DEFAULT_PERIOD          0.02f // 20ms
+
+static const PinMap PinMap_PWM[] = {
+    {PD1, PWM_0, PIN_DATA(1, 1)},
+    {PD2, PWM_1, PIN_DATA(1, 1)},
+    {PD3, PWM_2, PIN_DATA(1, 1)},
+    {PF4, PWM_3, PIN_DATA(1, 1)},
+    {PF5, PWM_4, PIN_DATA(1, 1)},
+    {PJ0, PWM_5, PIN_DATA(1, 1)},
+    {PJ1, PWM_6, PIN_DATA(1, 1)},
+    {NC,  NC,    0}
+};
+
+static const uint32_t prescale_tbl[] = {
+    2, 8, 32, 64, 128, 256, 512
+};
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+    uint16_t counter = 0;
+    TMRB_FFOutputTypeDef FFStruct;
+    TMRB_InitTypeDef m_tmrb;
+
+    // Determine the pwm channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    //Assert input is valid
+    MBED_ASSERT(pwm != (PWMName)NC);
+
+    // Enable clock supply to TB0
+    CG_SetFcPeriphA(CG_FC_PERIPH_TMRB0_3, ENABLE);
+    CG_SetFcPeriphA(CG_FC_PERIPH_TMRB4_6, ENABLE);
+
+    switch (pwm) {
+        case PWM_0:
+            obj->channel = TSB_TB0;
+            break;
+        case PWM_1:
+            obj->channel = TSB_TB1;
+            break;
+        case PWM_2:
+            obj->channel = TSB_TB2;
+            break;
+        case PWM_3:
+            obj->channel = TSB_TB3;
+            break;
+        case PWM_4:
+            obj->channel = TSB_TB4;
+            break;
+        case PWM_5:
+            obj->channel = TSB_TB5;
+            CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
+            break;
+        case PWM_6:
+            obj->channel = TSB_TB6;
+            CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE);
+            break;
+        default:
+            obj->channel = NULL;
+            return;
+    }
+    // Set pin function as PWM
+    pinmap_pinout(pin, PinMap_PWM);
+    obj->pin = pin;
+    obj->period = DEFAULT_PERIOD;
+    // Enable channel
+    TMRB_Enable(obj->channel);
+    // Stops and clear count operation
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    // Disables double buffering
+    TMRB_SetDoubleBuf(obj->channel, DISABLE);
+    // Set default period = 20ms, duty cycle = 0
+    obj->divisor = DEFAULT_CLOCK_DIVISION;
+    counter = (uint16_t)((DEFAULT_PERIOD * CLOCK_FREQUENCY) / obj->divisor);
+
+    // Init timer variable for using PPG mode
+    m_tmrb.Mode = TMRB_INTERVAL_TIMER;
+    m_tmrb.ClkDiv = TMRB_CLK_DIV_32;
+    m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR;     // clear UC when matching value
+    m_tmrb.TrailingTiming = counter;        // period = 20ms
+    m_tmrb.LeadingTiming = counter;         // duty cycle = 0%
+
+    // Init timer function
+    TMRB_Init(obj->channel, &m_tmrb);
+    obj->trailing_timing = counter;
+    obj->leading_timing = counter;
+
+    // Enable double buffering
+    TMRB_SetDoubleBuf(obj->channel, ENABLE);
+
+    // Setting to TBxFF0 reverse trigger
+    FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+    FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING;
+    TMRB_SetFlipFlop(obj->channel, &FFStruct);
+
+    // Start count operation
+    TMRB_SetRunState(obj->channel, TMRB_RUN);
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+    // Stops and clear count operation
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    pwmout_write(obj,0);
+    obj->pin = NC;
+    obj->channel = NULL;
+    obj->trailing_timing = 0;
+    obj->leading_timing = 0;
+    obj->divisor = 0;
+}
+
+void pwmout_write(pwmout_t *obj, float value)
+{
+    TMRB_FFOutputTypeDef FFStruct;
+
+    // Stop timer for setting clock again
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    // values outside this range will be saturated to 0.0f or 1.0f
+    // Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated
+    if (value <= 0.0f) {
+        value = 0;
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+        FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
+        TMRB_SetFlipFlop(obj->channel, &FFStruct);
+    } else if (value >= 1.0f) {
+        value = 1;
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
+        FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
+        TMRB_SetFlipFlop(obj->channel, &FFStruct);
+    } else {
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+        FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING;
+        TMRB_SetFlipFlop(obj->channel, &FFStruct);
+    }
+
+    // Store the new leading_timing value
+    obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value);
+
+    // Setting TBxRG0 register
+    TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing);
+    TMRB_SetRunState(obj->channel, TMRB_RUN);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+    float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
+    return duty_cycle;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+    pwmout_period_us(obj, (int)(seconds * 1000000.0f));
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+    float seconds = 0;
+    int cycles = 0;
+    uint32_t clkdiv = 0;
+    float duty_cycle = 0;
+    TMRB_InitTypeDef m_tmrb;
+    seconds = (float)((us) / 1000000.0f);
+    obj->period = seconds;
+
+    MBED_ASSERT(obj->channel != NULL);
+
+    // Select highest timer resolution
+    for (int i = 0; i < 7; ++i) {
+        cycles = (int)((CLOCK_FREQUENCY / prescale_tbl[i]) * seconds);
+        if (cycles <= MAX_COUNTER_16B) {
+            clkdiv = i + 1; // range 1:7
+            break;
+        }
+    }
+    // Stop timer for setting clock again
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    // Restore the duty-cycle
+    duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
+    obj->trailing_timing = cycles;
+    obj->leading_timing = (cycles - (uint16_t)(cycles * duty_cycle));
+
+    // Change the source clock division and period
+    m_tmrb.Mode = TMRB_INTERVAL_TIMER;
+    m_tmrb.ClkDiv = clkdiv;
+    m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR;
+    m_tmrb.TrailingTiming = obj->trailing_timing;
+    m_tmrb.LeadingTiming = obj->leading_timing;
+
+    //Init timer function
+    TMRB_Init(obj->channel, &m_tmrb);
+    //Start timer function
+    TMRB_SetRunState(obj->channel, TMRB_RUN);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+    float seconds = 0;
+    float value = 0;
+
+    MBED_ASSERT(obj->channel != NULL);
+
+    seconds = (float)(us / 1000000.0f);
+    value = (((seconds / obj->period) * 100.0f) / 100.0f);
+    pwmout_write(obj, value);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,249 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "serial_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+
+#define UART_NUM              2
+
+static const PinMap PinMap_UART_TX[] = {
+    {PC2, SERIAL_0, PIN_DATA(1, 1)},
+    {PE2, SERIAL_1, PIN_DATA(1, 1)},
+    {NC,  NC,       0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {PC3, SERIAL_0, PIN_DATA(1, 0)},
+    {PE1, SERIAL_1, PIN_DATA(1, 0)},
+    {NC,  NC,       0}
+};
+
+static int serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    int is_stdio_uart = 0;
+
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)uart_name != NC);
+
+    obj->index = uart_name;
+    // Initialize UART instance
+    switch (uart_name) {
+        case SERIAL_0:
+            CG_SetFcPeriphA(CG_FC_PERIPH_SIO0, ENABLE);
+            obj->UARTx = UART0;
+            break;
+        case SERIAL_1:
+            CG_SetFcPeriphB(CG_FC_PERIPH_SIO1, ENABLE);
+            obj->UARTx = UART1;
+            break;
+        default:
+            break;
+    }
+
+    obj->uart_config.BaudRate = 9600;
+    obj->uart_config.DataBits = UART_DATA_BITS_8;
+    obj->uart_config.StopBits = UART_STOP_BITS_1;
+    obj->uart_config.Parity   = UART_NO_PARITY;
+    obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL;
+
+    if (tx != NC && rx != NC) {
+        obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
+    } else {
+        if (tx != NC) {
+            obj->uart_config.Mode = UART_ENABLE_TX;
+        } else {
+            if (rx != NC) {
+                obj->uart_config.Mode = UART_ENABLE_RX;
+            }
+        }
+    }
+
+    // Pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    // Initialize UART configure
+    UART_Enable(obj->UARTx);
+    UART_SetIdleMode(obj->UARTx, ENABLE);
+    UART_Init(obj->UARTx, &obj->uart_config);
+    is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    // Disable UART
+    UART_Disable(obj->UARTx);
+    UART_SWReset(obj->UARTx);
+    // Set information of object to invalid
+    obj->uart_config.BaudRate = 0;
+    obj->uart_config.DataBits = 0;
+    obj->uart_config.StopBits = 0;
+    obj->uart_config.Parity = 0;
+    obj->uart_config.Mode = 0;
+    obj->uart_config.FlowCtrl = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    obj->uart_config.BaudRate = baudrate;
+    UART_Init(obj->UARTx, &obj->uart_config);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    // 0: 1 stop bits, 1: 2 stop bits
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+                (parity == ParityForced1) || (parity == ParityForced0));
+    // 0: 7 data bits ... 2: 9 data bits
+    MBED_ASSERT((data_bits > 6) && (data_bits < 10));
+
+    obj->uart_config.DataBits = data_bits;
+    obj->uart_config.StopBits = stop_bits;
+    obj->uart_config.Parity = parity;
+    UART_Init(obj->UARTx, &obj->uart_config);
+}
+
+// INTERRUPTS HANDLING
+void INTTX0_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
+}
+
+void INTRX0_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
+}
+
+void INTTX1_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
+}
+
+void INTRX1_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    IRQn_Type irq_n = (IRQn_Type)0;
+
+    switch (obj->index) {
+        case SERIAL_0:
+            if (irq == RxIrq) {
+                irq_n = INTRX0_IRQn;
+            } else {
+                irq_n = INTTX0_IRQn;
+            }
+            break;
+        case SERIAL_1:
+            if (irq == RxIrq) {
+                irq_n = INTRX1_IRQn;
+            } else {
+                irq_n = INTTX1_IRQn;
+            }
+            break;
+        default:
+            break;
+    }
+
+    if (enable) {
+        NVIC_EnableIRQ(irq_n);
+    } else {
+        NVIC_DisableIRQ(irq_n);
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    // Wait until Rx buffer is full
+    while (!serial_readable(obj)) {
+        // Do nothing
+    }
+
+    return UART_GetRxData(obj->UARTx);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    // Wait until Tx buffer is empty
+    while (!serial_writable(obj)) {
+        // Do nothing
+    }
+
+    UART_SetTxData(obj->UARTx, (uint32_t)c);
+}
+
+int serial_readable(serial_t *obj)
+{
+    int ret = 0;
+
+    if (UART_GetBufState(obj->UARTx, UART_RX) == DONE) {
+        ret = 1;
+    }
+
+    return ret;
+}
+
+int serial_writable(serial_t *obj)
+{
+    int ret = 0;
+
+    if (UART_GetBufState(obj->UARTx, UART_TX) == DONE) {
+        ret = 1;
+    }
+
+    return ret;
+}
+
+void serial_clear(serial_t *obj)
+{
+    UART_TxFIFOClear(obj->UARTx);
+    UART_RxFIFOClear(obj->UARTx);
+    UART_TxBufferClear(obj->UARTx);
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+}
+
+void serial_break_clear(serial_t *obj)
+{
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+
+// number of warm-up cycle = warm-up time to set / input frequency cycle (s)
+// number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60
+#define CG_WUODR_INT     ((uint16_t)0xea60)
+
+void external_losc_enable(void);
+
+void hal_sleep(void)
+{
+    // Set low power consumption mode IDLE
+    CG_SetSTBYMode(CG_STBY_MODE_IDLE);
+    // Enter idle mode
+    __WFI();
+}
+
+void hal_deepsleep(void)
+{
+    // Set low power consumption mode STOP1
+    CG_SetSTBYMode(CG_STBY_MODE_STOP1);
+    // Setup warm up time
+    CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT);
+    // Enter stop1 mode
+    __WFI();
+    // Switch over from IHOSC to EHOSC
+    external_losc_enable();
+}
+
+void external_losc_enable(void)
+{
+    // Enable high-speed oscillator
+    CG_SetFoscSrc(CG_FOSC_OSC_EXT);
+    // Select internal(fIHOSC) as warm-up clock
+    CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT);
+    // Start warm-up
+    CG_StartWarmUp();
+    // Wait until EHOSC become stable
+    while (CG_GetWarmUpState() != DONE) {
+        // Do nothing
+    }
+
+    // Set fosc source
+    CG_SetFoscSrc(CG_FOSC_OSC_EXT);
+    // Wait for <OSCSEL> to become "1"
+    while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) {
+        // Do nothing
+    }
+
+    // Stop IHOSC
+    CG_SetFoscSrc(CG_FOSC_OSC_INT);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+#include "mbed_critical.h"
+
+#define TMR16A_100US                0x960 // fsys = fc = 24MHz, Ttmra = 1/24us, 100us*24us = 2400 = 0x960
+#define TMR16A_SYSCK                ((uint32_t)0x00000001)
+#define TMR16A_RUN                  ((uint32_t)0x00000001)
+#define TMR16A_STOP                 ((uint32_t)0x00000000)
+#define OVERFLOW_32BIT              (0xFFFFFFFF / 0x64)
+
+static uint8_t us_ticker_inited = 0;                // Is ticker initialized yet?
+static volatile uint32_t ticker_int_counter = 0;    // Amount of overflows until user interrupt
+static volatile uint32_t us_ticker = 0;             // timer counter
+
+void INT16A0_IRQHandler(void)
+{
+    us_ticker++;
+
+    if (us_ticker > OVERFLOW_32BIT) {
+        us_ticker = 0;
+    }
+}
+
+void INT16A1_IRQHandler(void)
+{
+    us_ticker_irq_handler();
+}
+
+// initialize us_ticker
+void us_ticker_init(void)
+{
+    // Enable clock supply to TA0
+    CG_SetFcPeriphA(CG_FC_PERIPH_TMR16A, ENABLE);
+    if (us_ticker_inited) {
+        return;
+    }
+    us_ticker_inited = 1;
+
+    // Stops and clear count operation
+    TSB_T16A0->RUN = TMR16A_STOP;
+    TSB_T16A0->CR = TMR16A_SYSCK;
+    // Permits INTTA0 interrupt
+    NVIC_EnableIRQ(INT16A0_IRQn);
+    // Match counter set to max value
+    TSB_T16A0->RG = TMR16A_100US;
+    TSB_T16A0->RUN = TMR16A_RUN;
+}
+
+uint32_t us_ticker_read(void)
+{
+    uint32_t ret_val = 0;
+
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    uint32_t tickerbefore = 0;
+    do {
+        tickerbefore = us_ticker;
+        ret_val = (us_ticker * 100);
+    } while (tickerbefore != us_ticker);
+
+    return ret_val;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    uint32_t delta = 0;
+
+    // Stops and clear count operation
+    TSB_T16A1->RUN = TMR16A_STOP;
+    TSB_T16A1->CR = TMR16A_SYSCK;
+    // Set the compare register
+    delta = (timestamp - us_ticker_read());
+    TSB_T16A1->RG = delta;
+    // Set Interrupt
+    NVIC_EnableIRQ(INT16A1_IRQn);
+    // Start TMR_TA1 timer
+    TSB_T16A1->RUN = TMR16A_RUN;
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(INT16A1_IRQn);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    NVIC_DisableIRQ(INT16A1_IRQn);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    //no flags to clear
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/mbed_rtx.h	Thu Aug 31 17:27:04 2017 +0100
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MBED_RTX_H
+#define MBED_MBED_RTX_H
+
+#if defined(TARGET_TMPM066)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP                        (0x20004000UL)
+#endif
+
+#endif
+
+#endif  // MBED_MBED_RTX_H

--- a/targets/targets.json	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/targets.json	Thu Aug 31 17:27:04 2017 +0100
@@ -1279,7 +1279,7 @@
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0+",
-        "extra_labels_add": ["STM32L0", "STM32L053R8"],
+        "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1493,7 +1493,7 @@
     "DISCO_L053C8": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M0+",
-        "extra_labels_add": ["STM32L0", "STM32L053C8"],
+        "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
         "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
@@ -1649,6 +1649,12 @@
         "core": "Cortex-M3",
         "default_toolchain": "ARM",
         "extra_labels_add": ["STM32L1", "STM32L151CC"],
+        "config": {
+            "hse_value": {
+            "value": "24000000",
+            "macro_name": "HSE_VALUE"
+            }
+        },
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "device_has_add": ["ANALOGOUT", "FLASH"],
         "release_versions": ["5"],
@@ -3128,7 +3134,26 @@
         "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
+                "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            }
+        },
         "inherits": ["Target"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH"],
         "features": ["LWIP"],
         "release_versions": ["5"],
@@ -3178,6 +3203,24 @@
         "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453", "FLASH_CMSIS_ALGO"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+                "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            }
+        },
         "inherits": ["Target"],
         "progen": {"target": "numaker-pfm-m453"},
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
@@ -3259,5 +3302,57 @@
         "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2"],
         "device_name": "nRF52832_xxAA"
+    },
+    "NUMAKER_PFM_M487": {
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+                "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            },
+            "usb-device-hsusbd": {
+                "help": "Select high-speed USB device or not",
+                "value": 1
+            },
+            "ctrl01-enable": {
+                "help": "Enable control_01",
+                "value": 0
+            }
+        },
+        "inherits": ["Target"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN"],
+        "features": ["LWIP"],
+        "release_versions": ["5"],
+        "device_name": "M487JIDAE",
+        "bootloader_supported": true
+    },
+    "TMPM066": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "is_disk_virtual": true,
+        "extra_labels": ["TOSHIBA"],
+        "macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"],
+        "device_name": "TMPM066FWUG",
+        "detect_code": ["7011"],
+        "release_versions": ["5"]
     }
 }