Revision 0:31cd577d85a4, committed 2011-07-09

Comitter:

jp

Date:

Sat Jul 09 15:47:27 2011 +0000

Commit message:

Initial release of Snake for the mbed Game Console.

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/colors.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,326 @@
+/*
+* Copyright or © or Copr. 2010, Thomas SOETE
+* 
+*    MODIFIED BY J.P. ARMSTRONG FROM WWW.MBEDGC.COM
+*
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_LEDS_H__
+#define __SIMPLELIB_LEDS_H__
+
+#include "mbed_globals.h"
+
+/** Bits **/
+#define COLOR_OFF 0
+#define RED1 (1 << 25)
+#define RED2 (1 << 24)
+#define RED3 (1 << 23)
+#define GRN1 (1 << 16)
+#define GRN2 (1 << 6)
+#define GRN3 (1 << 7)
+
+#define BLU1 (1 << 8)
+#define BLU2 (1 << 9)
+
+#define COLOR_MASK ( RED1 | RED2 | RED3 | GRN1 | GRN2 | GRN3 | BLU1 | BLU2 )
+
+const uint32_t COLOR_VAR_MASK[] = {
+	RED1, 
+	RED2, 
+	RED1|RED2, 
+	RED3, 
+	RED1|RED3, 
+	RED2|RED3, 
+	RED1|RED2|RED3, 
+	GRN1, 
+	RED1|GRN1, 
+	RED2|GRN1, 
+	RED1|RED2|GRN1, 
+	RED3|GRN1, 
+	RED1|RED3|GRN1, 
+	RED2|RED3|GRN1, 
+	RED1|RED2|RED3|GRN1, 
+	GRN2, 
+	RED1|GRN2, 
+	RED2|GRN2, 
+	RED1|RED2|GRN2, 
+	RED3|GRN2, 
+	RED1|RED3|GRN2, 
+	RED2|RED3|GRN2, 
+	RED1|RED2|RED3|GRN2, 
+	GRN1|GRN2, 
+	RED1|GRN1|GRN2, 
+	RED2|GRN1|GRN2, 
+	RED1|RED2|GRN1|GRN2, 
+	RED3|GRN1|GRN2, 
+	RED1|RED3|GRN1|GRN2, 
+	RED2|RED3|GRN1|GRN2, 
+	RED1|RED2|RED3|GRN1|GRN2, 
+	GRN3, 
+	RED1|GRN3, 
+	RED2|GRN3, 
+	RED1|RED2|GRN3, 
+	RED3|GRN3, 
+	RED1|RED3|GRN3, 
+	RED2|RED3|GRN3, 
+	RED1|RED2|RED3|GRN3, 
+	GRN1|GRN3, 
+	RED1|GRN1|GRN3, 
+	RED2|GRN1|GRN3, 
+	RED1|RED2|GRN1|GRN3, 
+	RED3|GRN1|GRN3, 
+	RED1|RED3|GRN1|GRN3, 
+	RED2|RED3|GRN1|GRN3, 
+	RED1|RED2|RED3|GRN1|GRN3, 
+	GRN2|GRN3, 
+	RED1|GRN2|GRN3, 
+	RED2|GRN2|GRN3, 
+	RED1|RED2|GRN2|GRN3, 
+	RED3|GRN2|GRN3, 
+	RED1|RED3|GRN2|GRN3, 
+	RED2|RED3|GRN2|GRN3, 
+	RED1|RED2|RED3|GRN2|GRN3, 
+	GRN1|GRN2|GRN3, 
+	RED1|GRN1|GRN2|GRN3, 
+	RED2|GRN1|GRN2|GRN3, 
+	RED1|RED2|GRN1|GRN2|GRN3, 
+	RED3|GRN1|GRN2|GRN3, 
+	RED1|RED3|GRN1|GRN2|GRN3, 
+	RED2|RED3|GRN1|GRN2|GRN3, 
+	RED1|RED2|RED3|GRN1|GRN2|GRN3, 
+	BLU1, 
+	RED1|BLU1, 
+	RED2|BLU1, 
+	RED1|RED2|BLU1, 
+	RED3|BLU1, 
+	RED1|RED3|BLU1, 
+	RED2|RED3|BLU1, 
+	RED1|RED2|RED3|BLU1, 
+	GRN1|BLU1, 
+	RED1|GRN1|BLU1, 
+	RED2|GRN1|BLU1, 
+	RED1|RED2|GRN1|BLU1, 
+	RED3|GRN1|BLU1, 
+	RED1|RED3|GRN1|BLU1, 
+	RED2|RED3|GRN1|BLU1, 
+	RED1|RED2|RED3|GRN1|BLU1, 
+	GRN2|BLU1, 
+	RED1|GRN2|BLU1, 
+	RED2|GRN2|BLU1, 
+	RED1|RED2|GRN2|BLU1, 
+	RED3|GRN2|BLU1, 
+	RED1|RED3|GRN2|BLU1, 
+	RED2|RED3|GRN2|BLU1, 
+	RED1|RED2|RED3|GRN2|BLU1, 
+	GRN1|GRN2|BLU1, 
+	RED1|GRN1|GRN2|BLU1, 
+	RED2|GRN1|GRN2|BLU1, 
+	RED1|RED2|GRN1|GRN2|BLU1, 
+	RED3|GRN1|GRN2|BLU1, 
+	RED1|RED3|GRN1|GRN2|BLU1, 
+	RED2|RED3|GRN1|GRN2|BLU1, 
+	RED1|RED2|RED3|GRN1|GRN2|BLU1, 
+	GRN3|BLU1, 
+	RED1|GRN3|BLU1, 
+	RED2|GRN3|BLU1, 
+	RED1|RED2|GRN3|BLU1, 
+	RED3|GRN3|BLU1, 
+	RED1|RED3|GRN3|BLU1, 
+	RED2|RED3|GRN3|BLU1, 
+	RED1|RED2|RED3|GRN3|BLU1, 
+	GRN1|GRN3|BLU1, 
+	RED1|GRN1|GRN3|BLU1, 
+	RED2|GRN1|GRN3|BLU1, 
+	RED1|RED2|GRN1|GRN3|BLU1, 
+	RED3|GRN1|GRN3|BLU1, 
+	RED1|RED3|GRN1|GRN3|BLU1, 
+	RED2|RED3|GRN1|GRN3|BLU1, 
+	RED1|RED2|RED3|GRN1|GRN3|BLU1, 
+	GRN2|GRN3|BLU1, 
+	RED1|GRN2|GRN3|BLU1, 
+	RED2|GRN2|GRN3|BLU1, 
+	RED1|RED2|GRN2|GRN3|BLU1, 
+	RED3|GRN2|GRN3|BLU1, 
+	RED1|RED3|GRN2|GRN3|BLU1, 
+	RED2|RED3|GRN2|GRN3|BLU1, 
+	RED1|RED2|RED3|GRN2|GRN3|BLU1, 
+	GRN1|GRN2|GRN3|BLU1, 
+	RED1|GRN1|GRN2|GRN3|BLU1, 
+	RED2|GRN1|GRN2|GRN3|BLU1, 
+	RED1|RED2|GRN1|GRN2|GRN3|BLU1, 
+	RED3|GRN1|GRN2|GRN3|BLU1, 
+	RED1|RED3|GRN1|GRN2|GRN3|BLU1, 
+	RED2|RED3|GRN1|GRN2|GRN3|BLU1, 
+	RED1|RED2|RED3|GRN1|GRN2|GRN3|BLU1, 
+	BLU2, 
+	RED1|BLU2, 
+	RED2|BLU2, 
+	RED1|RED2|BLU2, 
+	RED3|BLU2, 
+	RED1|RED3|BLU2, 
+	RED2|RED3|BLU2, 
+	RED1|RED2|RED3|BLU2, 
+	GRN1|BLU2, 
+	RED1|GRN1|BLU2, 
+	RED2|GRN1|BLU2, 
+	RED1|RED2|GRN1|BLU2, 
+	RED3|GRN1|BLU2, 
+	RED1|RED3|GRN1|BLU2, 
+	RED2|RED3|GRN1|BLU2, 
+	RED1|RED2|RED3|GRN1|BLU2, 
+	GRN2|BLU2, 
+	RED1|GRN2|BLU2, 
+	RED2|GRN2|BLU2, 
+	RED1|RED2|GRN2|BLU2, 
+	RED3|GRN2|BLU2, 
+	RED1|RED3|GRN2|BLU2, 
+	RED2|RED3|GRN2|BLU2, 
+	RED1|RED2|RED3|GRN2|BLU2, 
+	GRN1|GRN2|BLU2, 
+	RED1|GRN1|GRN2|BLU2, 
+	RED2|GRN1|GRN2|BLU2, 
+	RED1|RED2|GRN1|GRN2|BLU2, 
+	RED3|GRN1|GRN2|BLU2, 
+	RED1|RED3|GRN1|GRN2|BLU2, 
+	RED2|RED3|GRN1|GRN2|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN2|BLU2, 
+	GRN3|BLU2, 
+	RED1|GRN3|BLU2, 
+	RED2|GRN3|BLU2, 
+	RED1|RED2|GRN3|BLU2, 
+	RED3|GRN3|BLU2, 
+	RED1|RED3|GRN3|BLU2, 
+	RED2|RED3|GRN3|BLU2, 
+	RED1|RED2|RED3|GRN3|BLU2, 
+	GRN1|GRN3|BLU2, 
+	RED1|GRN1|GRN3|BLU2, 
+	RED2|GRN1|GRN3|BLU2, 
+	RED1|RED2|GRN1|GRN3|BLU2, 
+	RED3|GRN1|GRN3|BLU2, 
+	RED1|RED3|GRN1|GRN3|BLU2, 
+	RED2|RED3|GRN1|GRN3|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN3|BLU2, 
+	GRN2|GRN3|BLU2, 
+	RED1|GRN2|GRN3|BLU2, 
+	RED2|GRN2|GRN3|BLU2, 
+	RED1|RED2|GRN2|GRN3|BLU2, 
+	RED3|GRN2|GRN3|BLU2, 
+	RED1|RED3|GRN2|GRN3|BLU2, 
+	RED2|RED3|GRN2|GRN3|BLU2, 
+	RED1|RED2|RED3|GRN2|GRN3|BLU2, 
+	GRN1|GRN2|GRN3|BLU2, 
+	RED1|GRN1|GRN2|GRN3|BLU2, 
+	RED2|GRN1|GRN2|GRN3|BLU2, 
+	RED1|RED2|GRN1|GRN2|GRN3|BLU2, 
+	RED3|GRN1|GRN2|GRN3|BLU2, 
+	RED1|RED3|GRN1|GRN2|GRN3|BLU2, 
+	RED2|RED3|GRN1|GRN2|GRN3|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN2|GRN3|BLU2, 
+	BLU1|BLU2, 
+	RED1|BLU1|BLU2, 
+	RED2|BLU1|BLU2, 
+	RED1|RED2|BLU1|BLU2, 
+	RED3|BLU1|BLU2, 
+	RED1|RED3|BLU1|BLU2, 
+	RED2|RED3|BLU1|BLU2, 
+	RED1|RED2|RED3|BLU1|BLU2, 
+	GRN1|BLU1|BLU2, 
+	RED1|GRN1|BLU1|BLU2, 
+	RED2|GRN1|BLU1|BLU2, 
+	RED1|RED2|GRN1|BLU1|BLU2, 
+	RED3|GRN1|BLU1|BLU2, 
+	RED1|RED3|GRN1|BLU1|BLU2, 
+	RED2|RED3|GRN1|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN1|BLU1|BLU2, 
+	GRN2|BLU1|BLU2, 
+	RED1|GRN2|BLU1|BLU2, 
+	RED2|GRN2|BLU1|BLU2, 
+	RED1|RED2|GRN2|BLU1|BLU2, 
+	RED3|GRN2|BLU1|BLU2, 
+	RED1|RED3|GRN2|BLU1|BLU2, 
+	RED2|RED3|GRN2|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN2|BLU1|BLU2, 
+	GRN1|GRN2|BLU1|BLU2, 
+	RED1|GRN1|GRN2|BLU1|BLU2, 
+	RED2|GRN1|GRN2|BLU1|BLU2, 
+	RED1|RED2|GRN1|GRN2|BLU1|BLU2, 
+	RED3|GRN1|GRN2|BLU1|BLU2, 
+	RED1|RED3|GRN1|GRN2|BLU1|BLU2, 
+	RED2|RED3|GRN1|GRN2|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN2|BLU1|BLU2, 
+	GRN3|BLU1|BLU2, 
+	RED1|GRN3|BLU1|BLU2, 
+	RED2|GRN3|BLU1|BLU2, 
+	RED1|RED2|GRN3|BLU1|BLU2, 
+	RED3|GRN3|BLU1|BLU2, 
+	RED1|RED3|GRN3|BLU1|BLU2, 
+	RED2|RED3|GRN3|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN3|BLU1|BLU2, 
+	GRN1|GRN3|BLU1|BLU2, 
+	RED1|GRN1|GRN3|BLU1|BLU2, 
+	RED2|GRN1|GRN3|BLU1|BLU2, 
+	RED1|RED2|GRN1|GRN3|BLU1|BLU2, 
+	RED3|GRN1|GRN3|BLU1|BLU2, 
+	RED1|RED3|GRN1|GRN3|BLU1|BLU2, 
+	RED2|RED3|GRN1|GRN3|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN3|BLU1|BLU2, 
+	GRN2|GRN3|BLU1|BLU2, 
+	RED1|GRN2|GRN3|BLU1|BLU2, 
+	RED2|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED2|GRN2|GRN3|BLU1|BLU2, 
+	RED3|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED3|GRN2|GRN3|BLU1|BLU2, 
+	RED2|RED3|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN2|GRN3|BLU1|BLU2, 
+	GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED1|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED2|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED2|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED3|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED3|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED2|RED3|GRN1|GRN2|GRN3|BLU1|BLU2, 
+	RED1|RED2|RED3|GRN1|GRN2|GRN3|BLU1|BLU2
+};
+
+/** Macros **/
+#define COLOR_INIT()     LPC_GPIO0->FIODIR |= COLOR_MASK;
+
+#define COLOR_SET(value) do {                                   \
+                            LPC_GPIO0->FIOMASK = ~COLOR_MASK; \
+                            LPC_GPIO0->FIOPIN = COLOR_VAR_MASK[value];      \
+} while(0)
+////                                LPC_GPIO0->FIOSET = COLOR_VAR_MASK[value];     \
+////                                LPC_GPIO0->FIOCLR = ~COLOR_VAR_MASK[value] & COLOR_MASK;     \
+
+//                            LPC_GPIO0->FIOMASK = ~COLOR_MASK; \
+//                            LPC_GPIO0->FIOPIN = COLOR_VAR_MASK[value];      \
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ethernet.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,66 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_ETHERNET_H__
+#define __SIMPLELIB_ETHERNET_H__
+
+typedef __packed struct {
+    char destination[6];
+    char source[6];
+    uint16_t type;
+} ethernet_packet;
+#define asETH(x) ((ethernet_packet*)(x))
+
+#define IPV4_TYPE 0x0800
+#define ARP_TYPE  0x0806
+
+typedef __packed struct {
+    ethernet_packet eth;
+    __packed struct {
+        char hardware_type[2];
+        char protocol_type[2];
+        char hardware_size;
+        char protocol_size;
+        uint16_t opcode_request;
+        char sender_mac[6];
+        char sender_ip[4];
+        char target_mac[6];
+        char target_ip[4];
+    } arp;
+} arp_packet;
+#define asARP(x) ((arp_packet*)(x))
+
+#define ARP_REQUEST 0x0001
+#define ARP_REPLY   0x0002
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/interrupts.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,121 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_INTERRUPTS_H__
+#define __SIMPLELIB_INTERRUPTS_H__
+
+#include "mbed_globals.h"
+
+/** Interrupt Managment **/
+#define ENABLE_INTERRUPT(intr)  NVIC_EnableIRQ(intr)
+#define DISABLE_INTERRUPT(intr) NVIC_DisableIRQ(intr)
+
+#if defined ( __CC_ARM )
+    #define __IRQ     __irq
+#elif defined   ( __GNUC__ )
+    #define __IRQ     __attribute__((interrupt("IRQ")))
+#endif
+
+/* Interrupts names
+ * WDT_IRQn         Watchdog Timer Interrupt
+ * TIMER0_IRQn      Timer0 Interrupt
+ * TIMER1_IRQn      Timer1 Interrupt
+ * TIMER2_IRQn      Timer2 Interrupt
+ * TIMER3_IRQn      Timer3 Interrupt
+ * UART0_IRQn       UART0 Interrupt
+ * UART1_IRQn        UART1 Interrupt
+ * UART2_IRQn        UART2 Interrupt
+ * UART3_IRQn        UART3 Interrupt
+ * PWM1_IRQn        PWM1 Interrupt
+ * I2C0_IRQn        I2C0 Interrupt
+ * I2C1_IRQn        I2C1 Interrupt
+ * I2C2_IRQn        I2C2 Interrupt
+ * SPI_IRQn         SPI Interrupt
+ * SSP0_IRQn        SSP0 Interrupt
+ * SSP1_IRQn        SSP1 Interrupt
+ * PLL0_IRQn        PLL0 Lock (Main PLL) Interrupt
+ * RTC_IRQn         Real Time Clock Interrupt
+ * EINT0_IRQn        External Interrupt 0 Interrupt
+ * EINT1_IRQn        External Interrupt 1 Interrupt
+ * EINT2_IRQn        External Interrupt 2 Interrupt
+ * EINT3_IRQn        External Interrupt 3 Interrupt
+ * ADC_IRQn         A/D Converter Interrupt
+ * BOD_IRQn            Brown-Out Detect Interrupt
+ * USB_IRQn            USB Interrupt
+ * CAN_IRQn            CAN Interrupt
+ * DMA_IRQn            General Purpose DMA Interrupt
+ * I2S_IRQn            I2S Interrupt
+ * ENET_IRQn        Ethernet Interrupt
+ * RIT_IRQn            Repetitive Interrupt Timer Interrupt
+ * MCPWM_IRQn        Motor Control PWM Interrupt
+ * QEI_IRQn            Quadrature Encoder Interface Interrupt
+ * PLL1_IRQn        PLL1 Lock (USB PLL) Interrupt
+ */
+
+/* Default interrupt handlers
+ * WDT_IRQHandler
+ * TIMER0_IRQHandler
+ * TIMER1_IRQHandler
+ * TIMER2_IRQHandler
+ * TIMER3_IRQHandler
+ * UART0_IRQHandler
+ * UART1_IRQHandler
+ * UART2_IRQHandler
+ * UART3_IRQHandler
+ * PWM1_IRQHandler
+ * I2C0_IRQHandler
+ * I2C1_IRQHandler
+ * I2C2_IRQHandler
+ * SPI_IRQHandler
+ * SSP0_IRQHandler
+ * SSP1_IRQHandler
+ * PLL0_IRQHandler
+ * RTC_IRQHandler
+ * EINT0_IRQHandler
+ * EINT1_IRQHandler
+ * EINT2_IRQHandler
+ * EINT3_IRQHandler
+ * ADC_IRQHandler
+ * BOD_IRQHandler
+ * USB_IRQHandler
+ * CAN_IRQHandler
+ * DMA_IRQHandler
+ * I2S_IRQHandler
+ * ENET_IRQHandler
+ * RIT_IRQHandler
+ * MCPWM_IRQHandler
+ * QEI_IRQHandler
+ * PLL1_IRQHandler
+*/ 
+ 
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ip.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,79 @@
+/*
+* Copyright or © or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_IP_H__
+#define __SIMPLELIB_IP_H__
+
+#include "ip.h"
+
+typedef __packed struct {
+    unsigned char version:4;
+    unsigned char length:4;
+    unsigned char services;
+    uint16_t total_length;
+    uint16_t identification;
+    unsigned int flags:3;
+    unsigned fragment_offset:13;
+    unsigned char ttl;
+    unsigned char protocol;
+    uint16_t header_checksum;
+    unsigned char source[4];
+    unsigned char destination[4];
+} s_ip;
+
+typedef __packed struct {
+    ethernet_packet eth;
+    s_ip ip;
+} ipv4_packet;
+#define asIPV4(x) ((ipv4_packet*)(x))
+
+#define PROTO_ICMP  0x01
+
+typedef __packed struct {
+    ethernet_packet eth;
+    s_ip ip;
+    __packed struct {
+        unsigned char type;
+        unsigned char code;
+        uint16_t checksum;
+        uint16_t identifier;
+        uint16_t sequence_number;
+        unsigned char data[];
+    } icmp;
+} icmp_packet;
+#define asICMP(x) ((icmp_packet*)(x))
+
+#define ICMP_REQUEST 0x08
+#define ICMP_REPLY   0x00
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/leds.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,55 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_LEDS_H__
+#define __SIMPLELIB_LEDS_H__
+
+#include "mbed_globals.h"
+
+/** Bits **/
+#define LEDS_OFF 0
+#define LED1 (1 << 18)
+#define LED2 (1 << 20)
+#define LED3 (1 << 21)
+#define LED4 (1 << 23)
+#define LEDS_MASK (LED1 | LED2 | LED3 | LED4)
+
+/** Macros **/
+#define LEDS_INIT()     LPC_GPIO1->FIODIR |= LEDS_MASK;
+
+#define LEDS_SET(value) do {                                 \
+                            LPC_GPIO1->FIOMASK = ~LEDS_MASK; \
+                            LPC_GPIO1->FIOPIN = (value);     \
+                        } while(0)
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/63bcd7ba4912

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed_globals.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,79 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_MBED_GLOBALS_H__
+#define __SIMPLELIB_MBED_GLOBALS_H__
+
+#include <LPC17xx.h>
+
+/* GLOBALS MACRO */
+#define GET_REGISTER8(reg)  *(volatile uint8_t *)(reg)
+#define GET_REGISTER16(reg) *(volatile uint16_t *)(reg)
+#define GET_REGISTER32(reg) *(volatile uint32_t *)(reg)
+
+#define SET_REGISTER8(reg, val)  *(uint8_t *)(reg)=(val)
+#define SET_REGISTER16(reg, val) *(uint16_t *)(reg)=(val)
+#define SET_REGISTER32(reg, val) *(uint32_t *)(reg)=(val)
+
+// See 34.3.2.5 p740
+#define BIT_BANDING_ADDRESS(reg, bit) (((reg) & 0xF0000000) | (0x02000000) | (((reg) & 0x000FFFFF) << 5) | ((bit) << 2))
+#define GET_BIT_ADDRESS(reg, bit) BIT_BANDING_ADDRESS(((uint32_t)&(reg)), (bit))
+#define GET_BIT_VALUE(reg, bit) GET_REGISTER32(GET_BIT_ADDRESS((reg), (bit)))
+#define SET_BIT_VALUE(reg, bit, value) SET_REGISTER32(GET_BIT_ADDRESS((reg), (bit)), (value))
+
+// Macro tools
+#define TOKENPASTE(x, y) x ## y
+#define TOKENPASTE2(x, y) TOKENPASTE(x, y)
+
+// Extern C
+#ifdef __cplusplus
+    #define EXTERN_C extern "C"
+#else
+    #define EXTERN_C
+#endif
+
+// Byte swap macros
+#define HTONS(x) (((((unsigned short)(x))>>8) & 0xff) | ((((unsigned short)(x)) & 0xff)<<8))
+#define NTOHS(x) (((((unsigned short)(x))>>8) & 0xff) | ((((unsigned short)(x)) & 0xff)<<8))
+#define HTONL(x) ((((x)>>24) & 0xffL) | (((x)>>8) & 0xff00L) | (((x)<<8) & 0xff0000L) | (((x)<<24) & 0xff000000L))
+#define NTOHL(x) ((((x)>>24) & 0xffL) | (((x)>>8) & 0xff00L) | (((x)<<8) & 0xff0000L) | (((x)<<24) & 0xff000000L))
+
+
+/** Constants **/
+// Peripheral Clock Selection register bit values (Table 42, p57)
+#define CCLK4   0U
+#define CCLK    1U
+#define CCLK2   2U
+#define CCLK8   3U
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbedgc.cpp	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,187 @@
+#include "mbed.h"
+#include "colors.h"
+#include "timers.h"
+
+#define fbW 53
+#define fbH 242
+
+DigitalOut vSync(p29);
+DigitalOut hSync(p30);
+
+DigitalOut myled(LED1);
+
+
+void vsync();
+void hsync();
+void setup();
+void loop();
+void blankFB();
+void fill();
+
+unsigned int frame = 0;
+unsigned char framebuffer[fbH][fbW];
+
+int snake_x = 5;
+int snake_y = 50; 
+int snake_direction = 0;
+unsigned char snake_color = 1;
+
+
+TIMER0_INTERRUPT_HANDLER(void)
+{
+    TIMER0_CLEAR_INTERRUPT(MR0_INT);
+    
+    myled = 1;
+
+    vsync();
+    for( int i = 0; i < fbH; i++ )
+    {
+        hsync();
+        for( int j = 0; j < fbW; j++ )
+        {
+            unsigned char bp = framebuffer[ i ][ j ];
+            COLOR_SET(bp);
+        }
+    }
+    COLOR_SET(0);
+    myled = 0;    
+}
+
+int main() {
+    fill();
+    NVIC_SetPriority(TIMER0_IRQn, 0);
+
+    COLOR_INIT();
+    TIMER0_INIT();
+    TIMER0_SETPCLK(CCLK4);
+    TIMER0_SETPRESCALE(96000); // 1ms = 96000 : 1
+    TIMER0_SETMATCH(0, 1);
+    TIMER0_SETMATCHCONTROL(0, MATCH_RESET | MATCH_INTERRUPT); // Reset and Interrupt each 100ms
+    TIMER0_ENABLE_INTERRUPT();
+    TIMER0_START();
+
+    setup();
+    
+    while (1)
+        loop();
+}
+
+void setup() {
+
+}
+
+void drawRectangle(int x, int y, int width, int height, unsigned char color) {
+        
+        if (x < 0 || y < 0)
+            return; 
+            
+        for (int i = 0; i < height; i++) {
+
+               for (int j = 0; j < width; j++) {
+                                                                
+                    framebuffer[ (y + i) % fbH ][ (x + j) % fbW ] = color;
+                    
+               }
+        }
+}
+
+
+void loop() {
+
+    if (snake_y <= 0)
+        snake_y = fbH - 1;
+    
+    if (snake_x <= 0)
+        snake_x = fbW - 1;
+        
+    snake_y %= fbH;
+    snake_x %= fbW;
+    
+    if (frame % (10 + rand() % 20) == 0) {
+        snake_direction++;
+        snake_direction %= 4;
+        
+        snake_color++;
+    }
+    
+    
+    switch (snake_direction) {
+        case 0:
+            snake_y += 4;
+            break;
+        case 2:
+            snake_y -= 4;
+            break;
+        case 1:
+            snake_x += 1;
+            break;
+        case 3:
+            snake_x -= 1;
+            break;
+     }
+
+    drawRectangle(snake_x, snake_y, 1, 4, snake_color);
+    wait_us(10000);
+}
+
+void draw() 
+{
+
+}
+
+
+void hsync() 
+{
+
+    COLOR_SET(0);
+    hSync = 1;
+    wait_us(4.8);
+    hSync = 0;
+    wait_us(4);
+}
+
+void vsync() 
+{
+    vSync = 1;
+    wait_us(1300);//650
+    vSync = 0;
+    frame++;
+    
+    if (frame == 65535)
+        frame = 0;
+}
+
+
+
+void fill() {
+
+    for (int i = 0; i < fbH; i++) {
+
+        for (int j = 0; j < fbW; j++) {
+            
+            if ( (i / 5) % 2 == 0 ) {
+            
+                 if ( (j / 2) % 2 == 0 )
+                    framebuffer[i][j] = 3;
+                else
+                    framebuffer[i][j] = 0;
+            }
+            else {
+                if ( (j / 2) % 2 == 0 )
+                    framebuffer[i][j] = 0;
+                else
+                    framebuffer[i][j] = 28;
+            }
+        }
+    }
+
+}
+
+void blankFB() {
+    for (int i = 0; i < fbH; i++) {
+        for (int j = 0; j < fbW; j++) {
+            framebuffer[i][j] = 0;
+        }
+    }
+
+}
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/serial.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,189 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_SERIAL_H__
+#define __SIMPLELIB_SERIAL_H__
+
+#include "mbed_globals.h"
+#include "interrupts.h"
+
+/**********************************
+ *    Simple Serial Managment     *
+ **********************************
+ * The interrupt handler is :     *
+ * SERIAL_INTERRUPT_HANDLER(void) *
+ * UART0 : Serial over USB        *
+ * UART1 : TX p13, RX p14         *
+ * UART2 : TX p28, RX p27         *
+ * UART3 : TX p9,  RX p10         *
+ **********************************/
+ 
+/** Registers **/
+// Serial port (Choose UARTn (0,1,2,3))
+#define UART_NUMBER UART0
+#define UART_BASE TOKENPASTE2(LPC_,UART_NUMBER)
+
+// Peripheral Clock Selection registers (See 4.7.3 p56)
+#define UART0_PCLK_REG (LPC_SC->PCLKSEL0)
+#define UART1_PCLK_REG (LPC_SC->PCLKSEL0)
+#define UART2_PCLK_REG (LPC_SC->PCLKSEL1)
+#define UART3_PCLK_REG (LPC_SC->PCLKSEL1)
+#define UART_PCLK_REG  TOKENPASTE2(UART_NUMBER,_PCLK_REG)
+
+#define UART0_PCLK_OFFSET   6
+#define UART1_PCLK_OFFSET   8
+#define UART2_PCLK_OFFSET  16
+#define UART3_PCLK_OFFSET  18
+#define UART_PCLK_OFFSET   TOKENPASTE2(UART_NUMBER,_PCLK_OFFSET)
+
+#define UART0_PCLK ((LPC_SC->PCLKSEL0 >>  6) & 0x03)
+#define UART1_PCLK ((LPC_SC->PCLKSEL0 >>  8) & 0x03)
+#define UART2_PCLK ((LPC_SC->PCLKSEL1 >> 16) & 0x03)
+#define UART3_PCLK ((LPC_SC->PCLKSEL1 >> 18) & 0x03)
+#define UART_PCLK TOKENPASTE2(UART_NUMBER,_PCLK)
+
+// Pin Function Select register (See 8.5.1-8 p108)
+#define UART0RX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UART1RX_PINSEL_REG (LPC_PINCON->PINSEL1)
+#define UART2RX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UART3RX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UARTRX_PINSEL_REG  TOKENPASTE2(UART_NUMBER,RX_PINSEL_REG)
+
+#define UART0TX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UART1TX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UART2TX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UART3TX_PINSEL_REG (LPC_PINCON->PINSEL0)
+#define UARTTX_PINSEL_REG  TOKENPASTE2(UART_NUMBER,TX_PINSEL_REG)
+
+#define UART0RX_PINSEL_OFFSET   6
+#define UART1RX_PINSEL_OFFSET   0
+#define UART2RX_PINSEL_OFFSET  22
+#define UART3RX_PINSEL_OFFSET   2
+#define UARTRX_PINSEL_OFFSET    TOKENPASTE2(UART_NUMBER,RX_PINSEL_OFFSET)
+
+#define UART0TX_PINSEL_OFFSET   4
+#define UART1TX_PINSEL_OFFSET  30
+#define UART2TX_PINSEL_OFFSET  20
+#define UART3TX_PINSEL_OFFSET   0
+#define UARTTX_PINSEL_OFFSET    TOKENPASTE2(UART_NUMBER,TX_PINSEL_OFFSET)
+
+#define UART0_PINSEL_VALUE    1U
+#define UART1_PINSEL_VALUE    1U
+#define UART2_PINSEL_VALUE    1U
+#define UART3_PINSEL_VALUE    2U
+#define UART_PINSEL_VALUE     TOKENPASTE2(UART_NUMBER,_PINSEL_VALUE)
+
+/** Interrupt handlers **/
+#define SERIAL_INTERRUPT_HANDLER EXTERN_C void __IRQ TOKENPASTE2(UART_NUMBER,_IRQHandler)
+
+/** Bits **/
+// RBR Interrupt Enable (UnIER, 14.4.4 p302)
+#define RBR_INT_BIT 0
+// Receiver Data Ready (UnLSR, 14.4.8 p306)
+#define RDR_BIT 0
+// Transmitter Holding Register Empty (UnLSR, 14.4.8 p306)
+#define THRE_BIT 5
+// RBR Interrupt Enable (UnIER, 14.4.4 p302)
+#define SERIAL_INT_RX 1
+// THRE Interrupt Enable (UnIER, 14.4.4 p302)
+#define SERIAL_INT_TX 2
+// Divisor Latch Access Bit (UnLCR, 14.4.7 p306)
+#define DLA_BIT 7
+// Power Control for Peripherals (PCONP, 4.8.7.1 p63)
+#define UART0_PCONP_BIT  3
+#define UART1_PCONP_BIT  4
+#define UART2_PCONP_BIT 24
+#define UART3_PCONP_BIT 25
+
+/** Macros **/
+#define SERIAL_PUTCHAR(c)               do {                                                        \
+                                            while (GET_BIT_VALUE(UART_BASE->LSR, THRE_BIT) == 0);   \
+                                            UART_BASE->THR = c;                                     \
+                                        } while(0)
+
+#define SERIAL_DATA_TO_READ()           (GET_BIT_VALUE(UART_BASE->LSR, RDR_BIT) == 1)
+
+#define SERIAL_GETCHAR()                (UART_BASE->RBR)
+
+// Enable interrupt for RX or TX (SERIAL_INT_RX and SERIAL_INT_TX)
+#define SERIAL_ENABLE_INTERRUPT(value)  do {                                                    \
+                                            UART_BASE->IER = value;                             \
+                                            ENABLE_INTERRUPT(TOKENPASTE2(UART_NUMBER,_IRQn));   \
+                                        } while(0)
+
+extern __INLINE void SERIAL_INIT()
+{
+    // Enable UARTn
+    SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(UART_NUMBER,_PCONP_BIT) , 1);
+    // Enable FIFO and reset RX/TX FIFO (See 14.4.6 p305)
+    UART_BASE->FCR = 0x07;
+    // 8-bits, No Parity, 1 stop bit (See 14.4.7 p306)
+    UART_BASE->LCR = 0x03;
+    // Set CCLK as Peripheral Clock for UART (96MHz with mbed library)
+    UART_PCLK_REG = (UART_PCLK_REG & (~(3UL << UART_PCLK_OFFSET))) | (1U << UART_PCLK_OFFSET);
+    // Define Pin's functions as UART
+    UARTRX_PINSEL_REG = (UARTRX_PINSEL_REG & (~(3U << UARTRX_PINSEL_OFFSET))) | (UART_PINSEL_VALUE << UARTRX_PINSEL_OFFSET);
+    UARTTX_PINSEL_REG = (UARTTX_PINSEL_REG & (~(3U << UARTTX_PINSEL_OFFSET))) | (UART_PINSEL_VALUE << UARTTX_PINSEL_OFFSET);
+}
+
+// See 14.4.5 p303
+extern __INLINE int SERIAL_CHECK_INTERRUPT(void) {
+    uint32_t serialStatus = UART_BASE->IIR;
+
+    if (serialStatus & 1) // IntStatus, 1 = No Interrupt is pending.
+        return 0;
+
+    serialStatus = (serialStatus >> 1) & 0x3; // IntId, 2 = More than threshold data to read, 6 = Some caracters to read
+    if (serialStatus != 2 && serialStatus != 6)
+        return 0;
+
+    return 1;
+}
+
+extern __INLINE void SERIAL_SETBAUD(unsigned int baud) {
+    // Peripheral Clock Selection register bit values (See Table 42, p57)
+    uint16_t divisorValue = (SystemCoreClock / 16 / baud);
+    #if 0
+        // Peripheral Clock for UART is set to CCLK in SERIAL_INIT. Divisor is then 1.
+        // Else, use code below
+        static int divisors[4] = { 4, 1, 2, 8 };
+        uint16_t divisorValue = ((SystemCoreClock / 16 / baud) / divisors[UART_PCLK]);
+    #endif
+    
+    UART_BASE->LCR |= (1 << DLA_BIT);
+    UART_BASE->DLM = (uint8_t) (divisorValue >> 8);
+    UART_BASE->DLL = (uint8_t)  divisorValue;
+    UART_BASE->LCR &= ~(1 << DLA_BIT);
+}
+
+#endif
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/timers.h	Sat Jul 09 15:47:27 2011 +0000
@@ -0,0 +1,165 @@
+/*
+* Copyright or � or Copr. 2010, Thomas SOETE
+* 
+* Author e-mail: thomas@soete.org
+* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
+* 
+* This software is governed by the CeCILL license under French law and
+* abiding by the rules of distribution of free software.  You can  use, 
+* modify and/ or redistribute the software under the terms of the CeCILL
+* license as circulated by CEA, CNRS and INRIA at the following URL
+* "http://www.cecill.info". 
+* 
+* As a counterpart to the access to the source code and  rights to copy,
+* modify and redistribute granted by the license, users are provided only
+* with a limited warranty  and the software's author,  the holder of the
+* economic rights,  and the successive licensors  have only  limited
+* liability. 
+* 
+* In this respect, the user's attention is drawn to the risks associated
+* with loading,  using,  modifying and/or developing or reproducing the
+* software by the user in light of its specific status of free software,
+* that may mean  that it is complicated to manipulate,  and  that  also
+* therefore means  that it is reserved for developers  and  experienced
+* professionals having in-depth computer knowledge. Users are therefore
+* encouraged to load and test the software's suitability as regards their
+* requirements in conditions enabling the security of their systems and/or 
+* data to be ensured and,  more generally, to use and operate it in the 
+* same conditions as regards security. 
+* 
+* The fact that you are presently reading this means that you have had
+* knowledge of the CeCILL license and that you accept its terms.
+*/
+
+#ifndef __SIMPLELIB_TIMERS_H__
+#define __SIMPLELIB_TIMERS_H__
+
+#include "mbed_globals.h"
+#include "interrupts.h"
+
+/**********************************
+ *    Simple Timers Managment     *
+ **********************************
+ * The interrupt handler is :     *
+ * TIMERn_INTERRUPT_HANDLER(void) *
+ **********************************/
+
+/** Registers **/
+#define TIMER0_BASE (LPC_TIM0)
+#define TIMER1_BASE (LPC_TIM1)
+#define TIMER2_BASE (LPC_TIM2)
+#define TIMER3_BASE (LPC_TIM3)
+#define TIMER_BASE(timer) TOKENPASTE2(timer,_BASE)
+
+// Peripheral Clock Selection registers (See 4.7.3 p56)
+#define TIMER0_PCLK_REG (LPC_SC->PCLKSEL0)
+#define TIMER1_PCLK_REG (LPC_SC->PCLKSEL0)
+#define TIMER2_PCLK_REG (LPC_SC->PCLKSEL1)
+#define TIMER3_PCLK_REG (LPC_SC->PCLKSEL1)
+#define TIMER_PCLK_REG(timer)  TOKENPASTE2(timer,_PCLK_REG)
+
+#define TIMER0_PCLK_OFFSET   2
+#define TIMER1_PCLK_OFFSET   4
+#define TIMER2_PCLK_OFFSET  12
+#define TIMER3_PCLK_OFFSET  14
+#define TIMER_PCLK_OFFSET(timer)   TOKENPASTE2(timer,_PCLK_OFFSET)
+
+/** Interrupt handlers **/
+#define TIMER0_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER0)
+#define TIMER1_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER1)
+#define TIMER2_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER2)
+#define TIMER3_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER3)
+#define TIMER_INTERRUPT_HANDLER(timer) EXTERN_C void __IRQ TOKENPASTE2(timer,_IRQHandler)
+
+/** Bits **/
+// Power Control for Peripherals (PCONP, 4.8.7.1 p63)
+#define TIMER0_PCONP_BIT  1
+#define TIMER1_PCONP_BIT  2
+#define TIMER2_PCONP_BIT 22
+#define TIMER3_PCONP_BIT 23
+
+// Match Control Register (TnMCR, 21.6.8 p496)
+#define MATCH_INTERRUPT   1
+#define MATCH_RESET       2
+#define MATCH_STOP        4
+#define MR0_OFFSET        0
+#define MR1_OFFSET        3
+#define MR2_OFFSET        6
+#define MR3_OFFSET        9
+
+// Interrupt Register (TnIR, 21.6.1, p493)
+#define MR0_INT    (1U << 0)
+#define MR1_INT    (1U << 1)
+#define MR2_INT    (1U << 2)
+#define MR3_INT    (1U << 3)
+#define CR0_INT    (1U << 4)
+#define CR1_INT    (1U << 5)
+
+/** Macros **/
+// Enable TIMERn
+#define TIMER0_INIT() TIMER_INIT(TIMER0)
+#define TIMER1_INIT() TIMER_INIT(TIMER1)
+#define TIMER2_INIT() TIMER_INIT(TIMER2)
+#define TIMER3_INIT() TIMER_INIT(TIMER3)
+#define TIMER_INIT(timer)   do {                                                                                                   \
+                                SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(timer,_PCONP_BIT) , 1); /* Enable Timer                */ \
+                                TIMER_BASE(timer)->TCR = 0x2;                                    /* Reset Timer, Table 427 p493 */ \
+                            } while(0)
+
+// Set Peripheral Clock
+#define TIMER0_SETPCLK(clk) TIMER_SETPCLK(TIMER0, clk)
+#define TIMER1_SETPCLK(clk) TIMER_SETPCLK(TIMER1, clk)
+#define TIMER2_SETPCLK(clk) TIMER_SETPCLK(TIMER2, clk)
+#define TIMER3_SETPCLK(clk) TIMER_SETPCLK(TIMER3, clk)
+#define TIMER_SETPCLK(timer, clk)  TIMER_PCLK_REG(timer) = ((TIMER_PCLK_REG(timer) & (~(3U << TIMER_PCLK_OFFSET(timer)))) | (clk << TIMER_PCLK_OFFSET(timer)))
+
+// Set Prescale Register
+#define TIMER0_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER0, value)
+#define TIMER1_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER1, value)
+#define TIMER2_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER2, value)
+#define TIMER3_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER3, value)
+#define TIMER_SETPRESCALE(timer, value)  TIMER_BASE(timer)->PR = (value)
+
+// Set Match Register (MR0-3, 21.6.7 p496)
+#define TIMER0_SETMATCH(id, value) TIMER_SETMATCH(TIMER0, id, value)
+#define TIMER1_SETMATCH(id, value) TIMER_SETMATCH(TIMER1, id, value)
+#define TIMER2_SETMATCH(id, value) TIMER_SETMATCH(TIMER2, id, value)
+#define TIMER3_SETMATCH(id, value) TIMER_SETMATCH(TIMER3, id, value)
+#define TIMER_SETMATCH(timer, id, value)  TIMER_BASE(timer)->TOKENPASTE2(MR,id) = (value)
+
+// Set Match Control Register (TnMCR, 21.6.8 p496)
+#define TIMER0_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER0, id, value)
+#define TIMER1_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER1, id, value)
+#define TIMER2_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER2, id, value)
+#define TIMER3_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER3, id, value)
+#define TIMER_SETMATCHCONTROL(timer, id, value)  TIMER_BASE(timer)->MCR = (value) << (MR ## id ## _OFFSET)
+
+// Enable interrupt for TIMERn
+#define TIMER0_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER0)
+#define TIMER1_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER1)
+#define TIMER2_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER2)
+#define TIMER3_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER3)
+#define TIMER_ENABLE_INTERRUPT(timer)  ENABLE_INTERRUPT(TOKENPASTE2(timer,_IRQn))
+
+// Interrut Register (TnIR, 21.6.1, p493)
+#define TIMER0_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER0, value)
+#define TIMER1_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER1, value)
+#define TIMER2_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER2, value)
+#define TIMER3_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER3, value)
+#define TIMER_CLEAR_INTERRUPT(timer, value)  TIMER_BASE(timer)->IR = (value)
+
+// Start Timer
+#define TIMER0_START() TIMER_START(TIMER0)
+#define TIMER1_START() TIMER_START(TIMER1)
+#define TIMER2_START() TIMER_START(TIMER2)
+#define TIMER3_START() TIMER_START(TIMER3)
+#define TIMER_START(timer)  TIMER_BASE(timer)->TCR = 0x1 /* Counter Enable, Table 427 p493*/
+
+// Get Timer Value
+#define TIMER0_VALUE() TIMER_VALUE(TIMER0)
+#define TIMER1_VALUE() TIMER_VALUE(TIMER1)
+#define TIMER2_VALUE() TIMER_VALUE(TIMER2)
+#define TIMER3_VALUE() TIMER_VALUE(TIMER3)
+#define TIMER_VALUE(timer)  (TIMER_BASE(timer)->TC)
+
+#endif
\ No newline at end of file