J.P. Armstrong / Mbed 2 deprecated mbgcSnake_01

The first video game for the mbed video game console. The code utilizes the SimpleLib package developed by thomas@soete.org. For more information about the project and if you'd like to download the schematics and PCB design visit http://www.mbedgc.com/

Dependencies:   mbed

interrupts.h@0:31cd577d85a4, 2011-07-09 (annotated)

Committer:
jp
Date:
Sat Jul 09 15:47:27 2011 +0000
Revision:
0:31cd577d85a4
Initial release of Snake for the mbed Game Console.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jp 0:31cd577d85a4 1 /*
jp 0:31cd577d85a4 2 * Copyright or � or Copr. 2010, Thomas SOETE
jp 0:31cd577d85a4 3 *
jp 0:31cd577d85a4 4 * Author e-mail: thomas@soete.org
jp 0:31cd577d85a4 5 * Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/
jp 0:31cd577d85a4 6 *
jp 0:31cd577d85a4 7 * This software is governed by the CeCILL license under French law and
jp 0:31cd577d85a4 8 * abiding by the rules of distribution of free software. You can use,
jp 0:31cd577d85a4 9 * modify and/ or redistribute the software under the terms of the CeCILL
jp 0:31cd577d85a4 10 * license as circulated by CEA, CNRS and INRIA at the following URL
jp 0:31cd577d85a4 11 * "http://www.cecill.info".
jp 0:31cd577d85a4 12 *
jp 0:31cd577d85a4 13 * As a counterpart to the access to the source code and rights to copy,
jp 0:31cd577d85a4 14 * modify and redistribute granted by the license, users are provided only
jp 0:31cd577d85a4 15 * with a limited warranty and the software's author, the holder of the
jp 0:31cd577d85a4 16 * economic rights, and the successive licensors have only limited
jp 0:31cd577d85a4 17 * liability.
jp 0:31cd577d85a4 18 *
jp 0:31cd577d85a4 19 * In this respect, the user's attention is drawn to the risks associated
jp 0:31cd577d85a4 20 * with loading, using, modifying and/or developing or reproducing the
jp 0:31cd577d85a4 21 * software by the user in light of its specific status of free software,
jp 0:31cd577d85a4 22 * that may mean that it is complicated to manipulate, and that also
jp 0:31cd577d85a4 23 * therefore means that it is reserved for developers and experienced
jp 0:31cd577d85a4 24 * professionals having in-depth computer knowledge. Users are therefore
jp 0:31cd577d85a4 25 * encouraged to load and test the software's suitability as regards their
jp 0:31cd577d85a4 26 * requirements in conditions enabling the security of their systems and/or
jp 0:31cd577d85a4 27 * data to be ensured and, more generally, to use and operate it in the
jp 0:31cd577d85a4 28 * same conditions as regards security.
jp 0:31cd577d85a4 29 *
jp 0:31cd577d85a4 30 * The fact that you are presently reading this means that you have had
jp 0:31cd577d85a4 31 * knowledge of the CeCILL license and that you accept its terms.
jp 0:31cd577d85a4 32 */
jp 0:31cd577d85a4 33
jp 0:31cd577d85a4 34 #ifndef __SIMPLELIB_INTERRUPTS_H__
jp 0:31cd577d85a4 35 #define __SIMPLELIB_INTERRUPTS_H__
jp 0:31cd577d85a4 36
jp 0:31cd577d85a4 37 #include "mbed_globals.h"
jp 0:31cd577d85a4 38
jp 0:31cd577d85a4 39 /** Interrupt Managment **/
jp 0:31cd577d85a4 40 #define ENABLE_INTERRUPT(intr) NVIC_EnableIRQ(intr)
jp 0:31cd577d85a4 41 #define DISABLE_INTERRUPT(intr) NVIC_DisableIRQ(intr)
jp 0:31cd577d85a4 42
jp 0:31cd577d85a4 43 #if defined ( __CC_ARM )
jp 0:31cd577d85a4 44 #define __IRQ __irq
jp 0:31cd577d85a4 45 #elif defined ( __GNUC__ )
jp 0:31cd577d85a4 46 #define __IRQ __attribute__((interrupt("IRQ")))
jp 0:31cd577d85a4 47 #endif
jp 0:31cd577d85a4 48
jp 0:31cd577d85a4 49 /* Interrupts names
jp 0:31cd577d85a4 50 * WDT_IRQn Watchdog Timer Interrupt
jp 0:31cd577d85a4 51 * TIMER0_IRQn Timer0 Interrupt
jp 0:31cd577d85a4 52 * TIMER1_IRQn Timer1 Interrupt
jp 0:31cd577d85a4 53 * TIMER2_IRQn Timer2 Interrupt
jp 0:31cd577d85a4 54 * TIMER3_IRQn Timer3 Interrupt
jp 0:31cd577d85a4 55 * UART0_IRQn UART0 Interrupt
jp 0:31cd577d85a4 56 * UART1_IRQn UART1 Interrupt
jp 0:31cd577d85a4 57 * UART2_IRQn UART2 Interrupt
jp 0:31cd577d85a4 58 * UART3_IRQn UART3 Interrupt
jp 0:31cd577d85a4 59 * PWM1_IRQn PWM1 Interrupt
jp 0:31cd577d85a4 60 * I2C0_IRQn I2C0 Interrupt
jp 0:31cd577d85a4 61 * I2C1_IRQn I2C1 Interrupt
jp 0:31cd577d85a4 62 * I2C2_IRQn I2C2 Interrupt
jp 0:31cd577d85a4 63 * SPI_IRQn SPI Interrupt
jp 0:31cd577d85a4 64 * SSP0_IRQn SSP0 Interrupt
jp 0:31cd577d85a4 65 * SSP1_IRQn SSP1 Interrupt
jp 0:31cd577d85a4 66 * PLL0_IRQn PLL0 Lock (Main PLL) Interrupt
jp 0:31cd577d85a4 67 * RTC_IRQn Real Time Clock Interrupt
jp 0:31cd577d85a4 68 * EINT0_IRQn External Interrupt 0 Interrupt
jp 0:31cd577d85a4 69 * EINT1_IRQn External Interrupt 1 Interrupt
jp 0:31cd577d85a4 70 * EINT2_IRQn External Interrupt 2 Interrupt
jp 0:31cd577d85a4 71 * EINT3_IRQn External Interrupt 3 Interrupt
jp 0:31cd577d85a4 72 * ADC_IRQn A/D Converter Interrupt
jp 0:31cd577d85a4 73 * BOD_IRQn Brown-Out Detect Interrupt
jp 0:31cd577d85a4 74 * USB_IRQn USB Interrupt
jp 0:31cd577d85a4 75 * CAN_IRQn CAN Interrupt
jp 0:31cd577d85a4 76 * DMA_IRQn General Purpose DMA Interrupt
jp 0:31cd577d85a4 77 * I2S_IRQn I2S Interrupt
jp 0:31cd577d85a4 78 * ENET_IRQn Ethernet Interrupt
jp 0:31cd577d85a4 79 * RIT_IRQn Repetitive Interrupt Timer Interrupt
jp 0:31cd577d85a4 80 * MCPWM_IRQn Motor Control PWM Interrupt
jp 0:31cd577d85a4 81 * QEI_IRQn Quadrature Encoder Interface Interrupt
jp 0:31cd577d85a4 82 * PLL1_IRQn PLL1 Lock (USB PLL) Interrupt
jp 0:31cd577d85a4 83 */
jp 0:31cd577d85a4 84
jp 0:31cd577d85a4 85 /* Default interrupt handlers
jp 0:31cd577d85a4 86 * WDT_IRQHandler
jp 0:31cd577d85a4 87 * TIMER0_IRQHandler
jp 0:31cd577d85a4 88 * TIMER1_IRQHandler
jp 0:31cd577d85a4 89 * TIMER2_IRQHandler
jp 0:31cd577d85a4 90 * TIMER3_IRQHandler
jp 0:31cd577d85a4 91 * UART0_IRQHandler
jp 0:31cd577d85a4 92 * UART1_IRQHandler
jp 0:31cd577d85a4 93 * UART2_IRQHandler
jp 0:31cd577d85a4 94 * UART3_IRQHandler
jp 0:31cd577d85a4 95 * PWM1_IRQHandler
jp 0:31cd577d85a4 96 * I2C0_IRQHandler
jp 0:31cd577d85a4 97 * I2C1_IRQHandler
jp 0:31cd577d85a4 98 * I2C2_IRQHandler
jp 0:31cd577d85a4 99 * SPI_IRQHandler
jp 0:31cd577d85a4 100 * SSP0_IRQHandler
jp 0:31cd577d85a4 101 * SSP1_IRQHandler
jp 0:31cd577d85a4 102 * PLL0_IRQHandler
jp 0:31cd577d85a4 103 * RTC_IRQHandler
jp 0:31cd577d85a4 104 * EINT0_IRQHandler
jp 0:31cd577d85a4 105 * EINT1_IRQHandler
jp 0:31cd577d85a4 106 * EINT2_IRQHandler
jp 0:31cd577d85a4 107 * EINT3_IRQHandler
jp 0:31cd577d85a4 108 * ADC_IRQHandler
jp 0:31cd577d85a4 109 * BOD_IRQHandler
jp 0:31cd577d85a4 110 * USB_IRQHandler
jp 0:31cd577d85a4 111 * CAN_IRQHandler
jp 0:31cd577d85a4 112 * DMA_IRQHandler
jp 0:31cd577d85a4 113 * I2S_IRQHandler
jp 0:31cd577d85a4 114 * ENET_IRQHandler
jp 0:31cd577d85a4 115 * RIT_IRQHandler
jp 0:31cd577d85a4 116 * MCPWM_IRQHandler
jp 0:31cd577d85a4 117 * QEI_IRQHandler
jp 0:31cd577d85a4 118 * PLL1_IRQHandler
jp 0:31cd577d85a4 119 */
jp 0:31cd577d85a4 120
jp 0:31cd577d85a4 121 #endif