J.P. Armstrong / SimpleLib

timers.h@3:d0fc1ce5e516, 2011-02-13 (annotated)

Committer:
jp
Date:
Sun Feb 13 02:18:50 2011 +0000
Revision:
3:d0fc1ce5e516
Parent:
2:98b11b7dd7b2 

        

        
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/*





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* Copyright or � or Copr. 2010, Thomas SOETE





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* 





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* Author e-mail: thomas@soete.org





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* Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/





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* 





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* This software is governed by the CeCILL license under French law and





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* abiding by the rules of distribution of free software.  You can  use, 





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* modify and/ or redistribute the software under the terms of the CeCILL





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* license as circulated by CEA, CNRS and INRIA at the following URL





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* "http://www.cecill.info". 





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* 





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* As a counterpart to the access to the source code and  rights to copy,





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* modify and redistribute granted by the license, users are provided only





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* with a limited warranty  and the software's author,  the holder of the





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* economic rights,  and the successive licensors  have only  limited





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* liability. 





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* 





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* In this respect, the user's attention is drawn to the risks associated





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* with loading,  using,  modifying and/or developing or reproducing the





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* software by the user in light of its specific status of free software,





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* that may mean  that it is complicated to manipulate,  and  that  also





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* therefore means  that it is reserved for developers  and  experienced





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* professionals having in-depth computer knowledge. Users are therefore





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* encouraged to load and test the software's suitability as regards their





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* requirements in conditions enabling the security of their systems and/or 





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* data to be ensured and,  more generally, to use and operate it in the 





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* same conditions as regards security. 





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* 





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* The fact that you are presently reading this means that you have had





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* knowledge of the CeCILL license and that you accept its terms.





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*/





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#ifndef __SIMPLELIB_TIMERS_H__





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#define __SIMPLELIB_TIMERS_H__





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#include "mbed_globals.h"





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#include "interrupts.h"





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/**********************************





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 *    Simple Timers Managment     *





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 **********************************





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 * The interrupt handler is :     *





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 * TIMERn_INTERRUPT_HANDLER(void) *





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 **********************************/





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/** Registers **/





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#define TIMER0_BASE (LPC_TIM0)





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#define TIMER1_BASE (LPC_TIM1)





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#define TIMER2_BASE (LPC_TIM2)





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#define TIMER3_BASE (LPC_TIM3)





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#define TIMER_BASE(timer) TOKENPASTE2(timer,_BASE)





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// Peripheral Clock Selection registers (See 4.7.3 p56)





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#define TIMER0_PCLK_REG (LPC_SC->PCLKSEL0)





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#define TIMER1_PCLK_REG (LPC_SC->PCLKSEL0)





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#define TIMER2_PCLK_REG (LPC_SC->PCLKSEL1)





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#define TIMER3_PCLK_REG (LPC_SC->PCLKSEL1)





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#define TIMER_PCLK_REG(timer)  TOKENPASTE2(timer,_PCLK_REG)





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#define TIMER0_PCLK_OFFSET   2





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#define TIMER1_PCLK_OFFSET   4





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#define TIMER2_PCLK_OFFSET  12





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#define TIMER3_PCLK_OFFSET  14





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#define TIMER_PCLK_OFFSET(timer)   TOKENPASTE2(timer,_PCLK_OFFSET)





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/** Interrupt handlers **/





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#define TIMER0_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER0)





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#define TIMER1_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER1)





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#define TIMER2_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER2)





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#define TIMER3_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER3)





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#define TIMER_INTERRUPT_HANDLER(timer) EXTERN_C void __IRQ TOKENPASTE2(timer,_IRQHandler)





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/** Bits **/





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// Power Control for Peripherals (PCONP, 4.8.7.1 p63)





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#define TIMER0_PCONP_BIT  1





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#define TIMER1_PCONP_BIT  2





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#define TIMER2_PCONP_BIT 22





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#define TIMER3_PCONP_BIT 23





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// Match Control Register (TnMCR, 21.6.8 p496)





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#define MATCH_INTERRUPT   1





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#define MATCH_RESET       2





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#define MATCH_STOP        4





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#define MR0_OFFSET        0





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#define MR1_OFFSET        3





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#define MR2_OFFSET        6





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#define MR3_OFFSET        9





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// Interrupt Register (TnIR, 21.6.1, p493)





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#define MR0_INT    (1U << 0)





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#define MR1_INT    (1U << 1)





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#define MR2_INT    (1U << 2)





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#define MR3_INT    (1U << 3)





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#define CR0_INT    (1U << 4)





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#define CR1_INT    (1U << 5)





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/** Macros **/





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// Enable TIMERn





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#define TIMER0_INIT() TIMER_INIT(TIMER0)





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#define TIMER1_INIT() TIMER_INIT(TIMER1)





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#define TIMER2_INIT() TIMER_INIT(TIMER2)





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#define TIMER3_INIT() TIMER_INIT(TIMER3)





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#define TIMER_INIT(timer)   do {                                                                                                   \





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                                SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(timer,_PCONP_BIT) , 1); /* Enable Timer                */ \





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                                TIMER_BASE(timer)->TCR = 0x2;                                    /* Reset Timer, Table 427 p493 */ \





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                            } while(0)





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// Set Peripheral Clock





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#define TIMER0_SETPCLK(clk) TIMER_SETPCLK(TIMER0, clk)





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#define TIMER1_SETPCLK(clk) TIMER_SETPCLK(TIMER1, clk)





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#define TIMER2_SETPCLK(clk) TIMER_SETPCLK(TIMER2, clk)





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#define TIMER3_SETPCLK(clk) TIMER_SETPCLK(TIMER3, clk)





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#define TIMER_SETPCLK(timer, clk)  TIMER_PCLK_REG(timer) = ((TIMER_PCLK_REG(timer) & (~(3U << TIMER_PCLK_OFFSET(timer)))) | (clk << TIMER_PCLK_OFFSET(timer)))





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// Set Prescale Register





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#define TIMER0_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER0, value)





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#define TIMER1_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER1, value)





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#define TIMER2_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER2, value)





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#define TIMER3_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER3, value)





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#define TIMER_SETPRESCALE(timer, value)  TIMER_BASE(timer)->PR = (value)





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// Set Match Register (MR0-3, 21.6.7 p496)





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#define TIMER0_SETMATCH(id, value) TIMER_SETMATCH(TIMER0, id, value)





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#define TIMER1_SETMATCH(id, value) TIMER_SETMATCH(TIMER1, id, value)





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#define TIMER2_SETMATCH(id, value) TIMER_SETMATCH(TIMER2, id, value)





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#define TIMER3_SETMATCH(id, value) TIMER_SETMATCH(TIMER3, id, value)





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#define TIMER_SETMATCH(timer, id, value)  TIMER_BASE(timer)->TOKENPASTE2(MR,id) = (value)





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// Set Match Control Register (TnMCR, 21.6.8 p496)





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#define TIMER0_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER0, id, value)





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#define TIMER1_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER1, id, value)





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#define TIMER2_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER2, id, value)





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#define TIMER3_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER3, id, value)





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#define TIMER_SETMATCHCONTROL(timer, id, value)  TIMER_BASE(timer)->MCR = (value) << (MR ## id ## _OFFSET)





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// Enable interrupt for TIMERn





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#define TIMER0_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER0)





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#define TIMER1_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER1)





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#define TIMER2_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER2)





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#define TIMER3_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER3)





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#define TIMER_ENABLE_INTERRUPT(timer)  ENABLE_INTERRUPT(TOKENPASTE2(timer,_IRQn))





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// Interrut Register (TnIR, 21.6.1, p493)





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#define TIMER0_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER0, value)





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#define TIMER1_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER1, value)





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#define TIMER2_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER2, value)





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#define TIMER3_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER3, value)





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#define TIMER_CLEAR_INTERRUPT(timer, value)  TIMER_BASE(timer)->IR = (value)





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// Start Timer





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#define TIMER0_START() TIMER_START(TIMER0)





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#define TIMER1_START() TIMER_START(TIMER1)





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#define TIMER2_START() TIMER_START(TIMER2)





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#define TIMER3_START() TIMER_START(TIMER3)





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#define TIMER_START(timer)  TIMER_BASE(timer)->TCR = 0x1 /* Counter Enable, Table 427 p493*/





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// Get Timer Value





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#define TIMER0_VALUE() TIMER_VALUE(TIMER0)





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#define TIMER1_VALUE() TIMER_VALUE(TIMER1)





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#define TIMER2_VALUE() TIMER_VALUE(TIMER2)





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#define TIMER3_VALUE() TIMER_VALUE(TIMER3)





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#define TIMER_VALUE(timer)  (TIMER_BASE(timer)->TC)





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#endif