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KL25Z/core_cmInstr.h@60:3d0ef94e36ec, 2013-02-19 (annotated)

Committer:
emilmont
Date:
Tue Feb 19 10:00:15 2013 +0000
Revision:
60:3d0ef94e36ec
Add Freescale FRDM-KL25Z

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emilmont 60:3d0ef94e36ec 1 /**************************************************************************//**
emilmont 60:3d0ef94e36ec 2 * @file core_cmInstr.h
emilmont 60:3d0ef94e36ec 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 60:3d0ef94e36ec 4 * @version V3.03
emilmont 60:3d0ef94e36ec 5 * @date 29. August 2012
emilmont 60:3d0ef94e36ec 6 *
emilmont 60:3d0ef94e36ec 7 * @note
emilmont 60:3d0ef94e36ec 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 60:3d0ef94e36ec 9 *
emilmont 60:3d0ef94e36ec 10 * @par
emilmont 60:3d0ef94e36ec 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 60:3d0ef94e36ec 12 * processor based microcontrollers. This file can be freely distributed
emilmont 60:3d0ef94e36ec 13 * within development tools that are supporting such ARM based processors.
emilmont 60:3d0ef94e36ec 14 *
emilmont 60:3d0ef94e36ec 15 * @par
emilmont 60:3d0ef94e36ec 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 60:3d0ef94e36ec 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 60:3d0ef94e36ec 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 60:3d0ef94e36ec 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 60:3d0ef94e36ec 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 60:3d0ef94e36ec 21 *
emilmont 60:3d0ef94e36ec 22 ******************************************************************************/
emilmont 60:3d0ef94e36ec 23
emilmont 60:3d0ef94e36ec 24 #ifndef __CORE_CMINSTR_H
emilmont 60:3d0ef94e36ec 25 #define __CORE_CMINSTR_H
emilmont 60:3d0ef94e36ec 26
emilmont 60:3d0ef94e36ec 27
emilmont 60:3d0ef94e36ec 28 /* ########################## Core Instruction Access ######################### */
emilmont 60:3d0ef94e36ec 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 60:3d0ef94e36ec 30 Access to dedicated instructions
emilmont 60:3d0ef94e36ec 31 @{
emilmont 60:3d0ef94e36ec 32 */
emilmont 60:3d0ef94e36ec 33
emilmont 60:3d0ef94e36ec 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 60:3d0ef94e36ec 35 /* ARM armcc specific functions */
emilmont 60:3d0ef94e36ec 36
emilmont 60:3d0ef94e36ec 37 #if (__ARMCC_VERSION < 400677)
emilmont 60:3d0ef94e36ec 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 60:3d0ef94e36ec 39 #endif
emilmont 60:3d0ef94e36ec 40
emilmont 60:3d0ef94e36ec 41
emilmont 60:3d0ef94e36ec 42 /** \brief No Operation
emilmont 60:3d0ef94e36ec 43
emilmont 60:3d0ef94e36ec 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 60:3d0ef94e36ec 45 */
emilmont 60:3d0ef94e36ec 46 #define __NOP __nop
emilmont 60:3d0ef94e36ec 47
emilmont 60:3d0ef94e36ec 48
emilmont 60:3d0ef94e36ec 49 /** \brief Wait For Interrupt
emilmont 60:3d0ef94e36ec 50
emilmont 60:3d0ef94e36ec 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 60:3d0ef94e36ec 52 until one of a number of events occurs.
emilmont 60:3d0ef94e36ec 53 */
emilmont 60:3d0ef94e36ec 54 #define __WFI __wfi
emilmont 60:3d0ef94e36ec 55
emilmont 60:3d0ef94e36ec 56
emilmont 60:3d0ef94e36ec 57 /** \brief Wait For Event
emilmont 60:3d0ef94e36ec 58
emilmont 60:3d0ef94e36ec 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 60:3d0ef94e36ec 60 a low-power state until one of a number of events occurs.
emilmont 60:3d0ef94e36ec 61 */
emilmont 60:3d0ef94e36ec 62 #define __WFE __wfe
emilmont 60:3d0ef94e36ec 63
emilmont 60:3d0ef94e36ec 64
emilmont 60:3d0ef94e36ec 65 /** \brief Send Event
emilmont 60:3d0ef94e36ec 66
emilmont 60:3d0ef94e36ec 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 60:3d0ef94e36ec 68 */
emilmont 60:3d0ef94e36ec 69 #define __SEV __sev
emilmont 60:3d0ef94e36ec 70
emilmont 60:3d0ef94e36ec 71
emilmont 60:3d0ef94e36ec 72 /** \brief Instruction Synchronization Barrier
emilmont 60:3d0ef94e36ec 73
emilmont 60:3d0ef94e36ec 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 60:3d0ef94e36ec 75 so that all instructions following the ISB are fetched from cache or
emilmont 60:3d0ef94e36ec 76 memory, after the instruction has been completed.
emilmont 60:3d0ef94e36ec 77 */
emilmont 60:3d0ef94e36ec 78 #define __ISB() __isb(0xF)
emilmont 60:3d0ef94e36ec 79
emilmont 60:3d0ef94e36ec 80
emilmont 60:3d0ef94e36ec 81 /** \brief Data Synchronization Barrier
emilmont 60:3d0ef94e36ec 82
emilmont 60:3d0ef94e36ec 83 This function acts as a special kind of Data Memory Barrier.
emilmont 60:3d0ef94e36ec 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 60:3d0ef94e36ec 85 */
emilmont 60:3d0ef94e36ec 86 #define __DSB() __dsb(0xF)
emilmont 60:3d0ef94e36ec 87
emilmont 60:3d0ef94e36ec 88
emilmont 60:3d0ef94e36ec 89 /** \brief Data Memory Barrier
emilmont 60:3d0ef94e36ec 90
emilmont 60:3d0ef94e36ec 91 This function ensures the apparent order of the explicit memory operations before
emilmont 60:3d0ef94e36ec 92 and after the instruction, without ensuring their completion.
emilmont 60:3d0ef94e36ec 93 */
emilmont 60:3d0ef94e36ec 94 #define __DMB() __dmb(0xF)
emilmont 60:3d0ef94e36ec 95
emilmont 60:3d0ef94e36ec 96
emilmont 60:3d0ef94e36ec 97 /** \brief Reverse byte order (32 bit)
emilmont 60:3d0ef94e36ec 98
emilmont 60:3d0ef94e36ec 99 This function reverses the byte order in integer value.
emilmont 60:3d0ef94e36ec 100
emilmont 60:3d0ef94e36ec 101 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 102 \return Reversed value
emilmont 60:3d0ef94e36ec 103 */
emilmont 60:3d0ef94e36ec 104 #define __REV __rev
emilmont 60:3d0ef94e36ec 105
emilmont 60:3d0ef94e36ec 106
emilmont 60:3d0ef94e36ec 107 /** \brief Reverse byte order (16 bit)
emilmont 60:3d0ef94e36ec 108
emilmont 60:3d0ef94e36ec 109 This function reverses the byte order in two unsigned short values.
emilmont 60:3d0ef94e36ec 110
emilmont 60:3d0ef94e36ec 111 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 112 \return Reversed value
emilmont 60:3d0ef94e36ec 113 */
emilmont 60:3d0ef94e36ec 114 #ifndef __NO_EMBEDDED_ASM
emilmont 60:3d0ef94e36ec 115 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 60:3d0ef94e36ec 116 {
emilmont 60:3d0ef94e36ec 117 rev16 r0, r0
emilmont 60:3d0ef94e36ec 118 bx lr
emilmont 60:3d0ef94e36ec 119 }
emilmont 60:3d0ef94e36ec 120 #endif
emilmont 60:3d0ef94e36ec 121
emilmont 60:3d0ef94e36ec 122 /** \brief Reverse byte order in signed short value
emilmont 60:3d0ef94e36ec 123
emilmont 60:3d0ef94e36ec 124 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 60:3d0ef94e36ec 125
emilmont 60:3d0ef94e36ec 126 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 127 \return Reversed value
emilmont 60:3d0ef94e36ec 128 */
emilmont 60:3d0ef94e36ec 129 #ifndef __NO_EMBEDDED_ASM
emilmont 60:3d0ef94e36ec 130 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 60:3d0ef94e36ec 131 {
emilmont 60:3d0ef94e36ec 132 revsh r0, r0
emilmont 60:3d0ef94e36ec 133 bx lr
emilmont 60:3d0ef94e36ec 134 }
emilmont 60:3d0ef94e36ec 135 #endif
emilmont 60:3d0ef94e36ec 136
emilmont 60:3d0ef94e36ec 137
emilmont 60:3d0ef94e36ec 138 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 60:3d0ef94e36ec 139
emilmont 60:3d0ef94e36ec 140 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 60:3d0ef94e36ec 141
emilmont 60:3d0ef94e36ec 142 \param [in] value Value to rotate
emilmont 60:3d0ef94e36ec 143 \param [in] value Number of Bits to rotate
emilmont 60:3d0ef94e36ec 144 \return Rotated value
emilmont 60:3d0ef94e36ec 145 */
emilmont 60:3d0ef94e36ec 146 #define __ROR __ror
emilmont 60:3d0ef94e36ec 147
emilmont 60:3d0ef94e36ec 148
emilmont 60:3d0ef94e36ec 149 /** \brief Breakpoint
emilmont 60:3d0ef94e36ec 150
emilmont 60:3d0ef94e36ec 151 This function causes the processor to enter Debug state.
emilmont 60:3d0ef94e36ec 152 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 60:3d0ef94e36ec 153
emilmont 60:3d0ef94e36ec 154 \param [in] value is ignored by the processor.
emilmont 60:3d0ef94e36ec 155 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 60:3d0ef94e36ec 156 */
emilmont 60:3d0ef94e36ec 157 #define __BKPT(value) __breakpoint(value)
emilmont 60:3d0ef94e36ec 158
emilmont 60:3d0ef94e36ec 159
emilmont 60:3d0ef94e36ec 160 #if (__CORTEX_M >= 0x03)
emilmont 60:3d0ef94e36ec 161
emilmont 60:3d0ef94e36ec 162 /** \brief Reverse bit order of value
emilmont 60:3d0ef94e36ec 163
emilmont 60:3d0ef94e36ec 164 This function reverses the bit order of the given value.
emilmont 60:3d0ef94e36ec 165
emilmont 60:3d0ef94e36ec 166 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 167 \return Reversed value
emilmont 60:3d0ef94e36ec 168 */
emilmont 60:3d0ef94e36ec 169 #define __RBIT __rbit
emilmont 60:3d0ef94e36ec 170
emilmont 60:3d0ef94e36ec 171
emilmont 60:3d0ef94e36ec 172 /** \brief LDR Exclusive (8 bit)
emilmont 60:3d0ef94e36ec 173
emilmont 60:3d0ef94e36ec 174 This function performs a exclusive LDR command for 8 bit value.
emilmont 60:3d0ef94e36ec 175
emilmont 60:3d0ef94e36ec 176 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 177 \return value of type uint8_t at (*ptr)
emilmont 60:3d0ef94e36ec 178 */
emilmont 60:3d0ef94e36ec 179 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 60:3d0ef94e36ec 180
emilmont 60:3d0ef94e36ec 181
emilmont 60:3d0ef94e36ec 182 /** \brief LDR Exclusive (16 bit)
emilmont 60:3d0ef94e36ec 183
emilmont 60:3d0ef94e36ec 184 This function performs a exclusive LDR command for 16 bit values.
emilmont 60:3d0ef94e36ec 185
emilmont 60:3d0ef94e36ec 186 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 187 \return value of type uint16_t at (*ptr)
emilmont 60:3d0ef94e36ec 188 */
emilmont 60:3d0ef94e36ec 189 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 60:3d0ef94e36ec 190
emilmont 60:3d0ef94e36ec 191
emilmont 60:3d0ef94e36ec 192 /** \brief LDR Exclusive (32 bit)
emilmont 60:3d0ef94e36ec 193
emilmont 60:3d0ef94e36ec 194 This function performs a exclusive LDR command for 32 bit values.
emilmont 60:3d0ef94e36ec 195
emilmont 60:3d0ef94e36ec 196 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 197 \return value of type uint32_t at (*ptr)
emilmont 60:3d0ef94e36ec 198 */
emilmont 60:3d0ef94e36ec 199 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 60:3d0ef94e36ec 200
emilmont 60:3d0ef94e36ec 201
emilmont 60:3d0ef94e36ec 202 /** \brief STR Exclusive (8 bit)
emilmont 60:3d0ef94e36ec 203
emilmont 60:3d0ef94e36ec 204 This function performs a exclusive STR command for 8 bit values.
emilmont 60:3d0ef94e36ec 205
emilmont 60:3d0ef94e36ec 206 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 207 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 208 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 209 \return 1 Function failed
emilmont 60:3d0ef94e36ec 210 */
emilmont 60:3d0ef94e36ec 211 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 60:3d0ef94e36ec 212
emilmont 60:3d0ef94e36ec 213
emilmont 60:3d0ef94e36ec 214 /** \brief STR Exclusive (16 bit)
emilmont 60:3d0ef94e36ec 215
emilmont 60:3d0ef94e36ec 216 This function performs a exclusive STR command for 16 bit values.
emilmont 60:3d0ef94e36ec 217
emilmont 60:3d0ef94e36ec 218 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 219 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 220 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 221 \return 1 Function failed
emilmont 60:3d0ef94e36ec 222 */
emilmont 60:3d0ef94e36ec 223 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 60:3d0ef94e36ec 224
emilmont 60:3d0ef94e36ec 225
emilmont 60:3d0ef94e36ec 226 /** \brief STR Exclusive (32 bit)
emilmont 60:3d0ef94e36ec 227
emilmont 60:3d0ef94e36ec 228 This function performs a exclusive STR command for 32 bit values.
emilmont 60:3d0ef94e36ec 229
emilmont 60:3d0ef94e36ec 230 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 231 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 232 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 233 \return 1 Function failed
emilmont 60:3d0ef94e36ec 234 */
emilmont 60:3d0ef94e36ec 235 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 60:3d0ef94e36ec 236
emilmont 60:3d0ef94e36ec 237
emilmont 60:3d0ef94e36ec 238 /** \brief Remove the exclusive lock
emilmont 60:3d0ef94e36ec 239
emilmont 60:3d0ef94e36ec 240 This function removes the exclusive lock which is created by LDREX.
emilmont 60:3d0ef94e36ec 241
emilmont 60:3d0ef94e36ec 242 */
emilmont 60:3d0ef94e36ec 243 #define __CLREX __clrex
emilmont 60:3d0ef94e36ec 244
emilmont 60:3d0ef94e36ec 245
emilmont 60:3d0ef94e36ec 246 /** \brief Signed Saturate
emilmont 60:3d0ef94e36ec 247
emilmont 60:3d0ef94e36ec 248 This function saturates a signed value.
emilmont 60:3d0ef94e36ec 249
emilmont 60:3d0ef94e36ec 250 \param [in] value Value to be saturated
emilmont 60:3d0ef94e36ec 251 \param [in] sat Bit position to saturate to (1..32)
emilmont 60:3d0ef94e36ec 252 \return Saturated value
emilmont 60:3d0ef94e36ec 253 */
emilmont 60:3d0ef94e36ec 254 #define __SSAT __ssat
emilmont 60:3d0ef94e36ec 255
emilmont 60:3d0ef94e36ec 256
emilmont 60:3d0ef94e36ec 257 /** \brief Unsigned Saturate
emilmont 60:3d0ef94e36ec 258
emilmont 60:3d0ef94e36ec 259 This function saturates an unsigned value.
emilmont 60:3d0ef94e36ec 260
emilmont 60:3d0ef94e36ec 261 \param [in] value Value to be saturated
emilmont 60:3d0ef94e36ec 262 \param [in] sat Bit position to saturate to (0..31)
emilmont 60:3d0ef94e36ec 263 \return Saturated value
emilmont 60:3d0ef94e36ec 264 */
emilmont 60:3d0ef94e36ec 265 #define __USAT __usat
emilmont 60:3d0ef94e36ec 266
emilmont 60:3d0ef94e36ec 267
emilmont 60:3d0ef94e36ec 268 /** \brief Count leading zeros
emilmont 60:3d0ef94e36ec 269
emilmont 60:3d0ef94e36ec 270 This function counts the number of leading zeros of a data value.
emilmont 60:3d0ef94e36ec 271
emilmont 60:3d0ef94e36ec 272 \param [in] value Value to count the leading zeros
emilmont 60:3d0ef94e36ec 273 \return number of leading zeros in value
emilmont 60:3d0ef94e36ec 274 */
emilmont 60:3d0ef94e36ec 275 #define __CLZ __clz
emilmont 60:3d0ef94e36ec 276
emilmont 60:3d0ef94e36ec 277 #endif /* (__CORTEX_M >= 0x03) */
emilmont 60:3d0ef94e36ec 278
emilmont 60:3d0ef94e36ec 279
emilmont 60:3d0ef94e36ec 280
emilmont 60:3d0ef94e36ec 281 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 60:3d0ef94e36ec 282 /* IAR iccarm specific functions */
emilmont 60:3d0ef94e36ec 283
emilmont 60:3d0ef94e36ec 284 #include <cmsis_iar.h>
emilmont 60:3d0ef94e36ec 285
emilmont 60:3d0ef94e36ec 286
emilmont 60:3d0ef94e36ec 287 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 60:3d0ef94e36ec 288 /* TI CCS specific functions */
emilmont 60:3d0ef94e36ec 289
emilmont 60:3d0ef94e36ec 290 #include <cmsis_ccs.h>
emilmont 60:3d0ef94e36ec 291
emilmont 60:3d0ef94e36ec 292
emilmont 60:3d0ef94e36ec 293 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 60:3d0ef94e36ec 294 /* GNU gcc specific functions */
emilmont 60:3d0ef94e36ec 295
emilmont 60:3d0ef94e36ec 296 /** \brief No Operation
emilmont 60:3d0ef94e36ec 297
emilmont 60:3d0ef94e36ec 298 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 60:3d0ef94e36ec 299 */
emilmont 60:3d0ef94e36ec 300 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 60:3d0ef94e36ec 301 {
emilmont 60:3d0ef94e36ec 302 __ASM volatile ("nop");
emilmont 60:3d0ef94e36ec 303 }
emilmont 60:3d0ef94e36ec 304
emilmont 60:3d0ef94e36ec 305
emilmont 60:3d0ef94e36ec 306 /** \brief Wait For Interrupt
emilmont 60:3d0ef94e36ec 307
emilmont 60:3d0ef94e36ec 308 Wait For Interrupt is a hint instruction that suspends execution
emilmont 60:3d0ef94e36ec 309 until one of a number of events occurs.
emilmont 60:3d0ef94e36ec 310 */
emilmont 60:3d0ef94e36ec 311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 60:3d0ef94e36ec 312 {
emilmont 60:3d0ef94e36ec 313 __ASM volatile ("wfi");
emilmont 60:3d0ef94e36ec 314 }
emilmont 60:3d0ef94e36ec 315
emilmont 60:3d0ef94e36ec 316
emilmont 60:3d0ef94e36ec 317 /** \brief Wait For Event
emilmont 60:3d0ef94e36ec 318
emilmont 60:3d0ef94e36ec 319 Wait For Event is a hint instruction that permits the processor to enter
emilmont 60:3d0ef94e36ec 320 a low-power state until one of a number of events occurs.
emilmont 60:3d0ef94e36ec 321 */
emilmont 60:3d0ef94e36ec 322 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 60:3d0ef94e36ec 323 {
emilmont 60:3d0ef94e36ec 324 __ASM volatile ("wfe");
emilmont 60:3d0ef94e36ec 325 }
emilmont 60:3d0ef94e36ec 326
emilmont 60:3d0ef94e36ec 327
emilmont 60:3d0ef94e36ec 328 /** \brief Send Event
emilmont 60:3d0ef94e36ec 329
emilmont 60:3d0ef94e36ec 330 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 60:3d0ef94e36ec 331 */
emilmont 60:3d0ef94e36ec 332 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 60:3d0ef94e36ec 333 {
emilmont 60:3d0ef94e36ec 334 __ASM volatile ("sev");
emilmont 60:3d0ef94e36ec 335 }
emilmont 60:3d0ef94e36ec 336
emilmont 60:3d0ef94e36ec 337
emilmont 60:3d0ef94e36ec 338 /** \brief Instruction Synchronization Barrier
emilmont 60:3d0ef94e36ec 339
emilmont 60:3d0ef94e36ec 340 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 60:3d0ef94e36ec 341 so that all instructions following the ISB are fetched from cache or
emilmont 60:3d0ef94e36ec 342 memory, after the instruction has been completed.
emilmont 60:3d0ef94e36ec 343 */
emilmont 60:3d0ef94e36ec 344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 60:3d0ef94e36ec 345 {
emilmont 60:3d0ef94e36ec 346 __ASM volatile ("isb");
emilmont 60:3d0ef94e36ec 347 }
emilmont 60:3d0ef94e36ec 348
emilmont 60:3d0ef94e36ec 349
emilmont 60:3d0ef94e36ec 350 /** \brief Data Synchronization Barrier
emilmont 60:3d0ef94e36ec 351
emilmont 60:3d0ef94e36ec 352 This function acts as a special kind of Data Memory Barrier.
emilmont 60:3d0ef94e36ec 353 It completes when all explicit memory accesses before this instruction complete.
emilmont 60:3d0ef94e36ec 354 */
emilmont 60:3d0ef94e36ec 355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 60:3d0ef94e36ec 356 {
emilmont 60:3d0ef94e36ec 357 __ASM volatile ("dsb");
emilmont 60:3d0ef94e36ec 358 }
emilmont 60:3d0ef94e36ec 359
emilmont 60:3d0ef94e36ec 360
emilmont 60:3d0ef94e36ec 361 /** \brief Data Memory Barrier
emilmont 60:3d0ef94e36ec 362
emilmont 60:3d0ef94e36ec 363 This function ensures the apparent order of the explicit memory operations before
emilmont 60:3d0ef94e36ec 364 and after the instruction, without ensuring their completion.
emilmont 60:3d0ef94e36ec 365 */
emilmont 60:3d0ef94e36ec 366 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 60:3d0ef94e36ec 367 {
emilmont 60:3d0ef94e36ec 368 __ASM volatile ("dmb");
emilmont 60:3d0ef94e36ec 369 }
emilmont 60:3d0ef94e36ec 370
emilmont 60:3d0ef94e36ec 371
emilmont 60:3d0ef94e36ec 372 /** \brief Reverse byte order (32 bit)
emilmont 60:3d0ef94e36ec 373
emilmont 60:3d0ef94e36ec 374 This function reverses the byte order in integer value.
emilmont 60:3d0ef94e36ec 375
emilmont 60:3d0ef94e36ec 376 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 377 \return Reversed value
emilmont 60:3d0ef94e36ec 378 */
emilmont 60:3d0ef94e36ec 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 60:3d0ef94e36ec 380 {
emilmont 60:3d0ef94e36ec 381 uint32_t result;
emilmont 60:3d0ef94e36ec 382
emilmont 60:3d0ef94e36ec 383 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 60:3d0ef94e36ec 384 return(result);
emilmont 60:3d0ef94e36ec 385 }
emilmont 60:3d0ef94e36ec 386
emilmont 60:3d0ef94e36ec 387
emilmont 60:3d0ef94e36ec 388 /** \brief Reverse byte order (16 bit)
emilmont 60:3d0ef94e36ec 389
emilmont 60:3d0ef94e36ec 390 This function reverses the byte order in two unsigned short values.
emilmont 60:3d0ef94e36ec 391
emilmont 60:3d0ef94e36ec 392 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 393 \return Reversed value
emilmont 60:3d0ef94e36ec 394 */
emilmont 60:3d0ef94e36ec 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 60:3d0ef94e36ec 396 {
emilmont 60:3d0ef94e36ec 397 uint32_t result;
emilmont 60:3d0ef94e36ec 398
emilmont 60:3d0ef94e36ec 399 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 60:3d0ef94e36ec 400 return(result);
emilmont 60:3d0ef94e36ec 401 }
emilmont 60:3d0ef94e36ec 402
emilmont 60:3d0ef94e36ec 403
emilmont 60:3d0ef94e36ec 404 /** \brief Reverse byte order in signed short value
emilmont 60:3d0ef94e36ec 405
emilmont 60:3d0ef94e36ec 406 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 60:3d0ef94e36ec 407
emilmont 60:3d0ef94e36ec 408 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 409 \return Reversed value
emilmont 60:3d0ef94e36ec 410 */
emilmont 60:3d0ef94e36ec 411 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 60:3d0ef94e36ec 412 {
emilmont 60:3d0ef94e36ec 413 uint32_t result;
emilmont 60:3d0ef94e36ec 414
emilmont 60:3d0ef94e36ec 415 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 60:3d0ef94e36ec 416 return(result);
emilmont 60:3d0ef94e36ec 417 }
emilmont 60:3d0ef94e36ec 418
emilmont 60:3d0ef94e36ec 419
emilmont 60:3d0ef94e36ec 420 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 60:3d0ef94e36ec 421
emilmont 60:3d0ef94e36ec 422 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 60:3d0ef94e36ec 423
emilmont 60:3d0ef94e36ec 424 \param [in] value Value to rotate
emilmont 60:3d0ef94e36ec 425 \param [in] value Number of Bits to rotate
emilmont 60:3d0ef94e36ec 426 \return Rotated value
emilmont 60:3d0ef94e36ec 427 */
emilmont 60:3d0ef94e36ec 428 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 60:3d0ef94e36ec 429 {
emilmont 60:3d0ef94e36ec 430
emilmont 60:3d0ef94e36ec 431 __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
emilmont 60:3d0ef94e36ec 432 return(op1);
emilmont 60:3d0ef94e36ec 433 }
emilmont 60:3d0ef94e36ec 434
emilmont 60:3d0ef94e36ec 435
emilmont 60:3d0ef94e36ec 436 /** \brief Breakpoint
emilmont 60:3d0ef94e36ec 437
emilmont 60:3d0ef94e36ec 438 This function causes the processor to enter Debug state.
emilmont 60:3d0ef94e36ec 439 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 60:3d0ef94e36ec 440
emilmont 60:3d0ef94e36ec 441 \param [in] value is ignored by the processor.
emilmont 60:3d0ef94e36ec 442 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 60:3d0ef94e36ec 443 */
emilmont 60:3d0ef94e36ec 444 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 60:3d0ef94e36ec 445
emilmont 60:3d0ef94e36ec 446
emilmont 60:3d0ef94e36ec 447 #if (__CORTEX_M >= 0x03)
emilmont 60:3d0ef94e36ec 448
emilmont 60:3d0ef94e36ec 449 /** \brief Reverse bit order of value
emilmont 60:3d0ef94e36ec 450
emilmont 60:3d0ef94e36ec 451 This function reverses the bit order of the given value.
emilmont 60:3d0ef94e36ec 452
emilmont 60:3d0ef94e36ec 453 \param [in] value Value to reverse
emilmont 60:3d0ef94e36ec 454 \return Reversed value
emilmont 60:3d0ef94e36ec 455 */
emilmont 60:3d0ef94e36ec 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 60:3d0ef94e36ec 457 {
emilmont 60:3d0ef94e36ec 458 uint32_t result;
emilmont 60:3d0ef94e36ec 459
emilmont 60:3d0ef94e36ec 460 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 60:3d0ef94e36ec 461 return(result);
emilmont 60:3d0ef94e36ec 462 }
emilmont 60:3d0ef94e36ec 463
emilmont 60:3d0ef94e36ec 464
emilmont 60:3d0ef94e36ec 465 /** \brief LDR Exclusive (8 bit)
emilmont 60:3d0ef94e36ec 466
emilmont 60:3d0ef94e36ec 467 This function performs a exclusive LDR command for 8 bit value.
emilmont 60:3d0ef94e36ec 468
emilmont 60:3d0ef94e36ec 469 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 470 \return value of type uint8_t at (*ptr)
emilmont 60:3d0ef94e36ec 471 */
emilmont 60:3d0ef94e36ec 472 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 60:3d0ef94e36ec 473 {
emilmont 60:3d0ef94e36ec 474 uint8_t result;
emilmont 60:3d0ef94e36ec 475
emilmont 60:3d0ef94e36ec 476 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 60:3d0ef94e36ec 477 return(result);
emilmont 60:3d0ef94e36ec 478 }
emilmont 60:3d0ef94e36ec 479
emilmont 60:3d0ef94e36ec 480
emilmont 60:3d0ef94e36ec 481 /** \brief LDR Exclusive (16 bit)
emilmont 60:3d0ef94e36ec 482
emilmont 60:3d0ef94e36ec 483 This function performs a exclusive LDR command for 16 bit values.
emilmont 60:3d0ef94e36ec 484
emilmont 60:3d0ef94e36ec 485 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 486 \return value of type uint16_t at (*ptr)
emilmont 60:3d0ef94e36ec 487 */
emilmont 60:3d0ef94e36ec 488 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 60:3d0ef94e36ec 489 {
emilmont 60:3d0ef94e36ec 490 uint16_t result;
emilmont 60:3d0ef94e36ec 491
emilmont 60:3d0ef94e36ec 492 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 60:3d0ef94e36ec 493 return(result);
emilmont 60:3d0ef94e36ec 494 }
emilmont 60:3d0ef94e36ec 495
emilmont 60:3d0ef94e36ec 496
emilmont 60:3d0ef94e36ec 497 /** \brief LDR Exclusive (32 bit)
emilmont 60:3d0ef94e36ec 498
emilmont 60:3d0ef94e36ec 499 This function performs a exclusive LDR command for 32 bit values.
emilmont 60:3d0ef94e36ec 500
emilmont 60:3d0ef94e36ec 501 \param [in] ptr Pointer to data
emilmont 60:3d0ef94e36ec 502 \return value of type uint32_t at (*ptr)
emilmont 60:3d0ef94e36ec 503 */
emilmont 60:3d0ef94e36ec 504 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 60:3d0ef94e36ec 505 {
emilmont 60:3d0ef94e36ec 506 uint32_t result;
emilmont 60:3d0ef94e36ec 507
emilmont 60:3d0ef94e36ec 508 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 60:3d0ef94e36ec 509 return(result);
emilmont 60:3d0ef94e36ec 510 }
emilmont 60:3d0ef94e36ec 511
emilmont 60:3d0ef94e36ec 512
emilmont 60:3d0ef94e36ec 513 /** \brief STR Exclusive (8 bit)
emilmont 60:3d0ef94e36ec 514
emilmont 60:3d0ef94e36ec 515 This function performs a exclusive STR command for 8 bit values.
emilmont 60:3d0ef94e36ec 516
emilmont 60:3d0ef94e36ec 517 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 518 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 519 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 520 \return 1 Function failed
emilmont 60:3d0ef94e36ec 521 */
emilmont 60:3d0ef94e36ec 522 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 60:3d0ef94e36ec 523 {
emilmont 60:3d0ef94e36ec 524 uint32_t result;
emilmont 60:3d0ef94e36ec 525
emilmont 60:3d0ef94e36ec 526 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 60:3d0ef94e36ec 527 return(result);
emilmont 60:3d0ef94e36ec 528 }
emilmont 60:3d0ef94e36ec 529
emilmont 60:3d0ef94e36ec 530
emilmont 60:3d0ef94e36ec 531 /** \brief STR Exclusive (16 bit)
emilmont 60:3d0ef94e36ec 532
emilmont 60:3d0ef94e36ec 533 This function performs a exclusive STR command for 16 bit values.
emilmont 60:3d0ef94e36ec 534
emilmont 60:3d0ef94e36ec 535 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 536 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 537 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 538 \return 1 Function failed
emilmont 60:3d0ef94e36ec 539 */
emilmont 60:3d0ef94e36ec 540 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 60:3d0ef94e36ec 541 {
emilmont 60:3d0ef94e36ec 542 uint32_t result;
emilmont 60:3d0ef94e36ec 543
emilmont 60:3d0ef94e36ec 544 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 60:3d0ef94e36ec 545 return(result);
emilmont 60:3d0ef94e36ec 546 }
emilmont 60:3d0ef94e36ec 547
emilmont 60:3d0ef94e36ec 548
emilmont 60:3d0ef94e36ec 549 /** \brief STR Exclusive (32 bit)
emilmont 60:3d0ef94e36ec 550
emilmont 60:3d0ef94e36ec 551 This function performs a exclusive STR command for 32 bit values.
emilmont 60:3d0ef94e36ec 552
emilmont 60:3d0ef94e36ec 553 \param [in] value Value to store
emilmont 60:3d0ef94e36ec 554 \param [in] ptr Pointer to location
emilmont 60:3d0ef94e36ec 555 \return 0 Function succeeded
emilmont 60:3d0ef94e36ec 556 \return 1 Function failed
emilmont 60:3d0ef94e36ec 557 */
emilmont 60:3d0ef94e36ec 558 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 60:3d0ef94e36ec 559 {
emilmont 60:3d0ef94e36ec 560 uint32_t result;
emilmont 60:3d0ef94e36ec 561
emilmont 60:3d0ef94e36ec 562 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 60:3d0ef94e36ec 563 return(result);
emilmont 60:3d0ef94e36ec 564 }
emilmont 60:3d0ef94e36ec 565
emilmont 60:3d0ef94e36ec 566
emilmont 60:3d0ef94e36ec 567 /** \brief Remove the exclusive lock
emilmont 60:3d0ef94e36ec 568
emilmont 60:3d0ef94e36ec 569 This function removes the exclusive lock which is created by LDREX.
emilmont 60:3d0ef94e36ec 570
emilmont 60:3d0ef94e36ec 571 */
emilmont 60:3d0ef94e36ec 572 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 60:3d0ef94e36ec 573 {
emilmont 60:3d0ef94e36ec 574 __ASM volatile ("clrex");
emilmont 60:3d0ef94e36ec 575 }
emilmont 60:3d0ef94e36ec 576
emilmont 60:3d0ef94e36ec 577
emilmont 60:3d0ef94e36ec 578 /** \brief Signed Saturate
emilmont 60:3d0ef94e36ec 579
emilmont 60:3d0ef94e36ec 580 This function saturates a signed value.
emilmont 60:3d0ef94e36ec 581
emilmont 60:3d0ef94e36ec 582 \param [in] value Value to be saturated
emilmont 60:3d0ef94e36ec 583 \param [in] sat Bit position to saturate to (1..32)
emilmont 60:3d0ef94e36ec 584 \return Saturated value
emilmont 60:3d0ef94e36ec 585 */
emilmont 60:3d0ef94e36ec 586 #define __SSAT(ARG1,ARG2) \
emilmont 60:3d0ef94e36ec 587 ({ \
emilmont 60:3d0ef94e36ec 588 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 60:3d0ef94e36ec 589 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 60:3d0ef94e36ec 590 __RES; \
emilmont 60:3d0ef94e36ec 591 })
emilmont 60:3d0ef94e36ec 592
emilmont 60:3d0ef94e36ec 593
emilmont 60:3d0ef94e36ec 594 /** \brief Unsigned Saturate
emilmont 60:3d0ef94e36ec 595
emilmont 60:3d0ef94e36ec 596 This function saturates an unsigned value.
emilmont 60:3d0ef94e36ec 597
emilmont 60:3d0ef94e36ec 598 \param [in] value Value to be saturated
emilmont 60:3d0ef94e36ec 599 \param [in] sat Bit position to saturate to (0..31)
emilmont 60:3d0ef94e36ec 600 \return Saturated value
emilmont 60:3d0ef94e36ec 601 */
emilmont 60:3d0ef94e36ec 602 #define __USAT(ARG1,ARG2) \
emilmont 60:3d0ef94e36ec 603 ({ \
emilmont 60:3d0ef94e36ec 604 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 60:3d0ef94e36ec 605 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 60:3d0ef94e36ec 606 __RES; \
emilmont 60:3d0ef94e36ec 607 })
emilmont 60:3d0ef94e36ec 608
emilmont 60:3d0ef94e36ec 609
emilmont 60:3d0ef94e36ec 610 /** \brief Count leading zeros
emilmont 60:3d0ef94e36ec 611
emilmont 60:3d0ef94e36ec 612 This function counts the number of leading zeros of a data value.
emilmont 60:3d0ef94e36ec 613
emilmont 60:3d0ef94e36ec 614 \param [in] value Value to count the leading zeros
emilmont 60:3d0ef94e36ec 615 \return number of leading zeros in value
emilmont 60:3d0ef94e36ec 616 */
emilmont 60:3d0ef94e36ec 617 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 60:3d0ef94e36ec 618 {
emilmont 60:3d0ef94e36ec 619 uint8_t result;
emilmont 60:3d0ef94e36ec 620
emilmont 60:3d0ef94e36ec 621 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 60:3d0ef94e36ec 622 return(result);
emilmont 60:3d0ef94e36ec 623 }
emilmont 60:3d0ef94e36ec 624
emilmont 60:3d0ef94e36ec 625 #endif /* (__CORTEX_M >= 0x03) */
emilmont 60:3d0ef94e36ec 626
emilmont 60:3d0ef94e36ec 627
emilmont 60:3d0ef94e36ec 628
emilmont 60:3d0ef94e36ec 629
emilmont 60:3d0ef94e36ec 630 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 60:3d0ef94e36ec 631 /* TASKING carm specific functions */
emilmont 60:3d0ef94e36ec 632
emilmont 60:3d0ef94e36ec 633 /*
emilmont 60:3d0ef94e36ec 634 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 60:3d0ef94e36ec 635 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 60:3d0ef94e36ec 636 * Including the CMSIS ones.
emilmont 60:3d0ef94e36ec 637 */
emilmont 60:3d0ef94e36ec 638
emilmont 60:3d0ef94e36ec 639 #endif
emilmont 60:3d0ef94e36ec 640
emilmont 60:3d0ef94e36ec 641 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 60:3d0ef94e36ec 642
emilmont 60:3d0ef94e36ec 643 #endif /* __CORE_CMINSTR_H */