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targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c@637:ed69428d4850, 2015-12-22 (annotated)

Committer:
jaerts
Date:
Tue Dec 22 13:22:16 2015 +0000
Revision:
637:ed69428d4850
Parent:
530:2939f5396008 
Add very shady LPC1768 CAN Filter implementation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include "can_api.h"
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22 #include <math.h>
emilmont 10:3bc89ef62ce7 23 #include <string.h>
emilmont 10:3bc89ef62ce7 24
bogdanm 15:4892fe388435 25 #define CAN_NUM 2
bogdanm 15:4892fe388435 26
emilmont 10:3bc89ef62ce7 27 /* Acceptance filter mode in AFMR register */
emilmont 10:3bc89ef62ce7 28 #define ACCF_OFF 0x01
emilmont 10:3bc89ef62ce7 29 #define ACCF_BYPASS 0x02
emilmont 10:3bc89ef62ce7 30 #define ACCF_ON 0x00
emilmont 10:3bc89ef62ce7 31 #define ACCF_FULLCAN 0x04
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33 /* There are several bit timing calculators on the internet.
emilmont 10:3bc89ef62ce7 34 http://www.port.de/engl/canprod/sv_req_form.html
emilmont 10:3bc89ef62ce7 35 http://www.kvaser.com/can/index.htm
emilmont 10:3bc89ef62ce7 36 */
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 static const PinMap PinMap_CAN_RD[] = {
emilmont 10:3bc89ef62ce7 39 {P0_0 , CAN_1, 1},
emilmont 10:3bc89ef62ce7 40 {P0_4 , CAN_2, 2},
emilmont 10:3bc89ef62ce7 41 {P0_21, CAN_1, 3},
emilmont 10:3bc89ef62ce7 42 {P2_7 , CAN_2, 1},
emilmont 10:3bc89ef62ce7 43 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 44 };
emilmont 10:3bc89ef62ce7 45
emilmont 10:3bc89ef62ce7 46 static const PinMap PinMap_CAN_TD[] = {
emilmont 10:3bc89ef62ce7 47 {P0_1 , CAN_1, 1},
emilmont 10:3bc89ef62ce7 48 {P0_5 , CAN_2, 2},
emilmont 10:3bc89ef62ce7 49 {P0_22, CAN_1, 3},
emilmont 10:3bc89ef62ce7 50 {P2_8 , CAN_2, 1},
emilmont 10:3bc89ef62ce7 51 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 52 };
emilmont 10:3bc89ef62ce7 53
emilmont 10:3bc89ef62ce7 54 // Type definition to hold a CAN message
emilmont 10:3bc89ef62ce7 55 struct CANMsg {
emilmont 10:3bc89ef62ce7 56 unsigned int reserved1 : 16;
emilmont 10:3bc89ef62ce7 57 unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
emilmont 10:3bc89ef62ce7 58 unsigned int reserved0 : 10;
emilmont 10:3bc89ef62ce7 59 unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
emilmont 10:3bc89ef62ce7 60 unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
emilmont 10:3bc89ef62ce7 61 unsigned int id; // CAN Message ID (11-bit or 29-bit)
emilmont 10:3bc89ef62ce7 62 unsigned char data[8]; // CAN Message Data Bytes 0-7
emilmont 10:3bc89ef62ce7 63 };
emilmont 10:3bc89ef62ce7 64 typedef struct CANMsg CANMsg;
emilmont 10:3bc89ef62ce7 65
jaerts 637:ed69428d4850 66 static int CAN_std_cnt = 0;
jaerts 637:ed69428d4850 67 static int CAN_ext_cnt = 0;
jaerts 637:ed69428d4850 68
bogdanm 15:4892fe388435 69 static uint32_t can_irq_ids[CAN_NUM] = {0};
bogdanm 15:4892fe388435 70 static can_irq_handler irq_handler;
bogdanm 15:4892fe388435 71
emilmont 10:3bc89ef62ce7 72 static uint32_t can_disable(can_t *obj) {
emilmont 10:3bc89ef62ce7 73 uint32_t sm = obj->dev->MOD;
emilmont 10:3bc89ef62ce7 74 obj->dev->MOD |= 1;
emilmont 10:3bc89ef62ce7 75 return sm;
emilmont 10:3bc89ef62ce7 76 }
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 static inline void can_enable(can_t *obj) {
emilmont 10:3bc89ef62ce7 79 if (obj->dev->MOD & 1) {
emilmont 10:3bc89ef62ce7 80 obj->dev->MOD &= ~(1);
emilmont 10:3bc89ef62ce7 81 }
emilmont 10:3bc89ef62ce7 82 }
emilmont 10:3bc89ef62ce7 83
mbed_official 41:e8b66477f5bf 84 int can_mode(can_t *obj, CanMode mode) {
mbed_official 530:2939f5396008 85 int success = 0;
mbed_official 530:2939f5396008 86 switch (mode) {
mbed_official 530:2939f5396008 87 case MODE_RESET:
mbed_official 530:2939f5396008 88 // Clear all special modes
mbed_official 530:2939f5396008 89 can_reset(obj);
mbed_official 530:2939f5396008 90 obj->dev->MOD &=~ 0x06;
mbed_official 530:2939f5396008 91 success = 1;
mbed_official 530:2939f5396008 92 break;
mbed_official 530:2939f5396008 93 case MODE_NORMAL:
mbed_official 530:2939f5396008 94 // Clear all special modes
mbed_official 530:2939f5396008 95 can_disable(obj);
mbed_official 530:2939f5396008 96 obj->dev->MOD &=~ 0x06;
mbed_official 530:2939f5396008 97 can_enable(obj);
mbed_official 530:2939f5396008 98 success = 1;
mbed_official 530:2939f5396008 99 break;
mbed_official 530:2939f5396008 100 case MODE_SILENT:
mbed_official 530:2939f5396008 101 // Set listen-only mode and clear self-test mode
mbed_official 530:2939f5396008 102 can_disable(obj);
mbed_official 530:2939f5396008 103 obj->dev->MOD |= 0x02;
mbed_official 530:2939f5396008 104 obj->dev->MOD &=~ 0x04;
mbed_official 530:2939f5396008 105 can_enable(obj);
mbed_official 530:2939f5396008 106 success = 1;
mbed_official 530:2939f5396008 107 break;
mbed_official 530:2939f5396008 108 case MODE_TEST_LOCAL:
mbed_official 530:2939f5396008 109 // Set self-test mode and clear listen-only mode
mbed_official 530:2939f5396008 110 can_disable(obj);
mbed_official 530:2939f5396008 111 obj->dev->MOD |= 0x04;
mbed_official 530:2939f5396008 112 obj->dev->MOD &=~ 0x02;
mbed_official 530:2939f5396008 113 can_enable(obj);
mbed_official 530:2939f5396008 114 success = 1;
mbed_official 530:2939f5396008 115 break;
mbed_official 530:2939f5396008 116 case MODE_TEST_SILENT:
mbed_official 530:2939f5396008 117 case MODE_TEST_GLOBAL:
mbed_official 530:2939f5396008 118 default:
mbed_official 530:2939f5396008 119 success = 0;
mbed_official 530:2939f5396008 120 break;
mbed_official 530:2939f5396008 121 }
mbed_official 530:2939f5396008 122
mbed_official 530:2939f5396008 123 return success;
mbed_official 41:e8b66477f5bf 124 }
mbed_official 41:e8b66477f5bf 125
mbed_official 41:e8b66477f5bf 126 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
jaerts 637:ed69428d4850 127 uint32_t buf0, buf1;
jaerts 637:ed69428d4850 128 int cnt1, cnt2, bound1;
jaerts 637:ed69428d4850 129
jaerts 637:ed69428d4850 130 /* Acceptance Filter Memory full */
jaerts 637:ed69428d4850 131 if ((((CAN_std_cnt + 1) >> 1) + CAN_ext_cnt) >= 512)
jaerts 637:ed69428d4850 132 return 0; /* error: objects full */
jaerts 637:ed69428d4850 133
jaerts 637:ed69428d4850 134 /* Setup Acceptance Filter Configuration
jaerts 637:ed69428d4850 135 Acceptance Filter Mode Register = Off */
jaerts 637:ed69428d4850 136 LPC_CANAF->AFMR = 0x00000001;
jaerts 637:ed69428d4850 137
jaerts 637:ed69428d4850 138 if (format == CANStandard) { /* Add mask for standard identifiers */
jaerts 637:ed69428d4850 139 id |= (int)obj->index << 13; /* Add controller number */
jaerts 637:ed69428d4850 140 id &= 0x0000F7FF; /* Mask out 16-bits of ID */
jaerts 637:ed69428d4850 141
jaerts 637:ed69428d4850 142 /* Move all remaining extended mask entries one place up
jaerts 637:ed69428d4850 143 if new entry will increase standard ID filters list */
jaerts 637:ed69428d4850 144 if ((CAN_std_cnt & 0x0001) == 0 && CAN_ext_cnt != 0) {
jaerts 637:ed69428d4850 145 cnt1 = (CAN_std_cnt >> 1);
jaerts 637:ed69428d4850 146 bound1 = CAN_ext_cnt;
jaerts 637:ed69428d4850 147 buf0 = LPC_CANAF_RAM->mask[cnt1];
jaerts 637:ed69428d4850 148 while (bound1--) {
jaerts 637:ed69428d4850 149 cnt1++;
jaerts 637:ed69428d4850 150 buf1 = LPC_CANAF_RAM->mask[cnt1];
jaerts 637:ed69428d4850 151 LPC_CANAF_RAM->mask[cnt1] = buf0;
jaerts 637:ed69428d4850 152 buf0 = buf1;
jaerts 637:ed69428d4850 153 }
jaerts 637:ed69428d4850 154 }
jaerts 637:ed69428d4850 155
jaerts 637:ed69428d4850 156 if (CAN_std_cnt == 0) { /* For entering first ID */
jaerts 637:ed69428d4850 157 LPC_CANAF_RAM->mask[0] = 0x0000FFFF | (id << 16);
jaerts 637:ed69428d4850 158 } else if (CAN_std_cnt == 1) { /* For entering second ID */
jaerts 637:ed69428d4850 159 if ((LPC_CANAF_RAM->mask[0] >> 16) > id)
jaerts 637:ed69428d4850 160 LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] >> 16) | (id << 16);
jaerts 637:ed69428d4850 161 else
jaerts 637:ed69428d4850 162 LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] & 0xFFFF0000) | id;
jaerts 637:ed69428d4850 163 } else {
jaerts 637:ed69428d4850 164 /* Find where to insert new ID */
jaerts 637:ed69428d4850 165 cnt1 = 0;
jaerts 637:ed69428d4850 166 cnt2 = CAN_std_cnt;
jaerts 637:ed69428d4850 167 bound1 = (CAN_std_cnt - 1) >> 1;
jaerts 637:ed69428d4850 168 while (cnt1 <= bound1) { /* Loop through standard existing IDs */
jaerts 637:ed69428d4850 169 if ((LPC_CANAF_RAM->mask[cnt1] >> 16) > id) {
jaerts 637:ed69428d4850 170 cnt2 = cnt1 * 2;
jaerts 637:ed69428d4850 171 break;
jaerts 637:ed69428d4850 172 }
jaerts 637:ed69428d4850 173 if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000FFFF) > id) {
jaerts 637:ed69428d4850 174 cnt2 = cnt1 * 2 + 1;
jaerts 637:ed69428d4850 175 break;
jaerts 637:ed69428d4850 176 }
jaerts 637:ed69428d4850 177 cnt1++; /* cnt1 = U32 where to insert new ID */
jaerts 637:ed69428d4850 178 } /* cnt2 = U16 where to insert new ID */
jaerts 637:ed69428d4850 179
jaerts 637:ed69428d4850 180 if (cnt1 > bound1) { /* Adding ID as last entry */
jaerts 637:ed69428d4850 181 if ((CAN_std_cnt & 0x0001) == 0) /* Even number of IDs exists */
jaerts 637:ed69428d4850 182 LPC_CANAF_RAM->mask[cnt1] = 0x0000FFFF | (id << 16);
jaerts 637:ed69428d4850 183 else /* Odd number of IDs exists */
jaerts 637:ed69428d4850 184 LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id;
jaerts 637:ed69428d4850 185 } else {
jaerts 637:ed69428d4850 186 buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
jaerts 637:ed69428d4850 187 if ((cnt2 & 0x0001) == 0) /* Insert new mask to even address */
jaerts 637:ed69428d4850 188 buf1 = (id << 16) | (buf0 >> 16);
jaerts 637:ed69428d4850 189 else /* Insert new mask to odd address */
jaerts 637:ed69428d4850 190 buf1 = (buf0 & 0xFFFF0000) | id;
jaerts 637:ed69428d4850 191
jaerts 637:ed69428d4850 192 LPC_CANAF_RAM->mask[cnt1] = buf1; /* Insert mask */
jaerts 637:ed69428d4850 193
jaerts 637:ed69428d4850 194 bound1 = CAN_std_cnt >> 1;
jaerts 637:ed69428d4850 195 /* Move all remaining standard mask entries one place up */
jaerts 637:ed69428d4850 196 while (cnt1 < bound1) {
jaerts 637:ed69428d4850 197 cnt1++;
jaerts 637:ed69428d4850 198 buf1 = LPC_CANAF_RAM->mask[cnt1];
jaerts 637:ed69428d4850 199 LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16);
jaerts 637:ed69428d4850 200 buf0 = buf1;
jaerts 637:ed69428d4850 201 }
jaerts 637:ed69428d4850 202
jaerts 637:ed69428d4850 203 if ((CAN_std_cnt & 0x0001) == 0) /* Even number of IDs exists */
jaerts 637:ed69428d4850 204 LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | (0x0000FFFF);
jaerts 637:ed69428d4850 205 }
jaerts 637:ed69428d4850 206 }
jaerts 637:ed69428d4850 207 CAN_std_cnt++;
jaerts 637:ed69428d4850 208 } else { /* Add mask for extended identifiers */
jaerts 637:ed69428d4850 209 id |= (int)obj->index << 29; /* Add controller number */
jaerts 637:ed69428d4850 210
jaerts 637:ed69428d4850 211 cnt1 = ((CAN_std_cnt + 1) >> 1);
jaerts 637:ed69428d4850 212 cnt2 = 0;
jaerts 637:ed69428d4850 213 while (cnt2 < CAN_ext_cnt) { /* Loop through extended existing masks */
jaerts 637:ed69428d4850 214 if (LPC_CANAF_RAM->mask[cnt1] > id)
jaerts 637:ed69428d4850 215 break;
jaerts 637:ed69428d4850 216 cnt1++; /* cnt1 = U32 where to insert new mask */
jaerts 637:ed69428d4850 217 cnt2++;
jaerts 637:ed69428d4850 218 }
jaerts 637:ed69428d4850 219
jaerts 637:ed69428d4850 220 buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
jaerts 637:ed69428d4850 221 LPC_CANAF_RAM->mask[cnt1] = id; /* Insert mask */
jaerts 637:ed69428d4850 222
jaerts 637:ed69428d4850 223 CAN_ext_cnt++;
jaerts 637:ed69428d4850 224
jaerts 637:ed69428d4850 225 bound1 = CAN_ext_cnt - 1;
jaerts 637:ed69428d4850 226 /* Move all remaining extended mask entries one place up */
jaerts 637:ed69428d4850 227 while (cnt2 < bound1) {
jaerts 637:ed69428d4850 228 cnt1++;
jaerts 637:ed69428d4850 229 cnt2++;
jaerts 637:ed69428d4850 230 buf1 = LPC_CANAF_RAM->mask[cnt1];
jaerts 637:ed69428d4850 231 LPC_CANAF_RAM->mask[cnt1] = buf0;
jaerts 637:ed69428d4850 232 buf0 = buf1;
jaerts 637:ed69428d4850 233 }
jaerts 637:ed69428d4850 234 }
jaerts 637:ed69428d4850 235
jaerts 637:ed69428d4850 236 /* Calculate std ID start address (buf0) and ext ID start address (buf1) */
jaerts 637:ed69428d4850 237 buf0 = ((CAN_std_cnt + 1) >> 1) << 2;
jaerts 637:ed69428d4850 238 buf1 = buf0 + (CAN_ext_cnt << 2);
jaerts 637:ed69428d4850 239
jaerts 637:ed69428d4850 240 /* Setup acceptance filter pointers */
jaerts 637:ed69428d4850 241 LPC_CANAF->SFF_sa = 0;
jaerts 637:ed69428d4850 242 LPC_CANAF->SFF_GRP_sa = buf0;
jaerts 637:ed69428d4850 243 LPC_CANAF->EFF_sa = buf0;
jaerts 637:ed69428d4850 244 LPC_CANAF->EFF_GRP_sa = buf1;
jaerts 637:ed69428d4850 245 LPC_CANAF->ENDofTable = buf1;
jaerts 637:ed69428d4850 246
jaerts 637:ed69428d4850 247 LPC_CANAF->AFMR = 0x00000000; /* Use acceptance filter */
jaerts 637:ed69428d4850 248
jaerts 637:ed69428d4850 249 return 1;
bogdanm 15:4892fe388435 250 }
bogdanm 15:4892fe388435 251
bogdanm 15:4892fe388435 252 static inline void can_irq(uint32_t icr, uint32_t index) {
bogdanm 15:4892fe388435 253 uint32_t i;
bogdanm 15:4892fe388435 254
bogdanm 15:4892fe388435 255 for(i = 0; i < 8; i++)
bogdanm 15:4892fe388435 256 {
bogdanm 15:4892fe388435 257 if((can_irq_ids[index] != 0) && (icr & (1 << i)))
bogdanm 15:4892fe388435 258 {
bogdanm 15:4892fe388435 259 switch (i) {
bogdanm 15:4892fe388435 260 case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
bogdanm 15:4892fe388435 261 case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
bogdanm 15:4892fe388435 262 case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
bogdanm 15:4892fe388435 263 case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
bogdanm 15:4892fe388435 264 case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
bogdanm 15:4892fe388435 265 case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
bogdanm 15:4892fe388435 266 case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
bogdanm 15:4892fe388435 267 case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
bogdanm 15:4892fe388435 268 case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
bogdanm 15:4892fe388435 269 }
bogdanm 15:4892fe388435 270 }
bogdanm 15:4892fe388435 271 }
bogdanm 15:4892fe388435 272 }
bogdanm 15:4892fe388435 273
bogdanm 15:4892fe388435 274 // Have to check that the CAN block is active before reading the Interrupt
bogdanm 15:4892fe388435 275 // Control Register, or the mbed hangs
bogdanm 15:4892fe388435 276 void can_irq_n() {
bogdanm 15:4892fe388435 277 uint32_t icr;
bogdanm 15:4892fe388435 278
bogdanm 15:4892fe388435 279 if(LPC_SC->PCONP & (1 << 13)) {
bogdanm 15:4892fe388435 280 icr = LPC_CAN1->ICR & 0x1FF;
bogdanm 15:4892fe388435 281 can_irq(icr, 0);
bogdanm 15:4892fe388435 282 }
bogdanm 15:4892fe388435 283
bogdanm 15:4892fe388435 284 if(LPC_SC->PCONP & (1 << 14)) {
bogdanm 15:4892fe388435 285 icr = LPC_CAN2->ICR & 0x1FF;
bogdanm 15:4892fe388435 286 can_irq(icr, 1);
bogdanm 15:4892fe388435 287 }
bogdanm 15:4892fe388435 288 }
bogdanm 15:4892fe388435 289
bogdanm 15:4892fe388435 290 // Register CAN object's irq handler
bogdanm 15:4892fe388435 291 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
bogdanm 15:4892fe388435 292 irq_handler = handler;
bogdanm 15:4892fe388435 293 can_irq_ids[obj->index] = id;
bogdanm 15:4892fe388435 294 }
bogdanm 15:4892fe388435 295
bogdanm 15:4892fe388435 296 // Unregister CAN object's irq handler
bogdanm 15:4892fe388435 297 void can_irq_free(can_t *obj) {
bogdanm 15:4892fe388435 298 obj->dev->IER &= ~(1);
bogdanm 15:4892fe388435 299 can_irq_ids[obj->index] = 0;
bogdanm 15:4892fe388435 300
bogdanm 15:4892fe388435 301 if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
bogdanm 15:4892fe388435 302 NVIC_DisableIRQ(CAN_IRQn);
bogdanm 15:4892fe388435 303 }
bogdanm 15:4892fe388435 304 }
bogdanm 15:4892fe388435 305
bogdanm 15:4892fe388435 306 // Clear or set a irq
bogdanm 15:4892fe388435 307 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
bogdanm 15:4892fe388435 308 uint32_t ier;
bogdanm 15:4892fe388435 309
bogdanm 15:4892fe388435 310 switch (type) {
bogdanm 15:4892fe388435 311 case IRQ_RX: ier = (1 << 0); break;
bogdanm 15:4892fe388435 312 case IRQ_TX: ier = (1 << 1); break;
bogdanm 15:4892fe388435 313 case IRQ_ERROR: ier = (1 << 2); break;
bogdanm 15:4892fe388435 314 case IRQ_OVERRUN: ier = (1 << 3); break;
bogdanm 15:4892fe388435 315 case IRQ_WAKEUP: ier = (1 << 4); break;
bogdanm 15:4892fe388435 316 case IRQ_PASSIVE: ier = (1 << 5); break;
bogdanm 15:4892fe388435 317 case IRQ_ARB: ier = (1 << 6); break;
bogdanm 15:4892fe388435 318 case IRQ_BUS: ier = (1 << 7); break;
bogdanm 15:4892fe388435 319 case IRQ_READY: ier = (1 << 8); break;
bogdanm 15:4892fe388435 320 default: return;
bogdanm 15:4892fe388435 321 }
bogdanm 15:4892fe388435 322
bogdanm 15:4892fe388435 323 obj->dev->MOD |= 1;
bogdanm 15:4892fe388435 324 if(enable == 0) {
bogdanm 15:4892fe388435 325 obj->dev->IER &= ~ier;
bogdanm 15:4892fe388435 326 }
bogdanm 15:4892fe388435 327 else {
bogdanm 15:4892fe388435 328 obj->dev->IER |= ier;
bogdanm 15:4892fe388435 329 }
bogdanm 15:4892fe388435 330 obj->dev->MOD &= ~(1);
bogdanm 15:4892fe388435 331
bogdanm 15:4892fe388435 332 // Enable NVIC if at least 1 interrupt is active
bogdanm 20:4263a77256ae 333 if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
bogdanm 15:4892fe388435 334 NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
bogdanm 15:4892fe388435 335 NVIC_EnableIRQ(CAN_IRQn);
bogdanm 15:4892fe388435 336 }
bogdanm 15:4892fe388435 337 else {
bogdanm 15:4892fe388435 338 NVIC_DisableIRQ(CAN_IRQn);
bogdanm 15:4892fe388435 339 }
bogdanm 15:4892fe388435 340 }
bogdanm 15:4892fe388435 341
emilmont 10:3bc89ef62ce7 342 static int can_pclk(can_t *obj) {
emilmont 10:3bc89ef62ce7 343 int value = 0;
emilmont 10:3bc89ef62ce7 344 switch ((int)obj->dev) {
emilmont 10:3bc89ef62ce7 345 case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
emilmont 10:3bc89ef62ce7 346 case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
emilmont 10:3bc89ef62ce7 347 }
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349 switch (value) {
emilmont 10:3bc89ef62ce7 350 case 1: return 1;
emilmont 10:3bc89ef62ce7 351 case 2: return 2;
emilmont 10:3bc89ef62ce7 352 case 3: return 6;
emilmont 10:3bc89ef62ce7 353 default: return 4;
emilmont 10:3bc89ef62ce7 354 }
emilmont 10:3bc89ef62ce7 355 }
emilmont 10:3bc89ef62ce7 356
emilmont 10:3bc89ef62ce7 357 // This table has the sampling points as close to 75% as possible. The first
emilmont 10:3bc89ef62ce7 358 // value is TSEG1, the second TSEG2.
emilmont 10:3bc89ef62ce7 359 static const int timing_pts[23][2] = {
emilmont 10:3bc89ef62ce7 360 {0x0, 0x0}, // 2, 50%
emilmont 10:3bc89ef62ce7 361 {0x1, 0x0}, // 3, 67%
emilmont 10:3bc89ef62ce7 362 {0x2, 0x0}, // 4, 75%
emilmont 10:3bc89ef62ce7 363 {0x3, 0x0}, // 5, 80%
emilmont 10:3bc89ef62ce7 364 {0x3, 0x1}, // 6, 67%
emilmont 10:3bc89ef62ce7 365 {0x4, 0x1}, // 7, 71%
emilmont 10:3bc89ef62ce7 366 {0x5, 0x1}, // 8, 75%
emilmont 10:3bc89ef62ce7 367 {0x6, 0x1}, // 9, 78%
emilmont 10:3bc89ef62ce7 368 {0x6, 0x2}, // 10, 70%
emilmont 10:3bc89ef62ce7 369 {0x7, 0x2}, // 11, 73%
emilmont 10:3bc89ef62ce7 370 {0x8, 0x2}, // 12, 75%
emilmont 10:3bc89ef62ce7 371 {0x9, 0x2}, // 13, 77%
emilmont 10:3bc89ef62ce7 372 {0x9, 0x3}, // 14, 71%
emilmont 10:3bc89ef62ce7 373 {0xA, 0x3}, // 15, 73%
emilmont 10:3bc89ef62ce7 374 {0xB, 0x3}, // 16, 75%
emilmont 10:3bc89ef62ce7 375 {0xC, 0x3}, // 17, 76%
emilmont 10:3bc89ef62ce7 376 {0xD, 0x3}, // 18, 78%
emilmont 10:3bc89ef62ce7 377 {0xD, 0x4}, // 19, 74%
emilmont 10:3bc89ef62ce7 378 {0xE, 0x4}, // 20, 75%
emilmont 10:3bc89ef62ce7 379 {0xF, 0x4}, // 21, 76%
emilmont 10:3bc89ef62ce7 380 {0xF, 0x5}, // 22, 73%
emilmont 10:3bc89ef62ce7 381 {0xF, 0x6}, // 23, 70%
emilmont 10:3bc89ef62ce7 382 {0xF, 0x7}, // 24, 67%
emilmont 10:3bc89ef62ce7 383 };
emilmont 10:3bc89ef62ce7 384
emilmont 10:3bc89ef62ce7 385 static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
emilmont 10:3bc89ef62ce7 386 uint32_t btr;
emilmont 10:3bc89ef62ce7 387 uint16_t brp = 0;
emilmont 10:3bc89ef62ce7 388 uint32_t calcbit;
emilmont 10:3bc89ef62ce7 389 uint32_t bitwidth;
emilmont 10:3bc89ef62ce7 390 int hit = 0;
emilmont 10:3bc89ef62ce7 391 int bits;
emilmont 10:3bc89ef62ce7 392
emilmont 10:3bc89ef62ce7 393 bitwidth = sclk / (pclk * cclk);
emilmont 10:3bc89ef62ce7 394
emilmont 10:3bc89ef62ce7 395 brp = bitwidth / 0x18;
emilmont 10:3bc89ef62ce7 396 while ((!hit) && (brp < bitwidth / 4)) {
emilmont 10:3bc89ef62ce7 397 brp++;
emilmont 10:3bc89ef62ce7 398 for (bits = 22; bits > 0; bits--) {
emilmont 10:3bc89ef62ce7 399 calcbit = (bits + 3) * (brp + 1);
emilmont 10:3bc89ef62ce7 400 if (calcbit == bitwidth) {
emilmont 10:3bc89ef62ce7 401 hit = 1;
emilmont 10:3bc89ef62ce7 402 break;
emilmont 10:3bc89ef62ce7 403 }
emilmont 10:3bc89ef62ce7 404 }
emilmont 10:3bc89ef62ce7 405 }
emilmont 10:3bc89ef62ce7 406
emilmont 10:3bc89ef62ce7 407 if (hit) {
emilmont 10:3bc89ef62ce7 408 btr = ((timing_pts[bits][1] << 20) & 0x00700000)
emilmont 10:3bc89ef62ce7 409 | ((timing_pts[bits][0] << 16) & 0x000F0000)
emilmont 10:3bc89ef62ce7 410 | ((psjw << 14) & 0x0000C000)
emilmont 10:3bc89ef62ce7 411 | ((brp << 0) & 0x000003FF);
emilmont 10:3bc89ef62ce7 412 } else {
emilmont 10:3bc89ef62ce7 413 btr = 0xFFFFFFFF;
emilmont 10:3bc89ef62ce7 414 }
emilmont 10:3bc89ef62ce7 415
emilmont 10:3bc89ef62ce7 416 return btr;
emilmont 10:3bc89ef62ce7 417
emilmont 10:3bc89ef62ce7 418 }
emilmont 10:3bc89ef62ce7 419
emilmont 10:3bc89ef62ce7 420 void can_init(can_t *obj, PinName rd, PinName td) {
emilmont 10:3bc89ef62ce7 421 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
emilmont 10:3bc89ef62ce7 422 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
emilmont 10:3bc89ef62ce7 423 obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
mbed_official 227:7bd0639b8911 424 MBED_ASSERT((int)obj->dev != NC);
emilmont 10:3bc89ef62ce7 425
emilmont 10:3bc89ef62ce7 426 switch ((int)obj->dev) {
emilmont 10:3bc89ef62ce7 427 case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
emilmont 10:3bc89ef62ce7 428 case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
emilmont 10:3bc89ef62ce7 429 }
emilmont 10:3bc89ef62ce7 430
emilmont 10:3bc89ef62ce7 431 pinmap_pinout(rd, PinMap_CAN_RD);
emilmont 10:3bc89ef62ce7 432 pinmap_pinout(td, PinMap_CAN_TD);
bogdanm 15:4892fe388435 433
bogdanm 15:4892fe388435 434 switch ((int)obj->dev) {
bogdanm 15:4892fe388435 435 case CAN_1: obj->index = 0; break;
bogdanm 15:4892fe388435 436 case CAN_2: obj->index = 1; break;
bogdanm 15:4892fe388435 437 }
bogdanm 15:4892fe388435 438
emilmont 10:3bc89ef62ce7 439 can_reset(obj);
emilmont 10:3bc89ef62ce7 440 obj->dev->IER = 0; // Disable Interrupts
emilmont 10:3bc89ef62ce7 441 can_frequency(obj, 100000);
emilmont 10:3bc89ef62ce7 442
emilmont 10:3bc89ef62ce7 443 LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
emilmont 10:3bc89ef62ce7 444 }
emilmont 10:3bc89ef62ce7 445
emilmont 10:3bc89ef62ce7 446 void can_free(can_t *obj) {
emilmont 10:3bc89ef62ce7 447 switch ((int)obj->dev) {
emilmont 10:3bc89ef62ce7 448 case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
emilmont 10:3bc89ef62ce7 449 case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
emilmont 10:3bc89ef62ce7 450 }
emilmont 10:3bc89ef62ce7 451 }
emilmont 10:3bc89ef62ce7 452
emilmont 10:3bc89ef62ce7 453 int can_frequency(can_t *obj, int f) {
emilmont 10:3bc89ef62ce7 454 int pclk = can_pclk(obj);
emilmont 10:3bc89ef62ce7 455
emilmont 10:3bc89ef62ce7 456 int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
emilmont 10:3bc89ef62ce7 457
emilmont 10:3bc89ef62ce7 458 if (btr > 0) {
emilmont 10:3bc89ef62ce7 459 uint32_t modmask = can_disable(obj);
emilmont 10:3bc89ef62ce7 460 obj->dev->BTR = btr;
emilmont 10:3bc89ef62ce7 461 obj->dev->MOD = modmask;
emilmont 10:3bc89ef62ce7 462 return 1;
emilmont 10:3bc89ef62ce7 463 } else {
emilmont 10:3bc89ef62ce7 464 return 0;
emilmont 10:3bc89ef62ce7 465 }
emilmont 10:3bc89ef62ce7 466 }
emilmont 10:3bc89ef62ce7 467
emilmont 10:3bc89ef62ce7 468 int can_write(can_t *obj, CAN_Message msg, int cc) {
emilmont 10:3bc89ef62ce7 469 unsigned int CANStatus;
emilmont 10:3bc89ef62ce7 470 CANMsg m;
emilmont 10:3bc89ef62ce7 471
emilmont 10:3bc89ef62ce7 472 can_enable(obj);
emilmont 10:3bc89ef62ce7 473
emilmont 10:3bc89ef62ce7 474 m.id = msg.id ;
emilmont 10:3bc89ef62ce7 475 m.dlc = msg.len & 0xF;
emilmont 10:3bc89ef62ce7 476 m.rtr = msg.type;
emilmont 10:3bc89ef62ce7 477 m.type = msg.format;
emilmont 10:3bc89ef62ce7 478 memcpy(m.data, msg.data, msg.len);
emilmont 10:3bc89ef62ce7 479 const unsigned int *buf = (const unsigned int *)&m;
emilmont 10:3bc89ef62ce7 480
emilmont 10:3bc89ef62ce7 481 CANStatus = obj->dev->SR;
mbed_official 530:2939f5396008 482
mbed_official 530:2939f5396008 483 // Send the message to ourself if in a test mode
mbed_official 530:2939f5396008 484 if (obj->dev->MOD & 0x04) {
mbed_official 530:2939f5396008 485 cc = 1;
mbed_official 530:2939f5396008 486 }
mbed_official 530:2939f5396008 487
emilmont 10:3bc89ef62ce7 488 if (CANStatus & 0x00000004) {
emilmont 10:3bc89ef62ce7 489 obj->dev->TFI1 = buf[0] & 0xC00F0000;
emilmont 10:3bc89ef62ce7 490 obj->dev->TID1 = buf[1];
emilmont 10:3bc89ef62ce7 491 obj->dev->TDA1 = buf[2];
emilmont 10:3bc89ef62ce7 492 obj->dev->TDB1 = buf[3];
emilmont 10:3bc89ef62ce7 493 if(cc) {
emilmont 10:3bc89ef62ce7 494 obj->dev->CMR = 0x30;
emilmont 10:3bc89ef62ce7 495 } else {
emilmont 10:3bc89ef62ce7 496 obj->dev->CMR = 0x21;
emilmont 10:3bc89ef62ce7 497 }
emilmont 10:3bc89ef62ce7 498 return 1;
emilmont 10:3bc89ef62ce7 499
emilmont 10:3bc89ef62ce7 500 } else if (CANStatus & 0x00000400) {
emilmont 10:3bc89ef62ce7 501 obj->dev->TFI2 = buf[0] & 0xC00F0000;
emilmont 10:3bc89ef62ce7 502 obj->dev->TID2 = buf[1];
emilmont 10:3bc89ef62ce7 503 obj->dev->TDA2 = buf[2];
emilmont 10:3bc89ef62ce7 504 obj->dev->TDB2 = buf[3];
emilmont 10:3bc89ef62ce7 505 if (cc) {
emilmont 10:3bc89ef62ce7 506 obj->dev->CMR = 0x50;
emilmont 10:3bc89ef62ce7 507 } else {
emilmont 10:3bc89ef62ce7 508 obj->dev->CMR = 0x41;
emilmont 10:3bc89ef62ce7 509 }
emilmont 10:3bc89ef62ce7 510 return 1;
emilmont 10:3bc89ef62ce7 511
emilmont 10:3bc89ef62ce7 512 } else if (CANStatus & 0x00040000) {
emilmont 10:3bc89ef62ce7 513 obj->dev->TFI3 = buf[0] & 0xC00F0000;
emilmont 10:3bc89ef62ce7 514 obj->dev->TID3 = buf[1];
emilmont 10:3bc89ef62ce7 515 obj->dev->TDA3 = buf[2];
emilmont 10:3bc89ef62ce7 516 obj->dev->TDB3 = buf[3];
emilmont 10:3bc89ef62ce7 517 if (cc) {
emilmont 10:3bc89ef62ce7 518 obj->dev->CMR = 0x90;
emilmont 10:3bc89ef62ce7 519 } else {
emilmont 10:3bc89ef62ce7 520 obj->dev->CMR = 0x81;
emilmont 10:3bc89ef62ce7 521 }
emilmont 10:3bc89ef62ce7 522 return 1;
emilmont 10:3bc89ef62ce7 523 }
emilmont 10:3bc89ef62ce7 524
emilmont 10:3bc89ef62ce7 525 return 0;
emilmont 10:3bc89ef62ce7 526 }
emilmont 10:3bc89ef62ce7 527
mbed_official 41:e8b66477f5bf 528 int can_read(can_t *obj, CAN_Message *msg, int handle) {
emilmont 10:3bc89ef62ce7 529 CANMsg x;
emilmont 10:3bc89ef62ce7 530 unsigned int *i = (unsigned int *)&x;
emilmont 10:3bc89ef62ce7 531
emilmont 10:3bc89ef62ce7 532 can_enable(obj);
emilmont 10:3bc89ef62ce7 533
emilmont 10:3bc89ef62ce7 534 if (obj->dev->GSR & 0x1) {
emilmont 10:3bc89ef62ce7 535 *i++ = obj->dev->RFS; // Frame
emilmont 10:3bc89ef62ce7 536 *i++ = obj->dev->RID; // ID
emilmont 10:3bc89ef62ce7 537 *i++ = obj->dev->RDA; // Data A
emilmont 10:3bc89ef62ce7 538 *i++ = obj->dev->RDB; // Data B
emilmont 10:3bc89ef62ce7 539 obj->dev->CMR = 0x04; // release receive buffer
emilmont 10:3bc89ef62ce7 540
emilmont 10:3bc89ef62ce7 541 msg->id = x.id;
emilmont 10:3bc89ef62ce7 542 msg->len = x.dlc;
emilmont 10:3bc89ef62ce7 543 msg->format = (x.type)? CANExtended : CANStandard;
emilmont 10:3bc89ef62ce7 544 msg->type = (x.rtr)? CANRemote: CANData;
emilmont 10:3bc89ef62ce7 545 memcpy(msg->data,x.data,x.dlc);
emilmont 10:3bc89ef62ce7 546 return 1;
emilmont 10:3bc89ef62ce7 547 }
emilmont 10:3bc89ef62ce7 548
emilmont 10:3bc89ef62ce7 549 return 0;
emilmont 10:3bc89ef62ce7 550 }
emilmont 10:3bc89ef62ce7 551
emilmont 10:3bc89ef62ce7 552 void can_reset(can_t *obj) {
emilmont 10:3bc89ef62ce7 553 can_disable(obj);
emilmont 10:3bc89ef62ce7 554 obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
emilmont 10:3bc89ef62ce7 555 }
emilmont 10:3bc89ef62ce7 556
emilmont 10:3bc89ef62ce7 557 unsigned char can_rderror(can_t *obj) {
emilmont 10:3bc89ef62ce7 558 return (obj->dev->GSR >> 16) & 0xFF;
emilmont 10:3bc89ef62ce7 559 }
emilmont 10:3bc89ef62ce7 560
emilmont 10:3bc89ef62ce7 561 unsigned char can_tderror(can_t *obj) {
emilmont 10:3bc89ef62ce7 562 return (obj->dev->GSR >> 24) & 0xFF;
emilmont 10:3bc89ef62ce7 563 }
emilmont 10:3bc89ef62ce7 564
emilmont 10:3bc89ef62ce7 565 void can_monitor(can_t *obj, int silent) {
emilmont 10:3bc89ef62ce7 566 uint32_t mod_mask = can_disable(obj);
emilmont 10:3bc89ef62ce7 567 if (silent) {
emilmont 10:3bc89ef62ce7 568 obj->dev->MOD |= (1 << 1);
emilmont 10:3bc89ef62ce7 569 } else {
emilmont 10:3bc89ef62ce7 570 obj->dev->MOD &= ~(1 << 1);
emilmont 10:3bc89ef62ce7 571 }
emilmont 10:3bc89ef62ce7 572 if (!(mod_mask & 1)) {
emilmont 10:3bc89ef62ce7 573 can_enable(obj);
emilmont 10:3bc89ef62ce7 574 }
emilmont 10:3bc89ef62ce7 575 }