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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h@632:7687fb9c4f91, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 14:00:11 2015 +0100
Revision:: 632:7687fb9c4f91
Parent:: 385:be64abf45658
Child:: 634:ac7d6880524d

Synchronized with git revision f7ce4ed029cc611121464252ff28d5e8beb895b0

Full URL: https://github.com/mbedmicro/mbed/commit/f7ce4ed029cc611121464252ff28d5e8beb895b0/

NUCLEO_F303K8 - add support of the STM32F303K8

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	330:c80ac197fa6a	1	/**
mbed_official	330:c80ac197fa6a	2	******************************************************************************
mbed_official	330:c80ac197fa6a	3	* @file stm32f3xx_hal_rcc_ex.h
mbed_official	330:c80ac197fa6a	4	* @author MCD Application Team
mbed_official	632:7687fb9c4f91	5	* @version V1.1.1
mbed_official	632:7687fb9c4f91	6	* @date 19-June-2015
mbed_official	330:c80ac197fa6a	7	* @brief Header file of RCC HAL Extended module.
mbed_official	330:c80ac197fa6a	8	******************************************************************************
mbed_official	330:c80ac197fa6a	9	* @attention
mbed_official	330:c80ac197fa6a	10	*
mbed_official	632:7687fb9c4f91	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	330:c80ac197fa6a	12	*
mbed_official	330:c80ac197fa6a	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	330:c80ac197fa6a	14	* are permitted provided that the following conditions are met:
mbed_official	330:c80ac197fa6a	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	330:c80ac197fa6a	16	* this list of conditions and the following disclaimer.
mbed_official	330:c80ac197fa6a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	330:c80ac197fa6a	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	330:c80ac197fa6a	19	* and/or other materials provided with the distribution.
mbed_official	330:c80ac197fa6a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	330:c80ac197fa6a	21	* may be used to endorse or promote products derived from this software
mbed_official	330:c80ac197fa6a	22	* without specific prior written permission.
mbed_official	330:c80ac197fa6a	23	*
mbed_official	330:c80ac197fa6a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	330:c80ac197fa6a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	330:c80ac197fa6a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	330:c80ac197fa6a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	330:c80ac197fa6a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	330:c80ac197fa6a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	330:c80ac197fa6a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	330:c80ac197fa6a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	330:c80ac197fa6a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	330:c80ac197fa6a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	330:c80ac197fa6a	34	*
mbed_official	330:c80ac197fa6a	35	******************************************************************************
mbed_official	330:c80ac197fa6a	36	*/
mbed_official	330:c80ac197fa6a	37
mbed_official	330:c80ac197fa6a	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	330:c80ac197fa6a	39	#ifndef __STM32F3xx_HAL_RCC_EX_H
mbed_official	330:c80ac197fa6a	40	#define __STM32F3xx_HAL_RCC_EX_H
mbed_official	330:c80ac197fa6a	41
mbed_official	330:c80ac197fa6a	42	#ifdef __cplusplus
mbed_official	330:c80ac197fa6a	43	extern "C" {
mbed_official	330:c80ac197fa6a	44	#endif
mbed_official	330:c80ac197fa6a	45
mbed_official	330:c80ac197fa6a	46	/* Includes ------------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	47	#include "stm32f3xx_hal_def.h"
mbed_official	330:c80ac197fa6a	48
mbed_official	330:c80ac197fa6a	49	/** @addtogroup STM32F3xx_HAL_Driver
mbed_official	330:c80ac197fa6a	50	* @{
mbed_official	330:c80ac197fa6a	51	*/
mbed_official	330:c80ac197fa6a	52
mbed_official	330:c80ac197fa6a	53	/** @addtogroup RCCEx
mbed_official	330:c80ac197fa6a	54	* @{
mbed_official	330:c80ac197fa6a	55	*/
mbed_official	330:c80ac197fa6a	56
mbed_official	330:c80ac197fa6a	57	/* Exported types ------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	58
mbed_official	330:c80ac197fa6a	59	/** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
mbed_official	330:c80ac197fa6a	60	* @{
mbed_official	330:c80ac197fa6a	61	*/
mbed_official	330:c80ac197fa6a	62	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	63	/**
mbed_official	330:c80ac197fa6a	64	* @brief RCC PLL configuration structure definition
mbed_official	330:c80ac197fa6a	65	*/
mbed_official	330:c80ac197fa6a	66	typedef struct
mbed_official	330:c80ac197fa6a	67	{
mbed_official	330:c80ac197fa6a	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
mbed_official	330:c80ac197fa6a	69	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	330:c80ac197fa6a	70
mbed_official	330:c80ac197fa6a	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	330:c80ac197fa6a	72	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
mbed_official	330:c80ac197fa6a	73
mbed_official	330:c80ac197fa6a	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
mbed_official	330:c80ac197fa6a	76
mbed_official	330:c80ac197fa6a	77	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	78	This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
mbed_official	330:c80ac197fa6a	79
mbed_official	330:c80ac197fa6a	80	}RCC_PLLInitTypeDef;
mbed_official	330:c80ac197fa6a	81
mbed_official	330:c80ac197fa6a	82	/**
mbed_official	330:c80ac197fa6a	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	330:c80ac197fa6a	84	*/
mbed_official	330:c80ac197fa6a	85	typedef struct
mbed_official	330:c80ac197fa6a	86	{
mbed_official	330:c80ac197fa6a	87	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	330:c80ac197fa6a	88	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	330:c80ac197fa6a	89
mbed_official	330:c80ac197fa6a	90	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	330:c80ac197fa6a	91	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	330:c80ac197fa6a	92
mbed_official	330:c80ac197fa6a	93	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	330:c80ac197fa6a	94	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	330:c80ac197fa6a	95
mbed_official	330:c80ac197fa6a	96	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	330:c80ac197fa6a	97	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	330:c80ac197fa6a	98
mbed_official	330:c80ac197fa6a	99	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	330:c80ac197fa6a	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	330:c80ac197fa6a	101
mbed_official	330:c80ac197fa6a	102	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	330:c80ac197fa6a	103	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	330:c80ac197fa6a	104
mbed_official	330:c80ac197fa6a	105	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	330:c80ac197fa6a	106
mbed_official	330:c80ac197fa6a	107	}RCC_OscInitTypeDef;
mbed_official	330:c80ac197fa6a	108
mbed_official	330:c80ac197fa6a	109	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	110
mbed_official	330:c80ac197fa6a	111	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	112	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	113	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	330:c80ac197fa6a	114	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	115	/**
mbed_official	330:c80ac197fa6a	116	* @brief RCC PLL configuration structure definition
mbed_official	330:c80ac197fa6a	117	*/
mbed_official	330:c80ac197fa6a	118	typedef struct
mbed_official	330:c80ac197fa6a	119	{
mbed_official	330:c80ac197fa6a	120	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
mbed_official	330:c80ac197fa6a	121	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	330:c80ac197fa6a	122
mbed_official	330:c80ac197fa6a	123	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	330:c80ac197fa6a	124	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
mbed_official	330:c80ac197fa6a	125
mbed_official	330:c80ac197fa6a	126	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	127	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
mbed_official	330:c80ac197fa6a	128
mbed_official	330:c80ac197fa6a	129	}RCC_PLLInitTypeDef;
mbed_official	330:c80ac197fa6a	130
mbed_official	330:c80ac197fa6a	131	/**
mbed_official	330:c80ac197fa6a	132	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	330:c80ac197fa6a	133	*/
mbed_official	330:c80ac197fa6a	134	typedef struct
mbed_official	330:c80ac197fa6a	135	{
mbed_official	330:c80ac197fa6a	136	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	330:c80ac197fa6a	137	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	330:c80ac197fa6a	138
mbed_official	330:c80ac197fa6a	139	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	330:c80ac197fa6a	140	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	330:c80ac197fa6a	141
mbed_official	330:c80ac197fa6a	142	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
mbed_official	330:c80ac197fa6a	143	This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
mbed_official	330:c80ac197fa6a	144
mbed_official	330:c80ac197fa6a	145	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	330:c80ac197fa6a	146	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	330:c80ac197fa6a	147
mbed_official	330:c80ac197fa6a	148	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	330:c80ac197fa6a	149	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	330:c80ac197fa6a	150
mbed_official	330:c80ac197fa6a	151	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	330:c80ac197fa6a	152	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	330:c80ac197fa6a	153
mbed_official	330:c80ac197fa6a	154	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	330:c80ac197fa6a	155	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	330:c80ac197fa6a	156
mbed_official	330:c80ac197fa6a	157	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	330:c80ac197fa6a	158
mbed_official	330:c80ac197fa6a	159	}RCC_OscInitTypeDef;
mbed_official	330:c80ac197fa6a	160	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	161	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	162	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	163	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	164
mbed_official	330:c80ac197fa6a	165	/**
mbed_official	330:c80ac197fa6a	166	* @brief RCC extended clocks structure definition
mbed_official	330:c80ac197fa6a	167	*/
mbed_official	330:c80ac197fa6a	168	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	169	typedef struct
mbed_official	330:c80ac197fa6a	170	{
mbed_official	330:c80ac197fa6a	171	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	172	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	173
mbed_official	330:c80ac197fa6a	174	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	175	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	176
mbed_official	330:c80ac197fa6a	177	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	178	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	179
mbed_official	330:c80ac197fa6a	180	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	181	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	182
mbed_official	330:c80ac197fa6a	183	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	184	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	185
mbed_official	330:c80ac197fa6a	186	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	187	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	188
mbed_official	330:c80ac197fa6a	189	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	190	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	191
mbed_official	330:c80ac197fa6a	192	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	330:c80ac197fa6a	193	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	330:c80ac197fa6a	194
mbed_official	330:c80ac197fa6a	195	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	330:c80ac197fa6a	196	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	330:c80ac197fa6a	197
mbed_official	330:c80ac197fa6a	198	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	199	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	200
mbed_official	330:c80ac197fa6a	201	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	202	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	203
mbed_official	330:c80ac197fa6a	204	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	330:c80ac197fa6a	205	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	330:c80ac197fa6a	206
mbed_official	330:c80ac197fa6a	207	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	330:c80ac197fa6a	208	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	330:c80ac197fa6a	209
mbed_official	330:c80ac197fa6a	210	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	330:c80ac197fa6a	211	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	330:c80ac197fa6a	212	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	213	#endif /* STM32F301x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	214
mbed_official	330:c80ac197fa6a	215	#if defined(STM32F302x8)
mbed_official	330:c80ac197fa6a	216	typedef struct
mbed_official	330:c80ac197fa6a	217	{
mbed_official	330:c80ac197fa6a	218	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	219	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	220
mbed_official	330:c80ac197fa6a	221	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	222	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	223
mbed_official	330:c80ac197fa6a	224	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	225	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	226
mbed_official	330:c80ac197fa6a	227	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	228	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	229
mbed_official	330:c80ac197fa6a	230	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	231	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	232
mbed_official	330:c80ac197fa6a	233	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	234	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	235
mbed_official	330:c80ac197fa6a	236	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	237	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	238
mbed_official	330:c80ac197fa6a	239	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	330:c80ac197fa6a	240	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	330:c80ac197fa6a	241
mbed_official	330:c80ac197fa6a	242	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	330:c80ac197fa6a	243	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	330:c80ac197fa6a	244
mbed_official	330:c80ac197fa6a	245	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	246	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	247
mbed_official	330:c80ac197fa6a	248	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	249	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	250
mbed_official	330:c80ac197fa6a	251	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	330:c80ac197fa6a	252	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	330:c80ac197fa6a	253
mbed_official	330:c80ac197fa6a	254	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	330:c80ac197fa6a	255	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	330:c80ac197fa6a	256
mbed_official	330:c80ac197fa6a	257	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	330:c80ac197fa6a	258	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	330:c80ac197fa6a	259
mbed_official	330:c80ac197fa6a	260	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	261	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	262
mbed_official	330:c80ac197fa6a	263	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	264	#endif /* STM32F302x8 */
mbed_official	330:c80ac197fa6a	265
mbed_official	330:c80ac197fa6a	266	#if defined(STM32F302xC)
mbed_official	330:c80ac197fa6a	267	typedef struct
mbed_official	330:c80ac197fa6a	268	{
mbed_official	330:c80ac197fa6a	269	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	270	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	271
mbed_official	330:c80ac197fa6a	272	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	273	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	274
mbed_official	330:c80ac197fa6a	275	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	276	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	277
mbed_official	330:c80ac197fa6a	278	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	279	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	280
mbed_official	330:c80ac197fa6a	281	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	282	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	283
mbed_official	330:c80ac197fa6a	284	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	285	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	286
mbed_official	330:c80ac197fa6a	287	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	288	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	289
mbed_official	330:c80ac197fa6a	290	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	291	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	292
mbed_official	330:c80ac197fa6a	293	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	294	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	295
mbed_official	330:c80ac197fa6a	296	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	297	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	298
mbed_official	330:c80ac197fa6a	299	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	300	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	301
mbed_official	330:c80ac197fa6a	302	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	303	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	304
mbed_official	330:c80ac197fa6a	305	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	306	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	307
mbed_official	330:c80ac197fa6a	308	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	309	#endif /* STM32F302xC */
mbed_official	330:c80ac197fa6a	310
mbed_official	330:c80ac197fa6a	311	#if defined(STM32F303xC)
mbed_official	330:c80ac197fa6a	312	typedef struct
mbed_official	330:c80ac197fa6a	313	{
mbed_official	330:c80ac197fa6a	314	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	315	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	316
mbed_official	330:c80ac197fa6a	317	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	318	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	319
mbed_official	330:c80ac197fa6a	320	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	321	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	322
mbed_official	330:c80ac197fa6a	323	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	324	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	325
mbed_official	330:c80ac197fa6a	326	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	327	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	328
mbed_official	330:c80ac197fa6a	329	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	330	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	331
mbed_official	330:c80ac197fa6a	332	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	333	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	334
mbed_official	330:c80ac197fa6a	335	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	336	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	337
mbed_official	330:c80ac197fa6a	338	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	339	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	340
mbed_official	330:c80ac197fa6a	341	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	342	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	343
mbed_official	330:c80ac197fa6a	344	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	330:c80ac197fa6a	345	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	330:c80ac197fa6a	346
mbed_official	330:c80ac197fa6a	347	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	348	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	349
mbed_official	330:c80ac197fa6a	350	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	351	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	352
mbed_official	330:c80ac197fa6a	353	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	330:c80ac197fa6a	354	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	330:c80ac197fa6a	355
mbed_official	330:c80ac197fa6a	356	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	357	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	358
mbed_official	330:c80ac197fa6a	359	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	360	#endif /* STM32F303xC */
mbed_official	330:c80ac197fa6a	361
mbed_official	330:c80ac197fa6a	362	#if defined(STM32F302xE)
mbed_official	330:c80ac197fa6a	363	typedef struct
mbed_official	330:c80ac197fa6a	364	{
mbed_official	330:c80ac197fa6a	365	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	366	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	367
mbed_official	330:c80ac197fa6a	368	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	369	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	370
mbed_official	330:c80ac197fa6a	371	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	372	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	373
mbed_official	330:c80ac197fa6a	374	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	375	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	376
mbed_official	330:c80ac197fa6a	377	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	378	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	379
mbed_official	330:c80ac197fa6a	380	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	381	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	382
mbed_official	330:c80ac197fa6a	383	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	384	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	385
mbed_official	330:c80ac197fa6a	386	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	387	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	388
mbed_official	330:c80ac197fa6a	389	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	390	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	391
mbed_official	330:c80ac197fa6a	392	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	330:c80ac197fa6a	393	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	330:c80ac197fa6a	394
mbed_official	330:c80ac197fa6a	395	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	396	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	397
mbed_official	330:c80ac197fa6a	398	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	399	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	400
mbed_official	330:c80ac197fa6a	401	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	402	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	403
mbed_official	330:c80ac197fa6a	404	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
mbed_official	330:c80ac197fa6a	405	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
mbed_official	330:c80ac197fa6a	406
mbed_official	330:c80ac197fa6a	407	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
mbed_official	330:c80ac197fa6a	408	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
mbed_official	330:c80ac197fa6a	409
mbed_official	330:c80ac197fa6a	410	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	330:c80ac197fa6a	411	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	330:c80ac197fa6a	412
mbed_official	330:c80ac197fa6a	413	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	330:c80ac197fa6a	414	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	330:c80ac197fa6a	415
mbed_official	330:c80ac197fa6a	416	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	330:c80ac197fa6a	417	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	330:c80ac197fa6a	418
mbed_official	330:c80ac197fa6a	419	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	420	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	421
mbed_official	330:c80ac197fa6a	422	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	423	#endif /* STM32F302xE */
mbed_official	330:c80ac197fa6a	424
mbed_official	330:c80ac197fa6a	425	#if defined(STM32F303xE)
mbed_official	330:c80ac197fa6a	426	typedef struct
mbed_official	330:c80ac197fa6a	427	{
mbed_official	330:c80ac197fa6a	428	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	429	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	430
mbed_official	330:c80ac197fa6a	431	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	432	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	433
mbed_official	330:c80ac197fa6a	434	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	435	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	436
mbed_official	330:c80ac197fa6a	437	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	438	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	439
mbed_official	330:c80ac197fa6a	440	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	441	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	442
mbed_official	330:c80ac197fa6a	443	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	444	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	445
mbed_official	330:c80ac197fa6a	446	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	447	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	448
mbed_official	330:c80ac197fa6a	449	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	450	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	451
mbed_official	330:c80ac197fa6a	452	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	453	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	454
mbed_official	330:c80ac197fa6a	455	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	330:c80ac197fa6a	456	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	330:c80ac197fa6a	457
mbed_official	330:c80ac197fa6a	458	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	459	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	460
mbed_official	330:c80ac197fa6a	461	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	330:c80ac197fa6a	462	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	330:c80ac197fa6a	463
mbed_official	330:c80ac197fa6a	464	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	465	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	466
mbed_official	330:c80ac197fa6a	467	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	468	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	469
mbed_official	330:c80ac197fa6a	470	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
mbed_official	330:c80ac197fa6a	471	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
mbed_official	330:c80ac197fa6a	472
mbed_official	330:c80ac197fa6a	473	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
mbed_official	330:c80ac197fa6a	474	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
mbed_official	330:c80ac197fa6a	475
mbed_official	330:c80ac197fa6a	476	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	330:c80ac197fa6a	477	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	330:c80ac197fa6a	478
mbed_official	330:c80ac197fa6a	479	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	330:c80ac197fa6a	480	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	330:c80ac197fa6a	481
mbed_official	330:c80ac197fa6a	482	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	330:c80ac197fa6a	483	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	330:c80ac197fa6a	484
mbed_official	330:c80ac197fa6a	485	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	330:c80ac197fa6a	486	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	330:c80ac197fa6a	487
mbed_official	330:c80ac197fa6a	488	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
mbed_official	330:c80ac197fa6a	489	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
mbed_official	330:c80ac197fa6a	490
mbed_official	330:c80ac197fa6a	491	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	492	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	493
mbed_official	330:c80ac197fa6a	494	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	495	#endif /* STM32F303xE */
mbed_official	330:c80ac197fa6a	496
mbed_official	330:c80ac197fa6a	497	#if defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	498	typedef struct
mbed_official	330:c80ac197fa6a	499	{
mbed_official	330:c80ac197fa6a	500	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	501	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	502
mbed_official	330:c80ac197fa6a	503	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	504	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	505
mbed_official	330:c80ac197fa6a	506	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	507	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	508
mbed_official	330:c80ac197fa6a	509	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	510	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	511
mbed_official	330:c80ac197fa6a	512	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	513	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	514
mbed_official	330:c80ac197fa6a	515	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	516	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	517
mbed_official	330:c80ac197fa6a	518	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	519	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	520
mbed_official	330:c80ac197fa6a	521	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	522	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	523
mbed_official	330:c80ac197fa6a	524	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	525	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	526
mbed_official	330:c80ac197fa6a	527	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	330:c80ac197fa6a	528	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	330:c80ac197fa6a	529
mbed_official	330:c80ac197fa6a	530	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	531	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	532
mbed_official	330:c80ac197fa6a	533	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	330:c80ac197fa6a	534	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	330:c80ac197fa6a	535
mbed_official	330:c80ac197fa6a	536	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	537	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	538
mbed_official	330:c80ac197fa6a	539	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	540	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	541
mbed_official	330:c80ac197fa6a	542	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
mbed_official	330:c80ac197fa6a	543	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
mbed_official	330:c80ac197fa6a	544
mbed_official	330:c80ac197fa6a	545	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
mbed_official	330:c80ac197fa6a	546	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
mbed_official	330:c80ac197fa6a	547
mbed_official	330:c80ac197fa6a	548	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	330:c80ac197fa6a	549	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	330:c80ac197fa6a	550
mbed_official	330:c80ac197fa6a	551	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	330:c80ac197fa6a	552	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	330:c80ac197fa6a	553
mbed_official	330:c80ac197fa6a	554	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	330:c80ac197fa6a	555	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	330:c80ac197fa6a	556
mbed_official	330:c80ac197fa6a	557	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	330:c80ac197fa6a	558	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	330:c80ac197fa6a	559
mbed_official	330:c80ac197fa6a	560	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
mbed_official	330:c80ac197fa6a	561	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
mbed_official	330:c80ac197fa6a	562
mbed_official	330:c80ac197fa6a	563	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	564	#endif /* STM32F398xx */
mbed_official	330:c80ac197fa6a	565
mbed_official	330:c80ac197fa6a	566	#if defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	567	typedef struct
mbed_official	330:c80ac197fa6a	568	{
mbed_official	330:c80ac197fa6a	569	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	570	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	571
mbed_official	330:c80ac197fa6a	572	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	573	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	574
mbed_official	330:c80ac197fa6a	575	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	576	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	577
mbed_official	330:c80ac197fa6a	578	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	579	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	580
mbed_official	330:c80ac197fa6a	581	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	582	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	583
mbed_official	330:c80ac197fa6a	584	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	330:c80ac197fa6a	585	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	330:c80ac197fa6a	586
mbed_official	330:c80ac197fa6a	587	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	330:c80ac197fa6a	588	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	330:c80ac197fa6a	589
mbed_official	330:c80ac197fa6a	590	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	591	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	592
mbed_official	330:c80ac197fa6a	593	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	594	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	595
mbed_official	330:c80ac197fa6a	596	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	597	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	598
mbed_official	330:c80ac197fa6a	599	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	330:c80ac197fa6a	600	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	330:c80ac197fa6a	601
mbed_official	330:c80ac197fa6a	602	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	330:c80ac197fa6a	603	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	330:c80ac197fa6a	604
mbed_official	330:c80ac197fa6a	605	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	606	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	607
mbed_official	330:c80ac197fa6a	608	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	330:c80ac197fa6a	609	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	330:c80ac197fa6a	610
mbed_official	330:c80ac197fa6a	611	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	612	#endif /* STM32F358xx */
mbed_official	330:c80ac197fa6a	613
mbed_official	330:c80ac197fa6a	614	#if defined(STM32F303x8)
mbed_official	330:c80ac197fa6a	615	typedef struct
mbed_official	330:c80ac197fa6a	616	{
mbed_official	330:c80ac197fa6a	617	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	618	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	619
mbed_official	330:c80ac197fa6a	620	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	621	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	622
mbed_official	330:c80ac197fa6a	623	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	624	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	625
mbed_official	330:c80ac197fa6a	626	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	627	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	628
mbed_official	330:c80ac197fa6a	629	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	630	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	631
mbed_official	330:c80ac197fa6a	632	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	633	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	634
mbed_official	330:c80ac197fa6a	635	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	636	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	637
mbed_official	330:c80ac197fa6a	638	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	639	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	640
mbed_official	330:c80ac197fa6a	641	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	642	#endif /* STM32F303x8 */
mbed_official	330:c80ac197fa6a	643
mbed_official	330:c80ac197fa6a	644	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	645	typedef struct
mbed_official	330:c80ac197fa6a	646	{
mbed_official	330:c80ac197fa6a	647	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	648	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	649
mbed_official	330:c80ac197fa6a	650	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	651	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	652
mbed_official	330:c80ac197fa6a	653	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	654	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	655
mbed_official	330:c80ac197fa6a	656	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	657	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	658
mbed_official	330:c80ac197fa6a	659	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	660	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	661
mbed_official	330:c80ac197fa6a	662	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	663	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	664
mbed_official	330:c80ac197fa6a	665	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	666	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	667
mbed_official	330:c80ac197fa6a	668	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	669	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	670
mbed_official	330:c80ac197fa6a	671	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
mbed_official	330:c80ac197fa6a	672	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	673
mbed_official	330:c80ac197fa6a	674	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	675	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	676
mbed_official	330:c80ac197fa6a	677	#if defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	678	typedef struct
mbed_official	330:c80ac197fa6a	679	{
mbed_official	330:c80ac197fa6a	680	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	681	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	682
mbed_official	330:c80ac197fa6a	683	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	684	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	685
mbed_official	330:c80ac197fa6a	686	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	687	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	688
mbed_official	330:c80ac197fa6a	689	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	690	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	691
mbed_official	330:c80ac197fa6a	692	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	693	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	694
mbed_official	330:c80ac197fa6a	695	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	696	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	697
mbed_official	330:c80ac197fa6a	698	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	330:c80ac197fa6a	699	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	330:c80ac197fa6a	700
mbed_official	330:c80ac197fa6a	701	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	330:c80ac197fa6a	702	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	330:c80ac197fa6a	703
mbed_official	330:c80ac197fa6a	704	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	705	#endif /* STM32F328xx */
mbed_official	330:c80ac197fa6a	706
mbed_official	330:c80ac197fa6a	707	#if defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	708	typedef struct
mbed_official	330:c80ac197fa6a	709	{
mbed_official	330:c80ac197fa6a	710	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	711	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	712
mbed_official	330:c80ac197fa6a	713	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	714	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	715
mbed_official	330:c80ac197fa6a	716	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	717	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	718
mbed_official	330:c80ac197fa6a	719	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	720	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	721
mbed_official	330:c80ac197fa6a	722	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	723	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	724
mbed_official	330:c80ac197fa6a	725	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	726	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	727
mbed_official	330:c80ac197fa6a	728	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	729	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	730
mbed_official	330:c80ac197fa6a	731	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	330:c80ac197fa6a	732	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	330:c80ac197fa6a	733
mbed_official	330:c80ac197fa6a	734	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
mbed_official	330:c80ac197fa6a	735	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
mbed_official	330:c80ac197fa6a	736
mbed_official	330:c80ac197fa6a	737	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	330:c80ac197fa6a	738	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	330:c80ac197fa6a	739
mbed_official	330:c80ac197fa6a	740	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	330:c80ac197fa6a	741	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	330:c80ac197fa6a	742
mbed_official	330:c80ac197fa6a	743	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	744	#endif /* STM32F373xC */
mbed_official	330:c80ac197fa6a	745
mbed_official	330:c80ac197fa6a	746	#if defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	747	typedef struct
mbed_official	330:c80ac197fa6a	748	{
mbed_official	330:c80ac197fa6a	749	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	330:c80ac197fa6a	750	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	330:c80ac197fa6a	751
mbed_official	330:c80ac197fa6a	752	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	330:c80ac197fa6a	753	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	330:c80ac197fa6a	754
mbed_official	330:c80ac197fa6a	755	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	330:c80ac197fa6a	756	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	330:c80ac197fa6a	757
mbed_official	330:c80ac197fa6a	758	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	330:c80ac197fa6a	759	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	330:c80ac197fa6a	760
mbed_official	330:c80ac197fa6a	761	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	330:c80ac197fa6a	762	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	330:c80ac197fa6a	763
mbed_official	330:c80ac197fa6a	764	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	330:c80ac197fa6a	765	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	330:c80ac197fa6a	766
mbed_official	330:c80ac197fa6a	767	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	330:c80ac197fa6a	768	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	330:c80ac197fa6a	769
mbed_official	330:c80ac197fa6a	770	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	330:c80ac197fa6a	771	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	330:c80ac197fa6a	772
mbed_official	330:c80ac197fa6a	773	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
mbed_official	330:c80ac197fa6a	774	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
mbed_official	330:c80ac197fa6a	775
mbed_official	330:c80ac197fa6a	776	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	330:c80ac197fa6a	777	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	330:c80ac197fa6a	778
mbed_official	330:c80ac197fa6a	779	}RCC_PeriphCLKInitTypeDef;
mbed_official	330:c80ac197fa6a	780	#endif /* STM32F378xx */
mbed_official	330:c80ac197fa6a	781
mbed_official	330:c80ac197fa6a	782	/**
mbed_official	330:c80ac197fa6a	783	* @}
mbed_official	330:c80ac197fa6a	784	*/
mbed_official	330:c80ac197fa6a	785
mbed_official	330:c80ac197fa6a	786	/* Exported constants --------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	787	/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
mbed_official	330:c80ac197fa6a	788	* @{
mbed_official	330:c80ac197fa6a	789	*/
mbed_official	330:c80ac197fa6a	790	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	791	defined(STM32F334x8) \|\| \
mbed_official	330:c80ac197fa6a	792	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	793	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
mbed_official	330:c80ac197fa6a	794	* @{
mbed_official	330:c80ac197fa6a	795	*/
mbed_official	330:c80ac197fa6a	796	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
mbed_official	330:c80ac197fa6a	797	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
mbed_official	330:c80ac197fa6a	798	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	330:c80ac197fa6a	799	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
mbed_official	330:c80ac197fa6a	800	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
mbed_official	330:c80ac197fa6a	801	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
mbed_official	330:c80ac197fa6a	802	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
mbed_official	330:c80ac197fa6a	803
mbed_official	330:c80ac197fa6a	804	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	330:c80ac197fa6a	805	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	330:c80ac197fa6a	806	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	807	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	808	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	809	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	330:c80ac197fa6a	810	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
mbed_official	330:c80ac197fa6a	811	/**
mbed_official	330:c80ac197fa6a	812	* @}
mbed_official	330:c80ac197fa6a	813	*/
mbed_official	330:c80ac197fa6a	814	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	815	/* STM32F334x8 */
mbed_official	330:c80ac197fa6a	816	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	817
mbed_official	330:c80ac197fa6a	818	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	819	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	820	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	821	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
mbed_official	330:c80ac197fa6a	822	* @{
mbed_official	330:c80ac197fa6a	823	*/
mbed_official	330:c80ac197fa6a	824	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
mbed_official	330:c80ac197fa6a	825	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
mbed_official	330:c80ac197fa6a	826	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	330:c80ac197fa6a	827	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
mbed_official	330:c80ac197fa6a	828	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
mbed_official	330:c80ac197fa6a	829	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
mbed_official	330:c80ac197fa6a	830	#define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV \| RCC_CFGR_MCO_PLL)
mbed_official	330:c80ac197fa6a	831	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
mbed_official	330:c80ac197fa6a	832
mbed_official	330:c80ac197fa6a	833	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	330:c80ac197fa6a	834	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	330:c80ac197fa6a	835	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	836	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	837	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	838	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	330:c80ac197fa6a	839	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	840	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
mbed_official	330:c80ac197fa6a	841	/**
mbed_official	330:c80ac197fa6a	842	* @}
mbed_official	330:c80ac197fa6a	843	*/
mbed_official	330:c80ac197fa6a	844	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	845	/* STM32F303x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	846	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	847
mbed_official	330:c80ac197fa6a	848	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	849	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
mbed_official	330:c80ac197fa6a	850	* @{
mbed_official	330:c80ac197fa6a	851	*/
mbed_official	330:c80ac197fa6a	852	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	330:c80ac197fa6a	853	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
mbed_official	330:c80ac197fa6a	854
mbed_official	330:c80ac197fa6a	855	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	856	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	330:c80ac197fa6a	857	/**
mbed_official	330:c80ac197fa6a	858	* @}
mbed_official	330:c80ac197fa6a	859	*/
mbed_official	330:c80ac197fa6a	860
mbed_official	330:c80ac197fa6a	861	/** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
mbed_official	330:c80ac197fa6a	862	* @{
mbed_official	330:c80ac197fa6a	863	*/
mbed_official	330:c80ac197fa6a	864	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
mbed_official	330:c80ac197fa6a	865	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
mbed_official	330:c80ac197fa6a	866	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
mbed_official	330:c80ac197fa6a	867	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
mbed_official	330:c80ac197fa6a	868	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
mbed_official	330:c80ac197fa6a	869	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
mbed_official	330:c80ac197fa6a	870	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
mbed_official	330:c80ac197fa6a	871	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
mbed_official	330:c80ac197fa6a	872	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
mbed_official	330:c80ac197fa6a	873	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
mbed_official	330:c80ac197fa6a	874	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
mbed_official	330:c80ac197fa6a	875	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
mbed_official	330:c80ac197fa6a	876	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
mbed_official	330:c80ac197fa6a	877	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
mbed_official	330:c80ac197fa6a	878	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
mbed_official	330:c80ac197fa6a	879	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
mbed_official	330:c80ac197fa6a	880
mbed_official	330:c80ac197fa6a	881	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
mbed_official	330:c80ac197fa6a	882	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	883	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
mbed_official	330:c80ac197fa6a	884	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	885	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
mbed_official	330:c80ac197fa6a	886	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	887	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
mbed_official	330:c80ac197fa6a	888	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
mbed_official	330:c80ac197fa6a	889	/**
mbed_official	330:c80ac197fa6a	890	* @}
mbed_official	330:c80ac197fa6a	891	*/
mbed_official	330:c80ac197fa6a	892	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	893
mbed_official	330:c80ac197fa6a	894	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	895	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	896	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	330:c80ac197fa6a	897	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	898	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
mbed_official	330:c80ac197fa6a	899	* @{
mbed_official	330:c80ac197fa6a	900	*/
mbed_official	330:c80ac197fa6a	901	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
mbed_official	330:c80ac197fa6a	902	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
mbed_official	330:c80ac197fa6a	903
mbed_official	330:c80ac197fa6a	904	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	905	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	330:c80ac197fa6a	906	/**
mbed_official	330:c80ac197fa6a	907	* @}
mbed_official	330:c80ac197fa6a	908	*/
mbed_official	330:c80ac197fa6a	909
mbed_official	330:c80ac197fa6a	910	/** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
mbed_official	330:c80ac197fa6a	911	* @{
mbed_official	330:c80ac197fa6a	912	*/
mbed_official	330:c80ac197fa6a	913
mbed_official	330:c80ac197fa6a	914	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
mbed_official	330:c80ac197fa6a	915	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
mbed_official	330:c80ac197fa6a	916	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
mbed_official	330:c80ac197fa6a	917	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
mbed_official	330:c80ac197fa6a	918	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
mbed_official	330:c80ac197fa6a	919	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
mbed_official	330:c80ac197fa6a	920	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
mbed_official	330:c80ac197fa6a	921	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
mbed_official	330:c80ac197fa6a	922	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
mbed_official	330:c80ac197fa6a	923	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
mbed_official	330:c80ac197fa6a	924	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
mbed_official	330:c80ac197fa6a	925	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
mbed_official	330:c80ac197fa6a	926	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
mbed_official	330:c80ac197fa6a	927	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
mbed_official	330:c80ac197fa6a	928	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
mbed_official	330:c80ac197fa6a	929	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
mbed_official	330:c80ac197fa6a	930
mbed_official	330:c80ac197fa6a	931	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
mbed_official	330:c80ac197fa6a	932	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	933	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
mbed_official	330:c80ac197fa6a	934	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	935	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
mbed_official	330:c80ac197fa6a	936	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	937	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
mbed_official	330:c80ac197fa6a	938	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
mbed_official	330:c80ac197fa6a	939	/**
mbed_official	330:c80ac197fa6a	940	* @}
mbed_official	330:c80ac197fa6a	941	*/
mbed_official	330:c80ac197fa6a	942	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	943	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	944	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	945	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	946
mbed_official	330:c80ac197fa6a	947	/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
mbed_official	330:c80ac197fa6a	948	* @{
mbed_official	330:c80ac197fa6a	949	*/
mbed_official	330:c80ac197fa6a	950	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	951	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	952	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	953	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	954	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	955	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	956	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	957	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	958	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	959	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
mbed_official	330:c80ac197fa6a	960	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	961	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
mbed_official	330:c80ac197fa6a	962	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
mbed_official	330:c80ac197fa6a	963	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
mbed_official	330:c80ac197fa6a	964
mbed_official	330:c80ac197fa6a	965	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	966	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	967	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
mbed_official	330:c80ac197fa6a	968	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	969	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	330:c80ac197fa6a	970	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	971	#endif /* STM32F301x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	972
mbed_official	330:c80ac197fa6a	973	#if defined(STM32F302x8)
mbed_official	330:c80ac197fa6a	974	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	975	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	976	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	977	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	978	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	979	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	980	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	981	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	982	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
mbed_official	330:c80ac197fa6a	983	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	984	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	985	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
mbed_official	330:c80ac197fa6a	986	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
mbed_official	330:c80ac197fa6a	987	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
mbed_official	330:c80ac197fa6a	988
mbed_official	330:c80ac197fa6a	989	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	990	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	991	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
mbed_official	330:c80ac197fa6a	992	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	993	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
mbed_official	330:c80ac197fa6a	994	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	330:c80ac197fa6a	995	RCC_PERIPHCLK_TIM17))
mbed_official	330:c80ac197fa6a	996	#endif /* STM32F302x8 */
mbed_official	330:c80ac197fa6a	997
mbed_official	330:c80ac197fa6a	998	#if defined(STM32F302xC)
mbed_official	330:c80ac197fa6a	999	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1000	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1001	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1002	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1003	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1004	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1005	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1006	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1007	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1008	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1009	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1010	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	1011
mbed_official	330:c80ac197fa6a	1012	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1013	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1014	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1015	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
mbed_official	330:c80ac197fa6a	1016	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1017	RCC_PERIPHCLK_USB))
mbed_official	330:c80ac197fa6a	1018	#endif /* STM32F302xC */
mbed_official	330:c80ac197fa6a	1019
mbed_official	330:c80ac197fa6a	1020	#if defined(STM32F303xC)
mbed_official	330:c80ac197fa6a	1021	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1022	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1023	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1024	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1025	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1026	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1027	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1028	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1029	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	330:c80ac197fa6a	1030	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1031	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1032	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	330:c80ac197fa6a	1033	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1034	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	1035
mbed_official	330:c80ac197fa6a	1036	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1037	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1038	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1039	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	330:c80ac197fa6a	1040	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	1041	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1042	RCC_PERIPHCLK_USB))
mbed_official	330:c80ac197fa6a	1043	#endif /* STM32F303xC */
mbed_official	330:c80ac197fa6a	1044
mbed_official	330:c80ac197fa6a	1045	#if defined(STM32F302xE)
mbed_official	330:c80ac197fa6a	1046	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1047	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1048	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1049	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1050	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1051	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1052	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1053	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1054	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1055	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1056	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1057	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	1058	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
mbed_official	330:c80ac197fa6a	1059	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
mbed_official	330:c80ac197fa6a	1060	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
mbed_official	330:c80ac197fa6a	1061	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
mbed_official	330:c80ac197fa6a	1062	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
mbed_official	330:c80ac197fa6a	1063	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
mbed_official	330:c80ac197fa6a	1064
mbed_official	330:c80ac197fa6a	1065	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1066	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1067	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1068	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
mbed_official	330:c80ac197fa6a	1069	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1070	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
mbed_official	330:c80ac197fa6a	1071	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
mbed_official	330:c80ac197fa6a	1072	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	330:c80ac197fa6a	1073	RCC_PERIPHCLK_TIM17))
mbed_official	330:c80ac197fa6a	1074	#endif /* STM32F302xE */
mbed_official	330:c80ac197fa6a	1075
mbed_official	330:c80ac197fa6a	1076	#if defined(STM32F303xE)
mbed_official	330:c80ac197fa6a	1077	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1078	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1079	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1080	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1081	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1082	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1083	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1084	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1085	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	330:c80ac197fa6a	1086	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1087	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1088	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	330:c80ac197fa6a	1089	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1090	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	1091	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
mbed_official	330:c80ac197fa6a	1092	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
mbed_official	330:c80ac197fa6a	1093	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
mbed_official	330:c80ac197fa6a	1094	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
mbed_official	330:c80ac197fa6a	1095	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
mbed_official	330:c80ac197fa6a	1096	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
mbed_official	330:c80ac197fa6a	1097	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
mbed_official	330:c80ac197fa6a	1098
mbed_official	330:c80ac197fa6a	1099	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1100	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1101	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1102	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	330:c80ac197fa6a	1103	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	1104	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1105	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
mbed_official	330:c80ac197fa6a	1106	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
mbed_official	330:c80ac197fa6a	1107	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	330:c80ac197fa6a	1108	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_TIM20))
mbed_official	330:c80ac197fa6a	1109	#endif /* STM32F303xE */
mbed_official	330:c80ac197fa6a	1110
mbed_official	330:c80ac197fa6a	1111	#if defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	1112	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1113	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1114	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1115	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1116	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1117	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1118	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1119	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1120	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	330:c80ac197fa6a	1121	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1122	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1123	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	330:c80ac197fa6a	1124	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1125	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
mbed_official	330:c80ac197fa6a	1126	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
mbed_official	330:c80ac197fa6a	1127	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
mbed_official	330:c80ac197fa6a	1128	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
mbed_official	330:c80ac197fa6a	1129	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
mbed_official	330:c80ac197fa6a	1130	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
mbed_official	330:c80ac197fa6a	1131	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
mbed_official	330:c80ac197fa6a	1132
mbed_official	330:c80ac197fa6a	1133	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1134	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1135	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1136	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	330:c80ac197fa6a	1137	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	1138	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1139	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM2 \| \
mbed_official	330:c80ac197fa6a	1140	RCC_PERIPHCLK_TIM34 \| RCC_PERIPHCLK_TIM15 \| \
mbed_official	330:c80ac197fa6a	1141	RCC_PERIPHCLK_TIM16 \| RCC_PERIPHCLK_TIM17 \| \
mbed_official	330:c80ac197fa6a	1142	RCC_PERIPHCLK_TIM20))
mbed_official	330:c80ac197fa6a	1143	#endif /* STM32F398xx */
mbed_official	330:c80ac197fa6a	1144
mbed_official	330:c80ac197fa6a	1145	#if defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	1146	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1147	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1148	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1149	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	330:c80ac197fa6a	1150	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	330:c80ac197fa6a	1151	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1152	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1153	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1154	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	330:c80ac197fa6a	1155	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	330:c80ac197fa6a	1156	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1157	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	330:c80ac197fa6a	1158	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1159
mbed_official	330:c80ac197fa6a	1160	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1161	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	330:c80ac197fa6a	1162	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1163	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	330:c80ac197fa6a	1164	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	330:c80ac197fa6a	1165	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	1166	#endif /* STM32F358xx */
mbed_official	330:c80ac197fa6a	1167
mbed_official	330:c80ac197fa6a	1168	#if defined(STM32F303x8)
mbed_official	330:c80ac197fa6a	1169	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1170	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1171	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1172	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1173	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1174	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1175	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1176
mbed_official	330:c80ac197fa6a	1177	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1178	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	330:c80ac197fa6a	1179	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	1180	#endif /* STM32F303x8 */
mbed_official	330:c80ac197fa6a	1181
mbed_official	330:c80ac197fa6a	1182	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	1183	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1184	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1185	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1186	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1187	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1188	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1189	#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
mbed_official	330:c80ac197fa6a	1190	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1191
mbed_official	330:c80ac197fa6a	1192	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1193	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	330:c80ac197fa6a	1194	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
mbed_official	330:c80ac197fa6a	1195	RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	1196	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	1197
mbed_official	330:c80ac197fa6a	1198	#if defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	1199	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1200	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1201	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1202	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1203	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1204	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	330:c80ac197fa6a	1205	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1206
mbed_official	330:c80ac197fa6a	1207	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1208	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	330:c80ac197fa6a	1209	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	1210	#endif /* STM32F328xx */
mbed_official	330:c80ac197fa6a	1211
mbed_official	330:c80ac197fa6a	1212	#if defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	1213	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1214	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1215	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1216	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1217	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1218	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1219	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	330:c80ac197fa6a	1220	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
mbed_official	330:c80ac197fa6a	1221	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1222	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	330:c80ac197fa6a	1223
mbed_official	330:c80ac197fa6a	1224	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1225	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1226	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
mbed_official	330:c80ac197fa6a	1227	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
mbed_official	330:c80ac197fa6a	1228	RCC_PERIPHCLK_USB))
mbed_official	330:c80ac197fa6a	1229	#endif /* STM32F373xC */
mbed_official	330:c80ac197fa6a	1230
mbed_official	330:c80ac197fa6a	1231	#if defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	1232	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	330:c80ac197fa6a	1233	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	330:c80ac197fa6a	1234	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	330:c80ac197fa6a	1235	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	330:c80ac197fa6a	1236	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	330:c80ac197fa6a	1237	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	330:c80ac197fa6a	1238	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	330:c80ac197fa6a	1239	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
mbed_official	330:c80ac197fa6a	1240	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	330:c80ac197fa6a	1241
mbed_official	330:c80ac197fa6a	1242	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	330:c80ac197fa6a	1243	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	330:c80ac197fa6a	1244	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
mbed_official	330:c80ac197fa6a	1245	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
mbed_official	330:c80ac197fa6a	1246	#endif /* STM32F378xx */
mbed_official	330:c80ac197fa6a	1247	/**
mbed_official	330:c80ac197fa6a	1248	* @}
mbed_official	330:c80ac197fa6a	1249	*/
mbed_official	330:c80ac197fa6a	1250
mbed_official	330:c80ac197fa6a	1251	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	1252
mbed_official	330:c80ac197fa6a	1253	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
mbed_official	330:c80ac197fa6a	1254	* @{
mbed_official	330:c80ac197fa6a	1255	*/
mbed_official	330:c80ac197fa6a	1256	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	330:c80ac197fa6a	1257	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	330:c80ac197fa6a	1258	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	330:c80ac197fa6a	1259	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	330:c80ac197fa6a	1260
mbed_official	330:c80ac197fa6a	1261	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	330:c80ac197fa6a	1262	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1263	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1264	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1265	/**
mbed_official	330:c80ac197fa6a	1266	* @}
mbed_official	330:c80ac197fa6a	1267	*/
mbed_official	330:c80ac197fa6a	1268
mbed_official	330:c80ac197fa6a	1269	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
mbed_official	330:c80ac197fa6a	1270	* @{
mbed_official	330:c80ac197fa6a	1271	*/
mbed_official	330:c80ac197fa6a	1272	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	330:c80ac197fa6a	1273	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	330:c80ac197fa6a	1274
mbed_official	330:c80ac197fa6a	1275	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1276	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1277	/**
mbed_official	330:c80ac197fa6a	1278	* @}
mbed_official	330:c80ac197fa6a	1279	*/
mbed_official	330:c80ac197fa6a	1280
mbed_official	330:c80ac197fa6a	1281	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
mbed_official	330:c80ac197fa6a	1282	* @{
mbed_official	330:c80ac197fa6a	1283	*/
mbed_official	330:c80ac197fa6a	1284	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
mbed_official	330:c80ac197fa6a	1285	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
mbed_official	330:c80ac197fa6a	1286
mbed_official	330:c80ac197fa6a	1287	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1288	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1289	/**
mbed_official	330:c80ac197fa6a	1290	* @}
mbed_official	330:c80ac197fa6a	1291	*/
mbed_official	330:c80ac197fa6a	1292
mbed_official	330:c80ac197fa6a	1293	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
mbed_official	330:c80ac197fa6a	1294	* @{
mbed_official	330:c80ac197fa6a	1295	*/
mbed_official	330:c80ac197fa6a	1296	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
mbed_official	330:c80ac197fa6a	1297	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
mbed_official	330:c80ac197fa6a	1298	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
mbed_official	330:c80ac197fa6a	1299	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
mbed_official	330:c80ac197fa6a	1300	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
mbed_official	330:c80ac197fa6a	1301	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
mbed_official	330:c80ac197fa6a	1302	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
mbed_official	330:c80ac197fa6a	1303	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
mbed_official	330:c80ac197fa6a	1304	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
mbed_official	330:c80ac197fa6a	1305	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
mbed_official	330:c80ac197fa6a	1306	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
mbed_official	330:c80ac197fa6a	1307	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
mbed_official	330:c80ac197fa6a	1308	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
mbed_official	330:c80ac197fa6a	1309
mbed_official	330:c80ac197fa6a	1310	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1311	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1312	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1313	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	1314	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1315	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
mbed_official	330:c80ac197fa6a	1316	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
mbed_official	330:c80ac197fa6a	1317	/**
mbed_official	330:c80ac197fa6a	1318	* @}
mbed_official	330:c80ac197fa6a	1319	*/
mbed_official	330:c80ac197fa6a	1320
mbed_official	330:c80ac197fa6a	1321	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
mbed_official	330:c80ac197fa6a	1322	* @{
mbed_official	330:c80ac197fa6a	1323	*/
mbed_official	330:c80ac197fa6a	1324	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
mbed_official	330:c80ac197fa6a	1325	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
mbed_official	330:c80ac197fa6a	1326
mbed_official	330:c80ac197fa6a	1327	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1328	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official	330:c80ac197fa6a	1329	/**
mbed_official	330:c80ac197fa6a	1330	* @}
mbed_official	330:c80ac197fa6a	1331	*/
mbed_official	330:c80ac197fa6a	1332
mbed_official	330:c80ac197fa6a	1333	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
mbed_official	330:c80ac197fa6a	1334	* @{
mbed_official	330:c80ac197fa6a	1335	*/
mbed_official	330:c80ac197fa6a	1336	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	330:c80ac197fa6a	1337	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	330:c80ac197fa6a	1338
mbed_official	330:c80ac197fa6a	1339	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1340	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1341	/**
mbed_official	330:c80ac197fa6a	1342	* @}
mbed_official	330:c80ac197fa6a	1343	*/
mbed_official	330:c80ac197fa6a	1344
mbed_official	330:c80ac197fa6a	1345	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
mbed_official	330:c80ac197fa6a	1346	* @{
mbed_official	330:c80ac197fa6a	1347	*/
mbed_official	330:c80ac197fa6a	1348	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
mbed_official	330:c80ac197fa6a	1349	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
mbed_official	330:c80ac197fa6a	1350
mbed_official	330:c80ac197fa6a	1351	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1352	((SOURCE) == RCC_TIM15CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1353	/**
mbed_official	330:c80ac197fa6a	1354	* @}
mbed_official	330:c80ac197fa6a	1355	*/
mbed_official	330:c80ac197fa6a	1356
mbed_official	330:c80ac197fa6a	1357	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
mbed_official	330:c80ac197fa6a	1358	* @{
mbed_official	330:c80ac197fa6a	1359	*/
mbed_official	330:c80ac197fa6a	1360	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
mbed_official	330:c80ac197fa6a	1361	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
mbed_official	330:c80ac197fa6a	1362
mbed_official	330:c80ac197fa6a	1363	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1364	((SOURCE) == RCC_TIM16CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1365	/**
mbed_official	330:c80ac197fa6a	1366	* @}
mbed_official	330:c80ac197fa6a	1367	*/
mbed_official	330:c80ac197fa6a	1368
mbed_official	330:c80ac197fa6a	1369	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
mbed_official	330:c80ac197fa6a	1370	* @{
mbed_official	330:c80ac197fa6a	1371	*/
mbed_official	330:c80ac197fa6a	1372	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
mbed_official	330:c80ac197fa6a	1373	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
mbed_official	330:c80ac197fa6a	1374
mbed_official	330:c80ac197fa6a	1375	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1376	((SOURCE) == RCC_TIM17CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1377	/**
mbed_official	330:c80ac197fa6a	1378	* @}
mbed_official	330:c80ac197fa6a	1379	*/
mbed_official	330:c80ac197fa6a	1380
mbed_official	330:c80ac197fa6a	1381	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	1382
mbed_official	330:c80ac197fa6a	1383	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	1384
mbed_official	330:c80ac197fa6a	1385	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
mbed_official	330:c80ac197fa6a	1386	* @{
mbed_official	330:c80ac197fa6a	1387	*/
mbed_official	330:c80ac197fa6a	1388	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	330:c80ac197fa6a	1389	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	330:c80ac197fa6a	1390	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	330:c80ac197fa6a	1391	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	330:c80ac197fa6a	1392
mbed_official	330:c80ac197fa6a	1393	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	330:c80ac197fa6a	1394	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1395	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1396	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1397	/**
mbed_official	330:c80ac197fa6a	1398	* @}
mbed_official	330:c80ac197fa6a	1399	*/
mbed_official	330:c80ac197fa6a	1400
mbed_official	330:c80ac197fa6a	1401	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
mbed_official	330:c80ac197fa6a	1402	* @{
mbed_official	330:c80ac197fa6a	1403	*/
mbed_official	330:c80ac197fa6a	1404	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	330:c80ac197fa6a	1405	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	330:c80ac197fa6a	1406
mbed_official	330:c80ac197fa6a	1407	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1408	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1409	/**
mbed_official	330:c80ac197fa6a	1410	* @}
mbed_official	330:c80ac197fa6a	1411	*/
mbed_official	330:c80ac197fa6a	1412
mbed_official	330:c80ac197fa6a	1413	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
mbed_official	330:c80ac197fa6a	1414	* @{
mbed_official	330:c80ac197fa6a	1415	*/
mbed_official	330:c80ac197fa6a	1416
mbed_official	330:c80ac197fa6a	1417	/* ADC1 & ADC2 */
mbed_official	330:c80ac197fa6a	1418	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
mbed_official	330:c80ac197fa6a	1419	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
mbed_official	330:c80ac197fa6a	1420	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
mbed_official	330:c80ac197fa6a	1421	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
mbed_official	330:c80ac197fa6a	1422	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
mbed_official	330:c80ac197fa6a	1423	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
mbed_official	330:c80ac197fa6a	1424	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
mbed_official	330:c80ac197fa6a	1425	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
mbed_official	330:c80ac197fa6a	1426	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
mbed_official	330:c80ac197fa6a	1427	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
mbed_official	330:c80ac197fa6a	1428	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
mbed_official	330:c80ac197fa6a	1429	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
mbed_official	330:c80ac197fa6a	1430	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
mbed_official	330:c80ac197fa6a	1431
mbed_official	330:c80ac197fa6a	1432	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1433	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1434	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1435	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	1436	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1437	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
mbed_official	330:c80ac197fa6a	1438	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
mbed_official	330:c80ac197fa6a	1439	/**
mbed_official	330:c80ac197fa6a	1440	* @}
mbed_official	330:c80ac197fa6a	1441	*/
mbed_official	330:c80ac197fa6a	1442
mbed_official	330:c80ac197fa6a	1443	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
mbed_official	330:c80ac197fa6a	1444	* @{
mbed_official	330:c80ac197fa6a	1445	*/
mbed_official	330:c80ac197fa6a	1446	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
mbed_official	330:c80ac197fa6a	1447	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
mbed_official	330:c80ac197fa6a	1448
mbed_official	330:c80ac197fa6a	1449	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1450	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official	330:c80ac197fa6a	1451	/**
mbed_official	330:c80ac197fa6a	1452	* @}
mbed_official	330:c80ac197fa6a	1453	*/
mbed_official	330:c80ac197fa6a	1454	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
mbed_official	330:c80ac197fa6a	1455	* @{
mbed_official	330:c80ac197fa6a	1456	*/
mbed_official	330:c80ac197fa6a	1457	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	330:c80ac197fa6a	1458	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	330:c80ac197fa6a	1459
mbed_official	330:c80ac197fa6a	1460	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1461	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1462	/**
mbed_official	330:c80ac197fa6a	1463	* @}
mbed_official	330:c80ac197fa6a	1464	*/
mbed_official	330:c80ac197fa6a	1465
mbed_official	330:c80ac197fa6a	1466	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
mbed_official	330:c80ac197fa6a	1467	* @{
mbed_official	330:c80ac197fa6a	1468	*/
mbed_official	330:c80ac197fa6a	1469	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
mbed_official	330:c80ac197fa6a	1470	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
mbed_official	330:c80ac197fa6a	1471	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
mbed_official	330:c80ac197fa6a	1472	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
mbed_official	330:c80ac197fa6a	1473
mbed_official	330:c80ac197fa6a	1474	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
mbed_official	330:c80ac197fa6a	1475	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1476	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1477	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1478	/**
mbed_official	330:c80ac197fa6a	1479	* @}
mbed_official	330:c80ac197fa6a	1480	*/
mbed_official	330:c80ac197fa6a	1481
mbed_official	330:c80ac197fa6a	1482	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
mbed_official	330:c80ac197fa6a	1483	* @{
mbed_official	330:c80ac197fa6a	1484	*/
mbed_official	330:c80ac197fa6a	1485	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
mbed_official	330:c80ac197fa6a	1486	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
mbed_official	330:c80ac197fa6a	1487	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
mbed_official	330:c80ac197fa6a	1488	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
mbed_official	330:c80ac197fa6a	1489
mbed_official	330:c80ac197fa6a	1490	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
mbed_official	330:c80ac197fa6a	1491	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1492	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1493	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1494	/**
mbed_official	330:c80ac197fa6a	1495	* @}
mbed_official	330:c80ac197fa6a	1496	*/
mbed_official	330:c80ac197fa6a	1497
mbed_official	330:c80ac197fa6a	1498	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	1499
mbed_official	330:c80ac197fa6a	1500	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	1501
mbed_official	330:c80ac197fa6a	1502	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
mbed_official	330:c80ac197fa6a	1503	* @{
mbed_official	330:c80ac197fa6a	1504	*/
mbed_official	330:c80ac197fa6a	1505	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	330:c80ac197fa6a	1506	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	330:c80ac197fa6a	1507	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	330:c80ac197fa6a	1508	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	330:c80ac197fa6a	1509
mbed_official	330:c80ac197fa6a	1510	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	330:c80ac197fa6a	1511	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1512	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1513	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1514	/**
mbed_official	330:c80ac197fa6a	1515	* @}
mbed_official	330:c80ac197fa6a	1516	*/
mbed_official	330:c80ac197fa6a	1517
mbed_official	330:c80ac197fa6a	1518	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
mbed_official	330:c80ac197fa6a	1519	* @{
mbed_official	330:c80ac197fa6a	1520	*/
mbed_official	330:c80ac197fa6a	1521	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	330:c80ac197fa6a	1522	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	330:c80ac197fa6a	1523
mbed_official	330:c80ac197fa6a	1524	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1525	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1526	/**
mbed_official	330:c80ac197fa6a	1527	* @}
mbed_official	330:c80ac197fa6a	1528	*/
mbed_official	330:c80ac197fa6a	1529
mbed_official	330:c80ac197fa6a	1530	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
mbed_official	330:c80ac197fa6a	1531	* @{
mbed_official	330:c80ac197fa6a	1532	*/
mbed_official	330:c80ac197fa6a	1533	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
mbed_official	330:c80ac197fa6a	1534	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
mbed_official	330:c80ac197fa6a	1535
mbed_official	330:c80ac197fa6a	1536	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1537	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1538	/**
mbed_official	330:c80ac197fa6a	1539	* @}
mbed_official	330:c80ac197fa6a	1540	*/
mbed_official	330:c80ac197fa6a	1541
mbed_official	330:c80ac197fa6a	1542	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
mbed_official	330:c80ac197fa6a	1543	* @{
mbed_official	330:c80ac197fa6a	1544	*/
mbed_official	330:c80ac197fa6a	1545
mbed_official	330:c80ac197fa6a	1546	/* ADC1 & ADC2 */
mbed_official	330:c80ac197fa6a	1547	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
mbed_official	330:c80ac197fa6a	1548	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
mbed_official	330:c80ac197fa6a	1549	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
mbed_official	330:c80ac197fa6a	1550	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
mbed_official	330:c80ac197fa6a	1551	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
mbed_official	330:c80ac197fa6a	1552	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
mbed_official	330:c80ac197fa6a	1553	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
mbed_official	330:c80ac197fa6a	1554	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
mbed_official	330:c80ac197fa6a	1555	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
mbed_official	330:c80ac197fa6a	1556	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
mbed_official	330:c80ac197fa6a	1557	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
mbed_official	330:c80ac197fa6a	1558	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
mbed_official	330:c80ac197fa6a	1559	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
mbed_official	330:c80ac197fa6a	1560
mbed_official	330:c80ac197fa6a	1561	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1562	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1563	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1564	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	1565	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1566	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
mbed_official	330:c80ac197fa6a	1567	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
mbed_official	330:c80ac197fa6a	1568	/**
mbed_official	330:c80ac197fa6a	1569	* @}
mbed_official	330:c80ac197fa6a	1570	*/
mbed_official	330:c80ac197fa6a	1571
mbed_official	330:c80ac197fa6a	1572	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
mbed_official	330:c80ac197fa6a	1573	* @{
mbed_official	330:c80ac197fa6a	1574	*/
mbed_official	330:c80ac197fa6a	1575	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
mbed_official	330:c80ac197fa6a	1576	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
mbed_official	330:c80ac197fa6a	1577
mbed_official	330:c80ac197fa6a	1578	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1579	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official	330:c80ac197fa6a	1580	/**
mbed_official	330:c80ac197fa6a	1581	* @}
mbed_official	330:c80ac197fa6a	1582	*/
mbed_official	330:c80ac197fa6a	1583
mbed_official	330:c80ac197fa6a	1584	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
mbed_official	330:c80ac197fa6a	1585	* @{
mbed_official	330:c80ac197fa6a	1586	*/
mbed_official	330:c80ac197fa6a	1587	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	330:c80ac197fa6a	1588	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	330:c80ac197fa6a	1589
mbed_official	330:c80ac197fa6a	1590	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1591	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1592	/**
mbed_official	330:c80ac197fa6a	1593	* @}
mbed_official	330:c80ac197fa6a	1594	*/
mbed_official	330:c80ac197fa6a	1595
mbed_official	330:c80ac197fa6a	1596	/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
mbed_official	330:c80ac197fa6a	1597	* @{
mbed_official	330:c80ac197fa6a	1598	*/
mbed_official	330:c80ac197fa6a	1599	#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
mbed_official	330:c80ac197fa6a	1600	#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
mbed_official	330:c80ac197fa6a	1601
mbed_official	330:c80ac197fa6a	1602	#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1603	((SOURCE) == RCC_TIM2CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1604	/**
mbed_official	330:c80ac197fa6a	1605	* @}
mbed_official	330:c80ac197fa6a	1606	*/
mbed_official	330:c80ac197fa6a	1607
mbed_official	330:c80ac197fa6a	1608	/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
mbed_official	330:c80ac197fa6a	1609	* @{
mbed_official	330:c80ac197fa6a	1610	*/
mbed_official	330:c80ac197fa6a	1611	#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
mbed_official	330:c80ac197fa6a	1612	#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
mbed_official	330:c80ac197fa6a	1613
mbed_official	330:c80ac197fa6a	1614	#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1615	((SOURCE) == RCC_TIM34CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1616	/**
mbed_official	330:c80ac197fa6a	1617	* @}
mbed_official	330:c80ac197fa6a	1618	*/
mbed_official	330:c80ac197fa6a	1619
mbed_official	330:c80ac197fa6a	1620	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
mbed_official	330:c80ac197fa6a	1621	* @{
mbed_official	330:c80ac197fa6a	1622	*/
mbed_official	330:c80ac197fa6a	1623	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
mbed_official	330:c80ac197fa6a	1624	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
mbed_official	330:c80ac197fa6a	1625
mbed_official	330:c80ac197fa6a	1626	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1627	((SOURCE) == RCC_TIM15CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1628	/**
mbed_official	330:c80ac197fa6a	1629	* @}
mbed_official	330:c80ac197fa6a	1630	*/
mbed_official	330:c80ac197fa6a	1631
mbed_official	330:c80ac197fa6a	1632	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
mbed_official	330:c80ac197fa6a	1633	* @{
mbed_official	330:c80ac197fa6a	1634	*/
mbed_official	330:c80ac197fa6a	1635	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
mbed_official	330:c80ac197fa6a	1636	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
mbed_official	330:c80ac197fa6a	1637
mbed_official	330:c80ac197fa6a	1638	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1639	((SOURCE) == RCC_TIM16CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1640	/**
mbed_official	330:c80ac197fa6a	1641	* @}
mbed_official	330:c80ac197fa6a	1642	*/
mbed_official	330:c80ac197fa6a	1643
mbed_official	330:c80ac197fa6a	1644	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
mbed_official	330:c80ac197fa6a	1645	* @{
mbed_official	330:c80ac197fa6a	1646	*/
mbed_official	330:c80ac197fa6a	1647	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
mbed_official	330:c80ac197fa6a	1648	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
mbed_official	330:c80ac197fa6a	1649
mbed_official	330:c80ac197fa6a	1650	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1651	((SOURCE) == RCC_TIM17CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1652	/**
mbed_official	330:c80ac197fa6a	1653	* @}
mbed_official	330:c80ac197fa6a	1654	*/
mbed_official	330:c80ac197fa6a	1655
mbed_official	330:c80ac197fa6a	1656	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
mbed_official	330:c80ac197fa6a	1657	* @{
mbed_official	330:c80ac197fa6a	1658	*/
mbed_official	330:c80ac197fa6a	1659	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
mbed_official	330:c80ac197fa6a	1660	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
mbed_official	330:c80ac197fa6a	1661	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
mbed_official	330:c80ac197fa6a	1662	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
mbed_official	330:c80ac197fa6a	1663
mbed_official	330:c80ac197fa6a	1664	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
mbed_official	330:c80ac197fa6a	1665	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1666	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1667	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1668	/**
mbed_official	330:c80ac197fa6a	1669	* @}
mbed_official	330:c80ac197fa6a	1670	*/
mbed_official	330:c80ac197fa6a	1671
mbed_official	330:c80ac197fa6a	1672	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
mbed_official	330:c80ac197fa6a	1673	* @{
mbed_official	330:c80ac197fa6a	1674	*/
mbed_official	330:c80ac197fa6a	1675	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
mbed_official	330:c80ac197fa6a	1676	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
mbed_official	330:c80ac197fa6a	1677	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
mbed_official	330:c80ac197fa6a	1678	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
mbed_official	330:c80ac197fa6a	1679
mbed_official	330:c80ac197fa6a	1680	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
mbed_official	330:c80ac197fa6a	1681	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1682	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1683	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1684	/**
mbed_official	330:c80ac197fa6a	1685	* @}
mbed_official	330:c80ac197fa6a	1686	*/
mbed_official	330:c80ac197fa6a	1687
mbed_official	330:c80ac197fa6a	1688	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	1689
mbed_official	330:c80ac197fa6a	1690	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	1691	/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
mbed_official	330:c80ac197fa6a	1692	* @{
mbed_official	330:c80ac197fa6a	1693	*/
mbed_official	330:c80ac197fa6a	1694	#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
mbed_official	330:c80ac197fa6a	1695	#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
mbed_official	330:c80ac197fa6a	1696
mbed_official	330:c80ac197fa6a	1697	#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1698	((SOURCE) == RCC_TIM20CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1699	/**
mbed_official	330:c80ac197fa6a	1700	* @}
mbed_official	330:c80ac197fa6a	1701	*/
mbed_official	330:c80ac197fa6a	1702	#endif /* STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	1703
mbed_official	330:c80ac197fa6a	1704	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	1705	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	1706
mbed_official	330:c80ac197fa6a	1707	/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
mbed_official	330:c80ac197fa6a	1708	* @{
mbed_official	330:c80ac197fa6a	1709	*/
mbed_official	330:c80ac197fa6a	1710
mbed_official	330:c80ac197fa6a	1711	/* ADC3 & ADC4 */
mbed_official	330:c80ac197fa6a	1712	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
mbed_official	330:c80ac197fa6a	1713	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
mbed_official	330:c80ac197fa6a	1714	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
mbed_official	330:c80ac197fa6a	1715	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
mbed_official	330:c80ac197fa6a	1716	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
mbed_official	330:c80ac197fa6a	1717	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
mbed_official	330:c80ac197fa6a	1718	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
mbed_official	330:c80ac197fa6a	1719	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
mbed_official	330:c80ac197fa6a	1720	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
mbed_official	330:c80ac197fa6a	1721	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
mbed_official	330:c80ac197fa6a	1722	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
mbed_official	330:c80ac197fa6a	1723	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
mbed_official	330:c80ac197fa6a	1724	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
mbed_official	330:c80ac197fa6a	1725
mbed_official	330:c80ac197fa6a	1726	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1727	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1728	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1729	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	1730	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1731	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
mbed_official	330:c80ac197fa6a	1732	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
mbed_official	330:c80ac197fa6a	1733	/**
mbed_official	330:c80ac197fa6a	1734	* @}
mbed_official	330:c80ac197fa6a	1735	*/
mbed_official	330:c80ac197fa6a	1736
mbed_official	330:c80ac197fa6a	1737	/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
mbed_official	330:c80ac197fa6a	1738	* @{
mbed_official	330:c80ac197fa6a	1739	*/
mbed_official	330:c80ac197fa6a	1740	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
mbed_official	330:c80ac197fa6a	1741	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
mbed_official	330:c80ac197fa6a	1742
mbed_official	330:c80ac197fa6a	1743	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1744	((SOURCE) == RCC_TIM8CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1745	/**
mbed_official	330:c80ac197fa6a	1746	* @}
mbed_official	330:c80ac197fa6a	1747	*/
mbed_official	330:c80ac197fa6a	1748
mbed_official	330:c80ac197fa6a	1749	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	1750
mbed_official	330:c80ac197fa6a	1751	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	1752
mbed_official	330:c80ac197fa6a	1753	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
mbed_official	330:c80ac197fa6a	1754	* @{
mbed_official	330:c80ac197fa6a	1755	*/
mbed_official	330:c80ac197fa6a	1756	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
mbed_official	330:c80ac197fa6a	1757	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	330:c80ac197fa6a	1758	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	330:c80ac197fa6a	1759	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	330:c80ac197fa6a	1760
mbed_official	330:c80ac197fa6a	1761	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
mbed_official	330:c80ac197fa6a	1762	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1763	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1764	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1765	/**
mbed_official	330:c80ac197fa6a	1766	* @}
mbed_official	330:c80ac197fa6a	1767	*/
mbed_official	330:c80ac197fa6a	1768
mbed_official	330:c80ac197fa6a	1769	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
mbed_official	330:c80ac197fa6a	1770	* @{
mbed_official	330:c80ac197fa6a	1771	*/
mbed_official	330:c80ac197fa6a	1772	/* ADC1 & ADC2 */
mbed_official	330:c80ac197fa6a	1773	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
mbed_official	330:c80ac197fa6a	1774	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
mbed_official	330:c80ac197fa6a	1775	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
mbed_official	330:c80ac197fa6a	1776	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
mbed_official	330:c80ac197fa6a	1777	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
mbed_official	330:c80ac197fa6a	1778	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
mbed_official	330:c80ac197fa6a	1779	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
mbed_official	330:c80ac197fa6a	1780	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
mbed_official	330:c80ac197fa6a	1781	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
mbed_official	330:c80ac197fa6a	1782	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
mbed_official	330:c80ac197fa6a	1783	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
mbed_official	330:c80ac197fa6a	1784	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
mbed_official	330:c80ac197fa6a	1785	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
mbed_official	330:c80ac197fa6a	1786
mbed_official	330:c80ac197fa6a	1787	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1788	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1789	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1790	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
mbed_official	330:c80ac197fa6a	1791	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1792	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
mbed_official	330:c80ac197fa6a	1793	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
mbed_official	330:c80ac197fa6a	1794	/**
mbed_official	330:c80ac197fa6a	1795	* @}
mbed_official	330:c80ac197fa6a	1796	*/
mbed_official	330:c80ac197fa6a	1797
mbed_official	330:c80ac197fa6a	1798	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
mbed_official	330:c80ac197fa6a	1799	* @{
mbed_official	330:c80ac197fa6a	1800	*/
mbed_official	330:c80ac197fa6a	1801	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	330:c80ac197fa6a	1802	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	330:c80ac197fa6a	1803
mbed_official	330:c80ac197fa6a	1804	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1805	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1806	/**
mbed_official	330:c80ac197fa6a	1807	* @}
mbed_official	330:c80ac197fa6a	1808	*/
mbed_official	330:c80ac197fa6a	1809
mbed_official	330:c80ac197fa6a	1810	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	1811
mbed_official	330:c80ac197fa6a	1812	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	1813
mbed_official	330:c80ac197fa6a	1814	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
mbed_official	330:c80ac197fa6a	1815	* @{
mbed_official	330:c80ac197fa6a	1816	*/
mbed_official	330:c80ac197fa6a	1817	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
mbed_official	330:c80ac197fa6a	1818	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
mbed_official	330:c80ac197fa6a	1819
mbed_official	330:c80ac197fa6a	1820	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
mbed_official	330:c80ac197fa6a	1821	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
mbed_official	330:c80ac197fa6a	1822	/**
mbed_official	330:c80ac197fa6a	1823	* @}
mbed_official	330:c80ac197fa6a	1824	*/
mbed_official	330:c80ac197fa6a	1825
mbed_official	330:c80ac197fa6a	1826	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	1827
mbed_official	330:c80ac197fa6a	1828	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	1829
mbed_official	330:c80ac197fa6a	1830	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
mbed_official	330:c80ac197fa6a	1831	* @{
mbed_official	330:c80ac197fa6a	1832	*/
mbed_official	330:c80ac197fa6a	1833	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	330:c80ac197fa6a	1834	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	330:c80ac197fa6a	1835	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	330:c80ac197fa6a	1836	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	330:c80ac197fa6a	1837
mbed_official	330:c80ac197fa6a	1838	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	330:c80ac197fa6a	1839	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	330:c80ac197fa6a	1840	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	330:c80ac197fa6a	1841	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	330:c80ac197fa6a	1842	/**
mbed_official	330:c80ac197fa6a	1843	* @}
mbed_official	330:c80ac197fa6a	1844	*/
mbed_official	330:c80ac197fa6a	1845
mbed_official	330:c80ac197fa6a	1846	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
mbed_official	330:c80ac197fa6a	1847	* @{
mbed_official	330:c80ac197fa6a	1848	*/
mbed_official	330:c80ac197fa6a	1849	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	330:c80ac197fa6a	1850	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	330:c80ac197fa6a	1851
mbed_official	330:c80ac197fa6a	1852	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1853	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	330:c80ac197fa6a	1854	/**
mbed_official	330:c80ac197fa6a	1855	* @}
mbed_official	330:c80ac197fa6a	1856	*/
mbed_official	330:c80ac197fa6a	1857
mbed_official	330:c80ac197fa6a	1858	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
mbed_official	330:c80ac197fa6a	1859	* @{
mbed_official	330:c80ac197fa6a	1860	*/
mbed_official	330:c80ac197fa6a	1861
mbed_official	330:c80ac197fa6a	1862	/* ADC1 */
mbed_official	330:c80ac197fa6a	1863	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
mbed_official	330:c80ac197fa6a	1864	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
mbed_official	330:c80ac197fa6a	1865	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
mbed_official	330:c80ac197fa6a	1866	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
mbed_official	330:c80ac197fa6a	1867
mbed_official	330:c80ac197fa6a	1868	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
mbed_official	330:c80ac197fa6a	1869	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
mbed_official	330:c80ac197fa6a	1870	/**
mbed_official	330:c80ac197fa6a	1871	* @}
mbed_official	330:c80ac197fa6a	1872	*/
mbed_official	330:c80ac197fa6a	1873
mbed_official	330:c80ac197fa6a	1874	/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
mbed_official	330:c80ac197fa6a	1875	* @{
mbed_official	330:c80ac197fa6a	1876	*/
mbed_official	330:c80ac197fa6a	1877	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
mbed_official	330:c80ac197fa6a	1878	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
mbed_official	330:c80ac197fa6a	1879
mbed_official	330:c80ac197fa6a	1880	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
mbed_official	330:c80ac197fa6a	1881	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	330:c80ac197fa6a	1882	/**
mbed_official	330:c80ac197fa6a	1883	* @}
mbed_official	330:c80ac197fa6a	1884	*/
mbed_official	330:c80ac197fa6a	1885
mbed_official	330:c80ac197fa6a	1886	/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
mbed_official	330:c80ac197fa6a	1887	* @{
mbed_official	330:c80ac197fa6a	1888	*/
mbed_official	330:c80ac197fa6a	1889	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
mbed_official	330:c80ac197fa6a	1890	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
mbed_official	330:c80ac197fa6a	1891	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
mbed_official	330:c80ac197fa6a	1892	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
mbed_official	330:c80ac197fa6a	1893	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
mbed_official	330:c80ac197fa6a	1894	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
mbed_official	330:c80ac197fa6a	1895	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
mbed_official	330:c80ac197fa6a	1896	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
mbed_official	330:c80ac197fa6a	1897	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
mbed_official	330:c80ac197fa6a	1898	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
mbed_official	330:c80ac197fa6a	1899	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
mbed_official	330:c80ac197fa6a	1900	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
mbed_official	330:c80ac197fa6a	1901	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
mbed_official	330:c80ac197fa6a	1902	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
mbed_official	330:c80ac197fa6a	1903	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
mbed_official	330:c80ac197fa6a	1904	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
mbed_official	330:c80ac197fa6a	1905	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
mbed_official	330:c80ac197fa6a	1906
mbed_official	330:c80ac197fa6a	1907	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
mbed_official	330:c80ac197fa6a	1908	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
mbed_official	330:c80ac197fa6a	1909	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
mbed_official	330:c80ac197fa6a	1910	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
mbed_official	330:c80ac197fa6a	1911	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
mbed_official	330:c80ac197fa6a	1912	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
mbed_official	330:c80ac197fa6a	1913	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
mbed_official	330:c80ac197fa6a	1914	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
mbed_official	330:c80ac197fa6a	1915	((DIV) == RCC_SDADCSYSCLK_DIV48))
mbed_official	330:c80ac197fa6a	1916	/**
mbed_official	330:c80ac197fa6a	1917	* @}
mbed_official	330:c80ac197fa6a	1918	*/
mbed_official	330:c80ac197fa6a	1919
mbed_official	330:c80ac197fa6a	1920	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	1921
mbed_official	330:c80ac197fa6a	1922	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
mbed_official	330:c80ac197fa6a	1923	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
mbed_official	330:c80ac197fa6a	1924	defined(STM32F302x8) \|\| \
mbed_official	330:c80ac197fa6a	1925	defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	1926	/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
mbed_official	330:c80ac197fa6a	1927	* @{
mbed_official	330:c80ac197fa6a	1928	*/
mbed_official	330:c80ac197fa6a	1929	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
mbed_official	330:c80ac197fa6a	1930	#define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
mbed_official	330:c80ac197fa6a	1931
mbed_official	330:c80ac197fa6a	1932	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) \|\| \
mbed_official	330:c80ac197fa6a	1933	((SOURCE) == RCC_USBPLLCLK_DIV1_5))
mbed_official	330:c80ac197fa6a	1934	/**
mbed_official	330:c80ac197fa6a	1935	* @}
mbed_official	330:c80ac197fa6a	1936	*/
mbed_official	330:c80ac197fa6a	1937
mbed_official	330:c80ac197fa6a	1938	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
mbed_official	330:c80ac197fa6a	1939	/* STM32F302xC \|\| STM32F303xC \|\| */
mbed_official	330:c80ac197fa6a	1940	/* STM32F302x8 \|\| */
mbed_official	330:c80ac197fa6a	1941	/* STM32F373xC */
mbed_official	330:c80ac197fa6a	1942
mbed_official	330:c80ac197fa6a	1943	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	1944	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	1945	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
mbed_official	330:c80ac197fa6a	1946	* @{
mbed_official	330:c80ac197fa6a	1947	*/
mbed_official	330:c80ac197fa6a	1948	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
mbed_official	330:c80ac197fa6a	1949
mbed_official	330:c80ac197fa6a	1950	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
mbed_official	330:c80ac197fa6a	1951	/**
mbed_official	330:c80ac197fa6a	1952	* @}
mbed_official	330:c80ac197fa6a	1953	*/
mbed_official	330:c80ac197fa6a	1954	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	1955	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	1956
mbed_official	330:c80ac197fa6a	1957	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	1958	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	1959	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	1960
mbed_official	330:c80ac197fa6a	1961	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
mbed_official	330:c80ac197fa6a	1962	* @{
mbed_official	330:c80ac197fa6a	1963	*/
mbed_official	330:c80ac197fa6a	1964	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
mbed_official	330:c80ac197fa6a	1965	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
mbed_official	330:c80ac197fa6a	1966	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
mbed_official	330:c80ac197fa6a	1967	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
mbed_official	330:c80ac197fa6a	1968	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
mbed_official	330:c80ac197fa6a	1969	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
mbed_official	330:c80ac197fa6a	1970	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
mbed_official	330:c80ac197fa6a	1971	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
mbed_official	330:c80ac197fa6a	1972
mbed_official	330:c80ac197fa6a	1973	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
mbed_official	330:c80ac197fa6a	1974	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
mbed_official	330:c80ac197fa6a	1975	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
mbed_official	330:c80ac197fa6a	1976	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
mbed_official	330:c80ac197fa6a	1977	/**
mbed_official	330:c80ac197fa6a	1978	* @}
mbed_official	330:c80ac197fa6a	1979	*/
mbed_official	330:c80ac197fa6a	1980
mbed_official	330:c80ac197fa6a	1981	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	1982	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	1983	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	1984
mbed_official	330:c80ac197fa6a	1985	/**
mbed_official	330:c80ac197fa6a	1986	* @}
mbed_official	330:c80ac197fa6a	1987	*/
mbed_official	330:c80ac197fa6a	1988
mbed_official	330:c80ac197fa6a	1989	/* Exported macro ------------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	1990	/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
mbed_official	330:c80ac197fa6a	1991	* @{
mbed_official	330:c80ac197fa6a	1992	*/
mbed_official	330:c80ac197fa6a	1993
mbed_official	330:c80ac197fa6a	1994	/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
mbed_official	330:c80ac197fa6a	1995	* @{
mbed_official	330:c80ac197fa6a	1996	*/
mbed_official	330:c80ac197fa6a	1997	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	1998	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
mbed_official	330:c80ac197fa6a	1999	* @note This macro must be used only when the PLL is disabled.
mbed_official	330:c80ac197fa6a	2000	*
mbed_official	330:c80ac197fa6a	2001	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	330:c80ac197fa6a	2002	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2003	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	330:c80ac197fa6a	2004	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	330:c80ac197fa6a	2005	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	2006	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
mbed_official	330:c80ac197fa6a	2007	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	2008	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
mbed_official	330:c80ac197fa6a	2009	*
mbed_official	330:c80ac197fa6a	2010	*/
mbed_official	330:c80ac197fa6a	2011	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
mbed_official	330:c80ac197fa6a	2012	do { \
mbed_official	330:c80ac197fa6a	2013	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
mbed_official	330:c80ac197fa6a	2014	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
mbed_official	330:c80ac197fa6a	2015	} while(0)
mbed_official	330:c80ac197fa6a	2016	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2017
mbed_official	330:c80ac197fa6a	2018	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2019	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2020	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	330:c80ac197fa6a	2021	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2022	/** @brief Macro to configure the PLL clock source and multiplication factor.
mbed_official	330:c80ac197fa6a	2023	* @note This macro must be used only when the PLL is disabled.
mbed_official	330:c80ac197fa6a	2024	*
mbed_official	330:c80ac197fa6a	2025	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	330:c80ac197fa6a	2026	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2027	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	330:c80ac197fa6a	2028	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	330:c80ac197fa6a	2029	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
mbed_official	330:c80ac197fa6a	2030	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
mbed_official	330:c80ac197fa6a	2031	*
mbed_official	330:c80ac197fa6a	2032	*/
mbed_official	330:c80ac197fa6a	2033	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
mbed_official	330:c80ac197fa6a	2034	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__)))
mbed_official	330:c80ac197fa6a	2035	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2036	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2037	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2038	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2039	/**
mbed_official	330:c80ac197fa6a	2040	* @}
mbed_official	330:c80ac197fa6a	2041	*/
mbed_official	330:c80ac197fa6a	2042
mbed_official	330:c80ac197fa6a	2043	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2044	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2045	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	330:c80ac197fa6a	2046	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2047	/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
mbed_official	330:c80ac197fa6a	2048	* @{
mbed_official	330:c80ac197fa6a	2049	*/
mbed_official	330:c80ac197fa6a	2050
mbed_official	330:c80ac197fa6a	2051	/**
mbed_official	330:c80ac197fa6a	2052	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
mbed_official	330:c80ac197fa6a	2053	* @note Predivision factor can not be changed if PLL is used as system clock
mbed_official	330:c80ac197fa6a	2054	* In this case, you have to select another source of the system clock, disable the PLL and
mbed_official	330:c80ac197fa6a	2055	* then change the HSE predivision factor.
mbed_official	330:c80ac197fa6a	2056	* @param __HSEPredivValue__: specifies the division value applied to HSE.
mbed_official	330:c80ac197fa6a	2057	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
mbed_official	330:c80ac197fa6a	2058	*/
mbed_official	330:c80ac197fa6a	2059	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
mbed_official	330:c80ac197fa6a	2060	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
mbed_official	330:c80ac197fa6a	2061	/**
mbed_official	330:c80ac197fa6a	2062	* @}
mbed_official	330:c80ac197fa6a	2063	*/
mbed_official	330:c80ac197fa6a	2064	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2065	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2066	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2067	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2068
mbed_official	330:c80ac197fa6a	2069	/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
mbed_official	330:c80ac197fa6a	2070	* @brief Enable or disable the AHB peripheral clock.
mbed_official	330:c80ac197fa6a	2071	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	330:c80ac197fa6a	2072	* is disabled and the application software has to enable this clock before
mbed_official	330:c80ac197fa6a	2073	* using it.
mbed_official	330:c80ac197fa6a	2074	* @{
mbed_official	330:c80ac197fa6a	2075	*/
mbed_official	330:c80ac197fa6a	2076	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2077	#define __ADC1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC1EN))
mbed_official	330:c80ac197fa6a	2078
mbed_official	330:c80ac197fa6a	2079	#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
mbed_official	330:c80ac197fa6a	2080	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2081
mbed_official	330:c80ac197fa6a	2082	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2083	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2084	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	330:c80ac197fa6a	2085	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	330:c80ac197fa6a	2086	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
mbed_official	330:c80ac197fa6a	2087	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2088	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	330:c80ac197fa6a	2089	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	330:c80ac197fa6a	2090
mbed_official	330:c80ac197fa6a	2091	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	330:c80ac197fa6a	2092	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	330:c80ac197fa6a	2093	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
mbed_official	330:c80ac197fa6a	2094	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2095	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	330:c80ac197fa6a	2096	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	330:c80ac197fa6a	2097	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2098	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2099
mbed_official	330:c80ac197fa6a	2100	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2101	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2102	#define __ADC34_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC34EN))
mbed_official	330:c80ac197fa6a	2103
mbed_official	330:c80ac197fa6a	2104	#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
mbed_official	330:c80ac197fa6a	2105	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2106	/* STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2107
mbed_official	330:c80ac197fa6a	2108	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2109	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
mbed_official	330:c80ac197fa6a	2110	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2111	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	330:c80ac197fa6a	2112	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	330:c80ac197fa6a	2113
mbed_official	330:c80ac197fa6a	2114	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
mbed_official	330:c80ac197fa6a	2115	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2116	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	330:c80ac197fa6a	2117	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	330:c80ac197fa6a	2118	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2119
mbed_official	330:c80ac197fa6a	2120	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2121	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	330:c80ac197fa6a	2122	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	330:c80ac197fa6a	2123
mbed_official	330:c80ac197fa6a	2124	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	330:c80ac197fa6a	2125	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	330:c80ac197fa6a	2126	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2127
mbed_official	330:c80ac197fa6a	2128	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2129	#define __FMC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FMCEN))
mbed_official	330:c80ac197fa6a	2130	#define __GPIOG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOGEN))
mbed_official	330:c80ac197fa6a	2131	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
mbed_official	330:c80ac197fa6a	2132
mbed_official	330:c80ac197fa6a	2133	#define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
mbed_official	330:c80ac197fa6a	2134	#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
mbed_official	330:c80ac197fa6a	2135	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
mbed_official	330:c80ac197fa6a	2136	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2137	/**
mbed_official	330:c80ac197fa6a	2138	* @}
mbed_official	330:c80ac197fa6a	2139	*/
mbed_official	330:c80ac197fa6a	2140
mbed_official	330:c80ac197fa6a	2141	/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
mbed_official	330:c80ac197fa6a	2142	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	330:c80ac197fa6a	2143	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	330:c80ac197fa6a	2144	* is disabled and the application software has to enable this clock before
mbed_official	330:c80ac197fa6a	2145	* using it.
mbed_official	330:c80ac197fa6a	2146	* @{
mbed_official	330:c80ac197fa6a	2147	*/
mbed_official	330:c80ac197fa6a	2148	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2149	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2150	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2151	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2152	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	330:c80ac197fa6a	2153
mbed_official	330:c80ac197fa6a	2154	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2155	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2156	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2157	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	330:c80ac197fa6a	2158	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2159
mbed_official	330:c80ac197fa6a	2160	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2161	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2162	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2163	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	330:c80ac197fa6a	2164	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2165	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2166	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
mbed_official	330:c80ac197fa6a	2167	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
mbed_official	330:c80ac197fa6a	2168	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2169
mbed_official	330:c80ac197fa6a	2170	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2171	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	330:c80ac197fa6a	2172	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2173	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2174	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	330:c80ac197fa6a	2175	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	330:c80ac197fa6a	2176	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2177	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2178	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2179
mbed_official	330:c80ac197fa6a	2180	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2181	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2182	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
mbed_official	330:c80ac197fa6a	2183
mbed_official	330:c80ac197fa6a	2184	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2185	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
mbed_official	330:c80ac197fa6a	2186	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2187
mbed_official	330:c80ac197fa6a	2188	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2189	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2190	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	330:c80ac197fa6a	2191	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
mbed_official	330:c80ac197fa6a	2192	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
mbed_official	330:c80ac197fa6a	2193	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
mbed_official	330:c80ac197fa6a	2194	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
mbed_official	330:c80ac197fa6a	2195	#define __TIM18_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM18EN))
mbed_official	330:c80ac197fa6a	2196	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2197	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2198	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2199	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
mbed_official	330:c80ac197fa6a	2200	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
mbed_official	330:c80ac197fa6a	2201
mbed_official	330:c80ac197fa6a	2202	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	330:c80ac197fa6a	2203	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	330:c80ac197fa6a	2204	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	330:c80ac197fa6a	2205	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	330:c80ac197fa6a	2206	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	330:c80ac197fa6a	2207	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	330:c80ac197fa6a	2208	#define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
mbed_official	330:c80ac197fa6a	2209	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	330:c80ac197fa6a	2210	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	330:c80ac197fa6a	2211	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	330:c80ac197fa6a	2212	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
mbed_official	330:c80ac197fa6a	2213	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	330:c80ac197fa6a	2214	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2215
mbed_official	330:c80ac197fa6a	2216	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2217	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2218	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2219	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2220	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	330:c80ac197fa6a	2221
mbed_official	330:c80ac197fa6a	2222	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	330:c80ac197fa6a	2223	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2224	/* STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2225	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2226	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2227
mbed_official	330:c80ac197fa6a	2228	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
mbed_official	330:c80ac197fa6a	2229	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
mbed_official	330:c80ac197fa6a	2230	defined(STM32F302x8) \|\| \
mbed_official	330:c80ac197fa6a	2231	defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	2232	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	330:c80ac197fa6a	2233
mbed_official	330:c80ac197fa6a	2234	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	330:c80ac197fa6a	2235	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
mbed_official	330:c80ac197fa6a	2236	/* STM32F302xC \|\| STM32F303xC \|\| */
mbed_official	330:c80ac197fa6a	2237	/* STM32F302x8 \|\| */
mbed_official	330:c80ac197fa6a	2238	/* STM32F373xC */
mbed_official	330:c80ac197fa6a	2239
mbed_official	330:c80ac197fa6a	2240	#if !defined(STM32F301x8)
mbed_official	330:c80ac197fa6a	2241	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
mbed_official	330:c80ac197fa6a	2242
mbed_official	330:c80ac197fa6a	2243	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
mbed_official	330:c80ac197fa6a	2244	#endif /* STM32F301x8*/
mbed_official	330:c80ac197fa6a	2245
mbed_official	330:c80ac197fa6a	2246	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2247	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	330:c80ac197fa6a	2248
mbed_official	330:c80ac197fa6a	2249	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	330:c80ac197fa6a	2250	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2251	/**
mbed_official	330:c80ac197fa6a	2252	* @}
mbed_official	330:c80ac197fa6a	2253	*/
mbed_official	330:c80ac197fa6a	2254
mbed_official	330:c80ac197fa6a	2255	/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
mbed_official	330:c80ac197fa6a	2256	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	330:c80ac197fa6a	2257	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	330:c80ac197fa6a	2258	* is disabled and the application software has to enable this clock before
mbed_official	330:c80ac197fa6a	2259	* using it.
mbed_official	330:c80ac197fa6a	2260	* @{
mbed_official	330:c80ac197fa6a	2261	*/
mbed_official	330:c80ac197fa6a	2262	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2263	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2264	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2265
mbed_official	330:c80ac197fa6a	2266	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2267	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2268	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2269
mbed_official	330:c80ac197fa6a	2270	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2271	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2272	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
mbed_official	330:c80ac197fa6a	2273
mbed_official	330:c80ac197fa6a	2274	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	330:c80ac197fa6a	2275	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2276	/* STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2277
mbed_official	330:c80ac197fa6a	2278	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2279	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2280
mbed_official	330:c80ac197fa6a	2281	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2282	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2283
mbed_official	330:c80ac197fa6a	2284	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	2285	#define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_HRTIM1EN))
mbed_official	330:c80ac197fa6a	2286
mbed_official	330:c80ac197fa6a	2287	#define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
mbed_official	330:c80ac197fa6a	2288	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	2289
mbed_official	330:c80ac197fa6a	2290	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2291	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	330:c80ac197fa6a	2292	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2293	#define __TIM19_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM19EN))
mbed_official	330:c80ac197fa6a	2294	#define __SDADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC1EN))
mbed_official	330:c80ac197fa6a	2295	#define __SDADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC2EN))
mbed_official	330:c80ac197fa6a	2296	#define __SDADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC3EN))
mbed_official	330:c80ac197fa6a	2297
mbed_official	330:c80ac197fa6a	2298	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	330:c80ac197fa6a	2299	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	330:c80ac197fa6a	2300	#define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
mbed_official	330:c80ac197fa6a	2301	#define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
mbed_official	330:c80ac197fa6a	2302	#define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
mbed_official	330:c80ac197fa6a	2303	#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
mbed_official	330:c80ac197fa6a	2304	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2305
mbed_official	330:c80ac197fa6a	2306	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2307	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2308	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2309	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2310	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
mbed_official	330:c80ac197fa6a	2311
mbed_official	330:c80ac197fa6a	2312	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	330:c80ac197fa6a	2313	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2314	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2315	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2316	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2317
mbed_official	330:c80ac197fa6a	2318	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2319	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
mbed_official	330:c80ac197fa6a	2320
mbed_official	330:c80ac197fa6a	2321	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official	330:c80ac197fa6a	2322	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2323
mbed_official	330:c80ac197fa6a	2324	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2325	#define __TIM20_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM20EN))
mbed_official	330:c80ac197fa6a	2326
mbed_official	330:c80ac197fa6a	2327	#define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
mbed_official	330:c80ac197fa6a	2328	#endif /* STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2329
mbed_official	330:c80ac197fa6a	2330	/**
mbed_official	330:c80ac197fa6a	2331	* @}
mbed_official	330:c80ac197fa6a	2332	*/
mbed_official	330:c80ac197fa6a	2333
mbed_official	330:c80ac197fa6a	2334	/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
mbed_official	330:c80ac197fa6a	2335	* @brief Force or release AHB peripheral reset.
mbed_official	330:c80ac197fa6a	2336	* @{
mbed_official	330:c80ac197fa6a	2337	*/
mbed_official	330:c80ac197fa6a	2338	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2339	#define __ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
mbed_official	330:c80ac197fa6a	2340
mbed_official	330:c80ac197fa6a	2341	#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
mbed_official	330:c80ac197fa6a	2342	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2343
mbed_official	330:c80ac197fa6a	2344	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2345	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2346	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	330:c80ac197fa6a	2347	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
mbed_official	330:c80ac197fa6a	2348	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2349	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	330:c80ac197fa6a	2350	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	330:c80ac197fa6a	2351
mbed_official	330:c80ac197fa6a	2352	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	330:c80ac197fa6a	2353	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
mbed_official	330:c80ac197fa6a	2354	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2355	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	330:c80ac197fa6a	2356	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	330:c80ac197fa6a	2357	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2358	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2359
mbed_official	330:c80ac197fa6a	2360	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2361	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2362	#define __ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
mbed_official	330:c80ac197fa6a	2363
mbed_official	330:c80ac197fa6a	2364	#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
mbed_official	330:c80ac197fa6a	2365	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2366	/* STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2367
mbed_official	330:c80ac197fa6a	2368	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2369	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
mbed_official	330:c80ac197fa6a	2370	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2371	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	330:c80ac197fa6a	2372	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	330:c80ac197fa6a	2373
mbed_official	330:c80ac197fa6a	2374	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
mbed_official	330:c80ac197fa6a	2375	/* Aliases for STM32 F3 compatibility */
mbed_official	330:c80ac197fa6a	2376	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	330:c80ac197fa6a	2377	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	330:c80ac197fa6a	2378	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2379
mbed_official	330:c80ac197fa6a	2380	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2381	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	330:c80ac197fa6a	2382
mbed_official	330:c80ac197fa6a	2383	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	330:c80ac197fa6a	2384	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2385
mbed_official	330:c80ac197fa6a	2386	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2387	#define __FMC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FMCRST))
mbed_official	330:c80ac197fa6a	2388	#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOGRST))
mbed_official	330:c80ac197fa6a	2389	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
mbed_official	330:c80ac197fa6a	2390
mbed_official	330:c80ac197fa6a	2391	#define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
mbed_official	330:c80ac197fa6a	2392	#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
mbed_official	330:c80ac197fa6a	2393	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
mbed_official	330:c80ac197fa6a	2394	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2395	/**
mbed_official	330:c80ac197fa6a	2396	* @}
mbed_official	330:c80ac197fa6a	2397	*/
mbed_official	330:c80ac197fa6a	2398
mbed_official	330:c80ac197fa6a	2399	/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
mbed_official	330:c80ac197fa6a	2400	* @brief Force or release APB1 peripheral reset.
mbed_official	330:c80ac197fa6a	2401	* @{
mbed_official	330:c80ac197fa6a	2402	*/
mbed_official	330:c80ac197fa6a	2403	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2404	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2405	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2406	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2407	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	330:c80ac197fa6a	2408
mbed_official	330:c80ac197fa6a	2409	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2410	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2411	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2412	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	330:c80ac197fa6a	2413	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2414
mbed_official	330:c80ac197fa6a	2415	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2416	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2417	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2418	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	330:c80ac197fa6a	2419	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2420	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2421	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	330:c80ac197fa6a	2422	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	330:c80ac197fa6a	2423	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2424
mbed_official	330:c80ac197fa6a	2425	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2426	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	330:c80ac197fa6a	2427	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2428	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2429	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	330:c80ac197fa6a	2430	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	330:c80ac197fa6a	2431	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2432	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2433	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2434
mbed_official	330:c80ac197fa6a	2435	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2436	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2437	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
mbed_official	330:c80ac197fa6a	2438
mbed_official	330:c80ac197fa6a	2439	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2440	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
mbed_official	330:c80ac197fa6a	2441	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2442
mbed_official	330:c80ac197fa6a	2443	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2444	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2445	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	330:c80ac197fa6a	2446	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	330:c80ac197fa6a	2447	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	330:c80ac197fa6a	2448	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	330:c80ac197fa6a	2449	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	330:c80ac197fa6a	2450	#define __TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
mbed_official	330:c80ac197fa6a	2451	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2452	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2453	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2454	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
mbed_official	330:c80ac197fa6a	2455	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	330:c80ac197fa6a	2456
mbed_official	330:c80ac197fa6a	2457	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	330:c80ac197fa6a	2458	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	330:c80ac197fa6a	2459	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	330:c80ac197fa6a	2460	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	330:c80ac197fa6a	2461	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	330:c80ac197fa6a	2462	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	330:c80ac197fa6a	2463	#define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
mbed_official	330:c80ac197fa6a	2464	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	330:c80ac197fa6a	2465	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	330:c80ac197fa6a	2466	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	330:c80ac197fa6a	2467	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
mbed_official	330:c80ac197fa6a	2468	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	330:c80ac197fa6a	2469	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2470
mbed_official	330:c80ac197fa6a	2471	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2472	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2473	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2474	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2475	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	330:c80ac197fa6a	2476
mbed_official	330:c80ac197fa6a	2477	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	330:c80ac197fa6a	2478	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2479	/* STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2480	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2481	/* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2482
mbed_official	330:c80ac197fa6a	2483	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
mbed_official	330:c80ac197fa6a	2484	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
mbed_official	330:c80ac197fa6a	2485	defined(STM32F302x8) \|\| \
mbed_official	330:c80ac197fa6a	2486	defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	2487	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	330:c80ac197fa6a	2488
mbed_official	330:c80ac197fa6a	2489	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	330:c80ac197fa6a	2490	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
mbed_official	330:c80ac197fa6a	2491	/* STM32F302xC \|\| STM32F303xC \|\| */
mbed_official	330:c80ac197fa6a	2492	/* STM32F302x8 \|\| */
mbed_official	330:c80ac197fa6a	2493	/* STM32F373xC */
mbed_official	330:c80ac197fa6a	2494
mbed_official	330:c80ac197fa6a	2495	#if !defined(STM32F301x8)
mbed_official	330:c80ac197fa6a	2496	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
mbed_official	330:c80ac197fa6a	2497
mbed_official	330:c80ac197fa6a	2498	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
mbed_official	330:c80ac197fa6a	2499	#endif /* STM32F301x8*/
mbed_official	330:c80ac197fa6a	2500
mbed_official	330:c80ac197fa6a	2501	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2502	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	330:c80ac197fa6a	2503
mbed_official	330:c80ac197fa6a	2504	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	330:c80ac197fa6a	2505	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2506	/**
mbed_official	330:c80ac197fa6a	2507	* @}
mbed_official	330:c80ac197fa6a	2508	*/
mbed_official	330:c80ac197fa6a	2509
mbed_official	330:c80ac197fa6a	2510	/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
mbed_official	330:c80ac197fa6a	2511	* @brief Force or release APB2 peripheral reset.
mbed_official	330:c80ac197fa6a	2512	* @{
mbed_official	330:c80ac197fa6a	2513	*/
mbed_official	330:c80ac197fa6a	2514	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2515	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2516	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2517
mbed_official	330:c80ac197fa6a	2518	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2519	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2520	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2521
mbed_official	330:c80ac197fa6a	2522	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2523	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2524	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	330:c80ac197fa6a	2525
mbed_official	330:c80ac197fa6a	2526	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	330:c80ac197fa6a	2527	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2528	/* STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2529
mbed_official	330:c80ac197fa6a	2530	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	2531	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2532
mbed_official	330:c80ac197fa6a	2533	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2534	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	2535
mbed_official	330:c80ac197fa6a	2536	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	2537	#define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
mbed_official	330:c80ac197fa6a	2538
mbed_official	330:c80ac197fa6a	2539	#define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
mbed_official	330:c80ac197fa6a	2540	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	2541
mbed_official	330:c80ac197fa6a	2542	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	2543	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	330:c80ac197fa6a	2544	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2545	#define __TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
mbed_official	330:c80ac197fa6a	2546	#define __SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
mbed_official	330:c80ac197fa6a	2547	#define __SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
mbed_official	330:c80ac197fa6a	2548	#define __SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
mbed_official	330:c80ac197fa6a	2549
mbed_official	330:c80ac197fa6a	2550	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	330:c80ac197fa6a	2551	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	330:c80ac197fa6a	2552	#define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
mbed_official	330:c80ac197fa6a	2553	#define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
mbed_official	330:c80ac197fa6a	2554	#define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
mbed_official	330:c80ac197fa6a	2555	#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
mbed_official	330:c80ac197fa6a	2556	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	2557
mbed_official	330:c80ac197fa6a	2558	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2559	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	330:c80ac197fa6a	2560	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	2561	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2562	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	330:c80ac197fa6a	2563
mbed_official	330:c80ac197fa6a	2564	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	330:c80ac197fa6a	2565	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2566	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	330:c80ac197fa6a	2567	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	2568	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2569
mbed_official	330:c80ac197fa6a	2570	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2571	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
mbed_official	330:c80ac197fa6a	2572
mbed_official	330:c80ac197fa6a	2573	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official	330:c80ac197fa6a	2574	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2575
mbed_official	330:c80ac197fa6a	2576	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	2577	#define __TIM20_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM20RST))
mbed_official	330:c80ac197fa6a	2578
mbed_official	330:c80ac197fa6a	2579	#define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
mbed_official	330:c80ac197fa6a	2580	#endif /* STM32F303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	2581
mbed_official	330:c80ac197fa6a	2582	/**
mbed_official	330:c80ac197fa6a	2583	* @}
mbed_official	330:c80ac197fa6a	2584	*/
mbed_official	330:c80ac197fa6a	2585
mbed_official	330:c80ac197fa6a	2586	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	2587	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
mbed_official	330:c80ac197fa6a	2588	* @{
mbed_official	330:c80ac197fa6a	2589	*/
mbed_official	330:c80ac197fa6a	2590
mbed_official	330:c80ac197fa6a	2591	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	330:c80ac197fa6a	2592	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	330:c80ac197fa6a	2593	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2594	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2595	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2596	*/
mbed_official	330:c80ac197fa6a	2597	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	330:c80ac197fa6a	2598	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	330:c80ac197fa6a	2599
mbed_official	330:c80ac197fa6a	2600	/** @brief Macro to get the I2C2 clock source.
mbed_official	330:c80ac197fa6a	2601	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2602	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2603	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2604	*/
mbed_official	330:c80ac197fa6a	2605	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	330:c80ac197fa6a	2606
mbed_official	330:c80ac197fa6a	2607	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
mbed_official	330:c80ac197fa6a	2608	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
mbed_official	330:c80ac197fa6a	2609	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2610	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	330:c80ac197fa6a	2611	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	330:c80ac197fa6a	2612	*/
mbed_official	330:c80ac197fa6a	2613	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
mbed_official	330:c80ac197fa6a	2614	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
mbed_official	330:c80ac197fa6a	2615
mbed_official	330:c80ac197fa6a	2616	/** @brief Macro to get the I2C3 clock source.
mbed_official	330:c80ac197fa6a	2617	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2618	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	330:c80ac197fa6a	2619	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	330:c80ac197fa6a	2620	*/
mbed_official	330:c80ac197fa6a	2621	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
mbed_official	330:c80ac197fa6a	2622
mbed_official	330:c80ac197fa6a	2623	/**
mbed_official	330:c80ac197fa6a	2624	* @}
mbed_official	330:c80ac197fa6a	2625	*/
mbed_official	330:c80ac197fa6a	2626
mbed_official	330:c80ac197fa6a	2627	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	2628	* @{
mbed_official	330:c80ac197fa6a	2629	*/
mbed_official	330:c80ac197fa6a	2630	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	2631	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	330:c80ac197fa6a	2632	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2633	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2634	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2635	*/
mbed_official	330:c80ac197fa6a	2636	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	330:c80ac197fa6a	2637	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	330:c80ac197fa6a	2638
mbed_official	330:c80ac197fa6a	2639	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	2640	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2641	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2642	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2643	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2644	*/
mbed_official	330:c80ac197fa6a	2645	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	330:c80ac197fa6a	2646
mbed_official	330:c80ac197fa6a	2647	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
mbed_official	330:c80ac197fa6a	2648	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
mbed_official	330:c80ac197fa6a	2649	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2650	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
mbed_official	330:c80ac197fa6a	2651	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
mbed_official	330:c80ac197fa6a	2652	*/
mbed_official	330:c80ac197fa6a	2653	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
mbed_official	330:c80ac197fa6a	2654	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
mbed_official	330:c80ac197fa6a	2655
mbed_official	330:c80ac197fa6a	2656	/** @brief Macro to get the TIM15 clock (TIM15CLK).
mbed_official	330:c80ac197fa6a	2657	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2658	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2659	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
mbed_official	330:c80ac197fa6a	2660	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
mbed_official	330:c80ac197fa6a	2661	*/
mbed_official	330:c80ac197fa6a	2662	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
mbed_official	330:c80ac197fa6a	2663
mbed_official	330:c80ac197fa6a	2664	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
mbed_official	330:c80ac197fa6a	2665	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
mbed_official	330:c80ac197fa6a	2666	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2667	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
mbed_official	330:c80ac197fa6a	2668	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
mbed_official	330:c80ac197fa6a	2669	*/
mbed_official	330:c80ac197fa6a	2670	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
mbed_official	330:c80ac197fa6a	2671	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
mbed_official	330:c80ac197fa6a	2672
mbed_official	330:c80ac197fa6a	2673	/** @brief Macro to get the TIM16 clock (TIM16CLK).
mbed_official	330:c80ac197fa6a	2674	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2675	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2676	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
mbed_official	330:c80ac197fa6a	2677	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
mbed_official	330:c80ac197fa6a	2678	*/
mbed_official	330:c80ac197fa6a	2679	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
mbed_official	330:c80ac197fa6a	2680
mbed_official	330:c80ac197fa6a	2681	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
mbed_official	330:c80ac197fa6a	2682	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
mbed_official	330:c80ac197fa6a	2683	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2684	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
mbed_official	330:c80ac197fa6a	2685	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
mbed_official	330:c80ac197fa6a	2686	*/
mbed_official	330:c80ac197fa6a	2687	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
mbed_official	330:c80ac197fa6a	2688	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
mbed_official	330:c80ac197fa6a	2689
mbed_official	330:c80ac197fa6a	2690	/** @brief Macro to get the TIM17 clock (TIM17CLK).
mbed_official	330:c80ac197fa6a	2691	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2692	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2693	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
mbed_official	330:c80ac197fa6a	2694	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
mbed_official	330:c80ac197fa6a	2695	*/
mbed_official	330:c80ac197fa6a	2696	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
mbed_official	330:c80ac197fa6a	2697
mbed_official	330:c80ac197fa6a	2698	/**
mbed_official	330:c80ac197fa6a	2699	* @}
mbed_official	330:c80ac197fa6a	2700	*/
mbed_official	330:c80ac197fa6a	2701
mbed_official	330:c80ac197fa6a	2702	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
mbed_official	330:c80ac197fa6a	2703	* @{
mbed_official	330:c80ac197fa6a	2704	*/
mbed_official	330:c80ac197fa6a	2705	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	330:c80ac197fa6a	2706	* @note This function must be called before enabling the I2S APB clock.
mbed_official	330:c80ac197fa6a	2707	* @param __I2SCLKSource__: specifies the I2S clock source.
mbed_official	330:c80ac197fa6a	2708	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2709	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	330:c80ac197fa6a	2710	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	330:c80ac197fa6a	2711	* used as I2S clock source
mbed_official	330:c80ac197fa6a	2712	*/
mbed_official	330:c80ac197fa6a	2713	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
mbed_official	330:c80ac197fa6a	2714	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
mbed_official	330:c80ac197fa6a	2715
mbed_official	330:c80ac197fa6a	2716	/** @brief Macro to get the I2S clock source (I2SCLK).
mbed_official	330:c80ac197fa6a	2717	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2718	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	330:c80ac197fa6a	2719	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	330:c80ac197fa6a	2720	* used as I2S clock source
mbed_official	330:c80ac197fa6a	2721	*/
mbed_official	330:c80ac197fa6a	2722	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
mbed_official	330:c80ac197fa6a	2723	/**
mbed_official	330:c80ac197fa6a	2724	* @}
mbed_official	330:c80ac197fa6a	2725	*/
mbed_official	330:c80ac197fa6a	2726
mbed_official	330:c80ac197fa6a	2727	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
mbed_official	330:c80ac197fa6a	2728	* @{
mbed_official	330:c80ac197fa6a	2729	*/
mbed_official	330:c80ac197fa6a	2730
mbed_official	330:c80ac197fa6a	2731	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
mbed_official	330:c80ac197fa6a	2732	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
mbed_official	330:c80ac197fa6a	2733	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2734	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
mbed_official	330:c80ac197fa6a	2735	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2736	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2737	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2738	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2739	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2740	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2741	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2742	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2743	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2744	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2745	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2746	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2747	*/
mbed_official	330:c80ac197fa6a	2748	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
mbed_official	330:c80ac197fa6a	2749	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
mbed_official	330:c80ac197fa6a	2750
mbed_official	330:c80ac197fa6a	2751	/** @brief Macro to get the ADC1 clock
mbed_official	330:c80ac197fa6a	2752	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2753	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
mbed_official	330:c80ac197fa6a	2754	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2755	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2756	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2757	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2758	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2759	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2760	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2761	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2762	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2763	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2764	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2765	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	2766	*/
mbed_official	330:c80ac197fa6a	2767	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
mbed_official	330:c80ac197fa6a	2768	/**
mbed_official	330:c80ac197fa6a	2769	* @}
mbed_official	330:c80ac197fa6a	2770	*/
mbed_official	330:c80ac197fa6a	2771
mbed_official	330:c80ac197fa6a	2772	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	2773
mbed_official	330:c80ac197fa6a	2774	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2775	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2776	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
mbed_official	330:c80ac197fa6a	2777	* @{
mbed_official	330:c80ac197fa6a	2778	*/
mbed_official	330:c80ac197fa6a	2779
mbed_official	330:c80ac197fa6a	2780	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	330:c80ac197fa6a	2781	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	330:c80ac197fa6a	2782	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2783	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2784	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2785	*/
mbed_official	330:c80ac197fa6a	2786	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	330:c80ac197fa6a	2787	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	330:c80ac197fa6a	2788
mbed_official	330:c80ac197fa6a	2789	/** @brief Macro to get the I2C2 clock source.
mbed_official	330:c80ac197fa6a	2790	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2791	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2792	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	2793	*/
mbed_official	330:c80ac197fa6a	2794	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	330:c80ac197fa6a	2795	/**
mbed_official	330:c80ac197fa6a	2796	* @}
mbed_official	330:c80ac197fa6a	2797	*/
mbed_official	330:c80ac197fa6a	2798
mbed_official	330:c80ac197fa6a	2799	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
mbed_official	330:c80ac197fa6a	2800	* @{
mbed_official	330:c80ac197fa6a	2801	*/
mbed_official	330:c80ac197fa6a	2802
mbed_official	330:c80ac197fa6a	2803	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
mbed_official	330:c80ac197fa6a	2804	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
mbed_official	330:c80ac197fa6a	2805	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2806	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	330:c80ac197fa6a	2807	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2808	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2809	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2810	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2811	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2812	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2813	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2814	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2815	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2816	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2817	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2818	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2819	*/
mbed_official	330:c80ac197fa6a	2820	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
mbed_official	330:c80ac197fa6a	2821	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
mbed_official	330:c80ac197fa6a	2822
mbed_official	330:c80ac197fa6a	2823	/** @brief Macro to get the ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2824	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2825	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	330:c80ac197fa6a	2826	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2827	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2828	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2829	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2830	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2831	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2832	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2833	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2834	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2835	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2836	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2837	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	2838	*/
mbed_official	330:c80ac197fa6a	2839	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
mbed_official	330:c80ac197fa6a	2840	/**
mbed_official	330:c80ac197fa6a	2841	* @}
mbed_official	330:c80ac197fa6a	2842	*/
mbed_official	330:c80ac197fa6a	2843
mbed_official	330:c80ac197fa6a	2844	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	2845	* @{
mbed_official	330:c80ac197fa6a	2846	*/
mbed_official	330:c80ac197fa6a	2847
mbed_official	330:c80ac197fa6a	2848	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	2849	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	330:c80ac197fa6a	2850	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2851	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2852	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2853	*/
mbed_official	330:c80ac197fa6a	2854	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	330:c80ac197fa6a	2855	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	330:c80ac197fa6a	2856
mbed_official	330:c80ac197fa6a	2857	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	2858	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2859	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2860	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2861	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	2862	*/
mbed_official	330:c80ac197fa6a	2863	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	330:c80ac197fa6a	2864	/**
mbed_official	330:c80ac197fa6a	2865	* @}
mbed_official	330:c80ac197fa6a	2866	*/
mbed_official	330:c80ac197fa6a	2867
mbed_official	330:c80ac197fa6a	2868	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
mbed_official	330:c80ac197fa6a	2869	* @{
mbed_official	330:c80ac197fa6a	2870	*/
mbed_official	330:c80ac197fa6a	2871
mbed_official	330:c80ac197fa6a	2872	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	330:c80ac197fa6a	2873	* @note This function must be called before enabling the I2S APB clock.
mbed_official	330:c80ac197fa6a	2874	* @param __I2SCLKSource__: specifies the I2S clock source.
mbed_official	330:c80ac197fa6a	2875	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2876	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	330:c80ac197fa6a	2877	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	330:c80ac197fa6a	2878	* used as I2S clock source
mbed_official	330:c80ac197fa6a	2879	*/
mbed_official	330:c80ac197fa6a	2880	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
mbed_official	330:c80ac197fa6a	2881	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
mbed_official	330:c80ac197fa6a	2882
mbed_official	330:c80ac197fa6a	2883	/** @brief Macro to get the I2S clock source (I2SCLK).
mbed_official	330:c80ac197fa6a	2884	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2885	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	330:c80ac197fa6a	2886	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	330:c80ac197fa6a	2887	* used as I2S clock source
mbed_official	330:c80ac197fa6a	2888	*/
mbed_official	330:c80ac197fa6a	2889	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
mbed_official	330:c80ac197fa6a	2890	/**
mbed_official	330:c80ac197fa6a	2891	* @}
mbed_official	330:c80ac197fa6a	2892	*/
mbed_official	330:c80ac197fa6a	2893
mbed_official	330:c80ac197fa6a	2894	/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
mbed_official	330:c80ac197fa6a	2895	* @{
mbed_official	330:c80ac197fa6a	2896	*/
mbed_official	330:c80ac197fa6a	2897
mbed_official	330:c80ac197fa6a	2898	/** @brief Macro to configure the UART4 clock (UART4CLK).
mbed_official	330:c80ac197fa6a	2899	* @param __UART4CLKSource__: specifies the UART4 clock source.
mbed_official	330:c80ac197fa6a	2900	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2901	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official	330:c80ac197fa6a	2902	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official	330:c80ac197fa6a	2903	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official	330:c80ac197fa6a	2904	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official	330:c80ac197fa6a	2905	*/
mbed_official	330:c80ac197fa6a	2906	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
mbed_official	330:c80ac197fa6a	2907	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
mbed_official	330:c80ac197fa6a	2908
mbed_official	330:c80ac197fa6a	2909	/** @brief Macro to get the UART4 clock source.
mbed_official	330:c80ac197fa6a	2910	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2911	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official	330:c80ac197fa6a	2912	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official	330:c80ac197fa6a	2913	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official	330:c80ac197fa6a	2914	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official	330:c80ac197fa6a	2915	*/
mbed_official	330:c80ac197fa6a	2916	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
mbed_official	330:c80ac197fa6a	2917
mbed_official	330:c80ac197fa6a	2918	/** @brief Macro to configure the UART5 clock (UART5CLK).
mbed_official	330:c80ac197fa6a	2919	* @param __UART5CLKSource__: specifies the UART5 clock source.
mbed_official	330:c80ac197fa6a	2920	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2921	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official	330:c80ac197fa6a	2922	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official	330:c80ac197fa6a	2923	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official	330:c80ac197fa6a	2924	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official	330:c80ac197fa6a	2925	*/
mbed_official	330:c80ac197fa6a	2926	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
mbed_official	330:c80ac197fa6a	2927	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
mbed_official	330:c80ac197fa6a	2928
mbed_official	330:c80ac197fa6a	2929	/** @brief Macro to get the UART5 clock source.
mbed_official	330:c80ac197fa6a	2930	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2931	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official	330:c80ac197fa6a	2932	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official	330:c80ac197fa6a	2933	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official	330:c80ac197fa6a	2934	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official	330:c80ac197fa6a	2935	*/
mbed_official	330:c80ac197fa6a	2936	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
mbed_official	330:c80ac197fa6a	2937	/**
mbed_official	330:c80ac197fa6a	2938	* @}
mbed_official	330:c80ac197fa6a	2939	*/
mbed_official	330:c80ac197fa6a	2940	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	2941	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	2942
mbed_official	330:c80ac197fa6a	2943	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	2944	defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	330:c80ac197fa6a	2945	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
mbed_official	330:c80ac197fa6a	2946	* @{
mbed_official	330:c80ac197fa6a	2947	*/
mbed_official	330:c80ac197fa6a	2948
mbed_official	330:c80ac197fa6a	2949	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
mbed_official	330:c80ac197fa6a	2950	* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
mbed_official	330:c80ac197fa6a	2951	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2952	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
mbed_official	330:c80ac197fa6a	2953	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2954	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2955	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2956	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2957	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2958	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2959	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2960	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2961	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2962	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2963	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2964	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2965	*/
mbed_official	330:c80ac197fa6a	2966	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
mbed_official	330:c80ac197fa6a	2967	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
mbed_official	330:c80ac197fa6a	2968
mbed_official	330:c80ac197fa6a	2969	/** @brief Macro to get the ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2970	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	2971	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
mbed_official	330:c80ac197fa6a	2972	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2973	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2974	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2975	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2976	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2977	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2978	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2979	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2980	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2981	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2982	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2983	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
mbed_official	330:c80ac197fa6a	2984	*/
mbed_official	330:c80ac197fa6a	2985	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
mbed_official	330:c80ac197fa6a	2986	/**
mbed_official	330:c80ac197fa6a	2987	* @}
mbed_official	330:c80ac197fa6a	2988	*/
mbed_official	330:c80ac197fa6a	2989
mbed_official	330:c80ac197fa6a	2990	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	2991	* @{
mbed_official	330:c80ac197fa6a	2992	*/
mbed_official	330:c80ac197fa6a	2993
mbed_official	330:c80ac197fa6a	2994	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
mbed_official	330:c80ac197fa6a	2995	* @param __TIM8CLKSource__: specifies the TIM8 clock source.
mbed_official	330:c80ac197fa6a	2996	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	2997	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
mbed_official	330:c80ac197fa6a	2998	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
mbed_official	330:c80ac197fa6a	2999	*/
mbed_official	330:c80ac197fa6a	3000	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
mbed_official	330:c80ac197fa6a	3001	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
mbed_official	330:c80ac197fa6a	3002
mbed_official	330:c80ac197fa6a	3003	/** @brief Macro to get the TIM8 clock (TIM8CLK).
mbed_official	330:c80ac197fa6a	3004	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3005	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3006	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
mbed_official	330:c80ac197fa6a	3007	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
mbed_official	330:c80ac197fa6a	3008	*/
mbed_official	330:c80ac197fa6a	3009	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
mbed_official	330:c80ac197fa6a	3010
mbed_official	330:c80ac197fa6a	3011	/**
mbed_official	330:c80ac197fa6a	3012	* @}
mbed_official	330:c80ac197fa6a	3013	*/
mbed_official	330:c80ac197fa6a	3014	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	3015	/* STM32F303xC \|\| STM32F358xx */
mbed_official	330:c80ac197fa6a	3016
mbed_official	330:c80ac197fa6a	3017	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	330:c80ac197fa6a	3018	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
mbed_official	330:c80ac197fa6a	3019	* @{
mbed_official	330:c80ac197fa6a	3020	*/
mbed_official	330:c80ac197fa6a	3021
mbed_official	330:c80ac197fa6a	3022	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
mbed_official	330:c80ac197fa6a	3023	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
mbed_official	330:c80ac197fa6a	3024	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3025	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	330:c80ac197fa6a	3026	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3027	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3028	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3029	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3030	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3031	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3032	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3033	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3034	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3035	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3036	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3037	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3038	*/
mbed_official	330:c80ac197fa6a	3039	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
mbed_official	330:c80ac197fa6a	3040	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
mbed_official	330:c80ac197fa6a	3041
mbed_official	330:c80ac197fa6a	3042	/** @brief Macro to get the ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3043	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3044	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	330:c80ac197fa6a	3045	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3046	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3047	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3048	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3049	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3050	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3051	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3052	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3053	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3054	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3055	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3056	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	330:c80ac197fa6a	3057	*/
mbed_official	330:c80ac197fa6a	3058	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
mbed_official	330:c80ac197fa6a	3059	/**
mbed_official	330:c80ac197fa6a	3060	* @}
mbed_official	330:c80ac197fa6a	3061	*/
mbed_official	330:c80ac197fa6a	3062
mbed_official	330:c80ac197fa6a	3063	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	3064	* @{
mbed_official	330:c80ac197fa6a	3065	*/
mbed_official	330:c80ac197fa6a	3066	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	3067	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	330:c80ac197fa6a	3068	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3069	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	3070	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	3071	*/
mbed_official	330:c80ac197fa6a	3072	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	330:c80ac197fa6a	3073	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	330:c80ac197fa6a	3074
mbed_official	330:c80ac197fa6a	3075	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	330:c80ac197fa6a	3076	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3077	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3078	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	330:c80ac197fa6a	3079	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	330:c80ac197fa6a	3080	*/
mbed_official	330:c80ac197fa6a	3081	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	330:c80ac197fa6a	3082	/**
mbed_official	330:c80ac197fa6a	3083	* @}
mbed_official	330:c80ac197fa6a	3084	*/
mbed_official	330:c80ac197fa6a	3085	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	330:c80ac197fa6a	3086
mbed_official	330:c80ac197fa6a	3087	#if defined(STM32F334x8)
mbed_official	330:c80ac197fa6a	3088	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
mbed_official	330:c80ac197fa6a	3089	* @{
mbed_official	330:c80ac197fa6a	3090	*/
mbed_official	330:c80ac197fa6a	3091	/** @brief Macro to configure the HRTIM1 clock.
mbed_official	330:c80ac197fa6a	3092	* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
mbed_official	330:c80ac197fa6a	3093	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3094	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
mbed_official	330:c80ac197fa6a	3095	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
mbed_official	330:c80ac197fa6a	3096	*/
mbed_official	330:c80ac197fa6a	3097	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
mbed_official	330:c80ac197fa6a	3098	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
mbed_official	330:c80ac197fa6a	3099
mbed_official	330:c80ac197fa6a	3100	/** @brief Macro to get the HRTIM1 clock source.
mbed_official	330:c80ac197fa6a	3101	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3102	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
mbed_official	330:c80ac197fa6a	3103	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
mbed_official	330:c80ac197fa6a	3104	*/
mbed_official	330:c80ac197fa6a	3105	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
mbed_official	330:c80ac197fa6a	3106	/**
mbed_official	330:c80ac197fa6a	3107	* @}
mbed_official	330:c80ac197fa6a	3108	*/
mbed_official	330:c80ac197fa6a	3109	#endif /* STM32F334x8 */
mbed_official	330:c80ac197fa6a	3110
mbed_official	330:c80ac197fa6a	3111	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	330:c80ac197fa6a	3112	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
mbed_official	330:c80ac197fa6a	3113	* @{
mbed_official	330:c80ac197fa6a	3114	*/
mbed_official	330:c80ac197fa6a	3115	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	330:c80ac197fa6a	3116	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	330:c80ac197fa6a	3117	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3118	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	3119	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	3120	*/
mbed_official	330:c80ac197fa6a	3121	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	330:c80ac197fa6a	3122	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	330:c80ac197fa6a	3123
mbed_official	330:c80ac197fa6a	3124	/** @brief Macro to get the I2C2 clock source.
mbed_official	330:c80ac197fa6a	3125	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3126	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	330:c80ac197fa6a	3127	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	330:c80ac197fa6a	3128	*/
mbed_official	330:c80ac197fa6a	3129	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	330:c80ac197fa6a	3130	/**
mbed_official	330:c80ac197fa6a	3131	* @}
mbed_official	330:c80ac197fa6a	3132	*/
mbed_official	330:c80ac197fa6a	3133
mbed_official	330:c80ac197fa6a	3134	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
mbed_official	330:c80ac197fa6a	3135	* @{
mbed_official	330:c80ac197fa6a	3136	*/
mbed_official	330:c80ac197fa6a	3137	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
mbed_official	330:c80ac197fa6a	3138	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
mbed_official	330:c80ac197fa6a	3139	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3140	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3141	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3142	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3143	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3144	*/
mbed_official	330:c80ac197fa6a	3145	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
mbed_official	330:c80ac197fa6a	3146	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
mbed_official	330:c80ac197fa6a	3147
mbed_official	330:c80ac197fa6a	3148	/** @brief Macro to get the ADC1 clock (ADC1CLK).
mbed_official	330:c80ac197fa6a	3149	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3150	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3151	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3152	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3153	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
mbed_official	330:c80ac197fa6a	3154	*/
mbed_official	330:c80ac197fa6a	3155	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
mbed_official	330:c80ac197fa6a	3156	/**
mbed_official	330:c80ac197fa6a	3157	* @}
mbed_official	330:c80ac197fa6a	3158	*/
mbed_official	330:c80ac197fa6a	3159
mbed_official	330:c80ac197fa6a	3160	/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
mbed_official	330:c80ac197fa6a	3161	* @{
mbed_official	330:c80ac197fa6a	3162	*/
mbed_official	330:c80ac197fa6a	3163	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
mbed_official	330:c80ac197fa6a	3164	* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
mbed_official	330:c80ac197fa6a	3165	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3166	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3167	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3168	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3169	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3170	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3171	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3172	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3173	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3174	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3175	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3176	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3177	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3178	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3179	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3180	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3181	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3182	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3183	*/
mbed_official	330:c80ac197fa6a	3184	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
mbed_official	330:c80ac197fa6a	3185	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
mbed_official	330:c80ac197fa6a	3186
mbed_official	330:c80ac197fa6a	3187	/** @brief Macro to get the SDADCx clock prescaler.
mbed_official	330:c80ac197fa6a	3188	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3189	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3190	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3191	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3192	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3193	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3194	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3195	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3196	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3197	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3198	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3199	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3200	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3201	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3202	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3203	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3204	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3205	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
mbed_official	330:c80ac197fa6a	3206	*/
mbed_official	330:c80ac197fa6a	3207	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
mbed_official	330:c80ac197fa6a	3208	/**
mbed_official	330:c80ac197fa6a	3209	* @}
mbed_official	330:c80ac197fa6a	3210	*/
mbed_official	330:c80ac197fa6a	3211
mbed_official	330:c80ac197fa6a	3212	/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
mbed_official	330:c80ac197fa6a	3213	* @{
mbed_official	330:c80ac197fa6a	3214	*/
mbed_official	330:c80ac197fa6a	3215	/** @brief Macro to configure the CEC clock.
mbed_official	330:c80ac197fa6a	3216	* @param __CECCLKSource__: specifies the CEC clock source.
mbed_official	330:c80ac197fa6a	3217	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3218	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	330:c80ac197fa6a	3219	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	330:c80ac197fa6a	3220	*/
mbed_official	330:c80ac197fa6a	3221	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
mbed_official	330:c80ac197fa6a	3222	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
mbed_official	330:c80ac197fa6a	3223
mbed_official	330:c80ac197fa6a	3224	/** @brief Macro to get the HDMI CEC clock source.
mbed_official	330:c80ac197fa6a	3225	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3226	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	330:c80ac197fa6a	3227	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	330:c80ac197fa6a	3228	*/
mbed_official	330:c80ac197fa6a	3229	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
mbed_official	330:c80ac197fa6a	3230	/**
mbed_official	330:c80ac197fa6a	3231	* @}
mbed_official	330:c80ac197fa6a	3232	*/
mbed_official	330:c80ac197fa6a	3233
mbed_official	330:c80ac197fa6a	3234	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	330:c80ac197fa6a	3235
mbed_official	330:c80ac197fa6a	3236	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
mbed_official	330:c80ac197fa6a	3237	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
mbed_official	330:c80ac197fa6a	3238	defined(STM32F302x8) \|\| \
mbed_official	330:c80ac197fa6a	3239	defined(STM32F373xC)
mbed_official	330:c80ac197fa6a	3240
mbed_official	330:c80ac197fa6a	3241	/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
mbed_official	330:c80ac197fa6a	3242	* @{
mbed_official	330:c80ac197fa6a	3243	*/
mbed_official	330:c80ac197fa6a	3244	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	330:c80ac197fa6a	3245	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	330:c80ac197fa6a	3246	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3247	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
mbed_official	330:c80ac197fa6a	3248	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
mbed_official	330:c80ac197fa6a	3249	*/
mbed_official	330:c80ac197fa6a	3250	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	330:c80ac197fa6a	3251	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
mbed_official	330:c80ac197fa6a	3252
mbed_official	330:c80ac197fa6a	3253	/** @brief Macro to get the USB clock source.
mbed_official	330:c80ac197fa6a	3254	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3255	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
mbed_official	330:c80ac197fa6a	3256	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
mbed_official	330:c80ac197fa6a	3257	*/
mbed_official	330:c80ac197fa6a	3258	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
mbed_official	330:c80ac197fa6a	3259	/**
mbed_official	330:c80ac197fa6a	3260	* @}
mbed_official	330:c80ac197fa6a	3261	*/
mbed_official	330:c80ac197fa6a	3262
mbed_official	330:c80ac197fa6a	3263	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
mbed_official	330:c80ac197fa6a	3264	/* STM32F302xC \|\| STM32F303xC \|\| */
mbed_official	330:c80ac197fa6a	3265	/* STM32F302x8 \|\| */
mbed_official	330:c80ac197fa6a	3266	/* STM32F373xC */
mbed_official	330:c80ac197fa6a	3267
mbed_official	330:c80ac197fa6a	3268	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
mbed_official	330:c80ac197fa6a	3269	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	330:c80ac197fa6a	3270	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	330:c80ac197fa6a	3271
mbed_official	330:c80ac197fa6a	3272	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
mbed_official	330:c80ac197fa6a	3273	* @{
mbed_official	330:c80ac197fa6a	3274	*/
mbed_official	330:c80ac197fa6a	3275	/** @brief macro to configure the MCO clock.
mbed_official	330:c80ac197fa6a	3276	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	330:c80ac197fa6a	3277	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3278	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	330:c80ac197fa6a	3279	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	330:c80ac197fa6a	3280	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	330:c80ac197fa6a	3281	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	330:c80ac197fa6a	3282	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	330:c80ac197fa6a	3283	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	330:c80ac197fa6a	3284	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	330:c80ac197fa6a	3285	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3286	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
mbed_official	330:c80ac197fa6a	3287	*/
mbed_official	330:c80ac197fa6a	3288	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	330:c80ac197fa6a	3289	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
mbed_official	330:c80ac197fa6a	3290	/**
mbed_official	330:c80ac197fa6a	3291	* @}
mbed_official	330:c80ac197fa6a	3292	*/
mbed_official	330:c80ac197fa6a	3293	#else
mbed_official	330:c80ac197fa6a	3294	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
mbed_official	330:c80ac197fa6a	3295	* @{
mbed_official	330:c80ac197fa6a	3296	*/
mbed_official	330:c80ac197fa6a	3297
mbed_official	330:c80ac197fa6a	3298	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	330:c80ac197fa6a	3299	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
mbed_official	330:c80ac197fa6a	3300	/**
mbed_official	330:c80ac197fa6a	3301	* @}
mbed_official	330:c80ac197fa6a	3302	*/
mbed_official	330:c80ac197fa6a	3303
mbed_official	330:c80ac197fa6a	3304	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
mbed_official	330:c80ac197fa6a	3305	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
mbed_official	330:c80ac197fa6a	3306	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	330:c80ac197fa6a	3307
mbed_official	330:c80ac197fa6a	3308	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	3309
mbed_official	330:c80ac197fa6a	3310	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
mbed_official	330:c80ac197fa6a	3311	* @{
mbed_official	330:c80ac197fa6a	3312	*/
mbed_official	330:c80ac197fa6a	3313	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
mbed_official	330:c80ac197fa6a	3314	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
mbed_official	330:c80ac197fa6a	3315	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3316	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	330:c80ac197fa6a	3317	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	330:c80ac197fa6a	3318	*/
mbed_official	330:c80ac197fa6a	3319	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
mbed_official	330:c80ac197fa6a	3320	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
mbed_official	330:c80ac197fa6a	3321
mbed_official	330:c80ac197fa6a	3322	/** @brief Macro to get the I2C3 clock source.
mbed_official	330:c80ac197fa6a	3323	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3324	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	330:c80ac197fa6a	3325	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	330:c80ac197fa6a	3326	*/
mbed_official	330:c80ac197fa6a	3327	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
mbed_official	330:c80ac197fa6a	3328	/**
mbed_official	330:c80ac197fa6a	3329	* @}
mbed_official	330:c80ac197fa6a	3330	*/
mbed_official	330:c80ac197fa6a	3331
mbed_official	330:c80ac197fa6a	3332	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	3333	* @{
mbed_official	330:c80ac197fa6a	3334	*/
mbed_official	330:c80ac197fa6a	3335	/** @brief Macro to configure the TIM2 clock (TIM2CLK).
mbed_official	330:c80ac197fa6a	3336	* @param __TIM2CLKSource__: specifies the TIM2 clock source.
mbed_official	330:c80ac197fa6a	3337	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3338	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
mbed_official	330:c80ac197fa6a	3339	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
mbed_official	330:c80ac197fa6a	3340	*/
mbed_official	330:c80ac197fa6a	3341	#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
mbed_official	330:c80ac197fa6a	3342	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
mbed_official	330:c80ac197fa6a	3343
mbed_official	330:c80ac197fa6a	3344	/** @brief Macro to get the TIM2 clock (TIM2CLK).
mbed_official	330:c80ac197fa6a	3345	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3346	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3347	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
mbed_official	330:c80ac197fa6a	3348	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
mbed_official	330:c80ac197fa6a	3349	*/
mbed_official	330:c80ac197fa6a	3350	#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
mbed_official	330:c80ac197fa6a	3351
mbed_official	330:c80ac197fa6a	3352	/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
mbed_official	330:c80ac197fa6a	3353	* @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
mbed_official	330:c80ac197fa6a	3354	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3355	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
mbed_official	330:c80ac197fa6a	3356	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
mbed_official	330:c80ac197fa6a	3357	*/
mbed_official	330:c80ac197fa6a	3358	#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
mbed_official	330:c80ac197fa6a	3359	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
mbed_official	330:c80ac197fa6a	3360
mbed_official	330:c80ac197fa6a	3361	/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
mbed_official	330:c80ac197fa6a	3362	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3363	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3364	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
mbed_official	330:c80ac197fa6a	3365	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
mbed_official	330:c80ac197fa6a	3366	*/
mbed_official	330:c80ac197fa6a	3367	#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
mbed_official	330:c80ac197fa6a	3368
mbed_official	330:c80ac197fa6a	3369	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
mbed_official	330:c80ac197fa6a	3370	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
mbed_official	330:c80ac197fa6a	3371	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3372	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
mbed_official	330:c80ac197fa6a	3373	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
mbed_official	330:c80ac197fa6a	3374	*/
mbed_official	330:c80ac197fa6a	3375	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
mbed_official	330:c80ac197fa6a	3376	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
mbed_official	330:c80ac197fa6a	3377
mbed_official	330:c80ac197fa6a	3378	/** @brief Macro to get the TIM15 clock (TIM15CLK).
mbed_official	330:c80ac197fa6a	3379	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3380	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3381	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
mbed_official	330:c80ac197fa6a	3382	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
mbed_official	330:c80ac197fa6a	3383	*/
mbed_official	330:c80ac197fa6a	3384	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
mbed_official	330:c80ac197fa6a	3385
mbed_official	330:c80ac197fa6a	3386	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
mbed_official	330:c80ac197fa6a	3387	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
mbed_official	330:c80ac197fa6a	3388	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3389	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
mbed_official	330:c80ac197fa6a	3390	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
mbed_official	330:c80ac197fa6a	3391	*/
mbed_official	330:c80ac197fa6a	3392	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
mbed_official	330:c80ac197fa6a	3393	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
mbed_official	330:c80ac197fa6a	3394
mbed_official	330:c80ac197fa6a	3395	/** @brief Macro to get the TIM16 clock (TIM16CLK).
mbed_official	330:c80ac197fa6a	3396	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3397	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3398	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
mbed_official	330:c80ac197fa6a	3399	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
mbed_official	330:c80ac197fa6a	3400	*/
mbed_official	330:c80ac197fa6a	3401	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
mbed_official	330:c80ac197fa6a	3402
mbed_official	330:c80ac197fa6a	3403	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
mbed_official	330:c80ac197fa6a	3404	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
mbed_official	330:c80ac197fa6a	3405	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3406	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
mbed_official	330:c80ac197fa6a	3407	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
mbed_official	330:c80ac197fa6a	3408	*/
mbed_official	330:c80ac197fa6a	3409	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
mbed_official	330:c80ac197fa6a	3410	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
mbed_official	330:c80ac197fa6a	3411
mbed_official	330:c80ac197fa6a	3412	/** @brief Macro to get the TIM17 clock (TIM17CLK).
mbed_official	330:c80ac197fa6a	3413	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3414	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3415	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
mbed_official	330:c80ac197fa6a	3416	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
mbed_official	330:c80ac197fa6a	3417	*/
mbed_official	330:c80ac197fa6a	3418	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
mbed_official	330:c80ac197fa6a	3419
mbed_official	330:c80ac197fa6a	3420	/**
mbed_official	330:c80ac197fa6a	3421	* @}
mbed_official	330:c80ac197fa6a	3422	*/
mbed_official	330:c80ac197fa6a	3423
mbed_official	330:c80ac197fa6a	3424	#endif /* STM32f302xE \|\| STM32f303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	3425
mbed_official	330:c80ac197fa6a	3426	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
mbed_official	330:c80ac197fa6a	3427	/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
mbed_official	330:c80ac197fa6a	3428	* @{
mbed_official	330:c80ac197fa6a	3429	*/
mbed_official	330:c80ac197fa6a	3430	/** @brief Macro to configure the TIM20 clock (TIM20CLK).
mbed_official	330:c80ac197fa6a	3431	* @param __TIM20CLKSource__: specifies the TIM20 clock source.
mbed_official	330:c80ac197fa6a	3432	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3433	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
mbed_official	330:c80ac197fa6a	3434	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
mbed_official	330:c80ac197fa6a	3435	*/
mbed_official	330:c80ac197fa6a	3436	#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
mbed_official	330:c80ac197fa6a	3437	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
mbed_official	330:c80ac197fa6a	3438
mbed_official	330:c80ac197fa6a	3439	/** @brief Macro to get the TIM20 clock (TIM20CLK).
mbed_official	330:c80ac197fa6a	3440	* @retval The clock source can be one of the following values:
mbed_official	330:c80ac197fa6a	3441	* This parameter can be one of the following values:
mbed_official	330:c80ac197fa6a	3442	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
mbed_official	330:c80ac197fa6a	3443	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
mbed_official	330:c80ac197fa6a	3444	*/
mbed_official	330:c80ac197fa6a	3445	#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
mbed_official	330:c80ac197fa6a	3446
mbed_official	330:c80ac197fa6a	3447	/**
mbed_official	330:c80ac197fa6a	3448	* @}
mbed_official	330:c80ac197fa6a	3449	*/
mbed_official	330:c80ac197fa6a	3450	#endif /* STM32f303xE \|\| STM32F398xx */
mbed_official	330:c80ac197fa6a	3451
mbed_official	330:c80ac197fa6a	3452
mbed_official	330:c80ac197fa6a	3453	/**
mbed_official	330:c80ac197fa6a	3454	* @}
mbed_official	330:c80ac197fa6a	3455	*/
mbed_official	330:c80ac197fa6a	3456
mbed_official	330:c80ac197fa6a	3457	/* Exported functions --------------------------------------------------------*/
mbed_official	330:c80ac197fa6a	3458	/** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
mbed_official	330:c80ac197fa6a	3459	* @{
mbed_official	330:c80ac197fa6a	3460	*/
mbed_official	330:c80ac197fa6a	3461
mbed_official	330:c80ac197fa6a	3462	/** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
mbed_official	330:c80ac197fa6a	3463	* @{
mbed_official	330:c80ac197fa6a	3464	*/
mbed_official	330:c80ac197fa6a	3465	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	330:c80ac197fa6a	3466	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	330:c80ac197fa6a	3467	/**
mbed_official	330:c80ac197fa6a	3468	* @}
mbed_official	330:c80ac197fa6a	3469	*/
mbed_official	330:c80ac197fa6a	3470
mbed_official	330:c80ac197fa6a	3471	/**
mbed_official	330:c80ac197fa6a	3472	* @}
mbed_official	330:c80ac197fa6a	3473	*/
mbed_official	330:c80ac197fa6a	3474
mbed_official	330:c80ac197fa6a	3475	/**
mbed_official	330:c80ac197fa6a	3476	* @}
mbed_official	330:c80ac197fa6a	3477	*/
mbed_official	330:c80ac197fa6a	3478
mbed_official	330:c80ac197fa6a	3479	/**
mbed_official	330:c80ac197fa6a	3480	* @}
mbed_official	330:c80ac197fa6a	3481	*/
mbed_official	330:c80ac197fa6a	3482	#ifdef __cplusplus
mbed_official	330:c80ac197fa6a	3483	}
mbed_official	330:c80ac197fa6a	3484	#endif
mbed_official	330:c80ac197fa6a	3485
mbed_official	330:c80ac197fa6a	3486	#endif /* __STM32F3xx_HAL_RCC_EX_H */
mbed_official	330:c80ac197fa6a	3487
mbed_official	330:c80ac197fa6a	3488	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	26 Nov 2015
Imports:	17
Forks:	0
Commits:	638
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h@632:7687fb9c4f91, 2015-09-28 (annotated)

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