Joris Aerts / mbed-src

mbed library sources

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targets/hal/TARGET_NXP/TARGET_LPC15XX/can_api.c@530:2939f5396008, 2015-04-30 (annotated)

Committer:
mbed_official
Date:
Thu Apr 30 09:15:06 2015 +0100
Revision:
530:2939f5396008
Parent:
285:31249416b6f9 
Synchronized with git revision 334b3418dfe6e5d09d62fee80232883fcd1cbb1e



Full URL: https://github.com/mbedmicro/mbed/commit/334b3418dfe6e5d09d62fee80232883fcd1cbb1e/



Implement some CAN modes for the LPC1549/LPC11Cxx/LPC1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 245:b4dea936db71 1 /* mbed Microcontroller Library
mbed_official 245:b4dea936db71 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 245:b4dea936db71 3 *
mbed_official 245:b4dea936db71 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 245:b4dea936db71 5 * you may not use this file except in compliance with the License.
mbed_official 245:b4dea936db71 6 * You may obtain a copy of the License at
mbed_official 245:b4dea936db71 7 *
mbed_official 245:b4dea936db71 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 245:b4dea936db71 9 *
mbed_official 245:b4dea936db71 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 245:b4dea936db71 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 245:b4dea936db71 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 245:b4dea936db71 13 * See the License for the specific language governing permissions and
mbed_official 245:b4dea936db71 14 * limitations under the License.
mbed_official 245:b4dea936db71 15 */
mbed_official 245:b4dea936db71 16
mbed_official 245:b4dea936db71 17 #include "can_api.h"
mbed_official 245:b4dea936db71 18
mbed_official 245:b4dea936db71 19 #include "cmsis.h"
mbed_official 285:31249416b6f9 20 #include "mbed_error.h"
mbed_official 245:b4dea936db71 21
mbed_official 245:b4dea936db71 22 #include <math.h>
mbed_official 245:b4dea936db71 23 #include <string.h>
mbed_official 245:b4dea936db71 24
mbed_official 245:b4dea936db71 25 /* Handy defines */
mbed_official 245:b4dea936db71 26 #define MSG_OBJ_MAX 32
mbed_official 245:b4dea936db71 27 #define DLC_MAX 8
mbed_official 245:b4dea936db71 28
mbed_official 245:b4dea936db71 29 #define ID_STD_MASK 0x07FF
mbed_official 245:b4dea936db71 30 #define ID_EXT_MASK 0x1FFFFFFF
mbed_official 245:b4dea936db71 31 #define DLC_MASK 0x0F
mbed_official 245:b4dea936db71 32
mbed_official 245:b4dea936db71 33 #define CANIFn_ARB2_DIR (1UL << 13)
mbed_official 245:b4dea936db71 34 #define CANIFn_ARB2_XTD (1UL << 14)
mbed_official 245:b4dea936db71 35 #define CANIFn_ARB2_MSGVAL (1UL << 15)
mbed_official 245:b4dea936db71 36 #define CANIFn_MSK2_MXTD (1UL << 15)
mbed_official 245:b4dea936db71 37 #define CANIFn_MSK2_MDIR (1UL << 14)
mbed_official 245:b4dea936db71 38 #define CANIFn_MCTRL_EOB (1UL << 7)
mbed_official 245:b4dea936db71 39 #define CANIFn_MCTRL_TXRQST (1UL << 8)
mbed_official 245:b4dea936db71 40 #define CANIFn_MCTRL_RMTEN (1UL << 9)
mbed_official 245:b4dea936db71 41 #define CANIFn_MCTRL_RXIE (1UL << 10)
mbed_official 245:b4dea936db71 42 #define CANIFn_MCTRL_TXIE (1UL << 11)
mbed_official 245:b4dea936db71 43 #define CANIFn_MCTRL_UMASK (1UL << 12)
mbed_official 245:b4dea936db71 44 #define CANIFn_MCTRL_INTPND (1UL << 13)
mbed_official 245:b4dea936db71 45 #define CANIFn_MCTRL_MSGLST (1UL << 14)
mbed_official 245:b4dea936db71 46 #define CANIFn_MCTRL_NEWDAT (1UL << 15)
mbed_official 245:b4dea936db71 47 #define CANIFn_CMDMSK_DATA_B (1UL << 0)
mbed_official 245:b4dea936db71 48 #define CANIFn_CMDMSK_DATA_A (1UL << 1)
mbed_official 245:b4dea936db71 49 #define CANIFn_CMDMSK_TXRQST (1UL << 2)
mbed_official 245:b4dea936db71 50 #define CANIFn_CMDMSK_NEWDAT (1UL << 2)
mbed_official 245:b4dea936db71 51 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
mbed_official 245:b4dea936db71 52 #define CANIFn_CMDMSK_CTRL (1UL << 4)
mbed_official 245:b4dea936db71 53 #define CANIFn_CMDMSK_ARB (1UL << 5)
mbed_official 245:b4dea936db71 54 #define CANIFn_CMDMSK_MASK (1UL << 6)
mbed_official 245:b4dea936db71 55 #define CANIFn_CMDMSK_WR (1UL << 7)
mbed_official 245:b4dea936db71 56 #define CANIFn_CMDMSK_RD (0UL << 7)
mbed_official 245:b4dea936db71 57 #define CANIFn_CMDREQ_BUSY (1UL << 15)
mbed_official 245:b4dea936db71 58
mbed_official 530:2939f5396008 59 #define CANCNTL_INIT (1 << 0) // Initialization
mbed_official 530:2939f5396008 60 #define CANCNTL_IE (1 << 1) // Module interrupt enable
mbed_official 530:2939f5396008 61 #define CANCNTL_SIE (1 << 2) // Status change interrupt enable
mbed_official 530:2939f5396008 62 #define CANCNTL_EIE (1 << 3) // Error interrupt enable
mbed_official 530:2939f5396008 63 #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
mbed_official 530:2939f5396008 64 #define CANCNTL_CCE (1 << 6) // Configuration change enable
mbed_official 530:2939f5396008 65 #define CANCNTL_TEST (1 << 7) // Test mode enable
mbed_official 530:2939f5396008 66
mbed_official 530:2939f5396008 67 #define CANTEST_BASIC (1 << 2) // Basic mode
mbed_official 530:2939f5396008 68 #define CANTEST_SILENT (1 << 3) // Silent mode
mbed_official 530:2939f5396008 69 #define CANTEST_LBACK (1 << 4) // Loop back mode
mbed_official 530:2939f5396008 70 #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
mbed_official 530:2939f5396008 71 #define CANTEST_TX_SHIFT 5
mbed_official 530:2939f5396008 72 #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
mbed_official 530:2939f5396008 73
mbed_official 245:b4dea936db71 74 static uint32_t can_irq_id = 0;
mbed_official 245:b4dea936db71 75 static can_irq_handler irq_handler;
mbed_official 245:b4dea936db71 76
mbed_official 245:b4dea936db71 77 static inline void can_disable(can_t *obj) {
mbed_official 245:b4dea936db71 78 LPC_C_CAN0->CANCNTL |= 0x1;
mbed_official 245:b4dea936db71 79 }
mbed_official 245:b4dea936db71 80
mbed_official 245:b4dea936db71 81 static inline void can_enable(can_t *obj) {
mbed_official 245:b4dea936db71 82 if (LPC_C_CAN0->CANCNTL & 0x1) {
mbed_official 245:b4dea936db71 83 LPC_C_CAN0->CANCNTL &= ~(0x1);
mbed_official 245:b4dea936db71 84 }
mbed_official 245:b4dea936db71 85 }
mbed_official 245:b4dea936db71 86
mbed_official 245:b4dea936db71 87 int can_mode(can_t *obj, CanMode mode) {
mbed_official 530:2939f5396008 88 int success = 0;
mbed_official 530:2939f5396008 89 switch (mode) {
mbed_official 530:2939f5396008 90 case MODE_RESET:
mbed_official 530:2939f5396008 91 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
mbed_official 530:2939f5396008 92 can_disable(obj);
mbed_official 530:2939f5396008 93 success = 1;
mbed_official 530:2939f5396008 94 break;
mbed_official 530:2939f5396008 95 case MODE_NORMAL:
mbed_official 530:2939f5396008 96 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
mbed_official 530:2939f5396008 97 can_enable(obj);
mbed_official 530:2939f5396008 98 success = 1;
mbed_official 530:2939f5396008 99 break;
mbed_official 530:2939f5396008 100 case MODE_SILENT:
mbed_official 530:2939f5396008 101 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
mbed_official 530:2939f5396008 102 LPC_C_CAN0->CANTEST |= CANTEST_SILENT;
mbed_official 530:2939f5396008 103 LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK;
mbed_official 530:2939f5396008 104 success = 1;
mbed_official 530:2939f5396008 105 break;
mbed_official 530:2939f5396008 106 case MODE_TEST_LOCAL:
mbed_official 530:2939f5396008 107 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
mbed_official 530:2939f5396008 108 LPC_C_CAN0->CANTEST &=~CANTEST_SILENT;
mbed_official 530:2939f5396008 109 LPC_C_CAN0->CANTEST |= CANTEST_LBACK;
mbed_official 530:2939f5396008 110 success = 1;
mbed_official 530:2939f5396008 111 break;
mbed_official 530:2939f5396008 112 case MODE_TEST_SILENT:
mbed_official 530:2939f5396008 113 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
mbed_official 530:2939f5396008 114 LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT);
mbed_official 530:2939f5396008 115 success = 1;
mbed_official 530:2939f5396008 116 break;
mbed_official 530:2939f5396008 117 case MODE_TEST_GLOBAL:
mbed_official 530:2939f5396008 118 default:
mbed_official 530:2939f5396008 119 success = 0;
mbed_official 530:2939f5396008 120 break;
mbed_official 530:2939f5396008 121 }
mbed_official 530:2939f5396008 122
mbed_official 530:2939f5396008 123 return success;
mbed_official 245:b4dea936db71 124 }
mbed_official 245:b4dea936db71 125
mbed_official 245:b4dea936db71 126 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
mbed_official 245:b4dea936db71 127 uint16_t i;
mbed_official 245:b4dea936db71 128
mbed_official 245:b4dea936db71 129 // Find first free message object
mbed_official 245:b4dea936db71 130 if (handle == 0) {
mbed_official 245:b4dea936db71 131 uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
mbed_official 245:b4dea936db71 132
mbed_official 245:b4dea936db71 133 // Find first free messagebox
mbed_official 245:b4dea936db71 134 for (i = 0; i < 32; i++) {
mbed_official 245:b4dea936db71 135 if ((msgval & (1 << i)) == 0) {
mbed_official 245:b4dea936db71 136 handle = i+1;
mbed_official 245:b4dea936db71 137 break;
mbed_official 245:b4dea936db71 138 }
mbed_official 245:b4dea936db71 139 }
mbed_official 245:b4dea936db71 140 }
mbed_official 245:b4dea936db71 141
mbed_official 245:b4dea936db71 142 if (handle > 0 && handle < 32) {
mbed_official 245:b4dea936db71 143 if (format == CANExtended) {
mbed_official 245:b4dea936db71 144 // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
mbed_official 245:b4dea936db71 145 LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
mbed_official 245:b4dea936db71 146 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 147 LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
mbed_official 245:b4dea936db71 148 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 149 } else {
mbed_official 245:b4dea936db71 150 // Mark message valid, Direction = TX, Set Identifier and mask everything
mbed_official 245:b4dea936db71 151 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 152 LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 153 }
mbed_official 245:b4dea936db71 154
mbed_official 245:b4dea936db71 155 // Use mask, single message object and set DLC
mbed_official 245:b4dea936db71 156 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | CANIFn_MCTRL_RXIE | (DLC_MAX & 0xF);
mbed_official 245:b4dea936db71 157
mbed_official 245:b4dea936db71 158 // Transfer all fields to message object
mbed_official 245:b4dea936db71 159 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
mbed_official 245:b4dea936db71 160
mbed_official 245:b4dea936db71 161 // Start Transfer to given message number
mbed_official 245:b4dea936db71 162 LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
mbed_official 245:b4dea936db71 163
mbed_official 245:b4dea936db71 164 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 165 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 166 }
mbed_official 245:b4dea936db71 167
mbed_official 245:b4dea936db71 168 return handle;
mbed_official 245:b4dea936db71 169 }
mbed_official 245:b4dea936db71 170
mbed_official 245:b4dea936db71 171 static inline void can_irq() {
mbed_official 245:b4dea936db71 172 irq_handler(can_irq_id, IRQ_RX);
mbed_official 245:b4dea936db71 173 }
mbed_official 245:b4dea936db71 174
mbed_official 245:b4dea936db71 175 // Register CAN object's irq handler
mbed_official 245:b4dea936db71 176 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
mbed_official 245:b4dea936db71 177 irq_handler = handler;
mbed_official 245:b4dea936db71 178 can_irq_id = id;
mbed_official 245:b4dea936db71 179 }
mbed_official 245:b4dea936db71 180
mbed_official 245:b4dea936db71 181 // Unregister CAN object's irq handler
mbed_official 245:b4dea936db71 182 void can_irq_free(can_t *obj) {
mbed_official 245:b4dea936db71 183 LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
mbed_official 245:b4dea936db71 184 can_irq_id = 0;
mbed_official 245:b4dea936db71 185 NVIC_DisableIRQ(C_CAN0_IRQn);
mbed_official 245:b4dea936db71 186 }
mbed_official 245:b4dea936db71 187
mbed_official 245:b4dea936db71 188 // Clear or set a irq
mbed_official 245:b4dea936db71 189 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
mbed_official 245:b4dea936db71 190 // Put CAN in Reset Mode and enable interrupt
mbed_official 245:b4dea936db71 191 can_disable(obj);
mbed_official 245:b4dea936db71 192 if (enable == 0) {
mbed_official 245:b4dea936db71 193 LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2);
mbed_official 245:b4dea936db71 194 } else {
mbed_official 245:b4dea936db71 195 LPC_C_CAN0->CANCNTL |= 1UL << 1 | 1UL << 2;
mbed_official 245:b4dea936db71 196 }
mbed_official 245:b4dea936db71 197 // Take it out of reset...
mbed_official 245:b4dea936db71 198 can_enable(obj);
mbed_official 245:b4dea936db71 199
mbed_official 245:b4dea936db71 200 // Enable NVIC if at least 1 interrupt is active
mbed_official 245:b4dea936db71 201 NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
mbed_official 245:b4dea936db71 202 NVIC_EnableIRQ(C_CAN0_IRQn);
mbed_official 245:b4dea936db71 203 }
mbed_official 245:b4dea936db71 204
mbed_official 245:b4dea936db71 205 // This table has the sampling points as close to 75% as possible. The first
mbed_official 245:b4dea936db71 206 // value is TSEG1, the second TSEG2.
mbed_official 245:b4dea936db71 207 static const int timing_pts[23][2] = {
mbed_official 245:b4dea936db71 208 {0x0, 0x0}, // 2, 50%
mbed_official 245:b4dea936db71 209 {0x1, 0x0}, // 3, 67%
mbed_official 245:b4dea936db71 210 {0x2, 0x0}, // 4, 75%
mbed_official 245:b4dea936db71 211 {0x3, 0x0}, // 5, 80%
mbed_official 245:b4dea936db71 212 {0x3, 0x1}, // 6, 67%
mbed_official 245:b4dea936db71 213 {0x4, 0x1}, // 7, 71%
mbed_official 245:b4dea936db71 214 {0x5, 0x1}, // 8, 75%
mbed_official 245:b4dea936db71 215 {0x6, 0x1}, // 9, 78%
mbed_official 245:b4dea936db71 216 {0x6, 0x2}, // 10, 70%
mbed_official 245:b4dea936db71 217 {0x7, 0x2}, // 11, 73%
mbed_official 245:b4dea936db71 218 {0x8, 0x2}, // 12, 75%
mbed_official 245:b4dea936db71 219 {0x9, 0x2}, // 13, 77%
mbed_official 245:b4dea936db71 220 {0x9, 0x3}, // 14, 71%
mbed_official 245:b4dea936db71 221 {0xA, 0x3}, // 15, 73%
mbed_official 245:b4dea936db71 222 {0xB, 0x3}, // 16, 75%
mbed_official 245:b4dea936db71 223 {0xC, 0x3}, // 17, 76%
mbed_official 245:b4dea936db71 224 {0xD, 0x3}, // 18, 78%
mbed_official 245:b4dea936db71 225 {0xD, 0x4}, // 19, 74%
mbed_official 245:b4dea936db71 226 {0xE, 0x4}, // 20, 75%
mbed_official 245:b4dea936db71 227 {0xF, 0x4}, // 21, 76%
mbed_official 245:b4dea936db71 228 {0xF, 0x5}, // 22, 73%
mbed_official 245:b4dea936db71 229 {0xF, 0x6}, // 23, 70%
mbed_official 245:b4dea936db71 230 {0xF, 0x7}, // 24, 67%
mbed_official 245:b4dea936db71 231 };
mbed_official 245:b4dea936db71 232
mbed_official 245:b4dea936db71 233 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
mbed_official 245:b4dea936db71 234 uint32_t btr;
mbed_official 245:b4dea936db71 235 uint32_t clkdiv = 1;
mbed_official 245:b4dea936db71 236 uint16_t brp = 0;
mbed_official 245:b4dea936db71 237 uint32_t calcbit;
mbed_official 245:b4dea936db71 238 uint32_t bitwidth;
mbed_official 245:b4dea936db71 239 int hit = 0;
mbed_official 245:b4dea936db71 240 int bits = 0;
mbed_official 245:b4dea936db71 241
mbed_official 245:b4dea936db71 242 bitwidth = sclk / cclk;
mbed_official 245:b4dea936db71 243
mbed_official 245:b4dea936db71 244 brp = bitwidth / 0x18;
mbed_official 245:b4dea936db71 245 while ((!hit) && (brp < bitwidth / 4)) {
mbed_official 245:b4dea936db71 246 brp++;
mbed_official 245:b4dea936db71 247 for (bits = 22; bits > 0; bits--) {
mbed_official 245:b4dea936db71 248 calcbit = (bits + 3) * (brp + 1);
mbed_official 245:b4dea936db71 249 if (calcbit == bitwidth) {
mbed_official 245:b4dea936db71 250 hit = 1;
mbed_official 245:b4dea936db71 251 break;
mbed_official 245:b4dea936db71 252 }
mbed_official 245:b4dea936db71 253 }
mbed_official 245:b4dea936db71 254 }
mbed_official 245:b4dea936db71 255
mbed_official 245:b4dea936db71 256 clkdiv = clkdiv - 1;
mbed_official 245:b4dea936db71 257
mbed_official 245:b4dea936db71 258 if (hit) {
mbed_official 245:b4dea936db71 259 btr = (timing_pts[bits][1] & 0x7) << 12
mbed_official 245:b4dea936db71 260 | (timing_pts[bits][0] & 0xf) << 8
mbed_official 245:b4dea936db71 261 | (psjw & 0x3) << 6
mbed_official 245:b4dea936db71 262 | (brp & 0x3F);
mbed_official 245:b4dea936db71 263 btr = btr | (clkdiv << 16);
mbed_official 245:b4dea936db71 264 } else {
mbed_official 245:b4dea936db71 265 btr = 0;
mbed_official 245:b4dea936db71 266 }
mbed_official 245:b4dea936db71 267
mbed_official 245:b4dea936db71 268 return btr;
mbed_official 245:b4dea936db71 269 }
mbed_official 245:b4dea936db71 270
mbed_official 245:b4dea936db71 271
mbed_official 245:b4dea936db71 272 int can_config_rxmsgobj(can_t *obj) {
mbed_official 245:b4dea936db71 273 uint16_t i = 0;
mbed_official 245:b4dea936db71 274
mbed_official 245:b4dea936db71 275 // Make sure the interface is available
mbed_official 245:b4dea936db71 276 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 277
mbed_official 245:b4dea936db71 278 // Mark message valid, Direction = RX, Don't care about anything else
mbed_official 245:b4dea936db71 279 LPC_C_CAN0->CANIF1_ARB1 = 0;
mbed_official 245:b4dea936db71 280 LPC_C_CAN0->CANIF1_ARB2 = 0;
mbed_official 245:b4dea936db71 281 LPC_C_CAN0->CANIF1_MCTRL = 0;
mbed_official 245:b4dea936db71 282
mbed_official 245:b4dea936db71 283 for ( i = 0; i < MSG_OBJ_MAX; i++ ) {
mbed_official 245:b4dea936db71 284 // Transfer arb and control fields to message object
mbed_official 245:b4dea936db71 285 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST;
mbed_official 245:b4dea936db71 286
mbed_official 245:b4dea936db71 287 // Start Transfer to given message number
mbed_official 245:b4dea936db71 288 LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
mbed_official 245:b4dea936db71 289
mbed_official 245:b4dea936db71 290 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 291 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 292 }
mbed_official 245:b4dea936db71 293
mbed_official 245:b4dea936db71 294 // Accept all messages
mbed_official 245:b4dea936db71 295 can_filter(obj, 0, 0, CANStandard, 1);
mbed_official 245:b4dea936db71 296
mbed_official 245:b4dea936db71 297 return 1;
mbed_official 245:b4dea936db71 298 }
mbed_official 245:b4dea936db71 299
mbed_official 245:b4dea936db71 300
mbed_official 245:b4dea936db71 301 void can_init(can_t *obj, PinName rd, PinName td) {
mbed_official 245:b4dea936db71 302 // Enable power and clock
mbed_official 245:b4dea936db71 303 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
mbed_official 245:b4dea936db71 304 LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
mbed_official 245:b4dea936db71 305 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 306
mbed_official 245:b4dea936db71 307 // Enable Initialization mode
mbed_official 245:b4dea936db71 308 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
mbed_official 245:b4dea936db71 309 LPC_C_CAN0->CANCNTL |= (1UL << 0);
mbed_official 245:b4dea936db71 310 }
mbed_official 245:b4dea936db71 311
mbed_official 245:b4dea936db71 312 LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
mbed_official 245:b4dea936db71 313 LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
mbed_official 245:b4dea936db71 314
mbed_official 245:b4dea936db71 315 can_frequency(obj, 100000);
mbed_official 245:b4dea936db71 316
mbed_official 245:b4dea936db71 317 // Resume operation
mbed_official 245:b4dea936db71 318 LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
mbed_official 245:b4dea936db71 319 while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
mbed_official 245:b4dea936db71 320
mbed_official 245:b4dea936db71 321 // Initialize RX message object
mbed_official 245:b4dea936db71 322 can_config_rxmsgobj(obj);
mbed_official 245:b4dea936db71 323 }
mbed_official 245:b4dea936db71 324
mbed_official 245:b4dea936db71 325 void can_free(can_t *obj) {
mbed_official 245:b4dea936db71 326 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 327 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 328 }
mbed_official 245:b4dea936db71 329
mbed_official 245:b4dea936db71 330 int can_frequency(can_t *obj, int f) {
mbed_official 245:b4dea936db71 331 int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
mbed_official 245:b4dea936db71 332 int clkdiv = (btr >> 16) & 0x0F;
mbed_official 245:b4dea936db71 333 btr = btr & 0xFFFF;
mbed_official 245:b4dea936db71 334
mbed_official 245:b4dea936db71 335 if (btr > 0) {
mbed_official 245:b4dea936db71 336 // Set the bit clock
mbed_official 245:b4dea936db71 337 LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
mbed_official 245:b4dea936db71 338 LPC_C_CAN0->CANCLKDIV = clkdiv;
mbed_official 245:b4dea936db71 339 LPC_C_CAN0->CANBT = btr;
mbed_official 245:b4dea936db71 340 LPC_C_CAN0->CANBRPE = 0x0000;
mbed_official 245:b4dea936db71 341 LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
mbed_official 245:b4dea936db71 342 return 1;
mbed_official 245:b4dea936db71 343 }
mbed_official 245:b4dea936db71 344 return 0;
mbed_official 245:b4dea936db71 345 }
mbed_official 245:b4dea936db71 346
mbed_official 245:b4dea936db71 347 int can_write(can_t *obj, CAN_Message msg, int cc) {
mbed_official 245:b4dea936db71 348 uint16_t msgnum = 0;
mbed_official 245:b4dea936db71 349
mbed_official 245:b4dea936db71 350 // Make sure controller is enabled
mbed_official 245:b4dea936db71 351 can_enable(obj);
mbed_official 245:b4dea936db71 352
mbed_official 245:b4dea936db71 353 // Make sure the interface is available
mbed_official 245:b4dea936db71 354 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 355
mbed_official 245:b4dea936db71 356 // Set the direction bit based on the message type
mbed_official 245:b4dea936db71 357 uint32_t direction = 0;
mbed_official 245:b4dea936db71 358 if (msg.type == CANData) {
mbed_official 245:b4dea936db71 359 direction = CANIFn_ARB2_DIR;
mbed_official 245:b4dea936db71 360 }
mbed_official 245:b4dea936db71 361
mbed_official 245:b4dea936db71 362 if (msg.format == CANExtended) {
mbed_official 245:b4dea936db71 363 // Mark message valid, Extended Frame, Set Identifier and mask everything
mbed_official 245:b4dea936db71 364 LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
mbed_official 245:b4dea936db71 365 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
mbed_official 245:b4dea936db71 366 LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
mbed_official 245:b4dea936db71 367 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
mbed_official 245:b4dea936db71 368 } else {
mbed_official 245:b4dea936db71 369 // Mark message valid, Set Identifier and mask everything
mbed_official 245:b4dea936db71 370 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 371 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
mbed_official 245:b4dea936db71 372 }
mbed_official 245:b4dea936db71 373
mbed_official 245:b4dea936db71 374 // Use mask, request transmission, single message object and set DLC
mbed_official 245:b4dea936db71 375 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
mbed_official 245:b4dea936db71 376
mbed_official 245:b4dea936db71 377 LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
mbed_official 245:b4dea936db71 378 LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
mbed_official 245:b4dea936db71 379 LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
mbed_official 245:b4dea936db71 380 LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
mbed_official 245:b4dea936db71 381
mbed_official 245:b4dea936db71 382 // Transfer all fields to message object
mbed_official 245:b4dea936db71 383 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
mbed_official 245:b4dea936db71 384
mbed_official 245:b4dea936db71 385 // Start Transfer to given message number
mbed_official 245:b4dea936db71 386 LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
mbed_official 245:b4dea936db71 387
mbed_official 245:b4dea936db71 388 // Wait until transfer to message ram complete - TODO: maybe not block??
mbed_official 245:b4dea936db71 389 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
mbed_official 245:b4dea936db71 390
mbed_official 245:b4dea936db71 391 // Wait until TXOK is set, then clear it - TODO: maybe not block
mbed_official 245:b4dea936db71 392 //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
mbed_official 245:b4dea936db71 393 LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
mbed_official 245:b4dea936db71 394
mbed_official 245:b4dea936db71 395 return 1;
mbed_official 245:b4dea936db71 396 }
mbed_official 245:b4dea936db71 397
mbed_official 245:b4dea936db71 398 int can_read(can_t *obj, CAN_Message *msg, int handle) {
mbed_official 245:b4dea936db71 399 uint16_t i;
mbed_official 245:b4dea936db71 400
mbed_official 245:b4dea936db71 401 // Make sure controller is enabled
mbed_official 245:b4dea936db71 402 can_enable(obj);
mbed_official 245:b4dea936db71 403
mbed_official 245:b4dea936db71 404 // Find first message object with new data
mbed_official 245:b4dea936db71 405 if (handle == 0) {
mbed_official 245:b4dea936db71 406 uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
mbed_official 245:b4dea936db71 407 // Find first free messagebox
mbed_official 245:b4dea936db71 408 for (i = 0; i < 32; i++) {
mbed_official 245:b4dea936db71 409 if (newdata & (1 << i)) {
mbed_official 245:b4dea936db71 410 handle = i+1;
mbed_official 245:b4dea936db71 411 break;
mbed_official 245:b4dea936db71 412 }
mbed_official 245:b4dea936db71 413 }
mbed_official 245:b4dea936db71 414 }
mbed_official 245:b4dea936db71 415
mbed_official 245:b4dea936db71 416 if (handle > 0 && handle < 32) {
mbed_official 245:b4dea936db71 417 // Wait until message interface is free
mbed_official 245:b4dea936db71 418 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 419
mbed_official 245:b4dea936db71 420 // Transfer all fields to message object
mbed_official 245:b4dea936db71 421 LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
mbed_official 245:b4dea936db71 422
mbed_official 245:b4dea936db71 423 // Start Transfer from given message number
mbed_official 245:b4dea936db71 424 LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
mbed_official 245:b4dea936db71 425
mbed_official 245:b4dea936db71 426 // Wait until transfer to message ram complete
mbed_official 245:b4dea936db71 427 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
mbed_official 245:b4dea936db71 428
mbed_official 245:b4dea936db71 429 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
mbed_official 245:b4dea936db71 430 msg->format = CANExtended;
mbed_official 245:b4dea936db71 431 msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
mbed_official 245:b4dea936db71 432 msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
mbed_official 245:b4dea936db71 433 } else {
mbed_official 245:b4dea936db71 434 msg->format = CANStandard;
mbed_official 245:b4dea936db71 435 msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
mbed_official 245:b4dea936db71 436 }
mbed_official 245:b4dea936db71 437
mbed_official 245:b4dea936db71 438 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
mbed_official 245:b4dea936db71 439 msg->type = CANRemote;
mbed_official 245:b4dea936db71 440 }
mbed_official 245:b4dea936db71 441 else {
mbed_official 245:b4dea936db71 442 msg->type = CANData;
mbed_official 245:b4dea936db71 443 }
mbed_official 245:b4dea936db71 444
mbed_official 245:b4dea936db71 445 msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
mbed_official 245:b4dea936db71 446 msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 447 msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 448 msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 449 msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 450 msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 451 msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 452 msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
mbed_official 245:b4dea936db71 453 msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
mbed_official 245:b4dea936db71 454
mbed_official 245:b4dea936db71 455 LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
mbed_official 245:b4dea936db71 456 return 1;
mbed_official 245:b4dea936db71 457 }
mbed_official 245:b4dea936db71 458 return 0;
mbed_official 245:b4dea936db71 459 }
mbed_official 245:b4dea936db71 460
mbed_official 245:b4dea936db71 461 void can_reset(can_t *obj) {
mbed_official 245:b4dea936db71 462 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
mbed_official 245:b4dea936db71 463 LPC_C_CAN0->CANSTAT = 0;
mbed_official 245:b4dea936db71 464 can_config_rxmsgobj(obj);
mbed_official 245:b4dea936db71 465 }
mbed_official 245:b4dea936db71 466
mbed_official 245:b4dea936db71 467 unsigned char can_rderror(can_t *obj) {
mbed_official 245:b4dea936db71 468 return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
mbed_official 245:b4dea936db71 469 }
mbed_official 245:b4dea936db71 470
mbed_official 245:b4dea936db71 471 unsigned char can_tderror(can_t *obj) {
mbed_official 245:b4dea936db71 472 return (LPC_C_CAN0->CANEC & 0xFF);
mbed_official 245:b4dea936db71 473 }
mbed_official 245:b4dea936db71 474
mbed_official 245:b4dea936db71 475 void can_monitor(can_t *obj, int silent) {
mbed_official 245:b4dea936db71 476 if (silent) {
mbed_official 245:b4dea936db71 477 LPC_C_CAN0->CANCNTL |= (1UL << 7);
mbed_official 245:b4dea936db71 478 LPC_C_CAN0->CANTEST |= (1UL << 3);
mbed_official 245:b4dea936db71 479 } else {
mbed_official 245:b4dea936db71 480 LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
mbed_official 245:b4dea936db71 481 LPC_C_CAN0->CANTEST &= ~(1UL << 3);
mbed_official 245:b4dea936db71 482 }
mbed_official 245:b4dea936db71 483
mbed_official 245:b4dea936db71 484 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
mbed_official 245:b4dea936db71 485 LPC_C_CAN0->CANCNTL |= (1UL << 0);
mbed_official 245:b4dea936db71 486 }
mbed_official 245:b4dea936db71 487 }