Joris Aerts / mbed-src

mbed library sources

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targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC2368/hal/gpio_irq_api.c@10:3bc89ef62ce7
Child:
35:371630885ad6
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "gpio_irq_api.h"
emilmont 10:3bc89ef62ce7 17 #include "error.h"
emilmont 10:3bc89ef62ce7 18 #include <stddef.h>
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 #define CHANNEL_NUM 48
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
emilmont 10:3bc89ef62ce7 24 static gpio_irq_handler irq_handler;
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 static void handle_interrupt_in(void) {
emilmont 10:3bc89ef62ce7 27 // Read in all current interrupt registers. We do this once as the
emilmont 10:3bc89ef62ce7 28 // GPIO interrupt registers are on the APB bus, and this is slow.
emilmont 10:3bc89ef62ce7 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
emilmont 10:3bc89ef62ce7 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
emilmont 10:3bc89ef62ce7 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
emilmont 10:3bc89ef62ce7 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
emilmont 10:3bc89ef62ce7 33 uint32_t mask0 = 0;
emilmont 10:3bc89ef62ce7 34 uint32_t mask2 = 0;
emilmont 10:3bc89ef62ce7 35 int i;
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 // P0.0-0.31
emilmont 10:3bc89ef62ce7 38 for (i = 0; i < 32; i++) {
emilmont 10:3bc89ef62ce7 39 uint32_t pmask = (1 << i);
emilmont 10:3bc89ef62ce7 40 if (rise0 & pmask) {
emilmont 10:3bc89ef62ce7 41 mask0 |= pmask;
emilmont 10:3bc89ef62ce7 42 if (channel_ids[i] != 0)
emilmont 10:3bc89ef62ce7 43 irq_handler(channel_ids[i], IRQ_RISE);
emilmont 10:3bc89ef62ce7 44 }
emilmont 10:3bc89ef62ce7 45 if (fall0 & pmask) {
emilmont 10:3bc89ef62ce7 46 mask0 |= pmask;
emilmont 10:3bc89ef62ce7 47 if (channel_ids[i] != 0)
emilmont 10:3bc89ef62ce7 48 irq_handler(channel_ids[i], IRQ_FALL);
emilmont 10:3bc89ef62ce7 49 }
emilmont 10:3bc89ef62ce7 50 }
emilmont 10:3bc89ef62ce7 51
emilmont 10:3bc89ef62ce7 52 // P2.0-2.15
emilmont 10:3bc89ef62ce7 53 for (i = 0; i < 16; i++) {
emilmont 10:3bc89ef62ce7 54 uint32_t pmask = (1 << i);
emilmont 10:3bc89ef62ce7 55 int channel_index = i + 32;
emilmont 10:3bc89ef62ce7 56 if (rise2 & pmask) {
emilmont 10:3bc89ef62ce7 57 mask2 |= pmask;
emilmont 10:3bc89ef62ce7 58 if (channel_ids[channel_index] != 0)
emilmont 10:3bc89ef62ce7 59 irq_handler(channel_ids[channel_index], IRQ_RISE);
emilmont 10:3bc89ef62ce7 60 }
emilmont 10:3bc89ef62ce7 61 if (fall2 & pmask) {
emilmont 10:3bc89ef62ce7 62 mask2 |= pmask;
emilmont 10:3bc89ef62ce7 63 if (channel_ids[channel_index] != 0)
emilmont 10:3bc89ef62ce7 64 irq_handler(channel_ids[channel_index], IRQ_FALL);
emilmont 10:3bc89ef62ce7 65 }
emilmont 10:3bc89ef62ce7 66 }
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 // Clear the interrupts we just handled
emilmont 10:3bc89ef62ce7 69 LPC_GPIOINT->IO0IntClr = mask0;
emilmont 10:3bc89ef62ce7 70 LPC_GPIOINT->IO2IntClr = mask2;
emilmont 10:3bc89ef62ce7 71 }
emilmont 10:3bc89ef62ce7 72
emilmont 10:3bc89ef62ce7 73 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
emilmont 10:3bc89ef62ce7 74 if (pin == NC) return -1;
emilmont 10:3bc89ef62ce7 75
emilmont 10:3bc89ef62ce7 76 irq_handler = handler;
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 obj->port = (int)pin & ~0x1F;
emilmont 10:3bc89ef62ce7 79 obj->pin = (int)pin & 0x1F;
emilmont 10:3bc89ef62ce7 80
emilmont 10:3bc89ef62ce7 81 // Interrupts available only on GPIO0 and GPIO2
emilmont 10:3bc89ef62ce7 82 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
emilmont 10:3bc89ef62ce7 83 error("pins on this port cannot generate interrupts\n");
emilmont 10:3bc89ef62ce7 84 }
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 // put us in the interrupt table
emilmont 10:3bc89ef62ce7 87 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
emilmont 10:3bc89ef62ce7 88 channel_ids[index] = id;
emilmont 10:3bc89ef62ce7 89 obj->ch = index;
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
emilmont 10:3bc89ef62ce7 92 NVIC_EnableIRQ(EINT3_IRQn);
emilmont 10:3bc89ef62ce7 93
emilmont 10:3bc89ef62ce7 94 return 0;
emilmont 10:3bc89ef62ce7 95 }
emilmont 10:3bc89ef62ce7 96
emilmont 10:3bc89ef62ce7 97 void gpio_irq_free(gpio_irq_t *obj) {
emilmont 10:3bc89ef62ce7 98 channel_ids[obj->ch] = 0;
emilmont 10:3bc89ef62ce7 99 }
emilmont 10:3bc89ef62ce7 100
emilmont 10:3bc89ef62ce7 101 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
emilmont 10:3bc89ef62ce7 102 // ensure nothing is pending
emilmont 10:3bc89ef62ce7 103 switch (obj->port) {
emilmont 10:3bc89ef62ce7 104 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
emilmont 10:3bc89ef62ce7 105 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
emilmont 10:3bc89ef62ce7 106 }
emilmont 10:3bc89ef62ce7 107
emilmont 10:3bc89ef62ce7 108 // enable the pin interrupt
emilmont 10:3bc89ef62ce7 109 if (event == IRQ_RISE) {
emilmont 10:3bc89ef62ce7 110 switch (obj->port) {
emilmont 10:3bc89ef62ce7 111 case LPC_GPIO0_BASE:
emilmont 10:3bc89ef62ce7 112 if (enable) {
emilmont 10:3bc89ef62ce7 113 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
emilmont 10:3bc89ef62ce7 114 } else {
emilmont 10:3bc89ef62ce7 115 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
emilmont 10:3bc89ef62ce7 116 }
emilmont 10:3bc89ef62ce7 117 break;
emilmont 10:3bc89ef62ce7 118 case LPC_GPIO2_BASE:
emilmont 10:3bc89ef62ce7 119 if (enable) {
emilmont 10:3bc89ef62ce7 120 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
emilmont 10:3bc89ef62ce7 121 } else {
emilmont 10:3bc89ef62ce7 122 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
emilmont 10:3bc89ef62ce7 123 }
emilmont 10:3bc89ef62ce7 124 break;
emilmont 10:3bc89ef62ce7 125 }
emilmont 10:3bc89ef62ce7 126 } else {
emilmont 10:3bc89ef62ce7 127 switch (obj->port) {
emilmont 10:3bc89ef62ce7 128 case LPC_GPIO0_BASE:
emilmont 10:3bc89ef62ce7 129 if (enable) {
emilmont 10:3bc89ef62ce7 130 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
emilmont 10:3bc89ef62ce7 131 } else {
emilmont 10:3bc89ef62ce7 132 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
emilmont 10:3bc89ef62ce7 133 }
emilmont 10:3bc89ef62ce7 134 break;
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136 case LPC_GPIO2_BASE:
emilmont 10:3bc89ef62ce7 137 if (enable) {
emilmont 10:3bc89ef62ce7 138 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
emilmont 10:3bc89ef62ce7 139 } else {
emilmont 10:3bc89ef62ce7 140 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
emilmont 10:3bc89ef62ce7 141 }
emilmont 10:3bc89ef62ce7 142 break;
emilmont 10:3bc89ef62ce7 143 }
emilmont 10:3bc89ef62ce7 144 }
emilmont 10:3bc89ef62ce7 145 }