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mbed library sources

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targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Child:
15:4892fe388435
Update mbed sources to revision 64

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bogdanm 13:0645d8841f51 1 /* mbed Microcontroller Library - cmsis_nvic for LPC11U24
bogdanm 13:0645d8841f51 2 * Copyright (c) 2011 ARM Limited. All rights reserved.
bogdanm 13:0645d8841f51 3 *
bogdanm 13:0645d8841f51 4 * CMSIS-style functionality to support dynamic vectors
bogdanm 13:0645d8841f51 5 */
bogdanm 13:0645d8841f51 6
bogdanm 13:0645d8841f51 7 #include "cmsis_nvic.h"
bogdanm 13:0645d8841f51 8
bogdanm 13:0645d8841f51 9 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
bogdanm 13:0645d8841f51 10 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
bogdanm 13:0645d8841f51 11 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
bogdanm 13:0645d8841f51 12 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
bogdanm 13:0645d8841f51 13 *
bogdanm 13:0645d8841f51 14 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
bogdanm 13:0645d8841f51 15 * above the vector table before 0x200 will actually go to RAM. So we need to provide
bogdanm 13:0645d8841f51 16 * a solution where the compiler gets the right results based on the memory map
bogdanm 13:0645d8841f51 17 *
bogdanm 13:0645d8841f51 18 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
bogdanm 13:0645d8841f51 19 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
bogdanm 13:0645d8841f51 20 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
bogdanm 13:0645d8841f51 21 *
bogdanm 13:0645d8841f51 22 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
bogdanm 13:0645d8841f51 23 * - No flash accesses will go to ram, as there will be nothing there
bogdanm 13:0645d8841f51 24 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
bogdanm 13:0645d8841f51 25 * - RAM overhead: 0, FLASH overhead: 320 bytes
bogdanm 13:0645d8841f51 26 *
bogdanm 13:0645d8841f51 27 * Option 2 is the one to go for, as RAM is the most valuable resource
bogdanm 13:0645d8841f51 28 */
bogdanm 13:0645d8841f51 29
bogdanm 13:0645d8841f51 30 #define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
bogdanm 13:0645d8841f51 31 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
bogdanm 13:0645d8841f51 32
bogdanm 13:0645d8841f51 33 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
bogdanm 13:0645d8841f51 34 int i;
bogdanm 13:0645d8841f51 35 // Space for dynamic vectors, initialised to allocate in R/W
bogdanm 13:0645d8841f51 36 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
bogdanm 13:0645d8841f51 37
bogdanm 13:0645d8841f51 38 // Copy and switch to dynamic vectors if first time called
bogdanm 13:0645d8841f51 39 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
bogdanm 13:0645d8841f51 40 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
bogdanm 13:0645d8841f51 41 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
bogdanm 13:0645d8841f51 42 vectors[i] = old_vectors[i];
bogdanm 13:0645d8841f51 43 }
bogdanm 13:0645d8841f51 44 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
bogdanm 13:0645d8841f51 45 }
bogdanm 13:0645d8841f51 46
bogdanm 13:0645d8841f51 47 // Set the vector
bogdanm 13:0645d8841f51 48 vectors[IRQn + 16] = vector;
bogdanm 13:0645d8841f51 49 }
bogdanm 13:0645d8841f51 50
bogdanm 13:0645d8841f51 51 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
bogdanm 13:0645d8841f51 52 // We can always read vectors at 0x0, as the addresses are remapped
bogdanm 13:0645d8841f51 53 uint32_t *vectors = (uint32_t*)0;
bogdanm 13:0645d8841f51 54
bogdanm 13:0645d8841f51 55 // Return the vector
bogdanm 13:0645d8841f51 56 return vectors[IRQn + 16];
bogdanm 13:0645d8841f51 57 }
bogdanm 13:0645d8841f51 58