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targets/cmsis/TARGET_Freescale/TARGET_KL25Z/MKL25Z4.h@13:0645d8841f51, 2013-08-05 (annotated)

Committer:: bogdanm
Date:: Mon Aug 05 14:12:34 2013 +0300
Revision:: 13:0645d8841f51
Parent:: vendor/Freescale/KL25Z/cmsis/MKL25Z4.h@10:3bc89ef62ce7

Update mbed sources to revision 64

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	10:3bc89ef62ce7	1	/*
emilmont	10:3bc89ef62ce7	2	** ###################################################################
emilmont	10:3bc89ef62ce7	3	** Processor: MKL25Z128VLK4
emilmont	10:3bc89ef62ce7	4	** Compilers: ARM Compiler
emilmont	10:3bc89ef62ce7	5	** Freescale C/C++ for Embedded ARM
emilmont	10:3bc89ef62ce7	6	** GNU C Compiler
emilmont	10:3bc89ef62ce7	7	** IAR ANSI C/C++ Compiler for ARM
emilmont	10:3bc89ef62ce7	8	**
emilmont	10:3bc89ef62ce7	9	** Reference manual: KL25RM, Rev.1, Jun 2012
emilmont	10:3bc89ef62ce7	10	** Version: rev. 1.1, 2012-06-21
emilmont	10:3bc89ef62ce7	11	**
emilmont	10:3bc89ef62ce7	12	** Abstract:
emilmont	10:3bc89ef62ce7	13	** CMSIS Peripheral Access Layer for MKL25Z4
emilmont	10:3bc89ef62ce7	14	**
emilmont	10:3bc89ef62ce7	15	** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
emilmont	10:3bc89ef62ce7	16	**
emilmont	10:3bc89ef62ce7	17	** http: www.freescale.com
emilmont	10:3bc89ef62ce7	18	** mail: support@freescale.com
emilmont	10:3bc89ef62ce7	19	**
emilmont	10:3bc89ef62ce7	20	** Revisions:
emilmont	10:3bc89ef62ce7	21	** - rev. 1.0 (2012-06-13)
emilmont	10:3bc89ef62ce7	22	** Initial version.
emilmont	10:3bc89ef62ce7	23	** - rev. 1.1 (2012-06-21)
emilmont	10:3bc89ef62ce7	24	** Update according to reference manual rev. 1.
emilmont	10:3bc89ef62ce7	25	**
emilmont	10:3bc89ef62ce7	26	** ###################################################################
emilmont	10:3bc89ef62ce7	27	*/
emilmont	10:3bc89ef62ce7	28
emilmont	10:3bc89ef62ce7	29	/**
emilmont	10:3bc89ef62ce7	30	* @file MKL25Z4.h
emilmont	10:3bc89ef62ce7	31	* @version 1.1
emilmont	10:3bc89ef62ce7	32	* @date 2012-06-21
emilmont	10:3bc89ef62ce7	33	* @brief CMSIS Peripheral Access Layer for MKL25Z4
emilmont	10:3bc89ef62ce7	34	*
emilmont	10:3bc89ef62ce7	35	* CMSIS Peripheral Access Layer for MKL25Z4
emilmont	10:3bc89ef62ce7	36	*/
emilmont	10:3bc89ef62ce7	37
emilmont	10:3bc89ef62ce7	38	#if !defined(MKL25Z4_H_)
emilmont	10:3bc89ef62ce7	39	#define MKL25Z4_H_ /*< Symbol preventing repeated inclusion /
emilmont	10:3bc89ef62ce7	40
emilmont	10:3bc89ef62ce7	41	/** Memory map major version (memory maps with equal major version number are
emilmont	10:3bc89ef62ce7	42	* compatible) */
emilmont	10:3bc89ef62ce7	43	#define MCU_MEM_MAP_VERSION 0x0100u
emilmont	10:3bc89ef62ce7	44	/** Memory map minor version */
emilmont	10:3bc89ef62ce7	45	#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
emilmont	10:3bc89ef62ce7	46
emilmont	10:3bc89ef62ce7	47
emilmont	10:3bc89ef62ce7	48	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	49	-- Interrupt vector numbers
emilmont	10:3bc89ef62ce7	50	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	51
emilmont	10:3bc89ef62ce7	52	/**
emilmont	10:3bc89ef62ce7	53	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
emilmont	10:3bc89ef62ce7	54	* @{
emilmont	10:3bc89ef62ce7	55	*/
emilmont	10:3bc89ef62ce7	56
emilmont	10:3bc89ef62ce7	57	/** Interrupt Number Definitions */
emilmont	10:3bc89ef62ce7	58	typedef enum IRQn {
emilmont	10:3bc89ef62ce7	59	/* Core interrupts */
emilmont	10:3bc89ef62ce7	60	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
emilmont	10:3bc89ef62ce7	61	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
emilmont	10:3bc89ef62ce7	62	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
emilmont	10:3bc89ef62ce7	63	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
emilmont	10:3bc89ef62ce7	64	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
emilmont	10:3bc89ef62ce7	65
emilmont	10:3bc89ef62ce7	66	/* Device specific interrupts */
emilmont	10:3bc89ef62ce7	67	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
emilmont	10:3bc89ef62ce7	68	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
emilmont	10:3bc89ef62ce7	69	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
emilmont	10:3bc89ef62ce7	70	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
emilmont	10:3bc89ef62ce7	71	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
emilmont	10:3bc89ef62ce7	72	FTFA_IRQn = 5, /*< FTFA interrupt /
emilmont	10:3bc89ef62ce7	73	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
emilmont	10:3bc89ef62ce7	74	LLW_IRQn = 7, /*< Low Leakage Wakeup /
emilmont	10:3bc89ef62ce7	75	I2C0_IRQn = 8, /*< I2C0 interrupt /
emilmont	10:3bc89ef62ce7	76	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
emilmont	10:3bc89ef62ce7	77	SPI0_IRQn = 10, /*< SPI0 interrupt /
emilmont	10:3bc89ef62ce7	78	SPI1_IRQn = 11, /*< SPI1 interrupt /
emilmont	10:3bc89ef62ce7	79	UART0_IRQn = 12, /*< UART0 status/error interrupt /
emilmont	10:3bc89ef62ce7	80	UART1_IRQn = 13, /*< UART1 status/error interrupt /
emilmont	10:3bc89ef62ce7	81	UART2_IRQn = 14, /*< UART2 status/error interrupt /
emilmont	10:3bc89ef62ce7	82	ADC0_IRQn = 15, /*< ADC0 interrupt /
emilmont	10:3bc89ef62ce7	83	CMP0_IRQn = 16, /*< CMP0 interrupt /
emilmont	10:3bc89ef62ce7	84	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
emilmont	10:3bc89ef62ce7	85	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
emilmont	10:3bc89ef62ce7	86	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
emilmont	10:3bc89ef62ce7	87	RTC_IRQn = 20, /*< RTC interrupt /
emilmont	10:3bc89ef62ce7	88	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
emilmont	10:3bc89ef62ce7	89	PIT_IRQn = 22, /*< PIT timer interrupt /
emilmont	10:3bc89ef62ce7	90	Reserved39_IRQn = 23, /*< Reserved interrupt 39 /
emilmont	10:3bc89ef62ce7	91	USB0_IRQn = 24, /*< USB0 interrupt /
emilmont	10:3bc89ef62ce7	92	DAC0_IRQn = 25, /*< DAC interrupt /
emilmont	10:3bc89ef62ce7	93	TSI0_IRQn = 26, /*< TSI0 interrupt /
emilmont	10:3bc89ef62ce7	94	MCG_IRQn = 27, /*< MCG interrupt /
emilmont	10:3bc89ef62ce7	95	LPTimer_IRQn = 28, /*< LPTimer interrupt /
emilmont	10:3bc89ef62ce7	96	Reserved45_IRQn = 29, /*< Reserved interrupt 45 /
emilmont	10:3bc89ef62ce7	97	PORTA_IRQn = 30, /*< Port A interrupt /
emilmont	10:3bc89ef62ce7	98	PORTD_IRQn = 31 /*< Port D interrupt /
emilmont	10:3bc89ef62ce7	99	} IRQn_Type;
emilmont	10:3bc89ef62ce7	100
emilmont	10:3bc89ef62ce7	101	/**
emilmont	10:3bc89ef62ce7	102	* @}
emilmont	10:3bc89ef62ce7	103	/ / end of group Interrupt_vector_numbers */
emilmont	10:3bc89ef62ce7	104
emilmont	10:3bc89ef62ce7	105
emilmont	10:3bc89ef62ce7	106	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	107	-- Cortex M0 Core Configuration
emilmont	10:3bc89ef62ce7	108	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	109
emilmont	10:3bc89ef62ce7	110	/**
emilmont	10:3bc89ef62ce7	111	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
emilmont	10:3bc89ef62ce7	112	* @{
emilmont	10:3bc89ef62ce7	113	*/
emilmont	10:3bc89ef62ce7	114
emilmont	10:3bc89ef62ce7	115	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
emilmont	10:3bc89ef62ce7	116	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
emilmont	10:3bc89ef62ce7	117	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
emilmont	10:3bc89ef62ce7	118	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
emilmont	10:3bc89ef62ce7	119	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
emilmont	10:3bc89ef62ce7	120
emilmont	10:3bc89ef62ce7	121	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
emilmont	10:3bc89ef62ce7	122	#include "system_MKL25Z4.h" /* Device specific configuration file */
emilmont	10:3bc89ef62ce7	123
emilmont	10:3bc89ef62ce7	124	/**
emilmont	10:3bc89ef62ce7	125	* @}
emilmont	10:3bc89ef62ce7	126	/ / end of group Cortex_Core_Configuration */
emilmont	10:3bc89ef62ce7	127
emilmont	10:3bc89ef62ce7	128
emilmont	10:3bc89ef62ce7	129	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	130	-- Device Peripheral Access Layer
emilmont	10:3bc89ef62ce7	131	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	132
emilmont	10:3bc89ef62ce7	133	/**
emilmont	10:3bc89ef62ce7	134	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
emilmont	10:3bc89ef62ce7	135	* @{
emilmont	10:3bc89ef62ce7	136	*/
emilmont	10:3bc89ef62ce7	137
emilmont	10:3bc89ef62ce7	138
emilmont	10:3bc89ef62ce7	139	/*
emilmont	10:3bc89ef62ce7	140	** Start of section using anonymous unions
emilmont	10:3bc89ef62ce7	141	*/
emilmont	10:3bc89ef62ce7	142
emilmont	10:3bc89ef62ce7	143	#if defined(__ARMCC_VERSION)
emilmont	10:3bc89ef62ce7	144	#pragma push
emilmont	10:3bc89ef62ce7	145	#pragma anon_unions
emilmont	10:3bc89ef62ce7	146	#elif defined(__CWCC__)
emilmont	10:3bc89ef62ce7	147	#pragma push
emilmont	10:3bc89ef62ce7	148	#pragma cpp_extensions on
emilmont	10:3bc89ef62ce7	149	#elif defined(__GNUC__)
emilmont	10:3bc89ef62ce7	150	/* anonymous unions are enabled by default */
emilmont	10:3bc89ef62ce7	151	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	10:3bc89ef62ce7	152	#pragma language=extended
emilmont	10:3bc89ef62ce7	153	#else
emilmont	10:3bc89ef62ce7	154	#error Not supported compiler type
emilmont	10:3bc89ef62ce7	155	#endif
emilmont	10:3bc89ef62ce7	156
emilmont	10:3bc89ef62ce7	157	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	158	-- ADC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	159	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	160
emilmont	10:3bc89ef62ce7	161	/**
emilmont	10:3bc89ef62ce7	162	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	163	* @{
emilmont	10:3bc89ef62ce7	164	*/
emilmont	10:3bc89ef62ce7	165
emilmont	10:3bc89ef62ce7	166	/** ADC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	167	typedef struct {
emilmont	10:3bc89ef62ce7	168	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	169	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
emilmont	10:3bc89ef62ce7	170	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
emilmont	10:3bc89ef62ce7	171	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
emilmont	10:3bc89ef62ce7	172	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
emilmont	10:3bc89ef62ce7	173	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
emilmont	10:3bc89ef62ce7	174	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
emilmont	10:3bc89ef62ce7	175	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
emilmont	10:3bc89ef62ce7	176	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
emilmont	10:3bc89ef62ce7	177	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
emilmont	10:3bc89ef62ce7	178	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
emilmont	10:3bc89ef62ce7	179	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
emilmont	10:3bc89ef62ce7	180	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
emilmont	10:3bc89ef62ce7	181	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
emilmont	10:3bc89ef62ce7	182	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
emilmont	10:3bc89ef62ce7	183	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
emilmont	10:3bc89ef62ce7	184	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
emilmont	10:3bc89ef62ce7	185	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
emilmont	10:3bc89ef62ce7	186	uint8_t RESERVED_0[4];
emilmont	10:3bc89ef62ce7	187	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
emilmont	10:3bc89ef62ce7	188	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
emilmont	10:3bc89ef62ce7	189	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
emilmont	10:3bc89ef62ce7	190	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
emilmont	10:3bc89ef62ce7	191	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
emilmont	10:3bc89ef62ce7	192	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
emilmont	10:3bc89ef62ce7	193	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
emilmont	10:3bc89ef62ce7	194	} ADC_Type;
emilmont	10:3bc89ef62ce7	195
emilmont	10:3bc89ef62ce7	196	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	197	-- ADC Register Masks
emilmont	10:3bc89ef62ce7	198	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	199
emilmont	10:3bc89ef62ce7	200	/**
emilmont	10:3bc89ef62ce7	201	* @addtogroup ADC_Register_Masks ADC Register Masks
emilmont	10:3bc89ef62ce7	202	* @{
emilmont	10:3bc89ef62ce7	203	*/
emilmont	10:3bc89ef62ce7	204
emilmont	10:3bc89ef62ce7	205	/* SC1 Bit Fields */
emilmont	10:3bc89ef62ce7	206	#define ADC_SC1_ADCH_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	207	#define ADC_SC1_ADCH_SHIFT 0
emilmont	10:3bc89ef62ce7	208	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
emilmont	10:3bc89ef62ce7	209	#define ADC_SC1_DIFF_MASK 0x20u
emilmont	10:3bc89ef62ce7	210	#define ADC_SC1_DIFF_SHIFT 5
emilmont	10:3bc89ef62ce7	211	#define ADC_SC1_AIEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	212	#define ADC_SC1_AIEN_SHIFT 6
emilmont	10:3bc89ef62ce7	213	#define ADC_SC1_COCO_MASK 0x80u
emilmont	10:3bc89ef62ce7	214	#define ADC_SC1_COCO_SHIFT 7
emilmont	10:3bc89ef62ce7	215	/* CFG1 Bit Fields */
emilmont	10:3bc89ef62ce7	216	#define ADC_CFG1_ADICLK_MASK 0x3u
emilmont	10:3bc89ef62ce7	217	#define ADC_CFG1_ADICLK_SHIFT 0
emilmont	10:3bc89ef62ce7	218	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
emilmont	10:3bc89ef62ce7	219	#define ADC_CFG1_MODE_MASK 0xCu
emilmont	10:3bc89ef62ce7	220	#define ADC_CFG1_MODE_SHIFT 2
emilmont	10:3bc89ef62ce7	221	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
emilmont	10:3bc89ef62ce7	222	#define ADC_CFG1_ADLSMP_MASK 0x10u
emilmont	10:3bc89ef62ce7	223	#define ADC_CFG1_ADLSMP_SHIFT 4
emilmont	10:3bc89ef62ce7	224	#define ADC_CFG1_ADIV_MASK 0x60u
emilmont	10:3bc89ef62ce7	225	#define ADC_CFG1_ADIV_SHIFT 5
emilmont	10:3bc89ef62ce7	226	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
emilmont	10:3bc89ef62ce7	227	#define ADC_CFG1_ADLPC_MASK 0x80u
emilmont	10:3bc89ef62ce7	228	#define ADC_CFG1_ADLPC_SHIFT 7
emilmont	10:3bc89ef62ce7	229	/* CFG2 Bit Fields */
emilmont	10:3bc89ef62ce7	230	#define ADC_CFG2_ADLSTS_MASK 0x3u
emilmont	10:3bc89ef62ce7	231	#define ADC_CFG2_ADLSTS_SHIFT 0
emilmont	10:3bc89ef62ce7	232	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
emilmont	10:3bc89ef62ce7	233	#define ADC_CFG2_ADHSC_MASK 0x4u
emilmont	10:3bc89ef62ce7	234	#define ADC_CFG2_ADHSC_SHIFT 2
emilmont	10:3bc89ef62ce7	235	#define ADC_CFG2_ADACKEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	236	#define ADC_CFG2_ADACKEN_SHIFT 3
emilmont	10:3bc89ef62ce7	237	#define ADC_CFG2_MUXSEL_MASK 0x10u
emilmont	10:3bc89ef62ce7	238	#define ADC_CFG2_MUXSEL_SHIFT 4
emilmont	10:3bc89ef62ce7	239	/* R Bit Fields */
emilmont	10:3bc89ef62ce7	240	#define ADC_R_D_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	241	#define ADC_R_D_SHIFT 0
emilmont	10:3bc89ef62ce7	242	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
emilmont	10:3bc89ef62ce7	243	/* CV1 Bit Fields */
emilmont	10:3bc89ef62ce7	244	#define ADC_CV1_CV_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	245	#define ADC_CV1_CV_SHIFT 0
emilmont	10:3bc89ef62ce7	246	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
emilmont	10:3bc89ef62ce7	247	/* CV2 Bit Fields */
emilmont	10:3bc89ef62ce7	248	#define ADC_CV2_CV_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	249	#define ADC_CV2_CV_SHIFT 0
emilmont	10:3bc89ef62ce7	250	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
emilmont	10:3bc89ef62ce7	251	/* SC2 Bit Fields */
emilmont	10:3bc89ef62ce7	252	#define ADC_SC2_REFSEL_MASK 0x3u
emilmont	10:3bc89ef62ce7	253	#define ADC_SC2_REFSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	254	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
emilmont	10:3bc89ef62ce7	255	#define ADC_SC2_DMAEN_MASK 0x4u
emilmont	10:3bc89ef62ce7	256	#define ADC_SC2_DMAEN_SHIFT 2
emilmont	10:3bc89ef62ce7	257	#define ADC_SC2_ACREN_MASK 0x8u
emilmont	10:3bc89ef62ce7	258	#define ADC_SC2_ACREN_SHIFT 3
emilmont	10:3bc89ef62ce7	259	#define ADC_SC2_ACFGT_MASK 0x10u
emilmont	10:3bc89ef62ce7	260	#define ADC_SC2_ACFGT_SHIFT 4
emilmont	10:3bc89ef62ce7	261	#define ADC_SC2_ACFE_MASK 0x20u
emilmont	10:3bc89ef62ce7	262	#define ADC_SC2_ACFE_SHIFT 5
emilmont	10:3bc89ef62ce7	263	#define ADC_SC2_ADTRG_MASK 0x40u
emilmont	10:3bc89ef62ce7	264	#define ADC_SC2_ADTRG_SHIFT 6
emilmont	10:3bc89ef62ce7	265	#define ADC_SC2_ADACT_MASK 0x80u
emilmont	10:3bc89ef62ce7	266	#define ADC_SC2_ADACT_SHIFT 7
emilmont	10:3bc89ef62ce7	267	/* SC3 Bit Fields */
emilmont	10:3bc89ef62ce7	268	#define ADC_SC3_AVGS_MASK 0x3u
emilmont	10:3bc89ef62ce7	269	#define ADC_SC3_AVGS_SHIFT 0
emilmont	10:3bc89ef62ce7	270	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
emilmont	10:3bc89ef62ce7	271	#define ADC_SC3_AVGE_MASK 0x4u
emilmont	10:3bc89ef62ce7	272	#define ADC_SC3_AVGE_SHIFT 2
emilmont	10:3bc89ef62ce7	273	#define ADC_SC3_ADCO_MASK 0x8u
emilmont	10:3bc89ef62ce7	274	#define ADC_SC3_ADCO_SHIFT 3
emilmont	10:3bc89ef62ce7	275	#define ADC_SC3_CALF_MASK 0x40u
emilmont	10:3bc89ef62ce7	276	#define ADC_SC3_CALF_SHIFT 6
emilmont	10:3bc89ef62ce7	277	#define ADC_SC3_CAL_MASK 0x80u
emilmont	10:3bc89ef62ce7	278	#define ADC_SC3_CAL_SHIFT 7
emilmont	10:3bc89ef62ce7	279	/* OFS Bit Fields */
emilmont	10:3bc89ef62ce7	280	#define ADC_OFS_OFS_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	281	#define ADC_OFS_OFS_SHIFT 0
emilmont	10:3bc89ef62ce7	282	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
emilmont	10:3bc89ef62ce7	283	/* PG Bit Fields */
emilmont	10:3bc89ef62ce7	284	#define ADC_PG_PG_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	285	#define ADC_PG_PG_SHIFT 0
emilmont	10:3bc89ef62ce7	286	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
emilmont	10:3bc89ef62ce7	287	/* MG Bit Fields */
emilmont	10:3bc89ef62ce7	288	#define ADC_MG_MG_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	289	#define ADC_MG_MG_SHIFT 0
emilmont	10:3bc89ef62ce7	290	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
emilmont	10:3bc89ef62ce7	291	/* CLPD Bit Fields */
emilmont	10:3bc89ef62ce7	292	#define ADC_CLPD_CLPD_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	293	#define ADC_CLPD_CLPD_SHIFT 0
emilmont	10:3bc89ef62ce7	294	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
emilmont	10:3bc89ef62ce7	295	/* CLPS Bit Fields */
emilmont	10:3bc89ef62ce7	296	#define ADC_CLPS_CLPS_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	297	#define ADC_CLPS_CLPS_SHIFT 0
emilmont	10:3bc89ef62ce7	298	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
emilmont	10:3bc89ef62ce7	299	/* CLP4 Bit Fields */
emilmont	10:3bc89ef62ce7	300	#define ADC_CLP4_CLP4_MASK 0x3FFu
emilmont	10:3bc89ef62ce7	301	#define ADC_CLP4_CLP4_SHIFT 0
emilmont	10:3bc89ef62ce7	302	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
emilmont	10:3bc89ef62ce7	303	/* CLP3 Bit Fields */
emilmont	10:3bc89ef62ce7	304	#define ADC_CLP3_CLP3_MASK 0x1FFu
emilmont	10:3bc89ef62ce7	305	#define ADC_CLP3_CLP3_SHIFT 0
emilmont	10:3bc89ef62ce7	306	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
emilmont	10:3bc89ef62ce7	307	/* CLP2 Bit Fields */
emilmont	10:3bc89ef62ce7	308	#define ADC_CLP2_CLP2_MASK 0xFFu
emilmont	10:3bc89ef62ce7	309	#define ADC_CLP2_CLP2_SHIFT 0
emilmont	10:3bc89ef62ce7	310	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
emilmont	10:3bc89ef62ce7	311	/* CLP1 Bit Fields */
emilmont	10:3bc89ef62ce7	312	#define ADC_CLP1_CLP1_MASK 0x7Fu
emilmont	10:3bc89ef62ce7	313	#define ADC_CLP1_CLP1_SHIFT 0
emilmont	10:3bc89ef62ce7	314	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
emilmont	10:3bc89ef62ce7	315	/* CLP0 Bit Fields */
emilmont	10:3bc89ef62ce7	316	#define ADC_CLP0_CLP0_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	317	#define ADC_CLP0_CLP0_SHIFT 0
emilmont	10:3bc89ef62ce7	318	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
emilmont	10:3bc89ef62ce7	319	/* CLMD Bit Fields */
emilmont	10:3bc89ef62ce7	320	#define ADC_CLMD_CLMD_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	321	#define ADC_CLMD_CLMD_SHIFT 0
emilmont	10:3bc89ef62ce7	322	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
emilmont	10:3bc89ef62ce7	323	/* CLMS Bit Fields */
emilmont	10:3bc89ef62ce7	324	#define ADC_CLMS_CLMS_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	325	#define ADC_CLMS_CLMS_SHIFT 0
emilmont	10:3bc89ef62ce7	326	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
emilmont	10:3bc89ef62ce7	327	/* CLM4 Bit Fields */
emilmont	10:3bc89ef62ce7	328	#define ADC_CLM4_CLM4_MASK 0x3FFu
emilmont	10:3bc89ef62ce7	329	#define ADC_CLM4_CLM4_SHIFT 0
emilmont	10:3bc89ef62ce7	330	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
emilmont	10:3bc89ef62ce7	331	/* CLM3 Bit Fields */
emilmont	10:3bc89ef62ce7	332	#define ADC_CLM3_CLM3_MASK 0x1FFu
emilmont	10:3bc89ef62ce7	333	#define ADC_CLM3_CLM3_SHIFT 0
emilmont	10:3bc89ef62ce7	334	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
emilmont	10:3bc89ef62ce7	335	/* CLM2 Bit Fields */
emilmont	10:3bc89ef62ce7	336	#define ADC_CLM2_CLM2_MASK 0xFFu
emilmont	10:3bc89ef62ce7	337	#define ADC_CLM2_CLM2_SHIFT 0
emilmont	10:3bc89ef62ce7	338	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
emilmont	10:3bc89ef62ce7	339	/* CLM1 Bit Fields */
emilmont	10:3bc89ef62ce7	340	#define ADC_CLM1_CLM1_MASK 0x7Fu
emilmont	10:3bc89ef62ce7	341	#define ADC_CLM1_CLM1_SHIFT 0
emilmont	10:3bc89ef62ce7	342	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
emilmont	10:3bc89ef62ce7	343	/* CLM0 Bit Fields */
emilmont	10:3bc89ef62ce7	344	#define ADC_CLM0_CLM0_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	345	#define ADC_CLM0_CLM0_SHIFT 0
emilmont	10:3bc89ef62ce7	346	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
emilmont	10:3bc89ef62ce7	347
emilmont	10:3bc89ef62ce7	348	/**
emilmont	10:3bc89ef62ce7	349	* @}
emilmont	10:3bc89ef62ce7	350	/ / end of group ADC_Register_Masks */
emilmont	10:3bc89ef62ce7	351
emilmont	10:3bc89ef62ce7	352
emilmont	10:3bc89ef62ce7	353	/* ADC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	354	/** Peripheral ADC0 base address */
emilmont	10:3bc89ef62ce7	355	#define ADC0_BASE (0x4003B000u)
emilmont	10:3bc89ef62ce7	356	/** Peripheral ADC0 base pointer */
emilmont	10:3bc89ef62ce7	357	#define ADC0 ((ADC_Type *)ADC0_BASE)
emilmont	10:3bc89ef62ce7	358	/** Array initializer of ADC peripheral base pointers */
emilmont	10:3bc89ef62ce7	359	#define ADC_BASES { ADC0 }
emilmont	10:3bc89ef62ce7	360
emilmont	10:3bc89ef62ce7	361	/**
emilmont	10:3bc89ef62ce7	362	* @}
emilmont	10:3bc89ef62ce7	363	/ / end of group ADC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	364
emilmont	10:3bc89ef62ce7	365
emilmont	10:3bc89ef62ce7	366	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	367	-- CMP Peripheral Access Layer
emilmont	10:3bc89ef62ce7	368	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	369
emilmont	10:3bc89ef62ce7	370	/**
emilmont	10:3bc89ef62ce7	371	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
emilmont	10:3bc89ef62ce7	372	* @{
emilmont	10:3bc89ef62ce7	373	*/
emilmont	10:3bc89ef62ce7	374
emilmont	10:3bc89ef62ce7	375	/** CMP - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	376	typedef struct {
emilmont	10:3bc89ef62ce7	377	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
emilmont	10:3bc89ef62ce7	378	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
emilmont	10:3bc89ef62ce7	379	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	380	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	381	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	382	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
emilmont	10:3bc89ef62ce7	383	} CMP_Type;
emilmont	10:3bc89ef62ce7	384
emilmont	10:3bc89ef62ce7	385	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	386	-- CMP Register Masks
emilmont	10:3bc89ef62ce7	387	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	388
emilmont	10:3bc89ef62ce7	389	/**
emilmont	10:3bc89ef62ce7	390	* @addtogroup CMP_Register_Masks CMP Register Masks
emilmont	10:3bc89ef62ce7	391	* @{
emilmont	10:3bc89ef62ce7	392	*/
emilmont	10:3bc89ef62ce7	393
emilmont	10:3bc89ef62ce7	394	/* CR0 Bit Fields */
emilmont	10:3bc89ef62ce7	395	#define CMP_CR0_HYSTCTR_MASK 0x3u
emilmont	10:3bc89ef62ce7	396	#define CMP_CR0_HYSTCTR_SHIFT 0
emilmont	10:3bc89ef62ce7	397	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
emilmont	10:3bc89ef62ce7	398	#define CMP_CR0_FILTER_CNT_MASK 0x70u
emilmont	10:3bc89ef62ce7	399	#define CMP_CR0_FILTER_CNT_SHIFT 4
emilmont	10:3bc89ef62ce7	400	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
emilmont	10:3bc89ef62ce7	401	/* CR1 Bit Fields */
emilmont	10:3bc89ef62ce7	402	#define CMP_CR1_EN_MASK 0x1u
emilmont	10:3bc89ef62ce7	403	#define CMP_CR1_EN_SHIFT 0
emilmont	10:3bc89ef62ce7	404	#define CMP_CR1_OPE_MASK 0x2u
emilmont	10:3bc89ef62ce7	405	#define CMP_CR1_OPE_SHIFT 1
emilmont	10:3bc89ef62ce7	406	#define CMP_CR1_COS_MASK 0x4u
emilmont	10:3bc89ef62ce7	407	#define CMP_CR1_COS_SHIFT 2
emilmont	10:3bc89ef62ce7	408	#define CMP_CR1_INV_MASK 0x8u
emilmont	10:3bc89ef62ce7	409	#define CMP_CR1_INV_SHIFT 3
emilmont	10:3bc89ef62ce7	410	#define CMP_CR1_PMODE_MASK 0x10u
emilmont	10:3bc89ef62ce7	411	#define CMP_CR1_PMODE_SHIFT 4
emilmont	10:3bc89ef62ce7	412	#define CMP_CR1_TRIGM_MASK 0x20u
emilmont	10:3bc89ef62ce7	413	#define CMP_CR1_TRIGM_SHIFT 5
emilmont	10:3bc89ef62ce7	414	#define CMP_CR1_WE_MASK 0x40u
emilmont	10:3bc89ef62ce7	415	#define CMP_CR1_WE_SHIFT 6
emilmont	10:3bc89ef62ce7	416	#define CMP_CR1_SE_MASK 0x80u
emilmont	10:3bc89ef62ce7	417	#define CMP_CR1_SE_SHIFT 7
emilmont	10:3bc89ef62ce7	418	/* FPR Bit Fields */
emilmont	10:3bc89ef62ce7	419	#define CMP_FPR_FILT_PER_MASK 0xFFu
emilmont	10:3bc89ef62ce7	420	#define CMP_FPR_FILT_PER_SHIFT 0
emilmont	10:3bc89ef62ce7	421	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
emilmont	10:3bc89ef62ce7	422	/* SCR Bit Fields */
emilmont	10:3bc89ef62ce7	423	#define CMP_SCR_COUT_MASK 0x1u
emilmont	10:3bc89ef62ce7	424	#define CMP_SCR_COUT_SHIFT 0
emilmont	10:3bc89ef62ce7	425	#define CMP_SCR_CFF_MASK 0x2u
emilmont	10:3bc89ef62ce7	426	#define CMP_SCR_CFF_SHIFT 1
emilmont	10:3bc89ef62ce7	427	#define CMP_SCR_CFR_MASK 0x4u
emilmont	10:3bc89ef62ce7	428	#define CMP_SCR_CFR_SHIFT 2
emilmont	10:3bc89ef62ce7	429	#define CMP_SCR_IEF_MASK 0x8u
emilmont	10:3bc89ef62ce7	430	#define CMP_SCR_IEF_SHIFT 3
emilmont	10:3bc89ef62ce7	431	#define CMP_SCR_IER_MASK 0x10u
emilmont	10:3bc89ef62ce7	432	#define CMP_SCR_IER_SHIFT 4
emilmont	10:3bc89ef62ce7	433	#define CMP_SCR_DMAEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	434	#define CMP_SCR_DMAEN_SHIFT 6
emilmont	10:3bc89ef62ce7	435	/* DACCR Bit Fields */
emilmont	10:3bc89ef62ce7	436	#define CMP_DACCR_VOSEL_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	437	#define CMP_DACCR_VOSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	438	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
emilmont	10:3bc89ef62ce7	439	#define CMP_DACCR_VRSEL_MASK 0x40u
emilmont	10:3bc89ef62ce7	440	#define CMP_DACCR_VRSEL_SHIFT 6
emilmont	10:3bc89ef62ce7	441	#define CMP_DACCR_DACEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	442	#define CMP_DACCR_DACEN_SHIFT 7
emilmont	10:3bc89ef62ce7	443	/* MUXCR Bit Fields */
emilmont	10:3bc89ef62ce7	444	#define CMP_MUXCR_MSEL_MASK 0x7u
emilmont	10:3bc89ef62ce7	445	#define CMP_MUXCR_MSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	446	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
emilmont	10:3bc89ef62ce7	447	#define CMP_MUXCR_PSEL_MASK 0x38u
emilmont	10:3bc89ef62ce7	448	#define CMP_MUXCR_PSEL_SHIFT 3
emilmont	10:3bc89ef62ce7	449	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
emilmont	10:3bc89ef62ce7	450	#define CMP_MUXCR_PSTM_MASK 0x40u
emilmont	10:3bc89ef62ce7	451	#define CMP_MUXCR_PSTM_SHIFT 6
emilmont	10:3bc89ef62ce7	452
emilmont	10:3bc89ef62ce7	453	/**
emilmont	10:3bc89ef62ce7	454	* @}
emilmont	10:3bc89ef62ce7	455	/ / end of group CMP_Register_Masks */
emilmont	10:3bc89ef62ce7	456
emilmont	10:3bc89ef62ce7	457
emilmont	10:3bc89ef62ce7	458	/* CMP - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	459	/** Peripheral CMP0 base address */
emilmont	10:3bc89ef62ce7	460	#define CMP0_BASE (0x40073000u)
emilmont	10:3bc89ef62ce7	461	/** Peripheral CMP0 base pointer */
emilmont	10:3bc89ef62ce7	462	#define CMP0 ((CMP_Type *)CMP0_BASE)
emilmont	10:3bc89ef62ce7	463	/** Array initializer of CMP peripheral base pointers */
emilmont	10:3bc89ef62ce7	464	#define CMP_BASES { CMP0 }
emilmont	10:3bc89ef62ce7	465
emilmont	10:3bc89ef62ce7	466	/**
emilmont	10:3bc89ef62ce7	467	* @}
emilmont	10:3bc89ef62ce7	468	/ / end of group CMP_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	469
emilmont	10:3bc89ef62ce7	470
emilmont	10:3bc89ef62ce7	471	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	472	-- DAC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	473	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	474
emilmont	10:3bc89ef62ce7	475	/**
emilmont	10:3bc89ef62ce7	476	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	477	* @{
emilmont	10:3bc89ef62ce7	478	*/
emilmont	10:3bc89ef62ce7	479
emilmont	10:3bc89ef62ce7	480	/** DAC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	481	typedef struct {
emilmont	10:3bc89ef62ce7	482	struct { /* offset: 0x0, array step: 0x2 */
emilmont	10:3bc89ef62ce7	483	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
emilmont	10:3bc89ef62ce7	484	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
emilmont	10:3bc89ef62ce7	485	} DAT[2];
emilmont	10:3bc89ef62ce7	486	uint8_t RESERVED_0[28];
emilmont	10:3bc89ef62ce7	487	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
emilmont	10:3bc89ef62ce7	488	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
emilmont	10:3bc89ef62ce7	489	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
emilmont	10:3bc89ef62ce7	490	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
emilmont	10:3bc89ef62ce7	491	} DAC_Type;
emilmont	10:3bc89ef62ce7	492
emilmont	10:3bc89ef62ce7	493	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	494	-- DAC Register Masks
emilmont	10:3bc89ef62ce7	495	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	496
emilmont	10:3bc89ef62ce7	497	/**
emilmont	10:3bc89ef62ce7	498	* @addtogroup DAC_Register_Masks DAC Register Masks
emilmont	10:3bc89ef62ce7	499	* @{
emilmont	10:3bc89ef62ce7	500	*/
emilmont	10:3bc89ef62ce7	501
emilmont	10:3bc89ef62ce7	502	/* DATL Bit Fields */
emilmont	10:3bc89ef62ce7	503	#define DAC_DATL_DATA0_MASK 0xFFu
emilmont	10:3bc89ef62ce7	504	#define DAC_DATL_DATA0_SHIFT 0
emilmont	10:3bc89ef62ce7	505	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
emilmont	10:3bc89ef62ce7	506	/* DATH Bit Fields */
emilmont	10:3bc89ef62ce7	507	#define DAC_DATH_DATA1_MASK 0xFu
emilmont	10:3bc89ef62ce7	508	#define DAC_DATH_DATA1_SHIFT 0
emilmont	10:3bc89ef62ce7	509	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
emilmont	10:3bc89ef62ce7	510	/* SR Bit Fields */
emilmont	10:3bc89ef62ce7	511	#define DAC_SR_DACBFRPBF_MASK 0x1u
emilmont	10:3bc89ef62ce7	512	#define DAC_SR_DACBFRPBF_SHIFT 0
emilmont	10:3bc89ef62ce7	513	#define DAC_SR_DACBFRPTF_MASK 0x2u
emilmont	10:3bc89ef62ce7	514	#define DAC_SR_DACBFRPTF_SHIFT 1
emilmont	10:3bc89ef62ce7	515	/* C0 Bit Fields */
emilmont	10:3bc89ef62ce7	516	#define DAC_C0_DACBBIEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	517	#define DAC_C0_DACBBIEN_SHIFT 0
emilmont	10:3bc89ef62ce7	518	#define DAC_C0_DACBTIEN_MASK 0x2u
emilmont	10:3bc89ef62ce7	519	#define DAC_C0_DACBTIEN_SHIFT 1
emilmont	10:3bc89ef62ce7	520	#define DAC_C0_LPEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	521	#define DAC_C0_LPEN_SHIFT 3
emilmont	10:3bc89ef62ce7	522	#define DAC_C0_DACSWTRG_MASK 0x10u
emilmont	10:3bc89ef62ce7	523	#define DAC_C0_DACSWTRG_SHIFT 4
emilmont	10:3bc89ef62ce7	524	#define DAC_C0_DACTRGSEL_MASK 0x20u
emilmont	10:3bc89ef62ce7	525	#define DAC_C0_DACTRGSEL_SHIFT 5
emilmont	10:3bc89ef62ce7	526	#define DAC_C0_DACRFS_MASK 0x40u
emilmont	10:3bc89ef62ce7	527	#define DAC_C0_DACRFS_SHIFT 6
emilmont	10:3bc89ef62ce7	528	#define DAC_C0_DACEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	529	#define DAC_C0_DACEN_SHIFT 7
emilmont	10:3bc89ef62ce7	530	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	531	#define DAC_C1_DACBFEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	532	#define DAC_C1_DACBFEN_SHIFT 0
emilmont	10:3bc89ef62ce7	533	#define DAC_C1_DACBFMD_MASK 0x4u
emilmont	10:3bc89ef62ce7	534	#define DAC_C1_DACBFMD_SHIFT 2
emilmont	10:3bc89ef62ce7	535	#define DAC_C1_DMAEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	536	#define DAC_C1_DMAEN_SHIFT 7
emilmont	10:3bc89ef62ce7	537	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	538	#define DAC_C2_DACBFUP_MASK 0x1u
emilmont	10:3bc89ef62ce7	539	#define DAC_C2_DACBFUP_SHIFT 0
emilmont	10:3bc89ef62ce7	540	#define DAC_C2_DACBFRP_MASK 0x10u
emilmont	10:3bc89ef62ce7	541	#define DAC_C2_DACBFRP_SHIFT 4
emilmont	10:3bc89ef62ce7	542
emilmont	10:3bc89ef62ce7	543	/**
emilmont	10:3bc89ef62ce7	544	* @}
emilmont	10:3bc89ef62ce7	545	/ / end of group DAC_Register_Masks */
emilmont	10:3bc89ef62ce7	546
emilmont	10:3bc89ef62ce7	547
emilmont	10:3bc89ef62ce7	548	/* DAC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	549	/** Peripheral DAC0 base address */
emilmont	10:3bc89ef62ce7	550	#define DAC0_BASE (0x4003F000u)
emilmont	10:3bc89ef62ce7	551	/** Peripheral DAC0 base pointer */
emilmont	10:3bc89ef62ce7	552	#define DAC0 ((DAC_Type *)DAC0_BASE)
emilmont	10:3bc89ef62ce7	553	/** Array initializer of DAC peripheral base pointers */
emilmont	10:3bc89ef62ce7	554	#define DAC_BASES { DAC0 }
emilmont	10:3bc89ef62ce7	555
emilmont	10:3bc89ef62ce7	556	/**
emilmont	10:3bc89ef62ce7	557	* @}
emilmont	10:3bc89ef62ce7	558	/ / end of group DAC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	559
emilmont	10:3bc89ef62ce7	560
emilmont	10:3bc89ef62ce7	561	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	562	-- DMA Peripheral Access Layer
emilmont	10:3bc89ef62ce7	563	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	564
emilmont	10:3bc89ef62ce7	565	/**
emilmont	10:3bc89ef62ce7	566	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
emilmont	10:3bc89ef62ce7	567	* @{
emilmont	10:3bc89ef62ce7	568	*/
emilmont	10:3bc89ef62ce7	569
emilmont	10:3bc89ef62ce7	570	/** DMA - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	571	typedef struct {
emilmont	10:3bc89ef62ce7	572	union { /* offset: 0x0 */
emilmont	10:3bc89ef62ce7	573	__IO uint8_t REQC_ARR[4]; /*< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 /
emilmont	10:3bc89ef62ce7	574	};
emilmont	10:3bc89ef62ce7	575	uint8_t RESERVED_0[252];
emilmont	10:3bc89ef62ce7	576	struct { /* offset: 0x100, array step: 0x10 */
emilmont	10:3bc89ef62ce7	577	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
emilmont	10:3bc89ef62ce7	578	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
emilmont	10:3bc89ef62ce7	579	union { /* offset: 0x108, array step: 0x10 */
emilmont	10:3bc89ef62ce7	580	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
emilmont	10:3bc89ef62ce7	581	struct { /* offset: 0x108, array step: 0x10 */
emilmont	10:3bc89ef62ce7	582	uint8_t RESERVED_0[3];
emilmont	10:3bc89ef62ce7	583	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
emilmont	10:3bc89ef62ce7	584	} DMA_DSR_ACCESS8BIT;
emilmont	10:3bc89ef62ce7	585	};
emilmont	10:3bc89ef62ce7	586	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
emilmont	10:3bc89ef62ce7	587	} DMA[4];
emilmont	10:3bc89ef62ce7	588	} DMA_Type;
emilmont	10:3bc89ef62ce7	589
emilmont	10:3bc89ef62ce7	590	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	591	-- DMA Register Masks
emilmont	10:3bc89ef62ce7	592	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	593
emilmont	10:3bc89ef62ce7	594	/**
emilmont	10:3bc89ef62ce7	595	* @addtogroup DMA_Register_Masks DMA Register Masks
emilmont	10:3bc89ef62ce7	596	* @{
emilmont	10:3bc89ef62ce7	597	*/
emilmont	10:3bc89ef62ce7	598
emilmont	10:3bc89ef62ce7	599	/* REQC_ARR Bit Fields */
emilmont	10:3bc89ef62ce7	600	#define DMA_REQC_ARR_DMAC_MASK 0xFu
emilmont	10:3bc89ef62ce7	601	#define DMA_REQC_ARR_DMAC_SHIFT 0
emilmont	10:3bc89ef62ce7	602	#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
emilmont	10:3bc89ef62ce7	603	#define DMA_REQC_ARR_CFSM_MASK 0x80u
emilmont	10:3bc89ef62ce7	604	#define DMA_REQC_ARR_CFSM_SHIFT 7
emilmont	10:3bc89ef62ce7	605	/* SAR Bit Fields */
emilmont	10:3bc89ef62ce7	606	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	607	#define DMA_SAR_SAR_SHIFT 0
emilmont	10:3bc89ef62ce7	608	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
emilmont	10:3bc89ef62ce7	609	/* DAR Bit Fields */
emilmont	10:3bc89ef62ce7	610	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	611	#define DMA_DAR_DAR_SHIFT 0
emilmont	10:3bc89ef62ce7	612	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
emilmont	10:3bc89ef62ce7	613	/* DSR_BCR Bit Fields */
emilmont	10:3bc89ef62ce7	614	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
emilmont	10:3bc89ef62ce7	615	#define DMA_DSR_BCR_BCR_SHIFT 0
emilmont	10:3bc89ef62ce7	616	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
emilmont	10:3bc89ef62ce7	617	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	618	#define DMA_DSR_BCR_DONE_SHIFT 24
emilmont	10:3bc89ef62ce7	619	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
emilmont	10:3bc89ef62ce7	620	#define DMA_DSR_BCR_BSY_SHIFT 25
emilmont	10:3bc89ef62ce7	621	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
emilmont	10:3bc89ef62ce7	622	#define DMA_DSR_BCR_REQ_SHIFT 26
emilmont	10:3bc89ef62ce7	623	#define DMA_DSR_BCR_BED_MASK 0x10000000u
emilmont	10:3bc89ef62ce7	624	#define DMA_DSR_BCR_BED_SHIFT 28
emilmont	10:3bc89ef62ce7	625	#define DMA_DSR_BCR_BES_MASK 0x20000000u
emilmont	10:3bc89ef62ce7	626	#define DMA_DSR_BCR_BES_SHIFT 29
emilmont	10:3bc89ef62ce7	627	#define DMA_DSR_BCR_CE_MASK 0x40000000u
emilmont	10:3bc89ef62ce7	628	#define DMA_DSR_BCR_CE_SHIFT 30
emilmont	10:3bc89ef62ce7	629	/* DCR Bit Fields */
emilmont	10:3bc89ef62ce7	630	#define DMA_DCR_LCH2_MASK 0x3u
emilmont	10:3bc89ef62ce7	631	#define DMA_DCR_LCH2_SHIFT 0
emilmont	10:3bc89ef62ce7	632	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
emilmont	10:3bc89ef62ce7	633	#define DMA_DCR_LCH1_MASK 0xCu
emilmont	10:3bc89ef62ce7	634	#define DMA_DCR_LCH1_SHIFT 2
emilmont	10:3bc89ef62ce7	635	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
emilmont	10:3bc89ef62ce7	636	#define DMA_DCR_LINKCC_MASK 0x30u
emilmont	10:3bc89ef62ce7	637	#define DMA_DCR_LINKCC_SHIFT 4
emilmont	10:3bc89ef62ce7	638	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
emilmont	10:3bc89ef62ce7	639	#define DMA_DCR_D_REQ_MASK 0x80u
emilmont	10:3bc89ef62ce7	640	#define DMA_DCR_D_REQ_SHIFT 7
emilmont	10:3bc89ef62ce7	641	#define DMA_DCR_DMOD_MASK 0xF00u
emilmont	10:3bc89ef62ce7	642	#define DMA_DCR_DMOD_SHIFT 8
emilmont	10:3bc89ef62ce7	643	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
emilmont	10:3bc89ef62ce7	644	#define DMA_DCR_SMOD_MASK 0xF000u
emilmont	10:3bc89ef62ce7	645	#define DMA_DCR_SMOD_SHIFT 12
emilmont	10:3bc89ef62ce7	646	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
emilmont	10:3bc89ef62ce7	647	#define DMA_DCR_START_MASK 0x10000u
emilmont	10:3bc89ef62ce7	648	#define DMA_DCR_START_SHIFT 16
emilmont	10:3bc89ef62ce7	649	#define DMA_DCR_DSIZE_MASK 0x60000u
emilmont	10:3bc89ef62ce7	650	#define DMA_DCR_DSIZE_SHIFT 17
emilmont	10:3bc89ef62ce7	651	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
emilmont	10:3bc89ef62ce7	652	#define DMA_DCR_DINC_MASK 0x80000u
emilmont	10:3bc89ef62ce7	653	#define DMA_DCR_DINC_SHIFT 19
emilmont	10:3bc89ef62ce7	654	#define DMA_DCR_SSIZE_MASK 0x300000u
emilmont	10:3bc89ef62ce7	655	#define DMA_DCR_SSIZE_SHIFT 20
emilmont	10:3bc89ef62ce7	656	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
emilmont	10:3bc89ef62ce7	657	#define DMA_DCR_SINC_MASK 0x400000u
emilmont	10:3bc89ef62ce7	658	#define DMA_DCR_SINC_SHIFT 22
emilmont	10:3bc89ef62ce7	659	#define DMA_DCR_EADREQ_MASK 0x800000u
emilmont	10:3bc89ef62ce7	660	#define DMA_DCR_EADREQ_SHIFT 23
emilmont	10:3bc89ef62ce7	661	#define DMA_DCR_AA_MASK 0x10000000u
emilmont	10:3bc89ef62ce7	662	#define DMA_DCR_AA_SHIFT 28
emilmont	10:3bc89ef62ce7	663	#define DMA_DCR_CS_MASK 0x20000000u
emilmont	10:3bc89ef62ce7	664	#define DMA_DCR_CS_SHIFT 29
emilmont	10:3bc89ef62ce7	665	#define DMA_DCR_ERQ_MASK 0x40000000u
emilmont	10:3bc89ef62ce7	666	#define DMA_DCR_ERQ_SHIFT 30
emilmont	10:3bc89ef62ce7	667	#define DMA_DCR_EINT_MASK 0x80000000u
emilmont	10:3bc89ef62ce7	668	#define DMA_DCR_EINT_SHIFT 31
emilmont	10:3bc89ef62ce7	669
emilmont	10:3bc89ef62ce7	670	/**
emilmont	10:3bc89ef62ce7	671	* @}
emilmont	10:3bc89ef62ce7	672	/ / end of group DMA_Register_Masks */
emilmont	10:3bc89ef62ce7	673
emilmont	10:3bc89ef62ce7	674
emilmont	10:3bc89ef62ce7	675	/* DMA - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	676	/** Peripheral DMA base address */
emilmont	10:3bc89ef62ce7	677	#define DMA_BASE (0x40008000u)
emilmont	10:3bc89ef62ce7	678	/** Peripheral DMA base pointer */
emilmont	10:3bc89ef62ce7	679	#define DMA0 ((DMA_Type *)DMA_BASE)
emilmont	10:3bc89ef62ce7	680	/** Array initializer of DMA peripheral base pointers */
emilmont	10:3bc89ef62ce7	681	#define DMA_BASES { DMA0 }
emilmont	10:3bc89ef62ce7	682
emilmont	10:3bc89ef62ce7	683	/**
emilmont	10:3bc89ef62ce7	684	* @}
emilmont	10:3bc89ef62ce7	685	/ / end of group DMA_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	686
emilmont	10:3bc89ef62ce7	687
emilmont	10:3bc89ef62ce7	688	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	689	-- DMAMUX Peripheral Access Layer
emilmont	10:3bc89ef62ce7	690	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	691
emilmont	10:3bc89ef62ce7	692	/**
emilmont	10:3bc89ef62ce7	693	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
emilmont	10:3bc89ef62ce7	694	* @{
emilmont	10:3bc89ef62ce7	695	*/
emilmont	10:3bc89ef62ce7	696
emilmont	10:3bc89ef62ce7	697	/** DMAMUX - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	698	typedef struct {
emilmont	10:3bc89ef62ce7	699	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
emilmont	10:3bc89ef62ce7	700	} DMAMUX_Type;
emilmont	10:3bc89ef62ce7	701
emilmont	10:3bc89ef62ce7	702	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	703	-- DMAMUX Register Masks
emilmont	10:3bc89ef62ce7	704	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	705
emilmont	10:3bc89ef62ce7	706	/**
emilmont	10:3bc89ef62ce7	707	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
emilmont	10:3bc89ef62ce7	708	* @{
emilmont	10:3bc89ef62ce7	709	*/
emilmont	10:3bc89ef62ce7	710
emilmont	10:3bc89ef62ce7	711	/* CHCFG Bit Fields */
emilmont	10:3bc89ef62ce7	712	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	713	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
emilmont	10:3bc89ef62ce7	714	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
emilmont	10:3bc89ef62ce7	715	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
emilmont	10:3bc89ef62ce7	716	#define DMAMUX_CHCFG_TRIG_SHIFT 6
emilmont	10:3bc89ef62ce7	717	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
emilmont	10:3bc89ef62ce7	718	#define DMAMUX_CHCFG_ENBL_SHIFT 7
emilmont	10:3bc89ef62ce7	719
emilmont	10:3bc89ef62ce7	720	/**
emilmont	10:3bc89ef62ce7	721	* @}
emilmont	10:3bc89ef62ce7	722	/ / end of group DMAMUX_Register_Masks */
emilmont	10:3bc89ef62ce7	723
emilmont	10:3bc89ef62ce7	724
emilmont	10:3bc89ef62ce7	725	/* DMAMUX - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	726	/** Peripheral DMAMUX0 base address */
emilmont	10:3bc89ef62ce7	727	#define DMAMUX0_BASE (0x40021000u)
emilmont	10:3bc89ef62ce7	728	/** Peripheral DMAMUX0 base pointer */
emilmont	10:3bc89ef62ce7	729	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
emilmont	10:3bc89ef62ce7	730	/** Array initializer of DMAMUX peripheral base pointers */
emilmont	10:3bc89ef62ce7	731	#define DMAMUX_BASES { DMAMUX0 }
emilmont	10:3bc89ef62ce7	732
emilmont	10:3bc89ef62ce7	733	/**
emilmont	10:3bc89ef62ce7	734	* @}
emilmont	10:3bc89ef62ce7	735	/ / end of group DMAMUX_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	736
emilmont	10:3bc89ef62ce7	737
emilmont	10:3bc89ef62ce7	738	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	739	-- FGPIO Peripheral Access Layer
emilmont	10:3bc89ef62ce7	740	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	741
emilmont	10:3bc89ef62ce7	742	/**
emilmont	10:3bc89ef62ce7	743	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
emilmont	10:3bc89ef62ce7	744	* @{
emilmont	10:3bc89ef62ce7	745	*/
emilmont	10:3bc89ef62ce7	746
emilmont	10:3bc89ef62ce7	747	/** FGPIO - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	748	typedef struct {
emilmont	10:3bc89ef62ce7	749	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	750	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	751	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	752	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	753	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	10:3bc89ef62ce7	754	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	10:3bc89ef62ce7	755	} FGPIO_Type;
emilmont	10:3bc89ef62ce7	756
emilmont	10:3bc89ef62ce7	757	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	758	-- FGPIO Register Masks
emilmont	10:3bc89ef62ce7	759	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	760
emilmont	10:3bc89ef62ce7	761	/**
emilmont	10:3bc89ef62ce7	762	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
emilmont	10:3bc89ef62ce7	763	* @{
emilmont	10:3bc89ef62ce7	764	*/
emilmont	10:3bc89ef62ce7	765
emilmont	10:3bc89ef62ce7	766	/* PDOR Bit Fields */
emilmont	10:3bc89ef62ce7	767	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	768	#define FGPIO_PDOR_PDO_SHIFT 0
emilmont	10:3bc89ef62ce7	769	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
emilmont	10:3bc89ef62ce7	770	/* PSOR Bit Fields */
emilmont	10:3bc89ef62ce7	771	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	772	#define FGPIO_PSOR_PTSO_SHIFT 0
emilmont	10:3bc89ef62ce7	773	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
emilmont	10:3bc89ef62ce7	774	/* PCOR Bit Fields */
emilmont	10:3bc89ef62ce7	775	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	776	#define FGPIO_PCOR_PTCO_SHIFT 0
emilmont	10:3bc89ef62ce7	777	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
emilmont	10:3bc89ef62ce7	778	/* PTOR Bit Fields */
emilmont	10:3bc89ef62ce7	779	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	780	#define FGPIO_PTOR_PTTO_SHIFT 0
emilmont	10:3bc89ef62ce7	781	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
emilmont	10:3bc89ef62ce7	782	/* PDIR Bit Fields */
emilmont	10:3bc89ef62ce7	783	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	784	#define FGPIO_PDIR_PDI_SHIFT 0
emilmont	10:3bc89ef62ce7	785	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
emilmont	10:3bc89ef62ce7	786	/* PDDR Bit Fields */
emilmont	10:3bc89ef62ce7	787	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	788	#define FGPIO_PDDR_PDD_SHIFT 0
emilmont	10:3bc89ef62ce7	789	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
emilmont	10:3bc89ef62ce7	790
emilmont	10:3bc89ef62ce7	791	/**
emilmont	10:3bc89ef62ce7	792	* @}
emilmont	10:3bc89ef62ce7	793	/ / end of group FGPIO_Register_Masks */
emilmont	10:3bc89ef62ce7	794
emilmont	10:3bc89ef62ce7	795
emilmont	10:3bc89ef62ce7	796	/* FGPIO - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	797	/** Peripheral FPTA base address */
emilmont	10:3bc89ef62ce7	798	#define FPTA_BASE (0xF80FF000u)
emilmont	10:3bc89ef62ce7	799	/** Peripheral FPTA base pointer */
emilmont	10:3bc89ef62ce7	800	#define FPTA ((FGPIO_Type *)FPTA_BASE)
emilmont	10:3bc89ef62ce7	801	/** Peripheral FPTB base address */
emilmont	10:3bc89ef62ce7	802	#define FPTB_BASE (0xF80FF040u)
emilmont	10:3bc89ef62ce7	803	/** Peripheral FPTB base pointer */
emilmont	10:3bc89ef62ce7	804	#define FPTB ((FGPIO_Type *)FPTB_BASE)
emilmont	10:3bc89ef62ce7	805	/** Peripheral FPTC base address */
emilmont	10:3bc89ef62ce7	806	#define FPTC_BASE (0xF80FF080u)
emilmont	10:3bc89ef62ce7	807	/** Peripheral FPTC base pointer */
emilmont	10:3bc89ef62ce7	808	#define FPTC ((FGPIO_Type *)FPTC_BASE)
emilmont	10:3bc89ef62ce7	809	/** Peripheral FPTD base address */
emilmont	10:3bc89ef62ce7	810	#define FPTD_BASE (0xF80FF0C0u)
emilmont	10:3bc89ef62ce7	811	/** Peripheral FPTD base pointer */
emilmont	10:3bc89ef62ce7	812	#define FPTD ((FGPIO_Type *)FPTD_BASE)
emilmont	10:3bc89ef62ce7	813	/** Peripheral FPTE base address */
emilmont	10:3bc89ef62ce7	814	#define FPTE_BASE (0xF80FF100u)
emilmont	10:3bc89ef62ce7	815	/** Peripheral FPTE base pointer */
emilmont	10:3bc89ef62ce7	816	#define FPTE ((FGPIO_Type *)FPTE_BASE)
emilmont	10:3bc89ef62ce7	817	/** Array initializer of FGPIO peripheral base pointers */
emilmont	10:3bc89ef62ce7	818	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
emilmont	10:3bc89ef62ce7	819
emilmont	10:3bc89ef62ce7	820	/**
emilmont	10:3bc89ef62ce7	821	* @}
emilmont	10:3bc89ef62ce7	822	/ / end of group FGPIO_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	823
emilmont	10:3bc89ef62ce7	824
emilmont	10:3bc89ef62ce7	825	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	826	-- FTFA Peripheral Access Layer
emilmont	10:3bc89ef62ce7	827	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	828
emilmont	10:3bc89ef62ce7	829	/**
emilmont	10:3bc89ef62ce7	830	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
emilmont	10:3bc89ef62ce7	831	* @{
emilmont	10:3bc89ef62ce7	832	*/
emilmont	10:3bc89ef62ce7	833
emilmont	10:3bc89ef62ce7	834	/** FTFA - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	835	typedef struct {
emilmont	10:3bc89ef62ce7	836	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	837	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	838	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	839	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	840	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
emilmont	10:3bc89ef62ce7	841	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
emilmont	10:3bc89ef62ce7	842	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
emilmont	10:3bc89ef62ce7	843	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
emilmont	10:3bc89ef62ce7	844	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
emilmont	10:3bc89ef62ce7	845	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
emilmont	10:3bc89ef62ce7	846	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
emilmont	10:3bc89ef62ce7	847	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
emilmont	10:3bc89ef62ce7	848	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
emilmont	10:3bc89ef62ce7	849	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
emilmont	10:3bc89ef62ce7	850	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
emilmont	10:3bc89ef62ce7	851	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
emilmont	10:3bc89ef62ce7	852	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
emilmont	10:3bc89ef62ce7	853	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
emilmont	10:3bc89ef62ce7	854	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
emilmont	10:3bc89ef62ce7	855	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
emilmont	10:3bc89ef62ce7	856	} FTFA_Type;
emilmont	10:3bc89ef62ce7	857
emilmont	10:3bc89ef62ce7	858	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	859	-- FTFA Register Masks
emilmont	10:3bc89ef62ce7	860	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	861
emilmont	10:3bc89ef62ce7	862	/**
emilmont	10:3bc89ef62ce7	863	* @addtogroup FTFA_Register_Masks FTFA Register Masks
emilmont	10:3bc89ef62ce7	864	* @{
emilmont	10:3bc89ef62ce7	865	*/
emilmont	10:3bc89ef62ce7	866
emilmont	10:3bc89ef62ce7	867	/* FSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	868	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
emilmont	10:3bc89ef62ce7	869	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
emilmont	10:3bc89ef62ce7	870	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
emilmont	10:3bc89ef62ce7	871	#define FTFA_FSTAT_FPVIOL_SHIFT 4
emilmont	10:3bc89ef62ce7	872	#define FTFA_FSTAT_ACCERR_MASK 0x20u
emilmont	10:3bc89ef62ce7	873	#define FTFA_FSTAT_ACCERR_SHIFT 5
emilmont	10:3bc89ef62ce7	874	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
emilmont	10:3bc89ef62ce7	875	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
emilmont	10:3bc89ef62ce7	876	#define FTFA_FSTAT_CCIF_MASK 0x80u
emilmont	10:3bc89ef62ce7	877	#define FTFA_FSTAT_CCIF_SHIFT 7
emilmont	10:3bc89ef62ce7	878	/* FCNFG Bit Fields */
emilmont	10:3bc89ef62ce7	879	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
emilmont	10:3bc89ef62ce7	880	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
emilmont	10:3bc89ef62ce7	881	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
emilmont	10:3bc89ef62ce7	882	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
emilmont	10:3bc89ef62ce7	883	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	884	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
emilmont	10:3bc89ef62ce7	885	#define FTFA_FCNFG_CCIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	886	#define FTFA_FCNFG_CCIE_SHIFT 7
emilmont	10:3bc89ef62ce7	887	/* FSEC Bit Fields */
emilmont	10:3bc89ef62ce7	888	#define FTFA_FSEC_SEC_MASK 0x3u
emilmont	10:3bc89ef62ce7	889	#define FTFA_FSEC_SEC_SHIFT 0
emilmont	10:3bc89ef62ce7	890	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
emilmont	10:3bc89ef62ce7	891	#define FTFA_FSEC_FSLACC_MASK 0xCu
emilmont	10:3bc89ef62ce7	892	#define FTFA_FSEC_FSLACC_SHIFT 2
emilmont	10:3bc89ef62ce7	893	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
emilmont	10:3bc89ef62ce7	894	#define FTFA_FSEC_MEEN_MASK 0x30u
emilmont	10:3bc89ef62ce7	895	#define FTFA_FSEC_MEEN_SHIFT 4
emilmont	10:3bc89ef62ce7	896	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
emilmont	10:3bc89ef62ce7	897	#define FTFA_FSEC_KEYEN_MASK 0xC0u
emilmont	10:3bc89ef62ce7	898	#define FTFA_FSEC_KEYEN_SHIFT 6
emilmont	10:3bc89ef62ce7	899	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
emilmont	10:3bc89ef62ce7	900	/* FOPT Bit Fields */
emilmont	10:3bc89ef62ce7	901	#define FTFA_FOPT_OPT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	902	#define FTFA_FOPT_OPT_SHIFT 0
emilmont	10:3bc89ef62ce7	903	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
emilmont	10:3bc89ef62ce7	904	/* FCCOB3 Bit Fields */
emilmont	10:3bc89ef62ce7	905	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	906	#define FTFA_FCCOB3_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	907	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	908	/* FCCOB2 Bit Fields */
emilmont	10:3bc89ef62ce7	909	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	910	#define FTFA_FCCOB2_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	911	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	912	/* FCCOB1 Bit Fields */
emilmont	10:3bc89ef62ce7	913	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	914	#define FTFA_FCCOB1_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	915	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	916	/* FCCOB0 Bit Fields */
emilmont	10:3bc89ef62ce7	917	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	918	#define FTFA_FCCOB0_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	919	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	920	/* FCCOB7 Bit Fields */
emilmont	10:3bc89ef62ce7	921	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	922	#define FTFA_FCCOB7_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	923	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	924	/* FCCOB6 Bit Fields */
emilmont	10:3bc89ef62ce7	925	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	926	#define FTFA_FCCOB6_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	927	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	928	/* FCCOB5 Bit Fields */
emilmont	10:3bc89ef62ce7	929	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	930	#define FTFA_FCCOB5_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	931	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	932	/* FCCOB4 Bit Fields */
emilmont	10:3bc89ef62ce7	933	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	934	#define FTFA_FCCOB4_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	935	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	936	/* FCCOBB Bit Fields */
emilmont	10:3bc89ef62ce7	937	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	938	#define FTFA_FCCOBB_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	939	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	940	/* FCCOBA Bit Fields */
emilmont	10:3bc89ef62ce7	941	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	942	#define FTFA_FCCOBA_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	943	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	944	/* FCCOB9 Bit Fields */
emilmont	10:3bc89ef62ce7	945	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	946	#define FTFA_FCCOB9_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	947	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	948	/* FCCOB8 Bit Fields */
emilmont	10:3bc89ef62ce7	949	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
emilmont	10:3bc89ef62ce7	950	#define FTFA_FCCOB8_CCOBn_SHIFT 0
emilmont	10:3bc89ef62ce7	951	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
emilmont	10:3bc89ef62ce7	952	/* FPROT3 Bit Fields */
emilmont	10:3bc89ef62ce7	953	#define FTFA_FPROT3_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	954	#define FTFA_FPROT3_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	955	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
emilmont	10:3bc89ef62ce7	956	/* FPROT2 Bit Fields */
emilmont	10:3bc89ef62ce7	957	#define FTFA_FPROT2_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	958	#define FTFA_FPROT2_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	959	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
emilmont	10:3bc89ef62ce7	960	/* FPROT1 Bit Fields */
emilmont	10:3bc89ef62ce7	961	#define FTFA_FPROT1_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	962	#define FTFA_FPROT1_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	963	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
emilmont	10:3bc89ef62ce7	964	/* FPROT0 Bit Fields */
emilmont	10:3bc89ef62ce7	965	#define FTFA_FPROT0_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	966	#define FTFA_FPROT0_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	967	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
emilmont	10:3bc89ef62ce7	968
emilmont	10:3bc89ef62ce7	969	/**
emilmont	10:3bc89ef62ce7	970	* @}
emilmont	10:3bc89ef62ce7	971	/ / end of group FTFA_Register_Masks */
emilmont	10:3bc89ef62ce7	972
emilmont	10:3bc89ef62ce7	973
emilmont	10:3bc89ef62ce7	974	/* FTFA - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	975	/** Peripheral FTFA base address */
emilmont	10:3bc89ef62ce7	976	#define FTFA_BASE (0x40020000u)
emilmont	10:3bc89ef62ce7	977	/** Peripheral FTFA base pointer */
emilmont	10:3bc89ef62ce7	978	#define FTFA ((FTFA_Type *)FTFA_BASE)
emilmont	10:3bc89ef62ce7	979	/** Array initializer of FTFA peripheral base pointers */
emilmont	10:3bc89ef62ce7	980	#define FTFA_BASES { FTFA }
emilmont	10:3bc89ef62ce7	981
emilmont	10:3bc89ef62ce7	982	/**
emilmont	10:3bc89ef62ce7	983	* @}
emilmont	10:3bc89ef62ce7	984	/ / end of group FTFA_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	985
emilmont	10:3bc89ef62ce7	986
emilmont	10:3bc89ef62ce7	987	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	988	-- GPIO Peripheral Access Layer
emilmont	10:3bc89ef62ce7	989	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	990
emilmont	10:3bc89ef62ce7	991	/**
emilmont	10:3bc89ef62ce7	992	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
emilmont	10:3bc89ef62ce7	993	* @{
emilmont	10:3bc89ef62ce7	994	*/
emilmont	10:3bc89ef62ce7	995
emilmont	10:3bc89ef62ce7	996	/** GPIO - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	997	typedef struct {
emilmont	10:3bc89ef62ce7	998	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	999	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1000	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1001	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	1002	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	10:3bc89ef62ce7	1003	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	10:3bc89ef62ce7	1004	} GPIO_Type;
emilmont	10:3bc89ef62ce7	1005
emilmont	10:3bc89ef62ce7	1006	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1007	-- GPIO Register Masks
emilmont	10:3bc89ef62ce7	1008	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1009
emilmont	10:3bc89ef62ce7	1010	/**
emilmont	10:3bc89ef62ce7	1011	* @addtogroup GPIO_Register_Masks GPIO Register Masks
emilmont	10:3bc89ef62ce7	1012	* @{
emilmont	10:3bc89ef62ce7	1013	*/
emilmont	10:3bc89ef62ce7	1014
emilmont	10:3bc89ef62ce7	1015	/* PDOR Bit Fields */
emilmont	10:3bc89ef62ce7	1016	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1017	#define GPIO_PDOR_PDO_SHIFT 0
emilmont	10:3bc89ef62ce7	1018	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
emilmont	10:3bc89ef62ce7	1019	/* PSOR Bit Fields */
emilmont	10:3bc89ef62ce7	1020	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1021	#define GPIO_PSOR_PTSO_SHIFT 0
emilmont	10:3bc89ef62ce7	1022	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
emilmont	10:3bc89ef62ce7	1023	/* PCOR Bit Fields */
emilmont	10:3bc89ef62ce7	1024	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1025	#define GPIO_PCOR_PTCO_SHIFT 0
emilmont	10:3bc89ef62ce7	1026	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
emilmont	10:3bc89ef62ce7	1027	/* PTOR Bit Fields */
emilmont	10:3bc89ef62ce7	1028	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1029	#define GPIO_PTOR_PTTO_SHIFT 0
emilmont	10:3bc89ef62ce7	1030	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
emilmont	10:3bc89ef62ce7	1031	/* PDIR Bit Fields */
emilmont	10:3bc89ef62ce7	1032	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1033	#define GPIO_PDIR_PDI_SHIFT 0
emilmont	10:3bc89ef62ce7	1034	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
emilmont	10:3bc89ef62ce7	1035	/* PDDR Bit Fields */
emilmont	10:3bc89ef62ce7	1036	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1037	#define GPIO_PDDR_PDD_SHIFT 0
emilmont	10:3bc89ef62ce7	1038	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
emilmont	10:3bc89ef62ce7	1039
emilmont	10:3bc89ef62ce7	1040	/**
emilmont	10:3bc89ef62ce7	1041	* @}
emilmont	10:3bc89ef62ce7	1042	/ / end of group GPIO_Register_Masks */
emilmont	10:3bc89ef62ce7	1043
emilmont	10:3bc89ef62ce7	1044
emilmont	10:3bc89ef62ce7	1045	/* GPIO - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1046	/** Peripheral PTA base address */
emilmont	10:3bc89ef62ce7	1047	#define PTA_BASE (0x400FF000u)
emilmont	10:3bc89ef62ce7	1048	/** Peripheral PTA base pointer */
emilmont	10:3bc89ef62ce7	1049	#define PTA ((GPIO_Type *)PTA_BASE)
emilmont	10:3bc89ef62ce7	1050	/** Peripheral PTB base address */
emilmont	10:3bc89ef62ce7	1051	#define PTB_BASE (0x400FF040u)
emilmont	10:3bc89ef62ce7	1052	/** Peripheral PTB base pointer */
emilmont	10:3bc89ef62ce7	1053	#define PTB ((GPIO_Type *)PTB_BASE)
emilmont	10:3bc89ef62ce7	1054	/** Peripheral PTC base address */
emilmont	10:3bc89ef62ce7	1055	#define PTC_BASE (0x400FF080u)
emilmont	10:3bc89ef62ce7	1056	/** Peripheral PTC base pointer */
emilmont	10:3bc89ef62ce7	1057	#define PTC ((GPIO_Type *)PTC_BASE)
emilmont	10:3bc89ef62ce7	1058	/** Peripheral PTD base address */
emilmont	10:3bc89ef62ce7	1059	#define PTD_BASE (0x400FF0C0u)
emilmont	10:3bc89ef62ce7	1060	/** Peripheral PTD base pointer */
emilmont	10:3bc89ef62ce7	1061	#define PTD ((GPIO_Type *)PTD_BASE)
emilmont	10:3bc89ef62ce7	1062	/** Peripheral PTE base address */
emilmont	10:3bc89ef62ce7	1063	#define PTE_BASE (0x400FF100u)
emilmont	10:3bc89ef62ce7	1064	/** Peripheral PTE base pointer */
emilmont	10:3bc89ef62ce7	1065	#define PTE ((GPIO_Type *)PTE_BASE)
emilmont	10:3bc89ef62ce7	1066	/** Array initializer of GPIO peripheral base pointers */
emilmont	10:3bc89ef62ce7	1067	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
emilmont	10:3bc89ef62ce7	1068
emilmont	10:3bc89ef62ce7	1069	/**
emilmont	10:3bc89ef62ce7	1070	* @}
emilmont	10:3bc89ef62ce7	1071	/ / end of group GPIO_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1072
emilmont	10:3bc89ef62ce7	1073
emilmont	10:3bc89ef62ce7	1074	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1075	-- I2C Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1076	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1077
emilmont	10:3bc89ef62ce7	1078	/**
emilmont	10:3bc89ef62ce7	1079	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1080	* @{
emilmont	10:3bc89ef62ce7	1081	*/
emilmont	10:3bc89ef62ce7	1082
emilmont	10:3bc89ef62ce7	1083	/** I2C - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1084	typedef struct {
emilmont	10:3bc89ef62ce7	1085	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1086	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	1087	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
emilmont	10:3bc89ef62ce7	1088	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	1089	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1090	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
emilmont	10:3bc89ef62ce7	1091	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
emilmont	10:3bc89ef62ce7	1092	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
emilmont	10:3bc89ef62ce7	1093	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1094	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
emilmont	10:3bc89ef62ce7	1095	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
emilmont	10:3bc89ef62ce7	1096	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
emilmont	10:3bc89ef62ce7	1097	} I2C_Type;
emilmont	10:3bc89ef62ce7	1098
emilmont	10:3bc89ef62ce7	1099	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1100	-- I2C Register Masks
emilmont	10:3bc89ef62ce7	1101	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1102
emilmont	10:3bc89ef62ce7	1103	/**
emilmont	10:3bc89ef62ce7	1104	* @addtogroup I2C_Register_Masks I2C Register Masks
emilmont	10:3bc89ef62ce7	1105	* @{
emilmont	10:3bc89ef62ce7	1106	*/
emilmont	10:3bc89ef62ce7	1107
emilmont	10:3bc89ef62ce7	1108	/* A1 Bit Fields */
emilmont	10:3bc89ef62ce7	1109	#define I2C_A1_AD_MASK 0xFEu
emilmont	10:3bc89ef62ce7	1110	#define I2C_A1_AD_SHIFT 1
emilmont	10:3bc89ef62ce7	1111	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
emilmont	10:3bc89ef62ce7	1112	/* F Bit Fields */
emilmont	10:3bc89ef62ce7	1113	#define I2C_F_ICR_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	1114	#define I2C_F_ICR_SHIFT 0
emilmont	10:3bc89ef62ce7	1115	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
emilmont	10:3bc89ef62ce7	1116	#define I2C_F_MULT_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1117	#define I2C_F_MULT_SHIFT 6
emilmont	10:3bc89ef62ce7	1118	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
emilmont	10:3bc89ef62ce7	1119	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	1120	#define I2C_C1_DMAEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	1121	#define I2C_C1_DMAEN_SHIFT 0
emilmont	10:3bc89ef62ce7	1122	#define I2C_C1_WUEN_MASK 0x2u
emilmont	10:3bc89ef62ce7	1123	#define I2C_C1_WUEN_SHIFT 1
emilmont	10:3bc89ef62ce7	1124	#define I2C_C1_RSTA_MASK 0x4u
emilmont	10:3bc89ef62ce7	1125	#define I2C_C1_RSTA_SHIFT 2
emilmont	10:3bc89ef62ce7	1126	#define I2C_C1_TXAK_MASK 0x8u
emilmont	10:3bc89ef62ce7	1127	#define I2C_C1_TXAK_SHIFT 3
emilmont	10:3bc89ef62ce7	1128	#define I2C_C1_TX_MASK 0x10u
emilmont	10:3bc89ef62ce7	1129	#define I2C_C1_TX_SHIFT 4
emilmont	10:3bc89ef62ce7	1130	#define I2C_C1_MST_MASK 0x20u
emilmont	10:3bc89ef62ce7	1131	#define I2C_C1_MST_SHIFT 5
emilmont	10:3bc89ef62ce7	1132	#define I2C_C1_IICIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	1133	#define I2C_C1_IICIE_SHIFT 6
emilmont	10:3bc89ef62ce7	1134	#define I2C_C1_IICEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	1135	#define I2C_C1_IICEN_SHIFT 7
emilmont	10:3bc89ef62ce7	1136	/* S Bit Fields */
emilmont	10:3bc89ef62ce7	1137	#define I2C_S_RXAK_MASK 0x1u
emilmont	10:3bc89ef62ce7	1138	#define I2C_S_RXAK_SHIFT 0
emilmont	10:3bc89ef62ce7	1139	#define I2C_S_IICIF_MASK 0x2u
emilmont	10:3bc89ef62ce7	1140	#define I2C_S_IICIF_SHIFT 1
emilmont	10:3bc89ef62ce7	1141	#define I2C_S_SRW_MASK 0x4u
emilmont	10:3bc89ef62ce7	1142	#define I2C_S_SRW_SHIFT 2
emilmont	10:3bc89ef62ce7	1143	#define I2C_S_RAM_MASK 0x8u
emilmont	10:3bc89ef62ce7	1144	#define I2C_S_RAM_SHIFT 3
emilmont	10:3bc89ef62ce7	1145	#define I2C_S_ARBL_MASK 0x10u
emilmont	10:3bc89ef62ce7	1146	#define I2C_S_ARBL_SHIFT 4
emilmont	10:3bc89ef62ce7	1147	#define I2C_S_BUSY_MASK 0x20u
emilmont	10:3bc89ef62ce7	1148	#define I2C_S_BUSY_SHIFT 5
emilmont	10:3bc89ef62ce7	1149	#define I2C_S_IAAS_MASK 0x40u
emilmont	10:3bc89ef62ce7	1150	#define I2C_S_IAAS_SHIFT 6
emilmont	10:3bc89ef62ce7	1151	#define I2C_S_TCF_MASK 0x80u
emilmont	10:3bc89ef62ce7	1152	#define I2C_S_TCF_SHIFT 7
emilmont	10:3bc89ef62ce7	1153	/* D Bit Fields */
emilmont	10:3bc89ef62ce7	1154	#define I2C_D_DATA_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1155	#define I2C_D_DATA_SHIFT 0
emilmont	10:3bc89ef62ce7	1156	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
emilmont	10:3bc89ef62ce7	1157	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	1158	#define I2C_C2_AD_MASK 0x7u
emilmont	10:3bc89ef62ce7	1159	#define I2C_C2_AD_SHIFT 0
emilmont	10:3bc89ef62ce7	1160	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
emilmont	10:3bc89ef62ce7	1161	#define I2C_C2_RMEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	1162	#define I2C_C2_RMEN_SHIFT 3
emilmont	10:3bc89ef62ce7	1163	#define I2C_C2_SBRC_MASK 0x10u
emilmont	10:3bc89ef62ce7	1164	#define I2C_C2_SBRC_SHIFT 4
emilmont	10:3bc89ef62ce7	1165	#define I2C_C2_HDRS_MASK 0x20u
emilmont	10:3bc89ef62ce7	1166	#define I2C_C2_HDRS_SHIFT 5
emilmont	10:3bc89ef62ce7	1167	#define I2C_C2_ADEXT_MASK 0x40u
emilmont	10:3bc89ef62ce7	1168	#define I2C_C2_ADEXT_SHIFT 6
emilmont	10:3bc89ef62ce7	1169	#define I2C_C2_GCAEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	1170	#define I2C_C2_GCAEN_SHIFT 7
emilmont	10:3bc89ef62ce7	1171	/* FLT Bit Fields */
emilmont	10:3bc89ef62ce7	1172	#define I2C_FLT_FLT_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	1173	#define I2C_FLT_FLT_SHIFT 0
emilmont	10:3bc89ef62ce7	1174	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
emilmont	10:3bc89ef62ce7	1175	#define I2C_FLT_STOPIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	1176	#define I2C_FLT_STOPIE_SHIFT 5
emilmont	10:3bc89ef62ce7	1177	#define I2C_FLT_STOPF_MASK 0x40u
emilmont	10:3bc89ef62ce7	1178	#define I2C_FLT_STOPF_SHIFT 6
emilmont	10:3bc89ef62ce7	1179	#define I2C_FLT_SHEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	1180	#define I2C_FLT_SHEN_SHIFT 7
emilmont	10:3bc89ef62ce7	1181	/* RA Bit Fields */
emilmont	10:3bc89ef62ce7	1182	#define I2C_RA_RAD_MASK 0xFEu
emilmont	10:3bc89ef62ce7	1183	#define I2C_RA_RAD_SHIFT 1
emilmont	10:3bc89ef62ce7	1184	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
emilmont	10:3bc89ef62ce7	1185	/* SMB Bit Fields */
emilmont	10:3bc89ef62ce7	1186	#define I2C_SMB_SHTF2IE_MASK 0x1u
emilmont	10:3bc89ef62ce7	1187	#define I2C_SMB_SHTF2IE_SHIFT 0
emilmont	10:3bc89ef62ce7	1188	#define I2C_SMB_SHTF2_MASK 0x2u
emilmont	10:3bc89ef62ce7	1189	#define I2C_SMB_SHTF2_SHIFT 1
emilmont	10:3bc89ef62ce7	1190	#define I2C_SMB_SHTF1_MASK 0x4u
emilmont	10:3bc89ef62ce7	1191	#define I2C_SMB_SHTF1_SHIFT 2
emilmont	10:3bc89ef62ce7	1192	#define I2C_SMB_SLTF_MASK 0x8u
emilmont	10:3bc89ef62ce7	1193	#define I2C_SMB_SLTF_SHIFT 3
emilmont	10:3bc89ef62ce7	1194	#define I2C_SMB_TCKSEL_MASK 0x10u
emilmont	10:3bc89ef62ce7	1195	#define I2C_SMB_TCKSEL_SHIFT 4
emilmont	10:3bc89ef62ce7	1196	#define I2C_SMB_SIICAEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	1197	#define I2C_SMB_SIICAEN_SHIFT 5
emilmont	10:3bc89ef62ce7	1198	#define I2C_SMB_ALERTEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	1199	#define I2C_SMB_ALERTEN_SHIFT 6
emilmont	10:3bc89ef62ce7	1200	#define I2C_SMB_FACK_MASK 0x80u
emilmont	10:3bc89ef62ce7	1201	#define I2C_SMB_FACK_SHIFT 7
emilmont	10:3bc89ef62ce7	1202	/* A2 Bit Fields */
emilmont	10:3bc89ef62ce7	1203	#define I2C_A2_SAD_MASK 0xFEu
emilmont	10:3bc89ef62ce7	1204	#define I2C_A2_SAD_SHIFT 1
emilmont	10:3bc89ef62ce7	1205	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
emilmont	10:3bc89ef62ce7	1206	/* SLTH Bit Fields */
emilmont	10:3bc89ef62ce7	1207	#define I2C_SLTH_SSLT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1208	#define I2C_SLTH_SSLT_SHIFT 0
emilmont	10:3bc89ef62ce7	1209	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
emilmont	10:3bc89ef62ce7	1210	/* SLTL Bit Fields */
emilmont	10:3bc89ef62ce7	1211	#define I2C_SLTL_SSLT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1212	#define I2C_SLTL_SSLT_SHIFT 0
emilmont	10:3bc89ef62ce7	1213	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
emilmont	10:3bc89ef62ce7	1214
emilmont	10:3bc89ef62ce7	1215	/**
emilmont	10:3bc89ef62ce7	1216	* @}
emilmont	10:3bc89ef62ce7	1217	/ / end of group I2C_Register_Masks */
emilmont	10:3bc89ef62ce7	1218
emilmont	10:3bc89ef62ce7	1219
emilmont	10:3bc89ef62ce7	1220	/* I2C - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1221	/** Peripheral I2C0 base address */
emilmont	10:3bc89ef62ce7	1222	#define I2C0_BASE (0x40066000u)
emilmont	10:3bc89ef62ce7	1223	/** Peripheral I2C0 base pointer */
emilmont	10:3bc89ef62ce7	1224	#define I2C0 ((I2C_Type *)I2C0_BASE)
emilmont	10:3bc89ef62ce7	1225	/** Peripheral I2C1 base address */
emilmont	10:3bc89ef62ce7	1226	#define I2C1_BASE (0x40067000u)
emilmont	10:3bc89ef62ce7	1227	/** Peripheral I2C1 base pointer */
emilmont	10:3bc89ef62ce7	1228	#define I2C1 ((I2C_Type *)I2C1_BASE)
emilmont	10:3bc89ef62ce7	1229	/** Array initializer of I2C peripheral base pointers */
emilmont	10:3bc89ef62ce7	1230	#define I2C_BASES { I2C0, I2C1 }
emilmont	10:3bc89ef62ce7	1231
emilmont	10:3bc89ef62ce7	1232	/**
emilmont	10:3bc89ef62ce7	1233	* @}
emilmont	10:3bc89ef62ce7	1234	/ / end of group I2C_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1235
emilmont	10:3bc89ef62ce7	1236
emilmont	10:3bc89ef62ce7	1237	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1238	-- LLWU Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1239	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1240
emilmont	10:3bc89ef62ce7	1241	/**
emilmont	10:3bc89ef62ce7	1242	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1243	* @{
emilmont	10:3bc89ef62ce7	1244	*/
emilmont	10:3bc89ef62ce7	1245
emilmont	10:3bc89ef62ce7	1246	/** LLWU - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1247	typedef struct {
emilmont	10:3bc89ef62ce7	1248	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1249	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	1250	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	1251	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	1252	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1253	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
emilmont	10:3bc89ef62ce7	1254	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
emilmont	10:3bc89ef62ce7	1255	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
emilmont	10:3bc89ef62ce7	1256	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1257	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
emilmont	10:3bc89ef62ce7	1258	} LLWU_Type;
emilmont	10:3bc89ef62ce7	1259
emilmont	10:3bc89ef62ce7	1260	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1261	-- LLWU Register Masks
emilmont	10:3bc89ef62ce7	1262	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1263
emilmont	10:3bc89ef62ce7	1264	/**
emilmont	10:3bc89ef62ce7	1265	* @addtogroup LLWU_Register_Masks LLWU Register Masks
emilmont	10:3bc89ef62ce7	1266	* @{
emilmont	10:3bc89ef62ce7	1267	*/
emilmont	10:3bc89ef62ce7	1268
emilmont	10:3bc89ef62ce7	1269	/* PE1 Bit Fields */
emilmont	10:3bc89ef62ce7	1270	#define LLWU_PE1_WUPE0_MASK 0x3u
emilmont	10:3bc89ef62ce7	1271	#define LLWU_PE1_WUPE0_SHIFT 0
emilmont	10:3bc89ef62ce7	1272	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
emilmont	10:3bc89ef62ce7	1273	#define LLWU_PE1_WUPE1_MASK 0xCu
emilmont	10:3bc89ef62ce7	1274	#define LLWU_PE1_WUPE1_SHIFT 2
emilmont	10:3bc89ef62ce7	1275	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
emilmont	10:3bc89ef62ce7	1276	#define LLWU_PE1_WUPE2_MASK 0x30u
emilmont	10:3bc89ef62ce7	1277	#define LLWU_PE1_WUPE2_SHIFT 4
emilmont	10:3bc89ef62ce7	1278	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
emilmont	10:3bc89ef62ce7	1279	#define LLWU_PE1_WUPE3_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1280	#define LLWU_PE1_WUPE3_SHIFT 6
emilmont	10:3bc89ef62ce7	1281	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
emilmont	10:3bc89ef62ce7	1282	/* PE2 Bit Fields */
emilmont	10:3bc89ef62ce7	1283	#define LLWU_PE2_WUPE4_MASK 0x3u
emilmont	10:3bc89ef62ce7	1284	#define LLWU_PE2_WUPE4_SHIFT 0
emilmont	10:3bc89ef62ce7	1285	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
emilmont	10:3bc89ef62ce7	1286	#define LLWU_PE2_WUPE5_MASK 0xCu
emilmont	10:3bc89ef62ce7	1287	#define LLWU_PE2_WUPE5_SHIFT 2
emilmont	10:3bc89ef62ce7	1288	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
emilmont	10:3bc89ef62ce7	1289	#define LLWU_PE2_WUPE6_MASK 0x30u
emilmont	10:3bc89ef62ce7	1290	#define LLWU_PE2_WUPE6_SHIFT 4
emilmont	10:3bc89ef62ce7	1291	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
emilmont	10:3bc89ef62ce7	1292	#define LLWU_PE2_WUPE7_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1293	#define LLWU_PE2_WUPE7_SHIFT 6
emilmont	10:3bc89ef62ce7	1294	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
emilmont	10:3bc89ef62ce7	1295	/* PE3 Bit Fields */
emilmont	10:3bc89ef62ce7	1296	#define LLWU_PE3_WUPE8_MASK 0x3u
emilmont	10:3bc89ef62ce7	1297	#define LLWU_PE3_WUPE8_SHIFT 0
emilmont	10:3bc89ef62ce7	1298	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
emilmont	10:3bc89ef62ce7	1299	#define LLWU_PE3_WUPE9_MASK 0xCu
emilmont	10:3bc89ef62ce7	1300	#define LLWU_PE3_WUPE9_SHIFT 2
emilmont	10:3bc89ef62ce7	1301	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
emilmont	10:3bc89ef62ce7	1302	#define LLWU_PE3_WUPE10_MASK 0x30u
emilmont	10:3bc89ef62ce7	1303	#define LLWU_PE3_WUPE10_SHIFT 4
emilmont	10:3bc89ef62ce7	1304	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
emilmont	10:3bc89ef62ce7	1305	#define LLWU_PE3_WUPE11_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1306	#define LLWU_PE3_WUPE11_SHIFT 6
emilmont	10:3bc89ef62ce7	1307	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
emilmont	10:3bc89ef62ce7	1308	/* PE4 Bit Fields */
emilmont	10:3bc89ef62ce7	1309	#define LLWU_PE4_WUPE12_MASK 0x3u
emilmont	10:3bc89ef62ce7	1310	#define LLWU_PE4_WUPE12_SHIFT 0
emilmont	10:3bc89ef62ce7	1311	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
emilmont	10:3bc89ef62ce7	1312	#define LLWU_PE4_WUPE13_MASK 0xCu
emilmont	10:3bc89ef62ce7	1313	#define LLWU_PE4_WUPE13_SHIFT 2
emilmont	10:3bc89ef62ce7	1314	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
emilmont	10:3bc89ef62ce7	1315	#define LLWU_PE4_WUPE14_MASK 0x30u
emilmont	10:3bc89ef62ce7	1316	#define LLWU_PE4_WUPE14_SHIFT 4
emilmont	10:3bc89ef62ce7	1317	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
emilmont	10:3bc89ef62ce7	1318	#define LLWU_PE4_WUPE15_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1319	#define LLWU_PE4_WUPE15_SHIFT 6
emilmont	10:3bc89ef62ce7	1320	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
emilmont	10:3bc89ef62ce7	1321	/* ME Bit Fields */
emilmont	10:3bc89ef62ce7	1322	#define LLWU_ME_WUME0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1323	#define LLWU_ME_WUME0_SHIFT 0
emilmont	10:3bc89ef62ce7	1324	#define LLWU_ME_WUME1_MASK 0x2u
emilmont	10:3bc89ef62ce7	1325	#define LLWU_ME_WUME1_SHIFT 1
emilmont	10:3bc89ef62ce7	1326	#define LLWU_ME_WUME2_MASK 0x4u
emilmont	10:3bc89ef62ce7	1327	#define LLWU_ME_WUME2_SHIFT 2
emilmont	10:3bc89ef62ce7	1328	#define LLWU_ME_WUME3_MASK 0x8u
emilmont	10:3bc89ef62ce7	1329	#define LLWU_ME_WUME3_SHIFT 3
emilmont	10:3bc89ef62ce7	1330	#define LLWU_ME_WUME4_MASK 0x10u
emilmont	10:3bc89ef62ce7	1331	#define LLWU_ME_WUME4_SHIFT 4
emilmont	10:3bc89ef62ce7	1332	#define LLWU_ME_WUME5_MASK 0x20u
emilmont	10:3bc89ef62ce7	1333	#define LLWU_ME_WUME5_SHIFT 5
emilmont	10:3bc89ef62ce7	1334	#define LLWU_ME_WUME6_MASK 0x40u
emilmont	10:3bc89ef62ce7	1335	#define LLWU_ME_WUME6_SHIFT 6
emilmont	10:3bc89ef62ce7	1336	#define LLWU_ME_WUME7_MASK 0x80u
emilmont	10:3bc89ef62ce7	1337	#define LLWU_ME_WUME7_SHIFT 7
emilmont	10:3bc89ef62ce7	1338	/* F1 Bit Fields */
emilmont	10:3bc89ef62ce7	1339	#define LLWU_F1_WUF0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1340	#define LLWU_F1_WUF0_SHIFT 0
emilmont	10:3bc89ef62ce7	1341	#define LLWU_F1_WUF1_MASK 0x2u
emilmont	10:3bc89ef62ce7	1342	#define LLWU_F1_WUF1_SHIFT 1
emilmont	10:3bc89ef62ce7	1343	#define LLWU_F1_WUF2_MASK 0x4u
emilmont	10:3bc89ef62ce7	1344	#define LLWU_F1_WUF2_SHIFT 2
emilmont	10:3bc89ef62ce7	1345	#define LLWU_F1_WUF3_MASK 0x8u
emilmont	10:3bc89ef62ce7	1346	#define LLWU_F1_WUF3_SHIFT 3
emilmont	10:3bc89ef62ce7	1347	#define LLWU_F1_WUF4_MASK 0x10u
emilmont	10:3bc89ef62ce7	1348	#define LLWU_F1_WUF4_SHIFT 4
emilmont	10:3bc89ef62ce7	1349	#define LLWU_F1_WUF5_MASK 0x20u
emilmont	10:3bc89ef62ce7	1350	#define LLWU_F1_WUF5_SHIFT 5
emilmont	10:3bc89ef62ce7	1351	#define LLWU_F1_WUF6_MASK 0x40u
emilmont	10:3bc89ef62ce7	1352	#define LLWU_F1_WUF6_SHIFT 6
emilmont	10:3bc89ef62ce7	1353	#define LLWU_F1_WUF7_MASK 0x80u
emilmont	10:3bc89ef62ce7	1354	#define LLWU_F1_WUF7_SHIFT 7
emilmont	10:3bc89ef62ce7	1355	/* F2 Bit Fields */
emilmont	10:3bc89ef62ce7	1356	#define LLWU_F2_WUF8_MASK 0x1u
emilmont	10:3bc89ef62ce7	1357	#define LLWU_F2_WUF8_SHIFT 0
emilmont	10:3bc89ef62ce7	1358	#define LLWU_F2_WUF9_MASK 0x2u
emilmont	10:3bc89ef62ce7	1359	#define LLWU_F2_WUF9_SHIFT 1
emilmont	10:3bc89ef62ce7	1360	#define LLWU_F2_WUF10_MASK 0x4u
emilmont	10:3bc89ef62ce7	1361	#define LLWU_F2_WUF10_SHIFT 2
emilmont	10:3bc89ef62ce7	1362	#define LLWU_F2_WUF11_MASK 0x8u
emilmont	10:3bc89ef62ce7	1363	#define LLWU_F2_WUF11_SHIFT 3
emilmont	10:3bc89ef62ce7	1364	#define LLWU_F2_WUF12_MASK 0x10u
emilmont	10:3bc89ef62ce7	1365	#define LLWU_F2_WUF12_SHIFT 4
emilmont	10:3bc89ef62ce7	1366	#define LLWU_F2_WUF13_MASK 0x20u
emilmont	10:3bc89ef62ce7	1367	#define LLWU_F2_WUF13_SHIFT 5
emilmont	10:3bc89ef62ce7	1368	#define LLWU_F2_WUF14_MASK 0x40u
emilmont	10:3bc89ef62ce7	1369	#define LLWU_F2_WUF14_SHIFT 6
emilmont	10:3bc89ef62ce7	1370	#define LLWU_F2_WUF15_MASK 0x80u
emilmont	10:3bc89ef62ce7	1371	#define LLWU_F2_WUF15_SHIFT 7
emilmont	10:3bc89ef62ce7	1372	/* F3 Bit Fields */
emilmont	10:3bc89ef62ce7	1373	#define LLWU_F3_MWUF0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1374	#define LLWU_F3_MWUF0_SHIFT 0
emilmont	10:3bc89ef62ce7	1375	#define LLWU_F3_MWUF1_MASK 0x2u
emilmont	10:3bc89ef62ce7	1376	#define LLWU_F3_MWUF1_SHIFT 1
emilmont	10:3bc89ef62ce7	1377	#define LLWU_F3_MWUF2_MASK 0x4u
emilmont	10:3bc89ef62ce7	1378	#define LLWU_F3_MWUF2_SHIFT 2
emilmont	10:3bc89ef62ce7	1379	#define LLWU_F3_MWUF3_MASK 0x8u
emilmont	10:3bc89ef62ce7	1380	#define LLWU_F3_MWUF3_SHIFT 3
emilmont	10:3bc89ef62ce7	1381	#define LLWU_F3_MWUF4_MASK 0x10u
emilmont	10:3bc89ef62ce7	1382	#define LLWU_F3_MWUF4_SHIFT 4
emilmont	10:3bc89ef62ce7	1383	#define LLWU_F3_MWUF5_MASK 0x20u
emilmont	10:3bc89ef62ce7	1384	#define LLWU_F3_MWUF5_SHIFT 5
emilmont	10:3bc89ef62ce7	1385	#define LLWU_F3_MWUF6_MASK 0x40u
emilmont	10:3bc89ef62ce7	1386	#define LLWU_F3_MWUF6_SHIFT 6
emilmont	10:3bc89ef62ce7	1387	#define LLWU_F3_MWUF7_MASK 0x80u
emilmont	10:3bc89ef62ce7	1388	#define LLWU_F3_MWUF7_SHIFT 7
emilmont	10:3bc89ef62ce7	1389	/* FILT1 Bit Fields */
emilmont	10:3bc89ef62ce7	1390	#define LLWU_FILT1_FILTSEL_MASK 0xFu
emilmont	10:3bc89ef62ce7	1391	#define LLWU_FILT1_FILTSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	1392	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
emilmont	10:3bc89ef62ce7	1393	#define LLWU_FILT1_FILTE_MASK 0x60u
emilmont	10:3bc89ef62ce7	1394	#define LLWU_FILT1_FILTE_SHIFT 5
emilmont	10:3bc89ef62ce7	1395	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
emilmont	10:3bc89ef62ce7	1396	#define LLWU_FILT1_FILTF_MASK 0x80u
emilmont	10:3bc89ef62ce7	1397	#define LLWU_FILT1_FILTF_SHIFT 7
emilmont	10:3bc89ef62ce7	1398	/* FILT2 Bit Fields */
emilmont	10:3bc89ef62ce7	1399	#define LLWU_FILT2_FILTSEL_MASK 0xFu
emilmont	10:3bc89ef62ce7	1400	#define LLWU_FILT2_FILTSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	1401	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
emilmont	10:3bc89ef62ce7	1402	#define LLWU_FILT2_FILTE_MASK 0x60u
emilmont	10:3bc89ef62ce7	1403	#define LLWU_FILT2_FILTE_SHIFT 5
emilmont	10:3bc89ef62ce7	1404	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
emilmont	10:3bc89ef62ce7	1405	#define LLWU_FILT2_FILTF_MASK 0x80u
emilmont	10:3bc89ef62ce7	1406	#define LLWU_FILT2_FILTF_SHIFT 7
emilmont	10:3bc89ef62ce7	1407
emilmont	10:3bc89ef62ce7	1408	/**
emilmont	10:3bc89ef62ce7	1409	* @}
emilmont	10:3bc89ef62ce7	1410	/ / end of group LLWU_Register_Masks */
emilmont	10:3bc89ef62ce7	1411
emilmont	10:3bc89ef62ce7	1412
emilmont	10:3bc89ef62ce7	1413	/* LLWU - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1414	/** Peripheral LLWU base address */
emilmont	10:3bc89ef62ce7	1415	#define LLWU_BASE (0x4007C000u)
emilmont	10:3bc89ef62ce7	1416	/** Peripheral LLWU base pointer */
emilmont	10:3bc89ef62ce7	1417	#define LLWU ((LLWU_Type *)LLWU_BASE)
emilmont	10:3bc89ef62ce7	1418	/** Array initializer of LLWU peripheral base pointers */
emilmont	10:3bc89ef62ce7	1419	#define LLWU_BASES { LLWU }
emilmont	10:3bc89ef62ce7	1420
emilmont	10:3bc89ef62ce7	1421	/**
emilmont	10:3bc89ef62ce7	1422	* @}
emilmont	10:3bc89ef62ce7	1423	/ / end of group LLWU_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1424
emilmont	10:3bc89ef62ce7	1425
emilmont	10:3bc89ef62ce7	1426	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1427	-- LPTMR Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1428	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1429
emilmont	10:3bc89ef62ce7	1430	/**
emilmont	10:3bc89ef62ce7	1431	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1432	* @{
emilmont	10:3bc89ef62ce7	1433	*/
emilmont	10:3bc89ef62ce7	1434
emilmont	10:3bc89ef62ce7	1435	/** LPTMR - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1436	typedef struct {
emilmont	10:3bc89ef62ce7	1437	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1438	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1439	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1440	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	1441	} LPTMR_Type;
emilmont	10:3bc89ef62ce7	1442
emilmont	10:3bc89ef62ce7	1443	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1444	-- LPTMR Register Masks
emilmont	10:3bc89ef62ce7	1445	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1446
emilmont	10:3bc89ef62ce7	1447	/**
emilmont	10:3bc89ef62ce7	1448	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
emilmont	10:3bc89ef62ce7	1449	* @{
emilmont	10:3bc89ef62ce7	1450	*/
emilmont	10:3bc89ef62ce7	1451
emilmont	10:3bc89ef62ce7	1452	/* CSR Bit Fields */
emilmont	10:3bc89ef62ce7	1453	#define LPTMR_CSR_TEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	1454	#define LPTMR_CSR_TEN_SHIFT 0
emilmont	10:3bc89ef62ce7	1455	#define LPTMR_CSR_TMS_MASK 0x2u
emilmont	10:3bc89ef62ce7	1456	#define LPTMR_CSR_TMS_SHIFT 1
emilmont	10:3bc89ef62ce7	1457	#define LPTMR_CSR_TFC_MASK 0x4u
emilmont	10:3bc89ef62ce7	1458	#define LPTMR_CSR_TFC_SHIFT 2
emilmont	10:3bc89ef62ce7	1459	#define LPTMR_CSR_TPP_MASK 0x8u
emilmont	10:3bc89ef62ce7	1460	#define LPTMR_CSR_TPP_SHIFT 3
emilmont	10:3bc89ef62ce7	1461	#define LPTMR_CSR_TPS_MASK 0x30u
emilmont	10:3bc89ef62ce7	1462	#define LPTMR_CSR_TPS_SHIFT 4
emilmont	10:3bc89ef62ce7	1463	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
emilmont	10:3bc89ef62ce7	1464	#define LPTMR_CSR_TIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	1465	#define LPTMR_CSR_TIE_SHIFT 6
emilmont	10:3bc89ef62ce7	1466	#define LPTMR_CSR_TCF_MASK 0x80u
emilmont	10:3bc89ef62ce7	1467	#define LPTMR_CSR_TCF_SHIFT 7
emilmont	10:3bc89ef62ce7	1468	/* PSR Bit Fields */
emilmont	10:3bc89ef62ce7	1469	#define LPTMR_PSR_PCS_MASK 0x3u
emilmont	10:3bc89ef62ce7	1470	#define LPTMR_PSR_PCS_SHIFT 0
emilmont	10:3bc89ef62ce7	1471	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
emilmont	10:3bc89ef62ce7	1472	#define LPTMR_PSR_PBYP_MASK 0x4u
emilmont	10:3bc89ef62ce7	1473	#define LPTMR_PSR_PBYP_SHIFT 2
emilmont	10:3bc89ef62ce7	1474	#define LPTMR_PSR_PRESCALE_MASK 0x78u
emilmont	10:3bc89ef62ce7	1475	#define LPTMR_PSR_PRESCALE_SHIFT 3
emilmont	10:3bc89ef62ce7	1476	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
emilmont	10:3bc89ef62ce7	1477	/* CMR Bit Fields */
emilmont	10:3bc89ef62ce7	1478	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	1479	#define LPTMR_CMR_COMPARE_SHIFT 0
emilmont	10:3bc89ef62ce7	1480	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
emilmont	10:3bc89ef62ce7	1481	/* CNR Bit Fields */
emilmont	10:3bc89ef62ce7	1482	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	1483	#define LPTMR_CNR_COUNTER_SHIFT 0
emilmont	10:3bc89ef62ce7	1484	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
emilmont	10:3bc89ef62ce7	1485
emilmont	10:3bc89ef62ce7	1486	/**
emilmont	10:3bc89ef62ce7	1487	* @}
emilmont	10:3bc89ef62ce7	1488	/ / end of group LPTMR_Register_Masks */
emilmont	10:3bc89ef62ce7	1489
emilmont	10:3bc89ef62ce7	1490
emilmont	10:3bc89ef62ce7	1491	/* LPTMR - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1492	/** Peripheral LPTMR0 base address */
emilmont	10:3bc89ef62ce7	1493	#define LPTMR0_BASE (0x40040000u)
emilmont	10:3bc89ef62ce7	1494	/** Peripheral LPTMR0 base pointer */
emilmont	10:3bc89ef62ce7	1495	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
emilmont	10:3bc89ef62ce7	1496	/** Array initializer of LPTMR peripheral base pointers */
emilmont	10:3bc89ef62ce7	1497	#define LPTMR_BASES { LPTMR0 }
emilmont	10:3bc89ef62ce7	1498
emilmont	10:3bc89ef62ce7	1499	/**
emilmont	10:3bc89ef62ce7	1500	* @}
emilmont	10:3bc89ef62ce7	1501	/ / end of group LPTMR_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1502
emilmont	10:3bc89ef62ce7	1503
emilmont	10:3bc89ef62ce7	1504	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1505	-- MCG Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1506	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1507
emilmont	10:3bc89ef62ce7	1508	/**
emilmont	10:3bc89ef62ce7	1509	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1510	* @{
emilmont	10:3bc89ef62ce7	1511	*/
emilmont	10:3bc89ef62ce7	1512
emilmont	10:3bc89ef62ce7	1513	/** MCG - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1514	typedef struct {
emilmont	10:3bc89ef62ce7	1515	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1516	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	1517	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	1518	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	1519	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1520	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
emilmont	10:3bc89ef62ce7	1521	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
emilmont	10:3bc89ef62ce7	1522	uint8_t RESERVED_0[1];
emilmont	10:3bc89ef62ce7	1523	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1524	uint8_t RESERVED_1[1];
emilmont	10:3bc89ef62ce7	1525	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
emilmont	10:3bc89ef62ce7	1526	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
emilmont	10:3bc89ef62ce7	1527	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	1528	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
emilmont	10:3bc89ef62ce7	1529	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
emilmont	10:3bc89ef62ce7	1530	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
emilmont	10:3bc89ef62ce7	1531	} MCG_Type;
emilmont	10:3bc89ef62ce7	1532
emilmont	10:3bc89ef62ce7	1533	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1534	-- MCG Register Masks
emilmont	10:3bc89ef62ce7	1535	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1536
emilmont	10:3bc89ef62ce7	1537	/**
emilmont	10:3bc89ef62ce7	1538	* @addtogroup MCG_Register_Masks MCG Register Masks
emilmont	10:3bc89ef62ce7	1539	* @{
emilmont	10:3bc89ef62ce7	1540	*/
emilmont	10:3bc89ef62ce7	1541
emilmont	10:3bc89ef62ce7	1542	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	1543	#define MCG_C1_IREFSTEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	1544	#define MCG_C1_IREFSTEN_SHIFT 0
emilmont	10:3bc89ef62ce7	1545	#define MCG_C1_IRCLKEN_MASK 0x2u
emilmont	10:3bc89ef62ce7	1546	#define MCG_C1_IRCLKEN_SHIFT 1
emilmont	10:3bc89ef62ce7	1547	#define MCG_C1_IREFS_MASK 0x4u
emilmont	10:3bc89ef62ce7	1548	#define MCG_C1_IREFS_SHIFT 2
emilmont	10:3bc89ef62ce7	1549	#define MCG_C1_FRDIV_MASK 0x38u
emilmont	10:3bc89ef62ce7	1550	#define MCG_C1_FRDIV_SHIFT 3
emilmont	10:3bc89ef62ce7	1551	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
emilmont	10:3bc89ef62ce7	1552	#define MCG_C1_CLKS_MASK 0xC0u
emilmont	10:3bc89ef62ce7	1553	#define MCG_C1_CLKS_SHIFT 6
emilmont	10:3bc89ef62ce7	1554	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
emilmont	10:3bc89ef62ce7	1555	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	1556	#define MCG_C2_IRCS_MASK 0x1u
emilmont	10:3bc89ef62ce7	1557	#define MCG_C2_IRCS_SHIFT 0
emilmont	10:3bc89ef62ce7	1558	#define MCG_C2_LP_MASK 0x2u
emilmont	10:3bc89ef62ce7	1559	#define MCG_C2_LP_SHIFT 1
emilmont	10:3bc89ef62ce7	1560	#define MCG_C2_EREFS0_MASK 0x4u
emilmont	10:3bc89ef62ce7	1561	#define MCG_C2_EREFS0_SHIFT 2
emilmont	10:3bc89ef62ce7	1562	#define MCG_C2_HGO0_MASK 0x8u
emilmont	10:3bc89ef62ce7	1563	#define MCG_C2_HGO0_SHIFT 3
emilmont	10:3bc89ef62ce7	1564	#define MCG_C2_RANGE0_MASK 0x30u
emilmont	10:3bc89ef62ce7	1565	#define MCG_C2_RANGE0_SHIFT 4
emilmont	10:3bc89ef62ce7	1566	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
emilmont	10:3bc89ef62ce7	1567	#define MCG_C2_LOCRE0_MASK 0x80u
emilmont	10:3bc89ef62ce7	1568	#define MCG_C2_LOCRE0_SHIFT 7
emilmont	10:3bc89ef62ce7	1569	/* C3 Bit Fields */
emilmont	10:3bc89ef62ce7	1570	#define MCG_C3_SCTRIM_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1571	#define MCG_C3_SCTRIM_SHIFT 0
emilmont	10:3bc89ef62ce7	1572	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
emilmont	10:3bc89ef62ce7	1573	/* C4 Bit Fields */
emilmont	10:3bc89ef62ce7	1574	#define MCG_C4_SCFTRIM_MASK 0x1u
emilmont	10:3bc89ef62ce7	1575	#define MCG_C4_SCFTRIM_SHIFT 0
emilmont	10:3bc89ef62ce7	1576	#define MCG_C4_FCTRIM_MASK 0x1Eu
emilmont	10:3bc89ef62ce7	1577	#define MCG_C4_FCTRIM_SHIFT 1
emilmont	10:3bc89ef62ce7	1578	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
emilmont	10:3bc89ef62ce7	1579	#define MCG_C4_DRST_DRS_MASK 0x60u
emilmont	10:3bc89ef62ce7	1580	#define MCG_C4_DRST_DRS_SHIFT 5
emilmont	10:3bc89ef62ce7	1581	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
emilmont	10:3bc89ef62ce7	1582	#define MCG_C4_DMX32_MASK 0x80u
emilmont	10:3bc89ef62ce7	1583	#define MCG_C4_DMX32_SHIFT 7
emilmont	10:3bc89ef62ce7	1584	/* C5 Bit Fields */
emilmont	10:3bc89ef62ce7	1585	#define MCG_C5_PRDIV0_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	1586	#define MCG_C5_PRDIV0_SHIFT 0
emilmont	10:3bc89ef62ce7	1587	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
emilmont	10:3bc89ef62ce7	1588	#define MCG_C5_PLLSTEN0_MASK 0x20u
emilmont	10:3bc89ef62ce7	1589	#define MCG_C5_PLLSTEN0_SHIFT 5
emilmont	10:3bc89ef62ce7	1590	#define MCG_C5_PLLCLKEN0_MASK 0x40u
emilmont	10:3bc89ef62ce7	1591	#define MCG_C5_PLLCLKEN0_SHIFT 6
emilmont	10:3bc89ef62ce7	1592	/* C6 Bit Fields */
emilmont	10:3bc89ef62ce7	1593	#define MCG_C6_VDIV0_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	1594	#define MCG_C6_VDIV0_SHIFT 0
emilmont	10:3bc89ef62ce7	1595	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
emilmont	10:3bc89ef62ce7	1596	#define MCG_C6_CME0_MASK 0x20u
emilmont	10:3bc89ef62ce7	1597	#define MCG_C6_CME0_SHIFT 5
emilmont	10:3bc89ef62ce7	1598	#define MCG_C6_PLLS_MASK 0x40u
emilmont	10:3bc89ef62ce7	1599	#define MCG_C6_PLLS_SHIFT 6
emilmont	10:3bc89ef62ce7	1600	#define MCG_C6_LOLIE0_MASK 0x80u
emilmont	10:3bc89ef62ce7	1601	#define MCG_C6_LOLIE0_SHIFT 7
emilmont	10:3bc89ef62ce7	1602	/* S Bit Fields */
emilmont	10:3bc89ef62ce7	1603	#define MCG_S_IRCST_MASK 0x1u
emilmont	10:3bc89ef62ce7	1604	#define MCG_S_IRCST_SHIFT 0
emilmont	10:3bc89ef62ce7	1605	#define MCG_S_OSCINIT0_MASK 0x2u
emilmont	10:3bc89ef62ce7	1606	#define MCG_S_OSCINIT0_SHIFT 1
emilmont	10:3bc89ef62ce7	1607	#define MCG_S_CLKST_MASK 0xCu
emilmont	10:3bc89ef62ce7	1608	#define MCG_S_CLKST_SHIFT 2
emilmont	10:3bc89ef62ce7	1609	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
emilmont	10:3bc89ef62ce7	1610	#define MCG_S_IREFST_MASK 0x10u
emilmont	10:3bc89ef62ce7	1611	#define MCG_S_IREFST_SHIFT 4
emilmont	10:3bc89ef62ce7	1612	#define MCG_S_PLLST_MASK 0x20u
emilmont	10:3bc89ef62ce7	1613	#define MCG_S_PLLST_SHIFT 5
emilmont	10:3bc89ef62ce7	1614	#define MCG_S_LOCK0_MASK 0x40u
emilmont	10:3bc89ef62ce7	1615	#define MCG_S_LOCK0_SHIFT 6
emilmont	10:3bc89ef62ce7	1616	#define MCG_S_LOLS_MASK 0x80u
emilmont	10:3bc89ef62ce7	1617	#define MCG_S_LOLS_SHIFT 7
emilmont	10:3bc89ef62ce7	1618	/* SC Bit Fields */
emilmont	10:3bc89ef62ce7	1619	#define MCG_SC_LOCS0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1620	#define MCG_SC_LOCS0_SHIFT 0
emilmont	10:3bc89ef62ce7	1621	#define MCG_SC_FCRDIV_MASK 0xEu
emilmont	10:3bc89ef62ce7	1622	#define MCG_SC_FCRDIV_SHIFT 1
emilmont	10:3bc89ef62ce7	1623	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
emilmont	10:3bc89ef62ce7	1624	#define MCG_SC_FLTPRSRV_MASK 0x10u
emilmont	10:3bc89ef62ce7	1625	#define MCG_SC_FLTPRSRV_SHIFT 4
emilmont	10:3bc89ef62ce7	1626	#define MCG_SC_ATMF_MASK 0x20u
emilmont	10:3bc89ef62ce7	1627	#define MCG_SC_ATMF_SHIFT 5
emilmont	10:3bc89ef62ce7	1628	#define MCG_SC_ATMS_MASK 0x40u
emilmont	10:3bc89ef62ce7	1629	#define MCG_SC_ATMS_SHIFT 6
emilmont	10:3bc89ef62ce7	1630	#define MCG_SC_ATME_MASK 0x80u
emilmont	10:3bc89ef62ce7	1631	#define MCG_SC_ATME_SHIFT 7
emilmont	10:3bc89ef62ce7	1632	/* ATCVH Bit Fields */
emilmont	10:3bc89ef62ce7	1633	#define MCG_ATCVH_ATCVH_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1634	#define MCG_ATCVH_ATCVH_SHIFT 0
emilmont	10:3bc89ef62ce7	1635	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
emilmont	10:3bc89ef62ce7	1636	/* ATCVL Bit Fields */
emilmont	10:3bc89ef62ce7	1637	#define MCG_ATCVL_ATCVL_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1638	#define MCG_ATCVL_ATCVL_SHIFT 0
emilmont	10:3bc89ef62ce7	1639	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
emilmont	10:3bc89ef62ce7	1640	/* C8 Bit Fields */
emilmont	10:3bc89ef62ce7	1641	#define MCG_C8_LOLRE_MASK 0x40u
emilmont	10:3bc89ef62ce7	1642	#define MCG_C8_LOLRE_SHIFT 6
emilmont	10:3bc89ef62ce7	1643
emilmont	10:3bc89ef62ce7	1644	/**
emilmont	10:3bc89ef62ce7	1645	* @}
emilmont	10:3bc89ef62ce7	1646	/ / end of group MCG_Register_Masks */
emilmont	10:3bc89ef62ce7	1647
emilmont	10:3bc89ef62ce7	1648
emilmont	10:3bc89ef62ce7	1649	/* MCG - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1650	/** Peripheral MCG base address */
emilmont	10:3bc89ef62ce7	1651	#define MCG_BASE (0x40064000u)
emilmont	10:3bc89ef62ce7	1652	/** Peripheral MCG base pointer */
emilmont	10:3bc89ef62ce7	1653	#define MCG ((MCG_Type *)MCG_BASE)
emilmont	10:3bc89ef62ce7	1654	/** Array initializer of MCG peripheral base pointers */
emilmont	10:3bc89ef62ce7	1655	#define MCG_BASES { MCG }
emilmont	10:3bc89ef62ce7	1656
emilmont	10:3bc89ef62ce7	1657	/**
emilmont	10:3bc89ef62ce7	1658	* @}
emilmont	10:3bc89ef62ce7	1659	/ / end of group MCG_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1660
emilmont	10:3bc89ef62ce7	1661
emilmont	10:3bc89ef62ce7	1662	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1663	-- MCM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1664	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1665
emilmont	10:3bc89ef62ce7	1666	/**
emilmont	10:3bc89ef62ce7	1667	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1668	* @{
emilmont	10:3bc89ef62ce7	1669	*/
emilmont	10:3bc89ef62ce7	1670
emilmont	10:3bc89ef62ce7	1671	/** MCM - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1672	typedef struct {
emilmont	10:3bc89ef62ce7	1673	uint8_t RESERVED_0[8];
emilmont	10:3bc89ef62ce7	1674	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1675	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
emilmont	10:3bc89ef62ce7	1676	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	1677	uint8_t RESERVED_1[48];
emilmont	10:3bc89ef62ce7	1678	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
emilmont	10:3bc89ef62ce7	1679	} MCM_Type;
emilmont	10:3bc89ef62ce7	1680
emilmont	10:3bc89ef62ce7	1681	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1682	-- MCM Register Masks
emilmont	10:3bc89ef62ce7	1683	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1684
emilmont	10:3bc89ef62ce7	1685	/**
emilmont	10:3bc89ef62ce7	1686	* @addtogroup MCM_Register_Masks MCM Register Masks
emilmont	10:3bc89ef62ce7	1687	* @{
emilmont	10:3bc89ef62ce7	1688	*/
emilmont	10:3bc89ef62ce7	1689
emilmont	10:3bc89ef62ce7	1690	/* PLASC Bit Fields */
emilmont	10:3bc89ef62ce7	1691	#define MCM_PLASC_ASC_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1692	#define MCM_PLASC_ASC_SHIFT 0
emilmont	10:3bc89ef62ce7	1693	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
emilmont	10:3bc89ef62ce7	1694	/* PLAMC Bit Fields */
emilmont	10:3bc89ef62ce7	1695	#define MCM_PLAMC_AMC_MASK 0xFFu
emilmont	10:3bc89ef62ce7	1696	#define MCM_PLAMC_AMC_SHIFT 0
emilmont	10:3bc89ef62ce7	1697	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
emilmont	10:3bc89ef62ce7	1698	/* PLACR Bit Fields */
emilmont	10:3bc89ef62ce7	1699	#define MCM_PLACR_ARB_MASK 0x200u
emilmont	10:3bc89ef62ce7	1700	#define MCM_PLACR_ARB_SHIFT 9
emilmont	10:3bc89ef62ce7	1701	#define MCM_PLACR_CFCC_MASK 0x400u
emilmont	10:3bc89ef62ce7	1702	#define MCM_PLACR_CFCC_SHIFT 10
emilmont	10:3bc89ef62ce7	1703	#define MCM_PLACR_DFCDA_MASK 0x800u
emilmont	10:3bc89ef62ce7	1704	#define MCM_PLACR_DFCDA_SHIFT 11
emilmont	10:3bc89ef62ce7	1705	#define MCM_PLACR_DFCIC_MASK 0x1000u
emilmont	10:3bc89ef62ce7	1706	#define MCM_PLACR_DFCIC_SHIFT 12
emilmont	10:3bc89ef62ce7	1707	#define MCM_PLACR_DFCC_MASK 0x2000u
emilmont	10:3bc89ef62ce7	1708	#define MCM_PLACR_DFCC_SHIFT 13
emilmont	10:3bc89ef62ce7	1709	#define MCM_PLACR_EFDS_MASK 0x4000u
emilmont	10:3bc89ef62ce7	1710	#define MCM_PLACR_EFDS_SHIFT 14
emilmont	10:3bc89ef62ce7	1711	#define MCM_PLACR_DFCS_MASK 0x8000u
emilmont	10:3bc89ef62ce7	1712	#define MCM_PLACR_DFCS_SHIFT 15
emilmont	10:3bc89ef62ce7	1713	#define MCM_PLACR_ESFC_MASK 0x10000u
emilmont	10:3bc89ef62ce7	1714	#define MCM_PLACR_ESFC_SHIFT 16
emilmont	10:3bc89ef62ce7	1715	/* CPO Bit Fields */
emilmont	10:3bc89ef62ce7	1716	#define MCM_CPO_CPOREQ_MASK 0x1u
emilmont	10:3bc89ef62ce7	1717	#define MCM_CPO_CPOREQ_SHIFT 0
emilmont	10:3bc89ef62ce7	1718	#define MCM_CPO_CPOACK_MASK 0x2u
emilmont	10:3bc89ef62ce7	1719	#define MCM_CPO_CPOACK_SHIFT 1
emilmont	10:3bc89ef62ce7	1720	#define MCM_CPO_CPOWOI_MASK 0x4u
emilmont	10:3bc89ef62ce7	1721	#define MCM_CPO_CPOWOI_SHIFT 2
emilmont	10:3bc89ef62ce7	1722
emilmont	10:3bc89ef62ce7	1723	/**
emilmont	10:3bc89ef62ce7	1724	* @}
emilmont	10:3bc89ef62ce7	1725	/ / end of group MCM_Register_Masks */
emilmont	10:3bc89ef62ce7	1726
emilmont	10:3bc89ef62ce7	1727
emilmont	10:3bc89ef62ce7	1728	/* MCM - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1729	/** Peripheral MCM base address */
emilmont	10:3bc89ef62ce7	1730	#define MCM_BASE (0xF0003000u)
emilmont	10:3bc89ef62ce7	1731	/** Peripheral MCM base pointer */
emilmont	10:3bc89ef62ce7	1732	#define MCM ((MCM_Type *)MCM_BASE)
emilmont	10:3bc89ef62ce7	1733	/** Array initializer of MCM peripheral base pointers */
emilmont	10:3bc89ef62ce7	1734	#define MCM_BASES { MCM }
emilmont	10:3bc89ef62ce7	1735
emilmont	10:3bc89ef62ce7	1736	/**
emilmont	10:3bc89ef62ce7	1737	* @}
emilmont	10:3bc89ef62ce7	1738	/ / end of group MCM_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1739
emilmont	10:3bc89ef62ce7	1740
emilmont	10:3bc89ef62ce7	1741	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1742	-- MTB Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1743	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1744
emilmont	10:3bc89ef62ce7	1745	/**
emilmont	10:3bc89ef62ce7	1746	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1747	* @{
emilmont	10:3bc89ef62ce7	1748	*/
emilmont	10:3bc89ef62ce7	1749
emilmont	10:3bc89ef62ce7	1750	/** MTB - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1751	typedef struct {
emilmont	10:3bc89ef62ce7	1752	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1753	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	1754	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	1755	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	1756	uint8_t RESERVED_0[3824];
emilmont	10:3bc89ef62ce7	1757	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
emilmont	10:3bc89ef62ce7	1758	uint8_t RESERVED_1[156];
emilmont	10:3bc89ef62ce7	1759	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
emilmont	10:3bc89ef62ce7	1760	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
emilmont	10:3bc89ef62ce7	1761	uint8_t RESERVED_2[8];
emilmont	10:3bc89ef62ce7	1762	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
emilmont	10:3bc89ef62ce7	1763	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
emilmont	10:3bc89ef62ce7	1764	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
emilmont	10:3bc89ef62ce7	1765	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
emilmont	10:3bc89ef62ce7	1766	uint8_t RESERVED_3[8];
emilmont	10:3bc89ef62ce7	1767	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	10:3bc89ef62ce7	1768	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	10:3bc89ef62ce7	1769	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	1770	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	1771	} MTB_Type;
emilmont	10:3bc89ef62ce7	1772
emilmont	10:3bc89ef62ce7	1773	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1774	-- MTB Register Masks
emilmont	10:3bc89ef62ce7	1775	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1776
emilmont	10:3bc89ef62ce7	1777	/**
emilmont	10:3bc89ef62ce7	1778	* @addtogroup MTB_Register_Masks MTB Register Masks
emilmont	10:3bc89ef62ce7	1779	* @{
emilmont	10:3bc89ef62ce7	1780	*/
emilmont	10:3bc89ef62ce7	1781
emilmont	10:3bc89ef62ce7	1782	/* POSITION Bit Fields */
emilmont	10:3bc89ef62ce7	1783	#define MTB_POSITION_WRAP_MASK 0x4u
emilmont	10:3bc89ef62ce7	1784	#define MTB_POSITION_WRAP_SHIFT 2
emilmont	10:3bc89ef62ce7	1785	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
emilmont	10:3bc89ef62ce7	1786	#define MTB_POSITION_POINTER_SHIFT 3
emilmont	10:3bc89ef62ce7	1787	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
emilmont	10:3bc89ef62ce7	1788	/* MASTER Bit Fields */
emilmont	10:3bc89ef62ce7	1789	#define MTB_MASTER_MASK_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	1790	#define MTB_MASTER_MASK_SHIFT 0
emilmont	10:3bc89ef62ce7	1791	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
emilmont	10:3bc89ef62ce7	1792	#define MTB_MASTER_TSTARTEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	1793	#define MTB_MASTER_TSTARTEN_SHIFT 5
emilmont	10:3bc89ef62ce7	1794	#define MTB_MASTER_TSTOPEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	1795	#define MTB_MASTER_TSTOPEN_SHIFT 6
emilmont	10:3bc89ef62ce7	1796	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
emilmont	10:3bc89ef62ce7	1797	#define MTB_MASTER_SFRWPRIV_SHIFT 7
emilmont	10:3bc89ef62ce7	1798	#define MTB_MASTER_RAMPRIV_MASK 0x100u
emilmont	10:3bc89ef62ce7	1799	#define MTB_MASTER_RAMPRIV_SHIFT 8
emilmont	10:3bc89ef62ce7	1800	#define MTB_MASTER_HALTREQ_MASK 0x200u
emilmont	10:3bc89ef62ce7	1801	#define MTB_MASTER_HALTREQ_SHIFT 9
emilmont	10:3bc89ef62ce7	1802	#define MTB_MASTER_EN_MASK 0x80000000u
emilmont	10:3bc89ef62ce7	1803	#define MTB_MASTER_EN_SHIFT 31
emilmont	10:3bc89ef62ce7	1804	/* FLOW Bit Fields */
emilmont	10:3bc89ef62ce7	1805	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
emilmont	10:3bc89ef62ce7	1806	#define MTB_FLOW_AUTOSTOP_SHIFT 0
emilmont	10:3bc89ef62ce7	1807	#define MTB_FLOW_AUTOHALT_MASK 0x2u
emilmont	10:3bc89ef62ce7	1808	#define MTB_FLOW_AUTOHALT_SHIFT 1
emilmont	10:3bc89ef62ce7	1809	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
emilmont	10:3bc89ef62ce7	1810	#define MTB_FLOW_WATERMARK_SHIFT 3
emilmont	10:3bc89ef62ce7	1811	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
emilmont	10:3bc89ef62ce7	1812	/* BASE Bit Fields */
emilmont	10:3bc89ef62ce7	1813	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1814	#define MTB_BASE_BASEADDR_SHIFT 0
emilmont	10:3bc89ef62ce7	1815	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
emilmont	10:3bc89ef62ce7	1816	/* MODECTRL Bit Fields */
emilmont	10:3bc89ef62ce7	1817	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1818	#define MTB_MODECTRL_MODECTRL_SHIFT 0
emilmont	10:3bc89ef62ce7	1819	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
emilmont	10:3bc89ef62ce7	1820	/* TAGSET Bit Fields */
emilmont	10:3bc89ef62ce7	1821	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1822	#define MTB_TAGSET_TAGSET_SHIFT 0
emilmont	10:3bc89ef62ce7	1823	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
emilmont	10:3bc89ef62ce7	1824	/* TAGCLEAR Bit Fields */
emilmont	10:3bc89ef62ce7	1825	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1826	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
emilmont	10:3bc89ef62ce7	1827	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
emilmont	10:3bc89ef62ce7	1828	/* LOCKACCESS Bit Fields */
emilmont	10:3bc89ef62ce7	1829	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1830	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
emilmont	10:3bc89ef62ce7	1831	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
emilmont	10:3bc89ef62ce7	1832	/* LOCKSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	1833	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1834	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
emilmont	10:3bc89ef62ce7	1835	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
emilmont	10:3bc89ef62ce7	1836	/* AUTHSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	1837	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1838	#define MTB_AUTHSTAT_BIT0_SHIFT 0
emilmont	10:3bc89ef62ce7	1839	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
emilmont	10:3bc89ef62ce7	1840	#define MTB_AUTHSTAT_BIT1_SHIFT 1
emilmont	10:3bc89ef62ce7	1841	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
emilmont	10:3bc89ef62ce7	1842	#define MTB_AUTHSTAT_BIT2_SHIFT 2
emilmont	10:3bc89ef62ce7	1843	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
emilmont	10:3bc89ef62ce7	1844	#define MTB_AUTHSTAT_BIT3_SHIFT 3
emilmont	10:3bc89ef62ce7	1845	/* DEVICEARCH Bit Fields */
emilmont	10:3bc89ef62ce7	1846	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1847	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
emilmont	10:3bc89ef62ce7	1848	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
emilmont	10:3bc89ef62ce7	1849	/* DEVICECFG Bit Fields */
emilmont	10:3bc89ef62ce7	1850	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1851	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	10:3bc89ef62ce7	1852	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
emilmont	10:3bc89ef62ce7	1853	/* DEVICETYPID Bit Fields */
emilmont	10:3bc89ef62ce7	1854	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1855	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	10:3bc89ef62ce7	1856	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
emilmont	10:3bc89ef62ce7	1857	/* PERIPHID Bit Fields */
emilmont	10:3bc89ef62ce7	1858	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1859	#define MTB_PERIPHID_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	1860	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	1861	/* COMPID Bit Fields */
emilmont	10:3bc89ef62ce7	1862	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1863	#define MTB_COMPID_COMPID_SHIFT 0
emilmont	10:3bc89ef62ce7	1864	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
emilmont	10:3bc89ef62ce7	1865
emilmont	10:3bc89ef62ce7	1866	/**
emilmont	10:3bc89ef62ce7	1867	* @}
emilmont	10:3bc89ef62ce7	1868	/ / end of group MTB_Register_Masks */
emilmont	10:3bc89ef62ce7	1869
emilmont	10:3bc89ef62ce7	1870
emilmont	10:3bc89ef62ce7	1871	/* MTB - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1872	/** Peripheral MTB base address */
emilmont	10:3bc89ef62ce7	1873	#define MTB_BASE (0xF0000000u)
emilmont	10:3bc89ef62ce7	1874	/** Peripheral MTB base pointer */
emilmont	10:3bc89ef62ce7	1875	#define MTB ((MTB_Type *)MTB_BASE)
emilmont	10:3bc89ef62ce7	1876	/** Array initializer of MTB peripheral base pointers */
emilmont	10:3bc89ef62ce7	1877	#define MTB_BASES { MTB }
emilmont	10:3bc89ef62ce7	1878
emilmont	10:3bc89ef62ce7	1879	/**
emilmont	10:3bc89ef62ce7	1880	* @}
emilmont	10:3bc89ef62ce7	1881	/ / end of group MTB_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1882
emilmont	10:3bc89ef62ce7	1883
emilmont	10:3bc89ef62ce7	1884	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1885	-- MTBDWT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1886	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1887
emilmont	10:3bc89ef62ce7	1888	/**
emilmont	10:3bc89ef62ce7	1889	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1890	* @{
emilmont	10:3bc89ef62ce7	1891	*/
emilmont	10:3bc89ef62ce7	1892
emilmont	10:3bc89ef62ce7	1893	/** MTBDWT - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	1894	typedef struct {
emilmont	10:3bc89ef62ce7	1895	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	1896	uint8_t RESERVED_0[28];
emilmont	10:3bc89ef62ce7	1897	struct { /* offset: 0x20, array step: 0x10 */
emilmont	10:3bc89ef62ce7	1898	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
emilmont	10:3bc89ef62ce7	1899	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
emilmont	10:3bc89ef62ce7	1900	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
emilmont	10:3bc89ef62ce7	1901	uint8_t RESERVED_0[4];
emilmont	10:3bc89ef62ce7	1902	} COMPARATOR[2];
emilmont	10:3bc89ef62ce7	1903	uint8_t RESERVED_1[448];
emilmont	10:3bc89ef62ce7	1904	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
emilmont	10:3bc89ef62ce7	1905	uint8_t RESERVED_2[3524];
emilmont	10:3bc89ef62ce7	1906	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	10:3bc89ef62ce7	1907	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	10:3bc89ef62ce7	1908	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	1909	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	1910	} MTBDWT_Type;
emilmont	10:3bc89ef62ce7	1911
emilmont	10:3bc89ef62ce7	1912	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1913	-- MTBDWT Register Masks
emilmont	10:3bc89ef62ce7	1914	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1915
emilmont	10:3bc89ef62ce7	1916	/**
emilmont	10:3bc89ef62ce7	1917	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
emilmont	10:3bc89ef62ce7	1918	* @{
emilmont	10:3bc89ef62ce7	1919	*/
emilmont	10:3bc89ef62ce7	1920
emilmont	10:3bc89ef62ce7	1921	/* CTRL Bit Fields */
emilmont	10:3bc89ef62ce7	1922	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
emilmont	10:3bc89ef62ce7	1923	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
emilmont	10:3bc89ef62ce7	1924	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
emilmont	10:3bc89ef62ce7	1925	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
emilmont	10:3bc89ef62ce7	1926	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
emilmont	10:3bc89ef62ce7	1927	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
emilmont	10:3bc89ef62ce7	1928	/* COMP Bit Fields */
emilmont	10:3bc89ef62ce7	1929	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1930	#define MTBDWT_COMP_COMP_SHIFT 0
emilmont	10:3bc89ef62ce7	1931	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
emilmont	10:3bc89ef62ce7	1932	/* MASK Bit Fields */
emilmont	10:3bc89ef62ce7	1933	#define MTBDWT_MASK_MASK_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	1934	#define MTBDWT_MASK_MASK_SHIFT 0
emilmont	10:3bc89ef62ce7	1935	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
emilmont	10:3bc89ef62ce7	1936	/* FCT Bit Fields */
emilmont	10:3bc89ef62ce7	1937	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
emilmont	10:3bc89ef62ce7	1938	#define MTBDWT_FCT_FUNCTION_SHIFT 0
emilmont	10:3bc89ef62ce7	1939	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
emilmont	10:3bc89ef62ce7	1940	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
emilmont	10:3bc89ef62ce7	1941	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
emilmont	10:3bc89ef62ce7	1942	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
emilmont	10:3bc89ef62ce7	1943	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
emilmont	10:3bc89ef62ce7	1944	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
emilmont	10:3bc89ef62ce7	1945	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
emilmont	10:3bc89ef62ce7	1946	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
emilmont	10:3bc89ef62ce7	1947	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
emilmont	10:3bc89ef62ce7	1948	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	1949	#define MTBDWT_FCT_MATCHED_SHIFT 24
emilmont	10:3bc89ef62ce7	1950	/* TBCTRL Bit Fields */
emilmont	10:3bc89ef62ce7	1951	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
emilmont	10:3bc89ef62ce7	1952	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
emilmont	10:3bc89ef62ce7	1953	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
emilmont	10:3bc89ef62ce7	1954	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
emilmont	10:3bc89ef62ce7	1955	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
emilmont	10:3bc89ef62ce7	1956	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
emilmont	10:3bc89ef62ce7	1957	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
emilmont	10:3bc89ef62ce7	1958	/* DEVICECFG Bit Fields */
emilmont	10:3bc89ef62ce7	1959	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1960	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	10:3bc89ef62ce7	1961	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
emilmont	10:3bc89ef62ce7	1962	/* DEVICETYPID Bit Fields */
emilmont	10:3bc89ef62ce7	1963	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1964	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	10:3bc89ef62ce7	1965	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
emilmont	10:3bc89ef62ce7	1966	/* PERIPHID Bit Fields */
emilmont	10:3bc89ef62ce7	1967	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1968	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	1969	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	1970	/* COMPID Bit Fields */
emilmont	10:3bc89ef62ce7	1971	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	1972	#define MTBDWT_COMPID_COMPID_SHIFT 0
emilmont	10:3bc89ef62ce7	1973	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
emilmont	10:3bc89ef62ce7	1974
emilmont	10:3bc89ef62ce7	1975	/**
emilmont	10:3bc89ef62ce7	1976	* @}
emilmont	10:3bc89ef62ce7	1977	/ / end of group MTBDWT_Register_Masks */
emilmont	10:3bc89ef62ce7	1978
emilmont	10:3bc89ef62ce7	1979
emilmont	10:3bc89ef62ce7	1980	/* MTBDWT - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	1981	/** Peripheral MTBDWT base address */
emilmont	10:3bc89ef62ce7	1982	#define MTBDWT_BASE (0xF0001000u)
emilmont	10:3bc89ef62ce7	1983	/** Peripheral MTBDWT base pointer */
emilmont	10:3bc89ef62ce7	1984	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
emilmont	10:3bc89ef62ce7	1985	/** Array initializer of MTBDWT peripheral base pointers */
emilmont	10:3bc89ef62ce7	1986	#define MTBDWT_BASES { MTBDWT }
emilmont	10:3bc89ef62ce7	1987
emilmont	10:3bc89ef62ce7	1988	/**
emilmont	10:3bc89ef62ce7	1989	* @}
emilmont	10:3bc89ef62ce7	1990	/ / end of group MTBDWT_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	1991
emilmont	10:3bc89ef62ce7	1992
emilmont	10:3bc89ef62ce7	1993	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	1994	-- NV Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1995	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	1996
emilmont	10:3bc89ef62ce7	1997	/**
emilmont	10:3bc89ef62ce7	1998	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
emilmont	10:3bc89ef62ce7	1999	* @{
emilmont	10:3bc89ef62ce7	2000	*/
emilmont	10:3bc89ef62ce7	2001
emilmont	10:3bc89ef62ce7	2002	/** NV - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2003	typedef struct {
emilmont	10:3bc89ef62ce7	2004	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
emilmont	10:3bc89ef62ce7	2005	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
emilmont	10:3bc89ef62ce7	2006	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
emilmont	10:3bc89ef62ce7	2007	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
emilmont	10:3bc89ef62ce7	2008	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
emilmont	10:3bc89ef62ce7	2009	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
emilmont	10:3bc89ef62ce7	2010	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
emilmont	10:3bc89ef62ce7	2011	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
emilmont	10:3bc89ef62ce7	2012	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	2013	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
emilmont	10:3bc89ef62ce7	2014	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
emilmont	10:3bc89ef62ce7	2015	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
emilmont	10:3bc89ef62ce7	2016	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	2017	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
emilmont	10:3bc89ef62ce7	2018	} NV_Type;
emilmont	10:3bc89ef62ce7	2019
emilmont	10:3bc89ef62ce7	2020	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2021	-- NV Register Masks
emilmont	10:3bc89ef62ce7	2022	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2023
emilmont	10:3bc89ef62ce7	2024	/**
emilmont	10:3bc89ef62ce7	2025	* @addtogroup NV_Register_Masks NV Register Masks
emilmont	10:3bc89ef62ce7	2026	* @{
emilmont	10:3bc89ef62ce7	2027	*/
emilmont	10:3bc89ef62ce7	2028
emilmont	10:3bc89ef62ce7	2029	/* BACKKEY3 Bit Fields */
emilmont	10:3bc89ef62ce7	2030	#define NV_BACKKEY3_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2031	#define NV_BACKKEY3_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2032	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
emilmont	10:3bc89ef62ce7	2033	/* BACKKEY2 Bit Fields */
emilmont	10:3bc89ef62ce7	2034	#define NV_BACKKEY2_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2035	#define NV_BACKKEY2_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2036	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
emilmont	10:3bc89ef62ce7	2037	/* BACKKEY1 Bit Fields */
emilmont	10:3bc89ef62ce7	2038	#define NV_BACKKEY1_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2039	#define NV_BACKKEY1_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2040	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
emilmont	10:3bc89ef62ce7	2041	/* BACKKEY0 Bit Fields */
emilmont	10:3bc89ef62ce7	2042	#define NV_BACKKEY0_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2043	#define NV_BACKKEY0_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2044	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
emilmont	10:3bc89ef62ce7	2045	/* BACKKEY7 Bit Fields */
emilmont	10:3bc89ef62ce7	2046	#define NV_BACKKEY7_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2047	#define NV_BACKKEY7_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2048	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
emilmont	10:3bc89ef62ce7	2049	/* BACKKEY6 Bit Fields */
emilmont	10:3bc89ef62ce7	2050	#define NV_BACKKEY6_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2051	#define NV_BACKKEY6_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2052	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
emilmont	10:3bc89ef62ce7	2053	/* BACKKEY5 Bit Fields */
emilmont	10:3bc89ef62ce7	2054	#define NV_BACKKEY5_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2055	#define NV_BACKKEY5_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2056	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
emilmont	10:3bc89ef62ce7	2057	/* BACKKEY4 Bit Fields */
emilmont	10:3bc89ef62ce7	2058	#define NV_BACKKEY4_KEY_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2059	#define NV_BACKKEY4_KEY_SHIFT 0
emilmont	10:3bc89ef62ce7	2060	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
emilmont	10:3bc89ef62ce7	2061	/* FPROT3 Bit Fields */
emilmont	10:3bc89ef62ce7	2062	#define NV_FPROT3_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2063	#define NV_FPROT3_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	2064	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
emilmont	10:3bc89ef62ce7	2065	/* FPROT2 Bit Fields */
emilmont	10:3bc89ef62ce7	2066	#define NV_FPROT2_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2067	#define NV_FPROT2_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	2068	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
emilmont	10:3bc89ef62ce7	2069	/* FPROT1 Bit Fields */
emilmont	10:3bc89ef62ce7	2070	#define NV_FPROT1_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2071	#define NV_FPROT1_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	2072	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
emilmont	10:3bc89ef62ce7	2073	/* FPROT0 Bit Fields */
emilmont	10:3bc89ef62ce7	2074	#define NV_FPROT0_PROT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2075	#define NV_FPROT0_PROT_SHIFT 0
emilmont	10:3bc89ef62ce7	2076	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
emilmont	10:3bc89ef62ce7	2077	/* FSEC Bit Fields */
emilmont	10:3bc89ef62ce7	2078	#define NV_FSEC_SEC_MASK 0x3u
emilmont	10:3bc89ef62ce7	2079	#define NV_FSEC_SEC_SHIFT 0
emilmont	10:3bc89ef62ce7	2080	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
emilmont	10:3bc89ef62ce7	2081	#define NV_FSEC_FSLACC_MASK 0xCu
emilmont	10:3bc89ef62ce7	2082	#define NV_FSEC_FSLACC_SHIFT 2
emilmont	10:3bc89ef62ce7	2083	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
emilmont	10:3bc89ef62ce7	2084	#define NV_FSEC_MEEN_MASK 0x30u
emilmont	10:3bc89ef62ce7	2085	#define NV_FSEC_MEEN_SHIFT 4
emilmont	10:3bc89ef62ce7	2086	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
emilmont	10:3bc89ef62ce7	2087	#define NV_FSEC_KEYEN_MASK 0xC0u
emilmont	10:3bc89ef62ce7	2088	#define NV_FSEC_KEYEN_SHIFT 6
emilmont	10:3bc89ef62ce7	2089	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
emilmont	10:3bc89ef62ce7	2090	/* FOPT Bit Fields */
emilmont	10:3bc89ef62ce7	2091	#define NV_FOPT_LPBOOT0_MASK 0x1u
emilmont	10:3bc89ef62ce7	2092	#define NV_FOPT_LPBOOT0_SHIFT 0
emilmont	10:3bc89ef62ce7	2093	#define NV_FOPT_NMI_DIS_MASK 0x4u
emilmont	10:3bc89ef62ce7	2094	#define NV_FOPT_NMI_DIS_SHIFT 2
emilmont	10:3bc89ef62ce7	2095	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
emilmont	10:3bc89ef62ce7	2096	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
emilmont	10:3bc89ef62ce7	2097	#define NV_FOPT_LPBOOT1_MASK 0x10u
emilmont	10:3bc89ef62ce7	2098	#define NV_FOPT_LPBOOT1_SHIFT 4
emilmont	10:3bc89ef62ce7	2099	#define NV_FOPT_FAST_INIT_MASK 0x20u
emilmont	10:3bc89ef62ce7	2100	#define NV_FOPT_FAST_INIT_SHIFT 5
emilmont	10:3bc89ef62ce7	2101
emilmont	10:3bc89ef62ce7	2102	/**
emilmont	10:3bc89ef62ce7	2103	* @}
emilmont	10:3bc89ef62ce7	2104	/ / end of group NV_Register_Masks */
emilmont	10:3bc89ef62ce7	2105
emilmont	10:3bc89ef62ce7	2106
emilmont	10:3bc89ef62ce7	2107	/* NV - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2108	/** Peripheral FTFA_FlashConfig base address */
emilmont	10:3bc89ef62ce7	2109	#define FTFA_FlashConfig_BASE (0x400u)
emilmont	10:3bc89ef62ce7	2110	/** Peripheral FTFA_FlashConfig base pointer */
emilmont	10:3bc89ef62ce7	2111	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
emilmont	10:3bc89ef62ce7	2112	/** Array initializer of NV peripheral base pointers */
emilmont	10:3bc89ef62ce7	2113	#define NV_BASES { FTFA_FlashConfig }
emilmont	10:3bc89ef62ce7	2114
emilmont	10:3bc89ef62ce7	2115	/**
emilmont	10:3bc89ef62ce7	2116	* @}
emilmont	10:3bc89ef62ce7	2117	/ / end of group NV_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2118
emilmont	10:3bc89ef62ce7	2119
emilmont	10:3bc89ef62ce7	2120	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2121	-- OSC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2122	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2123
emilmont	10:3bc89ef62ce7	2124	/**
emilmont	10:3bc89ef62ce7	2125	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2126	* @{
emilmont	10:3bc89ef62ce7	2127	*/
emilmont	10:3bc89ef62ce7	2128
emilmont	10:3bc89ef62ce7	2129	/** OSC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2130	typedef struct {
emilmont	10:3bc89ef62ce7	2131	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2132	} OSC_Type;
emilmont	10:3bc89ef62ce7	2133
emilmont	10:3bc89ef62ce7	2134	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2135	-- OSC Register Masks
emilmont	10:3bc89ef62ce7	2136	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2137
emilmont	10:3bc89ef62ce7	2138	/**
emilmont	10:3bc89ef62ce7	2139	* @addtogroup OSC_Register_Masks OSC Register Masks
emilmont	10:3bc89ef62ce7	2140	* @{
emilmont	10:3bc89ef62ce7	2141	*/
emilmont	10:3bc89ef62ce7	2142
emilmont	10:3bc89ef62ce7	2143	/* CR Bit Fields */
emilmont	10:3bc89ef62ce7	2144	#define OSC_CR_SC16P_MASK 0x1u
emilmont	10:3bc89ef62ce7	2145	#define OSC_CR_SC16P_SHIFT 0
emilmont	10:3bc89ef62ce7	2146	#define OSC_CR_SC8P_MASK 0x2u
emilmont	10:3bc89ef62ce7	2147	#define OSC_CR_SC8P_SHIFT 1
emilmont	10:3bc89ef62ce7	2148	#define OSC_CR_SC4P_MASK 0x4u
emilmont	10:3bc89ef62ce7	2149	#define OSC_CR_SC4P_SHIFT 2
emilmont	10:3bc89ef62ce7	2150	#define OSC_CR_SC2P_MASK 0x8u
emilmont	10:3bc89ef62ce7	2151	#define OSC_CR_SC2P_SHIFT 3
emilmont	10:3bc89ef62ce7	2152	#define OSC_CR_EREFSTEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	2153	#define OSC_CR_EREFSTEN_SHIFT 5
emilmont	10:3bc89ef62ce7	2154	#define OSC_CR_ERCLKEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	2155	#define OSC_CR_ERCLKEN_SHIFT 7
emilmont	10:3bc89ef62ce7	2156
emilmont	10:3bc89ef62ce7	2157	/**
emilmont	10:3bc89ef62ce7	2158	* @}
emilmont	10:3bc89ef62ce7	2159	/ / end of group OSC_Register_Masks */
emilmont	10:3bc89ef62ce7	2160
emilmont	10:3bc89ef62ce7	2161
emilmont	10:3bc89ef62ce7	2162	/* OSC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2163	/** Peripheral OSC0 base address */
emilmont	10:3bc89ef62ce7	2164	#define OSC0_BASE (0x40065000u)
emilmont	10:3bc89ef62ce7	2165	/** Peripheral OSC0 base pointer */
emilmont	10:3bc89ef62ce7	2166	#define OSC0 ((OSC_Type *)OSC0_BASE)
emilmont	10:3bc89ef62ce7	2167	/** Array initializer of OSC peripheral base pointers */
emilmont	10:3bc89ef62ce7	2168	#define OSC_BASES { OSC0 }
emilmont	10:3bc89ef62ce7	2169
emilmont	10:3bc89ef62ce7	2170	/**
emilmont	10:3bc89ef62ce7	2171	* @}
emilmont	10:3bc89ef62ce7	2172	/ / end of group OSC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2173
emilmont	10:3bc89ef62ce7	2174
emilmont	10:3bc89ef62ce7	2175	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2176	-- PIT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2177	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2178
emilmont	10:3bc89ef62ce7	2179	/**
emilmont	10:3bc89ef62ce7	2180	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2181	* @{
emilmont	10:3bc89ef62ce7	2182	*/
emilmont	10:3bc89ef62ce7	2183
emilmont	10:3bc89ef62ce7	2184	/** PIT - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2185	typedef struct {
emilmont	10:3bc89ef62ce7	2186	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2187	uint8_t RESERVED_0[220];
emilmont	10:3bc89ef62ce7	2188	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
emilmont	10:3bc89ef62ce7	2189	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
emilmont	10:3bc89ef62ce7	2190	uint8_t RESERVED_1[24];
emilmont	10:3bc89ef62ce7	2191	struct { /* offset: 0x100, array step: 0x10 */
emilmont	10:3bc89ef62ce7	2192	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
emilmont	10:3bc89ef62ce7	2193	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
emilmont	10:3bc89ef62ce7	2194	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
emilmont	10:3bc89ef62ce7	2195	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
emilmont	10:3bc89ef62ce7	2196	} CHANNEL[2];
emilmont	10:3bc89ef62ce7	2197	} PIT_Type;
emilmont	10:3bc89ef62ce7	2198
emilmont	10:3bc89ef62ce7	2199	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2200	-- PIT Register Masks
emilmont	10:3bc89ef62ce7	2201	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2202
emilmont	10:3bc89ef62ce7	2203	/**
emilmont	10:3bc89ef62ce7	2204	* @addtogroup PIT_Register_Masks PIT Register Masks
emilmont	10:3bc89ef62ce7	2205	* @{
emilmont	10:3bc89ef62ce7	2206	*/
emilmont	10:3bc89ef62ce7	2207
emilmont	10:3bc89ef62ce7	2208	/* MCR Bit Fields */
emilmont	10:3bc89ef62ce7	2209	#define PIT_MCR_FRZ_MASK 0x1u
emilmont	10:3bc89ef62ce7	2210	#define PIT_MCR_FRZ_SHIFT 0
emilmont	10:3bc89ef62ce7	2211	#define PIT_MCR_MDIS_MASK 0x2u
emilmont	10:3bc89ef62ce7	2212	#define PIT_MCR_MDIS_SHIFT 1
emilmont	10:3bc89ef62ce7	2213	/* LTMR64H Bit Fields */
emilmont	10:3bc89ef62ce7	2214	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2215	#define PIT_LTMR64H_LTH_SHIFT 0
emilmont	10:3bc89ef62ce7	2216	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
emilmont	10:3bc89ef62ce7	2217	/* LTMR64L Bit Fields */
emilmont	10:3bc89ef62ce7	2218	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2219	#define PIT_LTMR64L_LTL_SHIFT 0
emilmont	10:3bc89ef62ce7	2220	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
emilmont	10:3bc89ef62ce7	2221	/* LDVAL Bit Fields */
emilmont	10:3bc89ef62ce7	2222	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2223	#define PIT_LDVAL_TSV_SHIFT 0
emilmont	10:3bc89ef62ce7	2224	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
emilmont	10:3bc89ef62ce7	2225	/* CVAL Bit Fields */
emilmont	10:3bc89ef62ce7	2226	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2227	#define PIT_CVAL_TVL_SHIFT 0
emilmont	10:3bc89ef62ce7	2228	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
emilmont	10:3bc89ef62ce7	2229	/* TCTRL Bit Fields */
emilmont	10:3bc89ef62ce7	2230	#define PIT_TCTRL_TEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	2231	#define PIT_TCTRL_TEN_SHIFT 0
emilmont	10:3bc89ef62ce7	2232	#define PIT_TCTRL_TIE_MASK 0x2u
emilmont	10:3bc89ef62ce7	2233	#define PIT_TCTRL_TIE_SHIFT 1
emilmont	10:3bc89ef62ce7	2234	#define PIT_TCTRL_CHN_MASK 0x4u
emilmont	10:3bc89ef62ce7	2235	#define PIT_TCTRL_CHN_SHIFT 2
emilmont	10:3bc89ef62ce7	2236	/* TFLG Bit Fields */
emilmont	10:3bc89ef62ce7	2237	#define PIT_TFLG_TIF_MASK 0x1u
emilmont	10:3bc89ef62ce7	2238	#define PIT_TFLG_TIF_SHIFT 0
emilmont	10:3bc89ef62ce7	2239
emilmont	10:3bc89ef62ce7	2240	/**
emilmont	10:3bc89ef62ce7	2241	* @}
emilmont	10:3bc89ef62ce7	2242	/ / end of group PIT_Register_Masks */
emilmont	10:3bc89ef62ce7	2243
emilmont	10:3bc89ef62ce7	2244
emilmont	10:3bc89ef62ce7	2245	/* PIT - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2246	/** Peripheral PIT base address */
emilmont	10:3bc89ef62ce7	2247	#define PIT_BASE (0x40037000u)
emilmont	10:3bc89ef62ce7	2248	/** Peripheral PIT base pointer */
emilmont	10:3bc89ef62ce7	2249	#define PIT ((PIT_Type *)PIT_BASE)
emilmont	10:3bc89ef62ce7	2250	/** Array initializer of PIT peripheral base pointers */
emilmont	10:3bc89ef62ce7	2251	#define PIT_BASES { PIT }
emilmont	10:3bc89ef62ce7	2252
emilmont	10:3bc89ef62ce7	2253	/**
emilmont	10:3bc89ef62ce7	2254	* @}
emilmont	10:3bc89ef62ce7	2255	/ / end of group PIT_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2256
emilmont	10:3bc89ef62ce7	2257
emilmont	10:3bc89ef62ce7	2258	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2259	-- PMC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2260	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2261
emilmont	10:3bc89ef62ce7	2262	/**
emilmont	10:3bc89ef62ce7	2263	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2264	* @{
emilmont	10:3bc89ef62ce7	2265	*/
emilmont	10:3bc89ef62ce7	2266
emilmont	10:3bc89ef62ce7	2267	/** PMC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2268	typedef struct {
emilmont	10:3bc89ef62ce7	2269	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2270	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	2271	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	2272	} PMC_Type;
emilmont	10:3bc89ef62ce7	2273
emilmont	10:3bc89ef62ce7	2274	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2275	-- PMC Register Masks
emilmont	10:3bc89ef62ce7	2276	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2277
emilmont	10:3bc89ef62ce7	2278	/**
emilmont	10:3bc89ef62ce7	2279	* @addtogroup PMC_Register_Masks PMC Register Masks
emilmont	10:3bc89ef62ce7	2280	* @{
emilmont	10:3bc89ef62ce7	2281	*/
emilmont	10:3bc89ef62ce7	2282
emilmont	10:3bc89ef62ce7	2283	/* LVDSC1 Bit Fields */
emilmont	10:3bc89ef62ce7	2284	#define PMC_LVDSC1_LVDV_MASK 0x3u
emilmont	10:3bc89ef62ce7	2285	#define PMC_LVDSC1_LVDV_SHIFT 0
emilmont	10:3bc89ef62ce7	2286	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
emilmont	10:3bc89ef62ce7	2287	#define PMC_LVDSC1_LVDRE_MASK 0x10u
emilmont	10:3bc89ef62ce7	2288	#define PMC_LVDSC1_LVDRE_SHIFT 4
emilmont	10:3bc89ef62ce7	2289	#define PMC_LVDSC1_LVDIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	2290	#define PMC_LVDSC1_LVDIE_SHIFT 5
emilmont	10:3bc89ef62ce7	2291	#define PMC_LVDSC1_LVDACK_MASK 0x40u
emilmont	10:3bc89ef62ce7	2292	#define PMC_LVDSC1_LVDACK_SHIFT 6
emilmont	10:3bc89ef62ce7	2293	#define PMC_LVDSC1_LVDF_MASK 0x80u
emilmont	10:3bc89ef62ce7	2294	#define PMC_LVDSC1_LVDF_SHIFT 7
emilmont	10:3bc89ef62ce7	2295	/* LVDSC2 Bit Fields */
emilmont	10:3bc89ef62ce7	2296	#define PMC_LVDSC2_LVWV_MASK 0x3u
emilmont	10:3bc89ef62ce7	2297	#define PMC_LVDSC2_LVWV_SHIFT 0
emilmont	10:3bc89ef62ce7	2298	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
emilmont	10:3bc89ef62ce7	2299	#define PMC_LVDSC2_LVWIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	2300	#define PMC_LVDSC2_LVWIE_SHIFT 5
emilmont	10:3bc89ef62ce7	2301	#define PMC_LVDSC2_LVWACK_MASK 0x40u
emilmont	10:3bc89ef62ce7	2302	#define PMC_LVDSC2_LVWACK_SHIFT 6
emilmont	10:3bc89ef62ce7	2303	#define PMC_LVDSC2_LVWF_MASK 0x80u
emilmont	10:3bc89ef62ce7	2304	#define PMC_LVDSC2_LVWF_SHIFT 7
emilmont	10:3bc89ef62ce7	2305	/* REGSC Bit Fields */
emilmont	10:3bc89ef62ce7	2306	#define PMC_REGSC_BGBE_MASK 0x1u
emilmont	10:3bc89ef62ce7	2307	#define PMC_REGSC_BGBE_SHIFT 0
emilmont	10:3bc89ef62ce7	2308	#define PMC_REGSC_REGONS_MASK 0x4u
emilmont	10:3bc89ef62ce7	2309	#define PMC_REGSC_REGONS_SHIFT 2
emilmont	10:3bc89ef62ce7	2310	#define PMC_REGSC_ACKISO_MASK 0x8u
emilmont	10:3bc89ef62ce7	2311	#define PMC_REGSC_ACKISO_SHIFT 3
emilmont	10:3bc89ef62ce7	2312	#define PMC_REGSC_BGEN_MASK 0x10u
emilmont	10:3bc89ef62ce7	2313	#define PMC_REGSC_BGEN_SHIFT 4
emilmont	10:3bc89ef62ce7	2314
emilmont	10:3bc89ef62ce7	2315	/**
emilmont	10:3bc89ef62ce7	2316	* @}
emilmont	10:3bc89ef62ce7	2317	/ / end of group PMC_Register_Masks */
emilmont	10:3bc89ef62ce7	2318
emilmont	10:3bc89ef62ce7	2319
emilmont	10:3bc89ef62ce7	2320	/* PMC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2321	/** Peripheral PMC base address */
emilmont	10:3bc89ef62ce7	2322	#define PMC_BASE (0x4007D000u)
emilmont	10:3bc89ef62ce7	2323	/** Peripheral PMC base pointer */
emilmont	10:3bc89ef62ce7	2324	#define PMC ((PMC_Type *)PMC_BASE)
emilmont	10:3bc89ef62ce7	2325	/** Array initializer of PMC peripheral base pointers */
emilmont	10:3bc89ef62ce7	2326	#define PMC_BASES { PMC }
emilmont	10:3bc89ef62ce7	2327
emilmont	10:3bc89ef62ce7	2328	/**
emilmont	10:3bc89ef62ce7	2329	* @}
emilmont	10:3bc89ef62ce7	2330	/ / end of group PMC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2331
emilmont	10:3bc89ef62ce7	2332
emilmont	10:3bc89ef62ce7	2333	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2334	-- PORT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2335	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2336
emilmont	10:3bc89ef62ce7	2337	/**
emilmont	10:3bc89ef62ce7	2338	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2339	* @{
emilmont	10:3bc89ef62ce7	2340	*/
emilmont	10:3bc89ef62ce7	2341
emilmont	10:3bc89ef62ce7	2342	/** PORT - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2343	typedef struct {
emilmont	10:3bc89ef62ce7	2344	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	2345	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
emilmont	10:3bc89ef62ce7	2346	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
emilmont	10:3bc89ef62ce7	2347	uint8_t RESERVED_0[24];
emilmont	10:3bc89ef62ce7	2348	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
emilmont	10:3bc89ef62ce7	2349	} PORT_Type;
emilmont	10:3bc89ef62ce7	2350
emilmont	10:3bc89ef62ce7	2351	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2352	-- PORT Register Masks
emilmont	10:3bc89ef62ce7	2353	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2354
emilmont	10:3bc89ef62ce7	2355	/**
emilmont	10:3bc89ef62ce7	2356	* @addtogroup PORT_Register_Masks PORT Register Masks
emilmont	10:3bc89ef62ce7	2357	* @{
emilmont	10:3bc89ef62ce7	2358	*/
emilmont	10:3bc89ef62ce7	2359
emilmont	10:3bc89ef62ce7	2360	/* PCR Bit Fields */
emilmont	10:3bc89ef62ce7	2361	#define PORT_PCR_PS_MASK 0x1u
emilmont	10:3bc89ef62ce7	2362	#define PORT_PCR_PS_SHIFT 0
emilmont	10:3bc89ef62ce7	2363	#define PORT_PCR_PE_MASK 0x2u
emilmont	10:3bc89ef62ce7	2364	#define PORT_PCR_PE_SHIFT 1
emilmont	10:3bc89ef62ce7	2365	#define PORT_PCR_SRE_MASK 0x4u
emilmont	10:3bc89ef62ce7	2366	#define PORT_PCR_SRE_SHIFT 2
emilmont	10:3bc89ef62ce7	2367	#define PORT_PCR_PFE_MASK 0x10u
emilmont	10:3bc89ef62ce7	2368	#define PORT_PCR_PFE_SHIFT 4
emilmont	10:3bc89ef62ce7	2369	#define PORT_PCR_DSE_MASK 0x40u
emilmont	10:3bc89ef62ce7	2370	#define PORT_PCR_DSE_SHIFT 6
emilmont	10:3bc89ef62ce7	2371	#define PORT_PCR_MUX_MASK 0x700u
emilmont	10:3bc89ef62ce7	2372	#define PORT_PCR_MUX_SHIFT 8
emilmont	10:3bc89ef62ce7	2373	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
emilmont	10:3bc89ef62ce7	2374	#define PORT_PCR_IRQC_MASK 0xF0000u
emilmont	10:3bc89ef62ce7	2375	#define PORT_PCR_IRQC_SHIFT 16
emilmont	10:3bc89ef62ce7	2376	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
emilmont	10:3bc89ef62ce7	2377	#define PORT_PCR_ISF_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	2378	#define PORT_PCR_ISF_SHIFT 24
emilmont	10:3bc89ef62ce7	2379	/* GPCLR Bit Fields */
emilmont	10:3bc89ef62ce7	2380	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	2381	#define PORT_GPCLR_GPWD_SHIFT 0
emilmont	10:3bc89ef62ce7	2382	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
emilmont	10:3bc89ef62ce7	2383	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
emilmont	10:3bc89ef62ce7	2384	#define PORT_GPCLR_GPWE_SHIFT 16
emilmont	10:3bc89ef62ce7	2385	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
emilmont	10:3bc89ef62ce7	2386	/* GPCHR Bit Fields */
emilmont	10:3bc89ef62ce7	2387	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	2388	#define PORT_GPCHR_GPWD_SHIFT 0
emilmont	10:3bc89ef62ce7	2389	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
emilmont	10:3bc89ef62ce7	2390	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
emilmont	10:3bc89ef62ce7	2391	#define PORT_GPCHR_GPWE_SHIFT 16
emilmont	10:3bc89ef62ce7	2392	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
emilmont	10:3bc89ef62ce7	2393	/* ISFR Bit Fields */
emilmont	10:3bc89ef62ce7	2394	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2395	#define PORT_ISFR_ISF_SHIFT 0
emilmont	10:3bc89ef62ce7	2396	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
emilmont	10:3bc89ef62ce7	2397
emilmont	10:3bc89ef62ce7	2398	/**
emilmont	10:3bc89ef62ce7	2399	* @}
emilmont	10:3bc89ef62ce7	2400	/ / end of group PORT_Register_Masks */
emilmont	10:3bc89ef62ce7	2401
emilmont	10:3bc89ef62ce7	2402
emilmont	10:3bc89ef62ce7	2403	/* PORT - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2404	/** Peripheral PORTA base address */
emilmont	10:3bc89ef62ce7	2405	#define PORTA_BASE (0x40049000u)
emilmont	10:3bc89ef62ce7	2406	/** Peripheral PORTA base pointer */
emilmont	10:3bc89ef62ce7	2407	#define PORTA ((PORT_Type *)PORTA_BASE)
emilmont	10:3bc89ef62ce7	2408	/** Peripheral PORTB base address */
emilmont	10:3bc89ef62ce7	2409	#define PORTB_BASE (0x4004A000u)
emilmont	10:3bc89ef62ce7	2410	/** Peripheral PORTB base pointer */
emilmont	10:3bc89ef62ce7	2411	#define PORTB ((PORT_Type *)PORTB_BASE)
emilmont	10:3bc89ef62ce7	2412	/** Peripheral PORTC base address */
emilmont	10:3bc89ef62ce7	2413	#define PORTC_BASE (0x4004B000u)
emilmont	10:3bc89ef62ce7	2414	/** Peripheral PORTC base pointer */
emilmont	10:3bc89ef62ce7	2415	#define PORTC ((PORT_Type *)PORTC_BASE)
emilmont	10:3bc89ef62ce7	2416	/** Peripheral PORTD base address */
emilmont	10:3bc89ef62ce7	2417	#define PORTD_BASE (0x4004C000u)
emilmont	10:3bc89ef62ce7	2418	/** Peripheral PORTD base pointer */
emilmont	10:3bc89ef62ce7	2419	#define PORTD ((PORT_Type *)PORTD_BASE)
emilmont	10:3bc89ef62ce7	2420	/** Peripheral PORTE base address */
emilmont	10:3bc89ef62ce7	2421	#define PORTE_BASE (0x4004D000u)
emilmont	10:3bc89ef62ce7	2422	/** Peripheral PORTE base pointer */
emilmont	10:3bc89ef62ce7	2423	#define PORTE ((PORT_Type *)PORTE_BASE)
emilmont	10:3bc89ef62ce7	2424	/** Array initializer of PORT peripheral base pointers */
emilmont	10:3bc89ef62ce7	2425	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
emilmont	10:3bc89ef62ce7	2426
emilmont	10:3bc89ef62ce7	2427	/**
emilmont	10:3bc89ef62ce7	2428	* @}
emilmont	10:3bc89ef62ce7	2429	/ / end of group PORT_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2430
emilmont	10:3bc89ef62ce7	2431
emilmont	10:3bc89ef62ce7	2432	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2433	-- RCM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2434	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2435
emilmont	10:3bc89ef62ce7	2436	/**
emilmont	10:3bc89ef62ce7	2437	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2438	* @{
emilmont	10:3bc89ef62ce7	2439	*/
emilmont	10:3bc89ef62ce7	2440
emilmont	10:3bc89ef62ce7	2441	/** RCM - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2442	typedef struct {
emilmont	10:3bc89ef62ce7	2443	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2444	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
emilmont	10:3bc89ef62ce7	2445	uint8_t RESERVED_0[2];
emilmont	10:3bc89ef62ce7	2446	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	2447	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
emilmont	10:3bc89ef62ce7	2448	} RCM_Type;
emilmont	10:3bc89ef62ce7	2449
emilmont	10:3bc89ef62ce7	2450	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2451	-- RCM Register Masks
emilmont	10:3bc89ef62ce7	2452	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2453
emilmont	10:3bc89ef62ce7	2454	/**
emilmont	10:3bc89ef62ce7	2455	* @addtogroup RCM_Register_Masks RCM Register Masks
emilmont	10:3bc89ef62ce7	2456	* @{
emilmont	10:3bc89ef62ce7	2457	*/
emilmont	10:3bc89ef62ce7	2458
emilmont	10:3bc89ef62ce7	2459	/* SRS0 Bit Fields */
emilmont	10:3bc89ef62ce7	2460	#define RCM_SRS0_WAKEUP_MASK 0x1u
emilmont	10:3bc89ef62ce7	2461	#define RCM_SRS0_WAKEUP_SHIFT 0
emilmont	10:3bc89ef62ce7	2462	#define RCM_SRS0_LVD_MASK 0x2u
emilmont	10:3bc89ef62ce7	2463	#define RCM_SRS0_LVD_SHIFT 1
emilmont	10:3bc89ef62ce7	2464	#define RCM_SRS0_LOC_MASK 0x4u
emilmont	10:3bc89ef62ce7	2465	#define RCM_SRS0_LOC_SHIFT 2
emilmont	10:3bc89ef62ce7	2466	#define RCM_SRS0_LOL_MASK 0x8u
emilmont	10:3bc89ef62ce7	2467	#define RCM_SRS0_LOL_SHIFT 3
emilmont	10:3bc89ef62ce7	2468	#define RCM_SRS0_WDOG_MASK 0x20u
emilmont	10:3bc89ef62ce7	2469	#define RCM_SRS0_WDOG_SHIFT 5
emilmont	10:3bc89ef62ce7	2470	#define RCM_SRS0_PIN_MASK 0x40u
emilmont	10:3bc89ef62ce7	2471	#define RCM_SRS0_PIN_SHIFT 6
emilmont	10:3bc89ef62ce7	2472	#define RCM_SRS0_POR_MASK 0x80u
emilmont	10:3bc89ef62ce7	2473	#define RCM_SRS0_POR_SHIFT 7
emilmont	10:3bc89ef62ce7	2474	/* SRS1 Bit Fields */
emilmont	10:3bc89ef62ce7	2475	#define RCM_SRS1_LOCKUP_MASK 0x2u
emilmont	10:3bc89ef62ce7	2476	#define RCM_SRS1_LOCKUP_SHIFT 1
emilmont	10:3bc89ef62ce7	2477	#define RCM_SRS1_SW_MASK 0x4u
emilmont	10:3bc89ef62ce7	2478	#define RCM_SRS1_SW_SHIFT 2
emilmont	10:3bc89ef62ce7	2479	#define RCM_SRS1_MDM_AP_MASK 0x8u
emilmont	10:3bc89ef62ce7	2480	#define RCM_SRS1_MDM_AP_SHIFT 3
emilmont	10:3bc89ef62ce7	2481	#define RCM_SRS1_SACKERR_MASK 0x20u
emilmont	10:3bc89ef62ce7	2482	#define RCM_SRS1_SACKERR_SHIFT 5
emilmont	10:3bc89ef62ce7	2483	/* RPFC Bit Fields */
emilmont	10:3bc89ef62ce7	2484	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
emilmont	10:3bc89ef62ce7	2485	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
emilmont	10:3bc89ef62ce7	2486	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
emilmont	10:3bc89ef62ce7	2487	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
emilmont	10:3bc89ef62ce7	2488	#define RCM_RPFC_RSTFLTSS_SHIFT 2
emilmont	10:3bc89ef62ce7	2489	/* RPFW Bit Fields */
emilmont	10:3bc89ef62ce7	2490	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	2491	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	2492	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
emilmont	10:3bc89ef62ce7	2493
emilmont	10:3bc89ef62ce7	2494	/**
emilmont	10:3bc89ef62ce7	2495	* @}
emilmont	10:3bc89ef62ce7	2496	/ / end of group RCM_Register_Masks */
emilmont	10:3bc89ef62ce7	2497
emilmont	10:3bc89ef62ce7	2498
emilmont	10:3bc89ef62ce7	2499	/* RCM - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2500	/** Peripheral RCM base address */
emilmont	10:3bc89ef62ce7	2501	#define RCM_BASE (0x4007F000u)
emilmont	10:3bc89ef62ce7	2502	/** Peripheral RCM base pointer */
emilmont	10:3bc89ef62ce7	2503	#define RCM ((RCM_Type *)RCM_BASE)
emilmont	10:3bc89ef62ce7	2504	/** Array initializer of RCM peripheral base pointers */
emilmont	10:3bc89ef62ce7	2505	#define RCM_BASES { RCM }
emilmont	10:3bc89ef62ce7	2506
emilmont	10:3bc89ef62ce7	2507	/**
emilmont	10:3bc89ef62ce7	2508	* @}
emilmont	10:3bc89ef62ce7	2509	/ / end of group RCM_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2510
emilmont	10:3bc89ef62ce7	2511
emilmont	10:3bc89ef62ce7	2512	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2513	-- ROM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2514	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2515
emilmont	10:3bc89ef62ce7	2516	/**
emilmont	10:3bc89ef62ce7	2517	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2518	* @{
emilmont	10:3bc89ef62ce7	2519	*/
emilmont	10:3bc89ef62ce7	2520
emilmont	10:3bc89ef62ce7	2521	/** ROM - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2522	typedef struct {
emilmont	10:3bc89ef62ce7	2523	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	2524	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	2525	uint8_t RESERVED_0[4028];
emilmont	10:3bc89ef62ce7	2526	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
emilmont	10:3bc89ef62ce7	2527	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
emilmont	10:3bc89ef62ce7	2528	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
emilmont	10:3bc89ef62ce7	2529	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
emilmont	10:3bc89ef62ce7	2530	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
emilmont	10:3bc89ef62ce7	2531	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
emilmont	10:3bc89ef62ce7	2532	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
emilmont	10:3bc89ef62ce7	2533	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
emilmont	10:3bc89ef62ce7	2534	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
emilmont	10:3bc89ef62ce7	2535	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	2536	} ROM_Type;
emilmont	10:3bc89ef62ce7	2537
emilmont	10:3bc89ef62ce7	2538	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2539	-- ROM Register Masks
emilmont	10:3bc89ef62ce7	2540	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2541
emilmont	10:3bc89ef62ce7	2542	/**
emilmont	10:3bc89ef62ce7	2543	* @addtogroup ROM_Register_Masks ROM Register Masks
emilmont	10:3bc89ef62ce7	2544	* @{
emilmont	10:3bc89ef62ce7	2545	*/
emilmont	10:3bc89ef62ce7	2546
emilmont	10:3bc89ef62ce7	2547	/* ENTRY Bit Fields */
emilmont	10:3bc89ef62ce7	2548	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2549	#define ROM_ENTRY_ENTRY_SHIFT 0
emilmont	10:3bc89ef62ce7	2550	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
emilmont	10:3bc89ef62ce7	2551	/* TABLEMARK Bit Fields */
emilmont	10:3bc89ef62ce7	2552	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2553	#define ROM_TABLEMARK_MARK_SHIFT 0
emilmont	10:3bc89ef62ce7	2554	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
emilmont	10:3bc89ef62ce7	2555	/* SYSACCESS Bit Fields */
emilmont	10:3bc89ef62ce7	2556	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2557	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
emilmont	10:3bc89ef62ce7	2558	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
emilmont	10:3bc89ef62ce7	2559	/* PERIPHID4 Bit Fields */
emilmont	10:3bc89ef62ce7	2560	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2561	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2562	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2563	/* PERIPHID5 Bit Fields */
emilmont	10:3bc89ef62ce7	2564	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2565	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2566	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2567	/* PERIPHID6 Bit Fields */
emilmont	10:3bc89ef62ce7	2568	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2569	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2570	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2571	/* PERIPHID7 Bit Fields */
emilmont	10:3bc89ef62ce7	2572	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2573	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2574	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2575	/* PERIPHID0 Bit Fields */
emilmont	10:3bc89ef62ce7	2576	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2577	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2578	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2579	/* PERIPHID1 Bit Fields */
emilmont	10:3bc89ef62ce7	2580	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2581	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2582	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2583	/* PERIPHID2 Bit Fields */
emilmont	10:3bc89ef62ce7	2584	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2585	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2586	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2587	/* PERIPHID3 Bit Fields */
emilmont	10:3bc89ef62ce7	2588	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2589	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
emilmont	10:3bc89ef62ce7	2590	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
emilmont	10:3bc89ef62ce7	2591	/* COMPID Bit Fields */
emilmont	10:3bc89ef62ce7	2592	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2593	#define ROM_COMPID_COMPID_SHIFT 0
emilmont	10:3bc89ef62ce7	2594	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
emilmont	10:3bc89ef62ce7	2595
emilmont	10:3bc89ef62ce7	2596	/**
emilmont	10:3bc89ef62ce7	2597	* @}
emilmont	10:3bc89ef62ce7	2598	/ / end of group ROM_Register_Masks */
emilmont	10:3bc89ef62ce7	2599
emilmont	10:3bc89ef62ce7	2600
emilmont	10:3bc89ef62ce7	2601	/* ROM - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2602	/** Peripheral ROM base address */
emilmont	10:3bc89ef62ce7	2603	#define ROM_BASE (0xF0002000u)
emilmont	10:3bc89ef62ce7	2604	/** Peripheral ROM base pointer */
emilmont	10:3bc89ef62ce7	2605	#define ROM ((ROM_Type *)ROM_BASE)
emilmont	10:3bc89ef62ce7	2606	/** Array initializer of ROM peripheral base pointers */
emilmont	10:3bc89ef62ce7	2607	#define ROM_BASES { ROM }
emilmont	10:3bc89ef62ce7	2608
emilmont	10:3bc89ef62ce7	2609	/**
emilmont	10:3bc89ef62ce7	2610	* @}
emilmont	10:3bc89ef62ce7	2611	/ / end of group ROM_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2612
emilmont	10:3bc89ef62ce7	2613
emilmont	10:3bc89ef62ce7	2614	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2615	-- RTC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2616	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2617
emilmont	10:3bc89ef62ce7	2618	/**
emilmont	10:3bc89ef62ce7	2619	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2620	* @{
emilmont	10:3bc89ef62ce7	2621	*/
emilmont	10:3bc89ef62ce7	2622
emilmont	10:3bc89ef62ce7	2623	/** RTC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2624	typedef struct {
emilmont	10:3bc89ef62ce7	2625	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2626	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	2627	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	2628	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
emilmont	10:3bc89ef62ce7	2629	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
emilmont	10:3bc89ef62ce7	2630	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
emilmont	10:3bc89ef62ce7	2631	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
emilmont	10:3bc89ef62ce7	2632	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
emilmont	10:3bc89ef62ce7	2633	} RTC_Type;
emilmont	10:3bc89ef62ce7	2634
emilmont	10:3bc89ef62ce7	2635	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2636	-- RTC Register Masks
emilmont	10:3bc89ef62ce7	2637	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2638
emilmont	10:3bc89ef62ce7	2639	/**
emilmont	10:3bc89ef62ce7	2640	* @addtogroup RTC_Register_Masks RTC Register Masks
emilmont	10:3bc89ef62ce7	2641	* @{
emilmont	10:3bc89ef62ce7	2642	*/
emilmont	10:3bc89ef62ce7	2643
emilmont	10:3bc89ef62ce7	2644	/* TSR Bit Fields */
emilmont	10:3bc89ef62ce7	2645	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2646	#define RTC_TSR_TSR_SHIFT 0
emilmont	10:3bc89ef62ce7	2647	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
emilmont	10:3bc89ef62ce7	2648	/* TPR Bit Fields */
emilmont	10:3bc89ef62ce7	2649	#define RTC_TPR_TPR_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	2650	#define RTC_TPR_TPR_SHIFT 0
emilmont	10:3bc89ef62ce7	2651	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
emilmont	10:3bc89ef62ce7	2652	/* TAR Bit Fields */
emilmont	10:3bc89ef62ce7	2653	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2654	#define RTC_TAR_TAR_SHIFT 0
emilmont	10:3bc89ef62ce7	2655	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
emilmont	10:3bc89ef62ce7	2656	/* TCR Bit Fields */
emilmont	10:3bc89ef62ce7	2657	#define RTC_TCR_TCR_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2658	#define RTC_TCR_TCR_SHIFT 0
emilmont	10:3bc89ef62ce7	2659	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
emilmont	10:3bc89ef62ce7	2660	#define RTC_TCR_CIR_MASK 0xFF00u
emilmont	10:3bc89ef62ce7	2661	#define RTC_TCR_CIR_SHIFT 8
emilmont	10:3bc89ef62ce7	2662	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
emilmont	10:3bc89ef62ce7	2663	#define RTC_TCR_TCV_MASK 0xFF0000u
emilmont	10:3bc89ef62ce7	2664	#define RTC_TCR_TCV_SHIFT 16
emilmont	10:3bc89ef62ce7	2665	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
emilmont	10:3bc89ef62ce7	2666	#define RTC_TCR_CIC_MASK 0xFF000000u
emilmont	10:3bc89ef62ce7	2667	#define RTC_TCR_CIC_SHIFT 24
emilmont	10:3bc89ef62ce7	2668	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
emilmont	10:3bc89ef62ce7	2669	/* CR Bit Fields */
emilmont	10:3bc89ef62ce7	2670	#define RTC_CR_SWR_MASK 0x1u
emilmont	10:3bc89ef62ce7	2671	#define RTC_CR_SWR_SHIFT 0
emilmont	10:3bc89ef62ce7	2672	#define RTC_CR_WPE_MASK 0x2u
emilmont	10:3bc89ef62ce7	2673	#define RTC_CR_WPE_SHIFT 1
emilmont	10:3bc89ef62ce7	2674	#define RTC_CR_SUP_MASK 0x4u
emilmont	10:3bc89ef62ce7	2675	#define RTC_CR_SUP_SHIFT 2
emilmont	10:3bc89ef62ce7	2676	#define RTC_CR_UM_MASK 0x8u
emilmont	10:3bc89ef62ce7	2677	#define RTC_CR_UM_SHIFT 3
emilmont	10:3bc89ef62ce7	2678	#define RTC_CR_OSCE_MASK 0x100u
emilmont	10:3bc89ef62ce7	2679	#define RTC_CR_OSCE_SHIFT 8
emilmont	10:3bc89ef62ce7	2680	#define RTC_CR_CLKO_MASK 0x200u
emilmont	10:3bc89ef62ce7	2681	#define RTC_CR_CLKO_SHIFT 9
emilmont	10:3bc89ef62ce7	2682	#define RTC_CR_SC16P_MASK 0x400u
emilmont	10:3bc89ef62ce7	2683	#define RTC_CR_SC16P_SHIFT 10
emilmont	10:3bc89ef62ce7	2684	#define RTC_CR_SC8P_MASK 0x800u
emilmont	10:3bc89ef62ce7	2685	#define RTC_CR_SC8P_SHIFT 11
emilmont	10:3bc89ef62ce7	2686	#define RTC_CR_SC4P_MASK 0x1000u
emilmont	10:3bc89ef62ce7	2687	#define RTC_CR_SC4P_SHIFT 12
emilmont	10:3bc89ef62ce7	2688	#define RTC_CR_SC2P_MASK 0x2000u
emilmont	10:3bc89ef62ce7	2689	#define RTC_CR_SC2P_SHIFT 13
emilmont	10:3bc89ef62ce7	2690	/* SR Bit Fields */
emilmont	10:3bc89ef62ce7	2691	#define RTC_SR_TIF_MASK 0x1u
emilmont	10:3bc89ef62ce7	2692	#define RTC_SR_TIF_SHIFT 0
emilmont	10:3bc89ef62ce7	2693	#define RTC_SR_TOF_MASK 0x2u
emilmont	10:3bc89ef62ce7	2694	#define RTC_SR_TOF_SHIFT 1
emilmont	10:3bc89ef62ce7	2695	#define RTC_SR_TAF_MASK 0x4u
emilmont	10:3bc89ef62ce7	2696	#define RTC_SR_TAF_SHIFT 2
emilmont	10:3bc89ef62ce7	2697	#define RTC_SR_TCE_MASK 0x10u
emilmont	10:3bc89ef62ce7	2698	#define RTC_SR_TCE_SHIFT 4
emilmont	10:3bc89ef62ce7	2699	/* LR Bit Fields */
emilmont	10:3bc89ef62ce7	2700	#define RTC_LR_TCL_MASK 0x8u
emilmont	10:3bc89ef62ce7	2701	#define RTC_LR_TCL_SHIFT 3
emilmont	10:3bc89ef62ce7	2702	#define RTC_LR_CRL_MASK 0x10u
emilmont	10:3bc89ef62ce7	2703	#define RTC_LR_CRL_SHIFT 4
emilmont	10:3bc89ef62ce7	2704	#define RTC_LR_SRL_MASK 0x20u
emilmont	10:3bc89ef62ce7	2705	#define RTC_LR_SRL_SHIFT 5
emilmont	10:3bc89ef62ce7	2706	#define RTC_LR_LRL_MASK 0x40u
emilmont	10:3bc89ef62ce7	2707	#define RTC_LR_LRL_SHIFT 6
emilmont	10:3bc89ef62ce7	2708	/* IER Bit Fields */
emilmont	10:3bc89ef62ce7	2709	#define RTC_IER_TIIE_MASK 0x1u
emilmont	10:3bc89ef62ce7	2710	#define RTC_IER_TIIE_SHIFT 0
emilmont	10:3bc89ef62ce7	2711	#define RTC_IER_TOIE_MASK 0x2u
emilmont	10:3bc89ef62ce7	2712	#define RTC_IER_TOIE_SHIFT 1
emilmont	10:3bc89ef62ce7	2713	#define RTC_IER_TAIE_MASK 0x4u
emilmont	10:3bc89ef62ce7	2714	#define RTC_IER_TAIE_SHIFT 2
emilmont	10:3bc89ef62ce7	2715	#define RTC_IER_TSIE_MASK 0x10u
emilmont	10:3bc89ef62ce7	2716	#define RTC_IER_TSIE_SHIFT 4
emilmont	10:3bc89ef62ce7	2717	#define RTC_IER_WPON_MASK 0x80u
emilmont	10:3bc89ef62ce7	2718	#define RTC_IER_WPON_SHIFT 7
emilmont	10:3bc89ef62ce7	2719
emilmont	10:3bc89ef62ce7	2720	/**
emilmont	10:3bc89ef62ce7	2721	* @}
emilmont	10:3bc89ef62ce7	2722	/ / end of group RTC_Register_Masks */
emilmont	10:3bc89ef62ce7	2723
emilmont	10:3bc89ef62ce7	2724
emilmont	10:3bc89ef62ce7	2725	/* RTC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2726	/** Peripheral RTC base address */
emilmont	10:3bc89ef62ce7	2727	#define RTC_BASE (0x4003D000u)
emilmont	10:3bc89ef62ce7	2728	/** Peripheral RTC base pointer */
emilmont	10:3bc89ef62ce7	2729	#define RTC ((RTC_Type *)RTC_BASE)
emilmont	10:3bc89ef62ce7	2730	/** Array initializer of RTC peripheral base pointers */
emilmont	10:3bc89ef62ce7	2731	#define RTC_BASES { RTC }
emilmont	10:3bc89ef62ce7	2732
emilmont	10:3bc89ef62ce7	2733	/**
emilmont	10:3bc89ef62ce7	2734	* @}
emilmont	10:3bc89ef62ce7	2735	/ / end of group RTC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2736
emilmont	10:3bc89ef62ce7	2737
emilmont	10:3bc89ef62ce7	2738	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2739	-- SIM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2740	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2741
emilmont	10:3bc89ef62ce7	2742	/**
emilmont	10:3bc89ef62ce7	2743	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2744	* @{
emilmont	10:3bc89ef62ce7	2745	*/
emilmont	10:3bc89ef62ce7	2746
emilmont	10:3bc89ef62ce7	2747	/** SIM - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	2748	typedef struct {
emilmont	10:3bc89ef62ce7	2749	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
emilmont	10:3bc89ef62ce7	2750	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	2751	uint8_t RESERVED_0[4092];
emilmont	10:3bc89ef62ce7	2752	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
emilmont	10:3bc89ef62ce7	2753	uint8_t RESERVED_1[4];
emilmont	10:3bc89ef62ce7	2754	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
emilmont	10:3bc89ef62ce7	2755	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
emilmont	10:3bc89ef62ce7	2756	uint8_t RESERVED_2[4];
emilmont	10:3bc89ef62ce7	2757	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
emilmont	10:3bc89ef62ce7	2758	uint8_t RESERVED_3[8];
emilmont	10:3bc89ef62ce7	2759	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
emilmont	10:3bc89ef62ce7	2760	uint8_t RESERVED_4[12];
emilmont	10:3bc89ef62ce7	2761	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
emilmont	10:3bc89ef62ce7	2762	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
emilmont	10:3bc89ef62ce7	2763	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
emilmont	10:3bc89ef62ce7	2764	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
emilmont	10:3bc89ef62ce7	2765	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
emilmont	10:3bc89ef62ce7	2766	uint8_t RESERVED_5[4];
emilmont	10:3bc89ef62ce7	2767	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
emilmont	10:3bc89ef62ce7	2768	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
emilmont	10:3bc89ef62ce7	2769	uint8_t RESERVED_6[4];
emilmont	10:3bc89ef62ce7	2770	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
emilmont	10:3bc89ef62ce7	2771	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
emilmont	10:3bc89ef62ce7	2772	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
emilmont	10:3bc89ef62ce7	2773	uint8_t RESERVED_7[156];
emilmont	10:3bc89ef62ce7	2774	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
emilmont	10:3bc89ef62ce7	2775	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
emilmont	10:3bc89ef62ce7	2776	} SIM_Type;
emilmont	10:3bc89ef62ce7	2777
emilmont	10:3bc89ef62ce7	2778	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2779	-- SIM Register Masks
emilmont	10:3bc89ef62ce7	2780	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2781
emilmont	10:3bc89ef62ce7	2782	/**
emilmont	10:3bc89ef62ce7	2783	* @addtogroup SIM_Register_Masks SIM Register Masks
emilmont	10:3bc89ef62ce7	2784	* @{
emilmont	10:3bc89ef62ce7	2785	*/
emilmont	10:3bc89ef62ce7	2786
emilmont	10:3bc89ef62ce7	2787	/* SOPT1 Bit Fields */
emilmont	10:3bc89ef62ce7	2788	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
emilmont	10:3bc89ef62ce7	2789	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
emilmont	10:3bc89ef62ce7	2790	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
emilmont	10:3bc89ef62ce7	2791	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
emilmont	10:3bc89ef62ce7	2792	#define SIM_SOPT1_USBVSTBY_SHIFT 29
emilmont	10:3bc89ef62ce7	2793	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
emilmont	10:3bc89ef62ce7	2794	#define SIM_SOPT1_USBSSTBY_SHIFT 30
emilmont	10:3bc89ef62ce7	2795	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
emilmont	10:3bc89ef62ce7	2796	#define SIM_SOPT1_USBREGEN_SHIFT 31
emilmont	10:3bc89ef62ce7	2797	/* SOPT1CFG Bit Fields */
emilmont	10:3bc89ef62ce7	2798	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	2799	#define SIM_SOPT1CFG_URWE_SHIFT 24
emilmont	10:3bc89ef62ce7	2800	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
emilmont	10:3bc89ef62ce7	2801	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
emilmont	10:3bc89ef62ce7	2802	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
emilmont	10:3bc89ef62ce7	2803	#define SIM_SOPT1CFG_USSWE_SHIFT 26
emilmont	10:3bc89ef62ce7	2804	/* SOPT2 Bit Fields */
emilmont	10:3bc89ef62ce7	2805	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
emilmont	10:3bc89ef62ce7	2806	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
emilmont	10:3bc89ef62ce7	2807	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
emilmont	10:3bc89ef62ce7	2808	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
emilmont	10:3bc89ef62ce7	2809	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
emilmont	10:3bc89ef62ce7	2810	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
emilmont	10:3bc89ef62ce7	2811	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
emilmont	10:3bc89ef62ce7	2812	#define SIM_SOPT2_USBSRC_MASK 0x40000u
emilmont	10:3bc89ef62ce7	2813	#define SIM_SOPT2_USBSRC_SHIFT 18
emilmont	10:3bc89ef62ce7	2814	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
emilmont	10:3bc89ef62ce7	2815	#define SIM_SOPT2_TPMSRC_SHIFT 24
emilmont	10:3bc89ef62ce7	2816	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
emilmont	10:3bc89ef62ce7	2817	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
emilmont	10:3bc89ef62ce7	2818	#define SIM_SOPT2_UART0SRC_SHIFT 26
emilmont	10:3bc89ef62ce7	2819	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
emilmont	10:3bc89ef62ce7	2820	/* SOPT4 Bit Fields */
emilmont	10:3bc89ef62ce7	2821	#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
emilmont	10:3bc89ef62ce7	2822	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
emilmont	10:3bc89ef62ce7	2823	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
emilmont	10:3bc89ef62ce7	2824	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
emilmont	10:3bc89ef62ce7	2825	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	2826	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
emilmont	10:3bc89ef62ce7	2827	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
emilmont	10:3bc89ef62ce7	2828	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
emilmont	10:3bc89ef62ce7	2829	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
emilmont	10:3bc89ef62ce7	2830	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
emilmont	10:3bc89ef62ce7	2831	/* SOPT5 Bit Fields */
emilmont	10:3bc89ef62ce7	2832	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
emilmont	10:3bc89ef62ce7	2833	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
emilmont	10:3bc89ef62ce7	2834	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
emilmont	10:3bc89ef62ce7	2835	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
emilmont	10:3bc89ef62ce7	2836	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
emilmont	10:3bc89ef62ce7	2837	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
emilmont	10:3bc89ef62ce7	2838	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
emilmont	10:3bc89ef62ce7	2839	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
emilmont	10:3bc89ef62ce7	2840	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
emilmont	10:3bc89ef62ce7	2841	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
emilmont	10:3bc89ef62ce7	2842	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
emilmont	10:3bc89ef62ce7	2843	#define SIM_SOPT5_UART0ODE_SHIFT 16
emilmont	10:3bc89ef62ce7	2844	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
emilmont	10:3bc89ef62ce7	2845	#define SIM_SOPT5_UART1ODE_SHIFT 17
emilmont	10:3bc89ef62ce7	2846	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
emilmont	10:3bc89ef62ce7	2847	#define SIM_SOPT5_UART2ODE_SHIFT 18
emilmont	10:3bc89ef62ce7	2848	/* SOPT7 Bit Fields */
emilmont	10:3bc89ef62ce7	2849	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
emilmont	10:3bc89ef62ce7	2850	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
emilmont	10:3bc89ef62ce7	2851	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
emilmont	10:3bc89ef62ce7	2852	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
emilmont	10:3bc89ef62ce7	2853	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
emilmont	10:3bc89ef62ce7	2854	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	2855	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
emilmont	10:3bc89ef62ce7	2856	/* SDID Bit Fields */
emilmont	10:3bc89ef62ce7	2857	#define SIM_SDID_PINID_MASK 0xFu
emilmont	10:3bc89ef62ce7	2858	#define SIM_SDID_PINID_SHIFT 0
emilmont	10:3bc89ef62ce7	2859	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
emilmont	10:3bc89ef62ce7	2860	#define SIM_SDID_DIEID_MASK 0xF80u
emilmont	10:3bc89ef62ce7	2861	#define SIM_SDID_DIEID_SHIFT 7
emilmont	10:3bc89ef62ce7	2862	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
emilmont	10:3bc89ef62ce7	2863	#define SIM_SDID_REVID_MASK 0xF000u
emilmont	10:3bc89ef62ce7	2864	#define SIM_SDID_REVID_SHIFT 12
emilmont	10:3bc89ef62ce7	2865	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
emilmont	10:3bc89ef62ce7	2866	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
emilmont	10:3bc89ef62ce7	2867	#define SIM_SDID_SRAMSIZE_SHIFT 16
emilmont	10:3bc89ef62ce7	2868	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
emilmont	10:3bc89ef62ce7	2869	#define SIM_SDID_SERIESID_MASK 0xF00000u
emilmont	10:3bc89ef62ce7	2870	#define SIM_SDID_SERIESID_SHIFT 20
emilmont	10:3bc89ef62ce7	2871	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
emilmont	10:3bc89ef62ce7	2872	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
emilmont	10:3bc89ef62ce7	2873	#define SIM_SDID_SUBFAMID_SHIFT 24
emilmont	10:3bc89ef62ce7	2874	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
emilmont	10:3bc89ef62ce7	2875	#define SIM_SDID_FAMID_MASK 0xF0000000u
emilmont	10:3bc89ef62ce7	2876	#define SIM_SDID_FAMID_SHIFT 28
emilmont	10:3bc89ef62ce7	2877	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
emilmont	10:3bc89ef62ce7	2878	/* SCGC4 Bit Fields */
emilmont	10:3bc89ef62ce7	2879	#define SIM_SCGC4_I2C0_MASK 0x40u
emilmont	10:3bc89ef62ce7	2880	#define SIM_SCGC4_I2C0_SHIFT 6
emilmont	10:3bc89ef62ce7	2881	#define SIM_SCGC4_I2C1_MASK 0x80u
emilmont	10:3bc89ef62ce7	2882	#define SIM_SCGC4_I2C1_SHIFT 7
emilmont	10:3bc89ef62ce7	2883	#define SIM_SCGC4_UART0_MASK 0x400u
emilmont	10:3bc89ef62ce7	2884	#define SIM_SCGC4_UART0_SHIFT 10
emilmont	10:3bc89ef62ce7	2885	#define SIM_SCGC4_UART1_MASK 0x800u
emilmont	10:3bc89ef62ce7	2886	#define SIM_SCGC4_UART1_SHIFT 11
emilmont	10:3bc89ef62ce7	2887	#define SIM_SCGC4_UART2_MASK 0x1000u
emilmont	10:3bc89ef62ce7	2888	#define SIM_SCGC4_UART2_SHIFT 12
emilmont	10:3bc89ef62ce7	2889	#define SIM_SCGC4_USBOTG_MASK 0x40000u
emilmont	10:3bc89ef62ce7	2890	#define SIM_SCGC4_USBOTG_SHIFT 18
emilmont	10:3bc89ef62ce7	2891	#define SIM_SCGC4_CMP_MASK 0x80000u
emilmont	10:3bc89ef62ce7	2892	#define SIM_SCGC4_CMP_SHIFT 19
emilmont	10:3bc89ef62ce7	2893	#define SIM_SCGC4_SPI0_MASK 0x400000u
emilmont	10:3bc89ef62ce7	2894	#define SIM_SCGC4_SPI0_SHIFT 22
emilmont	10:3bc89ef62ce7	2895	#define SIM_SCGC4_SPI1_MASK 0x800000u
emilmont	10:3bc89ef62ce7	2896	#define SIM_SCGC4_SPI1_SHIFT 23
emilmont	10:3bc89ef62ce7	2897	/* SCGC5 Bit Fields */
emilmont	10:3bc89ef62ce7	2898	#define SIM_SCGC5_LPTMR_MASK 0x1u
emilmont	10:3bc89ef62ce7	2899	#define SIM_SCGC5_LPTMR_SHIFT 0
emilmont	10:3bc89ef62ce7	2900	#define SIM_SCGC5_TSI_MASK 0x20u
emilmont	10:3bc89ef62ce7	2901	#define SIM_SCGC5_TSI_SHIFT 5
emilmont	10:3bc89ef62ce7	2902	#define SIM_SCGC5_PORTA_MASK 0x200u
emilmont	10:3bc89ef62ce7	2903	#define SIM_SCGC5_PORTA_SHIFT 9
emilmont	10:3bc89ef62ce7	2904	#define SIM_SCGC5_PORTB_MASK 0x400u
emilmont	10:3bc89ef62ce7	2905	#define SIM_SCGC5_PORTB_SHIFT 10
emilmont	10:3bc89ef62ce7	2906	#define SIM_SCGC5_PORTC_MASK 0x800u
emilmont	10:3bc89ef62ce7	2907	#define SIM_SCGC5_PORTC_SHIFT 11
emilmont	10:3bc89ef62ce7	2908	#define SIM_SCGC5_PORTD_MASK 0x1000u
emilmont	10:3bc89ef62ce7	2909	#define SIM_SCGC5_PORTD_SHIFT 12
emilmont	10:3bc89ef62ce7	2910	#define SIM_SCGC5_PORTE_MASK 0x2000u
emilmont	10:3bc89ef62ce7	2911	#define SIM_SCGC5_PORTE_SHIFT 13
emilmont	10:3bc89ef62ce7	2912	/* SCGC6 Bit Fields */
emilmont	10:3bc89ef62ce7	2913	#define SIM_SCGC6_FTF_MASK 0x1u
emilmont	10:3bc89ef62ce7	2914	#define SIM_SCGC6_FTF_SHIFT 0
emilmont	10:3bc89ef62ce7	2915	#define SIM_SCGC6_DMAMUX_MASK 0x2u
emilmont	10:3bc89ef62ce7	2916	#define SIM_SCGC6_DMAMUX_SHIFT 1
emilmont	10:3bc89ef62ce7	2917	#define SIM_SCGC6_PIT_MASK 0x800000u
emilmont	10:3bc89ef62ce7	2918	#define SIM_SCGC6_PIT_SHIFT 23
emilmont	10:3bc89ef62ce7	2919	#define SIM_SCGC6_TPM0_MASK 0x1000000u
emilmont	10:3bc89ef62ce7	2920	#define SIM_SCGC6_TPM0_SHIFT 24
emilmont	10:3bc89ef62ce7	2921	#define SIM_SCGC6_TPM1_MASK 0x2000000u
emilmont	10:3bc89ef62ce7	2922	#define SIM_SCGC6_TPM1_SHIFT 25
emilmont	10:3bc89ef62ce7	2923	#define SIM_SCGC6_TPM2_MASK 0x4000000u
emilmont	10:3bc89ef62ce7	2924	#define SIM_SCGC6_TPM2_SHIFT 26
emilmont	10:3bc89ef62ce7	2925	#define SIM_SCGC6_ADC0_MASK 0x8000000u
emilmont	10:3bc89ef62ce7	2926	#define SIM_SCGC6_ADC0_SHIFT 27
emilmont	10:3bc89ef62ce7	2927	#define SIM_SCGC6_RTC_MASK 0x20000000u
emilmont	10:3bc89ef62ce7	2928	#define SIM_SCGC6_RTC_SHIFT 29
emilmont	10:3bc89ef62ce7	2929	#define SIM_SCGC6_DAC0_MASK 0x80000000u
emilmont	10:3bc89ef62ce7	2930	#define SIM_SCGC6_DAC0_SHIFT 31
emilmont	10:3bc89ef62ce7	2931	/* SCGC7 Bit Fields */
emilmont	10:3bc89ef62ce7	2932	#define SIM_SCGC7_DMA_MASK 0x100u
emilmont	10:3bc89ef62ce7	2933	#define SIM_SCGC7_DMA_SHIFT 8
emilmont	10:3bc89ef62ce7	2934	/* CLKDIV1 Bit Fields */
emilmont	10:3bc89ef62ce7	2935	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
emilmont	10:3bc89ef62ce7	2936	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
emilmont	10:3bc89ef62ce7	2937	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
emilmont	10:3bc89ef62ce7	2938	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
emilmont	10:3bc89ef62ce7	2939	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
emilmont	10:3bc89ef62ce7	2940	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
emilmont	10:3bc89ef62ce7	2941	/* FCFG1 Bit Fields */
emilmont	10:3bc89ef62ce7	2942	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
emilmont	10:3bc89ef62ce7	2943	#define SIM_FCFG1_FLASHDIS_SHIFT 0
emilmont	10:3bc89ef62ce7	2944	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
emilmont	10:3bc89ef62ce7	2945	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
emilmont	10:3bc89ef62ce7	2946	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
emilmont	10:3bc89ef62ce7	2947	#define SIM_FCFG1_PFSIZE_SHIFT 24
emilmont	10:3bc89ef62ce7	2948	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
emilmont	10:3bc89ef62ce7	2949	/* FCFG2 Bit Fields */
emilmont	10:3bc89ef62ce7	2950	#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
emilmont	10:3bc89ef62ce7	2951	#define SIM_FCFG2_MAXADDR_SHIFT 24
emilmont	10:3bc89ef62ce7	2952	#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
emilmont	10:3bc89ef62ce7	2953	/* UIDMH Bit Fields */
emilmont	10:3bc89ef62ce7	2954	#define SIM_UIDMH_UID_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	2955	#define SIM_UIDMH_UID_SHIFT 0
emilmont	10:3bc89ef62ce7	2956	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
emilmont	10:3bc89ef62ce7	2957	/* UIDML Bit Fields */
emilmont	10:3bc89ef62ce7	2958	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2959	#define SIM_UIDML_UID_SHIFT 0
emilmont	10:3bc89ef62ce7	2960	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
emilmont	10:3bc89ef62ce7	2961	/* UIDL Bit Fields */
emilmont	10:3bc89ef62ce7	2962	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
emilmont	10:3bc89ef62ce7	2963	#define SIM_UIDL_UID_SHIFT 0
emilmont	10:3bc89ef62ce7	2964	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
emilmont	10:3bc89ef62ce7	2965	/* COPC Bit Fields */
emilmont	10:3bc89ef62ce7	2966	#define SIM_COPC_COPW_MASK 0x1u
emilmont	10:3bc89ef62ce7	2967	#define SIM_COPC_COPW_SHIFT 0
emilmont	10:3bc89ef62ce7	2968	#define SIM_COPC_COPCLKS_MASK 0x2u
emilmont	10:3bc89ef62ce7	2969	#define SIM_COPC_COPCLKS_SHIFT 1
emilmont	10:3bc89ef62ce7	2970	#define SIM_COPC_COPT_MASK 0xCu
emilmont	10:3bc89ef62ce7	2971	#define SIM_COPC_COPT_SHIFT 2
emilmont	10:3bc89ef62ce7	2972	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
emilmont	10:3bc89ef62ce7	2973	/* SRVCOP Bit Fields */
emilmont	10:3bc89ef62ce7	2974	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
emilmont	10:3bc89ef62ce7	2975	#define SIM_SRVCOP_SRVCOP_SHIFT 0
emilmont	10:3bc89ef62ce7	2976	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
emilmont	10:3bc89ef62ce7	2977
emilmont	10:3bc89ef62ce7	2978	/**
emilmont	10:3bc89ef62ce7	2979	* @}
emilmont	10:3bc89ef62ce7	2980	/ / end of group SIM_Register_Masks */
emilmont	10:3bc89ef62ce7	2981
emilmont	10:3bc89ef62ce7	2982
emilmont	10:3bc89ef62ce7	2983	/* SIM - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	2984	/** Peripheral SIM base address */
emilmont	10:3bc89ef62ce7	2985	#define SIM_BASE (0x40047000u)
emilmont	10:3bc89ef62ce7	2986	/** Peripheral SIM base pointer */
emilmont	10:3bc89ef62ce7	2987	#define SIM ((SIM_Type *)SIM_BASE)
emilmont	10:3bc89ef62ce7	2988	/** Array initializer of SIM peripheral base pointers */
emilmont	10:3bc89ef62ce7	2989	#define SIM_BASES { SIM }
emilmont	10:3bc89ef62ce7	2990
emilmont	10:3bc89ef62ce7	2991	/**
emilmont	10:3bc89ef62ce7	2992	* @}
emilmont	10:3bc89ef62ce7	2993	/ / end of group SIM_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	2994
emilmont	10:3bc89ef62ce7	2995
emilmont	10:3bc89ef62ce7	2996	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	2997	-- SMC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	2998	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	2999
emilmont	10:3bc89ef62ce7	3000	/**
emilmont	10:3bc89ef62ce7	3001	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3002	* @{
emilmont	10:3bc89ef62ce7	3003	*/
emilmont	10:3bc89ef62ce7	3004
emilmont	10:3bc89ef62ce7	3005	/** SMC - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3006	typedef struct {
emilmont	10:3bc89ef62ce7	3007	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3008	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
emilmont	10:3bc89ef62ce7	3009	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	3010	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	3011	} SMC_Type;
emilmont	10:3bc89ef62ce7	3012
emilmont	10:3bc89ef62ce7	3013	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3014	-- SMC Register Masks
emilmont	10:3bc89ef62ce7	3015	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3016
emilmont	10:3bc89ef62ce7	3017	/**
emilmont	10:3bc89ef62ce7	3018	* @addtogroup SMC_Register_Masks SMC Register Masks
emilmont	10:3bc89ef62ce7	3019	* @{
emilmont	10:3bc89ef62ce7	3020	*/
emilmont	10:3bc89ef62ce7	3021
emilmont	10:3bc89ef62ce7	3022	/* PMPROT Bit Fields */
emilmont	10:3bc89ef62ce7	3023	#define SMC_PMPROT_AVLLS_MASK 0x2u
emilmont	10:3bc89ef62ce7	3024	#define SMC_PMPROT_AVLLS_SHIFT 1
emilmont	10:3bc89ef62ce7	3025	#define SMC_PMPROT_ALLS_MASK 0x8u
emilmont	10:3bc89ef62ce7	3026	#define SMC_PMPROT_ALLS_SHIFT 3
emilmont	10:3bc89ef62ce7	3027	#define SMC_PMPROT_AVLP_MASK 0x20u
emilmont	10:3bc89ef62ce7	3028	#define SMC_PMPROT_AVLP_SHIFT 5
emilmont	10:3bc89ef62ce7	3029	/* PMCTRL Bit Fields */
emilmont	10:3bc89ef62ce7	3030	#define SMC_PMCTRL_STOPM_MASK 0x7u
emilmont	10:3bc89ef62ce7	3031	#define SMC_PMCTRL_STOPM_SHIFT 0
emilmont	10:3bc89ef62ce7	3032	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
emilmont	10:3bc89ef62ce7	3033	#define SMC_PMCTRL_STOPA_MASK 0x8u
emilmont	10:3bc89ef62ce7	3034	#define SMC_PMCTRL_STOPA_SHIFT 3
emilmont	10:3bc89ef62ce7	3035	#define SMC_PMCTRL_RUNM_MASK 0x60u
emilmont	10:3bc89ef62ce7	3036	#define SMC_PMCTRL_RUNM_SHIFT 5
emilmont	10:3bc89ef62ce7	3037	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
emilmont	10:3bc89ef62ce7	3038	/* STOPCTRL Bit Fields */
emilmont	10:3bc89ef62ce7	3039	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
emilmont	10:3bc89ef62ce7	3040	#define SMC_STOPCTRL_VLLSM_SHIFT 0
emilmont	10:3bc89ef62ce7	3041	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
emilmont	10:3bc89ef62ce7	3042	#define SMC_STOPCTRL_PORPO_MASK 0x20u
emilmont	10:3bc89ef62ce7	3043	#define SMC_STOPCTRL_PORPO_SHIFT 5
emilmont	10:3bc89ef62ce7	3044	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
emilmont	10:3bc89ef62ce7	3045	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
emilmont	10:3bc89ef62ce7	3046	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
emilmont	10:3bc89ef62ce7	3047	/* PMSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	3048	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
emilmont	10:3bc89ef62ce7	3049	#define SMC_PMSTAT_PMSTAT_SHIFT 0
emilmont	10:3bc89ef62ce7	3050	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
emilmont	10:3bc89ef62ce7	3051
emilmont	10:3bc89ef62ce7	3052	/**
emilmont	10:3bc89ef62ce7	3053	* @}
emilmont	10:3bc89ef62ce7	3054	/ / end of group SMC_Register_Masks */
emilmont	10:3bc89ef62ce7	3055
emilmont	10:3bc89ef62ce7	3056
emilmont	10:3bc89ef62ce7	3057	/* SMC - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3058	/** Peripheral SMC base address */
emilmont	10:3bc89ef62ce7	3059	#define SMC_BASE (0x4007E000u)
emilmont	10:3bc89ef62ce7	3060	/** Peripheral SMC base pointer */
emilmont	10:3bc89ef62ce7	3061	#define SMC ((SMC_Type *)SMC_BASE)
emilmont	10:3bc89ef62ce7	3062	/** Array initializer of SMC peripheral base pointers */
emilmont	10:3bc89ef62ce7	3063	#define SMC_BASES { SMC }
emilmont	10:3bc89ef62ce7	3064
emilmont	10:3bc89ef62ce7	3065	/**
emilmont	10:3bc89ef62ce7	3066	* @}
emilmont	10:3bc89ef62ce7	3067	/ / end of group SMC_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3068
emilmont	10:3bc89ef62ce7	3069
emilmont	10:3bc89ef62ce7	3070	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3071	-- SPI Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3072	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3073
emilmont	10:3bc89ef62ce7	3074	/**
emilmont	10:3bc89ef62ce7	3075	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3076	* @{
emilmont	10:3bc89ef62ce7	3077	*/
emilmont	10:3bc89ef62ce7	3078
emilmont	10:3bc89ef62ce7	3079	/** SPI - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3080	typedef struct {
emilmont	10:3bc89ef62ce7	3081	__IO uint8_t C1; /*< SPI control register 1, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3082	__IO uint8_t C2; /*< SPI control register 2, offset: 0x1 /
emilmont	10:3bc89ef62ce7	3083	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x2 /
emilmont	10:3bc89ef62ce7	3084	__I uint8_t S; /*< SPI status register, offset: 0x3 /
emilmont	10:3bc89ef62ce7	3085	uint8_t RESERVED_0[1];
emilmont	10:3bc89ef62ce7	3086	__IO uint8_t D; /*< SPI data register, offset: 0x5 /
emilmont	10:3bc89ef62ce7	3087	uint8_t RESERVED_1[1];
emilmont	10:3bc89ef62ce7	3088	__IO uint8_t M; /*< SPI match register, offset: 0x7 /
emilmont	10:3bc89ef62ce7	3089	} SPI_Type;
emilmont	10:3bc89ef62ce7	3090
emilmont	10:3bc89ef62ce7	3091	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3092	-- SPI Register Masks
emilmont	10:3bc89ef62ce7	3093	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3094
emilmont	10:3bc89ef62ce7	3095	/**
emilmont	10:3bc89ef62ce7	3096	* @addtogroup SPI_Register_Masks SPI Register Masks
emilmont	10:3bc89ef62ce7	3097	* @{
emilmont	10:3bc89ef62ce7	3098	*/
emilmont	10:3bc89ef62ce7	3099
emilmont	10:3bc89ef62ce7	3100	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	3101	#define SPI_C1_LSBFE_MASK 0x1u
emilmont	10:3bc89ef62ce7	3102	#define SPI_C1_LSBFE_SHIFT 0
emilmont	10:3bc89ef62ce7	3103	#define SPI_C1_SSOE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3104	#define SPI_C1_SSOE_SHIFT 1
emilmont	10:3bc89ef62ce7	3105	#define SPI_C1_CPHA_MASK 0x4u
emilmont	10:3bc89ef62ce7	3106	#define SPI_C1_CPHA_SHIFT 2
emilmont	10:3bc89ef62ce7	3107	#define SPI_C1_CPOL_MASK 0x8u
emilmont	10:3bc89ef62ce7	3108	#define SPI_C1_CPOL_SHIFT 3
emilmont	10:3bc89ef62ce7	3109	#define SPI_C1_MSTR_MASK 0x10u
emilmont	10:3bc89ef62ce7	3110	#define SPI_C1_MSTR_SHIFT 4
emilmont	10:3bc89ef62ce7	3111	#define SPI_C1_SPTIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3112	#define SPI_C1_SPTIE_SHIFT 5
emilmont	10:3bc89ef62ce7	3113	#define SPI_C1_SPE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3114	#define SPI_C1_SPE_SHIFT 6
emilmont	10:3bc89ef62ce7	3115	#define SPI_C1_SPIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3116	#define SPI_C1_SPIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3117	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	3118	#define SPI_C2_SPC0_MASK 0x1u
emilmont	10:3bc89ef62ce7	3119	#define SPI_C2_SPC0_SHIFT 0
emilmont	10:3bc89ef62ce7	3120	#define SPI_C2_SPISWAI_MASK 0x2u
emilmont	10:3bc89ef62ce7	3121	#define SPI_C2_SPISWAI_SHIFT 1
emilmont	10:3bc89ef62ce7	3122	#define SPI_C2_RXDMAE_MASK 0x4u
emilmont	10:3bc89ef62ce7	3123	#define SPI_C2_RXDMAE_SHIFT 2
emilmont	10:3bc89ef62ce7	3124	#define SPI_C2_BIDIROE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3125	#define SPI_C2_BIDIROE_SHIFT 3
emilmont	10:3bc89ef62ce7	3126	#define SPI_C2_MODFEN_MASK 0x10u
emilmont	10:3bc89ef62ce7	3127	#define SPI_C2_MODFEN_SHIFT 4
emilmont	10:3bc89ef62ce7	3128	#define SPI_C2_TXDMAE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3129	#define SPI_C2_TXDMAE_SHIFT 5
emilmont	10:3bc89ef62ce7	3130	#define SPI_C2_SPLPIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3131	#define SPI_C2_SPLPIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3132	#define SPI_C2_SPMIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3133	#define SPI_C2_SPMIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3134	/* BR Bit Fields */
emilmont	10:3bc89ef62ce7	3135	#define SPI_BR_SPR_MASK 0xFu
emilmont	10:3bc89ef62ce7	3136	#define SPI_BR_SPR_SHIFT 0
emilmont	10:3bc89ef62ce7	3137	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
emilmont	10:3bc89ef62ce7	3138	#define SPI_BR_SPPR_MASK 0x70u
emilmont	10:3bc89ef62ce7	3139	#define SPI_BR_SPPR_SHIFT 4
emilmont	10:3bc89ef62ce7	3140	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
emilmont	10:3bc89ef62ce7	3141	/* S Bit Fields */
emilmont	10:3bc89ef62ce7	3142	#define SPI_S_MODF_MASK 0x10u
emilmont	10:3bc89ef62ce7	3143	#define SPI_S_MODF_SHIFT 4
emilmont	10:3bc89ef62ce7	3144	#define SPI_S_SPTEF_MASK 0x20u
emilmont	10:3bc89ef62ce7	3145	#define SPI_S_SPTEF_SHIFT 5
emilmont	10:3bc89ef62ce7	3146	#define SPI_S_SPMF_MASK 0x40u
emilmont	10:3bc89ef62ce7	3147	#define SPI_S_SPMF_SHIFT 6
emilmont	10:3bc89ef62ce7	3148	#define SPI_S_SPRF_MASK 0x80u
emilmont	10:3bc89ef62ce7	3149	#define SPI_S_SPRF_SHIFT 7
emilmont	10:3bc89ef62ce7	3150	/* D Bit Fields */
emilmont	10:3bc89ef62ce7	3151	#define SPI_D_Bits_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3152	#define SPI_D_Bits_SHIFT 0
emilmont	10:3bc89ef62ce7	3153	#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
emilmont	10:3bc89ef62ce7	3154	/* M Bit Fields */
emilmont	10:3bc89ef62ce7	3155	#define SPI_M_Bits_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3156	#define SPI_M_Bits_SHIFT 0
emilmont	10:3bc89ef62ce7	3157	#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
emilmont	10:3bc89ef62ce7	3158
emilmont	10:3bc89ef62ce7	3159	/**
emilmont	10:3bc89ef62ce7	3160	* @}
emilmont	10:3bc89ef62ce7	3161	/ / end of group SPI_Register_Masks */
emilmont	10:3bc89ef62ce7	3162
emilmont	10:3bc89ef62ce7	3163
emilmont	10:3bc89ef62ce7	3164	/* SPI - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3165	/** Peripheral SPI0 base address */
emilmont	10:3bc89ef62ce7	3166	#define SPI0_BASE (0x40076000u)
emilmont	10:3bc89ef62ce7	3167	/** Peripheral SPI0 base pointer */
emilmont	10:3bc89ef62ce7	3168	#define SPI0 ((SPI_Type *)SPI0_BASE)
emilmont	10:3bc89ef62ce7	3169	/** Peripheral SPI1 base address */
emilmont	10:3bc89ef62ce7	3170	#define SPI1_BASE (0x40077000u)
emilmont	10:3bc89ef62ce7	3171	/** Peripheral SPI1 base pointer */
emilmont	10:3bc89ef62ce7	3172	#define SPI1 ((SPI_Type *)SPI1_BASE)
emilmont	10:3bc89ef62ce7	3173	/** Array initializer of SPI peripheral base pointers */
emilmont	10:3bc89ef62ce7	3174	#define SPI_BASES { SPI0, SPI1 }
emilmont	10:3bc89ef62ce7	3175
emilmont	10:3bc89ef62ce7	3176	/**
emilmont	10:3bc89ef62ce7	3177	* @}
emilmont	10:3bc89ef62ce7	3178	/ / end of group SPI_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3179
emilmont	10:3bc89ef62ce7	3180
emilmont	10:3bc89ef62ce7	3181	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3182	-- TPM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3183	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3184
emilmont	10:3bc89ef62ce7	3185	/**
emilmont	10:3bc89ef62ce7	3186	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3187	* @{
emilmont	10:3bc89ef62ce7	3188	*/
emilmont	10:3bc89ef62ce7	3189
emilmont	10:3bc89ef62ce7	3190	/** TPM - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3191	typedef struct {
emilmont	10:3bc89ef62ce7	3192	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3193	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
emilmont	10:3bc89ef62ce7	3194	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
emilmont	10:3bc89ef62ce7	3195	struct { /* offset: 0xC, array step: 0x8 */
emilmont	10:3bc89ef62ce7	3196	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
emilmont	10:3bc89ef62ce7	3197	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
emilmont	10:3bc89ef62ce7	3198	} CONTROLS[6];
emilmont	10:3bc89ef62ce7	3199	uint8_t RESERVED_0[20];
emilmont	10:3bc89ef62ce7	3200	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
emilmont	10:3bc89ef62ce7	3201	uint8_t RESERVED_1[48];
emilmont	10:3bc89ef62ce7	3202	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
emilmont	10:3bc89ef62ce7	3203	} TPM_Type;
emilmont	10:3bc89ef62ce7	3204
emilmont	10:3bc89ef62ce7	3205	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3206	-- TPM Register Masks
emilmont	10:3bc89ef62ce7	3207	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3208
emilmont	10:3bc89ef62ce7	3209	/**
emilmont	10:3bc89ef62ce7	3210	* @addtogroup TPM_Register_Masks TPM Register Masks
emilmont	10:3bc89ef62ce7	3211	* @{
emilmont	10:3bc89ef62ce7	3212	*/
emilmont	10:3bc89ef62ce7	3213
emilmont	10:3bc89ef62ce7	3214	/* SC Bit Fields */
emilmont	10:3bc89ef62ce7	3215	#define TPM_SC_PS_MASK 0x7u
emilmont	10:3bc89ef62ce7	3216	#define TPM_SC_PS_SHIFT 0
emilmont	10:3bc89ef62ce7	3217	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
emilmont	10:3bc89ef62ce7	3218	#define TPM_SC_CMOD_MASK 0x18u
emilmont	10:3bc89ef62ce7	3219	#define TPM_SC_CMOD_SHIFT 3
emilmont	10:3bc89ef62ce7	3220	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
emilmont	10:3bc89ef62ce7	3221	#define TPM_SC_CPWMS_MASK 0x20u
emilmont	10:3bc89ef62ce7	3222	#define TPM_SC_CPWMS_SHIFT 5
emilmont	10:3bc89ef62ce7	3223	#define TPM_SC_TOIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3224	#define TPM_SC_TOIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3225	#define TPM_SC_TOF_MASK 0x80u
emilmont	10:3bc89ef62ce7	3226	#define TPM_SC_TOF_SHIFT 7
emilmont	10:3bc89ef62ce7	3227	#define TPM_SC_DMA_MASK 0x100u
emilmont	10:3bc89ef62ce7	3228	#define TPM_SC_DMA_SHIFT 8
emilmont	10:3bc89ef62ce7	3229	/* CNT Bit Fields */
emilmont	10:3bc89ef62ce7	3230	#define TPM_CNT_COUNT_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	3231	#define TPM_CNT_COUNT_SHIFT 0
emilmont	10:3bc89ef62ce7	3232	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
emilmont	10:3bc89ef62ce7	3233	/* MOD Bit Fields */
emilmont	10:3bc89ef62ce7	3234	#define TPM_MOD_MOD_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	3235	#define TPM_MOD_MOD_SHIFT 0
emilmont	10:3bc89ef62ce7	3236	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
emilmont	10:3bc89ef62ce7	3237	/* CnSC Bit Fields */
emilmont	10:3bc89ef62ce7	3238	#define TPM_CnSC_DMA_MASK 0x1u
emilmont	10:3bc89ef62ce7	3239	#define TPM_CnSC_DMA_SHIFT 0
emilmont	10:3bc89ef62ce7	3240	#define TPM_CnSC_ELSA_MASK 0x4u
emilmont	10:3bc89ef62ce7	3241	#define TPM_CnSC_ELSA_SHIFT 2
emilmont	10:3bc89ef62ce7	3242	#define TPM_CnSC_ELSB_MASK 0x8u
emilmont	10:3bc89ef62ce7	3243	#define TPM_CnSC_ELSB_SHIFT 3
emilmont	10:3bc89ef62ce7	3244	#define TPM_CnSC_MSA_MASK 0x10u
emilmont	10:3bc89ef62ce7	3245	#define TPM_CnSC_MSA_SHIFT 4
emilmont	10:3bc89ef62ce7	3246	#define TPM_CnSC_MSB_MASK 0x20u
emilmont	10:3bc89ef62ce7	3247	#define TPM_CnSC_MSB_SHIFT 5
emilmont	10:3bc89ef62ce7	3248	#define TPM_CnSC_CHIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3249	#define TPM_CnSC_CHIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3250	#define TPM_CnSC_CHF_MASK 0x80u
emilmont	10:3bc89ef62ce7	3251	#define TPM_CnSC_CHF_SHIFT 7
emilmont	10:3bc89ef62ce7	3252	/* CnV Bit Fields */
emilmont	10:3bc89ef62ce7	3253	#define TPM_CnV_VAL_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	3254	#define TPM_CnV_VAL_SHIFT 0
emilmont	10:3bc89ef62ce7	3255	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
emilmont	10:3bc89ef62ce7	3256	/* STATUS Bit Fields */
emilmont	10:3bc89ef62ce7	3257	#define TPM_STATUS_CH0F_MASK 0x1u
emilmont	10:3bc89ef62ce7	3258	#define TPM_STATUS_CH0F_SHIFT 0
emilmont	10:3bc89ef62ce7	3259	#define TPM_STATUS_CH1F_MASK 0x2u
emilmont	10:3bc89ef62ce7	3260	#define TPM_STATUS_CH1F_SHIFT 1
emilmont	10:3bc89ef62ce7	3261	#define TPM_STATUS_CH2F_MASK 0x4u
emilmont	10:3bc89ef62ce7	3262	#define TPM_STATUS_CH2F_SHIFT 2
emilmont	10:3bc89ef62ce7	3263	#define TPM_STATUS_CH3F_MASK 0x8u
emilmont	10:3bc89ef62ce7	3264	#define TPM_STATUS_CH3F_SHIFT 3
emilmont	10:3bc89ef62ce7	3265	#define TPM_STATUS_CH4F_MASK 0x10u
emilmont	10:3bc89ef62ce7	3266	#define TPM_STATUS_CH4F_SHIFT 4
emilmont	10:3bc89ef62ce7	3267	#define TPM_STATUS_CH5F_MASK 0x20u
emilmont	10:3bc89ef62ce7	3268	#define TPM_STATUS_CH5F_SHIFT 5
emilmont	10:3bc89ef62ce7	3269	#define TPM_STATUS_TOF_MASK 0x100u
emilmont	10:3bc89ef62ce7	3270	#define TPM_STATUS_TOF_SHIFT 8
emilmont	10:3bc89ef62ce7	3271	/* CONF Bit Fields */
emilmont	10:3bc89ef62ce7	3272	#define TPM_CONF_DOZEEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	3273	#define TPM_CONF_DOZEEN_SHIFT 5
emilmont	10:3bc89ef62ce7	3274	#define TPM_CONF_DBGMODE_MASK 0xC0u
emilmont	10:3bc89ef62ce7	3275	#define TPM_CONF_DBGMODE_SHIFT 6
emilmont	10:3bc89ef62ce7	3276	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
emilmont	10:3bc89ef62ce7	3277	#define TPM_CONF_GTBEEN_MASK 0x200u
emilmont	10:3bc89ef62ce7	3278	#define TPM_CONF_GTBEEN_SHIFT 9
emilmont	10:3bc89ef62ce7	3279	#define TPM_CONF_CSOT_MASK 0x10000u
emilmont	10:3bc89ef62ce7	3280	#define TPM_CONF_CSOT_SHIFT 16
emilmont	10:3bc89ef62ce7	3281	#define TPM_CONF_CSOO_MASK 0x20000u
emilmont	10:3bc89ef62ce7	3282	#define TPM_CONF_CSOO_SHIFT 17
emilmont	10:3bc89ef62ce7	3283	#define TPM_CONF_CROT_MASK 0x40000u
emilmont	10:3bc89ef62ce7	3284	#define TPM_CONF_CROT_SHIFT 18
emilmont	10:3bc89ef62ce7	3285	#define TPM_CONF_TRGSEL_MASK 0xF000000u
emilmont	10:3bc89ef62ce7	3286	#define TPM_CONF_TRGSEL_SHIFT 24
emilmont	10:3bc89ef62ce7	3287	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
emilmont	10:3bc89ef62ce7	3288
emilmont	10:3bc89ef62ce7	3289	/**
emilmont	10:3bc89ef62ce7	3290	* @}
emilmont	10:3bc89ef62ce7	3291	/ / end of group TPM_Register_Masks */
emilmont	10:3bc89ef62ce7	3292
emilmont	10:3bc89ef62ce7	3293
emilmont	10:3bc89ef62ce7	3294	/* TPM - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3295	/** Peripheral TPM0 base address */
emilmont	10:3bc89ef62ce7	3296	#define TPM0_BASE (0x40038000u)
emilmont	10:3bc89ef62ce7	3297	/** Peripheral TPM0 base pointer */
emilmont	10:3bc89ef62ce7	3298	#define TPM0 ((TPM_Type *)TPM0_BASE)
emilmont	10:3bc89ef62ce7	3299	/** Peripheral TPM1 base address */
emilmont	10:3bc89ef62ce7	3300	#define TPM1_BASE (0x40039000u)
emilmont	10:3bc89ef62ce7	3301	/** Peripheral TPM1 base pointer */
emilmont	10:3bc89ef62ce7	3302	#define TPM1 ((TPM_Type *)TPM1_BASE)
emilmont	10:3bc89ef62ce7	3303	/** Peripheral TPM2 base address */
emilmont	10:3bc89ef62ce7	3304	#define TPM2_BASE (0x4003A000u)
emilmont	10:3bc89ef62ce7	3305	/** Peripheral TPM2 base pointer */
emilmont	10:3bc89ef62ce7	3306	#define TPM2 ((TPM_Type *)TPM2_BASE)
emilmont	10:3bc89ef62ce7	3307	/** Array initializer of TPM peripheral base pointers */
emilmont	10:3bc89ef62ce7	3308	#define TPM_BASES { TPM0, TPM1, TPM2 }
emilmont	10:3bc89ef62ce7	3309
emilmont	10:3bc89ef62ce7	3310	/**
emilmont	10:3bc89ef62ce7	3311	* @}
emilmont	10:3bc89ef62ce7	3312	/ / end of group TPM_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3313
emilmont	10:3bc89ef62ce7	3314
emilmont	10:3bc89ef62ce7	3315	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3316	-- TSI Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3317	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3318
emilmont	10:3bc89ef62ce7	3319	/**
emilmont	10:3bc89ef62ce7	3320	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3321	* @{
emilmont	10:3bc89ef62ce7	3322	*/
emilmont	10:3bc89ef62ce7	3323
emilmont	10:3bc89ef62ce7	3324	/** TSI - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3325	typedef struct {
emilmont	10:3bc89ef62ce7	3326	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3327	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	3328	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	3329	} TSI_Type;
emilmont	10:3bc89ef62ce7	3330
emilmont	10:3bc89ef62ce7	3331	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3332	-- TSI Register Masks
emilmont	10:3bc89ef62ce7	3333	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3334
emilmont	10:3bc89ef62ce7	3335	/**
emilmont	10:3bc89ef62ce7	3336	* @addtogroup TSI_Register_Masks TSI Register Masks
emilmont	10:3bc89ef62ce7	3337	* @{
emilmont	10:3bc89ef62ce7	3338	*/
emilmont	10:3bc89ef62ce7	3339
emilmont	10:3bc89ef62ce7	3340	/* GENCS Bit Fields */
emilmont	10:3bc89ef62ce7	3341	#define TSI_GENCS_CURSW_MASK 0x2u
emilmont	10:3bc89ef62ce7	3342	#define TSI_GENCS_CURSW_SHIFT 1
emilmont	10:3bc89ef62ce7	3343	#define TSI_GENCS_EOSF_MASK 0x4u
emilmont	10:3bc89ef62ce7	3344	#define TSI_GENCS_EOSF_SHIFT 2
emilmont	10:3bc89ef62ce7	3345	#define TSI_GENCS_SCNIP_MASK 0x8u
emilmont	10:3bc89ef62ce7	3346	#define TSI_GENCS_SCNIP_SHIFT 3
emilmont	10:3bc89ef62ce7	3347	#define TSI_GENCS_STM_MASK 0x10u
emilmont	10:3bc89ef62ce7	3348	#define TSI_GENCS_STM_SHIFT 4
emilmont	10:3bc89ef62ce7	3349	#define TSI_GENCS_STPE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3350	#define TSI_GENCS_STPE_SHIFT 5
emilmont	10:3bc89ef62ce7	3351	#define TSI_GENCS_TSIIEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	3352	#define TSI_GENCS_TSIIEN_SHIFT 6
emilmont	10:3bc89ef62ce7	3353	#define TSI_GENCS_TSIEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	3354	#define TSI_GENCS_TSIEN_SHIFT 7
emilmont	10:3bc89ef62ce7	3355	#define TSI_GENCS_NSCN_MASK 0x1F00u
emilmont	10:3bc89ef62ce7	3356	#define TSI_GENCS_NSCN_SHIFT 8
emilmont	10:3bc89ef62ce7	3357	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
emilmont	10:3bc89ef62ce7	3358	#define TSI_GENCS_PS_MASK 0xE000u
emilmont	10:3bc89ef62ce7	3359	#define TSI_GENCS_PS_SHIFT 13
emilmont	10:3bc89ef62ce7	3360	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
emilmont	10:3bc89ef62ce7	3361	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
emilmont	10:3bc89ef62ce7	3362	#define TSI_GENCS_EXTCHRG_SHIFT 16
emilmont	10:3bc89ef62ce7	3363	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
emilmont	10:3bc89ef62ce7	3364	#define TSI_GENCS_DVOLT_MASK 0x180000u
emilmont	10:3bc89ef62ce7	3365	#define TSI_GENCS_DVOLT_SHIFT 19
emilmont	10:3bc89ef62ce7	3366	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
emilmont	10:3bc89ef62ce7	3367	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
emilmont	10:3bc89ef62ce7	3368	#define TSI_GENCS_REFCHRG_SHIFT 21
emilmont	10:3bc89ef62ce7	3369	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
emilmont	10:3bc89ef62ce7	3370	#define TSI_GENCS_MODE_MASK 0xF000000u
emilmont	10:3bc89ef62ce7	3371	#define TSI_GENCS_MODE_SHIFT 24
emilmont	10:3bc89ef62ce7	3372	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
emilmont	10:3bc89ef62ce7	3373	#define TSI_GENCS_ESOR_MASK 0x10000000u
emilmont	10:3bc89ef62ce7	3374	#define TSI_GENCS_ESOR_SHIFT 28
emilmont	10:3bc89ef62ce7	3375	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
emilmont	10:3bc89ef62ce7	3376	#define TSI_GENCS_OUTRGF_SHIFT 31
emilmont	10:3bc89ef62ce7	3377	/* DATA Bit Fields */
emilmont	10:3bc89ef62ce7	3378	#define TSI_DATA_TSICNT_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	3379	#define TSI_DATA_TSICNT_SHIFT 0
emilmont	10:3bc89ef62ce7	3380	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
emilmont	10:3bc89ef62ce7	3381	#define TSI_DATA_SWTS_MASK 0x400000u
emilmont	10:3bc89ef62ce7	3382	#define TSI_DATA_SWTS_SHIFT 22
emilmont	10:3bc89ef62ce7	3383	#define TSI_DATA_DMAEN_MASK 0x800000u
emilmont	10:3bc89ef62ce7	3384	#define TSI_DATA_DMAEN_SHIFT 23
emilmont	10:3bc89ef62ce7	3385	#define TSI_DATA_TSICH_MASK 0xF0000000u
emilmont	10:3bc89ef62ce7	3386	#define TSI_DATA_TSICH_SHIFT 28
emilmont	10:3bc89ef62ce7	3387	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
emilmont	10:3bc89ef62ce7	3388	/* TSHD Bit Fields */
emilmont	10:3bc89ef62ce7	3389	#define TSI_TSHD_THRESL_MASK 0xFFFFu
emilmont	10:3bc89ef62ce7	3390	#define TSI_TSHD_THRESL_SHIFT 0
emilmont	10:3bc89ef62ce7	3391	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
emilmont	10:3bc89ef62ce7	3392	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
emilmont	10:3bc89ef62ce7	3393	#define TSI_TSHD_THRESH_SHIFT 16
emilmont	10:3bc89ef62ce7	3394	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
emilmont	10:3bc89ef62ce7	3395
emilmont	10:3bc89ef62ce7	3396	/**
emilmont	10:3bc89ef62ce7	3397	* @}
emilmont	10:3bc89ef62ce7	3398	/ / end of group TSI_Register_Masks */
emilmont	10:3bc89ef62ce7	3399
emilmont	10:3bc89ef62ce7	3400
emilmont	10:3bc89ef62ce7	3401	/* TSI - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3402	/** Peripheral TSI0 base address */
emilmont	10:3bc89ef62ce7	3403	#define TSI0_BASE (0x40045000u)
emilmont	10:3bc89ef62ce7	3404	/** Peripheral TSI0 base pointer */
emilmont	10:3bc89ef62ce7	3405	#define TSI0 ((TSI_Type *)TSI0_BASE)
emilmont	10:3bc89ef62ce7	3406	/** Array initializer of TSI peripheral base pointers */
emilmont	10:3bc89ef62ce7	3407	#define TSI_BASES { TSI0 }
emilmont	10:3bc89ef62ce7	3408
emilmont	10:3bc89ef62ce7	3409	/**
emilmont	10:3bc89ef62ce7	3410	* @}
emilmont	10:3bc89ef62ce7	3411	/ / end of group TSI_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3412
emilmont	10:3bc89ef62ce7	3413
emilmont	10:3bc89ef62ce7	3414	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3415	-- UART Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3416	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3417
emilmont	10:3bc89ef62ce7	3418	/**
emilmont	10:3bc89ef62ce7	3419	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3420	* @{
emilmont	10:3bc89ef62ce7	3421	*/
emilmont	10:3bc89ef62ce7	3422
emilmont	10:3bc89ef62ce7	3423	/** UART - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3424	typedef struct {
emilmont	10:3bc89ef62ce7	3425	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3426	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
emilmont	10:3bc89ef62ce7	3427	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	10:3bc89ef62ce7	3428	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	10:3bc89ef62ce7	3429	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	10:3bc89ef62ce7	3430	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	10:3bc89ef62ce7	3431	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	10:3bc89ef62ce7	3432	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	10:3bc89ef62ce7	3433	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
emilmont	10:3bc89ef62ce7	3434	} UART_Type;
emilmont	10:3bc89ef62ce7	3435
emilmont	10:3bc89ef62ce7	3436	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3437	-- UART Register Masks
emilmont	10:3bc89ef62ce7	3438	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3439
emilmont	10:3bc89ef62ce7	3440	/**
emilmont	10:3bc89ef62ce7	3441	* @addtogroup UART_Register_Masks UART Register Masks
emilmont	10:3bc89ef62ce7	3442	* @{
emilmont	10:3bc89ef62ce7	3443	*/
emilmont	10:3bc89ef62ce7	3444
emilmont	10:3bc89ef62ce7	3445	/* BDH Bit Fields */
emilmont	10:3bc89ef62ce7	3446	#define UART_BDH_SBR_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	3447	#define UART_BDH_SBR_SHIFT 0
emilmont	10:3bc89ef62ce7	3448	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
emilmont	10:3bc89ef62ce7	3449	#define UART_BDH_SBNS_MASK 0x20u
emilmont	10:3bc89ef62ce7	3450	#define UART_BDH_SBNS_SHIFT 5
emilmont	10:3bc89ef62ce7	3451	#define UART_BDH_RXEDGIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3452	#define UART_BDH_RXEDGIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3453	#define UART_BDH_LBKDIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3454	#define UART_BDH_LBKDIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3455	/* BDL Bit Fields */
emilmont	10:3bc89ef62ce7	3456	#define UART_BDL_SBR_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3457	#define UART_BDL_SBR_SHIFT 0
emilmont	10:3bc89ef62ce7	3458	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
emilmont	10:3bc89ef62ce7	3459	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	3460	#define UART_C1_PT_MASK 0x1u
emilmont	10:3bc89ef62ce7	3461	#define UART_C1_PT_SHIFT 0
emilmont	10:3bc89ef62ce7	3462	#define UART_C1_PE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3463	#define UART_C1_PE_SHIFT 1
emilmont	10:3bc89ef62ce7	3464	#define UART_C1_ILT_MASK 0x4u
emilmont	10:3bc89ef62ce7	3465	#define UART_C1_ILT_SHIFT 2
emilmont	10:3bc89ef62ce7	3466	#define UART_C1_WAKE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3467	#define UART_C1_WAKE_SHIFT 3
emilmont	10:3bc89ef62ce7	3468	#define UART_C1_M_MASK 0x10u
emilmont	10:3bc89ef62ce7	3469	#define UART_C1_M_SHIFT 4
emilmont	10:3bc89ef62ce7	3470	#define UART_C1_RSRC_MASK 0x20u
emilmont	10:3bc89ef62ce7	3471	#define UART_C1_RSRC_SHIFT 5
emilmont	10:3bc89ef62ce7	3472	#define UART_C1_UARTSWAI_MASK 0x40u
emilmont	10:3bc89ef62ce7	3473	#define UART_C1_UARTSWAI_SHIFT 6
emilmont	10:3bc89ef62ce7	3474	#define UART_C1_LOOPS_MASK 0x80u
emilmont	10:3bc89ef62ce7	3475	#define UART_C1_LOOPS_SHIFT 7
emilmont	10:3bc89ef62ce7	3476	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	3477	#define UART_C2_SBK_MASK 0x1u
emilmont	10:3bc89ef62ce7	3478	#define UART_C2_SBK_SHIFT 0
emilmont	10:3bc89ef62ce7	3479	#define UART_C2_RWU_MASK 0x2u
emilmont	10:3bc89ef62ce7	3480	#define UART_C2_RWU_SHIFT 1
emilmont	10:3bc89ef62ce7	3481	#define UART_C2_RE_MASK 0x4u
emilmont	10:3bc89ef62ce7	3482	#define UART_C2_RE_SHIFT 2
emilmont	10:3bc89ef62ce7	3483	#define UART_C2_TE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3484	#define UART_C2_TE_SHIFT 3
emilmont	10:3bc89ef62ce7	3485	#define UART_C2_ILIE_MASK 0x10u
emilmont	10:3bc89ef62ce7	3486	#define UART_C2_ILIE_SHIFT 4
emilmont	10:3bc89ef62ce7	3487	#define UART_C2_RIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3488	#define UART_C2_RIE_SHIFT 5
emilmont	10:3bc89ef62ce7	3489	#define UART_C2_TCIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3490	#define UART_C2_TCIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3491	#define UART_C2_TIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3492	#define UART_C2_TIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3493	/* S1 Bit Fields */
emilmont	10:3bc89ef62ce7	3494	#define UART_S1_PF_MASK 0x1u
emilmont	10:3bc89ef62ce7	3495	#define UART_S1_PF_SHIFT 0
emilmont	10:3bc89ef62ce7	3496	#define UART_S1_FE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3497	#define UART_S1_FE_SHIFT 1
emilmont	10:3bc89ef62ce7	3498	#define UART_S1_NF_MASK 0x4u
emilmont	10:3bc89ef62ce7	3499	#define UART_S1_NF_SHIFT 2
emilmont	10:3bc89ef62ce7	3500	#define UART_S1_OR_MASK 0x8u
emilmont	10:3bc89ef62ce7	3501	#define UART_S1_OR_SHIFT 3
emilmont	10:3bc89ef62ce7	3502	#define UART_S1_IDLE_MASK 0x10u
emilmont	10:3bc89ef62ce7	3503	#define UART_S1_IDLE_SHIFT 4
emilmont	10:3bc89ef62ce7	3504	#define UART_S1_RDRF_MASK 0x20u
emilmont	10:3bc89ef62ce7	3505	#define UART_S1_RDRF_SHIFT 5
emilmont	10:3bc89ef62ce7	3506	#define UART_S1_TC_MASK 0x40u
emilmont	10:3bc89ef62ce7	3507	#define UART_S1_TC_SHIFT 6
emilmont	10:3bc89ef62ce7	3508	#define UART_S1_TDRE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3509	#define UART_S1_TDRE_SHIFT 7
emilmont	10:3bc89ef62ce7	3510	/* S2 Bit Fields */
emilmont	10:3bc89ef62ce7	3511	#define UART_S2_RAF_MASK 0x1u
emilmont	10:3bc89ef62ce7	3512	#define UART_S2_RAF_SHIFT 0
emilmont	10:3bc89ef62ce7	3513	#define UART_S2_LBKDE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3514	#define UART_S2_LBKDE_SHIFT 1
emilmont	10:3bc89ef62ce7	3515	#define UART_S2_BRK13_MASK 0x4u
emilmont	10:3bc89ef62ce7	3516	#define UART_S2_BRK13_SHIFT 2
emilmont	10:3bc89ef62ce7	3517	#define UART_S2_RWUID_MASK 0x8u
emilmont	10:3bc89ef62ce7	3518	#define UART_S2_RWUID_SHIFT 3
emilmont	10:3bc89ef62ce7	3519	#define UART_S2_RXINV_MASK 0x10u
emilmont	10:3bc89ef62ce7	3520	#define UART_S2_RXINV_SHIFT 4
emilmont	10:3bc89ef62ce7	3521	#define UART_S2_RXEDGIF_MASK 0x40u
emilmont	10:3bc89ef62ce7	3522	#define UART_S2_RXEDGIF_SHIFT 6
emilmont	10:3bc89ef62ce7	3523	#define UART_S2_LBKDIF_MASK 0x80u
emilmont	10:3bc89ef62ce7	3524	#define UART_S2_LBKDIF_SHIFT 7
emilmont	10:3bc89ef62ce7	3525	/* C3 Bit Fields */
emilmont	10:3bc89ef62ce7	3526	#define UART_C3_PEIE_MASK 0x1u
emilmont	10:3bc89ef62ce7	3527	#define UART_C3_PEIE_SHIFT 0
emilmont	10:3bc89ef62ce7	3528	#define UART_C3_FEIE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3529	#define UART_C3_FEIE_SHIFT 1
emilmont	10:3bc89ef62ce7	3530	#define UART_C3_NEIE_MASK 0x4u
emilmont	10:3bc89ef62ce7	3531	#define UART_C3_NEIE_SHIFT 2
emilmont	10:3bc89ef62ce7	3532	#define UART_C3_ORIE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3533	#define UART_C3_ORIE_SHIFT 3
emilmont	10:3bc89ef62ce7	3534	#define UART_C3_TXINV_MASK 0x10u
emilmont	10:3bc89ef62ce7	3535	#define UART_C3_TXINV_SHIFT 4
emilmont	10:3bc89ef62ce7	3536	#define UART_C3_TXDIR_MASK 0x20u
emilmont	10:3bc89ef62ce7	3537	#define UART_C3_TXDIR_SHIFT 5
emilmont	10:3bc89ef62ce7	3538	#define UART_C3_T8_MASK 0x40u
emilmont	10:3bc89ef62ce7	3539	#define UART_C3_T8_SHIFT 6
emilmont	10:3bc89ef62ce7	3540	#define UART_C3_R8_MASK 0x80u
emilmont	10:3bc89ef62ce7	3541	#define UART_C3_R8_SHIFT 7
emilmont	10:3bc89ef62ce7	3542	/* D Bit Fields */
emilmont	10:3bc89ef62ce7	3543	#define UART_D_R0T0_MASK 0x1u
emilmont	10:3bc89ef62ce7	3544	#define UART_D_R0T0_SHIFT 0
emilmont	10:3bc89ef62ce7	3545	#define UART_D_R1T1_MASK 0x2u
emilmont	10:3bc89ef62ce7	3546	#define UART_D_R1T1_SHIFT 1
emilmont	10:3bc89ef62ce7	3547	#define UART_D_R2T2_MASK 0x4u
emilmont	10:3bc89ef62ce7	3548	#define UART_D_R2T2_SHIFT 2
emilmont	10:3bc89ef62ce7	3549	#define UART_D_R3T3_MASK 0x8u
emilmont	10:3bc89ef62ce7	3550	#define UART_D_R3T3_SHIFT 3
emilmont	10:3bc89ef62ce7	3551	#define UART_D_R4T4_MASK 0x10u
emilmont	10:3bc89ef62ce7	3552	#define UART_D_R4T4_SHIFT 4
emilmont	10:3bc89ef62ce7	3553	#define UART_D_R5T5_MASK 0x20u
emilmont	10:3bc89ef62ce7	3554	#define UART_D_R5T5_SHIFT 5
emilmont	10:3bc89ef62ce7	3555	#define UART_D_R6T6_MASK 0x40u
emilmont	10:3bc89ef62ce7	3556	#define UART_D_R6T6_SHIFT 6
emilmont	10:3bc89ef62ce7	3557	#define UART_D_R7T7_MASK 0x80u
emilmont	10:3bc89ef62ce7	3558	#define UART_D_R7T7_SHIFT 7
emilmont	10:3bc89ef62ce7	3559	/* C4 Bit Fields */
emilmont	10:3bc89ef62ce7	3560	#define UART_C4_LBKDDMAS_MASK 0x8u
emilmont	10:3bc89ef62ce7	3561	#define UART_C4_LBKDDMAS_SHIFT 3
emilmont	10:3bc89ef62ce7	3562	#define UART_C4_ILDMAS_MASK 0x10u
emilmont	10:3bc89ef62ce7	3563	#define UART_C4_ILDMAS_SHIFT 4
emilmont	10:3bc89ef62ce7	3564	#define UART_C4_RDMAS_MASK 0x20u
emilmont	10:3bc89ef62ce7	3565	#define UART_C4_RDMAS_SHIFT 5
emilmont	10:3bc89ef62ce7	3566	#define UART_C4_TCDMAS_MASK 0x40u
emilmont	10:3bc89ef62ce7	3567	#define UART_C4_TCDMAS_SHIFT 6
emilmont	10:3bc89ef62ce7	3568	#define UART_C4_TDMAS_MASK 0x80u
emilmont	10:3bc89ef62ce7	3569	#define UART_C4_TDMAS_SHIFT 7
emilmont	10:3bc89ef62ce7	3570
emilmont	10:3bc89ef62ce7	3571	/**
emilmont	10:3bc89ef62ce7	3572	* @}
emilmont	10:3bc89ef62ce7	3573	/ / end of group UART_Register_Masks */
emilmont	10:3bc89ef62ce7	3574
emilmont	10:3bc89ef62ce7	3575
emilmont	10:3bc89ef62ce7	3576	/* UART - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3577	/** Peripheral UART1 base address */
emilmont	10:3bc89ef62ce7	3578	#define UART1_BASE (0x4006B000u)
emilmont	10:3bc89ef62ce7	3579	/** Peripheral UART1 base pointer */
emilmont	10:3bc89ef62ce7	3580	#define UART1 ((UART_Type *)UART1_BASE)
emilmont	10:3bc89ef62ce7	3581	/** Peripheral UART2 base address */
emilmont	10:3bc89ef62ce7	3582	#define UART2_BASE (0x4006C000u)
emilmont	10:3bc89ef62ce7	3583	/** Peripheral UART2 base pointer */
emilmont	10:3bc89ef62ce7	3584	#define UART2 ((UART_Type *)UART2_BASE)
emilmont	10:3bc89ef62ce7	3585	/** Array initializer of UART peripheral base pointers */
emilmont	10:3bc89ef62ce7	3586	#define UART_BASES { UART1, UART2 }
emilmont	10:3bc89ef62ce7	3587
emilmont	10:3bc89ef62ce7	3588	/**
emilmont	10:3bc89ef62ce7	3589	* @}
emilmont	10:3bc89ef62ce7	3590	/ / end of group UART_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3591
emilmont	10:3bc89ef62ce7	3592
emilmont	10:3bc89ef62ce7	3593	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3594	-- UARTLP Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3595	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3596
emilmont	10:3bc89ef62ce7	3597	/**
emilmont	10:3bc89ef62ce7	3598	* @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3599	* @{
emilmont	10:3bc89ef62ce7	3600	*/
emilmont	10:3bc89ef62ce7	3601
emilmont	10:3bc89ef62ce7	3602	/** UARTLP - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3603	typedef struct {
emilmont	10:3bc89ef62ce7	3604	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3605	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
emilmont	10:3bc89ef62ce7	3606	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	10:3bc89ef62ce7	3607	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	10:3bc89ef62ce7	3608	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	10:3bc89ef62ce7	3609	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	10:3bc89ef62ce7	3610	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	10:3bc89ef62ce7	3611	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	10:3bc89ef62ce7	3612	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
emilmont	10:3bc89ef62ce7	3613	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
emilmont	10:3bc89ef62ce7	3614	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
emilmont	10:3bc89ef62ce7	3615	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
emilmont	10:3bc89ef62ce7	3616	} UARTLP_Type;
emilmont	10:3bc89ef62ce7	3617
emilmont	10:3bc89ef62ce7	3618	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3619	-- UARTLP Register Masks
emilmont	10:3bc89ef62ce7	3620	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3621
emilmont	10:3bc89ef62ce7	3622	/**
emilmont	10:3bc89ef62ce7	3623	* @addtogroup UARTLP_Register_Masks UARTLP Register Masks
emilmont	10:3bc89ef62ce7	3624	* @{
emilmont	10:3bc89ef62ce7	3625	*/
emilmont	10:3bc89ef62ce7	3626
emilmont	10:3bc89ef62ce7	3627	/* BDH Bit Fields */
emilmont	10:3bc89ef62ce7	3628	#define UARTLP_BDH_SBR_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	3629	#define UARTLP_BDH_SBR_SHIFT 0
emilmont	10:3bc89ef62ce7	3630	#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
emilmont	10:3bc89ef62ce7	3631	#define UARTLP_BDH_SBNS_MASK 0x20u
emilmont	10:3bc89ef62ce7	3632	#define UARTLP_BDH_SBNS_SHIFT 5
emilmont	10:3bc89ef62ce7	3633	#define UARTLP_BDH_RXEDGIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3634	#define UARTLP_BDH_RXEDGIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3635	#define UARTLP_BDH_LBKDIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3636	#define UARTLP_BDH_LBKDIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3637	/* BDL Bit Fields */
emilmont	10:3bc89ef62ce7	3638	#define UARTLP_BDL_SBR_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3639	#define UARTLP_BDL_SBR_SHIFT 0
emilmont	10:3bc89ef62ce7	3640	#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
emilmont	10:3bc89ef62ce7	3641	/* C1 Bit Fields */
emilmont	10:3bc89ef62ce7	3642	#define UARTLP_C1_PT_MASK 0x1u
emilmont	10:3bc89ef62ce7	3643	#define UARTLP_C1_PT_SHIFT 0
emilmont	10:3bc89ef62ce7	3644	#define UARTLP_C1_PE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3645	#define UARTLP_C1_PE_SHIFT 1
emilmont	10:3bc89ef62ce7	3646	#define UARTLP_C1_ILT_MASK 0x4u
emilmont	10:3bc89ef62ce7	3647	#define UARTLP_C1_ILT_SHIFT 2
emilmont	10:3bc89ef62ce7	3648	#define UARTLP_C1_WAKE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3649	#define UARTLP_C1_WAKE_SHIFT 3
emilmont	10:3bc89ef62ce7	3650	#define UARTLP_C1_M_MASK 0x10u
emilmont	10:3bc89ef62ce7	3651	#define UARTLP_C1_M_SHIFT 4
emilmont	10:3bc89ef62ce7	3652	#define UARTLP_C1_RSRC_MASK 0x20u
emilmont	10:3bc89ef62ce7	3653	#define UARTLP_C1_RSRC_SHIFT 5
emilmont	10:3bc89ef62ce7	3654	#define UARTLP_C1_DOZEEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	3655	#define UARTLP_C1_DOZEEN_SHIFT 6
emilmont	10:3bc89ef62ce7	3656	#define UARTLP_C1_LOOPS_MASK 0x80u
emilmont	10:3bc89ef62ce7	3657	#define UARTLP_C1_LOOPS_SHIFT 7
emilmont	10:3bc89ef62ce7	3658	/* C2 Bit Fields */
emilmont	10:3bc89ef62ce7	3659	#define UARTLP_C2_SBK_MASK 0x1u
emilmont	10:3bc89ef62ce7	3660	#define UARTLP_C2_SBK_SHIFT 0
emilmont	10:3bc89ef62ce7	3661	#define UARTLP_C2_RWU_MASK 0x2u
emilmont	10:3bc89ef62ce7	3662	#define UARTLP_C2_RWU_SHIFT 1
emilmont	10:3bc89ef62ce7	3663	#define UARTLP_C2_RE_MASK 0x4u
emilmont	10:3bc89ef62ce7	3664	#define UARTLP_C2_RE_SHIFT 2
emilmont	10:3bc89ef62ce7	3665	#define UARTLP_C2_TE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3666	#define UARTLP_C2_TE_SHIFT 3
emilmont	10:3bc89ef62ce7	3667	#define UARTLP_C2_ILIE_MASK 0x10u
emilmont	10:3bc89ef62ce7	3668	#define UARTLP_C2_ILIE_SHIFT 4
emilmont	10:3bc89ef62ce7	3669	#define UARTLP_C2_RIE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3670	#define UARTLP_C2_RIE_SHIFT 5
emilmont	10:3bc89ef62ce7	3671	#define UARTLP_C2_TCIE_MASK 0x40u
emilmont	10:3bc89ef62ce7	3672	#define UARTLP_C2_TCIE_SHIFT 6
emilmont	10:3bc89ef62ce7	3673	#define UARTLP_C2_TIE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3674	#define UARTLP_C2_TIE_SHIFT 7
emilmont	10:3bc89ef62ce7	3675	/* S1 Bit Fields */
emilmont	10:3bc89ef62ce7	3676	#define UARTLP_S1_PF_MASK 0x1u
emilmont	10:3bc89ef62ce7	3677	#define UARTLP_S1_PF_SHIFT 0
emilmont	10:3bc89ef62ce7	3678	#define UARTLP_S1_FE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3679	#define UARTLP_S1_FE_SHIFT 1
emilmont	10:3bc89ef62ce7	3680	#define UARTLP_S1_NF_MASK 0x4u
emilmont	10:3bc89ef62ce7	3681	#define UARTLP_S1_NF_SHIFT 2
emilmont	10:3bc89ef62ce7	3682	#define UARTLP_S1_OR_MASK 0x8u
emilmont	10:3bc89ef62ce7	3683	#define UARTLP_S1_OR_SHIFT 3
emilmont	10:3bc89ef62ce7	3684	#define UARTLP_S1_IDLE_MASK 0x10u
emilmont	10:3bc89ef62ce7	3685	#define UARTLP_S1_IDLE_SHIFT 4
emilmont	10:3bc89ef62ce7	3686	#define UARTLP_S1_RDRF_MASK 0x20u
emilmont	10:3bc89ef62ce7	3687	#define UARTLP_S1_RDRF_SHIFT 5
emilmont	10:3bc89ef62ce7	3688	#define UARTLP_S1_TC_MASK 0x40u
emilmont	10:3bc89ef62ce7	3689	#define UARTLP_S1_TC_SHIFT 6
emilmont	10:3bc89ef62ce7	3690	#define UARTLP_S1_TDRE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3691	#define UARTLP_S1_TDRE_SHIFT 7
emilmont	10:3bc89ef62ce7	3692	/* S2 Bit Fields */
emilmont	10:3bc89ef62ce7	3693	#define UARTLP_S2_RAF_MASK 0x1u
emilmont	10:3bc89ef62ce7	3694	#define UARTLP_S2_RAF_SHIFT 0
emilmont	10:3bc89ef62ce7	3695	#define UARTLP_S2_LBKDE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3696	#define UARTLP_S2_LBKDE_SHIFT 1
emilmont	10:3bc89ef62ce7	3697	#define UARTLP_S2_BRK13_MASK 0x4u
emilmont	10:3bc89ef62ce7	3698	#define UARTLP_S2_BRK13_SHIFT 2
emilmont	10:3bc89ef62ce7	3699	#define UARTLP_S2_RWUID_MASK 0x8u
emilmont	10:3bc89ef62ce7	3700	#define UARTLP_S2_RWUID_SHIFT 3
emilmont	10:3bc89ef62ce7	3701	#define UARTLP_S2_RXINV_MASK 0x10u
emilmont	10:3bc89ef62ce7	3702	#define UARTLP_S2_RXINV_SHIFT 4
emilmont	10:3bc89ef62ce7	3703	#define UARTLP_S2_MSBF_MASK 0x20u
emilmont	10:3bc89ef62ce7	3704	#define UARTLP_S2_MSBF_SHIFT 5
emilmont	10:3bc89ef62ce7	3705	#define UARTLP_S2_RXEDGIF_MASK 0x40u
emilmont	10:3bc89ef62ce7	3706	#define UARTLP_S2_RXEDGIF_SHIFT 6
emilmont	10:3bc89ef62ce7	3707	#define UARTLP_S2_LBKDIF_MASK 0x80u
emilmont	10:3bc89ef62ce7	3708	#define UARTLP_S2_LBKDIF_SHIFT 7
emilmont	10:3bc89ef62ce7	3709	/* C3 Bit Fields */
emilmont	10:3bc89ef62ce7	3710	#define UARTLP_C3_PEIE_MASK 0x1u
emilmont	10:3bc89ef62ce7	3711	#define UARTLP_C3_PEIE_SHIFT 0
emilmont	10:3bc89ef62ce7	3712	#define UARTLP_C3_FEIE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3713	#define UARTLP_C3_FEIE_SHIFT 1
emilmont	10:3bc89ef62ce7	3714	#define UARTLP_C3_NEIE_MASK 0x4u
emilmont	10:3bc89ef62ce7	3715	#define UARTLP_C3_NEIE_SHIFT 2
emilmont	10:3bc89ef62ce7	3716	#define UARTLP_C3_ORIE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3717	#define UARTLP_C3_ORIE_SHIFT 3
emilmont	10:3bc89ef62ce7	3718	#define UARTLP_C3_TXINV_MASK 0x10u
emilmont	10:3bc89ef62ce7	3719	#define UARTLP_C3_TXINV_SHIFT 4
emilmont	10:3bc89ef62ce7	3720	#define UARTLP_C3_TXDIR_MASK 0x20u
emilmont	10:3bc89ef62ce7	3721	#define UARTLP_C3_TXDIR_SHIFT 5
emilmont	10:3bc89ef62ce7	3722	#define UARTLP_C3_R9T8_MASK 0x40u
emilmont	10:3bc89ef62ce7	3723	#define UARTLP_C3_R9T8_SHIFT 6
emilmont	10:3bc89ef62ce7	3724	#define UARTLP_C3_R8T9_MASK 0x80u
emilmont	10:3bc89ef62ce7	3725	#define UARTLP_C3_R8T9_SHIFT 7
emilmont	10:3bc89ef62ce7	3726	/* D Bit Fields */
emilmont	10:3bc89ef62ce7	3727	#define UARTLP_D_R0T0_MASK 0x1u
emilmont	10:3bc89ef62ce7	3728	#define UARTLP_D_R0T0_SHIFT 0
emilmont	10:3bc89ef62ce7	3729	#define UARTLP_D_R1T1_MASK 0x2u
emilmont	10:3bc89ef62ce7	3730	#define UARTLP_D_R1T1_SHIFT 1
emilmont	10:3bc89ef62ce7	3731	#define UARTLP_D_R2T2_MASK 0x4u
emilmont	10:3bc89ef62ce7	3732	#define UARTLP_D_R2T2_SHIFT 2
emilmont	10:3bc89ef62ce7	3733	#define UARTLP_D_R3T3_MASK 0x8u
emilmont	10:3bc89ef62ce7	3734	#define UARTLP_D_R3T3_SHIFT 3
emilmont	10:3bc89ef62ce7	3735	#define UARTLP_D_R4T4_MASK 0x10u
emilmont	10:3bc89ef62ce7	3736	#define UARTLP_D_R4T4_SHIFT 4
emilmont	10:3bc89ef62ce7	3737	#define UARTLP_D_R5T5_MASK 0x20u
emilmont	10:3bc89ef62ce7	3738	#define UARTLP_D_R5T5_SHIFT 5
emilmont	10:3bc89ef62ce7	3739	#define UARTLP_D_R6T6_MASK 0x40u
emilmont	10:3bc89ef62ce7	3740	#define UARTLP_D_R6T6_SHIFT 6
emilmont	10:3bc89ef62ce7	3741	#define UARTLP_D_R7T7_MASK 0x80u
emilmont	10:3bc89ef62ce7	3742	#define UARTLP_D_R7T7_SHIFT 7
emilmont	10:3bc89ef62ce7	3743	/* MA1 Bit Fields */
emilmont	10:3bc89ef62ce7	3744	#define UARTLP_MA1_MA_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3745	#define UARTLP_MA1_MA_SHIFT 0
emilmont	10:3bc89ef62ce7	3746	#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
emilmont	10:3bc89ef62ce7	3747	/* MA2 Bit Fields */
emilmont	10:3bc89ef62ce7	3748	#define UARTLP_MA2_MA_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3749	#define UARTLP_MA2_MA_SHIFT 0
emilmont	10:3bc89ef62ce7	3750	#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
emilmont	10:3bc89ef62ce7	3751	/* C4 Bit Fields */
emilmont	10:3bc89ef62ce7	3752	#define UARTLP_C4_OSR_MASK 0x1Fu
emilmont	10:3bc89ef62ce7	3753	#define UARTLP_C4_OSR_SHIFT 0
emilmont	10:3bc89ef62ce7	3754	#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
emilmont	10:3bc89ef62ce7	3755	#define UARTLP_C4_M10_MASK 0x20u
emilmont	10:3bc89ef62ce7	3756	#define UARTLP_C4_M10_SHIFT 5
emilmont	10:3bc89ef62ce7	3757	#define UARTLP_C4_MAEN2_MASK 0x40u
emilmont	10:3bc89ef62ce7	3758	#define UARTLP_C4_MAEN2_SHIFT 6
emilmont	10:3bc89ef62ce7	3759	#define UARTLP_C4_MAEN1_MASK 0x80u
emilmont	10:3bc89ef62ce7	3760	#define UARTLP_C4_MAEN1_SHIFT 7
emilmont	10:3bc89ef62ce7	3761	/* C5 Bit Fields */
emilmont	10:3bc89ef62ce7	3762	#define UARTLP_C5_RESYNCDIS_MASK 0x1u
emilmont	10:3bc89ef62ce7	3763	#define UARTLP_C5_RESYNCDIS_SHIFT 0
emilmont	10:3bc89ef62ce7	3764	#define UARTLP_C5_BOTHEDGE_MASK 0x2u
emilmont	10:3bc89ef62ce7	3765	#define UARTLP_C5_BOTHEDGE_SHIFT 1
emilmont	10:3bc89ef62ce7	3766	#define UARTLP_C5_RDMAE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3767	#define UARTLP_C5_RDMAE_SHIFT 5
emilmont	10:3bc89ef62ce7	3768	#define UARTLP_C5_TDMAE_MASK 0x80u
emilmont	10:3bc89ef62ce7	3769	#define UARTLP_C5_TDMAE_SHIFT 7
emilmont	10:3bc89ef62ce7	3770
emilmont	10:3bc89ef62ce7	3771	/**
emilmont	10:3bc89ef62ce7	3772	* @}
emilmont	10:3bc89ef62ce7	3773	/ / end of group UARTLP_Register_Masks */
emilmont	10:3bc89ef62ce7	3774
emilmont	10:3bc89ef62ce7	3775
emilmont	10:3bc89ef62ce7	3776	/* UARTLP - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	3777	/** Peripheral UART0 base address */
emilmont	10:3bc89ef62ce7	3778	#define UART0_BASE (0x4006A000u)
emilmont	10:3bc89ef62ce7	3779	/** Peripheral UART0 base pointer */
emilmont	10:3bc89ef62ce7	3780	#define UART0 ((UARTLP_Type *)UART0_BASE)
emilmont	10:3bc89ef62ce7	3781	/** Array initializer of UARTLP peripheral base pointers */
emilmont	10:3bc89ef62ce7	3782	#define UARTLP_BASES { UART0 }
emilmont	10:3bc89ef62ce7	3783
emilmont	10:3bc89ef62ce7	3784	/**
emilmont	10:3bc89ef62ce7	3785	* @}
emilmont	10:3bc89ef62ce7	3786	/ / end of group UARTLP_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	3787
emilmont	10:3bc89ef62ce7	3788
emilmont	10:3bc89ef62ce7	3789	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3790	-- USB Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3791	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3792
emilmont	10:3bc89ef62ce7	3793	/**
emilmont	10:3bc89ef62ce7	3794	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
emilmont	10:3bc89ef62ce7	3795	* @{
emilmont	10:3bc89ef62ce7	3796	*/
emilmont	10:3bc89ef62ce7	3797
emilmont	10:3bc89ef62ce7	3798	/** USB - Register Layout Typedef */
emilmont	10:3bc89ef62ce7	3799	typedef struct {
emilmont	10:3bc89ef62ce7	3800	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
emilmont	10:3bc89ef62ce7	3801	uint8_t RESERVED_0[3];
emilmont	10:3bc89ef62ce7	3802	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
emilmont	10:3bc89ef62ce7	3803	uint8_t RESERVED_1[3];
emilmont	10:3bc89ef62ce7	3804	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
emilmont	10:3bc89ef62ce7	3805	uint8_t RESERVED_2[3];
emilmont	10:3bc89ef62ce7	3806	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
emilmont	10:3bc89ef62ce7	3807	uint8_t RESERVED_3[3];
emilmont	10:3bc89ef62ce7	3808	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
emilmont	10:3bc89ef62ce7	3809	uint8_t RESERVED_4[3];
emilmont	10:3bc89ef62ce7	3810	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
emilmont	10:3bc89ef62ce7	3811	uint8_t RESERVED_5[3];
emilmont	10:3bc89ef62ce7	3812	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
emilmont	10:3bc89ef62ce7	3813	uint8_t RESERVED_6[3];
emilmont	10:3bc89ef62ce7	3814	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
emilmont	10:3bc89ef62ce7	3815	uint8_t RESERVED_7[99];
emilmont	10:3bc89ef62ce7	3816	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
emilmont	10:3bc89ef62ce7	3817	uint8_t RESERVED_8[3];
emilmont	10:3bc89ef62ce7	3818	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
emilmont	10:3bc89ef62ce7	3819	uint8_t RESERVED_9[3];
emilmont	10:3bc89ef62ce7	3820	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
emilmont	10:3bc89ef62ce7	3821	uint8_t RESERVED_10[3];
emilmont	10:3bc89ef62ce7	3822	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
emilmont	10:3bc89ef62ce7	3823	uint8_t RESERVED_11[3];
emilmont	10:3bc89ef62ce7	3824	__I uint8_t STAT; /*< Status register, offset: 0x90 /
emilmont	10:3bc89ef62ce7	3825	uint8_t RESERVED_12[3];
emilmont	10:3bc89ef62ce7	3826	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
emilmont	10:3bc89ef62ce7	3827	uint8_t RESERVED_13[3];
emilmont	10:3bc89ef62ce7	3828	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
emilmont	10:3bc89ef62ce7	3829	uint8_t RESERVED_14[3];
emilmont	10:3bc89ef62ce7	3830	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
emilmont	10:3bc89ef62ce7	3831	uint8_t RESERVED_15[3];
emilmont	10:3bc89ef62ce7	3832	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
emilmont	10:3bc89ef62ce7	3833	uint8_t RESERVED_16[3];
emilmont	10:3bc89ef62ce7	3834	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
emilmont	10:3bc89ef62ce7	3835	uint8_t RESERVED_17[3];
emilmont	10:3bc89ef62ce7	3836	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
emilmont	10:3bc89ef62ce7	3837	uint8_t RESERVED_18[3];
emilmont	10:3bc89ef62ce7	3838	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
emilmont	10:3bc89ef62ce7	3839	uint8_t RESERVED_19[3];
emilmont	10:3bc89ef62ce7	3840	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
emilmont	10:3bc89ef62ce7	3841	uint8_t RESERVED_20[3];
emilmont	10:3bc89ef62ce7	3842	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
emilmont	10:3bc89ef62ce7	3843	uint8_t RESERVED_21[11];
emilmont	10:3bc89ef62ce7	3844	struct { /* offset: 0xC0, array step: 0x4 */
emilmont	10:3bc89ef62ce7	3845	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
emilmont	10:3bc89ef62ce7	3846	uint8_t RESERVED_0[3];
emilmont	10:3bc89ef62ce7	3847	} ENDPOINT[16];
emilmont	10:3bc89ef62ce7	3848	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
emilmont	10:3bc89ef62ce7	3849	uint8_t RESERVED_22[3];
emilmont	10:3bc89ef62ce7	3850	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
emilmont	10:3bc89ef62ce7	3851	uint8_t RESERVED_23[3];
emilmont	10:3bc89ef62ce7	3852	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
emilmont	10:3bc89ef62ce7	3853	uint8_t RESERVED_24[3];
emilmont	10:3bc89ef62ce7	3854	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
emilmont	10:3bc89ef62ce7	3855	} USB_Type;
emilmont	10:3bc89ef62ce7	3856
emilmont	10:3bc89ef62ce7	3857	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	3858	-- USB Register Masks
emilmont	10:3bc89ef62ce7	3859	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	3860
emilmont	10:3bc89ef62ce7	3861	/**
emilmont	10:3bc89ef62ce7	3862	* @addtogroup USB_Register_Masks USB Register Masks
emilmont	10:3bc89ef62ce7	3863	* @{
emilmont	10:3bc89ef62ce7	3864	*/
emilmont	10:3bc89ef62ce7	3865
emilmont	10:3bc89ef62ce7	3866	/* PERID Bit Fields */
emilmont	10:3bc89ef62ce7	3867	#define USB_PERID_ID_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	3868	#define USB_PERID_ID_SHIFT 0
emilmont	10:3bc89ef62ce7	3869	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
emilmont	10:3bc89ef62ce7	3870	/* IDCOMP Bit Fields */
emilmont	10:3bc89ef62ce7	3871	#define USB_IDCOMP_NID_MASK 0x3Fu
emilmont	10:3bc89ef62ce7	3872	#define USB_IDCOMP_NID_SHIFT 0
emilmont	10:3bc89ef62ce7	3873	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
emilmont	10:3bc89ef62ce7	3874	/* REV Bit Fields */
emilmont	10:3bc89ef62ce7	3875	#define USB_REV_REV_MASK 0xFFu
emilmont	10:3bc89ef62ce7	3876	#define USB_REV_REV_SHIFT 0
emilmont	10:3bc89ef62ce7	3877	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
emilmont	10:3bc89ef62ce7	3878	/* ADDINFO Bit Fields */
emilmont	10:3bc89ef62ce7	3879	#define USB_ADDINFO_IEHOST_MASK 0x1u
emilmont	10:3bc89ef62ce7	3880	#define USB_ADDINFO_IEHOST_SHIFT 0
emilmont	10:3bc89ef62ce7	3881	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
emilmont	10:3bc89ef62ce7	3882	#define USB_ADDINFO_IRQNUM_SHIFT 3
emilmont	10:3bc89ef62ce7	3883	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
emilmont	10:3bc89ef62ce7	3884	/* OTGISTAT Bit Fields */
emilmont	10:3bc89ef62ce7	3885	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
emilmont	10:3bc89ef62ce7	3886	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
emilmont	10:3bc89ef62ce7	3887	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
emilmont	10:3bc89ef62ce7	3888	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
emilmont	10:3bc89ef62ce7	3889	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
emilmont	10:3bc89ef62ce7	3890	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
emilmont	10:3bc89ef62ce7	3891	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
emilmont	10:3bc89ef62ce7	3892	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
emilmont	10:3bc89ef62ce7	3893	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
emilmont	10:3bc89ef62ce7	3894	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
emilmont	10:3bc89ef62ce7	3895	#define USB_OTGISTAT_IDCHG_MASK 0x80u
emilmont	10:3bc89ef62ce7	3896	#define USB_OTGISTAT_IDCHG_SHIFT 7
emilmont	10:3bc89ef62ce7	3897	/* OTGICR Bit Fields */
emilmont	10:3bc89ef62ce7	3898	#define USB_OTGICR_AVBUSEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	3899	#define USB_OTGICR_AVBUSEN_SHIFT 0
emilmont	10:3bc89ef62ce7	3900	#define USB_OTGICR_BSESSEN_MASK 0x4u
emilmont	10:3bc89ef62ce7	3901	#define USB_OTGICR_BSESSEN_SHIFT 2
emilmont	10:3bc89ef62ce7	3902	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	3903	#define USB_OTGICR_SESSVLDEN_SHIFT 3
emilmont	10:3bc89ef62ce7	3904	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	3905	#define USB_OTGICR_LINESTATEEN_SHIFT 5
emilmont	10:3bc89ef62ce7	3906	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	3907	#define USB_OTGICR_ONEMSECEN_SHIFT 6
emilmont	10:3bc89ef62ce7	3908	#define USB_OTGICR_IDEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	3909	#define USB_OTGICR_IDEN_SHIFT 7
emilmont	10:3bc89ef62ce7	3910	/* OTGSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	3911	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
emilmont	10:3bc89ef62ce7	3912	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
emilmont	10:3bc89ef62ce7	3913	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
emilmont	10:3bc89ef62ce7	3914	#define USB_OTGSTAT_BSESSEND_SHIFT 2
emilmont	10:3bc89ef62ce7	3915	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
emilmont	10:3bc89ef62ce7	3916	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
emilmont	10:3bc89ef62ce7	3917	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
emilmont	10:3bc89ef62ce7	3918	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
emilmont	10:3bc89ef62ce7	3919	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	3920	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
emilmont	10:3bc89ef62ce7	3921	#define USB_OTGSTAT_ID_MASK 0x80u
emilmont	10:3bc89ef62ce7	3922	#define USB_OTGSTAT_ID_SHIFT 7
emilmont	10:3bc89ef62ce7	3923	/* OTGCTL Bit Fields */
emilmont	10:3bc89ef62ce7	3924	#define USB_OTGCTL_OTGEN_MASK 0x4u
emilmont	10:3bc89ef62ce7	3925	#define USB_OTGCTL_OTGEN_SHIFT 2
emilmont	10:3bc89ef62ce7	3926	#define USB_OTGCTL_DMLOW_MASK 0x10u
emilmont	10:3bc89ef62ce7	3927	#define USB_OTGCTL_DMLOW_SHIFT 4
emilmont	10:3bc89ef62ce7	3928	#define USB_OTGCTL_DPLOW_MASK 0x20u
emilmont	10:3bc89ef62ce7	3929	#define USB_OTGCTL_DPLOW_SHIFT 5
emilmont	10:3bc89ef62ce7	3930	#define USB_OTGCTL_DPHIGH_MASK 0x80u
emilmont	10:3bc89ef62ce7	3931	#define USB_OTGCTL_DPHIGH_SHIFT 7
emilmont	10:3bc89ef62ce7	3932	/* ISTAT Bit Fields */
emilmont	10:3bc89ef62ce7	3933	#define USB_ISTAT_USBRST_MASK 0x1u
emilmont	10:3bc89ef62ce7	3934	#define USB_ISTAT_USBRST_SHIFT 0
emilmont	10:3bc89ef62ce7	3935	#define USB_ISTAT_ERROR_MASK 0x2u
emilmont	10:3bc89ef62ce7	3936	#define USB_ISTAT_ERROR_SHIFT 1
emilmont	10:3bc89ef62ce7	3937	#define USB_ISTAT_SOFTOK_MASK 0x4u
emilmont	10:3bc89ef62ce7	3938	#define USB_ISTAT_SOFTOK_SHIFT 2
emilmont	10:3bc89ef62ce7	3939	#define USB_ISTAT_TOKDNE_MASK 0x8u
emilmont	10:3bc89ef62ce7	3940	#define USB_ISTAT_TOKDNE_SHIFT 3
emilmont	10:3bc89ef62ce7	3941	#define USB_ISTAT_SLEEP_MASK 0x10u
emilmont	10:3bc89ef62ce7	3942	#define USB_ISTAT_SLEEP_SHIFT 4
emilmont	10:3bc89ef62ce7	3943	#define USB_ISTAT_RESUME_MASK 0x20u
emilmont	10:3bc89ef62ce7	3944	#define USB_ISTAT_RESUME_SHIFT 5
emilmont	10:3bc89ef62ce7	3945	#define USB_ISTAT_ATTACH_MASK 0x40u
emilmont	10:3bc89ef62ce7	3946	#define USB_ISTAT_ATTACH_SHIFT 6
emilmont	10:3bc89ef62ce7	3947	#define USB_ISTAT_STALL_MASK 0x80u
emilmont	10:3bc89ef62ce7	3948	#define USB_ISTAT_STALL_SHIFT 7
emilmont	10:3bc89ef62ce7	3949	/* INTEN Bit Fields */
emilmont	10:3bc89ef62ce7	3950	#define USB_INTEN_USBRSTEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	3951	#define USB_INTEN_USBRSTEN_SHIFT 0
emilmont	10:3bc89ef62ce7	3952	#define USB_INTEN_ERROREN_MASK 0x2u
emilmont	10:3bc89ef62ce7	3953	#define USB_INTEN_ERROREN_SHIFT 1
emilmont	10:3bc89ef62ce7	3954	#define USB_INTEN_SOFTOKEN_MASK 0x4u
emilmont	10:3bc89ef62ce7	3955	#define USB_INTEN_SOFTOKEN_SHIFT 2
emilmont	10:3bc89ef62ce7	3956	#define USB_INTEN_TOKDNEEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	3957	#define USB_INTEN_TOKDNEEN_SHIFT 3
emilmont	10:3bc89ef62ce7	3958	#define USB_INTEN_SLEEPEN_MASK 0x10u
emilmont	10:3bc89ef62ce7	3959	#define USB_INTEN_SLEEPEN_SHIFT 4
emilmont	10:3bc89ef62ce7	3960	#define USB_INTEN_RESUMEEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	3961	#define USB_INTEN_RESUMEEN_SHIFT 5
emilmont	10:3bc89ef62ce7	3962	#define USB_INTEN_ATTACHEN_MASK 0x40u
emilmont	10:3bc89ef62ce7	3963	#define USB_INTEN_ATTACHEN_SHIFT 6
emilmont	10:3bc89ef62ce7	3964	#define USB_INTEN_STALLEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	3965	#define USB_INTEN_STALLEN_SHIFT 7
emilmont	10:3bc89ef62ce7	3966	/* ERRSTAT Bit Fields */
emilmont	10:3bc89ef62ce7	3967	#define USB_ERRSTAT_PIDERR_MASK 0x1u
emilmont	10:3bc89ef62ce7	3968	#define USB_ERRSTAT_PIDERR_SHIFT 0
emilmont	10:3bc89ef62ce7	3969	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
emilmont	10:3bc89ef62ce7	3970	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
emilmont	10:3bc89ef62ce7	3971	#define USB_ERRSTAT_CRC16_MASK 0x4u
emilmont	10:3bc89ef62ce7	3972	#define USB_ERRSTAT_CRC16_SHIFT 2
emilmont	10:3bc89ef62ce7	3973	#define USB_ERRSTAT_DFN8_MASK 0x8u
emilmont	10:3bc89ef62ce7	3974	#define USB_ERRSTAT_DFN8_SHIFT 3
emilmont	10:3bc89ef62ce7	3975	#define USB_ERRSTAT_BTOERR_MASK 0x10u
emilmont	10:3bc89ef62ce7	3976	#define USB_ERRSTAT_BTOERR_SHIFT 4
emilmont	10:3bc89ef62ce7	3977	#define USB_ERRSTAT_DMAERR_MASK 0x20u
emilmont	10:3bc89ef62ce7	3978	#define USB_ERRSTAT_DMAERR_SHIFT 5
emilmont	10:3bc89ef62ce7	3979	#define USB_ERRSTAT_BTSERR_MASK 0x80u
emilmont	10:3bc89ef62ce7	3980	#define USB_ERRSTAT_BTSERR_SHIFT 7
emilmont	10:3bc89ef62ce7	3981	/* ERREN Bit Fields */
emilmont	10:3bc89ef62ce7	3982	#define USB_ERREN_PIDERREN_MASK 0x1u
emilmont	10:3bc89ef62ce7	3983	#define USB_ERREN_PIDERREN_SHIFT 0
emilmont	10:3bc89ef62ce7	3984	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
emilmont	10:3bc89ef62ce7	3985	#define USB_ERREN_CRC5EOFEN_SHIFT 1
emilmont	10:3bc89ef62ce7	3986	#define USB_ERREN_CRC16EN_MASK 0x4u
emilmont	10:3bc89ef62ce7	3987	#define USB_ERREN_CRC16EN_SHIFT 2
emilmont	10:3bc89ef62ce7	3988	#define USB_ERREN_DFN8EN_MASK 0x8u
emilmont	10:3bc89ef62ce7	3989	#define USB_ERREN_DFN8EN_SHIFT 3
emilmont	10:3bc89ef62ce7	3990	#define USB_ERREN_BTOERREN_MASK 0x10u
emilmont	10:3bc89ef62ce7	3991	#define USB_ERREN_BTOERREN_SHIFT 4
emilmont	10:3bc89ef62ce7	3992	#define USB_ERREN_DMAERREN_MASK 0x20u
emilmont	10:3bc89ef62ce7	3993	#define USB_ERREN_DMAERREN_SHIFT 5
emilmont	10:3bc89ef62ce7	3994	#define USB_ERREN_BTSERREN_MASK 0x80u
emilmont	10:3bc89ef62ce7	3995	#define USB_ERREN_BTSERREN_SHIFT 7
emilmont	10:3bc89ef62ce7	3996	/* STAT Bit Fields */
emilmont	10:3bc89ef62ce7	3997	#define USB_STAT_ODD_MASK 0x4u
emilmont	10:3bc89ef62ce7	3998	#define USB_STAT_ODD_SHIFT 2
emilmont	10:3bc89ef62ce7	3999	#define USB_STAT_TX_MASK 0x8u
emilmont	10:3bc89ef62ce7	4000	#define USB_STAT_TX_SHIFT 3
emilmont	10:3bc89ef62ce7	4001	#define USB_STAT_ENDP_MASK 0xF0u
emilmont	10:3bc89ef62ce7	4002	#define USB_STAT_ENDP_SHIFT 4
emilmont	10:3bc89ef62ce7	4003	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
emilmont	10:3bc89ef62ce7	4004	/* CTL Bit Fields */
emilmont	10:3bc89ef62ce7	4005	#define USB_CTL_USBENSOFEN_MASK 0x1u
emilmont	10:3bc89ef62ce7	4006	#define USB_CTL_USBENSOFEN_SHIFT 0
emilmont	10:3bc89ef62ce7	4007	#define USB_CTL_ODDRST_MASK 0x2u
emilmont	10:3bc89ef62ce7	4008	#define USB_CTL_ODDRST_SHIFT 1
emilmont	10:3bc89ef62ce7	4009	#define USB_CTL_RESUME_MASK 0x4u
emilmont	10:3bc89ef62ce7	4010	#define USB_CTL_RESUME_SHIFT 2
emilmont	10:3bc89ef62ce7	4011	#define USB_CTL_HOSTMODEEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	4012	#define USB_CTL_HOSTMODEEN_SHIFT 3
emilmont	10:3bc89ef62ce7	4013	#define USB_CTL_RESET_MASK 0x10u
emilmont	10:3bc89ef62ce7	4014	#define USB_CTL_RESET_SHIFT 4
emilmont	10:3bc89ef62ce7	4015	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
emilmont	10:3bc89ef62ce7	4016	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
emilmont	10:3bc89ef62ce7	4017	#define USB_CTL_SE0_MASK 0x40u
emilmont	10:3bc89ef62ce7	4018	#define USB_CTL_SE0_SHIFT 6
emilmont	10:3bc89ef62ce7	4019	#define USB_CTL_JSTATE_MASK 0x80u
emilmont	10:3bc89ef62ce7	4020	#define USB_CTL_JSTATE_SHIFT 7
emilmont	10:3bc89ef62ce7	4021	/* ADDR Bit Fields */
emilmont	10:3bc89ef62ce7	4022	#define USB_ADDR_ADDR_MASK 0x7Fu
emilmont	10:3bc89ef62ce7	4023	#define USB_ADDR_ADDR_SHIFT 0
emilmont	10:3bc89ef62ce7	4024	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
emilmont	10:3bc89ef62ce7	4025	#define USB_ADDR_LSEN_MASK 0x80u
emilmont	10:3bc89ef62ce7	4026	#define USB_ADDR_LSEN_SHIFT 7
emilmont	10:3bc89ef62ce7	4027	/* BDTPAGE1 Bit Fields */
emilmont	10:3bc89ef62ce7	4028	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
emilmont	10:3bc89ef62ce7	4029	#define USB_BDTPAGE1_BDTBA_SHIFT 1
emilmont	10:3bc89ef62ce7	4030	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
emilmont	10:3bc89ef62ce7	4031	/* FRMNUML Bit Fields */
emilmont	10:3bc89ef62ce7	4032	#define USB_FRMNUML_FRM_MASK 0xFFu
emilmont	10:3bc89ef62ce7	4033	#define USB_FRMNUML_FRM_SHIFT 0
emilmont	10:3bc89ef62ce7	4034	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
emilmont	10:3bc89ef62ce7	4035	/* FRMNUMH Bit Fields */
emilmont	10:3bc89ef62ce7	4036	#define USB_FRMNUMH_FRM_MASK 0x7u
emilmont	10:3bc89ef62ce7	4037	#define USB_FRMNUMH_FRM_SHIFT 0
emilmont	10:3bc89ef62ce7	4038	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
emilmont	10:3bc89ef62ce7	4039	/* TOKEN Bit Fields */
emilmont	10:3bc89ef62ce7	4040	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
emilmont	10:3bc89ef62ce7	4041	#define USB_TOKEN_TOKENENDPT_SHIFT 0
emilmont	10:3bc89ef62ce7	4042	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
emilmont	10:3bc89ef62ce7	4043	#define USB_TOKEN_TOKENPID_MASK 0xF0u
emilmont	10:3bc89ef62ce7	4044	#define USB_TOKEN_TOKENPID_SHIFT 4
emilmont	10:3bc89ef62ce7	4045	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
emilmont	10:3bc89ef62ce7	4046	/* SOFTHLD Bit Fields */
emilmont	10:3bc89ef62ce7	4047	#define USB_SOFTHLD_CNT_MASK 0xFFu
emilmont	10:3bc89ef62ce7	4048	#define USB_SOFTHLD_CNT_SHIFT 0
emilmont	10:3bc89ef62ce7	4049	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
emilmont	10:3bc89ef62ce7	4050	/* BDTPAGE2 Bit Fields */
emilmont	10:3bc89ef62ce7	4051	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
emilmont	10:3bc89ef62ce7	4052	#define USB_BDTPAGE2_BDTBA_SHIFT 0
emilmont	10:3bc89ef62ce7	4053	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
emilmont	10:3bc89ef62ce7	4054	/* BDTPAGE3 Bit Fields */
emilmont	10:3bc89ef62ce7	4055	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
emilmont	10:3bc89ef62ce7	4056	#define USB_BDTPAGE3_BDTBA_SHIFT 0
emilmont	10:3bc89ef62ce7	4057	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
emilmont	10:3bc89ef62ce7	4058	/* ENDPT Bit Fields */
emilmont	10:3bc89ef62ce7	4059	#define USB_ENDPT_EPHSHK_MASK 0x1u
emilmont	10:3bc89ef62ce7	4060	#define USB_ENDPT_EPHSHK_SHIFT 0
emilmont	10:3bc89ef62ce7	4061	#define USB_ENDPT_EPSTALL_MASK 0x2u
emilmont	10:3bc89ef62ce7	4062	#define USB_ENDPT_EPSTALL_SHIFT 1
emilmont	10:3bc89ef62ce7	4063	#define USB_ENDPT_EPTXEN_MASK 0x4u
emilmont	10:3bc89ef62ce7	4064	#define USB_ENDPT_EPTXEN_SHIFT 2
emilmont	10:3bc89ef62ce7	4065	#define USB_ENDPT_EPRXEN_MASK 0x8u
emilmont	10:3bc89ef62ce7	4066	#define USB_ENDPT_EPRXEN_SHIFT 3
emilmont	10:3bc89ef62ce7	4067	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
emilmont	10:3bc89ef62ce7	4068	#define USB_ENDPT_EPCTLDIS_SHIFT 4
emilmont	10:3bc89ef62ce7	4069	#define USB_ENDPT_RETRYDIS_MASK 0x40u
emilmont	10:3bc89ef62ce7	4070	#define USB_ENDPT_RETRYDIS_SHIFT 6
emilmont	10:3bc89ef62ce7	4071	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
emilmont	10:3bc89ef62ce7	4072	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
emilmont	10:3bc89ef62ce7	4073	/* USBCTRL Bit Fields */
emilmont	10:3bc89ef62ce7	4074	#define USB_USBCTRL_PDE_MASK 0x40u
emilmont	10:3bc89ef62ce7	4075	#define USB_USBCTRL_PDE_SHIFT 6
emilmont	10:3bc89ef62ce7	4076	#define USB_USBCTRL_SUSP_MASK 0x80u
emilmont	10:3bc89ef62ce7	4077	#define USB_USBCTRL_SUSP_SHIFT 7
emilmont	10:3bc89ef62ce7	4078	/* OBSERVE Bit Fields */
emilmont	10:3bc89ef62ce7	4079	#define USB_OBSERVE_DMPD_MASK 0x10u
emilmont	10:3bc89ef62ce7	4080	#define USB_OBSERVE_DMPD_SHIFT 4
emilmont	10:3bc89ef62ce7	4081	#define USB_OBSERVE_DPPD_MASK 0x40u
emilmont	10:3bc89ef62ce7	4082	#define USB_OBSERVE_DPPD_SHIFT 6
emilmont	10:3bc89ef62ce7	4083	#define USB_OBSERVE_DPPU_MASK 0x80u
emilmont	10:3bc89ef62ce7	4084	#define USB_OBSERVE_DPPU_SHIFT 7
emilmont	10:3bc89ef62ce7	4085	/* CONTROL Bit Fields */
emilmont	10:3bc89ef62ce7	4086	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
emilmont	10:3bc89ef62ce7	4087	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
emilmont	10:3bc89ef62ce7	4088	/* USBTRC0 Bit Fields */
emilmont	10:3bc89ef62ce7	4089	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
emilmont	10:3bc89ef62ce7	4090	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
emilmont	10:3bc89ef62ce7	4091	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
emilmont	10:3bc89ef62ce7	4092	#define USB_USBTRC0_SYNC_DET_SHIFT 1
emilmont	10:3bc89ef62ce7	4093	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
emilmont	10:3bc89ef62ce7	4094	#define USB_USBTRC0_USBRESMEN_SHIFT 5
emilmont	10:3bc89ef62ce7	4095	#define USB_USBTRC0_USBRESET_MASK 0x80u
emilmont	10:3bc89ef62ce7	4096	#define USB_USBTRC0_USBRESET_SHIFT 7
emilmont	10:3bc89ef62ce7	4097
emilmont	10:3bc89ef62ce7	4098	/**
emilmont	10:3bc89ef62ce7	4099	* @}
emilmont	10:3bc89ef62ce7	4100	/ / end of group USB_Register_Masks */
emilmont	10:3bc89ef62ce7	4101
emilmont	10:3bc89ef62ce7	4102
emilmont	10:3bc89ef62ce7	4103	/* USB - Peripheral instance base addresses */
emilmont	10:3bc89ef62ce7	4104	/** Peripheral USB0 base address */
emilmont	10:3bc89ef62ce7	4105	#define USB0_BASE (0x40072000u)
emilmont	10:3bc89ef62ce7	4106	/** Peripheral USB0 base pointer */
emilmont	10:3bc89ef62ce7	4107	#define USB0 ((USB_Type *)USB0_BASE)
emilmont	10:3bc89ef62ce7	4108	/** Array initializer of USB peripheral base pointers */
emilmont	10:3bc89ef62ce7	4109	#define USB_BASES { USB0 }
emilmont	10:3bc89ef62ce7	4110
emilmont	10:3bc89ef62ce7	4111	/**
emilmont	10:3bc89ef62ce7	4112	* @}
emilmont	10:3bc89ef62ce7	4113	/ / end of group USB_Peripheral_Access_Layer */
emilmont	10:3bc89ef62ce7	4114
emilmont	10:3bc89ef62ce7	4115
emilmont	10:3bc89ef62ce7	4116	/*
emilmont	10:3bc89ef62ce7	4117	** End of section using anonymous unions
emilmont	10:3bc89ef62ce7	4118	*/
emilmont	10:3bc89ef62ce7	4119
emilmont	10:3bc89ef62ce7	4120	#if defined(__ARMCC_VERSION)
emilmont	10:3bc89ef62ce7	4121	#pragma pop
emilmont	10:3bc89ef62ce7	4122	#elif defined(__CWCC__)
emilmont	10:3bc89ef62ce7	4123	#pragma pop
emilmont	10:3bc89ef62ce7	4124	#elif defined(__GNUC__)
emilmont	10:3bc89ef62ce7	4125	/* leave anonymous unions enabled */
emilmont	10:3bc89ef62ce7	4126	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	10:3bc89ef62ce7	4127	#pragma language=default
emilmont	10:3bc89ef62ce7	4128	#else
emilmont	10:3bc89ef62ce7	4129	#error Not supported compiler type
emilmont	10:3bc89ef62ce7	4130	#endif
emilmont	10:3bc89ef62ce7	4131
emilmont	10:3bc89ef62ce7	4132	/**
emilmont	10:3bc89ef62ce7	4133	* @}
emilmont	10:3bc89ef62ce7	4134	/ / end of group Peripheral_access_layer */
emilmont	10:3bc89ef62ce7	4135
emilmont	10:3bc89ef62ce7	4136
emilmont	10:3bc89ef62ce7	4137	/* ----------------------------------------------------------------------------
emilmont	10:3bc89ef62ce7	4138	-- Backward Compatibility
emilmont	10:3bc89ef62ce7	4139	---------------------------------------------------------------------------- */
emilmont	10:3bc89ef62ce7	4140
emilmont	10:3bc89ef62ce7	4141	/**
emilmont	10:3bc89ef62ce7	4142	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
emilmont	10:3bc89ef62ce7	4143	* @{
emilmont	10:3bc89ef62ce7	4144	*/
emilmont	10:3bc89ef62ce7	4145
emilmont	10:3bc89ef62ce7	4146	/* No backward compatibility issues. */
emilmont	10:3bc89ef62ce7	4147
emilmont	10:3bc89ef62ce7	4148	/**
emilmont	10:3bc89ef62ce7	4149	* @}
emilmont	10:3bc89ef62ce7	4150	/ / end of group Backward_Compatibility_Symbols */
emilmont	10:3bc89ef62ce7	4151
emilmont	10:3bc89ef62ce7	4152
emilmont	10:3bc89ef62ce7	4153	#endif /* #if !defined(MKL25Z4_H_) */
emilmont	10:3bc89ef62ce7	4154
emilmont	10:3bc89ef62ce7	4155	/* MKL25Z4.h, eof. */

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Type:	Library
Created:	26 Nov 2015
Imports:	17
Forks:	0
Commits:	638
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_Freescale/TARGET_KL25Z/MKL25Z4.h@13:0645d8841f51, 2013-08-05 (annotated)

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