DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

source/lpc17xx_uart.c@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/**
igorsk	0:1063a091a062	2	* @file : lpc17xx_uart.c
igorsk	0:1063a091a062	3	* @brief : Contains all functions support for UART firmware library on LPC17xx
igorsk	0:1063a091a062	4	* @version : 1.0
igorsk	0:1063a091a062	5	* @date : 18. Mar. 2009
igorsk	0:1063a091a062	6	* @author : HieuNguyen
igorsk	0:1063a091a062	7	**************************************************************************
igorsk	0:1063a091a062	8	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	9	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	10	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	11	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	12	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	13	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	14	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	15	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	16	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	17	* use without further testing or modification.
igorsk	0:1063a091a062	18	**********************************************************************/
igorsk	0:1063a091a062	19
igorsk	0:1063a091a062	20	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	21	/** @addtogroup UART
igorsk	0:1063a091a062	22	* @{
igorsk	0:1063a091a062	23	*/
igorsk	0:1063a091a062	24
igorsk	0:1063a091a062	25	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	26	#include "lpc17xx_uart.h"
igorsk	0:1063a091a062	27	#include "lpc17xx_clkpwr.h"
igorsk	0:1063a091a062	28
igorsk	0:1063a091a062	29	/* If this source file built with example, the LPC17xx FW library configuration
igorsk	0:1063a091a062	30	* file in each example directory ("lpc17xx_libcfg.h") must be included,
igorsk	0:1063a091a062	31	* otherwise the default FW library configuration file must be included instead
igorsk	0:1063a091a062	32	*/
igorsk	0:1063a091a062	33	#ifdef __BUILD_WITH_EXAMPLE__
igorsk	0:1063a091a062	34	#include "lpc17xx_libcfg.h"
igorsk	0:1063a091a062	35	#else
igorsk	0:1063a091a062	36	#include "lpc17xx_libcfg_default.h"
igorsk	0:1063a091a062	37	#endif /* __BUILD_WITH_EXAMPLE__ */
igorsk	0:1063a091a062	38
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40	#ifdef _UART
igorsk	0:1063a091a062	41
igorsk	0:1063a091a062	42	/* Private Types -------------------------------------------------------------- */
igorsk	0:1063a091a062	43	/** @defgroup UART_Private_Types
igorsk	0:1063a091a062	44	* @{
igorsk	0:1063a091a062	45	*/
igorsk	0:1063a091a062	46
igorsk	0:1063a091a062	47	/**
igorsk	0:1063a091a062	48	* @brief UART call-back function type definitions
igorsk	0:1063a091a062	49	*/
igorsk	0:1063a091a062	50	typedef struct {
igorsk	0:1063a091a062	51	fnTxCbs_Type *pfnTxCbs; // Transmit callback
igorsk	0:1063a091a062	52	fnRxCbs_Type *pfnRxCbs; // Receive callback
igorsk	0:1063a091a062	53	fnABCbs_Type *pfnABCbs; // Auto-Baudrate callback
igorsk	0:1063a091a062	54	fnErrCbs_Type *pfnErrCbs; // Error callback
igorsk	0:1063a091a062	55	} UART_CBS_Type;
igorsk	0:1063a091a062	56
igorsk	0:1063a091a062	57	/**
igorsk	0:1063a091a062	58	* @}
igorsk	0:1063a091a062	59	*/
igorsk	0:1063a091a062	60
igorsk	0:1063a091a062	61
igorsk	0:1063a091a062	62	/* Private Variables ---------------------------------------------------------- */
igorsk	0:1063a091a062	63	/** @defgroup UART_Private_Variables
igorsk	0:1063a091a062	64	* @{
igorsk	0:1063a091a062	65	*/
igorsk	0:1063a091a062	66
igorsk	0:1063a091a062	67
igorsk	0:1063a091a062	68	/** Call-back function pointer data */
igorsk	0:1063a091a062	69	UART_CBS_Type uartCbsDat[4] = {
igorsk	0:1063a091a062	70	{NULL, NULL, NULL, NULL},
igorsk	0:1063a091a062	71	{NULL, NULL, NULL, NULL},
igorsk	0:1063a091a062	72	{NULL, NULL, NULL, NULL},
igorsk	0:1063a091a062	73	{NULL, NULL, NULL, NULL},
igorsk	0:1063a091a062	74	};
igorsk	0:1063a091a062	75
igorsk	0:1063a091a062	76	/** UART1 modem status interrupt callback pointer data */
igorsk	0:1063a091a062	77	fnModemCbs_Type *pfnModemCbs = NULL;
igorsk	0:1063a091a062	78
igorsk	0:1063a091a062	79	/**
igorsk	0:1063a091a062	80	* @}
igorsk	0:1063a091a062	81	*/
igorsk	0:1063a091a062	82
igorsk	0:1063a091a062	83
igorsk	0:1063a091a062	84	/* Private Functions ---------------------------------------------------------- */
igorsk	0:1063a091a062	85	/** @defgroup UART_Private_Functions
igorsk	0:1063a091a062	86	* @{
igorsk	0:1063a091a062	87	*/
igorsk	0:1063a091a062	88
igorsk	0:1063a091a062	89	/**
igorsk	0:1063a091a062	90	* @brief Get UART number due to UART peripheral pointer
igorsk	0:1063a091a062	91	* @param[in] UARTx UART pointer
igorsk	0:1063a091a062	92	* @return UART number
igorsk	0:1063a091a062	93	*/
igorsk	0:1063a091a062	94	uint8_t getUartNum(LPC_UART_TypeDef *UARTx) {
igorsk	0:1063a091a062	95	if (UARTx == (LPC_UART_TypeDef *)LPC_UART0) return (0);
igorsk	0:1063a091a062	96	else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1) return (1);
igorsk	0:1063a091a062	97	else if (UARTx == LPC_UART2) return (2);
igorsk	0:1063a091a062	98	else return (3);
igorsk	0:1063a091a062	99	}
igorsk	0:1063a091a062	100
igorsk	0:1063a091a062	101	/*******************************************************************//
igorsk	0:1063a091a062	102	* @brief Determines best dividers to get a target clock rate
igorsk	0:1063a091a062	103	* @param[in] UARTx Pointer to selected UART peripheral, should be
igorsk	0:1063a091a062	104	* UART0, UART1, UART2 or UART3.
igorsk	0:1063a091a062	105	* @param[in] baudrate Desired UART baud rate.
igorsk	0:1063a091a062	106	* @return Error status.
igorsk	0:1063a091a062	107	**********************************************************************/
igorsk	0:1063a091a062	108
igorsk	0:1063a091a062	109	Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
igorsk	0:1063a091a062	110	{
igorsk	0:1063a091a062	111	Status errorStatus = ERROR;
igorsk	0:1063a091a062	112
igorsk	0:1063a091a062	113	uint32_t uClk=0;
igorsk	0:1063a091a062	114	uint32_t calcBaudrate = 0;
igorsk	0:1063a091a062	115	uint32_t temp = 0;
igorsk	0:1063a091a062	116
igorsk	0:1063a091a062	117	uint32_t mulFracDiv, dividerAddFracDiv;
igorsk	0:1063a091a062	118	uint32_t diviser = 0 ;
igorsk	0:1063a091a062	119	uint32_t mulFracDivOptimal = 1;
igorsk	0:1063a091a062	120	uint32_t dividerAddOptimal = 0;
igorsk	0:1063a091a062	121	uint32_t diviserOptimal = 0;
igorsk	0:1063a091a062	122
igorsk	0:1063a091a062	123	uint32_t relativeError = 0;
igorsk	0:1063a091a062	124	uint32_t relativeOptimalError = 100000;
igorsk	0:1063a091a062	125
igorsk	0:1063a091a062	126	/* get UART block clock */
igorsk	0:1063a091a062	127	if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
igorsk	0:1063a091a062	128	{
igorsk	0:1063a091a062	129	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0);
igorsk	0:1063a091a062	130	}
igorsk	0:1063a091a062	131	else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
igorsk	0:1063a091a062	132	{
igorsk	0:1063a091a062	133	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1);
igorsk	0:1063a091a062	134	}
igorsk	0:1063a091a062	135	else if (UARTx == LPC_UART2)
igorsk	0:1063a091a062	136	{
igorsk	0:1063a091a062	137	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2);
igorsk	0:1063a091a062	138	}
igorsk	0:1063a091a062	139	else if (UARTx == LPC_UART3)
igorsk	0:1063a091a062	140	{
igorsk	0:1063a091a062	141	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3);
igorsk	0:1063a091a062	142	}
igorsk	0:1063a091a062	143
igorsk	0:1063a091a062	144
igorsk	0:1063a091a062	145	uClk = uClk >> 4; /* div by 16 */
igorsk	0:1063a091a062	146	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
igorsk	0:1063a091a062	147	* The formula is :
igorsk	0:1063a091a062	148	* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
igorsk	0:1063a091a062	149	* It involves floating point calculations. That's the reason the formulae are adjusted with
igorsk	0:1063a091a062	150	* Multiply and divide method.*/
igorsk	0:1063a091a062	151	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
igorsk	0:1063a091a062	152	* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
igorsk	0:1063a091a062	153	for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++)
igorsk	0:1063a091a062	154	{
igorsk	0:1063a091a062	155	for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++)
igorsk	0:1063a091a062	156	{
igorsk	0:1063a091a062	157	temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
igorsk	0:1063a091a062	158
igorsk	0:1063a091a062	159	diviser = temp / baudrate;
igorsk	0:1063a091a062	160	if ((temp % baudrate) > (baudrate / 2))
igorsk	0:1063a091a062	161	diviser++;
igorsk	0:1063a091a062	162
igorsk	0:1063a091a062	163	if (diviser > 2 && diviser < 65536)
igorsk	0:1063a091a062	164	{
igorsk	0:1063a091a062	165	calcBaudrate = temp / diviser;
igorsk	0:1063a091a062	166
igorsk	0:1063a091a062	167	if (calcBaudrate <= baudrate)
igorsk	0:1063a091a062	168	relativeError = baudrate - calcBaudrate;
igorsk	0:1063a091a062	169	else
igorsk	0:1063a091a062	170	relativeError = calcBaudrate - baudrate;
igorsk	0:1063a091a062	171
igorsk	0:1063a091a062	172	if ((relativeError < relativeOptimalError))
igorsk	0:1063a091a062	173	{
igorsk	0:1063a091a062	174	mulFracDivOptimal = mulFracDiv ;
igorsk	0:1063a091a062	175	dividerAddOptimal = dividerAddFracDiv;
igorsk	0:1063a091a062	176	diviserOptimal = diviser;
igorsk	0:1063a091a062	177	relativeOptimalError = relativeError;
igorsk	0:1063a091a062	178	if (relativeError == 0)
igorsk	0:1063a091a062	179	break;
igorsk	0:1063a091a062	180	}
igorsk	0:1063a091a062	181	} /* End of if */
igorsk	0:1063a091a062	182	} /* end of inner for loop */
igorsk	0:1063a091a062	183	if (relativeError == 0)
igorsk	0:1063a091a062	184	break;
igorsk	0:1063a091a062	185	} /* end of outer for loop */
igorsk	0:1063a091a062	186
igorsk	0:1063a091a062	187	if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100))
igorsk	0:1063a091a062	188	{
igorsk	0:1063a091a062	189	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	190	{
igorsk	0:1063a091a062	191	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	192	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
igorsk	0:1063a091a062	193	((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
igorsk	0:1063a091a062	194	/* Then reset DLAB bit */
igorsk	0:1063a091a062	195	((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
igorsk	0:1063a091a062	196	((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
igorsk	0:1063a091a062	197	\| UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
igorsk	0:1063a091a062	198	}
igorsk	0:1063a091a062	199	else
igorsk	0:1063a091a062	200	{
igorsk	0:1063a091a062	201	UARTx->LCR \|= UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	202	UARTx->/DLIER./DLM = UART_LOAD_DLM(diviserOptimal);
igorsk	0:1063a091a062	203	UARTx->/RBTHDLR./DLL = UART_LOAD_DLL(diviserOptimal);
igorsk	0:1063a091a062	204	/* Then reset DLAB bit */
igorsk	0:1063a091a062	205	UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
igorsk	0:1063a091a062	206	UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
igorsk	0:1063a091a062	207	\| UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
igorsk	0:1063a091a062	208	}
igorsk	0:1063a091a062	209	errorStatus = SUCCESS;
igorsk	0:1063a091a062	210	}
igorsk	0:1063a091a062	211
igorsk	0:1063a091a062	212	return errorStatus;
igorsk	0:1063a091a062	213	}
igorsk	0:1063a091a062	214
igorsk	0:1063a091a062	215	/*******************************************************************//
igorsk	0:1063a091a062	216	* @brief General UART interrupt handler and router
igorsk	0:1063a091a062	217	* @param[in] UARTx Selected UART peripheral, should be UART0..3
igorsk	0:1063a091a062	218	* @return None
igorsk	0:1063a091a062	219	*
igorsk	0:1063a091a062	220	* Note:
igorsk	0:1063a091a062	221	* - Handles transmit, receive, and status interrupts for the UART.
igorsk	0:1063a091a062	222	* Based on the interrupt status, routes the interrupt to the
igorsk	0:1063a091a062	223	* respective call-back to be handled by the user application using
igorsk	0:1063a091a062	224	* this driver.
igorsk	0:1063a091a062	225	* - If callback is not installed, corresponding interrupt will be disabled
igorsk	0:1063a091a062	226	* - All these interrupt source below will be checked:
igorsk	0:1063a091a062	227	* - Transmit Holding Register Empty.
igorsk	0:1063a091a062	228	* - Received Data Available and Character Time Out.
igorsk	0:1063a091a062	229	* - Receive Line Status (not implemented)
igorsk	0:1063a091a062	230	* - End of auto-baud interrupt (not implemented)
igorsk	0:1063a091a062	231	* - Auto-Baudrate Time-Out interrupt (not implemented)
igorsk	0:1063a091a062	232	* - Modem Status interrupt (UART0 Modem functionality)
igorsk	0:1063a091a062	233	* - CTS signal transition interrupt (UART0 Modem functionality)
igorsk	0:1063a091a062	234	**********************************************************************/
igorsk	0:1063a091a062	235	void UART_GenIntHandler(LPC_UART_TypeDef *UARTx)
igorsk	0:1063a091a062	236	{
igorsk	0:1063a091a062	237	uint8_t pUart, modemsts;
igorsk	0:1063a091a062	238	uint32_t intsrc, tmp, tmp1;
igorsk	0:1063a091a062	239
igorsk	0:1063a091a062	240	pUart = getUartNum(UARTx);
igorsk	0:1063a091a062	241
igorsk	0:1063a091a062	242	/* Determine the interrupt source */
igorsk	0:1063a091a062	243	intsrc = UARTx->IIR;
igorsk	0:1063a091a062	244	tmp = intsrc & UART_IIR_INTID_MASK;
igorsk	0:1063a091a062	245
igorsk	0:1063a091a062	246	/*
igorsk	0:1063a091a062	247	* In case of using UART1 with full modem,
igorsk	0:1063a091a062	248	* interrupt ID = 0 that means modem status interrupt has been detected
igorsk	0:1063a091a062	249	*/
igorsk	0:1063a091a062	250	if (pUart == 1) {
igorsk	0:1063a091a062	251	if (tmp == 0){
igorsk	0:1063a091a062	252	// Check Modem status
igorsk	0:1063a091a062	253	modemsts = LPC_UART1->MSR & UART1_MSR_BITMASK;
igorsk	0:1063a091a062	254	// Call modem status call-back
igorsk	0:1063a091a062	255	if (pfnModemCbs != NULL){
igorsk	0:1063a091a062	256	pfnModemCbs(modemsts);
igorsk	0:1063a091a062	257	}
igorsk	0:1063a091a062	258	// disable modem status interrupt and CTS status change interrupt
igorsk	0:1063a091a062	259	// if its callback is not installed
igorsk	0:1063a091a062	260	else {
igorsk	0:1063a091a062	261	LPC_UART1->IER &= ~(UART1_IER_MSINT_EN \| UART1_IER_CTSINT_EN);
igorsk	0:1063a091a062	262	}
igorsk	0:1063a091a062	263	}
igorsk	0:1063a091a062	264	}
igorsk	0:1063a091a062	265
igorsk	0:1063a091a062	266	// Receive Line Status
igorsk	0:1063a091a062	267	if (tmp == UART_IIR_INTID_RLS){
igorsk	0:1063a091a062	268	// Check line status
igorsk	0:1063a091a062	269	tmp1 = UARTx->LSR;
igorsk	0:1063a091a062	270	// Mask out the Receive Ready and Transmit Holding empty status
igorsk	0:1063a091a062	271	tmp1 &= (UART_LSR_OE \| UART_LSR_PE \| UART_LSR_FE \
igorsk	0:1063a091a062	272	\| UART_LSR_BI \| UART_LSR_RXFE);
igorsk	0:1063a091a062	273	// If any error exist
igorsk	0:1063a091a062	274	if (tmp1) {
igorsk	0:1063a091a062	275	// Call Call-back function with error input value
igorsk	0:1063a091a062	276	if (uartCbsDat[pUart].pfnErrCbs != NULL) {
igorsk	0:1063a091a062	277	uartCbsDat[pUart].pfnErrCbs(tmp1);
igorsk	0:1063a091a062	278	}
igorsk	0:1063a091a062	279	// Disable interrupt if its call-back is not install
igorsk	0:1063a091a062	280	else {
igorsk	0:1063a091a062	281	UARTx->IER &= ~(UART_IER_RLSINT_EN);
igorsk	0:1063a091a062	282	}
igorsk	0:1063a091a062	283	}
igorsk	0:1063a091a062	284	}
igorsk	0:1063a091a062	285
igorsk	0:1063a091a062	286	// Receive Data Available or Character time-out
igorsk	0:1063a091a062	287	if ((tmp == UART_IIR_INTID_RDA) \|\| (tmp == UART_IIR_INTID_CTI)){
igorsk	0:1063a091a062	288	// Call Rx call back function
igorsk	0:1063a091a062	289	if (uartCbsDat[pUart].pfnRxCbs != NULL) {
igorsk	0:1063a091a062	290	uartCbsDat[pUart].pfnRxCbs();
igorsk	0:1063a091a062	291	}
igorsk	0:1063a091a062	292	// Disable interrupt if its call-back is not install
igorsk	0:1063a091a062	293	else {
igorsk	0:1063a091a062	294	UARTx->IER &= ~(UART_IER_RBRINT_EN);
igorsk	0:1063a091a062	295	}
igorsk	0:1063a091a062	296	}
igorsk	0:1063a091a062	297
igorsk	0:1063a091a062	298	// Transmit Holding Empty
igorsk	0:1063a091a062	299	if (tmp == UART_IIR_INTID_THRE){
igorsk	0:1063a091a062	300	// Call Tx call back function
igorsk	0:1063a091a062	301	if (uartCbsDat[pUart].pfnTxCbs != NULL) {
igorsk	0:1063a091a062	302	uartCbsDat[pUart].pfnTxCbs();
igorsk	0:1063a091a062	303	}
igorsk	0:1063a091a062	304	// Disable interrupt if its call-back is not install
igorsk	0:1063a091a062	305	else {
igorsk	0:1063a091a062	306	UARTx->IER &= ~(UART_IER_THREINT_EN);
igorsk	0:1063a091a062	307	}
igorsk	0:1063a091a062	308	}
igorsk	0:1063a091a062	309
igorsk	0:1063a091a062	310	intsrc &= (UART_IIR_ABEO_INT \| UART_IIR_ABTO_INT);
igorsk	0:1063a091a062	311	// Check if End of auto-baudrate interrupt or Auto baudrate time out
igorsk	0:1063a091a062	312	if (intsrc){
igorsk	0:1063a091a062	313	// Clear interrupt pending
igorsk	0:1063a091a062	314	UARTx->ACR \|= ((intsrc & UART_IIR_ABEO_INT) ? UART_ACR_ABEOINT_CLR : 0) \
igorsk	0:1063a091a062	315	\| ((intsrc & UART_IIR_ABTO_INT) ? UART_ACR_ABTOINT_CLR : 0);
igorsk	0:1063a091a062	316	if (uartCbsDat[pUart].pfnABCbs != NULL) {
igorsk	0:1063a091a062	317	uartCbsDat[pUart].pfnABCbs(intsrc);
igorsk	0:1063a091a062	318	} else {
igorsk	0:1063a091a062	319	// Disable End of AB interrupt
igorsk	0:1063a091a062	320	UARTx->IER &= ~(UART_IER_ABEOINT_EN \| UART_IER_ABTOINT_EN);
igorsk	0:1063a091a062	321	}
igorsk	0:1063a091a062	322	}
igorsk	0:1063a091a062	323	}
igorsk	0:1063a091a062	324
igorsk	0:1063a091a062	325	/**
igorsk	0:1063a091a062	326	* @}
igorsk	0:1063a091a062	327	*/
igorsk	0:1063a091a062	328
igorsk	0:1063a091a062	329
igorsk	0:1063a091a062	330	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	331	/** @addtogroup UART_Public_Functions
igorsk	0:1063a091a062	332	* @{
igorsk	0:1063a091a062	333	*/
igorsk	0:1063a091a062	334
igorsk	0:1063a091a062	335	/*******************************************************************//
igorsk	0:1063a091a062	336	* @brief De-initializes the UARTx peripheral registers to their
igorsk	0:1063a091a062	337	* default reset values.
igorsk	0:1063a091a062	338	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	339	* UART2 or UART3.
igorsk	0:1063a091a062	340	* @return None
igorsk	0:1063a091a062	341	**********************************************************************/
igorsk	0:1063a091a062	342	void UART_DeInit(LPC_UART_TypeDef* UARTx)
igorsk	0:1063a091a062	343	{
igorsk	0:1063a091a062	344	// For debug mode
igorsk	0:1063a091a062	345	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	346
igorsk	0:1063a091a062	347	UART_TxCmd(UARTx, DISABLE);
igorsk	0:1063a091a062	348
igorsk	0:1063a091a062	349	#ifdef _UART0
igorsk	0:1063a091a062	350	if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
igorsk	0:1063a091a062	351	{
igorsk	0:1063a091a062	352	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	353	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
igorsk	0:1063a091a062	354	}
igorsk	0:1063a091a062	355	#endif
igorsk	0:1063a091a062	356
igorsk	0:1063a091a062	357	#ifdef _UART1
igorsk	0:1063a091a062	358	if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
igorsk	0:1063a091a062	359	{
igorsk	0:1063a091a062	360	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	361	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
igorsk	0:1063a091a062	362	}
igorsk	0:1063a091a062	363	#endif
igorsk	0:1063a091a062	364
igorsk	0:1063a091a062	365	#ifdef _UART2
igorsk	0:1063a091a062	366	if (UARTx == LPC_UART2)
igorsk	0:1063a091a062	367	{
igorsk	0:1063a091a062	368	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	369	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
igorsk	0:1063a091a062	370	}
igorsk	0:1063a091a062	371	#endif
igorsk	0:1063a091a062	372
igorsk	0:1063a091a062	373	#ifdef _UART3
igorsk	0:1063a091a062	374	if (UARTx == LPC_UART3)
igorsk	0:1063a091a062	375	{
igorsk	0:1063a091a062	376	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	377	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
igorsk	0:1063a091a062	378	}
igorsk	0:1063a091a062	379	#endif
igorsk	0:1063a091a062	380	}
igorsk	0:1063a091a062	381
igorsk	0:1063a091a062	382	/******************************************************************//
igorsk	0:1063a091a062	383	* @brief Initializes the UARTx peripheral according to the specified
igorsk	0:1063a091a062	384	* parameters in the UART_ConfigStruct.
igorsk	0:1063a091a062	385	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	386	* UART2 or UART3.
igorsk	0:1063a091a062	387	* @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure
igorsk	0:1063a091a062	388	* that contains the configuration information for the
igorsk	0:1063a091a062	389	* specified UART peripheral.
igorsk	0:1063a091a062	390	* @return None
igorsk	0:1063a091a062	391	*********************************************************************/
igorsk	0:1063a091a062	392	void UART_Init(LPC_UART_TypeDef UARTx, UART_CFG_Type UART_ConfigStruct)
igorsk	0:1063a091a062	393	{
igorsk	0:1063a091a062	394	uint32_t tmp;
igorsk	0:1063a091a062	395
igorsk	0:1063a091a062	396	// For debug mode
igorsk	0:1063a091a062	397	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	398	CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));
igorsk	0:1063a091a062	399	CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));
igorsk	0:1063a091a062	400	CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));
igorsk	0:1063a091a062	401
igorsk	0:1063a091a062	402	#ifdef _UART0
igorsk	0:1063a091a062	403	if(UARTx == (LPC_UART_TypeDef *)LPC_UART0)
igorsk	0:1063a091a062	404	{
igorsk	0:1063a091a062	405	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	406	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
igorsk	0:1063a091a062	407	}
igorsk	0:1063a091a062	408	#endif
igorsk	0:1063a091a062	409
igorsk	0:1063a091a062	410	#ifdef _UART1
igorsk	0:1063a091a062	411	if(UARTx == (LPC_UART_TypeDef *)LPC_UART1)
igorsk	0:1063a091a062	412	{
igorsk	0:1063a091a062	413	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	414	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
igorsk	0:1063a091a062	415	}
igorsk	0:1063a091a062	416	#endif
igorsk	0:1063a091a062	417
igorsk	0:1063a091a062	418	#ifdef _UART2
igorsk	0:1063a091a062	419	if(UARTx == LPC_UART2)
igorsk	0:1063a091a062	420	{
igorsk	0:1063a091a062	421	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	422	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
igorsk	0:1063a091a062	423	}
igorsk	0:1063a091a062	424	#endif
igorsk	0:1063a091a062	425
igorsk	0:1063a091a062	426	#ifdef _UART3
igorsk	0:1063a091a062	427	if(UARTx == LPC_UART3)
igorsk	0:1063a091a062	428	{
igorsk	0:1063a091a062	429	/* Set up clock and power for UART module */
igorsk	0:1063a091a062	430	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
igorsk	0:1063a091a062	431	}
igorsk	0:1063a091a062	432	#endif
igorsk	0:1063a091a062	433
igorsk	0:1063a091a062	434	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	435	{
igorsk	0:1063a091a062	436	/* FIFOs are empty */
igorsk	0:1063a091a062	437	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = ( UART_FCR_FIFO_EN \
igorsk	0:1063a091a062	438	\| UART_FCR_RX_RS \| UART_FCR_TX_RS);
igorsk	0:1063a091a062	439	// Disable FIFO
igorsk	0:1063a091a062	440	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = 0;
igorsk	0:1063a091a062	441
igorsk	0:1063a091a062	442	// Dummy reading
igorsk	0:1063a091a062	443	while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR)
igorsk	0:1063a091a062	444	{
igorsk	0:1063a091a062	445	tmp = ((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/RBR;
igorsk	0:1063a091a062	446	}
igorsk	0:1063a091a062	447
igorsk	0:1063a091a062	448	((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN;
igorsk	0:1063a091a062	449	// Wait for current transmit complete
igorsk	0:1063a091a062	450	while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE));
igorsk	0:1063a091a062	451	// Disable Tx
igorsk	0:1063a091a062	452	((LPC_UART1_TypeDef *)UARTx)->TER = 0;
igorsk	0:1063a091a062	453
igorsk	0:1063a091a062	454	// Disable interrupt
igorsk	0:1063a091a062	455	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER = 0;
igorsk	0:1063a091a062	456	// Set LCR to default state
igorsk	0:1063a091a062	457	((LPC_UART1_TypeDef *)UARTx)->LCR = 0;
igorsk	0:1063a091a062	458	// Set ACR to default state
igorsk	0:1063a091a062	459	((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
igorsk	0:1063a091a062	460	// Set Modem Control to default state
igorsk	0:1063a091a062	461	((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
igorsk	0:1063a091a062	462	// Set RS485 control to default state
igorsk	0:1063a091a062	463	((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0;
igorsk	0:1063a091a062	464	// Set RS485 delay timer to default state
igorsk	0:1063a091a062	465	((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0;
igorsk	0:1063a091a062	466	// Set RS485 addr match to default state
igorsk	0:1063a091a062	467	((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0;
igorsk	0:1063a091a062	468	//Dummy Reading to Clear Status
igorsk	0:1063a091a062	469	tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
igorsk	0:1063a091a062	470	tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR;
igorsk	0:1063a091a062	471	}
igorsk	0:1063a091a062	472	else
igorsk	0:1063a091a062	473	{
igorsk	0:1063a091a062	474	/* FIFOs are empty */
igorsk	0:1063a091a062	475	UARTx->/IIFCR./FCR = ( UART_FCR_FIFO_EN \| UART_FCR_RX_RS \| UART_FCR_TX_RS);
igorsk	0:1063a091a062	476	// Disable FIFO
igorsk	0:1063a091a062	477	UARTx->/IIFCR./FCR = 0;
igorsk	0:1063a091a062	478
igorsk	0:1063a091a062	479	// Dummy reading
igorsk	0:1063a091a062	480	while (UARTx->LSR & UART_LSR_RDR)
igorsk	0:1063a091a062	481	{
igorsk	0:1063a091a062	482	tmp = UARTx->/RBTHDLR./RBR;
igorsk	0:1063a091a062	483	}
igorsk	0:1063a091a062	484
igorsk	0:1063a091a062	485	UARTx->TER = UART_TER_TXEN;
igorsk	0:1063a091a062	486	// Wait for current transmit complete
igorsk	0:1063a091a062	487	while (!(UARTx->LSR & UART_LSR_THRE));
igorsk	0:1063a091a062	488	// Disable Tx
igorsk	0:1063a091a062	489	UARTx->TER = 0;
igorsk	0:1063a091a062	490
igorsk	0:1063a091a062	491	// Disable interrupt
igorsk	0:1063a091a062	492	UARTx->/DLIER./IER = 0;
igorsk	0:1063a091a062	493	// Set LCR to default state
igorsk	0:1063a091a062	494	UARTx->LCR = 0;
igorsk	0:1063a091a062	495	// Set ACR to default state
igorsk	0:1063a091a062	496	UARTx->ACR = 0;
igorsk	0:1063a091a062	497	// Dummy reading
igorsk	0:1063a091a062	498	tmp = UARTx->LSR;
igorsk	0:1063a091a062	499	}
igorsk	0:1063a091a062	500
igorsk	0:1063a091a062	501	if (UARTx == LPC_UART3)
igorsk	0:1063a091a062	502	{
igorsk	0:1063a091a062	503	// Set IrDA to default state
igorsk	0:1063a091a062	504	UARTx->ICR = 0;
igorsk	0:1063a091a062	505	}
igorsk	0:1063a091a062	506
igorsk	0:1063a091a062	507	// Set Line Control register ----------------------------
igorsk	0:1063a091a062	508
igorsk	0:1063a091a062	509	uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
igorsk	0:1063a091a062	510
igorsk	0:1063a091a062	511	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	512	{
igorsk	0:1063a091a062	513	tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN \| UART_LCR_BREAK_EN)) \
igorsk	0:1063a091a062	514	& UART_LCR_BITMASK;
igorsk	0:1063a091a062	515	}
igorsk	0:1063a091a062	516	else
igorsk	0:1063a091a062	517	{
igorsk	0:1063a091a062	518	tmp = (UARTx->LCR & (UART_LCR_DLAB_EN \| UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
igorsk	0:1063a091a062	519	}
igorsk	0:1063a091a062	520
igorsk	0:1063a091a062	521	switch (UART_ConfigStruct->Databits){
igorsk	0:1063a091a062	522	case UART_DATABIT_5:
igorsk	0:1063a091a062	523	tmp \|= UART_LCR_WLEN5;
igorsk	0:1063a091a062	524	break;
igorsk	0:1063a091a062	525	case UART_DATABIT_6:
igorsk	0:1063a091a062	526	tmp \|= UART_LCR_WLEN6;
igorsk	0:1063a091a062	527	break;
igorsk	0:1063a091a062	528	case UART_DATABIT_7:
igorsk	0:1063a091a062	529	tmp \|= UART_LCR_WLEN7;
igorsk	0:1063a091a062	530	break;
igorsk	0:1063a091a062	531	case UART_DATABIT_8:
igorsk	0:1063a091a062	532	default:
igorsk	0:1063a091a062	533	tmp \|= UART_LCR_WLEN8;
igorsk	0:1063a091a062	534	break;
igorsk	0:1063a091a062	535	}
igorsk	0:1063a091a062	536
igorsk	0:1063a091a062	537	if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
igorsk	0:1063a091a062	538	{
igorsk	0:1063a091a062	539	// Do nothing...
igorsk	0:1063a091a062	540	}
igorsk	0:1063a091a062	541	else
igorsk	0:1063a091a062	542	{
igorsk	0:1063a091a062	543	tmp \|= UART_LCR_PARITY_EN;
igorsk	0:1063a091a062	544	switch (UART_ConfigStruct->Parity)
igorsk	0:1063a091a062	545	{
igorsk	0:1063a091a062	546	case UART_PARITY_ODD:
igorsk	0:1063a091a062	547	tmp \|= UART_LCR_PARITY_ODD;
igorsk	0:1063a091a062	548	break;
igorsk	0:1063a091a062	549
igorsk	0:1063a091a062	550	case UART_PARITY_EVEN:
igorsk	0:1063a091a062	551	tmp \|= UART_LCR_PARITY_EVEN;
igorsk	0:1063a091a062	552	break;
igorsk	0:1063a091a062	553
igorsk	0:1063a091a062	554	case UART_PARITY_SP_1:
igorsk	0:1063a091a062	555	tmp \|= UART_LCR_PARITY_F_1;
igorsk	0:1063a091a062	556	break;
igorsk	0:1063a091a062	557
igorsk	0:1063a091a062	558	case UART_PARITY_SP_0:
igorsk	0:1063a091a062	559	tmp \|= UART_LCR_PARITY_F_0;
igorsk	0:1063a091a062	560	break;
igorsk	0:1063a091a062	561	default:
igorsk	0:1063a091a062	562	break;
igorsk	0:1063a091a062	563	}
igorsk	0:1063a091a062	564	}
igorsk	0:1063a091a062	565
igorsk	0:1063a091a062	566	switch (UART_ConfigStruct->Stopbits){
igorsk	0:1063a091a062	567	case UART_STOPBIT_2:
igorsk	0:1063a091a062	568	tmp \|= UART_LCR_STOPBIT_SEL;
igorsk	0:1063a091a062	569	break;
igorsk	0:1063a091a062	570	case UART_STOPBIT_1:
igorsk	0:1063a091a062	571	default:
igorsk	0:1063a091a062	572	// Do no thing
igorsk	0:1063a091a062	573	break;
igorsk	0:1063a091a062	574	}
igorsk	0:1063a091a062	575
igorsk	0:1063a091a062	576
igorsk	0:1063a091a062	577	// Write back to LCR, configure FIFO and Disable Tx
igorsk	0:1063a091a062	578	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	579	{
igorsk	0:1063a091a062	580	((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
igorsk	0:1063a091a062	581	}
igorsk	0:1063a091a062	582	else
igorsk	0:1063a091a062	583	{
igorsk	0:1063a091a062	584	UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
igorsk	0:1063a091a062	585	}
igorsk	0:1063a091a062	586	}
igorsk	0:1063a091a062	587
igorsk	0:1063a091a062	588
igorsk	0:1063a091a062	589	/***************************************************************************//
igorsk	0:1063a091a062	590	* @brief Fills each UART_InitStruct member with its default value:
igorsk	0:1063a091a062	591	* 9600 bps
igorsk	0:1063a091a062	592	* 8-bit data
igorsk	0:1063a091a062	593	* 1 Stopbit
igorsk	0:1063a091a062	594	* None Parity
igorsk	0:1063a091a062	595	* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure
igorsk	0:1063a091a062	596	* which will be initialized.
igorsk	0:1063a091a062	597	* @return None
igorsk	0:1063a091a062	598	*******************************************************************************/
igorsk	0:1063a091a062	599	void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
igorsk	0:1063a091a062	600	{
igorsk	0:1063a091a062	601	UART_InitStruct->Baud_rate = 9600;
igorsk	0:1063a091a062	602	UART_InitStruct->Databits = UART_DATABIT_8;
igorsk	0:1063a091a062	603	UART_InitStruct->Parity = UART_PARITY_NONE;
igorsk	0:1063a091a062	604	UART_InitStruct->Stopbits = UART_STOPBIT_1;
igorsk	0:1063a091a062	605	}
igorsk	0:1063a091a062	606
igorsk	0:1063a091a062	607
igorsk	0:1063a091a062	608	/*******************************************************************//
igorsk	0:1063a091a062	609	* @brief Transmit a single data through UART peripheral
igorsk	0:1063a091a062	610	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	611	* UART2 or UART3.
igorsk	0:1063a091a062	612	* @param[in] Data Data to transmit (must be 8-bit long)
igorsk	0:1063a091a062	613	* @return none
igorsk	0:1063a091a062	614	**********************************************************************/
igorsk	0:1063a091a062	615	void UART_SendData(LPC_UART_TypeDef* UARTx, uint8_t Data)
igorsk	0:1063a091a062	616	{
igorsk	0:1063a091a062	617	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	618
igorsk	0:1063a091a062	619	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	620	{
igorsk	0:1063a091a062	621	((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
igorsk	0:1063a091a062	622	}
igorsk	0:1063a091a062	623	else
igorsk	0:1063a091a062	624	{
igorsk	0:1063a091a062	625	UARTx->/RBTHDLR./THR = Data & UART_THR_MASKBIT;
igorsk	0:1063a091a062	626	}
igorsk	0:1063a091a062	627
igorsk	0:1063a091a062	628	}
igorsk	0:1063a091a062	629
igorsk	0:1063a091a062	630
igorsk	0:1063a091a062	631	/*******************************************************************//
igorsk	0:1063a091a062	632	* @brief Receive a single data from UART peripheral
igorsk	0:1063a091a062	633	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	634	* UART2 or UART3.
igorsk	0:1063a091a062	635	* @return Data received
igorsk	0:1063a091a062	636	**********************************************************************/
igorsk	0:1063a091a062	637	uint8_t UART_ReceiveData(LPC_UART_TypeDef* UARTx)
igorsk	0:1063a091a062	638	{
igorsk	0:1063a091a062	639	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	640
igorsk	0:1063a091a062	641	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	642	{
igorsk	0:1063a091a062	643	return (((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/RBR & UART_RBR_MASKBIT);
igorsk	0:1063a091a062	644	}
igorsk	0:1063a091a062	645	else
igorsk	0:1063a091a062	646	{
igorsk	0:1063a091a062	647	return (UARTx->/RBTHDLR./RBR & UART_RBR_MASKBIT);
igorsk	0:1063a091a062	648	}
igorsk	0:1063a091a062	649	}
igorsk	0:1063a091a062	650
igorsk	0:1063a091a062	651
igorsk	0:1063a091a062	652	/*******************************************************************//
igorsk	0:1063a091a062	653	* @brief Force BREAK character on UART line, output pin UARTx TXD is
igorsk	0:1063a091a062	654	forced to logic 0.
igorsk	0:1063a091a062	655	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	656	* UART2 or UART3.
igorsk	0:1063a091a062	657	* @return none
igorsk	0:1063a091a062	658	**********************************************************************/
igorsk	0:1063a091a062	659	void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
igorsk	0:1063a091a062	660	{
igorsk	0:1063a091a062	661	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	662
igorsk	0:1063a091a062	663	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	664	{
igorsk	0:1063a091a062	665	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_BREAK_EN;
igorsk	0:1063a091a062	666	}
igorsk	0:1063a091a062	667	else
igorsk	0:1063a091a062	668	{
igorsk	0:1063a091a062	669	UARTx->LCR \|= UART_LCR_BREAK_EN;
igorsk	0:1063a091a062	670	}
igorsk	0:1063a091a062	671	}
igorsk	0:1063a091a062	672
igorsk	0:1063a091a062	673
igorsk	0:1063a091a062	674	#ifdef _UART3
igorsk	0:1063a091a062	675
igorsk	0:1063a091a062	676	/*******************************************************************//
igorsk	0:1063a091a062	677	* @brief Enable or disable inverting serial input function of IrDA
igorsk	0:1063a091a062	678	* on UART peripheral.
igorsk	0:1063a091a062	679	* @param[in] UARTx UART peripheral selected, should be UART3 (only)
igorsk	0:1063a091a062	680	* @param[in] NewState New state of inverting serial input, should be:
igorsk	0:1063a091a062	681	* - ENABLE: Enable this function.
igorsk	0:1063a091a062	682	* - DISABLE: Disable this function.
igorsk	0:1063a091a062	683	* @return none
igorsk	0:1063a091a062	684	**********************************************************************/
igorsk	0:1063a091a062	685	void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
igorsk	0:1063a091a062	686	{
igorsk	0:1063a091a062	687	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
igorsk	0:1063a091a062	688	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	689
igorsk	0:1063a091a062	690	if (NewState == ENABLE)
igorsk	0:1063a091a062	691	{
igorsk	0:1063a091a062	692	UARTx->ICR \|= UART_ICR_IRDAINV;
igorsk	0:1063a091a062	693	}
igorsk	0:1063a091a062	694	else if (NewState == DISABLE)
igorsk	0:1063a091a062	695	{
igorsk	0:1063a091a062	696	UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
igorsk	0:1063a091a062	697	}
igorsk	0:1063a091a062	698	}
igorsk	0:1063a091a062	699
igorsk	0:1063a091a062	700
igorsk	0:1063a091a062	701	/*******************************************************************//
igorsk	0:1063a091a062	702	* @brief Enable or disable IrDA function on UART peripheral.
igorsk	0:1063a091a062	703	* @param[in] UARTx UART peripheral selected, should be UART3 (only)
igorsk	0:1063a091a062	704	* @param[in] NewState New state of IrDA function, should be:
igorsk	0:1063a091a062	705	* - ENABLE: Enable this function.
igorsk	0:1063a091a062	706	* - DISABLE: Disable this function.
igorsk	0:1063a091a062	707	* @return none
igorsk	0:1063a091a062	708	**********************************************************************/
igorsk	0:1063a091a062	709	void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
igorsk	0:1063a091a062	710	{
igorsk	0:1063a091a062	711	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
igorsk	0:1063a091a062	712	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	713
igorsk	0:1063a091a062	714	if (NewState == ENABLE)
igorsk	0:1063a091a062	715	{
igorsk	0:1063a091a062	716	UARTx->ICR \|= UART_ICR_IRDAEN;
igorsk	0:1063a091a062	717	}
igorsk	0:1063a091a062	718	else
igorsk	0:1063a091a062	719	{
igorsk	0:1063a091a062	720	UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
igorsk	0:1063a091a062	721	}
igorsk	0:1063a091a062	722	}
igorsk	0:1063a091a062	723
igorsk	0:1063a091a062	724
igorsk	0:1063a091a062	725	/*******************************************************************//
igorsk	0:1063a091a062	726	* @brief Configure Pulse divider for IrDA function on UART peripheral.
igorsk	0:1063a091a062	727	* @param[in] UARTx UART peripheral selected, should be UART3 (only)
igorsk	0:1063a091a062	728	* @param[in] PulseDiv Pulse Divider value from Peripheral clock,
igorsk	0:1063a091a062	729	* should be one of the following:
igorsk	0:1063a091a062	730	- UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk
igorsk	0:1063a091a062	731	- UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk
igorsk	0:1063a091a062	732	- UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk
igorsk	0:1063a091a062	733	- UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk
igorsk	0:1063a091a062	734	- UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk
igorsk	0:1063a091a062	735	- UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk
igorsk	0:1063a091a062	736	- UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
igorsk	0:1063a091a062	737	- UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
igorsk	0:1063a091a062	738
igorsk	0:1063a091a062	739	* @return none
igorsk	0:1063a091a062	740	**********************************************************************/
igorsk	0:1063a091a062	741	void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
igorsk	0:1063a091a062	742	{
igorsk	0:1063a091a062	743	uint32_t tmp, tmp1;
igorsk	0:1063a091a062	744	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
igorsk	0:1063a091a062	745	CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));
igorsk	0:1063a091a062	746
igorsk	0:1063a091a062	747	tmp1 = UART_ICR_PULSEDIV(PulseDiv);
igorsk	0:1063a091a062	748	tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));
igorsk	0:1063a091a062	749	tmp \|= tmp1 \| UART_ICR_FIXPULSE_EN;
igorsk	0:1063a091a062	750	UARTx->ICR = tmp & UART_ICR_BITMASK;
igorsk	0:1063a091a062	751	}
igorsk	0:1063a091a062	752
igorsk	0:1063a091a062	753	#endif
igorsk	0:1063a091a062	754
igorsk	0:1063a091a062	755
igorsk	0:1063a091a062	756	/******************************************************************//
igorsk	0:1063a091a062	757	* @brief Enable or disable specified UART interrupt.
igorsk	0:1063a091a062	758	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	759	* UART2 or UART3.
igorsk	0:1063a091a062	760	* @param[in] UARTIntCfg Specifies the interrupt flag,
igorsk	0:1063a091a062	761	* should be one of the following:
igorsk	0:1063a091a062	762	- UART_INTCFG_RBR : RBR Interrupt enable
igorsk	0:1063a091a062	763	- UART_INTCFG_THRE : THR Interrupt enable
igorsk	0:1063a091a062	764	- UART_INTCFG_RLS : RX line status interrupt enable
igorsk	0:1063a091a062	765	- UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
igorsk	0:1063a091a062	766	- UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
igorsk	0:1063a091a062	767	- UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
igorsk	0:1063a091a062	768	- UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
igorsk	0:1063a091a062	769	* @param[in] NewState New state of specified UART interrupt type,
igorsk	0:1063a091a062	770	* should be:
igorsk	0:1063a091a062	771	* - ENALBE: Enable this UART interrupt type.
igorsk	0:1063a091a062	772	* - DISALBE: Disable this UART interrupt type.
igorsk	0:1063a091a062	773	* @return None
igorsk	0:1063a091a062	774	*********************************************************************/
igorsk	0:1063a091a062	775	void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
igorsk	0:1063a091a062	776	{
igorsk	0:1063a091a062	777	uint32_t tmp=0;
igorsk	0:1063a091a062	778
igorsk	0:1063a091a062	779	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	780	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	781
igorsk	0:1063a091a062	782	switch(UARTIntCfg){
igorsk	0:1063a091a062	783	case UART_INTCFG_RBR:
igorsk	0:1063a091a062	784	tmp = UART_IER_RBRINT_EN;
igorsk	0:1063a091a062	785	break;
igorsk	0:1063a091a062	786	case UART_INTCFG_THRE:
igorsk	0:1063a091a062	787	tmp = UART_IER_THREINT_EN;
igorsk	0:1063a091a062	788	break;
igorsk	0:1063a091a062	789	case UART_INTCFG_RLS:
igorsk	0:1063a091a062	790	tmp = UART_IER_RLSINT_EN;
igorsk	0:1063a091a062	791	break;
igorsk	0:1063a091a062	792	case UART1_INTCFG_MS:
igorsk	0:1063a091a062	793	tmp = UART1_IER_MSINT_EN;
igorsk	0:1063a091a062	794	break;
igorsk	0:1063a091a062	795	case UART1_INTCFG_CTS:
igorsk	0:1063a091a062	796	tmp = UART1_IER_CTSINT_EN;
igorsk	0:1063a091a062	797	break;
igorsk	0:1063a091a062	798	case UART_INTCFG_ABEO:
igorsk	0:1063a091a062	799	tmp = UART_IER_ABEOINT_EN;
igorsk	0:1063a091a062	800	break;
igorsk	0:1063a091a062	801	case UART_INTCFG_ABTO:
igorsk	0:1063a091a062	802	tmp = UART_IER_ABTOINT_EN;
igorsk	0:1063a091a062	803	break;
igorsk	0:1063a091a062	804	}
igorsk	0:1063a091a062	805
igorsk	0:1063a091a062	806	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
igorsk	0:1063a091a062	807	{
igorsk	0:1063a091a062	808	CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) \|\| (PARAM_UART1_INTCFG(UARTIntCfg)));
igorsk	0:1063a091a062	809	}
igorsk	0:1063a091a062	810	else
igorsk	0:1063a091a062	811	{
igorsk	0:1063a091a062	812	CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));
igorsk	0:1063a091a062	813	}
igorsk	0:1063a091a062	814
igorsk	0:1063a091a062	815	if (NewState == ENABLE)
igorsk	0:1063a091a062	816	{
igorsk	0:1063a091a062	817	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
igorsk	0:1063a091a062	818	{
igorsk	0:1063a091a062	819	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER \|= tmp;
igorsk	0:1063a091a062	820	}
igorsk	0:1063a091a062	821	else
igorsk	0:1063a091a062	822	{
igorsk	0:1063a091a062	823	UARTx->/DLIER./IER \|= tmp;
igorsk	0:1063a091a062	824	}
igorsk	0:1063a091a062	825	}
igorsk	0:1063a091a062	826	else
igorsk	0:1063a091a062	827	{
igorsk	0:1063a091a062	828	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
igorsk	0:1063a091a062	829	{
igorsk	0:1063a091a062	830	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;
igorsk	0:1063a091a062	831	}
igorsk	0:1063a091a062	832	else
igorsk	0:1063a091a062	833	{
igorsk	0:1063a091a062	834	UARTx->/DLIER./IER &= (~tmp) & UART_IER_BITMASK;
igorsk	0:1063a091a062	835	}
igorsk	0:1063a091a062	836	}
igorsk	0:1063a091a062	837	}
igorsk	0:1063a091a062	838
igorsk	0:1063a091a062	839
igorsk	0:1063a091a062	840	/******************************************************************//
igorsk	0:1063a091a062	841	* @brief Get current value of Line Status register in UART peripheral.
igorsk	0:1063a091a062	842	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	843	* UART2 or UART3.
igorsk	0:1063a091a062	844	* @return Current value of Line Status register in UART peripheral.
igorsk	0:1063a091a062	845	* Note: The return value of this function must be ANDed with each member in
igorsk	0:1063a091a062	846	* UART_LS_Type enumeration to determine current flag status
igorsk	0:1063a091a062	847	* corresponding to each Line status type. Because some flags in
igorsk	0:1063a091a062	848	* Line Status register will be cleared after reading, the next reading
igorsk	0:1063a091a062	849	* Line Status register could not be correct. So this function used to
igorsk	0:1063a091a062	850	* read Line status register in one time only, then the return value
igorsk	0:1063a091a062	851	* used to check all flags.
igorsk	0:1063a091a062	852	*********************************************************************/
igorsk	0:1063a091a062	853	uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
igorsk	0:1063a091a062	854	{
igorsk	0:1063a091a062	855	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	856
igorsk	0:1063a091a062	857	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	858	{
igorsk	0:1063a091a062	859	return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
igorsk	0:1063a091a062	860	}
igorsk	0:1063a091a062	861	else
igorsk	0:1063a091a062	862	{
igorsk	0:1063a091a062	863	return ((UARTx->LSR) & UART_LSR_BITMASK);
igorsk	0:1063a091a062	864	}
igorsk	0:1063a091a062	865	}
igorsk	0:1063a091a062	866
igorsk	0:1063a091a062	867	/*******************************************************************//
igorsk	0:1063a091a062	868	* @brief Check whether if UART is busy or not
igorsk	0:1063a091a062	869	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	870	* UART2 or UART3.
igorsk	0:1063a091a062	871	* @return RESET if UART is not busy, otherwise return SET.
igorsk	0:1063a091a062	872	**********************************************************************/
igorsk	0:1063a091a062	873	FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
igorsk	0:1063a091a062	874	{
igorsk	0:1063a091a062	875	if (UARTx->LSR & UART_LSR_TEMT){
igorsk	0:1063a091a062	876	return RESET;
igorsk	0:1063a091a062	877	} else {
igorsk	0:1063a091a062	878	return SET;
igorsk	0:1063a091a062	879	}
igorsk	0:1063a091a062	880	}
igorsk	0:1063a091a062	881
igorsk	0:1063a091a062	882
igorsk	0:1063a091a062	883	/*******************************************************************//
igorsk	0:1063a091a062	884	* @brief Configure FIFO function on selected UART peripheral
igorsk	0:1063a091a062	885	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	886	* UART2 or UART3.
igorsk	0:1063a091a062	887	* @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that
igorsk	0:1063a091a062	888	* contains specified information about FIFO configuration
igorsk	0:1063a091a062	889	* @return none
igorsk	0:1063a091a062	890	**********************************************************************/
igorsk	0:1063a091a062	891	void UART_FIFOConfig(LPC_UART_TypeDef UARTx, UART_FIFO_CFG_Type FIFOCfg)
igorsk	0:1063a091a062	892	{
igorsk	0:1063a091a062	893	uint8_t tmp = 0;
igorsk	0:1063a091a062	894
igorsk	0:1063a091a062	895	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	896	CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));
igorsk	0:1063a091a062	897	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));
igorsk	0:1063a091a062	898	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));
igorsk	0:1063a091a062	899	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));
igorsk	0:1063a091a062	900
igorsk	0:1063a091a062	901	tmp \|= UART_FCR_FIFO_EN;
igorsk	0:1063a091a062	902	switch (FIFOCfg->FIFO_Level){
igorsk	0:1063a091a062	903	case UART_FIFO_TRGLEV0:
igorsk	0:1063a091a062	904	tmp \|= UART_FCR_TRG_LEV0;
igorsk	0:1063a091a062	905	break;
igorsk	0:1063a091a062	906	case UART_FIFO_TRGLEV1:
igorsk	0:1063a091a062	907	tmp \|= UART_FCR_TRG_LEV1;
igorsk	0:1063a091a062	908	break;
igorsk	0:1063a091a062	909	case UART_FIFO_TRGLEV2:
igorsk	0:1063a091a062	910	tmp \|= UART_FCR_TRG_LEV2;
igorsk	0:1063a091a062	911	break;
igorsk	0:1063a091a062	912	case UART_FIFO_TRGLEV3:
igorsk	0:1063a091a062	913	default:
igorsk	0:1063a091a062	914	tmp \|= UART_FCR_TRG_LEV3;
igorsk	0:1063a091a062	915	break;
igorsk	0:1063a091a062	916	}
igorsk	0:1063a091a062	917
igorsk	0:1063a091a062	918	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
igorsk	0:1063a091a062	919	{
igorsk	0:1063a091a062	920	tmp \|= UART_FCR_TX_RS;
igorsk	0:1063a091a062	921	}
igorsk	0:1063a091a062	922	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
igorsk	0:1063a091a062	923	{
igorsk	0:1063a091a062	924	tmp \|= UART_FCR_RX_RS;
igorsk	0:1063a091a062	925	}
igorsk	0:1063a091a062	926	if (FIFOCfg->FIFO_DMAMode == ENABLE)
igorsk	0:1063a091a062	927	{
igorsk	0:1063a091a062	928	tmp \|= UART_FCR_DMAMODE_SEL;
igorsk	0:1063a091a062	929	}
igorsk	0:1063a091a062	930
igorsk	0:1063a091a062	931
igorsk	0:1063a091a062	932	//write to FIFO control register
igorsk	0:1063a091a062	933	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	934	{
igorsk	0:1063a091a062	935	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
igorsk	0:1063a091a062	936	}
igorsk	0:1063a091a062	937	else
igorsk	0:1063a091a062	938	{
igorsk	0:1063a091a062	939	UARTx->/IIFCR./FCR = tmp & UART_FCR_BITMASK;
igorsk	0:1063a091a062	940	}
igorsk	0:1063a091a062	941
igorsk	0:1063a091a062	942	}
igorsk	0:1063a091a062	943
igorsk	0:1063a091a062	944
igorsk	0:1063a091a062	945	/***************************************************************************//
igorsk	0:1063a091a062	946	* @brief Fills each UART_FIFOInitStruct member with its default value:
igorsk	0:1063a091a062	947	* - FIFO_DMAMode = DISABLE
igorsk	0:1063a091a062	948	* - FIFO_Level = UART_FIFO_TRGLEV0
igorsk	0:1063a091a062	949	* - FIFO_ResetRxBuf = ENABLE
igorsk	0:1063a091a062	950	* - FIFO_ResetTxBuf = ENABLE
igorsk	0:1063a091a062	951	* - FIFO_State = ENABLE
igorsk	0:1063a091a062	952
igorsk	0:1063a091a062	953	* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
igorsk	0:1063a091a062	954	* which will be initialized.
igorsk	0:1063a091a062	955	* @return None
igorsk	0:1063a091a062	956	*******************************************************************************/
igorsk	0:1063a091a062	957	void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
igorsk	0:1063a091a062	958	{
igorsk	0:1063a091a062	959	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
igorsk	0:1063a091a062	960	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
igorsk	0:1063a091a062	961	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
igorsk	0:1063a091a062	962	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
igorsk	0:1063a091a062	963	}
igorsk	0:1063a091a062	964
igorsk	0:1063a091a062	965
igorsk	0:1063a091a062	966	/*******************************************************************//
igorsk	0:1063a091a062	967	* @brief Start/Stop Auto Baudrate activity
igorsk	0:1063a091a062	968	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	969	* UART2 or UART3.
igorsk	0:1063a091a062	970	* @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that
igorsk	0:1063a091a062	971	* contains specified information about UART
igorsk	0:1063a091a062	972	* auto baudrate configuration
igorsk	0:1063a091a062	973	* @param[in] NewState New State of Auto baudrate activity, should be:
igorsk	0:1063a091a062	974	* - ENABLE: Start this activity
igorsk	0:1063a091a062	975	* - DISABLE: Stop this activity
igorsk	0:1063a091a062	976	* Note: Auto-baudrate mode enable bit will be cleared once this mode
igorsk	0:1063a091a062	977	* completed.
igorsk	0:1063a091a062	978	* @return none
igorsk	0:1063a091a062	979	**********************************************************************/
igorsk	0:1063a091a062	980	void UART_ABCmd(LPC_UART_TypeDef UARTx, UART_AB_CFG_Type ABConfigStruct, \
igorsk	0:1063a091a062	981	FunctionalState NewState)
igorsk	0:1063a091a062	982	{
igorsk	0:1063a091a062	983	uint32_t tmp;
igorsk	0:1063a091a062	984
igorsk	0:1063a091a062	985	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	986	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	987
igorsk	0:1063a091a062	988	tmp = 0;
igorsk	0:1063a091a062	989	if (NewState == ENABLE) {
igorsk	0:1063a091a062	990	if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){
igorsk	0:1063a091a062	991	tmp \|= UART_ACR_MODE;
igorsk	0:1063a091a062	992	}
igorsk	0:1063a091a062	993	if (ABConfigStruct->AutoRestart == ENABLE){
igorsk	0:1063a091a062	994	tmp \|= UART_ACR_AUTO_RESTART;
igorsk	0:1063a091a062	995	}
igorsk	0:1063a091a062	996	}
igorsk	0:1063a091a062	997
igorsk	0:1063a091a062	998	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	999	{
igorsk	0:1063a091a062	1000	if (NewState == ENABLE)
igorsk	0:1063a091a062	1001	{
igorsk	0:1063a091a062	1002	// Clear DLL and DLM value
igorsk	0:1063a091a062	1003	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	1004	((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
igorsk	0:1063a091a062	1005	((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
igorsk	0:1063a091a062	1006	((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	1007	// FDR value must be reset to default value
igorsk	0:1063a091a062	1008	((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
igorsk	0:1063a091a062	1009	((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START \| tmp;
igorsk	0:1063a091a062	1010	}
igorsk	0:1063a091a062	1011	else
igorsk	0:1063a091a062	1012	{
igorsk	0:1063a091a062	1013	((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
igorsk	0:1063a091a062	1014	}
igorsk	0:1063a091a062	1015	}
igorsk	0:1063a091a062	1016	else
igorsk	0:1063a091a062	1017	{
igorsk	0:1063a091a062	1018	if (NewState == ENABLE)
igorsk	0:1063a091a062	1019	{
igorsk	0:1063a091a062	1020	// Clear DLL and DLM value
igorsk	0:1063a091a062	1021	UARTx->LCR \|= UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	1022	UARTx->DLL = 0;
igorsk	0:1063a091a062	1023	UARTx->DLM = 0;
igorsk	0:1063a091a062	1024	UARTx->LCR &= ~UART_LCR_DLAB_EN;
igorsk	0:1063a091a062	1025	// FDR value must be reset to default value
igorsk	0:1063a091a062	1026	UARTx->FDR = 0x10;
igorsk	0:1063a091a062	1027	UARTx->ACR = UART_ACR_START \| tmp;
igorsk	0:1063a091a062	1028	}
igorsk	0:1063a091a062	1029	else
igorsk	0:1063a091a062	1030	{
igorsk	0:1063a091a062	1031	UARTx->ACR = 0;
igorsk	0:1063a091a062	1032	}
igorsk	0:1063a091a062	1033	}
igorsk	0:1063a091a062	1034	}
igorsk	0:1063a091a062	1035
igorsk	0:1063a091a062	1036
igorsk	0:1063a091a062	1037	/*******************************************************************//
igorsk	0:1063a091a062	1038	* @brief Enable/Disable transmission on UART TxD pin
igorsk	0:1063a091a062	1039	* @param[in] UARTx UART peripheral selected, should be UART0, UART1,
igorsk	0:1063a091a062	1040	* UART2 or UART3.
igorsk	0:1063a091a062	1041	* @param[in] NewState New State of Tx transmission function, should be:
igorsk	0:1063a091a062	1042	* - ENABLE: Enable this function
igorsk	0:1063a091a062	1043	- DISABLE: Disable this function
igorsk	0:1063a091a062	1044	* @return none
igorsk	0:1063a091a062	1045	**********************************************************************/
igorsk	0:1063a091a062	1046	void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
igorsk	0:1063a091a062	1047	{
igorsk	0:1063a091a062	1048	CHECK_PARAM(PARAM_UARTx(UARTx));
igorsk	0:1063a091a062	1049	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	1050
igorsk	0:1063a091a062	1051	if (NewState == ENABLE)
igorsk	0:1063a091a062	1052	{
igorsk	0:1063a091a062	1053	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	1054	{
igorsk	0:1063a091a062	1055	((LPC_UART1_TypeDef *)UARTx)->TER \|= UART_TER_TXEN;
igorsk	0:1063a091a062	1056	}
igorsk	0:1063a091a062	1057	else
igorsk	0:1063a091a062	1058	{
igorsk	0:1063a091a062	1059	UARTx->TER \|= UART_TER_TXEN;
igorsk	0:1063a091a062	1060	}
igorsk	0:1063a091a062	1061	}
igorsk	0:1063a091a062	1062	else
igorsk	0:1063a091a062	1063	{
igorsk	0:1063a091a062	1064	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
igorsk	0:1063a091a062	1065	{
igorsk	0:1063a091a062	1066	((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
igorsk	0:1063a091a062	1067	}
igorsk	0:1063a091a062	1068	else
igorsk	0:1063a091a062	1069	{
igorsk	0:1063a091a062	1070	UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
igorsk	0:1063a091a062	1071	}
igorsk	0:1063a091a062	1072	}
igorsk	0:1063a091a062	1073	}
igorsk	0:1063a091a062	1074
igorsk	0:1063a091a062	1075	#ifdef _UART1
igorsk	0:1063a091a062	1076
igorsk	0:1063a091a062	1077	/*******************************************************************//
igorsk	0:1063a091a062	1078	* @brief Force pin DTR/RTS corresponding to given state (Full modem mode)
igorsk	0:1063a091a062	1079	* @param[in] UARTx UART1 (only)
igorsk	0:1063a091a062	1080	* @param[in] Pin Pin that NewState will be applied to, should be:
igorsk	0:1063a091a062	1081	* - UART1_MODEM_PIN_DTR: DTR pin.
igorsk	0:1063a091a062	1082	* - UART1_MODEM_PIN_RTS: RTS pin.
igorsk	0:1063a091a062	1083	* @param[in] NewState New State of DTR/RTS pin, should be:
igorsk	0:1063a091a062	1084	* - INACTIVE: Force the pin to inactive signal.
igorsk	0:1063a091a062	1085	- ACTIVE: Force the pin to active signal.
igorsk	0:1063a091a062	1086	* @return none
igorsk	0:1063a091a062	1087	**********************************************************************/
igorsk	0:1063a091a062	1088	void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
igorsk	0:1063a091a062	1089	UART1_SignalState NewState)
igorsk	0:1063a091a062	1090	{
igorsk	0:1063a091a062	1091	uint8_t tmp = 0;
igorsk	0:1063a091a062	1092
igorsk	0:1063a091a062	1093	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
igorsk	0:1063a091a062	1094	CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));
igorsk	0:1063a091a062	1095	CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));
igorsk	0:1063a091a062	1096
igorsk	0:1063a091a062	1097	switch (Pin){
igorsk	0:1063a091a062	1098	case UART1_MODEM_PIN_DTR:
igorsk	0:1063a091a062	1099	tmp = UART1_MCR_DTR_CTRL;
igorsk	0:1063a091a062	1100	break;
igorsk	0:1063a091a062	1101	case UART1_MODEM_PIN_RTS:
igorsk	0:1063a091a062	1102	tmp = UART1_MCR_RTS_CTRL;
igorsk	0:1063a091a062	1103	break;
igorsk	0:1063a091a062	1104	default:
igorsk	0:1063a091a062	1105	break;
igorsk	0:1063a091a062	1106	}
igorsk	0:1063a091a062	1107
igorsk	0:1063a091a062	1108	if (NewState == ACTIVE){
igorsk	0:1063a091a062	1109	UARTx->MCR \|= tmp;
igorsk	0:1063a091a062	1110	} else {
igorsk	0:1063a091a062	1111	UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
igorsk	0:1063a091a062	1112	}
igorsk	0:1063a091a062	1113	}
igorsk	0:1063a091a062	1114
igorsk	0:1063a091a062	1115
igorsk	0:1063a091a062	1116	/*******************************************************************//
igorsk	0:1063a091a062	1117	* @brief Configure Full Modem mode for UART peripheral
igorsk	0:1063a091a062	1118	* @param[in] UARTx UART1 (only)
igorsk	0:1063a091a062	1119	* @param[in] Mode Full Modem mode, should be:
igorsk	0:1063a091a062	1120	* - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
igorsk	0:1063a091a062	1121	* - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
igorsk	0:1063a091a062	1122	* - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
igorsk	0:1063a091a062	1123	* @param[in] NewState New State of this mode, should be:
igorsk	0:1063a091a062	1124	* - ENABLE: Enable this mode.
igorsk	0:1063a091a062	1125	- DISABLE: Disable this mode.
igorsk	0:1063a091a062	1126	* @return none
igorsk	0:1063a091a062	1127	**********************************************************************/
igorsk	0:1063a091a062	1128	void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
igorsk	0:1063a091a062	1129	FunctionalState NewState)
igorsk	0:1063a091a062	1130	{
igorsk	0:1063a091a062	1131	uint8_t tmp=0;
igorsk	0:1063a091a062	1132
igorsk	0:1063a091a062	1133	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
igorsk	0:1063a091a062	1134	CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));
igorsk	0:1063a091a062	1135	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
igorsk	0:1063a091a062	1136
igorsk	0:1063a091a062	1137	switch(Mode){
igorsk	0:1063a091a062	1138	case UART1_MODEM_MODE_LOOPBACK:
igorsk	0:1063a091a062	1139	tmp = UART1_MCR_LOOPB_EN;
igorsk	0:1063a091a062	1140	break;
igorsk	0:1063a091a062	1141	case UART1_MODEM_MODE_AUTO_RTS:
igorsk	0:1063a091a062	1142	tmp = UART1_MCR_AUTO_RTS_EN;
igorsk	0:1063a091a062	1143	break;
igorsk	0:1063a091a062	1144	case UART1_MODEM_MODE_AUTO_CTS:
igorsk	0:1063a091a062	1145	tmp = UART1_MCR_AUTO_CTS_EN;
igorsk	0:1063a091a062	1146	break;
igorsk	0:1063a091a062	1147	default:
igorsk	0:1063a091a062	1148	break;
igorsk	0:1063a091a062	1149	}
igorsk	0:1063a091a062	1150
igorsk	0:1063a091a062	1151	if (NewState == ENABLE)
igorsk	0:1063a091a062	1152	{
igorsk	0:1063a091a062	1153	UARTx->MCR \|= tmp;
igorsk	0:1063a091a062	1154	}
igorsk	0:1063a091a062	1155	else
igorsk	0:1063a091a062	1156	{
igorsk	0:1063a091a062	1157	UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
igorsk	0:1063a091a062	1158	}
igorsk	0:1063a091a062	1159	}
igorsk	0:1063a091a062	1160
igorsk	0:1063a091a062	1161
igorsk	0:1063a091a062	1162	/*******************************************************************//
igorsk	0:1063a091a062	1163	* @brief Get current status of modem status register
igorsk	0:1063a091a062	1164	* @param[in] UARTx UART1 (only)
igorsk	0:1063a091a062	1165	* @return Current value of modem status register
igorsk	0:1063a091a062	1166	* Note: The return value of this function must be ANDed with each member
igorsk	0:1063a091a062	1167	* UART_MODEM_STAT_type enumeration to determine current flag status
igorsk	0:1063a091a062	1168	* corresponding to each modem flag status. Because some flags in
igorsk	0:1063a091a062	1169	* modem status register will be cleared after reading, the next reading
igorsk	0:1063a091a062	1170	* modem register could not be correct. So this function used to
igorsk	0:1063a091a062	1171	* read modem status register in one time only, then the return value
igorsk	0:1063a091a062	1172	* used to check all flags.
igorsk	0:1063a091a062	1173	**********************************************************************/
igorsk	0:1063a091a062	1174	uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
igorsk	0:1063a091a062	1175	{
igorsk	0:1063a091a062	1176	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
igorsk	0:1063a091a062	1177	return ((UARTx->MSR) & UART1_MSR_BITMASK);
igorsk	0:1063a091a062	1178	}
igorsk	0:1063a091a062	1179
igorsk	0:1063a091a062	1180
igorsk	0:1063a091a062	1181	/*******************************************************************//
igorsk	0:1063a091a062	1182	* @brief Configure UART peripheral in RS485 mode according to the specified
igorsk	0:1063a091a062	1183	* parameters in the RS485ConfigStruct.
igorsk	0:1063a091a062	1184	* @param[in] UARTx UART1 (only)
igorsk	0:1063a091a062	1185	* @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
igorsk	0:1063a091a062	1186	* that contains the configuration information for specified UART
igorsk	0:1063a091a062	1187	* in RS485 mode.
igorsk	0:1063a091a062	1188	* @return None
igorsk	0:1063a091a062	1189	**********************************************************************/
igorsk	0:1063a091a062	1190	void UART_RS485Config(LPC_UART1_TypeDef UARTx, UART1_RS485_CTRLCFG_Type RS485ConfigStruct)
igorsk	0:1063a091a062	1191	{
igorsk	0:1063a091a062	1192	uint32_t tmp;
igorsk	0:1063a091a062	1193
igorsk	0:1063a091a062	1194	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
igorsk	0:1063a091a062	1195	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));
igorsk	0:1063a091a062	1196	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));
igorsk	0:1063a091a062	1197	CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));
igorsk	0:1063a091a062	1198	CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));
igorsk	0:1063a091a062	1199	CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));
igorsk	0:1063a091a062	1200	CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));
igorsk	0:1063a091a062	1201	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));
igorsk	0:1063a091a062	1202	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));
igorsk	0:1063a091a062	1203
igorsk	0:1063a091a062	1204	tmp = 0;
igorsk	0:1063a091a062	1205	// If Auto Direction Control is enabled - This function is used in Master mode
igorsk	0:1063a091a062	1206	if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
igorsk	0:1063a091a062	1207	{
igorsk	0:1063a091a062	1208	tmp \|= UART1_RS485CTRL_DCTRL_EN;
igorsk	0:1063a091a062	1209
igorsk	0:1063a091a062	1210	// Set polar
igorsk	0:1063a091a062	1211	if (RS485ConfigStruct->DirCtrlPol_Level == SET)
igorsk	0:1063a091a062	1212	{
igorsk	0:1063a091a062	1213	tmp \|= UART1_RS485CTRL_OINV_1;
igorsk	0:1063a091a062	1214	}
igorsk	0:1063a091a062	1215
igorsk	0:1063a091a062	1216	// Set pin according to
igorsk	0:1063a091a062	1217	if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
igorsk	0:1063a091a062	1218	{
igorsk	0:1063a091a062	1219	tmp \|= UART1_RS485CTRL_SEL_DTR;
igorsk	0:1063a091a062	1220	}
igorsk	0:1063a091a062	1221
igorsk	0:1063a091a062	1222	// Fill delay time
igorsk	0:1063a091a062	1223	UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
igorsk	0:1063a091a062	1224	}
igorsk	0:1063a091a062	1225
igorsk	0:1063a091a062	1226	// MultiDrop mode is enable
igorsk	0:1063a091a062	1227	if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
igorsk	0:1063a091a062	1228	{
igorsk	0:1063a091a062	1229	tmp \|= UART1_RS485CTRL_NMM_EN;
igorsk	0:1063a091a062	1230	}
igorsk	0:1063a091a062	1231
igorsk	0:1063a091a062	1232	// Auto Address Detect function
igorsk	0:1063a091a062	1233	if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
igorsk	0:1063a091a062	1234	{
igorsk	0:1063a091a062	1235	tmp \|= UART1_RS485CTRL_AADEN;
igorsk	0:1063a091a062	1236	// Fill Match Address
igorsk	0:1063a091a062	1237	UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
igorsk	0:1063a091a062	1238	}
igorsk	0:1063a091a062	1239
igorsk	0:1063a091a062	1240
igorsk	0:1063a091a062	1241	// Receiver is disable
igorsk	0:1063a091a062	1242	if (RS485ConfigStruct->Rx_State == DISABLE)
igorsk	0:1063a091a062	1243	{
igorsk	0:1063a091a062	1244	tmp \|= UART1_RS485CTRL_RX_DIS;
igorsk	0:1063a091a062	1245	}
igorsk	0:1063a091a062	1246
igorsk	0:1063a091a062	1247	// write back to RS485 control register
igorsk	0:1063a091a062	1248	UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
igorsk	0:1063a091a062	1249
igorsk	0:1063a091a062	1250	// Enable Parity function and leave parity in stick '0' parity as default
igorsk	0:1063a091a062	1251	UARTx->LCR \|= (UART_LCR_PARITY_F_0 \| UART_LCR_PARITY_EN);
igorsk	0:1063a091a062	1252	}
igorsk	0:1063a091a062	1253
igorsk	0:1063a091a062	1254
igorsk	0:1063a091a062	1255	/**
igorsk	0:1063a091a062	1256	* @brief Enable/Disable receiver in RS485 module in UART1
igorsk	0:1063a091a062	1257	* @param[in] UARTx UART1 only.
igorsk	0:1063a091a062	1258	* @param[in] NewState New State of command, should be:
igorsk	0:1063a091a062	1259	* - ENABLE: Enable this function.
igorsk	0:1063a091a062	1260	* - DISABLE: Disable this function.
igorsk	0:1063a091a062	1261	* @return None
igorsk	0:1063a091a062	1262	*/
igorsk	0:1063a091a062	1263	void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState)
igorsk	0:1063a091a062	1264	{
igorsk	0:1063a091a062	1265	if (NewState == ENABLE){
igorsk	0:1063a091a062	1266	UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
igorsk	0:1063a091a062	1267	} else {
igorsk	0:1063a091a062	1268	UARTx->RS485CTRL \|= UART1_RS485CTRL_RX_DIS;
igorsk	0:1063a091a062	1269	}
igorsk	0:1063a091a062	1270	}
igorsk	0:1063a091a062	1271
igorsk	0:1063a091a062	1272
igorsk	0:1063a091a062	1273	/**
igorsk	0:1063a091a062	1274	* @brief Send data on RS485 bus with specified parity stick value (9-bit mode).
igorsk	0:1063a091a062	1275	* @param[in] UARTx UART1 (only).
igorsk	0:1063a091a062	1276	* @param[in] pDatFrm Pointer to data frame.
igorsk	0:1063a091a062	1277	* @param[in] size Size of data.
igorsk	0:1063a091a062	1278	* @param[in] ParityStick Parity Stick value, should be 0 or 1.
igorsk	0:1063a091a062	1279	* @return None.
igorsk	0:1063a091a062	1280	*/
igorsk	0:1063a091a062	1281	uint32_t UART_RS485Send(LPC_UART1_TypeDef UARTx, uint8_t pDatFrm, \
igorsk	0:1063a091a062	1282	uint32_t size, uint8_t ParityStick)
igorsk	0:1063a091a062	1283	{
igorsk	0:1063a091a062	1284	uint8_t tmp, save;
igorsk	0:1063a091a062	1285	uint32_t cnt;
igorsk	0:1063a091a062	1286
igorsk	0:1063a091a062	1287	if (ParityStick){
igorsk	0:1063a091a062	1288	save = tmp = UARTx->LCR & UART_LCR_BITMASK;
igorsk	0:1063a091a062	1289	tmp &= ~(UART_LCR_PARITY_EVEN);
igorsk	0:1063a091a062	1290	UARTx->LCR = tmp;
igorsk	0:1063a091a062	1291	cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
igorsk	0:1063a091a062	1292	while (!(UARTx->LSR & UART_LSR_TEMT));
igorsk	0:1063a091a062	1293	UARTx->LCR = save;
igorsk	0:1063a091a062	1294	} else {
igorsk	0:1063a091a062	1295	cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
igorsk	0:1063a091a062	1296	while (!(UARTx->LSR & UART_LSR_TEMT));
igorsk	0:1063a091a062	1297	}
igorsk	0:1063a091a062	1298	return cnt;
igorsk	0:1063a091a062	1299	}
igorsk	0:1063a091a062	1300
igorsk	0:1063a091a062	1301
igorsk	0:1063a091a062	1302	/**
igorsk	0:1063a091a062	1303	* @brief Send Slave address frames on RS485 bus.
igorsk	0:1063a091a062	1304	* @param[in] UARTx UART1 (only).
igorsk	0:1063a091a062	1305	* @param[in] SlvAddr Slave Address.
igorsk	0:1063a091a062	1306	* @return None.
igorsk	0:1063a091a062	1307	*/
igorsk	0:1063a091a062	1308	void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr)
igorsk	0:1063a091a062	1309	{
igorsk	0:1063a091a062	1310	UART_RS485Send(UARTx, &SlvAddr, 1, 1);
igorsk	0:1063a091a062	1311	}
igorsk	0:1063a091a062	1312
igorsk	0:1063a091a062	1313
igorsk	0:1063a091a062	1314	/**
igorsk	0:1063a091a062	1315	* @brief Send Data frames on RS485 bus.
igorsk	0:1063a091a062	1316	* @param[in] UARTx UART1 (only).
igorsk	0:1063a091a062	1317	* @param[in] pData Pointer to data to be sent.
igorsk	0:1063a091a062	1318	* @param[in] size Size of data frame to be sent.
igorsk	0:1063a091a062	1319	* @return None.
igorsk	0:1063a091a062	1320	*/
igorsk	0:1063a091a062	1321	uint32_t UART_RS485SendData(LPC_UART1_TypeDef UARTx, uint8_t pData, uint32_t size)
igorsk	0:1063a091a062	1322	{
igorsk	0:1063a091a062	1323	return (UART_RS485Send(UARTx, pData, size, 0));
igorsk	0:1063a091a062	1324	}
igorsk	0:1063a091a062	1325
igorsk	0:1063a091a062	1326	#endif /* _UART1 */
igorsk	0:1063a091a062	1327
igorsk	0:1063a091a062	1328
igorsk	0:1063a091a062	1329	/* Additional driver APIs ----------------------------------------------------------------------- */
igorsk	0:1063a091a062	1330
igorsk	0:1063a091a062	1331	/*******************************************************************//
igorsk	0:1063a091a062	1332	* @brief Send a block of data via UART peripheral
igorsk	0:1063a091a062	1333	* @param[in] UARTx Selected UART peripheral used to send data,
igorsk	0:1063a091a062	1334	* should be UART0, UART1, UART2 or UART3.
igorsk	0:1063a091a062	1335	* @param[in] txbuf Pointer to Transmit buffer
igorsk	0:1063a091a062	1336	* @param[in] buflen Length of Transmit buffer
igorsk	0:1063a091a062	1337	* @param[in] flag Flag used in UART transfer, should be
igorsk	0:1063a091a062	1338	* NONE_BLOCKING or BLOCKING
igorsk	0:1063a091a062	1339	* @return Number of bytes sent.
igorsk	0:1063a091a062	1340	*
igorsk	0:1063a091a062	1341	* Note: when using UART in BLOCKING mode, a time-out condition is used
igorsk	0:1063a091a062	1342	* via defined symbol UART_BLOCKING_TIMEOUT.
igorsk	0:1063a091a062	1343	**********************************************************************/
igorsk	0:1063a091a062	1344	uint32_t UART_Send(LPC_UART_TypeDef UARTx, uint8_t txbuf,
igorsk	0:1063a091a062	1345	uint32_t buflen, TRANSFER_BLOCK_Type flag)
igorsk	0:1063a091a062	1346	{
igorsk	0:1063a091a062	1347	uint32_t bToSend, bSent, timeOut, fifo_cnt;
igorsk	0:1063a091a062	1348	uint8_t *pChar = txbuf;
igorsk	0:1063a091a062	1349
igorsk	0:1063a091a062	1350	bToSend = buflen;
igorsk	0:1063a091a062	1351
igorsk	0:1063a091a062	1352	// blocking mode
igorsk	0:1063a091a062	1353	if (flag == BLOCKING) {
igorsk	0:1063a091a062	1354	bSent = 0;
igorsk	0:1063a091a062	1355	while (bToSend){
igorsk	0:1063a091a062	1356	timeOut = UART_BLOCKING_TIMEOUT;
igorsk	0:1063a091a062	1357	// Wait for THR empty with timeout
igorsk	0:1063a091a062	1358	while (!(UARTx->LSR & UART_LSR_THRE)) {
igorsk	0:1063a091a062	1359	if (timeOut == 0) break;
igorsk	0:1063a091a062	1360	timeOut--;
igorsk	0:1063a091a062	1361	}
igorsk	0:1063a091a062	1362	// Time out!
igorsk	0:1063a091a062	1363	if(timeOut == 0) break;
igorsk	0:1063a091a062	1364	fifo_cnt = UART_TX_FIFO_SIZE;
igorsk	0:1063a091a062	1365	while (fifo_cnt && bToSend){
igorsk	0:1063a091a062	1366	UART_SendData(UARTx, (*pChar++));
igorsk	0:1063a091a062	1367	fifo_cnt--;
igorsk	0:1063a091a062	1368	bToSend--;
igorsk	0:1063a091a062	1369	bSent++;
igorsk	0:1063a091a062	1370	}
igorsk	0:1063a091a062	1371	}
igorsk	0:1063a091a062	1372	}
igorsk	0:1063a091a062	1373	// None blocking mode
igorsk	0:1063a091a062	1374	else {
igorsk	0:1063a091a062	1375	bSent = 0;
igorsk	0:1063a091a062	1376	while (bToSend) {
igorsk	0:1063a091a062	1377	if (!(UARTx->LSR & UART_LSR_THRE)){
igorsk	0:1063a091a062	1378	break;
igorsk	0:1063a091a062	1379	}
igorsk	0:1063a091a062	1380	fifo_cnt = UART_TX_FIFO_SIZE;
igorsk	0:1063a091a062	1381	while (fifo_cnt && bToSend) {
igorsk	0:1063a091a062	1382	UART_SendData(UARTx, (*pChar++));
igorsk	0:1063a091a062	1383	bToSend--;
igorsk	0:1063a091a062	1384	fifo_cnt--;
igorsk	0:1063a091a062	1385	bSent++;
igorsk	0:1063a091a062	1386	}
igorsk	0:1063a091a062	1387	}
igorsk	0:1063a091a062	1388	}
igorsk	0:1063a091a062	1389	return bSent;
igorsk	0:1063a091a062	1390	}
igorsk	0:1063a091a062	1391
igorsk	0:1063a091a062	1392	/*******************************************************************//
igorsk	0:1063a091a062	1393	* @brief Receive a block of data via UART peripheral
igorsk	0:1063a091a062	1394	* @param[in] UARTx Selected UART peripheral used to send data,
igorsk	0:1063a091a062	1395	* should be UART0, UART1, UART2 or UART3.
igorsk	0:1063a091a062	1396	* @param[out] rxbuf Pointer to Received buffer
igorsk	0:1063a091a062	1397	* @param[in] buflen Length of Received buffer
igorsk	0:1063a091a062	1398	* @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING
igorsk	0:1063a091a062	1399
igorsk	0:1063a091a062	1400	* @return Number of bytes received
igorsk	0:1063a091a062	1401	*
igorsk	0:1063a091a062	1402	* Note: when using UART in BLOCKING mode, a time-out condition is used
igorsk	0:1063a091a062	1403	* via defined symbol UART_BLOCKING_TIMEOUT.
igorsk	0:1063a091a062	1404	**********************************************************************/
igorsk	0:1063a091a062	1405	uint32_t UART_Receive(LPC_UART_TypeDef UARTx, uint8_t rxbuf, \
igorsk	0:1063a091a062	1406	uint32_t buflen, TRANSFER_BLOCK_Type flag)
igorsk	0:1063a091a062	1407	{
igorsk	0:1063a091a062	1408	uint32_t bToRecv, bRecv, timeOut;
igorsk	0:1063a091a062	1409	uint8_t *pChar = rxbuf;
igorsk	0:1063a091a062	1410
igorsk	0:1063a091a062	1411	bToRecv = buflen;
igorsk	0:1063a091a062	1412
igorsk	0:1063a091a062	1413	// Blocking mode
igorsk	0:1063a091a062	1414	if (flag == BLOCKING) {
igorsk	0:1063a091a062	1415	bRecv = 0;
igorsk	0:1063a091a062	1416	while (bToRecv){
igorsk	0:1063a091a062	1417	timeOut = UART_BLOCKING_TIMEOUT;
igorsk	0:1063a091a062	1418	while (!(UARTx->LSR & UART_LSR_RDR)){
igorsk	0:1063a091a062	1419	if (timeOut == 0) break;
igorsk	0:1063a091a062	1420	timeOut--;
igorsk	0:1063a091a062	1421	}
igorsk	0:1063a091a062	1422	// Time out!
igorsk	0:1063a091a062	1423	if(timeOut == 0) break;
igorsk	0:1063a091a062	1424	// Get data from the buffer
igorsk	0:1063a091a062	1425	(*pChar++) = UART_ReceiveData(UARTx);
igorsk	0:1063a091a062	1426	bToRecv--;
igorsk	0:1063a091a062	1427	bRecv++;
igorsk	0:1063a091a062	1428	}
igorsk	0:1063a091a062	1429	}
igorsk	0:1063a091a062	1430	// None blocking mode
igorsk	0:1063a091a062	1431	else {
igorsk	0:1063a091a062	1432	bRecv = 0;
igorsk	0:1063a091a062	1433	while (bToRecv) {
igorsk	0:1063a091a062	1434	if (!(UARTx->LSR & UART_LSR_RDR)) {
igorsk	0:1063a091a062	1435	break;
igorsk	0:1063a091a062	1436	} else {
igorsk	0:1063a091a062	1437	(*pChar++) = UART_ReceiveData(UARTx);
igorsk	0:1063a091a062	1438	bRecv++;
igorsk	0:1063a091a062	1439	bToRecv--;
igorsk	0:1063a091a062	1440	}
igorsk	0:1063a091a062	1441	}
igorsk	0:1063a091a062	1442	}
igorsk	0:1063a091a062	1443	return bRecv;
igorsk	0:1063a091a062	1444	}
igorsk	0:1063a091a062	1445
igorsk	0:1063a091a062	1446
igorsk	0:1063a091a062	1447	/*******************************************************************//
igorsk	0:1063a091a062	1448	* @brief Setup call-back function for UART interrupt handler for each
igorsk	0:1063a091a062	1449	* UART peripheral
igorsk	0:1063a091a062	1450	* @param[in] UARTx Selected UART peripheral, should be UART0..3
igorsk	0:1063a091a062	1451	* @param[in] CbType Call-back type, should be:
igorsk	0:1063a091a062	1452	* 0 - Receive Call-back
igorsk	0:1063a091a062	1453	* 1 - Transmit Call-back
igorsk	0:1063a091a062	1454	* 2 - Auto Baudrate Callback
igorsk	0:1063a091a062	1455	* 3 - Error Call-back
igorsk	0:1063a091a062	1456	* 4 - Modem Status Call-back (UART1 only)
igorsk	0:1063a091a062	1457	* @param[in] pfnCbs Pointer to Call-back function
igorsk	0:1063a091a062	1458	* @return None
igorsk	0:1063a091a062	1459	**********************************************************************/
igorsk	0:1063a091a062	1460	void UART_SetupCbs(LPC_UART_TypeDef UARTx, uint8_t CbType, void pfnCbs)
igorsk	0:1063a091a062	1461	{
igorsk	0:1063a091a062	1462	uint8_t pUartNum;
igorsk	0:1063a091a062	1463
igorsk	0:1063a091a062	1464	pUartNum = getUartNum(UARTx);
igorsk	0:1063a091a062	1465	switch(CbType){
igorsk	0:1063a091a062	1466	case 0:
igorsk	0:1063a091a062	1467	uartCbsDat[pUartNum].pfnRxCbs = (fnTxCbs_Type *)pfnCbs;
igorsk	0:1063a091a062	1468	break;
igorsk	0:1063a091a062	1469	case 1:
igorsk	0:1063a091a062	1470	uartCbsDat[pUartNum].pfnTxCbs = (fnRxCbs_Type *)pfnCbs;
igorsk	0:1063a091a062	1471	break;
igorsk	0:1063a091a062	1472	case 2:
igorsk	0:1063a091a062	1473	uartCbsDat[pUartNum].pfnABCbs = (fnABCbs_Type *)pfnCbs;
igorsk	0:1063a091a062	1474	break;
igorsk	0:1063a091a062	1475	case 3:
igorsk	0:1063a091a062	1476	uartCbsDat[pUartNum].pfnErrCbs = (fnErrCbs_Type *)pfnCbs;
igorsk	0:1063a091a062	1477	break;
igorsk	0:1063a091a062	1478	case 4:
igorsk	0:1063a091a062	1479	pfnModemCbs = (fnModemCbs_Type *)pfnCbs;
igorsk	0:1063a091a062	1480	break;
igorsk	0:1063a091a062	1481	default:
igorsk	0:1063a091a062	1482	break;
igorsk	0:1063a091a062	1483	}
igorsk	0:1063a091a062	1484	}
igorsk	0:1063a091a062	1485
igorsk	0:1063a091a062	1486	/*******************************************************************//
igorsk	0:1063a091a062	1487	* @brief Standard UART0 interrupt handler
igorsk	0:1063a091a062	1488	* @param[in] None
igorsk	0:1063a091a062	1489	* @return None
igorsk	0:1063a091a062	1490	**********************************************************************/
igorsk	0:1063a091a062	1491	void UART0_StdIntHandler(void)
igorsk	0:1063a091a062	1492	{
igorsk	0:1063a091a062	1493	UART_GenIntHandler((LPC_UART_TypeDef *)LPC_UART0);
igorsk	0:1063a091a062	1494	}
igorsk	0:1063a091a062	1495
igorsk	0:1063a091a062	1496	/*******************************************************************//
igorsk	0:1063a091a062	1497	* @brief Standard UART1 interrupt handler
igorsk	0:1063a091a062	1498	* @param[in] None
igorsk	0:1063a091a062	1499	* @return None
igorsk	0:1063a091a062	1500	**********************************************************************/
igorsk	0:1063a091a062	1501	void UART1_StdIntHandler(void)
igorsk	0:1063a091a062	1502	{
igorsk	0:1063a091a062	1503	UART_GenIntHandler((LPC_UART_TypeDef *)LPC_UART1);
igorsk	0:1063a091a062	1504	}
igorsk	0:1063a091a062	1505
igorsk	0:1063a091a062	1506	/*******************************************************************//
igorsk	0:1063a091a062	1507	* @brief Standard UART2 interrupt handler
igorsk	0:1063a091a062	1508	* @param[in] None
igorsk	0:1063a091a062	1509	* @return None
igorsk	0:1063a091a062	1510	**********************************************************************/
igorsk	0:1063a091a062	1511	void UART2_StdIntHandler(void)
igorsk	0:1063a091a062	1512	{
igorsk	0:1063a091a062	1513	UART_GenIntHandler(LPC_UART2);
igorsk	0:1063a091a062	1514	}
igorsk	0:1063a091a062	1515
igorsk	0:1063a091a062	1516	/*******************************************************************//
igorsk	0:1063a091a062	1517	* @brief Standard UART3 interrupt handler
igorsk	0:1063a091a062	1518	* @param[in] None
igorsk	0:1063a091a062	1519	* @return
igorsk	0:1063a091a062	1520	**********************************************************************/
igorsk	0:1063a091a062	1521	void UART3_StdIntHandler(void)
igorsk	0:1063a091a062	1522	{
igorsk	0:1063a091a062	1523	UART_GenIntHandler(LPC_UART3);
igorsk	0:1063a091a062	1524	}
igorsk	0:1063a091a062	1525
igorsk	0:1063a091a062	1526	/**
igorsk	0:1063a091a062	1527	* @}
igorsk	0:1063a091a062	1528	*/
igorsk	0:1063a091a062	1529
igorsk	0:1063a091a062	1530
igorsk	0:1063a091a062	1531	#endif /* _UART */
igorsk	0:1063a091a062	1532
igorsk	0:1063a091a062	1533	/**
igorsk	0:1063a091a062	1534	* @}
igorsk	0:1063a091a062	1535	*/
igorsk	0:1063a091a062	1536
igorsk	0:1063a091a062	1537	/* --------------------------------- End Of File ------------------------------ */
igorsk	0:1063a091a062	1538

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

source/lpc17xx_uart.c@0:1063a091a062, 2010-02-17 (annotated)

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