DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

source/lpc17xx_gpdma.c@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/**
igorsk	0:1063a091a062	2	* @file : lpc17xx_gpdma.c
igorsk	0:1063a091a062	3	* @brief : Contains all functions support for GPDMA firmware library on LPC17xx
igorsk	0:1063a091a062	4	* @version : 1.0
igorsk	0:1063a091a062	5	* @date : 20. Apr. 2009
igorsk	0:1063a091a062	6	* @author : HieuNguyen
igorsk	0:1063a091a062	7	**************************************************************************
igorsk	0:1063a091a062	8	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	9	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	10	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	11	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	12	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	13	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	14	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	15	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	16	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	17	* use without further testing or modification.
igorsk	0:1063a091a062	18	**********************************************************************/
igorsk	0:1063a091a062	19
igorsk	0:1063a091a062	20	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	21	/** @addtogroup GPDMA
igorsk	0:1063a091a062	22	* @{
igorsk	0:1063a091a062	23	*/
igorsk	0:1063a091a062	24
igorsk	0:1063a091a062	25	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	26	#include "lpc17xx_gpdma.h"
igorsk	0:1063a091a062	27	#include "lpc17xx_clkpwr.h"
igorsk	0:1063a091a062	28
igorsk	0:1063a091a062	29	/* If this source file built with example, the LPC17xx FW library configuration
igorsk	0:1063a091a062	30	* file in each example directory ("lpc17xx_libcfg.h") must be included,
igorsk	0:1063a091a062	31	* otherwise the default FW library configuration file must be included instead
igorsk	0:1063a091a062	32	*/
igorsk	0:1063a091a062	33	#ifdef __BUILD_WITH_EXAMPLE__
igorsk	0:1063a091a062	34	#include "lpc17xx_libcfg.h"
igorsk	0:1063a091a062	35	#else
igorsk	0:1063a091a062	36	#include "lpc17xx_libcfg_default.h"
igorsk	0:1063a091a062	37	#endif /* __BUILD_WITH_EXAMPLE__ */
igorsk	0:1063a091a062	38
igorsk	0:1063a091a062	39	#ifdef _GPDMA
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41
igorsk	0:1063a091a062	42	/* Private Variables ---------------------------------------------------------- */
igorsk	0:1063a091a062	43	/** @defgroup GPDMA_Private_Variables
igorsk	0:1063a091a062	44	* @{
igorsk	0:1063a091a062	45	*/
igorsk	0:1063a091a062	46
igorsk	0:1063a091a062	47	/**
igorsk	0:1063a091a062	48	* @brief Lookup Table of Connection Type matched with
igorsk	0:1063a091a062	49	* Peripheral Data (FIFO) register base address
igorsk	0:1063a091a062	50	*/
igorsk	0:1063a091a062	51	#ifdef __IAR_SYSTEMS_ICC__
igorsk	0:1063a091a062	52	volatile const void *GPDMA_LUTPerAddr[] = {
igorsk	0:1063a091a062	53	(&LPC_SSP0->DR), // SSP0 Tx
igorsk	0:1063a091a062	54	(&LPC_SSP0->DR), // SSP0 Rx
igorsk	0:1063a091a062	55	(&LPC_SSP1->DR), // SSP1 Tx
igorsk	0:1063a091a062	56	(&LPC_SSP1->DR), // SSP1 Rx
igorsk	0:1063a091a062	57	(&LPC_ADC->ADGDR), // ADC
igorsk	0:1063a091a062	58	(&LPC_I2S->I2STXFIFO), // I2S Tx
igorsk	0:1063a091a062	59	(&LPC_I2S->I2SRXFIFO), // I2S Rx
igorsk	0:1063a091a062	60	(&LPC_DAC->DACR), // DAC
igorsk	0:1063a091a062	61	(&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
igorsk	0:1063a091a062	62	(&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
igorsk	0:1063a091a062	63	(&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
igorsk	0:1063a091a062	64	(&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
igorsk	0:1063a091a062	65	(&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
igorsk	0:1063a091a062	66	(&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
igorsk	0:1063a091a062	67	(&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
igorsk	0:1063a091a062	68	(&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
igorsk	0:1063a091a062	69	(&LPC_TIM0->MR0), // MAT0.0
igorsk	0:1063a091a062	70	(&LPC_TIM0->MR1), // MAT0.1
igorsk	0:1063a091a062	71	(&LPC_TIM1->MR0), // MAT1.0
igorsk	0:1063a091a062	72	(&LPC_TIM1->MR1), // MAT1.1
igorsk	0:1063a091a062	73	(&LPC_TIM2->MR0), // MAT2.0
igorsk	0:1063a091a062	74	(&LPC_TIM2->MR1), // MAT2.1
igorsk	0:1063a091a062	75	(&LPC_TIM3->MR0), // MAT3.0
igorsk	0:1063a091a062	76	(&LPC_TIM3->MR1), // MAT3.1
igorsk	0:1063a091a062	77	};
igorsk	0:1063a091a062	78	#else
igorsk	0:1063a091a062	79	const uint32_t GPDMA_LUTPerAddr[] = {
igorsk	0:1063a091a062	80	((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
igorsk	0:1063a091a062	81	((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
igorsk	0:1063a091a062	82	((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
igorsk	0:1063a091a062	83	((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
igorsk	0:1063a091a062	84	((uint32_t)&LPC_ADC->ADGDR), // ADC
igorsk	0:1063a091a062	85	((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
igorsk	0:1063a091a062	86	((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
igorsk	0:1063a091a062	87	((uint32_t)&LPC_DAC->DACR), // DAC
igorsk	0:1063a091a062	88	((uint32_t)&LPC_UART0->/RBTHDLR./THR), // UART0 Tx
igorsk	0:1063a091a062	89	((uint32_t)&LPC_UART0->/RBTHDLR./RBR), // UART0 Rx
igorsk	0:1063a091a062	90	((uint32_t)&LPC_UART1->/RBTHDLR./THR), // UART1 Tx
igorsk	0:1063a091a062	91	((uint32_t)&LPC_UART1->/RBTHDLR./RBR), // UART1 Rx
igorsk	0:1063a091a062	92	((uint32_t)&LPC_UART2->/RBTHDLR./THR), // UART2 Tx
igorsk	0:1063a091a062	93	((uint32_t)&LPC_UART2->/RBTHDLR./RBR), // UART2 Rx
igorsk	0:1063a091a062	94	((uint32_t)&LPC_UART3->/RBTHDLR./THR), // UART3 Tx
igorsk	0:1063a091a062	95	((uint32_t)&LPC_UART3->/RBTHDLR./RBR), // UART3 Rx
igorsk	0:1063a091a062	96	((uint32_t)&LPC_TIM0->MR0), // MAT0.0
igorsk	0:1063a091a062	97	((uint32_t)&LPC_TIM0->MR1), // MAT0.1
igorsk	0:1063a091a062	98	((uint32_t)&LPC_TIM1->MR0), // MAT1.0
igorsk	0:1063a091a062	99	((uint32_t)&LPC_TIM1->MR1), // MAT1.1
igorsk	0:1063a091a062	100	((uint32_t)&LPC_TIM2->MR0), // MAT2.0
igorsk	0:1063a091a062	101	((uint32_t)&LPC_TIM2->MR1), // MAT2.1
igorsk	0:1063a091a062	102	((uint32_t)&LPC_TIM3->MR0), // MAT3.0
igorsk	0:1063a091a062	103	((uint32_t)&LPC_TIM3->MR1), // MAT3.1
igorsk	0:1063a091a062	104	};
igorsk	0:1063a091a062	105	#endif
igorsk	0:1063a091a062	106	/**
igorsk	0:1063a091a062	107	* @brief Lookup Table of GPDMA Channel Number matched with
igorsk	0:1063a091a062	108	* GPDMA channel pointer
igorsk	0:1063a091a062	109	*/
igorsk	0:1063a091a062	110	const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
igorsk	0:1063a091a062	111	LPC_GPDMACH0, // GPDMA Channel 0
igorsk	0:1063a091a062	112	LPC_GPDMACH1, // GPDMA Channel 1
igorsk	0:1063a091a062	113	LPC_GPDMACH2, // GPDMA Channel 2
igorsk	0:1063a091a062	114	LPC_GPDMACH3, // GPDMA Channel 3
igorsk	0:1063a091a062	115	LPC_GPDMACH4, // GPDMA Channel 4
igorsk	0:1063a091a062	116	LPC_GPDMACH5, // GPDMA Channel 5
igorsk	0:1063a091a062	117	LPC_GPDMACH6, // GPDMA Channel 6
igorsk	0:1063a091a062	118	LPC_GPDMACH7, // GPDMA Channel 7
igorsk	0:1063a091a062	119	};
igorsk	0:1063a091a062	120	/**
igorsk	0:1063a091a062	121	* @brief Optimized Peripheral Source and Destination burst size
igorsk	0:1063a091a062	122	*/
igorsk	0:1063a091a062	123	const uint8_t GPDMA_LUTPerBurst[] = {
igorsk	0:1063a091a062	124	GPDMA_BSIZE_4, // SSP0 Tx
igorsk	0:1063a091a062	125	GPDMA_BSIZE_4, // SSP0 Rx
igorsk	0:1063a091a062	126	GPDMA_BSIZE_4, // SSP1 Tx
igorsk	0:1063a091a062	127	GPDMA_BSIZE_4, // SSP1 Rx
igorsk	0:1063a091a062	128	GPDMA_BSIZE_4, // ADC
igorsk	0:1063a091a062	129	GPDMA_BSIZE_32, // I2S channel 0
igorsk	0:1063a091a062	130	GPDMA_BSIZE_32, // I2S channel 1
igorsk	0:1063a091a062	131	GPDMA_BSIZE_1, // DAC
igorsk	0:1063a091a062	132	GPDMA_BSIZE_1, // UART0 Tx
igorsk	0:1063a091a062	133	GPDMA_BSIZE_1, // UART0 Rx
igorsk	0:1063a091a062	134	GPDMA_BSIZE_1, // UART1 Tx
igorsk	0:1063a091a062	135	GPDMA_BSIZE_1, // UART1 Rx
igorsk	0:1063a091a062	136	GPDMA_BSIZE_1, // UART2 Tx
igorsk	0:1063a091a062	137	GPDMA_BSIZE_1, // UART2 Rx
igorsk	0:1063a091a062	138	GPDMA_BSIZE_1, // UART3 Tx
igorsk	0:1063a091a062	139	GPDMA_BSIZE_1, // UART3 Rx
igorsk	0:1063a091a062	140	GPDMA_BSIZE_1, // MAT0.0
igorsk	0:1063a091a062	141	GPDMA_BSIZE_1, // MAT0.1
igorsk	0:1063a091a062	142	GPDMA_BSIZE_1, // MAT1.0
igorsk	0:1063a091a062	143	GPDMA_BSIZE_1, // MAT1.1
igorsk	0:1063a091a062	144	GPDMA_BSIZE_1, // MAT2.0
igorsk	0:1063a091a062	145	GPDMA_BSIZE_1, // MAT2.1
igorsk	0:1063a091a062	146	GPDMA_BSIZE_1, // MAT3.0
igorsk	0:1063a091a062	147	GPDMA_BSIZE_1, // MAT3.1
igorsk	0:1063a091a062	148	};
igorsk	0:1063a091a062	149	/**
igorsk	0:1063a091a062	150	* @brief Optimized Peripheral Source and Destination transfer width
igorsk	0:1063a091a062	151	*/
igorsk	0:1063a091a062	152	const uint8_t GPDMA_LUTPerWid[] = {
igorsk	0:1063a091a062	153	GPDMA_WIDTH_BYTE, // SSP0 Tx
igorsk	0:1063a091a062	154	GPDMA_WIDTH_BYTE, // SSP0 Rx
igorsk	0:1063a091a062	155	GPDMA_WIDTH_BYTE, // SSP1 Tx
igorsk	0:1063a091a062	156	GPDMA_WIDTH_BYTE, // SSP1 Rx
igorsk	0:1063a091a062	157	GPDMA_WIDTH_WORD, // ADC
igorsk	0:1063a091a062	158	GPDMA_WIDTH_WORD, // I2S channel 0
igorsk	0:1063a091a062	159	GPDMA_WIDTH_WORD, // I2S channel 1
igorsk	0:1063a091a062	160	GPDMA_WIDTH_BYTE, // DAC
igorsk	0:1063a091a062	161	GPDMA_WIDTH_BYTE, // UART0 Tx
igorsk	0:1063a091a062	162	GPDMA_WIDTH_BYTE, // UART0 Rx
igorsk	0:1063a091a062	163	GPDMA_WIDTH_BYTE, // UART1 Tx
igorsk	0:1063a091a062	164	GPDMA_WIDTH_BYTE, // UART1 Rx
igorsk	0:1063a091a062	165	GPDMA_WIDTH_BYTE, // UART2 Tx
igorsk	0:1063a091a062	166	GPDMA_WIDTH_BYTE, // UART2 Rx
igorsk	0:1063a091a062	167	GPDMA_WIDTH_BYTE, // UART3 Tx
igorsk	0:1063a091a062	168	GPDMA_WIDTH_BYTE, // UART3 Rx
igorsk	0:1063a091a062	169	GPDMA_WIDTH_WORD, // MAT0.0
igorsk	0:1063a091a062	170	GPDMA_WIDTH_WORD, // MAT0.1
igorsk	0:1063a091a062	171	GPDMA_WIDTH_WORD, // MAT1.0
igorsk	0:1063a091a062	172	GPDMA_WIDTH_WORD, // MAT1.1
igorsk	0:1063a091a062	173	GPDMA_WIDTH_WORD, // MAT2.0
igorsk	0:1063a091a062	174	GPDMA_WIDTH_WORD, // MAT2.1
igorsk	0:1063a091a062	175	GPDMA_WIDTH_WORD, // MAT3.0
igorsk	0:1063a091a062	176	GPDMA_WIDTH_WORD, // MAT3.1
igorsk	0:1063a091a062	177	};
igorsk	0:1063a091a062	178
igorsk	0:1063a091a062	179	/** Interrupt Call-back function pointer data for each GPDMA channel */
igorsk	0:1063a091a062	180	static fnGPDMACbs_Type *_apfnGPDMACbs[8] = {
igorsk	0:1063a091a062	181	NULL, // GPDMA Call-back function pointer for Channel 0
igorsk	0:1063a091a062	182	NULL, // GPDMA Call-back function pointer for Channel 1
igorsk	0:1063a091a062	183	NULL, // GPDMA Call-back function pointer for Channel 2
igorsk	0:1063a091a062	184	NULL, // GPDMA Call-back function pointer for Channel 3
igorsk	0:1063a091a062	185	NULL, // GPDMA Call-back function pointer for Channel 4
igorsk	0:1063a091a062	186	NULL, // GPDMA Call-back function pointer for Channel 5
igorsk	0:1063a091a062	187	NULL, // GPDMA Call-back function pointer for Channel 6
igorsk	0:1063a091a062	188	NULL, // GPDMA Call-back function pointer for Channel 7
igorsk	0:1063a091a062	189	};
igorsk	0:1063a091a062	190
igorsk	0:1063a091a062	191	/**
igorsk	0:1063a091a062	192	* @}
igorsk	0:1063a091a062	193	*/
igorsk	0:1063a091a062	194
igorsk	0:1063a091a062	195	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	196	/** @addtogroup GPDMA_Public_Functions
igorsk	0:1063a091a062	197	* @{
igorsk	0:1063a091a062	198	*/
igorsk	0:1063a091a062	199
igorsk	0:1063a091a062	200	/******************************************************************//
igorsk	0:1063a091a062	201	* @brief Initialize GPDMA controller
igorsk	0:1063a091a062	202	* @param None
igorsk	0:1063a091a062	203	* @return None
igorsk	0:1063a091a062	204	*********************************************************************/
igorsk	0:1063a091a062	205	void GPDMA_Init(void)
igorsk	0:1063a091a062	206	{
igorsk	0:1063a091a062	207	/* Enable GPDMA clock */
igorsk	0:1063a091a062	208	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
igorsk	0:1063a091a062	209
igorsk	0:1063a091a062	210	// Reset all channel configuration register
igorsk	0:1063a091a062	211	LPC_GPDMACH0->DMACCConfig = 0;
igorsk	0:1063a091a062	212	LPC_GPDMACH1->DMACCConfig = 0;
igorsk	0:1063a091a062	213	LPC_GPDMACH2->DMACCConfig = 0;
igorsk	0:1063a091a062	214	LPC_GPDMACH3->DMACCConfig = 0;
igorsk	0:1063a091a062	215	LPC_GPDMACH4->DMACCConfig = 0;
igorsk	0:1063a091a062	216	LPC_GPDMACH5->DMACCConfig = 0;
igorsk	0:1063a091a062	217	LPC_GPDMACH6->DMACCConfig = 0;
igorsk	0:1063a091a062	218	LPC_GPDMACH7->DMACCConfig = 0;
igorsk	0:1063a091a062	219
igorsk	0:1063a091a062	220	/* Clear all DMA interrupt and error flag */
igorsk	0:1063a091a062	221	LPC_GPDMA->DMACIntTCClear = 0xFF;
igorsk	0:1063a091a062	222	LPC_GPDMA->DMACIntErrClr = 0xFF;
igorsk	0:1063a091a062	223	}
igorsk	0:1063a091a062	224
igorsk	0:1063a091a062	225	/******************************************************************//
igorsk	0:1063a091a062	226	* @brief Setup GPDMA channel peripheral according to the specified
igorsk	0:1063a091a062	227	* parameters in the GPDMAChannelConfig.
igorsk	0:1063a091a062	228	* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
igorsk	0:1063a091a062	229	* structure that contains the configuration
igorsk	0:1063a091a062	230	* information for the specified GPDMA channel peripheral.
igorsk	0:1063a091a062	231	* @param[in] pfnGPDMACbs Pointer to a GPDMA interrupt call-back function
igorsk	0:1063a091a062	232	* @return ERROR if selected channel is enabled before
igorsk	0:1063a091a062	233	* or SUCCESS if channel is configured successfully
igorsk	0:1063a091a062	234	*********************************************************************/
igorsk	0:1063a091a062	235	Status GPDMA_Setup(GPDMA_Channel_CFG_Type GPDMAChannelConfig, fnGPDMACbs_Type pfnGPDMACbs)
igorsk	0:1063a091a062	236	{
igorsk	0:1063a091a062	237	LPC_GPDMACH_TypeDef *pDMAch;
igorsk	0:1063a091a062	238	uint32_t tmp1, tmp2;
igorsk	0:1063a091a062	239
igorsk	0:1063a091a062	240	if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
igorsk	0:1063a091a062	241	// This channel is enabled, return ERROR, need to release this channel first
igorsk	0:1063a091a062	242	return ERROR;
igorsk	0:1063a091a062	243	}
igorsk	0:1063a091a062	244
igorsk	0:1063a091a062	245	// Get Channel pointer
igorsk	0:1063a091a062	246	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
igorsk	0:1063a091a062	247
igorsk	0:1063a091a062	248	// Setup call back function for this channel
igorsk	0:1063a091a062	249	_apfnGPDMACbs[GPDMAChannelConfig->ChannelNum] = pfnGPDMACbs;
igorsk	0:1063a091a062	250
igorsk	0:1063a091a062	251	// Reset the Interrupt status
igorsk	0:1063a091a062	252	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
igorsk	0:1063a091a062	253	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
igorsk	0:1063a091a062	254
igorsk	0:1063a091a062	255	// Clear DMA configure
igorsk	0:1063a091a062	256	pDMAch->DMACCControl = 0x00;
igorsk	0:1063a091a062	257	pDMAch->DMACCConfig = 0x00;
igorsk	0:1063a091a062	258
igorsk	0:1063a091a062	259	/* Assign Linker List Item value */
igorsk	0:1063a091a062	260	pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
igorsk	0:1063a091a062	261
igorsk	0:1063a091a062	262	/* Set value to Channel Control Registers */
igorsk	0:1063a091a062	263	switch (GPDMAChannelConfig->TransferType)
igorsk	0:1063a091a062	264	{
igorsk	0:1063a091a062	265	// Memory to memory
igorsk	0:1063a091a062	266	case GPDMA_TRANSFERTYPE_M2M:
igorsk	0:1063a091a062	267	// Assign physical source and destination address
igorsk	0:1063a091a062	268	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
igorsk	0:1063a091a062	269	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
igorsk	0:1063a091a062	270	pDMAch->DMACCControl
igorsk	0:1063a091a062	271	= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
igorsk	0:1063a091a062	272	\| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
igorsk	0:1063a091a062	273	\| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
igorsk	0:1063a091a062	274	\| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
igorsk	0:1063a091a062	275	\| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
igorsk	0:1063a091a062	276	\| GPDMA_DMACCxControl_SI \
igorsk	0:1063a091a062	277	\| GPDMA_DMACCxControl_DI \
igorsk	0:1063a091a062	278	\| GPDMA_DMACCxControl_I;
igorsk	0:1063a091a062	279	break;
igorsk	0:1063a091a062	280	// Memory to peripheral
igorsk	0:1063a091a062	281	case GPDMA_TRANSFERTYPE_M2P:
igorsk	0:1063a091a062	282	// Assign physical source
igorsk	0:1063a091a062	283	pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
igorsk	0:1063a091a062	284	// Assign peripheral destination address
igorsk	0:1063a091a062	285	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
igorsk	0:1063a091a062	286	pDMAch->DMACCControl
igorsk	0:1063a091a062	287	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
igorsk	0:1063a091a062	288	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	289	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	290	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	291	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	292	\| GPDMA_DMACCxControl_SI \
igorsk	0:1063a091a062	293	\| GPDMA_DMACCxControl_I;
igorsk	0:1063a091a062	294	break;
igorsk	0:1063a091a062	295	// Peripheral to memory
igorsk	0:1063a091a062	296	case GPDMA_TRANSFERTYPE_P2M:
igorsk	0:1063a091a062	297	// Assign peripheral source address
igorsk	0:1063a091a062	298	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
igorsk	0:1063a091a062	299	// Assign memory destination address
igorsk	0:1063a091a062	300	pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
igorsk	0:1063a091a062	301	pDMAch->DMACCControl
igorsk	0:1063a091a062	302	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
igorsk	0:1063a091a062	303	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	304	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	305	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	306	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	307	\| GPDMA_DMACCxControl_DI \
igorsk	0:1063a091a062	308	\| GPDMA_DMACCxControl_I;
igorsk	0:1063a091a062	309	break;
igorsk	0:1063a091a062	310	// Peripheral to peripheral
igorsk	0:1063a091a062	311	case GPDMA_TRANSFERTYPE_P2P:
igorsk	0:1063a091a062	312	// Assign peripheral source address
igorsk	0:1063a091a062	313	pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
igorsk	0:1063a091a062	314	// Assign peripheral destination address
igorsk	0:1063a091a062	315	pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
igorsk	0:1063a091a062	316	pDMAch->DMACCControl
igorsk	0:1063a091a062	317	= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
igorsk	0:1063a091a062	318	\| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	319	\| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	320	\| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
igorsk	0:1063a091a062	321	\| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
igorsk	0:1063a091a062	322	\| GPDMA_DMACCxControl_I;
igorsk	0:1063a091a062	323	break;
igorsk	0:1063a091a062	324	// Do not support any more transfer type, return ERROR
igorsk	0:1063a091a062	325	default:
igorsk	0:1063a091a062	326	return ERROR;
igorsk	0:1063a091a062	327	}
igorsk	0:1063a091a062	328
igorsk	0:1063a091a062	329	/* Re-Configure DMA Request Select for source peripheral */
igorsk	0:1063a091a062	330	if (GPDMAChannelConfig->SrcConn > 15)
igorsk	0:1063a091a062	331	{
igorsk	0:1063a091a062	332	LPC_SC->RESERVED9 \|= (1<<(GPDMAChannelConfig->SrcConn - 16));
igorsk	0:1063a091a062	333	} else {
igorsk	0:1063a091a062	334	LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
igorsk	0:1063a091a062	335	}
igorsk	0:1063a091a062	336
igorsk	0:1063a091a062	337	/* Re-Configure DMA Request Select for Destination peripheral */
igorsk	0:1063a091a062	338	if (GPDMAChannelConfig->DstConn > 15)
igorsk	0:1063a091a062	339	{
igorsk	0:1063a091a062	340	LPC_SC->RESERVED9 \|= (1<<(GPDMAChannelConfig->DstConn - 16));
igorsk	0:1063a091a062	341	} else {
igorsk	0:1063a091a062	342	LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
igorsk	0:1063a091a062	343	}
igorsk	0:1063a091a062	344
igorsk	0:1063a091a062	345	/* Enable DMA channels, little endian */
igorsk	0:1063a091a062	346	LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
igorsk	0:1063a091a062	347	while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
igorsk	0:1063a091a062	348
igorsk	0:1063a091a062	349	// Calculate absolute value for Connection number
igorsk	0:1063a091a062	350	tmp1 = GPDMAChannelConfig->SrcConn;
igorsk	0:1063a091a062	351	tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
igorsk	0:1063a091a062	352	tmp2 = GPDMAChannelConfig->DstConn;
igorsk	0:1063a091a062	353	tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
igorsk	0:1063a091a062	354
igorsk	0:1063a091a062	355	// Configure DMA Channel, enable Error Counter and Terminate counter
igorsk	0:1063a091a062	356	pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE \| GPDMA_DMACCxConfig_ITC /\| GPDMA_DMACCxConfig_E/ \
igorsk	0:1063a091a062	357	\| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
igorsk	0:1063a091a062	358	\| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
igorsk	0:1063a091a062	359	\| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
igorsk	0:1063a091a062	360
igorsk	0:1063a091a062	361	return SUCCESS;
igorsk	0:1063a091a062	362	}
igorsk	0:1063a091a062	363
igorsk	0:1063a091a062	364
igorsk	0:1063a091a062	365	/*******************************************************************//
igorsk	0:1063a091a062	366	* @brief Enable/Disable DMA channel
igorsk	0:1063a091a062	367	* @param[in] channelNum GPDMA channel, should be in range from 0 to 7
igorsk	0:1063a091a062	368	* @param[in] NewState New State of this command, should be:
igorsk	0:1063a091a062	369	* - ENABLE.
igorsk	0:1063a091a062	370	* - DISABLE.
igorsk	0:1063a091a062	371	* @return None
igorsk	0:1063a091a062	372	**********************************************************************/
igorsk	0:1063a091a062	373	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
igorsk	0:1063a091a062	374	{
igorsk	0:1063a091a062	375	LPC_GPDMACH_TypeDef *pDMAch;
igorsk	0:1063a091a062	376
igorsk	0:1063a091a062	377	// Get Channel pointer
igorsk	0:1063a091a062	378	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
igorsk	0:1063a091a062	379
igorsk	0:1063a091a062	380	if (NewState == ENABLE) {
igorsk	0:1063a091a062	381	pDMAch->DMACCConfig \|= GPDMA_DMACCxConfig_E;
igorsk	0:1063a091a062	382	} else {
igorsk	0:1063a091a062	383	pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
igorsk	0:1063a091a062	384	}
igorsk	0:1063a091a062	385	}
igorsk	0:1063a091a062	386
igorsk	0:1063a091a062	387	/*******************************************************************//
igorsk	0:1063a091a062	388	* @brief Standard GPDMA interrupt handler, this function will check
igorsk	0:1063a091a062	389	* all interrupt status of GPDMA channels, then execute the call
igorsk	0:1063a091a062	390	* back function id they're already installed
igorsk	0:1063a091a062	391	* @param[in] None
igorsk	0:1063a091a062	392	* @return None
igorsk	0:1063a091a062	393	**********************************************************************/
igorsk	0:1063a091a062	394	void GPDMA_IntHandler(void)
igorsk	0:1063a091a062	395	{
igorsk	0:1063a091a062	396	uint32_t tmp;
igorsk	0:1063a091a062	397	// Scan interrupt pending
igorsk	0:1063a091a062	398	for (tmp = 0; tmp <= 7; tmp++) {
igorsk	0:1063a091a062	399	if (LPC_GPDMA->DMACIntStat & GPDMA_DMACIntStat_Ch(tmp)) {
igorsk	0:1063a091a062	400	// Check counter terminal status
igorsk	0:1063a091a062	401	if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(tmp)) {
igorsk	0:1063a091a062	402	// Clear terminate counter Interrupt pending
igorsk	0:1063a091a062	403	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(tmp);
igorsk	0:1063a091a062	404	// Execute call-back function if it is already installed
igorsk	0:1063a091a062	405	if(_apfnGPDMACbs[tmp] != NULL) {
igorsk	0:1063a091a062	406	_apfnGPDMACbs[tmp](GPDMA_STAT_INTTC);
igorsk	0:1063a091a062	407	}
igorsk	0:1063a091a062	408	}
igorsk	0:1063a091a062	409	// Check error terminal status
igorsk	0:1063a091a062	410	if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntErrStat_Ch(tmp)) {
igorsk	0:1063a091a062	411	// Clear error counter Interrupt pending
igorsk	0:1063a091a062	412	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(tmp);
igorsk	0:1063a091a062	413	// Execute call-back function if it is already installed
igorsk	0:1063a091a062	414	if(_apfnGPDMACbs[tmp] != NULL) {
igorsk	0:1063a091a062	415	_apfnGPDMACbs[tmp](GPDMA_STAT_INTERR);
igorsk	0:1063a091a062	416	}
igorsk	0:1063a091a062	417	}
igorsk	0:1063a091a062	418	}
igorsk	0:1063a091a062	419	}
igorsk	0:1063a091a062	420	}
igorsk	0:1063a091a062	421
igorsk	0:1063a091a062	422
igorsk	0:1063a091a062	423	/**
igorsk	0:1063a091a062	424	* @}
igorsk	0:1063a091a062	425	*/
igorsk	0:1063a091a062	426
igorsk	0:1063a091a062	427	#endif /* _GPDMA */
igorsk	0:1063a091a062	428
igorsk	0:1063a091a062	429	/**
igorsk	0:1063a091a062	430	* @}
igorsk	0:1063a091a062	431	*/
igorsk	0:1063a091a062	432
igorsk	0:1063a091a062	433	/* --------------------------------- End Of File ------------------------------ */
igorsk	0:1063a091a062	434

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

source/lpc17xx_gpdma.c@0:1063a091a062, 2010-02-17 (annotated)

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