Hugo Zijlmans / Mbed 2 deprecated BLDC

Dependencies:   mbed

Timer0.c@2:f034e862af1f, 2010-12-02 (annotated)

Committer:
hugozijlmans
Date:
Thu Dec 02 20:55:45 2010 +0000
Revision:
2:f034e862af1f
Parent:
1:2c52307d223f 
Added UART0 support over USB mBed1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hugozijlmans 1:2c52307d223f 1 #include "LPC17xx.h"
hugozijlmans 1:2c52307d223f 2 #include "core_cm3.h"
hugozijlmans 1:2c52307d223f 3 #include "cmsis_nvic.h"
hugozijlmans 1:2c52307d223f 4 #include "Timer0.h"
hugozijlmans 1:2c52307d223f 5 #include "main.h"
hugozijlmans 1:2c52307d223f 6 #include "LPC1768.h"
hugozijlmans 1:2c52307d223f 7
hugozijlmans 1:2c52307d223f 8 void Timer0_interrupt_enable(void) {
hugozijlmans 1:2c52307d223f 9
hugozijlmans 1:2c52307d223f 10 // Enable Timer0 interrupt
hugozijlmans 1:2c52307d223f 11 NVIC_EnableIRQ(TIMER0_IRQn);
hugozijlmans 1:2c52307d223f 12 }
hugozijlmans 1:2c52307d223f 13
hugozijlmans 1:2c52307d223f 14 void Timer0_interrupt_disable(void) {
hugozijlmans 1:2c52307d223f 15
hugozijlmans 1:2c52307d223f 16 // Disable Timer0 interrupt
hugozijlmans 1:2c52307d223f 17 NVIC_DisableIRQ(TIMER0_IRQn);
hugozijlmans 1:2c52307d223f 18 }
hugozijlmans 1:2c52307d223f 19
hugozijlmans 1:2c52307d223f 20 void Timer0_IRQHandler(void) {
hugozijlmans 1:2c52307d223f 21
hugozijlmans 1:2c52307d223f 22 // Determine the cause of the interrupt
hugozijlmans 1:2c52307d223f 23
hugozijlmans 1:2c52307d223f 24 // Match register 0 interrupt
hugozijlmans 1:2c52307d223f 25 if ((T0IR & T0IR_MR0) == T0IR_MR0)
hugozijlmans 1:2c52307d223f 26 T0IR |= T0IR_MR0;
hugozijlmans 1:2c52307d223f 27 // Match register 1 interrupt
hugozijlmans 1:2c52307d223f 28 if ((T0IR & T0IR_MR1) == T0IR_MR1);
hugozijlmans 1:2c52307d223f 29 // Match register 2 interrupt
hugozijlmans 1:2c52307d223f 30 if ((T0IR & T0IR_MR2) == T0IR_MR2);
hugozijlmans 1:2c52307d223f 31 // Match register 3 interrupt
hugozijlmans 1:2c52307d223f 32 if ((T0IR & T0IR_MR3) == T0IR_MR3);
hugozijlmans 1:2c52307d223f 33 // Match register 0 interrupt
hugozijlmans 1:2c52307d223f 34 if ((T0IR & T0IR_CR0) == T0IR_CR0);
hugozijlmans 1:2c52307d223f 35 // Match register 0 interrupt
hugozijlmans 1:2c52307d223f 36 if ((T0IR & T0IR_CR1) == T0IR_CR1);
hugozijlmans 1:2c52307d223f 37
hugozijlmans 1:2c52307d223f 38 // Clear the Timer0 interrupt
hugozijlmans 1:2c52307d223f 39 NVIC_ClearPendingIRQ(TIMER0_IRQn);
hugozijlmans 1:2c52307d223f 40
hugozijlmans 1:2c52307d223f 41 //Set Timer0 interrupt flag
hugozijlmans 1:2c52307d223f 42 i_flags.Timer0_int = 1;
hugozijlmans 1:2c52307d223f 43 }
hugozijlmans 1:2c52307d223f 44
hugozijlmans 1:2c52307d223f 45 void Timer0_init(void) {
hugozijlmans 1:2c52307d223f 46
hugozijlmans 1:2c52307d223f 47 // Set Timer0 interrupt priority
hugozijlmans 1:2c52307d223f 48 NVIC_SetPriority(TIMER0_IRQn, 10);
hugozijlmans 1:2c52307d223f 49
hugozijlmans 1:2c52307d223f 50 // Power the Timer0
hugozijlmans 1:2c52307d223f 51 Timer0_power_enable();
hugozijlmans 1:2c52307d223f 52
hugozijlmans 1:2c52307d223f 53 // Reset counter
hugozijlmans 1:2c52307d223f 54 T0TCR = 2;
hugozijlmans 1:2c52307d223f 55
hugozijlmans 1:2c52307d223f 56 // Select perhiperal clk
hugozijlmans 1:2c52307d223f 57 Timer0_select_clk();
hugozijlmans 1:2c52307d223f 58
hugozijlmans 1:2c52307d223f 59 // Timer0 overflow value
hugozijlmans 1:2c52307d223f 60 T0MR0 = TIMER0_DIV;
hugozijlmans 1:2c52307d223f 61
hugozijlmans 1:2c52307d223f 62 // Set the prescale register 0
hugozijlmans 1:2c52307d223f 63 T0PR = 0;
hugozijlmans 1:2c52307d223f 64
hugozijlmans 1:2c52307d223f 65 // Timer0 is incremented when the prescale register =<
hugozijlmans 1:2c52307d223f 66 T0CTCR = 0x0;
hugozijlmans 1:2c52307d223f 67
hugozijlmans 1:2c52307d223f 68 // Set the timer0 reset after reaching T0MR0 and interrupt
hugozijlmans 1:2c52307d223f 69 // T0MCR &= ~0x7;
hugozijlmans 1:2c52307d223f 70 T0MCR = 0x3;
hugozijlmans 1:2c52307d223f 71
hugozijlmans 1:2c52307d223f 72 // Connect the Timer0 interrupt to the interrupt handler
hugozijlmans 1:2c52307d223f 73 NVIC_SetVector(TIMER0_IRQn, (uint32_t)&Timer0_IRQHandler);
hugozijlmans 1:2c52307d223f 74
hugozijlmans 1:2c52307d223f 75 Timer0_interrupt_enable();
hugozijlmans 1:2c52307d223f 76
hugozijlmans 1:2c52307d223f 77 // Enable the counter
hugozijlmans 1:2c52307d223f 78 T0TCR = 1 << 0;
hugozijlmans 1:2c52307d223f 79 }
hugozijlmans 1:2c52307d223f 80
hugozijlmans 1:2c52307d223f 81 void Timer0_power_enable(void) {
hugozijlmans 1:2c52307d223f 82
hugozijlmans 1:2c52307d223f 83 // Power the timer0
hugozijlmans 1:2c52307d223f 84 PCONP |= PCTIM0;
hugozijlmans 1:2c52307d223f 85
hugozijlmans 1:2c52307d223f 86 }
hugozijlmans 1:2c52307d223f 87
hugozijlmans 1:2c52307d223f 88 void Timer0_power_disable(void) {
hugozijlmans 1:2c52307d223f 89
hugozijlmans 1:2c52307d223f 90 // Powerdown the timer0
hugozijlmans 1:2c52307d223f 91 PCONP &= ~(PCTIM0);
hugozijlmans 1:2c52307d223f 92
hugozijlmans 1:2c52307d223f 93 }
hugozijlmans 1:2c52307d223f 94
hugozijlmans 1:2c52307d223f 95 void Timer0_select_clk(void) {
hugozijlmans 1:2c52307d223f 96
hugozijlmans 1:2c52307d223f 97 // Including work-around described in errata.lpc1768.pdf R04
hugozijlmans 1:2c52307d223f 98
hugozijlmans 1:2c52307d223f 99 PLL0_disconnect();
hugozijlmans 1:2c52307d223f 100
hugozijlmans 1:2c52307d223f 101 PLL0_disable();
hugozijlmans 1:2c52307d223f 102
hugozijlmans 1:2c52307d223f 103 // Timer0 perhiperal clock select (01 = CCLK)
hugozijlmans 1:2c52307d223f 104 PCLKSEL0 &= ~(PCLK_TIMER0_1 | PCLK_TIMER0_0);
hugozijlmans 1:2c52307d223f 105 PCLKSEL0 |= PCLK_TIMER0_0;
hugozijlmans 1:2c52307d223f 106
hugozijlmans 1:2c52307d223f 107 PLL0_enable();
hugozijlmans 1:2c52307d223f 108
hugozijlmans 1:2c52307d223f 109 PLL0_connect();
hugozijlmans 1:2c52307d223f 110
hugozijlmans 1:2c52307d223f 111 }