Seungchan Lee / Mbed 2 deprecated 210714_ads1299_ex3_multi_reg_control

ADS1299 multi register control test

Dependencies:   mbed

main.cpp@0:cf9b0921277e, 2021-12-23 (annotated)

Committer:
futuremax
Date:
Thu Dec 23 17:11:56 2021 +0000
Revision:
0:cf9b0921277e
ADS1299 multi register control test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
futuremax 0:cf9b0921277e 1 #include "mbed.h"
futuremax 0:cf9b0921277e 2 // Programed by Seungchan Lee, futuremax7@gmail.com
futuremax 0:cf9b0921277e 3 // 2021.07.15
futuremax 0:cf9b0921277e 4
futuremax 0:cf9b0921277e 5 //Serial pc(USBTX, USBRX);
futuremax 0:cf9b0921277e 6 static UARTSerial pc(USBTX, USBRX, 115200);
futuremax 0:cf9b0921277e 7
futuremax 0:cf9b0921277e 8 InterruptIn drdy(D10);
futuremax 0:cf9b0921277e 9 SPI ads1299(D11, D12, D13); // mosi, miso, sclk
futuremax 0:cf9b0921277e 10 DigitalOut cs(D9);
futuremax 0:cf9b0921277e 11 DigitalOut reset(A1);
futuremax 0:cf9b0921277e 12 DigitalOut pwdn(A2);
futuremax 0:cf9b0921277e 13 DigitalOut start(A0);
futuremax 0:cf9b0921277e 14
futuremax 0:cf9b0921277e 15 //SPI Command Definition Byte Assignments (Datasheet, p35)
futuremax 0:cf9b0921277e 16 #define _WAKEUP 0x02 // Wake-up from standby mode
futuremax 0:cf9b0921277e 17 #define _STANDBY 0x04 // Enter Standby mode
futuremax 0:cf9b0921277e 18 #define _RESET 0x06 // Reset the device
futuremax 0:cf9b0921277e 19 #define _START 0x08 // Start and restart (synchronize) conversions
futuremax 0:cf9b0921277e 20 #define _STOP 0x0A // Stop conversion
futuremax 0:cf9b0921277e 21 #define _RDATAC 0x10 // Enable Read Data Continuous mode (default mode at power-up)
futuremax 0:cf9b0921277e 22 #define _SDATAC 0x11 // Stop Read Data Continuous mode
futuremax 0:cf9b0921277e 23 #define _RDATA 0x12 // Read data by command; supports multiple read back
futuremax 0:cf9b0921277e 24
futuremax 0:cf9b0921277e 25 //Register Addresses
futuremax 0:cf9b0921277e 26 #define ID 0x00
futuremax 0:cf9b0921277e 27 #define CONFIG1 0x01
futuremax 0:cf9b0921277e 28 #define CONFIG2 0x02
futuremax 0:cf9b0921277e 29 #define CONFIG3 0x03
futuremax 0:cf9b0921277e 30 #define LOFF 0x04
futuremax 0:cf9b0921277e 31 #define CH1SET 0x05
futuremax 0:cf9b0921277e 32 #define CH2SET 0x06
futuremax 0:cf9b0921277e 33 #define CH3SET 0x07
futuremax 0:cf9b0921277e 34 #define CH4SET 0x08
futuremax 0:cf9b0921277e 35 #define CH5SET 0x09
futuremax 0:cf9b0921277e 36 #define CH6SET 0x0A
futuremax 0:cf9b0921277e 37 #define CH7SET 0x0B
futuremax 0:cf9b0921277e 38 #define CH8SET 0x0C
futuremax 0:cf9b0921277e 39 #define BIAS_SENSP 0x0D
futuremax 0:cf9b0921277e 40 #define BIAS_SENSN 0x0E
futuremax 0:cf9b0921277e 41 #define LOFF_SENSP 0x0F
futuremax 0:cf9b0921277e 42 #define LOFF_SENSN 0x10
futuremax 0:cf9b0921277e 43 #define LOFF_FLIP 0x11
futuremax 0:cf9b0921277e 44 #define LOFF_STATP 0x12
futuremax 0:cf9b0921277e 45 #define LOFF_STATN 0x13
futuremax 0:cf9b0921277e 46 #define GPIO 0x14
futuremax 0:cf9b0921277e 47 #define MISC1 0x15
futuremax 0:cf9b0921277e 48 #define MISC2 0x16
futuremax 0:cf9b0921277e 49 #define CONFIG4 0x17
futuremax 0:cf9b0921277e 50
futuremax 0:cf9b0921277e 51 #define REG_LENGTH 0x18
futuremax 0:cf9b0921277e 52 #define REG_UPPER_START 0x01
futuremax 0:cf9b0921277e 53 #define REG_UPPER_LENGTH 0x11
futuremax 0:cf9b0921277e 54 #define REG_LOWER_START 0x14
futuremax 0:cf9b0921277e 55 #define REG_LOWER_LENGTH 0x04
futuremax 0:cf9b0921277e 56
futuremax 0:cf9b0921277e 57 #define BYTE_DATA 28
futuremax 0:cf9b0921277e 58 #define BYTE_HEADER 2
futuremax 0:cf9b0921277e 59 #define BYTE_INFO 1
futuremax 0:cf9b0921277e 60 #define DATA_LENGTH (BYTE_DATA+BYTE_HEADER+BYTE_INFO)
futuremax 0:cf9b0921277e 61
futuremax 0:cf9b0921277e 62 char ads1299_reg_data0[REG_LENGTH] = {0x3C, 0x96, 0xC0, 0x60, 0x00, 0x61, 0x61, 0x61, 0x61, 0x00, 0x00, 0x00, 0x00,
futuremax 0:cf9b0921277e 63 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00};
futuremax 0:cf9b0921277e 64 char ads1299_reg_data1[REG_LENGTH] = {0x3C, 0x96, 0xD0, 0xFC, 0x00, 0x65, 0x65, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00,
futuremax 0:cf9b0921277e 65 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
futuremax 0:cf9b0921277e 66 char ads1299_reg_buf[REG_LENGTH] = {0};
futuremax 0:cf9b0921277e 67
futuremax 0:cf9b0921277e 68 void ads1299_command(char command)
futuremax 0:cf9b0921277e 69 {
futuremax 0:cf9b0921277e 70 cs = 0;
futuremax 0:cf9b0921277e 71 ads1299.write(command);
futuremax 0:cf9b0921277e 72 cs = 1;
futuremax 0:cf9b0921277e 73 wait(0.01); // 100 ms
futuremax 0:cf9b0921277e 74 }
futuremax 0:cf9b0921277e 75
futuremax 0:cf9b0921277e 76 char ads1299_rreg(char address)
futuremax 0:cf9b0921277e 77 {
futuremax 0:cf9b0921277e 78 char opcode1 = address + 0x20; // RREG expects 001rrrrr where rrrrr = _address
futuremax 0:cf9b0921277e 79 cs = 0; // open SPI
futuremax 0:cf9b0921277e 80 ads1299.write(opcode1); // opcode1
futuremax 0:cf9b0921277e 81 ads1299.write(0x00); // opcode2
futuremax 0:cf9b0921277e 82 ads1299_reg_buf[address] = ads1299.write(0x00); // update mirror location with returned byte
futuremax 0:cf9b0921277e 83 cs = 1; // close SPI
futuremax 0:cf9b0921277e 84 printf("RREG 0x%0X = 0x%0X\n", address, ads1299_reg_buf[address]);
futuremax 0:cf9b0921277e 85
futuremax 0:cf9b0921277e 86 return ads1299_reg_buf[address]; // return requested register value
futuremax 0:cf9b0921277e 87 }
futuremax 0:cf9b0921277e 88
futuremax 0:cf9b0921277e 89 void ads1299_rregs()
futuremax 0:cf9b0921277e 90 {
futuremax 0:cf9b0921277e 91 const char tx_buf[REG_LENGTH]={0};
futuremax 0:cf9b0921277e 92
futuremax 0:cf9b0921277e 93 cs = 0; // open SPI
futuremax 0:cf9b0921277e 94 ads1299.write(0x20); // opcode1
futuremax 0:cf9b0921277e 95 ads1299.write(REG_LENGTH-1); // opcode2
futuremax 0:cf9b0921277e 96 ads1299.write(tx_buf, REG_LENGTH, ads1299_reg_buf, REG_LENGTH);
futuremax 0:cf9b0921277e 97 cs = 1; // close SPI
futuremax 0:cf9b0921277e 98 for (char n = 0; n<REG_LENGTH; n++)
futuremax 0:cf9b0921277e 99 {
futuremax 0:cf9b0921277e 100 printf("RREG 0x%0X = 0x%0X\n", n, ads1299_reg_buf[n]);
futuremax 0:cf9b0921277e 101 }
futuremax 0:cf9b0921277e 102 }
futuremax 0:cf9b0921277e 103
futuremax 0:cf9b0921277e 104 void ads1299_wreg(char address, char data)
futuremax 0:cf9b0921277e 105 {
futuremax 0:cf9b0921277e 106 char opcode1 = address + 0x40; // RREG expects 001rrrrr where rrrrr = _address
futuremax 0:cf9b0921277e 107 cs = 0; // open SPI
futuremax 0:cf9b0921277e 108 ads1299.write(opcode1); // opcode1
futuremax 0:cf9b0921277e 109 ads1299.write(0x00); // opcode2
futuremax 0:cf9b0921277e 110 ads1299.write(data); // update mirror location with returned byte
futuremax 0:cf9b0921277e 111 cs = 1; // close SPI
futuremax 0:cf9b0921277e 112
futuremax 0:cf9b0921277e 113 // char check = ads1299_rreg(address);
futuremax 0:cf9b0921277e 114 // printf("WREG 0x%X = 0x%X\n", address, check);
futuremax 0:cf9b0921277e 115 }
futuremax 0:cf9b0921277e 116
futuremax 0:cf9b0921277e 117 void ads1299_wregs_upper(char* data)
futuremax 0:cf9b0921277e 118 {
futuremax 0:cf9b0921277e 119 char rx_buf[REG_UPPER_LENGTH]={0};
futuremax 0:cf9b0921277e 120
futuremax 0:cf9b0921277e 121 cs = 0; // open SPI
futuremax 0:cf9b0921277e 122 ads1299.write(0x40+REG_UPPER_START); // opcode1
futuremax 0:cf9b0921277e 123 ads1299.write(REG_UPPER_LENGTH-1); // opcode2
futuremax 0:cf9b0921277e 124 ads1299.write(data+REG_UPPER_START, REG_UPPER_LENGTH, rx_buf, REG_UPPER_LENGTH);
futuremax 0:cf9b0921277e 125 cs = 1; // close SPI
futuremax 0:cf9b0921277e 126
futuremax 0:cf9b0921277e 127 // printf("WREG ALL check!\n");
futuremax 0:cf9b0921277e 128 // ads1299_rregs();
futuremax 0:cf9b0921277e 129 }
futuremax 0:cf9b0921277e 130
futuremax 0:cf9b0921277e 131 void ads1299_wregs_lower(char* data)
futuremax 0:cf9b0921277e 132 {
futuremax 0:cf9b0921277e 133 char rx_buf[REG_LOWER_LENGTH]={0};
futuremax 0:cf9b0921277e 134
futuremax 0:cf9b0921277e 135 cs = 0; // open SPI
futuremax 0:cf9b0921277e 136 ads1299.write(0x40+REG_LOWER_START); // opcode1
futuremax 0:cf9b0921277e 137 ads1299.write(REG_LOWER_LENGTH-1); // opcode2
futuremax 0:cf9b0921277e 138 ads1299.write(data+REG_LOWER_START, REG_LOWER_LENGTH, rx_buf, REG_LOWER_LENGTH);
futuremax 0:cf9b0921277e 139 cs = 1; // close SPI
futuremax 0:cf9b0921277e 140
futuremax 0:cf9b0921277e 141 // printf("WREG ALL check!\n");
futuremax 0:cf9b0921277e 142 // ads1299_rregs();
futuremax 0:cf9b0921277e 143 }
futuremax 0:cf9b0921277e 144
futuremax 0:cf9b0921277e 145 //-------------------------------------------------------------------------------------------------------
futuremax 0:cf9b0921277e 146
futuremax 0:cf9b0921277e 147 int main() {
futuremax 0:cf9b0921277e 148 // pc.baud(115200);
futuremax 0:cf9b0921277e 149
futuremax 0:cf9b0921277e 150 // GPIO setting
futuremax 0:cf9b0921277e 151 reset = 1;
futuremax 0:cf9b0921277e 152 pwdn = 1;
futuremax 0:cf9b0921277e 153 start = 0;
futuremax 0:cf9b0921277e 154 cs = 1;
futuremax 0:cf9b0921277e 155
futuremax 0:cf9b0921277e 156 // Setup the ads1299 for 8 bit data, high steady state clock,
futuremax 0:cf9b0921277e 157 // second edge capture, with a 1MHz clock rate
futuremax 0:cf9b0921277e 158 ads1299.format(8,1);
futuremax 0:cf9b0921277e 159 ads1299.frequency(10000000);
futuremax 0:cf9b0921277e 160 wait(0.1);
futuremax 0:cf9b0921277e 161
futuremax 0:cf9b0921277e 162 cs = 0;
futuremax 0:cf9b0921277e 163 ads1299.write(0x06); //RESET
futuremax 0:cf9b0921277e 164 cs = 1;
futuremax 0:cf9b0921277e 165 wait(0.5); // 100 ms
futuremax 0:cf9b0921277e 166
futuremax 0:cf9b0921277e 167 cs = 0;
futuremax 0:cf9b0921277e 168 ads1299.write(0x11); //SDATAC
futuremax 0:cf9b0921277e 169 cs = 1;
futuremax 0:cf9b0921277e 170 wait(0.1); // 100 ms
futuremax 0:cf9b0921277e 171
futuremax 0:cf9b0921277e 172 while(1)
futuremax 0:cf9b0921277e 173 {
futuremax 0:cf9b0921277e 174 printf("REG SET0 WREGS\n");
futuremax 0:cf9b0921277e 175 ads1299_wregs_upper(ads1299_reg_data0);
futuremax 0:cf9b0921277e 176 ads1299_wregs_lower(ads1299_reg_data0);
futuremax 0:cf9b0921277e 177 ads1299_rregs();
futuremax 0:cf9b0921277e 178 wait(0.5);
futuremax 0:cf9b0921277e 179
futuremax 0:cf9b0921277e 180 printf("REG SET1 WREGS\n");
futuremax 0:cf9b0921277e 181 ads1299_wregs_upper(ads1299_reg_data1);
futuremax 0:cf9b0921277e 182 ads1299_wregs_lower(ads1299_reg_data1);
futuremax 0:cf9b0921277e 183 ads1299_rregs();
futuremax 0:cf9b0921277e 184 wait(0.5);
futuremax 0:cf9b0921277e 185 }
futuremax 0:cf9b0921277e 186 }