Adam C. / Mbed OS Hexi_Battery_Example

HEXIWEAR Battery driver and example.

Dependencies:   Hexi_OLED_SSD1351

Hexi_Battery/hexi_battery.cpp@0:579e15da3834, 2016-10-29 (annotated)

Committer:
fredlak
Date:
Sat Oct 29 17:13:31 2016 +0000
Revision:
0:579e15da3834
Hexiwear battery driver for mbed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fredlak 0:579e15da3834 1
fredlak 0:579e15da3834 2 #include "hexi_battery.h"
fredlak 0:579e15da3834 3 #include "mbed.h"
fredlak 0:579e15da3834 4
fredlak 0:579e15da3834 5 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
fredlak 0:579e15da3834 6 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
fredlak 0:579e15da3834 7 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
fredlak 0:579e15da3834 8 #define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
fredlak 0:579e15da3834 9 #define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
fredlak 0:579e15da3834 10 #define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
fredlak 0:579e15da3834 11 #define ADC_R_REG(base,index) ((base)->R[index])
fredlak 0:579e15da3834 12 #define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
fredlak 0:579e15da3834 13 #define SIM_SCGC_BIT_SHIFT(index) ((uint32_t)(index) & ((1U << 5) - 1U))
fredlak 0:579e15da3834 14 #define SIM_SCGC_BIT_REG(base, index) (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
fredlak 0:579e15da3834 15 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
fredlak 0:579e15da3834 16
fredlak 0:579e15da3834 17 #define ADC_RD_CFG1(base) (ADC_CFG1_REG(base))
fredlak 0:579e15da3834 18 #define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
fredlak 0:579e15da3834 19
fredlak 0:579e15da3834 20 #define ADC_CFG1_REG(base) ((base)->CFG1)
fredlak 0:579e15da3834 21 #define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
fredlak 0:579e15da3834 22 #define ADC_CFG2_REG(base) ((base)->CFG2)
fredlak 0:579e15da3834 23
fredlak 0:579e15da3834 24 #define ADC_WR_CV1(base, value) (ADC_CV1_REG(base) = (value))
fredlak 0:579e15da3834 25 #define ADC_CV1_REG(base) ((base)->CV1)
fredlak 0:579e15da3834 26 #define ADC_WR_CV2(base, value) (ADC_CV2_REG(base) = (value))
fredlak 0:579e15da3834 27 #define ADC_CV2_REG(base) ((base)->CV2)
fredlak 0:579e15da3834 28
fredlak 0:579e15da3834 29 #define ADC_WR_SC2(base, value) (ADC_SC2_REG(base) = (value))
fredlak 0:579e15da3834 30 #define ADC_SC2_REG(base) ((base)->SC2)
fredlak 0:579e15da3834 31
fredlak 0:579e15da3834 32 #define ADC_WR_SC3(base, value) (ADC_SC3_REG(base) = (value))
fredlak 0:579e15da3834 33 #define ADC_SC3_REG(base) ((base)->SC3)
fredlak 0:579e15da3834 34
fredlak 0:579e15da3834 35 #define ADC_RD_SC2(base) (ADC_SC2_REG(base))
fredlak 0:579e15da3834 36 #define ADC_RD_CFG2(base) (ADC_CFG2_REG(base))
fredlak 0:579e15da3834 37 #define ADC_CFG2_REG(base) ((base)->CFG2)
fredlak 0:579e15da3834 38
fredlak 0:579e15da3834 39 #define ADC_RD_SC3(base) (ADC_SC3_REG(base))
fredlak 0:579e15da3834 40 #define ADC_SC3_REG(base) ((base)->SC3)
fredlak 0:579e15da3834 41
fredlak 0:579e15da3834 42 #define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
fredlak 0:579e15da3834 43 const IRQn_Type g_adcIrqId[ADC_INSTANCE_COUNT] = ADC_IRQS;
fredlak 0:579e15da3834 44
fredlak 0:579e15da3834 45 typedef enum _adc16_chn {
fredlak 0:579e15da3834 46 kAdc16Chn0 = 0U, /*!< AD0. */
fredlak 0:579e15da3834 47 kAdc16Chn1 = 1U, /*!< AD1. */
fredlak 0:579e15da3834 48 kAdc16Chn2 = 2U, /*!< AD2. */
fredlak 0:579e15da3834 49 kAdc16Chn3 = 3U, /*!< AD3. */
fredlak 0:579e15da3834 50 kAdc16Chn4 = 4U, /*!< AD4. */
fredlak 0:579e15da3834 51 kAdc16Chn5 = 5U, /*!< AD5. */
fredlak 0:579e15da3834 52 kAdc16Chn6 = 6U, /*!< AD6. */
fredlak 0:579e15da3834 53 kAdc16Chn7 = 7U, /*!< AD6. */
fredlak 0:579e15da3834 54 kAdc16Chn8 = 8U, /*!< AD8. */
fredlak 0:579e15da3834 55 kAdc16Chn9 = 9U, /*!< AD9. */
fredlak 0:579e15da3834 56 kAdc16Chn10 = 10U, /*!< AD10. */
fredlak 0:579e15da3834 57 kAdc16Chn11 = 11U, /*!< AD11. */
fredlak 0:579e15da3834 58 kAdc16Chn12 = 12U, /*!< AD12. */
fredlak 0:579e15da3834 59 kAdc16Chn13 = 13U, /*!< AD13. */
fredlak 0:579e15da3834 60 kAdc16Chn14 = 14U, /*!< AD14. */
fredlak 0:579e15da3834 61 kAdc16Chn15 = 15U, /*!< AD15. */
fredlak 0:579e15da3834 62 kAdc16Chn16 = 16U, /*!< AD16. */
fredlak 0:579e15da3834 63 kAdc16Chn17 = 17U, /*!< AD17. */
fredlak 0:579e15da3834 64 kAdc16Chn18 = 18U, /*!< AD18. */
fredlak 0:579e15da3834 65 kAdc16Chn19 = 19U, /*!< AD19. */
fredlak 0:579e15da3834 66 kAdc16Chn20 = 20U, /*!< AD20. */
fredlak 0:579e15da3834 67 kAdc16Chn21 = 21U, /*!< AD21. */
fredlak 0:579e15da3834 68 kAdc16Chn22 = 22U, /*!< AD22. */
fredlak 0:579e15da3834 69 kAdc16Chn23 = 23U, /*!< AD23. */
fredlak 0:579e15da3834 70 kAdc16Chn24 = 24U, /*!< AD24. */
fredlak 0:579e15da3834 71 kAdc16Chn25 = 25U, /*!< AD25. */
fredlak 0:579e15da3834 72 kAdc16Chn26 = 26U, /*!< AD26. */
fredlak 0:579e15da3834 73 kAdc16Chn27 = 27U, /*!< AD27. */
fredlak 0:579e15da3834 74 kAdc16Chn28 = 28U, /*!< AD28. */
fredlak 0:579e15da3834 75 kAdc16Chn29 = 29U, /*!< AD29. */
fredlak 0:579e15da3834 76 kAdc16Chn30 = 30U, /*!< AD30. */
fredlak 0:579e15da3834 77 kAdc16Chn31 = 31U, /*!< AD31. */
fredlak 0:579e15da3834 78
fredlak 0:579e15da3834 79 kAdc16Chn0d = kAdc16Chn0, /*!< DAD0. */
fredlak 0:579e15da3834 80 kAdc16Chn1d = kAdc16Chn1, /*!< DAD1. */
fredlak 0:579e15da3834 81 kAdc16Chn2d = kAdc16Chn2, /*!< DAD2. */
fredlak 0:579e15da3834 82 kAdc16Chn3d = kAdc16Chn3, /*!< DAD3. */
fredlak 0:579e15da3834 83 kAdc16Chn4a = kAdc16Chn4, /*!< AD4a. */
fredlak 0:579e15da3834 84 kAdc16Chn5a = kAdc16Chn5, /*!< AD5a. */
fredlak 0:579e15da3834 85 kAdc16Chn6a = kAdc16Chn6, /*!< AD6a. */
fredlak 0:579e15da3834 86 kAdc16Chn7a = kAdc16Chn7, /*!< AD7a. */
fredlak 0:579e15da3834 87 kAdc16Chn4b = kAdc16Chn4, /*!< AD4b. */
fredlak 0:579e15da3834 88 kAdc16Chn5b = kAdc16Chn5, /*!< AD5b. */
fredlak 0:579e15da3834 89 kAdc16Chn6b = kAdc16Chn6, /*!< AD6b. */
fredlak 0:579e15da3834 90 kAdc16Chn7b = kAdc16Chn7 /*!< AD7b. */
fredlak 0:579e15da3834 91
fredlak 0:579e15da3834 92 } adc16_chn_t;
fredlak 0:579e15da3834 93
fredlak 0:579e15da3834 94 typedef enum _adc16_status {
fredlak 0:579e15da3834 95 kStatus_ADC16_Success = 0U, /*!< Success. */
fredlak 0:579e15da3834 96 kStatus_ADC16_InvalidArgument = 1U, /*!< Invalid argument existed. */
fredlak 0:579e15da3834 97 kStatus_ADC16_Failed = 2U /*!< Execution failed. */
fredlak 0:579e15da3834 98 } adc16_status_t;
fredlak 0:579e15da3834 99
fredlak 0:579e15da3834 100 typedef struct Adc16ChnConfig {
fredlak 0:579e15da3834 101 adc16_chn_t chnIdx; /*!< Select the sample channel index. */
fredlak 0:579e15da3834 102 bool convCompletedIntEnable; /*!< Enable the conversion complete interrupt. */
fredlak 0:579e15da3834 103 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
fredlak 0:579e15da3834 104 bool diffConvEnable; /*!< Enable the differential conversion. */
fredlak 0:579e15da3834 105 #endif /** FSL_FEATURE_ADC16_HAS_DIFF_MODE */
fredlak 0:579e15da3834 106 } adc16_chn_config_t;
fredlak 0:579e15da3834 107
fredlak 0:579e15da3834 108 extern const adc16_chn_config_t BATTERY_ADC_ChnConfig;
fredlak 0:579e15da3834 109
fredlak 0:579e15da3834 110 const adc16_chn_config_t BATTERY_ADC_ChnConfig = {
fredlak 0:579e15da3834 111 .chnIdx = kAdc16Chn16,
fredlak 0:579e15da3834 112 .convCompletedIntEnable = false,
fredlak 0:579e15da3834 113 .diffConvEnable = false
fredlak 0:579e15da3834 114 };
fredlak 0:579e15da3834 115
fredlak 0:579e15da3834 116 ADC_Type * const g_adcBase[] = ADC_BASE_PTRS;
fredlak 0:579e15da3834 117
fredlak 0:579e15da3834 118
fredlak 0:579e15da3834 119 void ADC16_HAL_ConfigChn(ADC_Type * base, uint32_t chnGroup, const adc16_chn_config_t *configPtr)
fredlak 0:579e15da3834 120 {
fredlak 0:579e15da3834 121 uint16_t tmp = 0U;
fredlak 0:579e15da3834 122
fredlak 0:579e15da3834 123 /** Interrupt enable. */
fredlak 0:579e15da3834 124 if (configPtr->convCompletedIntEnable) {
fredlak 0:579e15da3834 125 tmp |= ADC_SC1_AIEN_MASK;
fredlak 0:579e15da3834 126 }
fredlak 0:579e15da3834 127
fredlak 0:579e15da3834 128 /** Differential mode enable. */
fredlak 0:579e15da3834 129 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
fredlak 0:579e15da3834 130 if (configPtr->diffConvEnable) {
fredlak 0:579e15da3834 131 tmp |= ADC_SC1_DIFF_MASK;
fredlak 0:579e15da3834 132 }
fredlak 0:579e15da3834 133 #endif /** FSL_FEATURE_ADC16_HAS_DIFF_MODE */
fredlak 0:579e15da3834 134
fredlak 0:579e15da3834 135 /** Input channel select. */
fredlak 0:579e15da3834 136 tmp |= ADC_SC1_ADCH((uint32_t)(configPtr->chnIdx));
fredlak 0:579e15da3834 137
fredlak 0:579e15da3834 138 ADC_WR_SC1(base, chnGroup, tmp);
fredlak 0:579e15da3834 139 }
fredlak 0:579e15da3834 140
fredlak 0:579e15da3834 141 adc16_status_t ADC16_DRV_ConfigConvChn(uint32_t instance,
fredlak 0:579e15da3834 142 uint32_t chnGroup, const adc16_chn_config_t *configPtr)
fredlak 0:579e15da3834 143 {
fredlak 0:579e15da3834 144 ADC_Type * base = g_adcBase[instance];
fredlak 0:579e15da3834 145
fredlak 0:579e15da3834 146 if (!configPtr) {
fredlak 0:579e15da3834 147 return kStatus_ADC16_InvalidArgument;
fredlak 0:579e15da3834 148 }
fredlak 0:579e15da3834 149
fredlak 0:579e15da3834 150 ADC16_HAL_ConfigChn(base, chnGroup, configPtr);
fredlak 0:579e15da3834 151
fredlak 0:579e15da3834 152 return kStatus_ADC16_Success;
fredlak 0:579e15da3834 153 }
fredlak 0:579e15da3834 154
fredlak 0:579e15da3834 155 static inline bool ADC16_HAL_GetChnConvCompletedFlag(ADC_Type * base, uint32_t chnGroup)
fredlak 0:579e15da3834 156 {
fredlak 0:579e15da3834 157 return (1U == ADC_BRD_SC1_COCO(base, chnGroup) );
fredlak 0:579e15da3834 158 }
fredlak 0:579e15da3834 159
fredlak 0:579e15da3834 160 void ADC16_DRV_WaitConvDone(uint32_t instance, uint32_t chnGroup)
fredlak 0:579e15da3834 161 {
fredlak 0:579e15da3834 162 ADC_Type * base = g_adcBase[instance];
fredlak 0:579e15da3834 163
fredlak 0:579e15da3834 164 while ( !ADC16_HAL_GetChnConvCompletedFlag(base, chnGroup) )
fredlak 0:579e15da3834 165 {}
fredlak 0:579e15da3834 166 }
fredlak 0:579e15da3834 167
fredlak 0:579e15da3834 168 static inline uint16_t ADC16_HAL_GetChnConvValue(ADC_Type * base, uint32_t chnGroup )
fredlak 0:579e15da3834 169 {
fredlak 0:579e15da3834 170 return (uint16_t)(ADC_BRD_R_D(base, chnGroup) );
fredlak 0:579e15da3834 171 }
fredlak 0:579e15da3834 172
fredlak 0:579e15da3834 173 uint16_t ADC16_DRV_GetConvValueRAW(uint32_t instance, uint32_t chnGroup)
fredlak 0:579e15da3834 174 {
fredlak 0:579e15da3834 175
fredlak 0:579e15da3834 176 ADC_Type * base = g_adcBase[instance];
fredlak 0:579e15da3834 177
fredlak 0:579e15da3834 178 return ADC16_HAL_GetChnConvValue(base, chnGroup);
fredlak 0:579e15da3834 179 }
fredlak 0:579e15da3834 180
fredlak 0:579e15da3834 181 int16_t ADC16_DRV_GetConvValueSigned(uint32_t instance, uint32_t chnGroup)
fredlak 0:579e15da3834 182 {
fredlak 0:579e15da3834 183 return (int16_t)ADC16_DRV_GetConvValueRAW(instance, chnGroup);
fredlak 0:579e15da3834 184 }
fredlak 0:579e15da3834 185
fredlak 0:579e15da3834 186 void ADC16_DRV_PauseConv(uint32_t instance, uint32_t chnGroup)
fredlak 0:579e15da3834 187 {
fredlak 0:579e15da3834 188 adc16_chn_config_t configStruct;
fredlak 0:579e15da3834 189
fredlak 0:579e15da3834 190 configStruct.chnIdx = kAdc16Chn31;
fredlak 0:579e15da3834 191 configStruct.convCompletedIntEnable = false;
fredlak 0:579e15da3834 192 #if FSL_FEATURE_ADC16_HAS_DIFF_MODE
fredlak 0:579e15da3834 193 configStruct.diffConvEnable = false;
fredlak 0:579e15da3834 194 #endif
fredlak 0:579e15da3834 195 ADC16_DRV_ConfigConvChn(instance, chnGroup, &configStruct);
fredlak 0:579e15da3834 196 }
fredlak 0:579e15da3834 197
fredlak 0:579e15da3834 198 typedef enum _adc16_clk_divider {
fredlak 0:579e15da3834 199 kAdc16ClkDividerOf1 = 0U, /*!< For divider 1 from the input clock to ADC16. @internal gui name="1" */
fredlak 0:579e15da3834 200 kAdc16ClkDividerOf2 = 1U, /*!< For divider 2 from the input clock to ADC16. @internal gui name="2" */
fredlak 0:579e15da3834 201 kAdc16ClkDividerOf4 = 2U, /*!< For divider 4 from the input clock to ADC16. @internal gui name="4" */
fredlak 0:579e15da3834 202 kAdc16ClkDividerOf8 = 3U /*!< For divider 8 from the input clock to ADC16. @internal gui name="8" */
fredlak 0:579e15da3834 203 } adc16_clk_divider_t;
fredlak 0:579e15da3834 204
fredlak 0:579e15da3834 205 typedef enum _adc16_resolution {
fredlak 0:579e15da3834 206 kAdc16ResolutionBitOf8or9 = 0U,
fredlak 0:579e15da3834 207 /*!< 8-bit for single end sample, or 9-bit for differential sample. @internal gui name="" */
fredlak 0:579e15da3834 208 kAdc16ResolutionBitOfSingleEndAs8 = kAdc16ResolutionBitOf8or9, /*!< 8-bit for single end sample. @internal gui name="8 bit in single mode" */
fredlak 0:579e15da3834 209 kAdc16ResolutionBitOfDiffModeAs9 = kAdc16ResolutionBitOf8or9, /*!< 9-bit for differential sample. @internal gui name="9 bit in differential mode" */
fredlak 0:579e15da3834 210
fredlak 0:579e15da3834 211 kAdc16ResolutionBitOf12or13 = 1U,
fredlak 0:579e15da3834 212 /*!< 12-bit for single end sample, or 13-bit for differential sample. @internal gui name="" */
fredlak 0:579e15da3834 213 kAdc16ResolutionBitOfSingleEndAs12 = kAdc16ResolutionBitOf12or13, /*!< 12-bit for single end sample. @internal gui name="12 bit in single mode" */
fredlak 0:579e15da3834 214 kAdc16ResolutionBitOfDiffModeAs13 = kAdc16ResolutionBitOf12or13, /*!< 13-bit for differential sample. @internal gui name="13 bit in differential mode" */
fredlak 0:579e15da3834 215
fredlak 0:579e15da3834 216 kAdc16ResolutionBitOf10or11 = 2U,
fredlak 0:579e15da3834 217 /*!< 10-bit for single end sample, or 11-bit for differential sample. @internal gui name="" */
fredlak 0:579e15da3834 218 kAdc16ResolutionBitOfSingleEndAs10 = kAdc16ResolutionBitOf10or11, /*!< 10-bit for single end sample. @internal gui name="10 bit in single mode" */
fredlak 0:579e15da3834 219 kAdc16ResolutionBitOfDiffModeAs11 = kAdc16ResolutionBitOf10or11 /*!< 11-bit for differential sample. @internal gui name="11 bit in differential mode" */
fredlak 0:579e15da3834 220 #if (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
fredlak 0:579e15da3834 221 , kAdc16ResolutionBitOf16 = 3U,
fredlak 0:579e15da3834 222 /*!< 16-bit for both single end sample and differential sample. @internal gui name="16-bit" */
fredlak 0:579e15da3834 223 kAdc16ResolutionBitOfSingleEndAs16 = kAdc16ResolutionBitOf16, /*!< 16-bit for single end sample. @internal gui name="" */
fredlak 0:579e15da3834 224 kAdc16ResolutionBitOfDiffModeAs16 = kAdc16ResolutionBitOf16 /*!< 16-bit for differential sample. @internal gui name="" */
fredlak 0:579e15da3834 225
fredlak 0:579e15da3834 226 #endif /** FSL_FEATURE_ADC16_MAX_RESOLUTION */
fredlak 0:579e15da3834 227 } adc16_resolution_t;
fredlak 0:579e15da3834 228
fredlak 0:579e15da3834 229 typedef enum _adc16_long_sample_cycle {
fredlak 0:579e15da3834 230 kAdc16LongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
fredlak 0:579e15da3834 231 kAdc16LongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
fredlak 0:579e15da3834 232 kAdc16LongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
fredlak 0:579e15da3834 233 kAdc16LongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
fredlak 0:579e15da3834 234 } adc16_long_sample_cycle_t;
fredlak 0:579e15da3834 235
fredlak 0:579e15da3834 236 typedef enum _adc16_clk_src_mode {
fredlak 0:579e15da3834 237 kAdc16ClkSrcOfBusClk = 0U, /*!< For input as bus clock. @internal gui name="Bus clock" */
fredlak 0:579e15da3834 238 kAdc16ClkSrcOfAltClk2 = 1U, /*!< For input as alternate clock 2 (AltClk2). @internal gui name="Alternate clock 2" */
fredlak 0:579e15da3834 239 kAdc16ClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). @internal gui name="Alternate clock 1" */
fredlak 0:579e15da3834 240 kAdc16ClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). @internal gui name="Asynchronous clock" */
fredlak 0:579e15da3834 241 } adc16_clk_src_mode_t;
fredlak 0:579e15da3834 242
fredlak 0:579e15da3834 243 typedef enum _adc16_ref_volt_src {
fredlak 0:579e15da3834 244 kAdc16RefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. @internal gui name="Vref pair" */
fredlak 0:579e15da3834 245 kAdc16RefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL. @internal gui name="Valt pair" */
fredlak 0:579e15da3834 246 } adc16_ref_volt_src_t;
fredlak 0:579e15da3834 247
fredlak 0:579e15da3834 248 typedef struct Adc16ConverterConfig {
fredlak 0:579e15da3834 249 bool lowPowerEnable; /*!< Enable low power. @internal gui name="Low power mode" id="LowPowerMode" */
fredlak 0:579e15da3834 250 adc16_clk_divider_t clkDividerMode; /*!< Select the divider of input clock source. @internal gui name="Clock divider" id="ClockDivider" */
fredlak 0:579e15da3834 251 bool longSampleTimeEnable; /*!< Enable the long sample time. @internal gui name="Long sample time" id="LongSampleTime" */
fredlak 0:579e15da3834 252 adc16_resolution_t resolution; /*!< Select the sample resolution mode. @internal gui name="Resolution" id="Resolution" */
fredlak 0:579e15da3834 253 adc16_clk_src_mode_t clkSrc; /*!< Select the input clock source to converter. @internal gui name="Clock source" id="ClockSource" */
fredlak 0:579e15da3834 254 bool asyncClkEnable; /*!< Enable the asynchronous clock inside the ADC. @internal gui name="Internal async. clock" id="InternalAsyncClock" */
fredlak 0:579e15da3834 255 bool highSpeedEnable; /*!< Enable the high speed mode. @internal gui name="High speed mode" id="HighSpeed" */
fredlak 0:579e15da3834 256 adc16_long_sample_cycle_t longSampleCycleMode; /*!< Select the long sample mode. @internal gui name="Long sample mode" id="LongSampleMode" */
fredlak 0:579e15da3834 257 bool hwTriggerEnable; /*!< Enable hardware trigger function. @internal gui name="Hardware trigger" id="HwTrigger" */
fredlak 0:579e15da3834 258 adc16_ref_volt_src_t refVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="ReferenceVoltage" */
fredlak 0:579e15da3834 259 bool continuousConvEnable; /*!< Enable continuous conversion mode. @internal gui name="Continuous mode" id="ContinuousMode" */
fredlak 0:579e15da3834 260 #if FSL_FEATURE_ADC16_HAS_DMA
fredlak 0:579e15da3834 261 bool dmaEnable; /*!< Enable the DMA for ADC converter. @internal gui name="DMA mode" id="DMASupport" */
fredlak 0:579e15da3834 262 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
fredlak 0:579e15da3834 263 } adc16_converter_config_t;
fredlak 0:579e15da3834 264
fredlak 0:579e15da3834 265 const adc16_converter_config_t BATTERY_ADC_InitConfig = {
fredlak 0:579e15da3834 266 .lowPowerEnable = false,
fredlak 0:579e15da3834 267 .clkDividerMode = kAdc16ClkDividerOf1,
fredlak 0:579e15da3834 268 .longSampleTimeEnable = false,
fredlak 0:579e15da3834 269 .resolution = kAdc16ResolutionBitOf16,
fredlak 0:579e15da3834 270 .clkSrc = kAdc16ClkSrcOfBusClk,
fredlak 0:579e15da3834 271 .asyncClkEnable = false,
fredlak 0:579e15da3834 272 .highSpeedEnable = true,
fredlak 0:579e15da3834 273 .longSampleCycleMode = kAdc16LongSampleCycleOf4,
fredlak 0:579e15da3834 274 .hwTriggerEnable = false,
fredlak 0:579e15da3834 275 .refVoltSrc = kAdc16RefVoltSrcOfVref,
fredlak 0:579e15da3834 276 .continuousConvEnable = false,
fredlak 0:579e15da3834 277 .dmaEnable = false,
fredlak 0:579e15da3834 278 };
fredlak 0:579e15da3834 279
fredlak 0:579e15da3834 280 #define FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n)
fredlak 0:579e15da3834 281
fredlak 0:579e15da3834 282 typedef enum _sim_clock_gate_name {
fredlak 0:579e15da3834 283 kSimClockGateI2c2 = FSL_SIM_SCGC_BIT(1U, 6U),
fredlak 0:579e15da3834 284 kSimClockGateUart4 = FSL_SIM_SCGC_BIT(1U, 10U),
fredlak 0:579e15da3834 285 kSimClockGateUart5 = FSL_SIM_SCGC_BIT(1U, 11U),
fredlak 0:579e15da3834 286 kSimClockGateEnet0 = FSL_SIM_SCGC_BIT(2U, 0U),
fredlak 0:579e15da3834 287 kSimClockGateDac0 = FSL_SIM_SCGC_BIT(2U, 12U),
fredlak 0:579e15da3834 288 kSimClockGateDac1 = FSL_SIM_SCGC_BIT(2U, 13U),
fredlak 0:579e15da3834 289 kSimClockGateSpi2 = FSL_SIM_SCGC_BIT(3U, 12U),
fredlak 0:579e15da3834 290 kSimClockGateSdhc0 = FSL_SIM_SCGC_BIT(3U, 17U),
fredlak 0:579e15da3834 291 kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(3U, 25U),
fredlak 0:579e15da3834 292 kSimClockGateAdc1 = FSL_SIM_SCGC_BIT(3U, 27U),
fredlak 0:579e15da3834 293 kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
fredlak 0:579e15da3834 294 kSimClockGateCmt0 = FSL_SIM_SCGC_BIT(4U, 2U),
fredlak 0:579e15da3834 295 kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
fredlak 0:579e15da3834 296 kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
fredlak 0:579e15da3834 297 kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
fredlak 0:579e15da3834 298 kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
fredlak 0:579e15da3834 299 kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
fredlak 0:579e15da3834 300 kSimClockGateUart3 = FSL_SIM_SCGC_BIT(4U, 13U),
fredlak 0:579e15da3834 301 kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
fredlak 0:579e15da3834 302 kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
fredlak 0:579e15da3834 303 kSimClockGateVref0 = FSL_SIM_SCGC_BIT(4U, 20U),
fredlak 0:579e15da3834 304 kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
fredlak 0:579e15da3834 305 kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
fredlak 0:579e15da3834 306 kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
fredlak 0:579e15da3834 307 kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
fredlak 0:579e15da3834 308 kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
fredlak 0:579e15da3834 309 kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
fredlak 0:579e15da3834 310 kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
fredlak 0:579e15da3834 311 kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
fredlak 0:579e15da3834 312 kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
fredlak 0:579e15da3834 313 kSimClockGateRnga0 = FSL_SIM_SCGC_BIT(6U, 9U),
fredlak 0:579e15da3834 314 kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
fredlak 0:579e15da3834 315 kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(6U, 13U),
fredlak 0:579e15da3834 316 kSimClockGateSai0 = FSL_SIM_SCGC_BIT(6U, 15U),
fredlak 0:579e15da3834 317 kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
fredlak 0:579e15da3834 318 kSimClockGateUsbdcd0 = FSL_SIM_SCGC_BIT(6U, 21U),
fredlak 0:579e15da3834 319 kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
fredlak 0:579e15da3834 320 kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
fredlak 0:579e15da3834 321 kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
fredlak 0:579e15da3834 322 kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
fredlak 0:579e15da3834 323 kSimClockGateFtm2 = FSL_SIM_SCGC_BIT(6U, 26U),
fredlak 0:579e15da3834 324 kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
fredlak 0:579e15da3834 325 kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
fredlak 0:579e15da3834 326 kSimClockGateFlexbus0 = FSL_SIM_SCGC_BIT(7U, 0U),
fredlak 0:579e15da3834 327 kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 1U),
fredlak 0:579e15da3834 328 kSimClockGateMpu0 = FSL_SIM_SCGC_BIT(7U, 2U),
fredlak 0:579e15da3834 329 #if (defined(DOXYGEN_OUTPUT) && (DOXYGEN_OUTPUT))
fredlak 0:579e15da3834 330 } sim_clock_gate_name_k64f12_t;
fredlak 0:579e15da3834 331 #else
fredlak 0:579e15da3834 332 } sim_clock_gate_name_t;
fredlak 0:579e15da3834 333 #endif
fredlak 0:579e15da3834 334
fredlak 0:579e15da3834 335 static const sim_clock_gate_name_t adcGateTable[] = {
fredlak 0:579e15da3834 336 kSimClockGateAdc0,
fredlak 0:579e15da3834 337 kSimClockGateAdc1
fredlak 0:579e15da3834 338 };
fredlak 0:579e15da3834 339
fredlak 0:579e15da3834 340 static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
fredlak 0:579e15da3834 341 {
fredlak 0:579e15da3834 342 SIM_BWR_SCGC_BIT(base, name, 1U);
fredlak 0:579e15da3834 343 }
fredlak 0:579e15da3834 344
fredlak 0:579e15da3834 345 void CLOCK_SYS_EnableAdcClock(uint32_t instance)
fredlak 0:579e15da3834 346 {
fredlak 0:579e15da3834 347 SIM_HAL_EnableClock(SIM, adcGateTable[instance]);
fredlak 0:579e15da3834 348 }
fredlak 0:579e15da3834 349
fredlak 0:579e15da3834 350 void ADC16_HAL_Init(ADC_Type * base)
fredlak 0:579e15da3834 351 {
fredlak 0:579e15da3834 352 ADC_WR_CFG1(base, 0U);
fredlak 0:579e15da3834 353 ADC_WR_CFG2(base, 0U);
fredlak 0:579e15da3834 354 ADC_WR_CV1(base, 0U);
fredlak 0:579e15da3834 355 ADC_WR_CV2(base, 0U);
fredlak 0:579e15da3834 356 ADC_WR_SC2(base, 0U);
fredlak 0:579e15da3834 357 ADC_WR_SC3(base, 0U);
fredlak 0:579e15da3834 358 #if FSL_FEATURE_ADC16_HAS_PGA
fredlak 0:579e15da3834 359 ADC_WR_PGA(base, 0U);
fredlak 0:579e15da3834 360 #endif /** FSL_FEATURE_ADC16_HAS_PGA */
fredlak 0:579e15da3834 361 }
fredlak 0:579e15da3834 362
fredlak 0:579e15da3834 363 void ADC16_HAL_ConfigConverter(ADC_Type * base, const adc16_converter_config_t *configPtr)
fredlak 0:579e15da3834 364 {
fredlak 0:579e15da3834 365 uint16_t cfg1, cfg2, sc2, sc3;
fredlak 0:579e15da3834 366
fredlak 0:579e15da3834 367 cfg1 = ADC_RD_CFG1(base);
fredlak 0:579e15da3834 368 cfg1 &= ~( ADC_CFG1_ADLPC_MASK
fredlak 0:579e15da3834 369 | ADC_CFG1_ADIV_MASK
fredlak 0:579e15da3834 370 | ADC_CFG1_ADLSMP_MASK
fredlak 0:579e15da3834 371 | ADC_CFG1_MODE_MASK
fredlak 0:579e15da3834 372 | ADC_CFG1_ADICLK_MASK );
fredlak 0:579e15da3834 373
fredlak 0:579e15da3834 374 /** Low power mode. */
fredlak 0:579e15da3834 375 if (configPtr->lowPowerEnable) {
fredlak 0:579e15da3834 376 cfg1 |= ADC_CFG1_ADLPC_MASK;
fredlak 0:579e15da3834 377 }
fredlak 0:579e15da3834 378 /** Clock divider. */
fredlak 0:579e15da3834 379 cfg1 |= ADC_CFG1_ADIV(configPtr->clkDividerMode);
fredlak 0:579e15da3834 380 /** Long sample time. */
fredlak 0:579e15da3834 381 if (configPtr->longSampleTimeEnable) {
fredlak 0:579e15da3834 382 cfg1 |= ADC_CFG1_ADLSMP_MASK;
fredlak 0:579e15da3834 383 }
fredlak 0:579e15da3834 384 /** Sample resolution mode. */
fredlak 0:579e15da3834 385 cfg1 |= ADC_CFG1_MODE(configPtr->resolution);
fredlak 0:579e15da3834 386 /** Clock source input. */
fredlak 0:579e15da3834 387 cfg1 |= ADC_CFG1_ADICLK(configPtr->clkSrc);
fredlak 0:579e15da3834 388
fredlak 0:579e15da3834 389 cfg2 = ADC_RD_CFG2(base);
fredlak 0:579e15da3834 390 cfg2 &= ~( ADC_CFG2_ADACKEN_MASK
fredlak 0:579e15da3834 391 | ADC_CFG2_ADHSC_MASK
fredlak 0:579e15da3834 392 | ADC_CFG2_ADLSTS_MASK );
fredlak 0:579e15da3834 393 /** Asynchronous clock output enable. */
fredlak 0:579e15da3834 394 if (configPtr->asyncClkEnable) {
fredlak 0:579e15da3834 395 cfg2 |= ADC_CFG2_ADACKEN_MASK;
fredlak 0:579e15da3834 396 }
fredlak 0:579e15da3834 397 /** High speed configuration. */
fredlak 0:579e15da3834 398 if (configPtr->highSpeedEnable) {
fredlak 0:579e15da3834 399 cfg2 |= ADC_CFG2_ADHSC_MASK;
fredlak 0:579e15da3834 400 }
fredlak 0:579e15da3834 401 /** Long sample time select. */
fredlak 0:579e15da3834 402 cfg2 |= ADC_CFG2_ADLSTS(configPtr->longSampleCycleMode);
fredlak 0:579e15da3834 403
fredlak 0:579e15da3834 404 sc2 = ADC_RD_SC2(base);
fredlak 0:579e15da3834 405 sc2 &= ~( ADC_SC2_ADTRG_MASK
fredlak 0:579e15da3834 406 | ADC_SC2_REFSEL_MASK
fredlak 0:579e15da3834 407 #if FSL_FEATURE_ADC16_HAS_DMA
fredlak 0:579e15da3834 408 | ADC_SC2_DMAEN_MASK
fredlak 0:579e15da3834 409 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
fredlak 0:579e15da3834 410 );
fredlak 0:579e15da3834 411 /** Conversion trigger select. */
fredlak 0:579e15da3834 412 if (configPtr->hwTriggerEnable) {
fredlak 0:579e15da3834 413 sc2 |= ADC_SC2_ADTRG_MASK;
fredlak 0:579e15da3834 414 }
fredlak 0:579e15da3834 415 /** Voltage reference selection. */
fredlak 0:579e15da3834 416 sc2 |= ADC_SC2_REFSEL(configPtr->refVoltSrc);
fredlak 0:579e15da3834 417 #if FSL_FEATURE_ADC16_HAS_DMA
fredlak 0:579e15da3834 418 /** DMA. */
fredlak 0:579e15da3834 419 if (configPtr->dmaEnable) {
fredlak 0:579e15da3834 420 sc2 |= ADC_SC2_DMAEN_MASK;
fredlak 0:579e15da3834 421 }
fredlak 0:579e15da3834 422 #endif /** FSL_FEATURE_ADC16_HAS_DMA */
fredlak 0:579e15da3834 423
fredlak 0:579e15da3834 424 sc3 = ADC_RD_SC3(base);
fredlak 0:579e15da3834 425 sc3 &= ~( ADC_SC3_ADCO_MASK
fredlak 0:579e15da3834 426 | ADC_SC3_CALF_MASK );
fredlak 0:579e15da3834 427 /** Continuous conversion enable. */
fredlak 0:579e15da3834 428 if (configPtr->continuousConvEnable) {
fredlak 0:579e15da3834 429 sc3 |= ADC_SC3_ADCO_MASK;
fredlak 0:579e15da3834 430 }
fredlak 0:579e15da3834 431
fredlak 0:579e15da3834 432 ADC_WR_CFG1(base, cfg1);
fredlak 0:579e15da3834 433 ADC_WR_CFG2(base, cfg2);
fredlak 0:579e15da3834 434 ADC_WR_SC2(base, sc2);
fredlak 0:579e15da3834 435 ADC_WR_SC3(base, sc3);
fredlak 0:579e15da3834 436 }
fredlak 0:579e15da3834 437
fredlak 0:579e15da3834 438 static inline void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
fredlak 0:579e15da3834 439 {
fredlak 0:579e15da3834 440 /** call core API to enable the IRQ*/
fredlak 0:579e15da3834 441 NVIC_EnableIRQ(irqNumber);
fredlak 0:579e15da3834 442 }
fredlak 0:579e15da3834 443
fredlak 0:579e15da3834 444 adc16_status_t ADC16_DRV_Init(uint32_t instance, const adc16_converter_config_t *userConfigPtr)
fredlak 0:579e15da3834 445 {
fredlak 0:579e15da3834 446 ADC_Type * base = g_adcBase[instance];
fredlak 0:579e15da3834 447
fredlak 0:579e15da3834 448 if (!userConfigPtr) {
fredlak 0:579e15da3834 449 return kStatus_ADC16_InvalidArgument;
fredlak 0:579e15da3834 450 }
fredlak 0:579e15da3834 451 /** Enable clock for ADC. */
fredlak 0:579e15da3834 452 CLOCK_SYS_EnableAdcClock(instance);
fredlak 0:579e15da3834 453
fredlak 0:579e15da3834 454 /** Reset all the register to a known state. */
fredlak 0:579e15da3834 455 ADC16_HAL_Init(base);
fredlak 0:579e15da3834 456 ADC16_HAL_ConfigConverter(base, userConfigPtr);
fredlak 0:579e15da3834 457
fredlak 0:579e15da3834 458 /** Enable ADC interrupt in NVIC level.*/
fredlak 0:579e15da3834 459 INT_SYS_EnableIRQ(g_adcIrqId[instance] );
fredlak 0:579e15da3834 460
fredlak 0:579e15da3834 461 return kStatus_ADC16_Success;
fredlak 0:579e15da3834 462 }
fredlak 0:579e15da3834 463
fredlak 0:579e15da3834 464 static uint8_t bat_convert_data(uint16_t input)
fredlak 0:579e15da3834 465 {
fredlak 0:579e15da3834 466 uint8_t output = 0;
fredlak 0:579e15da3834 467
fredlak 0:579e15da3834 468 uint16_t bat_mvolts = (uint16_t)( ( (float)input * ( 3.3 / 65535.0 ) ) * 1000 );
fredlak 0:579e15da3834 469
fredlak 0:579e15da3834 470 if ( bat_mvolts > 2670 ) {
fredlak 0:579e15da3834 471 output = 100;
fredlak 0:579e15da3834 472 }
fredlak 0:579e15da3834 473
fredlak 0:579e15da3834 474 else if ( bat_mvolts > 2500 ) {
fredlak 0:579e15da3834 475 output = (uint8_t)( 50 + 50.0 * ( ( bat_mvolts - 2500 ) / 170.0 ) );
fredlak 0:579e15da3834 476 } else if ( bat_mvolts > 2430 ) {
fredlak 0:579e15da3834 477 output = (uint8_t)( 30 + 20.0 * ( ( bat_mvolts - 2430 ) / 70.0 ) );
fredlak 0:579e15da3834 478 } else if ( bat_mvolts > 2370 ) {
fredlak 0:579e15da3834 479 output = (uint8_t)( 10 + 20.0 * ( ( bat_mvolts - 2370 ) / 60.0 ) );
fredlak 0:579e15da3834 480 } else {
fredlak 0:579e15da3834 481 output = 0;
fredlak 0:579e15da3834 482 }
fredlak 0:579e15da3834 483 return output;
fredlak 0:579e15da3834 484
fredlak 0:579e15da3834 485 }
fredlak 0:579e15da3834 486
fredlak 0:579e15da3834 487 HexiwearBattery::HexiwearBattery()
fredlak 0:579e15da3834 488 {
fredlak 0:579e15da3834 489 batCharging = new DigitalIn(PTC12);
fredlak 0:579e15da3834 490 batSensSwitch = new DigitalOut(PTC14);
fredlak 0:579e15da3834 491 ADC16_DRV_Init(0, &BATTERY_ADC_InitConfig);
fredlak 0:579e15da3834 492 ADC16_DRV_ConfigConvChn(0, 0U, &BATTERY_ADC_ChnConfig);
fredlak 0:579e15da3834 493 }
fredlak 0:579e15da3834 494
fredlak 0:579e15da3834 495 HexiwearBattery::~HexiwearBattery()
fredlak 0:579e15da3834 496 {
fredlak 0:579e15da3834 497 delete batSensSwitch;
fredlak 0:579e15da3834 498 delete batCharging;
fredlak 0:579e15da3834 499 }
fredlak 0:579e15da3834 500
fredlak 0:579e15da3834 501 void HexiwearBattery::sensorOn()
fredlak 0:579e15da3834 502 {
fredlak 0:579e15da3834 503 *batSensSwitch = 0;
fredlak 0:579e15da3834 504 };
fredlak 0:579e15da3834 505
fredlak 0:579e15da3834 506
fredlak 0:579e15da3834 507 void HexiwearBattery::sensorOff()
fredlak 0:579e15da3834 508 {
fredlak 0:579e15da3834 509 *batSensSwitch = 1;
fredlak 0:579e15da3834 510 };
fredlak 0:579e15da3834 511
fredlak 0:579e15da3834 512 bool HexiwearBattery::isBatteryCharging()
fredlak 0:579e15da3834 513 {
fredlak 0:579e15da3834 514 return *batCharging == 0;
fredlak 0:579e15da3834 515 }
fredlak 0:579e15da3834 516
fredlak 0:579e15da3834 517 uint8_t HexiwearBattery::readLevelPercent()
fredlak 0:579e15da3834 518 {
fredlak 0:579e15da3834 519 ADC16_DRV_ConfigConvChn( 0, 0, &BATTERY_ADC_ChnConfig);
fredlak 0:579e15da3834 520 ADC16_DRV_WaitConvDone ( 0, 0 );
fredlak 0:579e15da3834 521 int16_t result = ADC16_DRV_GetConvValueSigned( 0, 0 );
fredlak 0:579e15da3834 522 ADC16_DRV_PauseConv(0, 0 );
fredlak 0:579e15da3834 523 return bat_convert_data(result);
fredlak 0:579e15da3834 524 }
fredlak 0:579e15da3834 525