Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_mcpwm.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_mcpwm.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for Motor Control PWM firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 2.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 21. May. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup MCPWM MCPWM |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_MCPWM_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_MCPWM_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "LPC17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 41 | /** @defgroup MCPWM_Public_Macros MCPWM Public Macros |
| frank26080115 | 0:84d7747641aa | 42 | * @{ |
| frank26080115 | 0:84d7747641aa | 43 | */ |
| frank26080115 | 0:84d7747641aa | 44 | |
| frank26080115 | 0:84d7747641aa | 45 | |
| frank26080115 | 0:84d7747641aa | 46 | /** Edge aligned mode for channel in MCPWM */ |
| frank26080115 | 0:84d7747641aa | 47 | #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 48 | /** Center aligned mode for channel in MCPWM */ |
| frank26080115 | 0:84d7747641aa | 49 | #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 50 | |
| frank26080115 | 0:84d7747641aa | 51 | /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ |
| frank26080115 | 0:84d7747641aa | 52 | #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 53 | /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ |
| frank26080115 | 0:84d7747641aa | 54 | #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 55 | |
| frank26080115 | 0:84d7747641aa | 56 | /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of |
| frank26080115 | 0:84d7747641aa | 57 | * the six output pins under the control of the bits in this register */ |
| frank26080115 | 0:84d7747641aa | 58 | #define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 59 | #define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 60 | #define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 61 | #define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 62 | #define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 63 | #define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 64 | |
| frank26080115 | 0:84d7747641aa | 65 | /* Interrupt type in MCPWM */ |
| frank26080115 | 0:84d7747641aa | 66 | /** Limit interrupt for channel (0) */ |
| frank26080115 | 0:84d7747641aa | 67 | #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) |
| frank26080115 | 0:84d7747641aa | 68 | /** Match interrupt for channel (0) */ |
| frank26080115 | 0:84d7747641aa | 69 | #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) |
| frank26080115 | 0:84d7747641aa | 70 | /** Capture interrupt for channel (0) */ |
| frank26080115 | 0:84d7747641aa | 71 | #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) |
| frank26080115 | 0:84d7747641aa | 72 | |
| frank26080115 | 0:84d7747641aa | 73 | /** Limit interrupt for channel (1) */ |
| frank26080115 | 0:84d7747641aa | 74 | #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) |
| frank26080115 | 0:84d7747641aa | 75 | /** Match interrupt for channel (1) */ |
| frank26080115 | 0:84d7747641aa | 76 | #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) |
| frank26080115 | 0:84d7747641aa | 77 | /** Capture interrupt for channel (1) */ |
| frank26080115 | 0:84d7747641aa | 78 | #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) |
| frank26080115 | 0:84d7747641aa | 79 | |
| frank26080115 | 0:84d7747641aa | 80 | /** Limit interrupt for channel (2) */ |
| frank26080115 | 0:84d7747641aa | 81 | #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) |
| frank26080115 | 0:84d7747641aa | 82 | /** Match interrupt for channel (2) */ |
| frank26080115 | 0:84d7747641aa | 83 | #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) |
| frank26080115 | 0:84d7747641aa | 84 | /** Capture interrupt for channel (2) */ |
| frank26080115 | 0:84d7747641aa | 85 | #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) |
| frank26080115 | 0:84d7747641aa | 86 | |
| frank26080115 | 0:84d7747641aa | 87 | /** Fast abort interrupt */ |
| frank26080115 | 0:84d7747641aa | 88 | #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT |
| frank26080115 | 0:84d7747641aa | 89 | |
| frank26080115 | 0:84d7747641aa | 90 | /** |
| frank26080115 | 0:84d7747641aa | 91 | * @} |
| frank26080115 | 0:84d7747641aa | 92 | */ |
| frank26080115 | 0:84d7747641aa | 93 | |
| frank26080115 | 0:84d7747641aa | 94 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 95 | /** @defgroup MCPWM_Private_Macros MCPWM Private Macros |
| frank26080115 | 0:84d7747641aa | 96 | * @{ |
| frank26080115 | 0:84d7747641aa | 97 | */ |
| frank26080115 | 0:84d7747641aa | 98 | |
| frank26080115 | 0:84d7747641aa | 99 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 100 | * Macro defines for MCPWM Control register |
| frank26080115 | 0:84d7747641aa | 101 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 102 | /* MCPWM Control register, these macro definitions below can be applied for these |
| frank26080115 | 0:84d7747641aa | 103 | * register type: |
| frank26080115 | 0:84d7747641aa | 104 | * - MCPWM Control read address |
| frank26080115 | 0:84d7747641aa | 105 | * - MCPWM Control set address |
| frank26080115 | 0:84d7747641aa | 106 | * - MCPWM Control clear address |
| frank26080115 | 0:84d7747641aa | 107 | */ |
| frank26080115 | 0:84d7747641aa | 108 | #define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */ |
| frank26080115 | 0:84d7747641aa | 109 | #define MCPWM_CON_CENTER(n) (((n)<=2) ? ((uint32_t)(1<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */ |
| frank26080115 | 0:84d7747641aa | 110 | #define MCPWM_CON_POLAR(n) (((n)<=2) ? ((uint32_t)(1<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */ |
| frank26080115 | 0:84d7747641aa | 111 | #define MCPWM_CON_DTE(n) (((n)<=2) ? ((uint32_t)(1<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */ |
| frank26080115 | 0:84d7747641aa | 112 | #define MCPWM_CON_DISUP(n) (((n)<=2) ? ((uint32_t)(1<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */ |
| frank26080115 | 0:84d7747641aa | 113 | #define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */ |
| frank26080115 | 0:84d7747641aa | 114 | #define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */ |
| frank26080115 | 0:84d7747641aa | 115 | #define MCPWM_CON_DCMODE ((uint32_t)(1UL<<31)) /**< 3-phase DC mode select */ |
| frank26080115 | 0:84d7747641aa | 116 | |
| frank26080115 | 0:84d7747641aa | 117 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 118 | * Macro defines for MCPWM Capture Control register |
| frank26080115 | 0:84d7747641aa | 119 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 120 | /* Capture Control register, these macro definitions below can be applied for these |
| frank26080115 | 0:84d7747641aa | 121 | * register type: |
| frank26080115 | 0:84d7747641aa | 122 | * - MCPWM Capture Control read address |
| frank26080115 | 0:84d7747641aa | 123 | * - MCPWM Capture Control set address |
| frank26080115 | 0:84d7747641aa | 124 | * - MCPWM Capture control clear address |
| frank26080115 | 0:84d7747641aa | 125 | */ |
| frank26080115 | 0:84d7747641aa | 126 | /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ |
| frank26080115 | 0:84d7747641aa | 127 | #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) ((((cap)<=2)&&((mci)<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) |
| frank26080115 | 0:84d7747641aa | 128 | /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ |
| frank26080115 | 0:84d7747641aa | 129 | #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) ((((cap)<=2)&&((mci)<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) |
| frank26080115 | 0:84d7747641aa | 130 | /** TC(n) is reset by channel (n) capture event */ |
| frank26080115 | 0:84d7747641aa | 131 | #define MCPWM_CAPCON_RT(n) (((n)<=2) ? ((uint32_t)(1<<(18+(n)))) : (0)) |
| frank26080115 | 0:84d7747641aa | 132 | /** Hardware noise filter: channel (n) capture events are delayed */ |
| frank26080115 | 0:84d7747641aa | 133 | #define MCPWM_CAPCON_HNFCAP(n) (((n)<=2) ? ((uint32_t)(1<<(21+(n)))) : (0)) |
| frank26080115 | 0:84d7747641aa | 134 | |
| frank26080115 | 0:84d7747641aa | 135 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 136 | * Macro defines for MCPWM Interrupt register |
| frank26080115 | 0:84d7747641aa | 137 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 138 | /* Interrupt registers, these macro definitions below can be applied for these |
| frank26080115 | 0:84d7747641aa | 139 | * register type: |
| frank26080115 | 0:84d7747641aa | 140 | * - MCPWM Interrupt Enable read address |
| frank26080115 | 0:84d7747641aa | 141 | * - MCPWM Interrupt Enable set address |
| frank26080115 | 0:84d7747641aa | 142 | * - MCPWM Interrupt Enable clear address |
| frank26080115 | 0:84d7747641aa | 143 | * - MCPWM Interrupt Flags read address |
| frank26080115 | 0:84d7747641aa | 144 | * - MCPWM Interrupt Flags set address |
| frank26080115 | 0:84d7747641aa | 145 | * - MCPWM Interrupt Flags clear address |
| frank26080115 | 0:84d7747641aa | 146 | */ |
| frank26080115 | 0:84d7747641aa | 147 | /** Limit interrupt for channel (n) */ |
| frank26080115 | 0:84d7747641aa | 148 | #define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) |
| frank26080115 | 0:84d7747641aa | 149 | /** Match interrupt for channel (n) */ |
| frank26080115 | 0:84d7747641aa | 150 | #define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) |
| frank26080115 | 0:84d7747641aa | 151 | /** Capture interrupt for channel (n) */ |
| frank26080115 | 0:84d7747641aa | 152 | #define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) |
| frank26080115 | 0:84d7747641aa | 153 | /** Fast abort interrupt */ |
| frank26080115 | 0:84d7747641aa | 154 | #define MCPWM_INT_ABORT ((uint32_t)(1<<15)) |
| frank26080115 | 0:84d7747641aa | 155 | |
| frank26080115 | 0:84d7747641aa | 156 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 157 | * Macro defines for MCPWM Count Control register |
| frank26080115 | 0:84d7747641aa | 158 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 159 | /* MCPWM Count Control register, these macro definitions below can be applied for these |
| frank26080115 | 0:84d7747641aa | 160 | * register type: |
| frank26080115 | 0:84d7747641aa | 161 | * - MCPWM Count Control read address |
| frank26080115 | 0:84d7747641aa | 162 | * - MCPWM Count Control set address |
| frank26080115 | 0:84d7747641aa | 163 | * - MCPWM Count Control clear address |
| frank26080115 | 0:84d7747641aa | 164 | */ |
| frank26080115 | 0:84d7747641aa | 165 | /** Counter(tc) advances on a rising edge on MCI(mci) pin */ |
| frank26080115 | 0:84d7747641aa | 166 | #define MCPWM_CNTCON_TCMCI_RE(tc,mci) ((((tc)<=2)&&((mci)<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) |
| frank26080115 | 0:84d7747641aa | 167 | /** Counter(cnt) advances on a falling edge on MCI(mci) pin */ |
| frank26080115 | 0:84d7747641aa | 168 | #define MCPWM_CNTCON_TCMCI_FE(tc,mci) ((((tc)<=2)&&((mci)<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) |
| frank26080115 | 0:84d7747641aa | 169 | /** Channel (n) is in counter mode */ |
| frank26080115 | 0:84d7747641aa | 170 | #define MCPWM_CNTCON_CNTR(n) (((n)<=2) ? ((uint32_t)(1<<(29+n))) : (0)) |
| frank26080115 | 0:84d7747641aa | 171 | |
| frank26080115 | 0:84d7747641aa | 172 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 173 | * Macro defines for MCPWM Dead-time register |
| frank26080115 | 0:84d7747641aa | 174 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 175 | /** Dead time value x for channel n */ |
| frank26080115 | 0:84d7747641aa | 176 | #define MCPWM_DT(n,x) (((n)<=2) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) |
| frank26080115 | 0:84d7747641aa | 177 | |
| frank26080115 | 0:84d7747641aa | 178 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 179 | * Macro defines for MCPWM Communication Pattern register |
| frank26080115 | 0:84d7747641aa | 180 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 181 | #define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 182 | #define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 183 | #define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 184 | #define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 185 | #define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 186 | #define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
| frank26080115 | 0:84d7747641aa | 187 | |
| frank26080115 | 0:84d7747641aa | 188 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 189 | * Macro defines for MCPWM Capture clear address register |
| frank26080115 | 0:84d7747641aa | 190 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 191 | /** Clear the MCCAP (n) register */ |
| frank26080115 | 0:84d7747641aa | 192 | #define MCPWM_CAPCLR_CAP(n) (((n)<=2) ? ((uint32_t)(1<<n)) : (0)) |
| frank26080115 | 0:84d7747641aa | 193 | |
| frank26080115 | 0:84d7747641aa | 194 | |
| frank26080115 | 0:84d7747641aa | 195 | /** |
| frank26080115 | 0:84d7747641aa | 196 | * @} |
| frank26080115 | 0:84d7747641aa | 197 | */ |
| frank26080115 | 0:84d7747641aa | 198 | |
| frank26080115 | 0:84d7747641aa | 199 | |
| frank26080115 | 0:84d7747641aa | 200 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 201 | /** @defgroup MCPWM_Public_Types MCPWM Public Types |
| frank26080115 | 0:84d7747641aa | 202 | * @{ |
| frank26080115 | 0:84d7747641aa | 203 | */ |
| frank26080115 | 0:84d7747641aa | 204 | |
| frank26080115 | 0:84d7747641aa | 205 | /** |
| frank26080115 | 0:84d7747641aa | 206 | * @brief Motor Control PWM Channel Configuration structure type definition |
| frank26080115 | 0:84d7747641aa | 207 | */ |
| frank26080115 | 0:84d7747641aa | 208 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 209 | uint32_t channelType; /**< Edge/center aligned mode for this channel, |
| frank26080115 | 0:84d7747641aa | 210 | should be: |
| frank26080115 | 0:84d7747641aa | 211 | - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode |
| frank26080115 | 0:84d7747641aa | 212 | - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode |
| frank26080115 | 0:84d7747641aa | 213 | */ |
| frank26080115 | 0:84d7747641aa | 214 | uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be: |
| frank26080115 | 0:84d7747641aa | 215 | - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH |
| frank26080115 | 0:84d7747641aa | 216 | - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW |
| frank26080115 | 0:84d7747641aa | 217 | */ |
| frank26080115 | 0:84d7747641aa | 218 | uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be: |
| frank26080115 | 0:84d7747641aa | 219 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 220 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 221 | */ |
| frank26080115 | 0:84d7747641aa | 222 | uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */ |
| frank26080115 | 0:84d7747641aa | 223 | uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers, |
| frank26080115 | 0:84d7747641aa | 224 | should be: |
| frank26080115 | 0:84d7747641aa | 225 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 226 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 227 | */ |
| frank26080115 | 0:84d7747641aa | 228 | uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */ |
| frank26080115 | 0:84d7747641aa | 229 | uint32_t channelPeriodValue; /**< MCPWM Period value */ |
| frank26080115 | 0:84d7747641aa | 230 | uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */ |
| frank26080115 | 0:84d7747641aa | 231 | } MCPWM_CHANNEL_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 232 | |
| frank26080115 | 0:84d7747641aa | 233 | /** |
| frank26080115 | 0:84d7747641aa | 234 | * @brief MCPWM Capture Configuration type definition |
| frank26080115 | 0:84d7747641aa | 235 | */ |
| frank26080115 | 0:84d7747641aa | 236 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 237 | uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */ |
| frank26080115 | 0:84d7747641aa | 238 | uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
| frank26080115 | 0:84d7747641aa | 239 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 240 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 241 | */ |
| frank26080115 | 0:84d7747641aa | 242 | uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
| frank26080115 | 0:84d7747641aa | 243 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 244 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 245 | */ |
| frank26080115 | 0:84d7747641aa | 246 | uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be: |
| frank26080115 | 0:84d7747641aa | 247 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 248 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 249 | */ |
| frank26080115 | 0:84d7747641aa | 250 | uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be: |
| frank26080115 | 0:84d7747641aa | 251 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 252 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 253 | */ |
| frank26080115 | 0:84d7747641aa | 254 | } MCPWM_CAPTURE_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 255 | |
| frank26080115 | 0:84d7747641aa | 256 | |
| frank26080115 | 0:84d7747641aa | 257 | /** |
| frank26080115 | 0:84d7747641aa | 258 | * @brief MCPWM Count Control Configuration type definition |
| frank26080115 | 0:84d7747641aa | 259 | */ |
| frank26080115 | 0:84d7747641aa | 260 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 261 | uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */ |
| frank26080115 | 0:84d7747641aa | 262 | uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
| frank26080115 | 0:84d7747641aa | 263 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 264 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 265 | */ |
| frank26080115 | 0:84d7747641aa | 266 | uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
| frank26080115 | 0:84d7747641aa | 267 | - ENABLE. |
| frank26080115 | 0:84d7747641aa | 268 | - DISABLE. |
| frank26080115 | 0:84d7747641aa | 269 | */ |
| frank26080115 | 0:84d7747641aa | 270 | } MCPWM_COUNT_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 271 | |
| frank26080115 | 0:84d7747641aa | 272 | /** |
| frank26080115 | 0:84d7747641aa | 273 | * @} |
| frank26080115 | 0:84d7747641aa | 274 | */ |
| frank26080115 | 0:84d7747641aa | 275 | |
| frank26080115 | 0:84d7747641aa | 276 | |
| frank26080115 | 0:84d7747641aa | 277 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 278 | /** @defgroup MCPWM_Public_Functions MCPWM Public Functions |
| frank26080115 | 0:84d7747641aa | 279 | * @{ |
| frank26080115 | 0:84d7747641aa | 280 | */ |
| frank26080115 | 0:84d7747641aa | 281 | |
| frank26080115 | 0:84d7747641aa | 282 | void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx); |
| frank26080115 | 0:84d7747641aa | 283 | void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| frank26080115 | 0:84d7747641aa | 284 | MCPWM_CHANNEL_CFG_Type * channelSetup); |
| frank26080115 | 0:84d7747641aa | 285 | void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| frank26080115 | 0:84d7747641aa | 286 | MCPWM_CHANNEL_CFG_Type *channelSetup); |
| frank26080115 | 0:84d7747641aa | 287 | void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| frank26080115 | 0:84d7747641aa | 288 | MCPWM_CAPTURE_CFG_Type *captureConfig); |
| frank26080115 | 0:84d7747641aa | 289 | void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
| frank26080115 | 0:84d7747641aa | 290 | uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
| frank26080115 | 0:84d7747641aa | 291 | void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| frank26080115 | 0:84d7747641aa | 292 | uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig); |
| frank26080115 | 0:84d7747641aa | 293 | void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
| frank26080115 | 0:84d7747641aa | 294 | void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
| frank26080115 | 0:84d7747641aa | 295 | void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode); |
| frank26080115 | 0:84d7747641aa | 296 | void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode, |
| frank26080115 | 0:84d7747641aa | 297 | uint32_t outputInvered, uint32_t outputPattern); |
| frank26080115 | 0:84d7747641aa | 298 | void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 299 | void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 300 | void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 301 | FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 302 | |
| frank26080115 | 0:84d7747641aa | 303 | /** |
| frank26080115 | 0:84d7747641aa | 304 | * @} |
| frank26080115 | 0:84d7747641aa | 305 | */ |
| frank26080115 | 0:84d7747641aa | 306 | |
| frank26080115 | 0:84d7747641aa | 307 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 308 | } |
| frank26080115 | 0:84d7747641aa | 309 | #endif |
| frank26080115 | 0:84d7747641aa | 310 | |
| frank26080115 | 0:84d7747641aa | 311 | #endif /* LPC17XX_MCPWM_H_ */ |
| frank26080115 | 0:84d7747641aa | 312 | |
| frank26080115 | 0:84d7747641aa | 313 | /** |
| frank26080115 | 0:84d7747641aa | 314 | * @} |
| frank26080115 | 0:84d7747641aa | 315 | */ |
| frank26080115 | 0:84d7747641aa | 316 | |
| frank26080115 | 0:84d7747641aa | 317 | /* --------------------------------- End Of File ------------------------------ */ |