frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #if !defined(__FSL_RTC_HAL_H__)
bogdanm 82:6473597d706e 31 #define __FSL_RTC_HAL_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33
bogdanm 82:6473597d706e 34 #include "fsl_rtc_features.h"
bogdanm 82:6473597d706e 35 #include "fsl_device_registers.h"
bogdanm 82:6473597d706e 36
bogdanm 82:6473597d706e 37 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 38 #include "fsl_rtc_hal_monotonic.h"
bogdanm 82:6473597d706e 39 #endif
bogdanm 82:6473597d706e 40 #if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL
bogdanm 82:6473597d706e 41 #include "fsl_rtc_hal_access_control.h"
bogdanm 82:6473597d706e 42 #endif
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 #include <stdint.h>
bogdanm 82:6473597d706e 45 #include <stdbool.h>
bogdanm 82:6473597d706e 46
bogdanm 82:6473597d706e 47 /*!
bogdanm 82:6473597d706e 48 * @addtogroup rtc_hal
bogdanm 82:6473597d706e 49 * @{
bogdanm 82:6473597d706e 50 */
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 /*******************************************************************************
bogdanm 82:6473597d706e 53 * Definitions
bogdanm 82:6473597d706e 54 ******************************************************************************/
bogdanm 82:6473597d706e 55
bogdanm 82:6473597d706e 56 typedef struct rtc_hal_init_config
bogdanm 82:6473597d706e 57 {
bogdanm 82:6473597d706e 58
bogdanm 82:6473597d706e 59 /*! Configures the oscillator load in pF. \n
bogdanm 82:6473597d706e 60 * Example:\n
bogdanm 82:6473597d706e 61 * value 0 => to be configured: 0pF \n
bogdanm 82:6473597d706e 62 * value 2 => to be configured: 2pF \n
bogdanm 82:6473597d706e 63 * value 4 => to be configured: 4pF \n
bogdanm 82:6473597d706e 64 * value 8 => to be configured: 8pF \n
bogdanm 82:6473597d706e 65 * value 16 => to be configured: 16pF \n
bogdanm 82:6473597d706e 66 * Any other value is ignored.
bogdanm 82:6473597d706e 67 */
bogdanm 82:6473597d706e 68 uint8_t enableOscillatorLoadConfg;
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 bool disableClockOutToPeripheral; /*!< at register field CR[CLKO]*/
bogdanm 82:6473597d706e 71
bogdanm 82:6473597d706e 72 /*! After enabling this, waits the oscillator startup time before enabling
bogdanm 82:6473597d706e 73 * the time counter TSR[TSR] to allow the 32.768 kHz clock time to stabilize.
bogdanm 82:6473597d706e 74 */
bogdanm 82:6473597d706e 75 bool enable32kOscillator; /*!< at register field CR[OSCE]*/
bogdanm 82:6473597d706e 76
bogdanm 82:6473597d706e 77 #if FSL_FEATURE_RTC_HAS_WAKEUP_PIN
bogdanm 82:6473597d706e 78 /*! For devices that have the wakeup pin, this variable indicates whether it is
bogdanm 82:6473597d706e 79 * to be enabled (set to 'true') or not (set to 'false') at the initialization
bogdanm 82:6473597d706e 80 * function.\n
bogdanm 82:6473597d706e 81 * See the device's user manual for details depending on each device
bogdanm 82:6473597d706e 82 * specific wakeup pin feature implementation.
bogdanm 82:6473597d706e 83 */
bogdanm 82:6473597d706e 84 bool enableWakeupPin;
bogdanm 82:6473597d706e 85 #endif
bogdanm 82:6473597d706e 86
bogdanm 82:6473597d706e 87 /*! Sets the register field TSR[TSR]. Set to zero to skip this configuration.*/
bogdanm 82:6473597d706e 88 uint32_t startSecondsCounterAt;
bogdanm 82:6473597d706e 89
bogdanm 82:6473597d706e 90 /*! Sets the register field TPR[TPR]. Set to zero to skip this configuration.*/
bogdanm 82:6473597d706e 91 uint16_t prescalerAt;
bogdanm 82:6473597d706e 92
bogdanm 82:6473597d706e 93 /*! Sets the register field TAR[TAR]. Set to zero to skip this configuration.*/
bogdanm 82:6473597d706e 94 uint32_t alarmCounterAt;
bogdanm 82:6473597d706e 95
bogdanm 82:6473597d706e 96 /*! Configures the compensation interval in seconds from 1 to 256 to control
bogdanm 82:6473597d706e 97 * how frequently the TCR should adjusts the number of 32.768 kHz cycles in
bogdanm 82:6473597d706e 98 * each second. The value written should be one less than the number of
bogdanm 82:6473597d706e 99 * seconds (for example, write zero to configure for a compensation interval
bogdanm 82:6473597d706e 100 * of one second). This register is double-buffered and writes do not take
bogdanm 82:6473597d706e 101 * affect until the end of the current compensation interval.\n
bogdanm 82:6473597d706e 102 * Set to zero to skip this configuration.
bogdanm 82:6473597d706e 103 */
bogdanm 82:6473597d706e 104 uint8_t compensationInterval;
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 /*! Configures the number of 32.768 kHz clock cycles in each second. This
bogdanm 82:6473597d706e 107 * register is double-buffered and writes do not take affect until the end
bogdanm 82:6473597d706e 108 * of the current compensation interval.\n
bogdanm 82:6473597d706e 109 * \n
bogdanm 82:6473597d706e 110 * 80h Time prescaler register overflows every 32896 clock cycles.\n
bogdanm 82:6473597d706e 111 * ... ...\n
bogdanm 82:6473597d706e 112 * FFh Time prescaler register overflows every 32769 clock cycles.\n
bogdanm 82:6473597d706e 113 * 00h Time prescaler register overflows every 32768 clock cycles.\n
bogdanm 82:6473597d706e 114 * 01h Time prescaler register overflows every 32767 clock cycles.\n
bogdanm 82:6473597d706e 115 * ... ...\n
bogdanm 82:6473597d706e 116 * 7Fh Time prescaler register overflows every 32641 clock cycles.\n
bogdanm 82:6473597d706e 117 */
bogdanm 82:6473597d706e 118 uint8_t timeCompensation;
bogdanm 82:6473597d706e 119
bogdanm 82:6473597d706e 120 /*! Sets/clears any of the following bitfields to enable/disable the
bogdanm 82:6473597d706e 121 * respective interrupts.\n
bogdanm 82:6473597d706e 122 * TSIE: Time Seconds Interrupt Enable \n
bogdanm 82:6473597d706e 123 * TAIE: Time Alarm Interrupt Enable \n
bogdanm 82:6473597d706e 124 * TOIE: Time Overflow Interrupt Enable \n
bogdanm 82:6473597d706e 125 * TIIE: Time Invalid Interrupt Enable \n
bogdanm 82:6473597d706e 126 * \n
bogdanm 82:6473597d706e 127 * For MCUs that have the Wakeup Pin only: \n
bogdanm 82:6473597d706e 128 * WPON: Wakeup Pin On (see the corresponding MCU's reference manual)\n
bogdanm 82:6473597d706e 129 * \n
bogdanm 82:6473597d706e 130 * For MCUs that have the Monotonic Counter only: \n
bogdanm 82:6473597d706e 131 * MOIE: Monotonic Overflow Interrupt Enable \n
bogdanm 82:6473597d706e 132 */
bogdanm 82:6473597d706e 133 hw_rtc_ier_t enableInterrupts;
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 136 /*! Sets the Monotonic Counter to the pointed variable's value.
bogdanm 82:6473597d706e 137 * To skip setting a value or if does not apply set pointer to NULL.
bogdanm 82:6473597d706e 138 */
bogdanm 82:6473597d706e 139 uint64_t * monotonicCounterAt;
bogdanm 82:6473597d706e 140 #endif
bogdanm 82:6473597d706e 141
bogdanm 82:6473597d706e 142 } rtc_hal_init_config_t;
bogdanm 82:6473597d706e 143
bogdanm 82:6473597d706e 144 /*******************************************************************************
bogdanm 82:6473597d706e 145 * API
bogdanm 82:6473597d706e 146 ******************************************************************************/
bogdanm 82:6473597d706e 147
bogdanm 82:6473597d706e 148 #if defined(__cplusplus)
bogdanm 82:6473597d706e 149 extern "C" {
bogdanm 82:6473597d706e 150 #endif
bogdanm 82:6473597d706e 151
bogdanm 82:6473597d706e 152 /*! @brief Initializes the RTC module.
bogdanm 82:6473597d706e 153 *
bogdanm 82:6473597d706e 154 * @param configs Pointer to a structure where the configuration details are
bogdanm 82:6473597d706e 155 * stored at. The structure values that do NOT apply to the
bogdanm 82:6473597d706e 156 * MCU in use are ignored.
bogdanm 82:6473597d706e 157 */
bogdanm 82:6473597d706e 158 void rtc_hal_init(rtc_hal_init_config_t * configs);
bogdanm 82:6473597d706e 159
bogdanm 82:6473597d706e 160
bogdanm 82:6473597d706e 161 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 162 /* RTC Register Reset Functions*/
bogdanm 82:6473597d706e 163 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 164
bogdanm 82:6473597d706e 165 /*! @brief Resets the RTC Time Seconds Register (RTC_TSR).*/
bogdanm 82:6473597d706e 166 static inline void rtc_hal_reset_reg_TSR(void)
bogdanm 82:6473597d706e 167 {
bogdanm 82:6473597d706e 168 HW_RTC_TSR_WR((uint32_t)0x00000000U);
bogdanm 82:6473597d706e 169 }
bogdanm 82:6473597d706e 170
bogdanm 82:6473597d706e 171 /*! @brief Resets the RTC Time Prescaler Register (RTC_TPR).*/
bogdanm 82:6473597d706e 172 static inline void rtc_hal_reset_reg_TPR(void)
bogdanm 82:6473597d706e 173 {
bogdanm 82:6473597d706e 174 HW_RTC_TPR_WR((uint32_t)0x00000000U);
bogdanm 82:6473597d706e 175 }
bogdanm 82:6473597d706e 176
bogdanm 82:6473597d706e 177 /*! @brief Resets the RTC Time Alarm Register (RTC_TAR).*/
bogdanm 82:6473597d706e 178 static inline void rtc_hal_reset_reg_TAR(void)
bogdanm 82:6473597d706e 179 {
bogdanm 82:6473597d706e 180 HW_RTC_TAR_WR((uint32_t)0x00000000U);
bogdanm 82:6473597d706e 181 }
bogdanm 82:6473597d706e 182
bogdanm 82:6473597d706e 183 /*! @brief Resets the RTC Time Compensation Register (RTC_TCR).*/
bogdanm 82:6473597d706e 184 static inline void rtc_hal_reset_reg_TCR(void)
bogdanm 82:6473597d706e 185 {
bogdanm 82:6473597d706e 186 HW_RTC_TCR_WR((uint32_t)0x00000000U);
bogdanm 82:6473597d706e 187 }
bogdanm 82:6473597d706e 188
bogdanm 82:6473597d706e 189 /*! @brief Resets the RTC Control Register (RTC_CR).*/
bogdanm 82:6473597d706e 190 static inline void rtc_hal_reset_reg_CR(void)
bogdanm 82:6473597d706e 191 {
bogdanm 82:6473597d706e 192 HW_RTC_CR_WR((uint32_t)0x00000000U);
bogdanm 82:6473597d706e 193 }
bogdanm 82:6473597d706e 194
bogdanm 82:6473597d706e 195 /*! @brief Resets the RTC Status Register (RTC_SR).*/
bogdanm 82:6473597d706e 196 static inline void rtc_hal_reset_reg_SR(void)
bogdanm 82:6473597d706e 197 {
bogdanm 82:6473597d706e 198 HW_RTC_SR_WR((uint32_t)0x00000001U);
bogdanm 82:6473597d706e 199 }
bogdanm 82:6473597d706e 200
bogdanm 82:6473597d706e 201 /*! @brief Resets the RTC Lock Register (RTC_LR).*/
bogdanm 82:6473597d706e 202 static inline void rtc_hal_reset_reg_LR(void)
bogdanm 82:6473597d706e 203 {
bogdanm 82:6473597d706e 204 #if (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
bogdanm 82:6473597d706e 205 defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
bogdanm 82:6473597d706e 206 defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
bogdanm 82:6473597d706e 207 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \
bogdanm 82:6473597d706e 208 defined(CPU_MK22FN512VDC12))
bogdanm 82:6473597d706e 209
bogdanm 82:6473597d706e 210 HW_RTC_LR_WR((uint32_t)0x000000FFU);
bogdanm 82:6473597d706e 211
bogdanm 82:6473597d706e 212 #elif (defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ12) || \
bogdanm 82:6473597d706e 213 defined(CPU_MK70FX512VMJ15) || defined(CPU_MK70FN1M0VMJ15) || \
bogdanm 82:6473597d706e 214 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || \
bogdanm 82:6473597d706e 215 defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12))
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 HW_RTC_LR_WR((uint32_t)0x0000FFFFU);
bogdanm 82:6473597d706e 218
bogdanm 82:6473597d706e 219 #else
bogdanm 82:6473597d706e 220 #error "No valid CPU defined"
bogdanm 82:6473597d706e 221 #endif
bogdanm 82:6473597d706e 222 }
bogdanm 82:6473597d706e 223
bogdanm 82:6473597d706e 224 /*! @brief Resets the RTC Interrupt Enable Register (RTC_IER).*/
bogdanm 82:6473597d706e 225 static inline void rtc_hal_reset_reg_IER(void)
bogdanm 82:6473597d706e 226 {
bogdanm 82:6473597d706e 227 HW_RTC_IER_WR((uint32_t)0x00000007U);
bogdanm 82:6473597d706e 228 }
bogdanm 82:6473597d706e 229
bogdanm 82:6473597d706e 230 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 231 /* RTC Time Seconds*/
bogdanm 82:6473597d706e 232 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 233
bogdanm 82:6473597d706e 234 /*! @brief Reads the value of the time seconds counter.
bogdanm 82:6473597d706e 235 * @param Seconds [out] pointer to variable where the seconds are stored.
bogdanm 82:6473597d706e 236 */
bogdanm 82:6473597d706e 237 static inline void rtc_hal_get_seconds(uint32_t * seconds)
bogdanm 82:6473597d706e 238 {
bogdanm 82:6473597d706e 239 /* When the time counter is enabled, the TSR is read only and increments
bogdanm 82:6473597d706e 240 * once a second provided SR[TOF] and SR[TIF] are not set. The time counter
bogdanm 82:6473597d706e 241 * reads as zero when SR[TOF] or SR[TIF] are set. When the time counter
bogdanm 82:6473597d706e 242 * is disabled, the TSR can be read or written. */
bogdanm 82:6473597d706e 243 *seconds = BR_RTC_TSR_TSR;
bogdanm 82:6473597d706e 244
bogdanm 82:6473597d706e 245 }
bogdanm 82:6473597d706e 246
bogdanm 82:6473597d706e 247 /*! @brief Writes to the time seconds counter.
bogdanm 82:6473597d706e 248 * @param seconds [in] pointer to a variable from where to write the seconds.
bogdanm 82:6473597d706e 249 * @return true: write success since time counter is disabled.
bogdanm 82:6473597d706e 250 * false: write error since time counter is enabled.
bogdanm 82:6473597d706e 251 */
bogdanm 82:6473597d706e 252 static inline bool rtc_hal_set_seconds(const uint32_t * seconds)
bogdanm 82:6473597d706e 253 {
bogdanm 82:6473597d706e 254 /* When the time counter is enabled, the TSR is read only and increments
bogdanm 82:6473597d706e 255 * once a second provided SR[TOF] or SR[TIF] are not set. The time counter
bogdanm 82:6473597d706e 256 * reads as zero when SR[TOF] or SR[TIF] are set. When the time counter
bogdanm 82:6473597d706e 257 * is disabled, the TSR can be read or written. Writing to the TSR when the
bogdanm 82:6473597d706e 258 * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing
bogdanm 82:6473597d706e 259 * to the TSR register with zero is supported, but not recommended since TSR
bogdanm 82:6473597d706e 260 * reads as zero when SR[TIF] or SR[TOF] are set (indicating the time is
bogdanm 82:6473597d706e 261 * invalid). */
bogdanm 82:6473597d706e 262
bogdanm 82:6473597d706e 263 bool result = false;
bogdanm 82:6473597d706e 264
bogdanm 82:6473597d706e 265 if(!(BR_RTC_SR_TCE))
bogdanm 82:6473597d706e 266 {
bogdanm 82:6473597d706e 267 BW_RTC_TSR_TSR(*seconds); /* jgsp: add write to prescaler with 0x00 before writing to TSR.*/
bogdanm 82:6473597d706e 268 result = true;
bogdanm 82:6473597d706e 269 }
bogdanm 82:6473597d706e 270
bogdanm 82:6473597d706e 271 return result;
bogdanm 82:6473597d706e 272 }
bogdanm 82:6473597d706e 273
bogdanm 82:6473597d706e 274 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 275 /* RTC Time Prescaler*/
bogdanm 82:6473597d706e 276 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 277
bogdanm 82:6473597d706e 278 /*! @brief Reads the value of the time prescaler.
bogdanm 82:6473597d706e 279 * @param prescale [out] pointer to variable where the prescaler's value
bogdanm 82:6473597d706e 280 * is stored.
bogdanm 82:6473597d706e 281 */
bogdanm 82:6473597d706e 282 static inline void rtc_hal_get_prescaler(uint16_t * prescale)
bogdanm 82:6473597d706e 283 {
bogdanm 82:6473597d706e 284 /* When the time counter is enabled, the TPR is read only and increments
bogdanm 82:6473597d706e 285 * every 32.768 kHz clock cycle. The time counter reads as zero when
bogdanm 82:6473597d706e 286 * SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TPR
bogdanm 82:6473597d706e 287 * can be read or written. The TSR[TSR] increments when bit 14 of the TPR
bogdanm 82:6473597d706e 288 * transitions from a logic one to a logic zero. */
bogdanm 82:6473597d706e 289 *prescale = BR_RTC_TPR_TPR;
bogdanm 82:6473597d706e 290
bogdanm 82:6473597d706e 291 }
bogdanm 82:6473597d706e 292
bogdanm 82:6473597d706e 293 /*! @brief Sets the time prescaler.
bogdanm 82:6473597d706e 294 * @param prescale [in] pointer to variable from where to write the
bogdanm 82:6473597d706e 295 * seconds.
bogdanm 82:6473597d706e 296 * @return true: set successfull; false: error, unable to set prescaler
bogdanm 82:6473597d706e 297 * since the the time counter is enabled.
bogdanm 82:6473597d706e 298 */
bogdanm 82:6473597d706e 299 static inline bool rtc_hal_set_prescaler(const uint16_t * prescale)
bogdanm 82:6473597d706e 300 {
bogdanm 82:6473597d706e 301 /* When the time counter is enabled, the TPR is read only and increments
bogdanm 82:6473597d706e 302 * every 32.768 kHz clock cycle. The time counter reads as zero when the
bogdanm 82:6473597d706e 303 * SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TPR
bogdanm 82:6473597d706e 304 * can be read or written. The TSR[TSR] increments when bit 14 of the TPR
bogdanm 82:6473597d706e 305 * transitions from a logic one to a logic zero. */
bogdanm 82:6473597d706e 306 bool result = false;
bogdanm 82:6473597d706e 307
bogdanm 82:6473597d706e 308 if(!(BR_RTC_SR_TCE))
bogdanm 82:6473597d706e 309 {
bogdanm 82:6473597d706e 310 BW_RTC_TPR_TPR(*prescale);
bogdanm 82:6473597d706e 311 result = true;
bogdanm 82:6473597d706e 312 }
bogdanm 82:6473597d706e 313
bogdanm 82:6473597d706e 314 return result;
bogdanm 82:6473597d706e 315
bogdanm 82:6473597d706e 316 }
bogdanm 82:6473597d706e 317
bogdanm 82:6473597d706e 318 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 319 /* RTC Time Alarm*/
bogdanm 82:6473597d706e 320 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 321
bogdanm 82:6473597d706e 322 /*! @brief Reads the value of the time alarm.
bogdanm 82:6473597d706e 323 * @param seconds [out] pointer to a variable where the alarm value in seconds
bogdanm 82:6473597d706e 324 * will be stored.
bogdanm 82:6473597d706e 325 */
bogdanm 82:6473597d706e 326 static inline void rtc_hal_get_alarm(uint32_t * seconds)
bogdanm 82:6473597d706e 327 {
bogdanm 82:6473597d706e 328 *seconds = BR_RTC_TAR_TAR;
bogdanm 82:6473597d706e 329 }
bogdanm 82:6473597d706e 330
bogdanm 82:6473597d706e 331 /*! @brief Sets the time alarm, this clears the time alarm flag.
bogdanm 82:6473597d706e 332 * @param seconds [in] pointer to variable from where to write alarm value
bogdanm 82:6473597d706e 333 * in seconds.
bogdanm 82:6473597d706e 334 */
bogdanm 82:6473597d706e 335 static inline void rtc_hal_set_alarm(const uint32_t * seconds)
bogdanm 82:6473597d706e 336 {
bogdanm 82:6473597d706e 337 /* When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
bogdanm 82:6473597d706e 338 * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR
bogdanm 82:6473597d706e 339 * clears the SR[TAF]. */
bogdanm 82:6473597d706e 340 BW_RTC_TAR_TAR(*seconds);
bogdanm 82:6473597d706e 341 }
bogdanm 82:6473597d706e 342
bogdanm 82:6473597d706e 343 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 344 /* RTC Time Compensation*/
bogdanm 82:6473597d706e 345 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 346
bogdanm 82:6473597d706e 347 /*! @brief Reads the compensation interval counter value.*/
bogdanm 82:6473597d706e 348 /*! @param counter [out] pointer to variable where the value is stored.*/
bogdanm 82:6473597d706e 349 static inline void rtc_hal_get_comp_intrvl_counter(uint8_t * counter)
bogdanm 82:6473597d706e 350 {
bogdanm 82:6473597d706e 351 *counter = BR_RTC_TCR_CIC;
bogdanm 82:6473597d706e 352 }
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 /*! @brief Reads the current time compensation interval counter value.
bogdanm 82:6473597d706e 355 * @param tcValue [out] pointer to variable where the value is stored.
bogdanm 82:6473597d706e 356 */
bogdanm 82:6473597d706e 357 static inline void rtc_hal_get_current_time_compensation(uint8_t * tcValue)
bogdanm 82:6473597d706e 358 {
bogdanm 82:6473597d706e 359 *tcValue = BR_RTC_TCR_TCV;
bogdanm 82:6473597d706e 360 }
bogdanm 82:6473597d706e 361
bogdanm 82:6473597d706e 362 /*! @brief Reads the compensation interval. The value is the configured
bogdanm 82:6473597d706e 363 * compensation interval in seconds from 1 to 256 to control
bogdanm 82:6473597d706e 364 * how frequently the time compensation register should adjust the
bogdanm 82:6473597d706e 365 * number of 32.768 kHz cycles in each second. The value is one
bogdanm 82:6473597d706e 366 * less than the number of seconds (for example. Zero means a
bogdanm 82:6473597d706e 367 * configuration for a compensation interval of one second).
bogdanm 82:6473597d706e 368 * @param value [out] pointer to variable where the value is stored.
bogdanm 82:6473597d706e 369 */
bogdanm 82:6473597d706e 370 static inline void rtc_hal_get_compensation_interval(uint8_t * value)
bogdanm 82:6473597d706e 371 {
bogdanm 82:6473597d706e 372 *value = BR_RTC_TCR_CIR;
bogdanm 82:6473597d706e 373 }
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 /*! @brief Writes the compensation interval. This configures the
bogdanm 82:6473597d706e 376 * compensation interval in seconds from 1 to 256 to control
bogdanm 82:6473597d706e 377 * how frequently the TCR should adjust the number of 32.768 kHz
bogdanm 82:6473597d706e 378 * cycles in each second. The value written should be one less than
bogdanm 82:6473597d706e 379 * the number of seconds (for example, write zero to configure for
bogdanm 82:6473597d706e 380 * a compensation interval of one second). This register is double
bogdanm 82:6473597d706e 381 * buffered and writes do not take affect until the end of the
bogdanm 82:6473597d706e 382 * current compensation interval.
bogdanm 82:6473597d706e 383 * @param value [in] pointer to a variable from where to write the value.
bogdanm 82:6473597d706e 384 */
bogdanm 82:6473597d706e 385 static inline void rtc_hal_set_compensation_interval(const uint8_t * value)
bogdanm 82:6473597d706e 386 {
bogdanm 82:6473597d706e 387 BW_RTC_TCR_CIR(*value);
bogdanm 82:6473597d706e 388 }
bogdanm 82:6473597d706e 389
bogdanm 82:6473597d706e 390 /*! @brief Reads the time compensation value which is the configured number
bogdanm 82:6473597d706e 391 * of the 32.768 kHz clock cycles in each second.
bogdanm 82:6473597d706e 392 * @param value [out] pointer to variable where the value is stored.
bogdanm 82:6473597d706e 393 */
bogdanm 82:6473597d706e 394 static inline void rtc_hal_get_time_compensation(uint8_t * value)
bogdanm 82:6473597d706e 395 {
bogdanm 82:6473597d706e 396 *value = BR_RTC_TCR_TCR;
bogdanm 82:6473597d706e 397 }
bogdanm 82:6473597d706e 398
bogdanm 82:6473597d706e 399 /*! @brief Writes to the RTC Time Compensation Register (RTC_TCR), field
bogdanm 82:6473597d706e 400 * Time Compensation Register (TCR). Configuring the number of
bogdanm 82:6473597d706e 401 * 32.768 kHz clock cycles in each second. This register is double
bogdanm 82:6473597d706e 402 * buffered and writes do not take affect until the end of the
bogdanm 82:6473597d706e 403 * current compensation interval.\n
bogdanm 82:6473597d706e 404 * 80h Time prescaler register overflows every 32896 clock cycles.\n
bogdanm 82:6473597d706e 405 * ... ...\n
bogdanm 82:6473597d706e 406 * FFh Time prescaler register overflows every 32769 clock cycles.\n
bogdanm 82:6473597d706e 407 * 00h Time prescaler register overflows every 32768 clock cycles.\n
bogdanm 82:6473597d706e 408 * 01h Time prescaler register overflows every 32767 clock cycles.\n
bogdanm 82:6473597d706e 409 * ... ...\n
bogdanm 82:6473597d706e 410 * 7Fh Time prescaler register overflows every 32641 clock cycles.\n
bogdanm 82:6473597d706e 411 * @param enable [in] pointer to variable from where to write the value.
bogdanm 82:6473597d706e 412 */
bogdanm 82:6473597d706e 413 static inline void rtc_hal_set_time_compensation(const uint8_t * enable)
bogdanm 82:6473597d706e 414 {
bogdanm 82:6473597d706e 415 BW_RTC_TCR_TCR(*enable);
bogdanm 82:6473597d706e 416 }
bogdanm 82:6473597d706e 417
bogdanm 82:6473597d706e 418 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 419 /* RTC Control*/
bogdanm 82:6473597d706e 420 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 421
bogdanm 82:6473597d706e 422 /*! @brief Enables/disables oscillator configuration for 2pF load.*/
bogdanm 82:6473597d706e 423 /*! @param enable true: enables load; false: disables load.*/
bogdanm 82:6473597d706e 424 static inline void rtc_hal_config_osc_2pf_load(bool enable)
bogdanm 82:6473597d706e 425 {
bogdanm 82:6473597d706e 426 BW_RTC_CR_SC2P(enable);
bogdanm 82:6473597d706e 427 }
bogdanm 82:6473597d706e 428
bogdanm 82:6473597d706e 429 /*! @brief Enables/disables oscillator configuration for 4pF load.*/
bogdanm 82:6473597d706e 430 /*! @param enable true: enables load; false: disables load.*/
bogdanm 82:6473597d706e 431 static inline void rtc_hal_config_osc_4pf_load(bool enable)
bogdanm 82:6473597d706e 432 {
bogdanm 82:6473597d706e 433 BW_RTC_CR_SC4P(enable);
bogdanm 82:6473597d706e 434 }
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 /*! @brief Enables/disables oscillator configuration for 8pF load.*/
bogdanm 82:6473597d706e 437 /*! @param enable true: enables load; false: disables load.*/
bogdanm 82:6473597d706e 438 static inline void rtc_hal_config_osc_8pf_load(bool enable)
bogdanm 82:6473597d706e 439 {
bogdanm 82:6473597d706e 440 BW_RTC_CR_SC8P(enable);
bogdanm 82:6473597d706e 441 }
bogdanm 82:6473597d706e 442
bogdanm 82:6473597d706e 443 /*! @brief Enables/disables oscillator configuration for 16pF load.*/
bogdanm 82:6473597d706e 444 /*! @param enable true: enables load; false: disables load.*/
bogdanm 82:6473597d706e 445 static inline void rtc_hal_config_osc_16pf_load(bool enable)
bogdanm 82:6473597d706e 446 {
bogdanm 82:6473597d706e 447 BW_RTC_CR_SC16P(enable);
bogdanm 82:6473597d706e 448 }
bogdanm 82:6473597d706e 449
bogdanm 82:6473597d706e 450 /*! @brief Enables/disables the 32kHz clock output to other peripherals.*/
bogdanm 82:6473597d706e 451 /*! @param enable true: enables clock out; false: disables clock out.*/
bogdanm 82:6473597d706e 452 static inline void rtc_hal_config_clock_out(bool enable)
bogdanm 82:6473597d706e 453 {
bogdanm 82:6473597d706e 454 BW_RTC_CR_CLKO(!enable);
bogdanm 82:6473597d706e 455 }
bogdanm 82:6473597d706e 456
bogdanm 82:6473597d706e 457 /*! @brief Enables/disables the oscillator. After enablement, wait the
bogdanm 82:6473597d706e 458 * oscillator startup time before enabling the time counter to
bogdanm 82:6473597d706e 459 * allow the 32.768 kHz clock time to stabilize.
bogdanm 82:6473597d706e 460 * @param enable true: enables oscillator; false: disables oscillator.
bogdanm 82:6473597d706e 461 */
bogdanm 82:6473597d706e 462 static inline void rtc_hal_config_oscillator(bool enable)
bogdanm 82:6473597d706e 463 {
bogdanm 82:6473597d706e 464 BW_RTC_CR_OSCE(enable);
bogdanm 82:6473597d706e 465 }
bogdanm 82:6473597d706e 466
bogdanm 82:6473597d706e 467 /*! @brief Enables/disables the update mode. This mode allows the time counter
bogdanm 82:6473597d706e 468 * enabled to be written even when the status register is locked.
bogdanm 82:6473597d706e 469 * When set, the time counter enable, can always be written if the
bogdanm 82:6473597d706e 470 * TIF (Time Invalid Flag) or TOF (Time Overflow Flag) are set or
bogdanm 82:6473597d706e 471 * if the time counter enable is clear. For devices with the
bogdanm 82:6473597d706e 472 * monotonic counter, it allows the monotonic enable to be written
bogdanm 82:6473597d706e 473 * when it is locked. When set, the monotonic enable can always be
bogdanm 82:6473597d706e 474 * written if the TIF (Time Invalid Flag) or TOF (Time Overflow Flag)
bogdanm 82:6473597d706e 475 * are set or if the monotonic counter enable is clear.
bogdanm 82:6473597d706e 476 * For devices with tamper detect, it allows the it to be written
bogdanm 82:6473597d706e 477 * when it is locked. When set, the tamper detect can always be
bogdanm 82:6473597d706e 478 * written if the TIF (Time Invalid Flag) is clear.
bogdanm 82:6473597d706e 479 * Note: Tamper and Monotonic features are not available in all MCUs.
bogdanm 82:6473597d706e 480 * @param lock true: enables register lock, registers cannot be written
bogdanm 82:6473597d706e 481 * when locked; False: disables register lock, registers
bogdanm 82:6473597d706e 482 * can be written when locked under limited conditions.
bogdanm 82:6473597d706e 483 */
bogdanm 82:6473597d706e 484 static inline void rtc_hal_configure_update_mode(bool lock)
bogdanm 82:6473597d706e 485 {
bogdanm 82:6473597d706e 486 BW_RTC_CR_UM(lock);
bogdanm 82:6473597d706e 487 }
bogdanm 82:6473597d706e 488
bogdanm 82:6473597d706e 489 /*! @brief Enables/disables the supervisor access, which configures
bogdanm 82:6473597d706e 490 * non-supervisor mode write access to all RTC registers and
bogdanm 82:6473597d706e 491 * non-supervisor mode read access to RTC tamper/monotonic registers.
bogdanm 82:6473597d706e 492 * Note: Tamper and Monotonic features are NOT available in all MCUs.
bogdanm 82:6473597d706e 493 * @param enable_reg_write true: enables register lock, Non-supervisor
bogdanm 82:6473597d706e 494 * mode write accesses are supported; false: disables register
bogdanm 82:6473597d706e 495 * lock, non-supervisor mode write accesses are not supported and
bogdanm 82:6473597d706e 496 * generate a bus error.
bogdanm 82:6473597d706e 497 */
bogdanm 82:6473597d706e 498 static inline void rtc_hal_configure_supervisor_access(bool enable_reg_write)
bogdanm 82:6473597d706e 499 {
bogdanm 82:6473597d706e 500 BW_RTC_CR_SUP(enable_reg_write);
bogdanm 82:6473597d706e 501 }
bogdanm 82:6473597d706e 502
bogdanm 82:6473597d706e 503 #if FSL_FEATURE_RTC_HAS_WAKEUP_PIN
bogdanm 82:6473597d706e 504 /*! @brief Enables/disables the wakeup pin.
bogdanm 82:6473597d706e 505 * Note: The wakeup pin is optional and not available on all devices.
bogdanm 82:6473597d706e 506 * @param enable_wp true: enables wakeup-pin, wakeup pin asserts if the
bogdanm 82:6473597d706e 507 * RTC interrupt asserts and the chip is powered down;
bogdanm 82:6473597d706e 508 * false: disables wakeup-pin.
bogdanm 82:6473597d706e 509 */
bogdanm 82:6473597d706e 510 static inline void rtc_hal_config_wakeup_pin(bool enable_wp)
bogdanm 82:6473597d706e 511 {
bogdanm 82:6473597d706e 512 BW_RTC_CR_WPE(enable_wp);
bogdanm 82:6473597d706e 513 }
bogdanm 82:6473597d706e 514 #endif
bogdanm 82:6473597d706e 515
bogdanm 82:6473597d706e 516 /*! @brief Performs a software reset on the RTC module. This resets all
bogdanm 82:6473597d706e 517 * RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
bogdanm 82:6473597d706e 518 * registers. The SWR bit is cleared after VBAT POR and by software
bogdanm 82:6473597d706e 519 * explicitly clearing it.
bogdanm 82:6473597d706e 520 * Note: access control features (RTC_WAR and RTC_RAR registers)
bogdanm 82:6473597d706e 521 * are not available in all MCUs.
bogdanm 82:6473597d706e 522 */
bogdanm 82:6473597d706e 523 static inline void rtc_hal_software_reset(void)
bogdanm 82:6473597d706e 524 {
bogdanm 82:6473597d706e 525 BW_RTC_CR_SWR(1u);
bogdanm 82:6473597d706e 526 }
bogdanm 82:6473597d706e 527
bogdanm 82:6473597d706e 528 /*! @brief Clears the software reset flag.*/
bogdanm 82:6473597d706e 529 static inline void rtc_hal_software_reset_flag_clear(void)
bogdanm 82:6473597d706e 530 {
bogdanm 82:6473597d706e 531 BW_RTC_CR_SWR(0u);
bogdanm 82:6473597d706e 532 }
bogdanm 82:6473597d706e 533
bogdanm 82:6473597d706e 534 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 535 /* RTC Status*/
bogdanm 82:6473597d706e 536 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 537
bogdanm 82:6473597d706e 538 /*! @brief Reads the time counter enabled/disabled status.
bogdanm 82:6473597d706e 539 * @return true: time counter is enabled, time seconds register and time
bogdanm 82:6473597d706e 540 * prescaler register are not writeable, but increment; false: time
bogdanm 82:6473597d706e 541 * counter is disabled, time seconds register and time prescaler
bogdanm 82:6473597d706e 542 * register are writeable, but do not increment. */
bogdanm 82:6473597d706e 543 static inline bool rtc_hal_is_counter_enabled(void)
bogdanm 82:6473597d706e 544 {
bogdanm 82:6473597d706e 545 return (bool)BR_RTC_SR_TCE;
bogdanm 82:6473597d706e 546 }
bogdanm 82:6473597d706e 547
bogdanm 82:6473597d706e 548 /*! @brief Changes the time counter enabled/disabled status.
bogdanm 82:6473597d706e 549 * @param enable true: enables the time counter;
bogdanm 82:6473597d706e 550 * false: disables the time counter.
bogdanm 82:6473597d706e 551 */
bogdanm 82:6473597d706e 552 static inline void rtc_hal_counter_enable(bool enable)
bogdanm 82:6473597d706e 553 {
bogdanm 82:6473597d706e 554 BW_RTC_SR_TCE(enable);
bogdanm 82:6473597d706e 555 }
bogdanm 82:6473597d706e 556
bogdanm 82:6473597d706e 557 /*! @brief Checks if the configured time alarm occurred.
bogdanm 82:6473597d706e 558 * @return true: time alarm has occurred.
bogdanm 82:6473597d706e 559 * false: NO time alarm occurred.
bogdanm 82:6473597d706e 560 */
bogdanm 82:6473597d706e 561 static inline bool rtc_hal_is_alarm_occured(void)
bogdanm 82:6473597d706e 562 {
bogdanm 82:6473597d706e 563 /* Reads time alarm flag (TAF). This flag is set when the time
bogdanm 82:6473597d706e 564 * alarm register (TAR) equals the time seconds register (TSR) and
bogdanm 82:6473597d706e 565 * the TSR increments. This flag is cleared by writing the TAR register. */
bogdanm 82:6473597d706e 566 return (bool)BR_RTC_SR_TAF;
bogdanm 82:6473597d706e 567 }
bogdanm 82:6473597d706e 568
bogdanm 82:6473597d706e 569 /*! @brief Checks whether a counter overflow happened.
bogdanm 82:6473597d706e 570 * @return true: time overflow occurred and time counter is zero.
bogdanm 82:6473597d706e 571 * false: NO time overflow occurred.
bogdanm 82:6473597d706e 572 */
bogdanm 82:6473597d706e 573 static inline bool rtc_hal_is_counter_overflow(void)
bogdanm 82:6473597d706e 574 {
bogdanm 82:6473597d706e 575 /* Reads the value of RTC Status Register (RTC_SR), field Time
bogdanm 82:6473597d706e 576 * Overflow Flag (TOF). This flag is set when the time counter is
bogdanm 82:6473597d706e 577 * enabled and overflows. The TSR and TPR do not increment and read
bogdanm 82:6473597d706e 578 * as zero when this bit is set. This flag is cleared by writing the
bogdanm 82:6473597d706e 579 * TSR register when the time counter is disabled. */
bogdanm 82:6473597d706e 580 return (bool)BR_RTC_SR_TOF;
bogdanm 82:6473597d706e 581 }
bogdanm 82:6473597d706e 582
bogdanm 82:6473597d706e 583 /*! @brief Checks whether the time is marked as invalid.
bogdanm 82:6473597d706e 584 * @return true: time is INVALID and time counter is zero.
bogdanm 82:6473597d706e 585 * false: time is valid.
bogdanm 82:6473597d706e 586 */
bogdanm 82:6473597d706e 587 static inline bool rtc_hal_is_time_invalid(void)
bogdanm 82:6473597d706e 588 {
bogdanm 82:6473597d706e 589 /*! Reads the value of the RTC Status Register (RTC_SR), field Time
bogdanm 82:6473597d706e 590 * Invalid Flag (TIF). This flag is set on the VBAT POR or the software
bogdanm 82:6473597d706e 591 * reset. The TSR and TPR do not increment and read as zero when
bogdanm 82:6473597d706e 592 * this bit is set. This flag is cleared by writing the TSR
bogdanm 82:6473597d706e 593 * register when the time counter is disabled. */
bogdanm 82:6473597d706e 594 return (bool)BR_RTC_SR_TIF;
bogdanm 82:6473597d706e 595 }
bogdanm 82:6473597d706e 596
bogdanm 82:6473597d706e 597 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 598 /* RTC Lock*/
bogdanm 82:6473597d706e 599 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 600
bogdanm 82:6473597d706e 601 /*! @brief Configures the register lock to other module fields.
bogdanm 82:6473597d706e 602 * @param bitfields [in] configuration flags:\n
bogdanm 82:6473597d706e 603 * Valid bitfields:\n
bogdanm 82:6473597d706e 604 * LRL: Lock Register Lock \n
bogdanm 82:6473597d706e 605 * SRL: Status Register Lock \n
bogdanm 82:6473597d706e 606 * CRL: Control Register Lock \n
bogdanm 82:6473597d706e 607 * TCL: Time Compensation Lock \n
bogdanm 82:6473597d706e 608 *
bogdanm 82:6473597d706e 609 * For MCUs that have the Tamper Detect only: \n
bogdanm 82:6473597d706e 610 * TIL: Tamper Interrupt Lock \n
bogdanm 82:6473597d706e 611 * TTL: Tamper Trim Lock \n
bogdanm 82:6473597d706e 612 * TDL: Tamper Detect Lock \n
bogdanm 82:6473597d706e 613 * TEL: Tamper Enable Lock \n
bogdanm 82:6473597d706e 614 * TTSL: Tamper Time Seconds Lock \n
bogdanm 82:6473597d706e 615 *
bogdanm 82:6473597d706e 616 * For MCUs that have the Monotonic Counter only: \n
bogdanm 82:6473597d706e 617 * MCHL: Monotonic Counter High Lock \n
bogdanm 82:6473597d706e 618 * MCLL: Monotonic Counter Low Lock \n
bogdanm 82:6473597d706e 619 * MEL: Monotonic Enable Lock \n
bogdanm 82:6473597d706e 620 */
bogdanm 82:6473597d706e 621 static inline void rtc_hal_config_lock_registers(hw_rtc_lr_t bitfields)
bogdanm 82:6473597d706e 622 {
bogdanm 82:6473597d706e 623 uint32_t valid_flags = 0;
bogdanm 82:6473597d706e 624
bogdanm 82:6473597d706e 625 valid_flags |= (BM_RTC_LR_LRL | BM_RTC_LR_SRL | BM_RTC_LR_CRL |
bogdanm 82:6473597d706e 626 BM_RTC_LR_TCL);
bogdanm 82:6473597d706e 627
bogdanm 82:6473597d706e 628 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 629 valid_flags |= (BM_RTC_LR_MCHL | BM_RTC_LR_MCLL | BM_RTC_LR_MEL);
bogdanm 82:6473597d706e 630 #endif
bogdanm 82:6473597d706e 631 HW_RTC_LR_WR((bitfields.U) & valid_flags);
bogdanm 82:6473597d706e 632
bogdanm 82:6473597d706e 633 }
bogdanm 82:6473597d706e 634
bogdanm 82:6473597d706e 635 /*! @brief Obtains the lock status of the lock register.
bogdanm 82:6473597d706e 636 * @return true: lock register is not locked and writes complete normally.
bogdanm 82:6473597d706e 637 * false: lock register is locked and writes are ignored.
bogdanm 82:6473597d706e 638 */
bogdanm 82:6473597d706e 639 static inline bool rtc_hal_get_lock_reg_lock(void)
bogdanm 82:6473597d706e 640 {
bogdanm 82:6473597d706e 641 /* Reads the value of the RTC Lock Register (RTC_LR),
bogdanm 82:6473597d706e 642 * field Lock Register Lock (LRL). Once cleared, this flag can
bogdanm 82:6473597d706e 643 * only be set by VBAT POR or software reset. */
bogdanm 82:6473597d706e 644 return (bool)BR_RTC_LR_LRL;
bogdanm 82:6473597d706e 645 }
bogdanm 82:6473597d706e 646
bogdanm 82:6473597d706e 647 /*! @brief Changes the lock status of the lock register. Once cleared,
bogdanm 82:6473597d706e 648 * this can only be set by the VBAT POR or the software reset.
bogdanm 82:6473597d706e 649 * @param set_to true: Lock register is not locked and writes complete normally.
bogdanm 82:6473597d706e 650 * false: Lock register is locked and writes are ignored.
bogdanm 82:6473597d706e 651 */
bogdanm 82:6473597d706e 652 static inline void rtc_hal_set_lock_reg_lock(bool set_to)
bogdanm 82:6473597d706e 653 {
bogdanm 82:6473597d706e 654 /* Writes to the RTC Lock Register (RTC_LR), field Lock Register Lock (LRL).
bogdanm 82:6473597d706e 655 * Once cleared, this flag can only be set by VBAT POR or software reset. */
bogdanm 82:6473597d706e 656 BW_RTC_LR_LRL((uint32_t) set_to);
bogdanm 82:6473597d706e 657 }
bogdanm 82:6473597d706e 658
bogdanm 82:6473597d706e 659 /*! @brief Obtains the state of the status register lock.
bogdanm 82:6473597d706e 660 * @return true: Status register is not locked and writes complete
bogdanm 82:6473597d706e 661 * normally.
bogdanm 82:6473597d706e 662 * false: Status register is locked and writes are ignored.
bogdanm 82:6473597d706e 663 */
bogdanm 82:6473597d706e 664 static inline bool rtc_hal_get_status_reg_lock(void)
bogdanm 82:6473597d706e 665 {
bogdanm 82:6473597d706e 666 /* Reads the value of the RTC Lock Register (RTC_LR), field Status Register
bogdanm 82:6473597d706e 667 * Lock (SRL). Once cleared, this flag can only be set by VBAT POR or software
bogdanm 82:6473597d706e 668 * reset. */
bogdanm 82:6473597d706e 669 return (bool)BR_RTC_LR_SRL;
bogdanm 82:6473597d706e 670 }
bogdanm 82:6473597d706e 671
bogdanm 82:6473597d706e 672 /*! @brief Changes the state of the status register lock. Once cleared,
bogdanm 82:6473597d706e 673 * this can only be set by the VBAT POR or the software reset.
bogdanm 82:6473597d706e 674 * @param set_to true: Status register is not locked and writes complete
bogdanm 82:6473597d706e 675 * normally.
bogdanm 82:6473597d706e 676 * false: Status register is locked and writes are ignored.
bogdanm 82:6473597d706e 677 */
bogdanm 82:6473597d706e 678 static inline void rtc_hal_set_status_reg_lock(bool set_to)
bogdanm 82:6473597d706e 679 {
bogdanm 82:6473597d706e 680 BW_RTC_LR_SRL((uint32_t) set_to);
bogdanm 82:6473597d706e 681 }
bogdanm 82:6473597d706e 682
bogdanm 82:6473597d706e 683 /*! @brief Obtains the state of the control register lock
bogdanm 82:6473597d706e 684 * @return true: Control register is not locked and writes complete
bogdanm 82:6473597d706e 685 * normally.
bogdanm 82:6473597d706e 686 * false: Control register is locked and writes are ignored.
bogdanm 82:6473597d706e 687 */
bogdanm 82:6473597d706e 688 static inline bool rtc_hal_get_control_reg_lock(void)
bogdanm 82:6473597d706e 689 {
bogdanm 82:6473597d706e 690 /* Reads the value of the RTC Lock Register (RTC_LR), field Control Register
bogdanm 82:6473597d706e 691 * Lock (CRL). Once cleared, this flag can only be set by the VBAT POR or the software
bogdanm 82:6473597d706e 692 * reset. */
bogdanm 82:6473597d706e 693 return (bool)BR_RTC_LR_CRL;
bogdanm 82:6473597d706e 694 }
bogdanm 82:6473597d706e 695
bogdanm 82:6473597d706e 696 /*! @brief Changes the state of the control register lock. Once cleared,
bogdanm 82:6473597d706e 697 * this can only be set by the VBAT POR or the software reset.
bogdanm 82:6473597d706e 698 * @param set_to true: Control register is not locked and writes complete
bogdanm 82:6473597d706e 699 * normally.
bogdanm 82:6473597d706e 700 * false: Control register is locked and writes are ignored.
bogdanm 82:6473597d706e 701 */
bogdanm 82:6473597d706e 702 static inline void rtc_hal_set_control_reg_lock(bool set_to)
bogdanm 82:6473597d706e 703 {
bogdanm 82:6473597d706e 704 /* Writes to the RTC Lock Register (RTC_LR), field Control Register Lock (CRL).
bogdanm 82:6473597d706e 705 * Once cleared, this flag can only be set by VBAT POR or software reset. */
bogdanm 82:6473597d706e 706 BW_RTC_LR_CRL((uint32_t) set_to);
bogdanm 82:6473597d706e 707 }
bogdanm 82:6473597d706e 708
bogdanm 82:6473597d706e 709 /*! @brief Obtains the state of the time compensation lock.
bogdanm 82:6473597d706e 710 * @return true: Time compensation register is not locked and writes
bogdanm 82:6473597d706e 711 * complete normally.
bogdanm 82:6473597d706e 712 * false: Time compensation register is locked and writes are
bogdanm 82:6473597d706e 713 * ignored.
bogdanm 82:6473597d706e 714 */
bogdanm 82:6473597d706e 715 static inline bool rtc_hal_get_time_comp_lock(void)
bogdanm 82:6473597d706e 716 {
bogdanm 82:6473597d706e 717 /* Reads the value of the RTC Lock Register (RTC_LR), field Time Compensation
bogdanm 82:6473597d706e 718 * Lock (TCL). Once cleared, this flag can only be set by VBAT POR or software
bogdanm 82:6473597d706e 719 * reset. */
bogdanm 82:6473597d706e 720 return (bool)BR_RTC_LR_TCL;
bogdanm 82:6473597d706e 721 }
bogdanm 82:6473597d706e 722
bogdanm 82:6473597d706e 723 /*! @brief Changes the state of the time compensation lock. Once cleared,
bogdanm 82:6473597d706e 724 * this can only be set by the VBAT POR or the software reset.
bogdanm 82:6473597d706e 725 * @param set_to true: Time compensation register is not locked and writes
bogdanm 82:6473597d706e 726 * complete normally.
bogdanm 82:6473597d706e 727 * false: Time compensation register is locked and writes are
bogdanm 82:6473597d706e 728 * ignored.
bogdanm 82:6473597d706e 729 */
bogdanm 82:6473597d706e 730 static inline void rtc_hal_set_time_comp_lock(bool set_to)
bogdanm 82:6473597d706e 731 {
bogdanm 82:6473597d706e 732 /* Writes to the RTC Lock Register (RTC_LR), field Time Compensation Lock (TCL).
bogdanm 82:6473597d706e 733 * Once cleared, this flag can only be set by VBAT POR or software reset. */
bogdanm 82:6473597d706e 734 BW_RTC_LR_TCL((uint32_t) set_to);
bogdanm 82:6473597d706e 735 }
bogdanm 82:6473597d706e 736
bogdanm 82:6473597d706e 737 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 738 /* RTC Interrupt Enable*/
bogdanm 82:6473597d706e 739 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 740
bogdanm 82:6473597d706e 741 /*! @brief Enables/disables RTC interrupts.
bogdanm 82:6473597d706e 742 * @param bitfields [in] set/clear respective bitfields to enabled/disabled
bogdanm 82:6473597d706e 743 * interrupts. \n
bogdanm 82:6473597d706e 744 * [out] resulting interrupt enable state. \n
bogdanm 82:6473597d706e 745 * Valid bitfields: \n
bogdanm 82:6473597d706e 746 * TSIE: Time Seconds Interrupt Enable \n
bogdanm 82:6473597d706e 747 * TAIE: Time Alarm Interrupt Enable \n
bogdanm 82:6473597d706e 748 * TOIE: Time Overflow Interrupt Enable \n
bogdanm 82:6473597d706e 749 * TIIE: Time Invalid Interrupt Enable \n
bogdanm 82:6473597d706e 750 * \n
bogdanm 82:6473597d706e 751 * For MCUs that have the Wakeup Pin only: \n
bogdanm 82:6473597d706e 752 * WPON: Wakeup Pin On (see the corresponding MCU's reference manual)\n
bogdanm 82:6473597d706e 753 * \n
bogdanm 82:6473597d706e 754 * For MCUs that have the Monotonic Counter only: \n
bogdanm 82:6473597d706e 755 * MOIE: Monotonic Overflow Interrupt Enable \n
bogdanm 82:6473597d706e 756 */
bogdanm 82:6473597d706e 757 static inline void rtc_hal_config_interrupts(hw_rtc_ier_t * bitfields)
bogdanm 82:6473597d706e 758 {
bogdanm 82:6473597d706e 759 HW_RTC_IER_WR((bitfields->U) & ( BM_RTC_IER_TSIE | BM_RTC_IER_TAIE | BM_RTC_IER_TOIE |
bogdanm 82:6473597d706e 760 BM_RTC_IER_TIIE));
bogdanm 82:6473597d706e 761
bogdanm 82:6473597d706e 762 #if FSL_FEATURE_RTC_HAS_WAKEUP_PIN
bogdanm 82:6473597d706e 763 BW_RTC_IER_WPON(bitfields->B.WPON);
bogdanm 82:6473597d706e 764 #endif
bogdanm 82:6473597d706e 765 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 766 BW_RTC_IER_MOIE(bitfields->B.MOIE);
bogdanm 82:6473597d706e 767 #endif
bogdanm 82:6473597d706e 768
bogdanm 82:6473597d706e 769 bitfields->U = HW_RTC_IER_RD();
bogdanm 82:6473597d706e 770 }
bogdanm 82:6473597d706e 771
bogdanm 82:6473597d706e 772 /*! @brief Checks whether the Time Seconds Interrupt is enabled/disabled.
bogdanm 82:6473597d706e 773 * @return true: Seconds interrupt is enabled.
bogdanm 82:6473597d706e 774 * false: Seconds interrupt is disabled.
bogdanm 82:6473597d706e 775 */
bogdanm 82:6473597d706e 776 static inline bool rtc_hal_read_seconds_int_enable(void)
bogdanm 82:6473597d706e 777 {
bogdanm 82:6473597d706e 778 /* Reads the value of the RTC Interrupt Enable Register (RTC_IER), field Time
bogdanm 82:6473597d706e 779 * Seconds Interrupt Enable (TSIE). The seconds interrupt is an edge-sensitive
bogdanm 82:6473597d706e 780 * interrupt with a dedicated interrupt vector. It is generated once a second
bogdanm 82:6473597d706e 781 * and requires no software overhead (there is no corresponding status flag to
bogdanm 82:6473597d706e 782 * clear). */
bogdanm 82:6473597d706e 783 return (bool)BR_RTC_IER_TSIE;
bogdanm 82:6473597d706e 784 }
bogdanm 82:6473597d706e 785
bogdanm 82:6473597d706e 786 /*! @brief Enables/disables the Time Seconds Interrupt.
bogdanm 82:6473597d706e 787 * Note: The seconds interrupt is an edge-sensitive interrupt with a
bogdanm 82:6473597d706e 788 * dedicated interrupt vector. It is generated once a second and
bogdanm 82:6473597d706e 789 * requires no software overhead (there is no corresponding status
bogdanm 82:6473597d706e 790 * flag to clear).
bogdanm 82:6473597d706e 791 * @param enable true: Seconds interrupt is enabled.
bogdanm 82:6473597d706e 792 * false: Seconds interrupt is disabled.
bogdanm 82:6473597d706e 793 */
bogdanm 82:6473597d706e 794 static inline void rtc_hal_config_seconds_int(bool enable)
bogdanm 82:6473597d706e 795 {
bogdanm 82:6473597d706e 796 /* Writes to the RTC Interrupt Enable Register (RTC_IER), field Time Seconds
bogdanm 82:6473597d706e 797 * Interrupt Enable (TSIE). The seconds interrupt is an edge-sensitive
bogdanm 82:6473597d706e 798 * interrupt with a dedicated interrupt vector. It is generated once a second
bogdanm 82:6473597d706e 799 * and requires no software overhead (there is no corresponding status flag to
bogdanm 82:6473597d706e 800 * clear). */
bogdanm 82:6473597d706e 801 BW_RTC_IER_TSIE((uint32_t) enable);
bogdanm 82:6473597d706e 802 }
bogdanm 82:6473597d706e 803
bogdanm 82:6473597d706e 804 /*! @brief Checks whether the Time Alarm Interrupt is enabled/disabled.
bogdanm 82:6473597d706e 805 * @return true: Time alarm flag does generate an interrupt.
bogdanm 82:6473597d706e 806 * false: Time alarm flag does not generate an interrupt.
bogdanm 82:6473597d706e 807 */
bogdanm 82:6473597d706e 808 static inline bool rtc_hal_read_alarm_int_enable(void)
bogdanm 82:6473597d706e 809 {
bogdanm 82:6473597d706e 810 /* Reads the value of the RTC Interrupt Enable Register (RTC_IER),
bogdanm 82:6473597d706e 811 * field Time Alarm Interrupt Enable (TAIE). */
bogdanm 82:6473597d706e 812 return (bool)BR_RTC_IER_TAIE;
bogdanm 82:6473597d706e 813 }
bogdanm 82:6473597d706e 814
bogdanm 82:6473597d706e 815 /*! @brief Enables/disables the Time Alarm Interrupt.
bogdanm 82:6473597d706e 816 * @param enable true: Time alarm flag does generate an interrupt.
bogdanm 82:6473597d706e 817 * false: Time alarm flag does not generate an interrupt.
bogdanm 82:6473597d706e 818 */
bogdanm 82:6473597d706e 819 static inline void rtc_hal_config_alarm_int_enable(bool enable)
bogdanm 82:6473597d706e 820 {
bogdanm 82:6473597d706e 821 /* Writes to the RTC Interrupt Enable Register (RTC_IER), field Time Alarm
bogdanm 82:6473597d706e 822 * Interrupt Enable (TAIE). */
bogdanm 82:6473597d706e 823 BW_RTC_IER_TAIE((uint32_t) enable);
bogdanm 82:6473597d706e 824 }
bogdanm 82:6473597d706e 825
bogdanm 82:6473597d706e 826 /*! @brief Checks whether the Time Overflow Interrupt is enabled/disabled .
bogdanm 82:6473597d706e 827 * @return true: Time overflow flag does generate an interrupt.
bogdanm 82:6473597d706e 828 * false: Time overflow flag does not generate an interrupt.
bogdanm 82:6473597d706e 829 */
bogdanm 82:6473597d706e 830 static inline bool rtc_hal_read_time_overflow_int_enable(void)
bogdanm 82:6473597d706e 831 {
bogdanm 82:6473597d706e 832 /* Reads the value of the RTC Interrupt Enable Register (RTC_IER), field
bogdanm 82:6473597d706e 833 * Time Overflow Interrupt Enable (TOIE). */
bogdanm 82:6473597d706e 834 return (bool)BR_RTC_IER_TOIE;
bogdanm 82:6473597d706e 835 }
bogdanm 82:6473597d706e 836
bogdanm 82:6473597d706e 837 /*! @brief Enables/disables the Time Overflow Interrupt.
bogdanm 82:6473597d706e 838 * @param enable true: Time overflow flag does generate an interrupt.
bogdanm 82:6473597d706e 839 * false: Time overflow flag does not generate an interrupt.
bogdanm 82:6473597d706e 840 */
bogdanm 82:6473597d706e 841 static inline void rtc_hal_config_time_overflow_int_enable(bool enable)
bogdanm 82:6473597d706e 842 {
bogdanm 82:6473597d706e 843 /* Writes to the RTC Interrupt Enable Register (RTC_IER),
bogdanm 82:6473597d706e 844 * field Time Overflow Interrupt Enable (TOIE). */
bogdanm 82:6473597d706e 845 BW_RTC_IER_TOIE((uint32_t) enable);
bogdanm 82:6473597d706e 846 }
bogdanm 82:6473597d706e 847
bogdanm 82:6473597d706e 848 /*! @brief Checks whether the Time Invalid Interrupt is enabled/disabled.
bogdanm 82:6473597d706e 849 * @return true: Time invalid flag does generate an interrupt.
bogdanm 82:6473597d706e 850 * false: Time invalid flag does not generate an interrupt.
bogdanm 82:6473597d706e 851 */
bogdanm 82:6473597d706e 852 static inline bool rtc_hal_read_time_interval_int_enable(void)
bogdanm 82:6473597d706e 853 {
bogdanm 82:6473597d706e 854 /* Reads the value of the RTC Interrupt Enable Register (RTC_IER), field Time
bogdanm 82:6473597d706e 855 * Invalid Interrupt Enable (TIIE). */
bogdanm 82:6473597d706e 856 return (bool)BR_RTC_IER_TIIE;
bogdanm 82:6473597d706e 857 }
bogdanm 82:6473597d706e 858
bogdanm 82:6473597d706e 859 /*! @brief Enables/disables the Time Invalid Interrupt.
bogdanm 82:6473597d706e 860 * @param enable true: Time invalid flag does generate an interrupt.
bogdanm 82:6473597d706e 861 * false: Time invalid flag does not generate an interrupt.
bogdanm 82:6473597d706e 862 */
bogdanm 82:6473597d706e 863 static inline void rtc_hal_config_time_interval_int(bool enable)
bogdanm 82:6473597d706e 864 {
bogdanm 82:6473597d706e 865 /* writes to the RTC Interrupt Enable Register (RTC_IER), field Time Invalid
bogdanm 82:6473597d706e 866 * Interrupt Enable (TIIE). */
bogdanm 82:6473597d706e 867 BW_RTC_IER_TIIE((uint32_t) enable);
bogdanm 82:6473597d706e 868 }
bogdanm 82:6473597d706e 869
bogdanm 82:6473597d706e 870
bogdanm 82:6473597d706e 871 #if defined(__cplusplus)
bogdanm 82:6473597d706e 872 }
bogdanm 82:6473597d706e 873 #endif
bogdanm 82:6473597d706e 874
bogdanm 82:6473597d706e 875
bogdanm 82:6473597d706e 876 /*! @}*/
bogdanm 82:6473597d706e 877
bogdanm 82:6473597d706e 878 #endif /* __FSL_RTC_HAL_H__*/
bogdanm 82:6473597d706e 879
bogdanm 82:6473597d706e 880 /*******************************************************************************
bogdanm 82:6473597d706e 881 * EOF
bogdanm 82:6473597d706e 882 ******************************************************************************/
bogdanm 82:6473597d706e 883