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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e
Child:: 90:cb3d968589d8

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	82:6473597d706e	6	* are permitted provided that the following conditions are met:
bogdanm	82:6473597d706e	7	*
bogdanm	82:6473597d706e	8	* o Redistributions of source code must retain the above copyright notice, this list
bogdanm	82:6473597d706e	9	* of conditions and the following disclaimer.
bogdanm	82:6473597d706e	10	*
bogdanm	82:6473597d706e	11	* o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm	82:6473597d706e	12	* list of conditions and the following disclaimer in the documentation and/or
bogdanm	82:6473597d706e	13	* other materials provided with the distribution.
bogdanm	82:6473597d706e	14	*
bogdanm	82:6473597d706e	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm	82:6473597d706e	16	* contributors may be used to endorse or promote products derived from this
bogdanm	82:6473597d706e	17	* software without specific prior written permission.
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm	82:6473597d706e	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm	82:6473597d706e	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	82:6473597d706e	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm	82:6473597d706e	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm	82:6473597d706e	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm	82:6473597d706e	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm	82:6473597d706e	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm	82:6473597d706e	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm	82:6473597d706e	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	82:6473597d706e	29	*/
bogdanm	82:6473597d706e	30
bogdanm	82:6473597d706e	31	#if !defined(__FSL_MCG_HAL_H__)
bogdanm	82:6473597d706e	32	#define __FSL_MCG_HAL_H__
bogdanm	82:6473597d706e	33
bogdanm	82:6473597d706e	34	#include <stdint.h>
bogdanm	82:6473597d706e	35	#include <stdbool.h>
bogdanm	82:6473597d706e	36	#include <assert.h>
bogdanm	82:6473597d706e	37	#include "fsl_device_registers.h"
bogdanm	82:6473597d706e	38	#include "fsl_mcg_features.h"
bogdanm	82:6473597d706e	39
bogdanm	82:6473597d706e	40	/! @addtogroup mcg_hal/
bogdanm	82:6473597d706e	41	/! @{/
bogdanm	82:6473597d706e	42
bogdanm	82:6473597d706e	43	/! @file fsl_mcg_hal.h /
bogdanm	82:6473597d706e	44
bogdanm	82:6473597d706e	45	/*******************************************************************************
bogdanm	82:6473597d706e	46	* Definitions
bogdanm	82:6473597d706e	47	******************************************************************************/
bogdanm	82:6473597d706e	48	/! @brief MCG constant definitions/
bogdanm	82:6473597d706e	49	enum _mcg_constant
bogdanm	82:6473597d706e	50	{
bogdanm	82:6473597d706e	51	kMcgConstant1 = (1u),
bogdanm	82:6473597d706e	52	kMcgConstant5 = (5u),
bogdanm	82:6473597d706e	53
bogdanm	82:6473597d706e	54	kMcgConstant640 = (640u),
bogdanm	82:6473597d706e	55	kMcgConstant1280 = (1280u),
bogdanm	82:6473597d706e	56	kMcgConstant1920 = (1920u),
bogdanm	82:6473597d706e	57	kMcgConstant2560 = (2560u),
bogdanm	82:6473597d706e	58	kMcgConstant732 = (732u),
bogdanm	82:6473597d706e	59	kMcgConstant1464 = (1464u),
bogdanm	82:6473597d706e	60	kMcgConstant2197 = (2197u),
bogdanm	82:6473597d706e	61	kMcgConstant2929 = (2929u),
bogdanm	82:6473597d706e	62
bogdanm	82:6473597d706e	63	kMcgConstantHex20 = (0x20u),
bogdanm	82:6473597d706e	64	kMcgConstantHex40 = (0x40u),
bogdanm	82:6473597d706e	65	kMcgConstantHex60 = (0x60u),
bogdanm	82:6473597d706e	66	kMcgConstantHex80 = (0x80u),
bogdanm	82:6473597d706e	67	kMcgConstantHexA0 = (0xA0u),
bogdanm	82:6473597d706e	68	kMcgConstantHexC0 = (0xC0u),
bogdanm	82:6473597d706e	69	kMcgConstantHexE0 = (0xE0u)
bogdanm	82:6473597d706e	70	};
bogdanm	82:6473597d706e	71
bogdanm	82:6473597d706e	72	/! @brief MCG clock source select /
bogdanm	82:6473597d706e	73	typedef enum _mcg_clock_select
bogdanm	82:6473597d706e	74	{
bogdanm	82:6473597d706e	75	kMcgClockSelectOut, /* Output of FLL or PLLCS is selected(depends on PLLS bit) */
bogdanm	82:6473597d706e	76	kMcgClockSelectIn, /* Internal reference clock is selected */
bogdanm	82:6473597d706e	77	kMcgClockSelectExt, /* External reference clock is selected */
bogdanm	82:6473597d706e	78	kMcgClockSelectReserved
bogdanm	82:6473597d706e	79	} mcg_clock_select_t;
bogdanm	82:6473597d706e	80
bogdanm	82:6473597d706e	81	/! @brief MCG internal reference clock source select /
bogdanm	82:6473597d706e	82	typedef enum _mcg_iref_clock_source
bogdanm	82:6473597d706e	83	{
bogdanm	82:6473597d706e	84	kMcgIrefClockSourceExt, /* External reference clock is selected */
bogdanm	82:6473597d706e	85	kMcgIrefClockSourceSlow /* The slow internal reference clock is selected */
bogdanm	82:6473597d706e	86	} mcg_iref_clock_source_t;
bogdanm	82:6473597d706e	87
bogdanm	82:6473597d706e	88	/! @brief MCG frequency range select /
bogdanm	82:6473597d706e	89	typedef enum _mcg_freq_range_select
bogdanm	82:6473597d706e	90	{
bogdanm	82:6473597d706e	91	kMcgFreqRangeSelectLow, /* Low frequency range selected for the crystal OSC */
bogdanm	82:6473597d706e	92	kMcgFreqRangeSelectHigh, /* High frequency range selected for the crystal OSC */
bogdanm	82:6473597d706e	93	kMcgFreqRangeSelectVeryHigh, /* Very High frequency range selected for the crystal OSC */
bogdanm	82:6473597d706e	94	kMcgFreqRangeSelectVeryHigh1 /* Very High frequency range selected for the crystal OSC */
bogdanm	82:6473597d706e	95	} mcg_freq_range_select_t;
bogdanm	82:6473597d706e	96
bogdanm	82:6473597d706e	97	/! @brief MCG high gain oscillator select /
bogdanm	82:6473597d706e	98	typedef enum _mcg_hgo_select
bogdanm	82:6473597d706e	99	{
bogdanm	82:6473597d706e	100	kMcgHgoSelectLow, /* Configure crystal oscillator for low-power operation */
bogdanm	82:6473597d706e	101	kMcgHgoSelectHigh /* Configure crystal oscillator for high-gain operation */
bogdanm	82:6473597d706e	102	} mcg_hgo_select_t;
bogdanm	82:6473597d706e	103
bogdanm	82:6473597d706e	104	/! @brief MCG high gain oscillator select /
bogdanm	82:6473597d706e	105	typedef enum _mcg_eref_clock_select
bogdanm	82:6473597d706e	106	{
bogdanm	82:6473597d706e	107	kMcgErefClockSelectExt, /* External reference clock requested */
bogdanm	82:6473597d706e	108	kMcgErefClockSelectOsc /* Oscillator requested */
bogdanm	82:6473597d706e	109	} mcg_eref_clock_select_t;
bogdanm	82:6473597d706e	110
bogdanm	82:6473597d706e	111	/! @brief MCG low power select /
bogdanm	82:6473597d706e	112	typedef enum _mcg_lp_select
bogdanm	82:6473597d706e	113	{
bogdanm	82:6473597d706e	114	kMcgLpSelectNormal, /* FLL (or PLL) is not disabled in bypass modes */
bogdanm	82:6473597d706e	115	kMcgLpSelectLowPower /* FLL (or PLL) is disabled in bypass modes (lower power) */
bogdanm	82:6473597d706e	116	} mcg_lp_select_t;
bogdanm	82:6473597d706e	117
bogdanm	82:6473597d706e	118	/! @brief MCG internal reference clock select /
bogdanm	82:6473597d706e	119	typedef enum _mcg_iref_clock_select
bogdanm	82:6473597d706e	120	{
bogdanm	82:6473597d706e	121	kMcgIrefClockSelectSlow, /* Slow internal reference clock selected */
bogdanm	82:6473597d706e	122	kMcgIrefClockSelectFast /* Fast internal reference clock selected */
bogdanm	82:6473597d706e	123	} mcg_iref_clock_select_t;
bogdanm	82:6473597d706e	124
bogdanm	82:6473597d706e	125	/! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference /
bogdanm	82:6473597d706e	126	typedef enum _mcg_dmx32_select
bogdanm	82:6473597d706e	127	{
bogdanm	82:6473597d706e	128	kMcgDmx32Default, /* DCO has a default range of 25% */
bogdanm	82:6473597d706e	129	kMcgDmx32Fine /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
bogdanm	82:6473597d706e	130	} mcg_dmx32_select_t;
bogdanm	82:6473597d706e	131
bogdanm	82:6473597d706e	132	/! @brief MCG DCO range select /
bogdanm	82:6473597d706e	133	typedef enum _mcg_dco_range_select
bogdanm	82:6473597d706e	134	{
bogdanm	82:6473597d706e	135	kMcgDcoRangeSelectLow, /* Low frequency range */
bogdanm	82:6473597d706e	136	kMcgDcoRangeSelectMid, /* Mid frequency range*/
bogdanm	82:6473597d706e	137	kMcgDcoRangeSelectMidHigh, /* Mid-High frequency range */
bogdanm	82:6473597d706e	138	kMcgDcoRangeSelectHigh /* High frequency range */
bogdanm	82:6473597d706e	139	} mcg_dco_range_select_t;
bogdanm	82:6473597d706e	140
bogdanm	82:6473597d706e	141	/! @brief MCG PLL external reference clock select /
bogdanm	82:6473597d706e	142	typedef enum _mcg_pll_eref_clock_select
bogdanm	82:6473597d706e	143	{
bogdanm	82:6473597d706e	144	kMcgPllErefClockSelectOsc0, /* Selects OSC0 clock source as its external reference clock */
bogdanm	82:6473597d706e	145	kMcgPllErefClockSelectOsc1 /* Selects OSC1 clock source as its external reference clock */
bogdanm	82:6473597d706e	146	} mcg_pll_eref_clock_select_t;
bogdanm	82:6473597d706e	147
bogdanm	82:6473597d706e	148	/! @brief MCG PLL select /
bogdanm	82:6473597d706e	149	typedef enum _mcg_pll_select
bogdanm	82:6473597d706e	150	{
bogdanm	82:6473597d706e	151	kMcgPllSelectFll, /* FLL is selected */
bogdanm	82:6473597d706e	152	kMcgPllSelectPllcs /* PLLCS output clock is selected */
bogdanm	82:6473597d706e	153	} mcg_pll_select_t;
bogdanm	82:6473597d706e	154
bogdanm	82:6473597d706e	155	/! @brief MCG loss of lock status /
bogdanm	82:6473597d706e	156	typedef enum _mcg_lols_status
bogdanm	82:6473597d706e	157	{
bogdanm	82:6473597d706e	158	kMcgLolsNotLostLock, /* PLL has not lost lock since LOLS 0 was last cleared */
bogdanm	82:6473597d706e	159	kMcgLolsLostLock /* PLL has lost lock since LOLS 0 was last cleared */
bogdanm	82:6473597d706e	160	} mcg_lols_status_t;
bogdanm	82:6473597d706e	161
bogdanm	82:6473597d706e	162	/! @brief MCG lock status /
bogdanm	82:6473597d706e	163	typedef enum _mcg_lock_status
bogdanm	82:6473597d706e	164	{
bogdanm	82:6473597d706e	165	kMcgLockUnlocked, /* PLL is currently unlocked */
bogdanm	82:6473597d706e	166	kMcgLockLocked /* PLL is currently locked */
bogdanm	82:6473597d706e	167	} mcg_lock_status_t;
bogdanm	82:6473597d706e	168
bogdanm	82:6473597d706e	169	/! @brief MCG clock status /
bogdanm	82:6473597d706e	170	typedef enum _mcg_pllst_status
bogdanm	82:6473597d706e	171	{
bogdanm	82:6473597d706e	172	kMcgPllstFll, /* Source of PLLS clock is FLL clock */
bogdanm	82:6473597d706e	173	kMcgPllstPllcs /* Source of PLLS clock is PLLCS output clock */
bogdanm	82:6473597d706e	174	} mcg_pllst_status_t;
bogdanm	82:6473597d706e	175
bogdanm	82:6473597d706e	176	/! @brief MCG iref status /
bogdanm	82:6473597d706e	177	typedef enum _mcg_irefst_status
bogdanm	82:6473597d706e	178	{
bogdanm	82:6473597d706e	179	kMcgIrefstExt, /* FLL reference clock is the external reference clock */
bogdanm	82:6473597d706e	180	kMcgIrefstInt /* FLL reference clock is the internal reference clock */
bogdanm	82:6473597d706e	181	} mcg_irefst_status_t;
bogdanm	82:6473597d706e	182
bogdanm	82:6473597d706e	183	/! @brief MCG clock mode status /
bogdanm	82:6473597d706e	184	typedef enum _mcg_clkst_status
bogdanm	82:6473597d706e	185	{
bogdanm	82:6473597d706e	186	kMcgClkstFll, /* Output of the FLL is selected (reset default) */
bogdanm	82:6473597d706e	187	kMcgClkstIref, /* Internal reference clock is selected */
bogdanm	82:6473597d706e	188	kMcgClkstEref, /* External reference clock is selected */
bogdanm	82:6473597d706e	189	kMcgClkstPll /* Output of the PLL is selected */
bogdanm	82:6473597d706e	190	} mcg_clkst_status_t;
bogdanm	82:6473597d706e	191
bogdanm	82:6473597d706e	192	/! @brief MCG ircst status /
bogdanm	82:6473597d706e	193	typedef enum _mcg_ircst_status
bogdanm	82:6473597d706e	194	{
bogdanm	82:6473597d706e	195	kMcgIrcstSlow, /* internal reference clock is the slow clock (32 kHz IRC) */
bogdanm	82:6473597d706e	196	kMcgIrcstFast /* internal reference clock is the fast clock (2 MHz IRC) */
bogdanm	82:6473597d706e	197	} mcg_ircst_status_t;
bogdanm	82:6473597d706e	198
bogdanm	82:6473597d706e	199	/! @brief MCG auto trim fail status /
bogdanm	82:6473597d706e	200	typedef enum _mcg_atmf_status
bogdanm	82:6473597d706e	201	{
bogdanm	82:6473597d706e	202	kMcgAtmfNormal, /* Automatic Trim Machine completed normally */
bogdanm	82:6473597d706e	203	kMcgAtmfFail /* Automatic Trim Machine failed */
bogdanm	82:6473597d706e	204	} mcg_atmf_status_t;
bogdanm	82:6473597d706e	205
bogdanm	82:6473597d706e	206	/! @brief MCG loss of clock status /
bogdanm	82:6473597d706e	207	typedef enum _mcg_locs0_status
bogdanm	82:6473597d706e	208	{
bogdanm	82:6473597d706e	209	kMcgLocs0NotOccured, /* Loss of OSC0 has not occurred */
bogdanm	82:6473597d706e	210	kMcgLocs0Occured /* Loss of OSC0 has occurred */
bogdanm	82:6473597d706e	211	} mcg_locs0_status_t;
bogdanm	82:6473597d706e	212
bogdanm	82:6473597d706e	213	/! @brief MCG Automatic Trim Machine Select /
bogdanm	82:6473597d706e	214	typedef enum _mcg_atms_select
bogdanm	82:6473597d706e	215	{
bogdanm	82:6473597d706e	216	kMcgAtmsSelect32k, /* 32 kHz Internal Reference Clock selected */
bogdanm	82:6473597d706e	217	kMcgAtmsSelect4m /* 4 MHz Internal Reference Clock selected */
bogdanm	82:6473597d706e	218	} mcg_atms_select_t;
bogdanm	82:6473597d706e	219
bogdanm	82:6473597d706e	220	/! @brief MCG OSC Clock Select /
bogdanm	82:6473597d706e	221	typedef enum _mcg_oscsel_select
bogdanm	82:6473597d706e	222	{
bogdanm	82:6473597d706e	223	kMcgOscselOsc, /* Selects System Oscillator (OSCCLK) */
bogdanm	82:6473597d706e	224	kMcgOscselRtc, /* Selects 32 kHz RTC Oscillator */
bogdanm	82:6473597d706e	225	kMcgOscselIrc /* Selects 48 MkHz IRC Oscillator */
bogdanm	82:6473597d706e	226	} mcg_oscsel_select_t;
bogdanm	82:6473597d706e	227
bogdanm	82:6473597d706e	228	/! @brief MCG loss of clock status /
bogdanm	82:6473597d706e	229	typedef enum _mcg_locs1_status
bogdanm	82:6473597d706e	230	{
bogdanm	82:6473597d706e	231	kMcgLocs1NotOccured, /* Loss of RTC has not occurred */
bogdanm	82:6473597d706e	232	kMcgLocs1Occured /* Loss of RTC has occurred */
bogdanm	82:6473597d706e	233	} mcg_locs1_status_t;
bogdanm	82:6473597d706e	234
bogdanm	82:6473597d706e	235	/! @brief MCG PLLCS select /
bogdanm	82:6473597d706e	236	typedef enum _mcg_pllcs_select
bogdanm	82:6473597d706e	237	{
bogdanm	82:6473597d706e	238	kMcgPllcsSelectPll0, /* PLL0 output clock is selected */
bogdanm	82:6473597d706e	239	kMcgPllcsSelectPll1, /* PLL1 output clock is selected */
bogdanm	82:6473597d706e	240	} mcg_pllcs_select_t;
bogdanm	82:6473597d706e	241
bogdanm	82:6473597d706e	242	/! @brief MCG loss of clock status /
bogdanm	82:6473597d706e	243	typedef enum _mcg_locs2_status
bogdanm	82:6473597d706e	244	{
bogdanm	82:6473597d706e	245	kMcgLocs2NotOccured, /* Loss of OSC1 has not occurred */
bogdanm	82:6473597d706e	246	kMcgLocs2Occured /* Loss of OSC1 has occurred */
bogdanm	82:6473597d706e	247	} mcg_locs2_status_t;
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	/*******************************************************************************
bogdanm	82:6473597d706e	250	* API
bogdanm	82:6473597d706e	251	******************************************************************************/
bogdanm	82:6473597d706e	252
bogdanm	82:6473597d706e	253	#if defined(__cplusplus)
bogdanm	82:6473597d706e	254	extern "C" {
bogdanm	82:6473597d706e	255	#endif /* __cplusplus*/
bogdanm	82:6473597d706e	256
bogdanm	82:6473597d706e	257	/! @name MCG out clock access API/
bogdanm	82:6473597d706e	258	/@{/
bogdanm	82:6473597d706e	259
bogdanm	82:6473597d706e	260	/*!
bogdanm	82:6473597d706e	261	* @brief Gets the current MCG FLL clock.
bogdanm	82:6473597d706e	262	*
bogdanm	82:6473597d706e	263	* This function returns the mcgfllclk value in frequency(Hertz) based on the
bogdanm	82:6473597d706e	264	* current MCG configurations and settings. FLL should be properly configured
bogdanm	82:6473597d706e	265	* in order to get the valid value.
bogdanm	82:6473597d706e	266	*
bogdanm	82:6473597d706e	267	* @param none
bogdanm	82:6473597d706e	268	* @return value Frequency value in Hertz of the mcgpllclk.
bogdanm	82:6473597d706e	269	*/
bogdanm	82:6473597d706e	270	uint32_t clock_hal_get_fllclk(void);
bogdanm	82:6473597d706e	271
bogdanm	82:6473597d706e	272	/*!
bogdanm	82:6473597d706e	273	* @brief Gets the current MCG PLL/PLL0 clock.
bogdanm	82:6473597d706e	274	*
bogdanm	82:6473597d706e	275	* This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based
bogdanm	82:6473597d706e	276	* on the current MCG configurations and settings. PLL/PLL0 should be properly
bogdanm	82:6473597d706e	277	* configured in order to get the valid value.
bogdanm	82:6473597d706e	278	*
bogdanm	82:6473597d706e	279	* @param none
bogdanm	82:6473597d706e	280	* @return value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.
bogdanm	82:6473597d706e	281	*/
bogdanm	82:6473597d706e	282	uint32_t clock_hal_get_pll0clk(void);
bogdanm	82:6473597d706e	283
bogdanm	82:6473597d706e	284	#if FSL_FEATURE_MCG_HAS_PLL1
bogdanm	82:6473597d706e	285	/*!
bogdanm	82:6473597d706e	286	* @brief Gets the current MCG PLL1 clock.
bogdanm	82:6473597d706e	287	*
bogdanm	82:6473597d706e	288	* This function returns the mcgpll1clk value in frequency (Hertz) based
bogdanm	82:6473597d706e	289	* on the current MCG configurations and settings. PLL1 should be properly configured
bogdanm	82:6473597d706e	290	* in order to get the valid value.
bogdanm	82:6473597d706e	291	*
bogdanm	82:6473597d706e	292	* @param none
bogdanm	82:6473597d706e	293	* @return value Frequency value in Hertz of mcgpll1clk.
bogdanm	82:6473597d706e	294	*/
bogdanm	82:6473597d706e	295	uint32_t clock_hal_get_pll1clk(void);
bogdanm	82:6473597d706e	296	#endif
bogdanm	82:6473597d706e	297
bogdanm	82:6473597d706e	298	/*!
bogdanm	82:6473597d706e	299	* @brief Gets the current MCG IR clock.
bogdanm	82:6473597d706e	300	*
bogdanm	82:6473597d706e	301	* This function returns the mcgirclk value in frequency (Hertz) based
bogdanm	82:6473597d706e	302	* on the current MCG configurations and settings. It does not check if the
bogdanm	82:6473597d706e	303	* mcgirclk is enabled or not, just calculate and return the value.
bogdanm	82:6473597d706e	304	*
bogdanm	82:6473597d706e	305	* @param none
bogdanm	82:6473597d706e	306	* @return value Frequency value in Hertz of the mcgirclk.
bogdanm	82:6473597d706e	307	*/
bogdanm	82:6473597d706e	308	uint32_t clock_hal_get_irclk(void);
bogdanm	82:6473597d706e	309
bogdanm	82:6473597d706e	310	/*!
bogdanm	82:6473597d706e	311	* @brief Gets the current MCG out clock.
bogdanm	82:6473597d706e	312	*
bogdanm	82:6473597d706e	313	* This function returns the mcgoutclk value in frequency (Hertz) based on the
bogdanm	82:6473597d706e	314	* current MCG configurations and settings. The configuration should be
bogdanm	82:6473597d706e	315	* properly done in order to get the valid value.
bogdanm	82:6473597d706e	316	*
bogdanm	82:6473597d706e	317	* @param none
bogdanm	82:6473597d706e	318	* @return value Frequency value in Hertz of mcgoutclk.
bogdanm	82:6473597d706e	319	*/
bogdanm	82:6473597d706e	320	uint32_t clock_hal_get_outclk(void);
bogdanm	82:6473597d706e	321
bogdanm	82:6473597d706e	322	/@}/
bogdanm	82:6473597d706e	323
bogdanm	82:6473597d706e	324	/! @name MCG control register access API/
bogdanm	82:6473597d706e	325	/@{/
bogdanm	82:6473597d706e	326
bogdanm	82:6473597d706e	327	/*!
bogdanm	82:6473597d706e	328	* @brief Sets the Clock Source Select
bogdanm	82:6473597d706e	329	*
bogdanm	82:6473597d706e	330	* This function selects the clock source for the MCGOUTCLK.
bogdanm	82:6473597d706e	331	*
bogdanm	82:6473597d706e	332	* @param select Clock source selection
bogdanm	82:6473597d706e	333	* - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
bogdanm	82:6473597d706e	334	* - 01: Internal reference clock is selected.
bogdanm	82:6473597d706e	335	* - 10: External reference clock is selected.
bogdanm	82:6473597d706e	336	* - 11: Reserved.
bogdanm	82:6473597d706e	337	*/
bogdanm	82:6473597d706e	338	static inline void clock_set_clks(mcg_clock_select_t select)
bogdanm	82:6473597d706e	339	{
bogdanm	82:6473597d706e	340	BW_MCG_C1_CLKS(select);
bogdanm	82:6473597d706e	341	}
bogdanm	82:6473597d706e	342
bogdanm	82:6473597d706e	343	/*!
bogdanm	82:6473597d706e	344	* @brief Gets the Clock Source Select.
bogdanm	82:6473597d706e	345	*
bogdanm	82:6473597d706e	346	* This function gets the select of the clock source for the MCGOUTCLK.
bogdanm	82:6473597d706e	347	*
bogdanm	82:6473597d706e	348	* @return select Clock source selection
bogdanm	82:6473597d706e	349	*/
bogdanm	82:6473597d706e	350	static inline mcg_clock_select_t clock_get_clks(void)
bogdanm	82:6473597d706e	351	{
bogdanm	82:6473597d706e	352	return (mcg_clock_select_t)BR_MCG_C1_CLKS;
bogdanm	82:6473597d706e	353	}
bogdanm	82:6473597d706e	354
bogdanm	82:6473597d706e	355	/*!
bogdanm	82:6473597d706e	356	* @brief Sets the FLL External Reference Divider.
bogdanm	82:6473597d706e	357	*
bogdanm	82:6473597d706e	358	* This function sets the FLL External Reference Divider.
bogdanm	82:6473597d706e	359	*
bogdanm	82:6473597d706e	360	* @param setting Divider setting
bogdanm	82:6473597d706e	361	*/
bogdanm	82:6473597d706e	362	static inline void clock_set_frdiv(uint8_t setting)
bogdanm	82:6473597d706e	363	{
bogdanm	82:6473597d706e	364	BW_MCG_C1_FRDIV(setting);
bogdanm	82:6473597d706e	365	}
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	/*!
bogdanm	82:6473597d706e	368	* @brief Gets the FLL External Reference Divider.
bogdanm	82:6473597d706e	369	*
bogdanm	82:6473597d706e	370	* This function gets the FLL External Reference Divider.
bogdanm	82:6473597d706e	371	*
bogdanm	82:6473597d706e	372	* @return setting Divider setting
bogdanm	82:6473597d706e	373	*/
bogdanm	82:6473597d706e	374	static inline uint8_t clock_get_frdiv(void)
bogdanm	82:6473597d706e	375	{
bogdanm	82:6473597d706e	376	return BR_MCG_C1_FRDIV;
bogdanm	82:6473597d706e	377	}
bogdanm	82:6473597d706e	378
bogdanm	82:6473597d706e	379	/*!
bogdanm	82:6473597d706e	380	* @brief Sets the Internal Reference Select.
bogdanm	82:6473597d706e	381	*
bogdanm	82:6473597d706e	382	* This function selects the reference clock source for the FLL.
bogdanm	82:6473597d706e	383	*
bogdanm	82:6473597d706e	384	* @param select Clock source select
bogdanm	82:6473597d706e	385	* - 0: External reference clock is selected
bogdanm	82:6473597d706e	386	* - 1: The slow internal reference clock is selected
bogdanm	82:6473597d706e	387	*/
bogdanm	82:6473597d706e	388	static inline void clock_set_irefs(mcg_iref_clock_source_t select)
bogdanm	82:6473597d706e	389	{
bogdanm	82:6473597d706e	390	BW_MCG_C1_IREFS(select);
bogdanm	82:6473597d706e	391	}
bogdanm	82:6473597d706e	392
bogdanm	82:6473597d706e	393	/*!
bogdanm	82:6473597d706e	394	* @brief Gets the Internal Reference Select
bogdanm	82:6473597d706e	395	*
bogdanm	82:6473597d706e	396	* This function gets the reference clock source for the FLL.
bogdanm	82:6473597d706e	397	*
bogdanm	82:6473597d706e	398	* @return select Clock source select
bogdanm	82:6473597d706e	399	*/
bogdanm	82:6473597d706e	400	static inline mcg_iref_clock_source_t clock_get_irefs(void)
bogdanm	82:6473597d706e	401	{
bogdanm	82:6473597d706e	402	return (mcg_iref_clock_source_t)BR_MCG_C1_IREFS;
bogdanm	82:6473597d706e	403	}
bogdanm	82:6473597d706e	404
bogdanm	82:6473597d706e	405	/*!
bogdanm	82:6473597d706e	406	* @brief Sets the CLKS, FRDIV and IREFS at the same time.
bogdanm	82:6473597d706e	407	*
bogdanm	82:6473597d706e	408	* This function sets the CLKS, FRDIV, and IREFS settings at the same time
bogdanm	82:6473597d706e	409	* in order keep the integrity of the clock switching.
bogdanm	82:6473597d706e	410	*
bogdanm	82:6473597d706e	411	* @param clks Clock source select
bogdanm	82:6473597d706e	412	* @param frdiv FLL external reference divider select
bogdanm	82:6473597d706e	413	* @param irefs Internal reference select
bogdanm	82:6473597d706e	414	*/
bogdanm	82:6473597d706e	415	static inline void clock_set_clks_frdiv_irefs(mcg_clock_select_t clks,
bogdanm	82:6473597d706e	416	uint8_t frdiv,
bogdanm	82:6473597d706e	417	mcg_iref_clock_source_t irefs)
bogdanm	82:6473597d706e	418	{
bogdanm	82:6473597d706e	419	/* Set the required CLKS , FRDIV and IREFS values */
bogdanm	82:6473597d706e	420	HW_MCG_C1_WR((HW_MCG_C1_RD() & ~(BM_MCG_C1_CLKS \| BM_MCG_C1_FRDIV \| BM_MCG_C1_IREFS))
bogdanm	82:6473597d706e	421	\| (BF_MCG_C1_CLKS(clks) \| BF_MCG_C1_FRDIV(frdiv) \| BF_MCG_C1_IREFS(irefs)));
bogdanm	82:6473597d706e	422	}
bogdanm	82:6473597d706e	423
bogdanm	82:6473597d706e	424	/*!
bogdanm	82:6473597d706e	425	* @brief Sets the Enable Internal Reference Clock setting.
bogdanm	82:6473597d706e	426	*
bogdanm	82:6473597d706e	427	* This function enables/disables the internal reference clock to use as the MCGIRCLK.
bogdanm	82:6473597d706e	428	*
bogdanm	82:6473597d706e	429	* @params enable Enable or disable internal reference clock.
bogdanm	82:6473597d706e	430	* - true: MCGIRCLK active
bogdanm	82:6473597d706e	431	* - false: MCGIRCLK inactive
bogdanm	82:6473597d706e	432	*/
bogdanm	82:6473597d706e	433	static inline void clock_set_irclken(bool enable)
bogdanm	82:6473597d706e	434	{
bogdanm	82:6473597d706e	435	BW_MCG_C1_IRCLKEN(enable ? 1 : 0);
bogdanm	82:6473597d706e	436	}
bogdanm	82:6473597d706e	437
bogdanm	82:6473597d706e	438	/*!
bogdanm	82:6473597d706e	439	* @brief Gets the enable Internal Reference Clock setting.
bogdanm	82:6473597d706e	440	*
bogdanm	82:6473597d706e	441	* This function gets the reference clock enable setting.
bogdanm	82:6473597d706e	442	*
bogdanm	82:6473597d706e	443	* @return enabled True if the internal reference clock is enabled.
bogdanm	82:6473597d706e	444	*/
bogdanm	82:6473597d706e	445	static inline bool clock_get_irclken(void)
bogdanm	82:6473597d706e	446	{
bogdanm	82:6473597d706e	447	return BR_MCG_C1_IRCLKEN;
bogdanm	82:6473597d706e	448	}
bogdanm	82:6473597d706e	449
bogdanm	82:6473597d706e	450	/*!
bogdanm	82:6473597d706e	451	* @brief Sets the Internal Reference Clock Stop Enable setting.
bogdanm	82:6473597d706e	452	*
bogdanm	82:6473597d706e	453	* This function controls whether or not the internal reference clock remains
bogdanm	82:6473597d706e	454	* enabled when the MCG enters Stop mode.
bogdanm	82:6473597d706e	455	*
bogdanm	82:6473597d706e	456	* @params enable Enable or disable the internal reference clock stop setting.
bogdanm	82:6473597d706e	457	* - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set
bogdanm	82:6473597d706e	458	or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
bogdanm	82:6473597d706e	459	* - false: Internal reference clock is disabled in Stop mode
bogdanm	82:6473597d706e	460	*/
bogdanm	82:6473597d706e	461	static inline void clock_set_irefsten(bool enable)
bogdanm	82:6473597d706e	462	{
bogdanm	82:6473597d706e	463	BW_MCG_C1_IREFSTEN(enable ? 1 : 0);
bogdanm	82:6473597d706e	464	}
bogdanm	82:6473597d706e	465
bogdanm	82:6473597d706e	466	/*!
bogdanm	82:6473597d706e	467	* @brief Gets the Enable Internal Reference Clock setting.
bogdanm	82:6473597d706e	468	*
bogdanm	82:6473597d706e	469	* This function gets the Internal Reference Clock Stop Enable setting.
bogdanm	82:6473597d706e	470	*
bogdanm	82:6473597d706e	471	* @return enabled True if internal reference clock stop is enabled.
bogdanm	82:6473597d706e	472	*/
bogdanm	82:6473597d706e	473	static inline bool clock_get_irefsten(void)
bogdanm	82:6473597d706e	474	{
bogdanm	82:6473597d706e	475	return BR_MCG_C1_IREFSTEN;
bogdanm	82:6473597d706e	476	}
bogdanm	82:6473597d706e	477
bogdanm	82:6473597d706e	478	/*!
bogdanm	82:6473597d706e	479	* @brief Sets the Loss of Clock Reset Enable setting.
bogdanm	82:6473597d706e	480	*
bogdanm	82:6473597d706e	481	* This function determines whether an interrupt or a reset request is made following a loss
bogdanm	82:6473597d706e	482	* of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
bogdanm	82:6473597d706e	483	*
bogdanm	82:6473597d706e	484	* @params enable Loss of Clock Reset Enable setting
bogdanm	82:6473597d706e	485	* - true: Generate a reset request on a loss of OSC0 external reference clock
bogdanm	82:6473597d706e	486	* - false: Interrupt request is generated on a loss of OSC0 external reference clock
bogdanm	82:6473597d706e	487	*/
bogdanm	82:6473597d706e	488	static inline void clock_set_locre0(bool enable)
bogdanm	82:6473597d706e	489	{
bogdanm	82:6473597d706e	490	BW_MCG_C2_LOCRE0(enable ? 1 : 0);
bogdanm	82:6473597d706e	491	}
bogdanm	82:6473597d706e	492
bogdanm	82:6473597d706e	493	/*!
bogdanm	82:6473597d706e	494	* @brief Gets the Loss of Clock Reset Enable setting.
bogdanm	82:6473597d706e	495	*
bogdanm	82:6473597d706e	496	* This function gets the Loss of Clock Reset Enable setting.
bogdanm	82:6473597d706e	497	*
bogdanm	82:6473597d706e	498	* @return enabled True if Loss of Clock Reset is enabled.
bogdanm	82:6473597d706e	499	*/
bogdanm	82:6473597d706e	500	static inline bool clock_get_locre0(void)
bogdanm	82:6473597d706e	501	{
bogdanm	82:6473597d706e	502	return BR_MCG_C2_LOCRE0;
bogdanm	82:6473597d706e	503	}
bogdanm	82:6473597d706e	504
bogdanm	82:6473597d706e	505	#if FSL_FEATURE_MCG_HAS_FCFTRIM
bogdanm	82:6473597d706e	506	/*!
bogdanm	82:6473597d706e	507	* @brief Sets the Fast Internal Reference Clock Fine Trim setting.
bogdanm	82:6473597d706e	508	*
bogdanm	82:6473597d706e	509	* This function sets the Fast Internal Reference Clock Fine Trim setting. FCFTRIM
bogdanm	82:6473597d706e	510	* controls the smallest adjustment of the fast internal reference clock frequency.
bogdanm	82:6473597d706e	511	* Setting the FCFTRIM increases the period and clearing FCFTRIM decreases the period
bogdanm	82:6473597d706e	512	* by the smallest amount possible. If an FCFTRIM value is stored and non-volatile
bogdanm	82:6473597d706e	513	* memory is to be used, it is the user's responsibility to copy that value from the
bogdanm	82:6473597d706e	514	* non-volatile memory location to this bit.
bogdanm	82:6473597d706e	515	*
bogdanm	82:6473597d706e	516	* @params setting Fast Internal Reference Clock Fine Trim setting
bogdanm	82:6473597d706e	517	*/
bogdanm	82:6473597d706e	518	static inline void clock_set_fcftrim(uint8_t setting)
bogdanm	82:6473597d706e	519	{
bogdanm	82:6473597d706e	520	BW_MCG_C2_FCFTRIM(setting);
bogdanm	82:6473597d706e	521	}
bogdanm	82:6473597d706e	522
bogdanm	82:6473597d706e	523	/*!
bogdanm	82:6473597d706e	524	* @brief Gets the Fast Internal Reference Clock Fine Trim setting.
bogdanm	82:6473597d706e	525	*
bogdanm	82:6473597d706e	526	* This function gets the Fast Internal Reference Clock Fine Trim setting.
bogdanm	82:6473597d706e	527	*
bogdanm	82:6473597d706e	528	* @return setting Fast Internal Reference Clock Fine Trim setting
bogdanm	82:6473597d706e	529	*/
bogdanm	82:6473597d706e	530	static inline uint8_t clock_get_fcftrim(void)
bogdanm	82:6473597d706e	531	{
bogdanm	82:6473597d706e	532	return BR_MCG_C2_FCFTRIM;
bogdanm	82:6473597d706e	533	}
bogdanm	82:6473597d706e	534	#endif /* FSL_FEATURE_MCG_HAS_FCFTRIM */
bogdanm	82:6473597d706e	535
bogdanm	82:6473597d706e	536	/*!
bogdanm	82:6473597d706e	537	* @brief Sets the Frequency Range Select.
bogdanm	82:6473597d706e	538	*
bogdanm	82:6473597d706e	539	* This function selects the frequency range for the crystal oscillator or an external
bogdanm	82:6473597d706e	540	* clock source. See the Oscillator (OSC) chapter for more details and the device
bogdanm	82:6473597d706e	541	* data sheet for the frequency ranges used.
bogdanm	82:6473597d706e	542	*
bogdanm	82:6473597d706e	543	* @params select Frequency Range Select
bogdanm	82:6473597d706e	544	* - 00: Low frequency range selected for the crystal oscillator
bogdanm	82:6473597d706e	545	* - 01: High frequency range selected for the crystal oscillator
bogdanm	82:6473597d706e	546	* - 1X: Very high frequency range selected for the crystal oscillator
bogdanm	82:6473597d706e	547	*/
bogdanm	82:6473597d706e	548	static inline void clock_set_range0(mcg_freq_range_select_t select)
bogdanm	82:6473597d706e	549	{
bogdanm	82:6473597d706e	550	BW_MCG_C2_RANGE(select);
bogdanm	82:6473597d706e	551	}
bogdanm	82:6473597d706e	552
bogdanm	82:6473597d706e	553	/*!
bogdanm	82:6473597d706e	554	* @brief Gets the Frequency Range Select.
bogdanm	82:6473597d706e	555	*
bogdanm	82:6473597d706e	556	* This function gets the Frequency Range Select.
bogdanm	82:6473597d706e	557	*
bogdanm	82:6473597d706e	558	* @return select Frequency Range Select
bogdanm	82:6473597d706e	559	*/
bogdanm	82:6473597d706e	560	static inline mcg_freq_range_select_t clock_get_range0(void)
bogdanm	82:6473597d706e	561	{
bogdanm	82:6473597d706e	562	return (mcg_freq_range_select_t)BR_MCG_C2_RANGE;
bogdanm	82:6473597d706e	563	}
bogdanm	82:6473597d706e	564
bogdanm	82:6473597d706e	565	/*!
bogdanm	82:6473597d706e	566	* @brief Sets the High Gain Oscillator Select.
bogdanm	82:6473597d706e	567	*
bogdanm	82:6473597d706e	568	* This function controls the crystal oscillator mode of operation. See the
bogdanm	82:6473597d706e	569	* Oscillator (OSC) chapter for more details.
bogdanm	82:6473597d706e	570	*
bogdanm	82:6473597d706e	571	* @params select High Gain Oscillator Select.
bogdanm	82:6473597d706e	572	* - 0: Configure crystal oscillator for low-power operation
bogdanm	82:6473597d706e	573	* - 1: Configure crystal oscillator for high-gain operation
bogdanm	82:6473597d706e	574	*/
bogdanm	82:6473597d706e	575	static inline void clock_set_hgo0(mcg_hgo_select_t select)
bogdanm	82:6473597d706e	576	{
bogdanm	82:6473597d706e	577	BW_MCG_C2_HGO(select);
bogdanm	82:6473597d706e	578	}
bogdanm	82:6473597d706e	579
bogdanm	82:6473597d706e	580	/*!
bogdanm	82:6473597d706e	581	* @brief Gets the High Gain Oscillator Select.
bogdanm	82:6473597d706e	582	*
bogdanm	82:6473597d706e	583	* This function gets the High Gain Oscillator Select.
bogdanm	82:6473597d706e	584	*
bogdanm	82:6473597d706e	585	* @return select High Gain Oscillator Select
bogdanm	82:6473597d706e	586	*/
bogdanm	82:6473597d706e	587	static inline mcg_hgo_select_t clock_get_hgo0(void)
bogdanm	82:6473597d706e	588	{
bogdanm	82:6473597d706e	589	return (mcg_hgo_select_t)BR_MCG_C2_HGO;
bogdanm	82:6473597d706e	590	}
bogdanm	82:6473597d706e	591
bogdanm	82:6473597d706e	592	/*!
bogdanm	82:6473597d706e	593	* @brief Sets the External Reference Select.
bogdanm	82:6473597d706e	594	*
bogdanm	82:6473597d706e	595	* This function selects the source for the external reference clock.
bogdanm	82:6473597d706e	596	* See the Oscillator (OSC) chapter for more details.
bogdanm	82:6473597d706e	597	*
bogdanm	82:6473597d706e	598	* @params select External Reference Select
bogdanm	82:6473597d706e	599	* - 0: External reference clock requested
bogdanm	82:6473597d706e	600	* - 1: Oscillator requested
bogdanm	82:6473597d706e	601	*/
bogdanm	82:6473597d706e	602	static inline void clock_set_erefs0(mcg_eref_clock_select_t select)
bogdanm	82:6473597d706e	603	{
bogdanm	82:6473597d706e	604	BW_MCG_C2_EREFS(select);
bogdanm	82:6473597d706e	605	}
bogdanm	82:6473597d706e	606
bogdanm	82:6473597d706e	607	/*!
bogdanm	82:6473597d706e	608	* @brief Gets the External Reference Select.
bogdanm	82:6473597d706e	609	*
bogdanm	82:6473597d706e	610	* This function gets the External Reference Select.
bogdanm	82:6473597d706e	611	*
bogdanm	82:6473597d706e	612	* @return select External Reference Select
bogdanm	82:6473597d706e	613	*/
bogdanm	82:6473597d706e	614	static inline mcg_eref_clock_select_t clock_get_erefs0(void)
bogdanm	82:6473597d706e	615	{
bogdanm	82:6473597d706e	616	return (mcg_eref_clock_select_t)BR_MCG_C2_EREFS;
bogdanm	82:6473597d706e	617	}
bogdanm	82:6473597d706e	618
bogdanm	82:6473597d706e	619	/*!
bogdanm	82:6473597d706e	620	* @brief Sets the Low Power Select.
bogdanm	82:6473597d706e	621	*
bogdanm	82:6473597d706e	622	* This function controls whether the FLL (or PLL) is disabled in the BLPI and the
bogdanm	82:6473597d706e	623	* BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG
bogdanm	82:6473597d706e	624	* into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into
bogdanm	82:6473597d706e	625	* the BLPI mode. In any other MCG mode, the LP bit has no affect..
bogdanm	82:6473597d706e	626	*
bogdanm	82:6473597d706e	627	* @params select Low Power Select
bogdanm	82:6473597d706e	628	* - 0: FLL (or PLL) is not disabled in bypass modes
bogdanm	82:6473597d706e	629	* - 1: FLL (or PLL) is disabled in bypass modes (lower power)
bogdanm	82:6473597d706e	630	*/
bogdanm	82:6473597d706e	631	static inline void clock_set_lp(mcg_lp_select_t select)
bogdanm	82:6473597d706e	632	{
bogdanm	82:6473597d706e	633	BW_MCG_C2_LP(select);
bogdanm	82:6473597d706e	634	}
bogdanm	82:6473597d706e	635
bogdanm	82:6473597d706e	636	/*!
bogdanm	82:6473597d706e	637	* @brief Gets the Low Power Select.
bogdanm	82:6473597d706e	638	*
bogdanm	82:6473597d706e	639	* This function gets the Low Power Select.
bogdanm	82:6473597d706e	640	*
bogdanm	82:6473597d706e	641	* @return select Low Power Select
bogdanm	82:6473597d706e	642	*/
bogdanm	82:6473597d706e	643	static inline mcg_lp_select_t clock_get_lp(void)
bogdanm	82:6473597d706e	644	{
bogdanm	82:6473597d706e	645	return (mcg_lp_select_t)BR_MCG_C2_LP;
bogdanm	82:6473597d706e	646	}
bogdanm	82:6473597d706e	647
bogdanm	82:6473597d706e	648	/*!
bogdanm	82:6473597d706e	649	* @brief Sets the Internal Reference Clock Select.
bogdanm	82:6473597d706e	650	*
bogdanm	82:6473597d706e	651	* This function selects between the fast or slow internal reference clock source.
bogdanm	82:6473597d706e	652	*
bogdanm	82:6473597d706e	653	* @params select Low Power Select
bogdanm	82:6473597d706e	654	* - 0: Slow internal reference clock selected.
bogdanm	82:6473597d706e	655	* - 1: Fast internal reference clock selected.
bogdanm	82:6473597d706e	656	*/
bogdanm	82:6473597d706e	657	static inline void clock_set_ircs(mcg_iref_clock_select_t select)
bogdanm	82:6473597d706e	658	{
bogdanm	82:6473597d706e	659	BW_MCG_C2_IRCS(select);
bogdanm	82:6473597d706e	660	}
bogdanm	82:6473597d706e	661
bogdanm	82:6473597d706e	662	/*!
bogdanm	82:6473597d706e	663	* @brief Gets the Internal Reference Clock Select.
bogdanm	82:6473597d706e	664	*
bogdanm	82:6473597d706e	665	* This function gets the Internal Reference Clock Select.
bogdanm	82:6473597d706e	666	*
bogdanm	82:6473597d706e	667	* @return select Internal Reference Clock Select
bogdanm	82:6473597d706e	668	*/
bogdanm	82:6473597d706e	669	static inline mcg_iref_clock_select_t clock_get_ircs(void)
bogdanm	82:6473597d706e	670	{
bogdanm	82:6473597d706e	671	return (mcg_iref_clock_select_t)BR_MCG_C2_IRCS;
bogdanm	82:6473597d706e	672	}
bogdanm	82:6473597d706e	673
bogdanm	82:6473597d706e	674	/*!
bogdanm	82:6473597d706e	675	* @brief Sets the Slow Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	676	*
bogdanm	82:6473597d706e	677	* This function controls the slow internal reference clock frequency by
bogdanm	82:6473597d706e	678	* controlling the slow internal reference clock period. The SCTRIM bits are
bogdanm	82:6473597d706e	679	* binary weighted (that is, bit 1 adjusts twice as much as bit 0).
bogdanm	82:6473597d706e	680	* Increasing the binary value increases the period, and decreasing the value
bogdanm	82:6473597d706e	681	* decreases the period.
bogdanm	82:6473597d706e	682	* An additional fine trim bit is available in the C4 register as the SCFTRIM bit.
bogdanm	82:6473597d706e	683	* Upon reset, this value is loaded with a factory trim value.
bogdanm	82:6473597d706e	684	* If an SCTRIM value stored in non-volatile memory is to be used, it is the user's
bogdanm	82:6473597d706e	685	* responsibility to copy that value from the non-volatile memory location to
bogdanm	82:6473597d706e	686	* this register.
bogdanm	82:6473597d706e	687	*
bogdanm	82:6473597d706e	688	* @params setting Slow Internal Reference Clock Trim Setting
bogdanm	82:6473597d706e	689	*/
bogdanm	82:6473597d706e	690	static inline void clock_set_sctrim(uint8_t setting)
bogdanm	82:6473597d706e	691	{
bogdanm	82:6473597d706e	692	BW_MCG_C3_SCTRIM(setting);
bogdanm	82:6473597d706e	693	}
bogdanm	82:6473597d706e	694
bogdanm	82:6473597d706e	695	/*!
bogdanm	82:6473597d706e	696	* @brief Gets the Slow Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	697	*
bogdanm	82:6473597d706e	698	* This function gets the Slow Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	699	*
bogdanm	82:6473597d706e	700	* @return setting Slow Internal Reference Clock Trim Setting
bogdanm	82:6473597d706e	701	*/
bogdanm	82:6473597d706e	702	static inline uint8_t clock_get_sctrim(void)
bogdanm	82:6473597d706e	703	{
bogdanm	82:6473597d706e	704	return BR_MCG_C3_SCTRIM;
bogdanm	82:6473597d706e	705	}
bogdanm	82:6473597d706e	706
bogdanm	82:6473597d706e	707	/*!
bogdanm	82:6473597d706e	708	* @brief Sets the DCO Maximum Frequency with 32.768 kHz Reference.
bogdanm	82:6473597d706e	709	*
bogdanm	82:6473597d706e	710	* This function controls whether or not the DCO frequency range
bogdanm	82:6473597d706e	711	* is narrowed to its maximum frequency with a 32.768 kHz reference.
bogdanm	82:6473597d706e	712	*
bogdanm	82:6473597d706e	713	* @params setting DCO Maximum Frequency with 32.768 kHz Reference Setting
bogdanm	82:6473597d706e	714	* - 0: DCO has a default range of 25%.
bogdanm	82:6473597d706e	715	* - 1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
bogdanm	82:6473597d706e	716	*/
bogdanm	82:6473597d706e	717	static inline void clock_set_dmx32(mcg_dmx32_select_t setting)
bogdanm	82:6473597d706e	718	{
bogdanm	82:6473597d706e	719	BW_MCG_C4_DMX32(setting);
bogdanm	82:6473597d706e	720	}
bogdanm	82:6473597d706e	721
bogdanm	82:6473597d706e	722	/*!
bogdanm	82:6473597d706e	723	* @brief Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting.
bogdanm	82:6473597d706e	724	*
bogdanm	82:6473597d706e	725	* This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting.
bogdanm	82:6473597d706e	726	*
bogdanm	82:6473597d706e	727	* @return setting DCO Maximum Frequency with 32.768 kHz Reference Setting
bogdanm	82:6473597d706e	728	*/
bogdanm	82:6473597d706e	729	static inline mcg_dmx32_select_t clock_get_dmx32(void)
bogdanm	82:6473597d706e	730	{
bogdanm	82:6473597d706e	731	return (mcg_dmx32_select_t)BR_MCG_C4_DMX32;
bogdanm	82:6473597d706e	732	}
bogdanm	82:6473597d706e	733
bogdanm	82:6473597d706e	734	/*!
bogdanm	82:6473597d706e	735	* @brief Sets the DCO Range Select.
bogdanm	82:6473597d706e	736	*
bogdanm	82:6473597d706e	737	* This function selects the frequency range for the FLL output, DCOOUT.
bogdanm	82:6473597d706e	738	* When the LP bit is set, the writes to the DRS bits are ignored. The DRST read
bogdanm	82:6473597d706e	739	* field indicates the current frequency range for the DCOOUT. The DRST field does
bogdanm	82:6473597d706e	740	* not update immediately after a write to the DRS field due to internal
bogdanm	82:6473597d706e	741	* synchronization between the clock domains. See the DCO Frequency Range table
bogdanm	82:6473597d706e	742	* for more details.
bogdanm	82:6473597d706e	743	*
bogdanm	82:6473597d706e	744	* @params setting DCO Range Select Setting
bogdanm	82:6473597d706e	745	* - 00: Low range (reset default).
bogdanm	82:6473597d706e	746	* - 01: Mid range.
bogdanm	82:6473597d706e	747	* - 10: Mid-high range.
bogdanm	82:6473597d706e	748	* - 11: High range.
bogdanm	82:6473597d706e	749	*/
bogdanm	82:6473597d706e	750	static inline void clock_set_drst_drs(mcg_dco_range_select_t setting)
bogdanm	82:6473597d706e	751	{
bogdanm	82:6473597d706e	752	BW_MCG_C4_DRST_DRS(setting);
bogdanm	82:6473597d706e	753	}
bogdanm	82:6473597d706e	754
bogdanm	82:6473597d706e	755	/*!
bogdanm	82:6473597d706e	756	* @brief Gets the DCO Range Select Setting.
bogdanm	82:6473597d706e	757	*
bogdanm	82:6473597d706e	758	* This function gets the DCO Range Select Setting.
bogdanm	82:6473597d706e	759	*
bogdanm	82:6473597d706e	760	* @return setting DCO Range Select Setting
bogdanm	82:6473597d706e	761	*/
bogdanm	82:6473597d706e	762	static inline mcg_dco_range_select_t clock_get_drst_drs(void)
bogdanm	82:6473597d706e	763	{
bogdanm	82:6473597d706e	764	return (mcg_dco_range_select_t)BR_MCG_C4_DRST_DRS;
bogdanm	82:6473597d706e	765	}
bogdanm	82:6473597d706e	766
bogdanm	82:6473597d706e	767	/*!
bogdanm	82:6473597d706e	768	* @brief Sets the Fast Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	769	*
bogdanm	82:6473597d706e	770	* This function controls the fast internal reference clock frequency
bogdanm	82:6473597d706e	771	* by controlling the fast internal reference clock period. The FCTRIM
bogdanm	82:6473597d706e	772	* bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
bogdanm	82:6473597d706e	773	* Increasing the binary value increases the period, and decreasing the
bogdanm	82:6473597d706e	774	* value decreases the period.
bogdanm	82:6473597d706e	775	* If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is
bogdanm	82:6473597d706e	776	* the user's responsibility to copy that value from the non-volatile memory location
bogdanm	82:6473597d706e	777	* to this register.
bogdanm	82:6473597d706e	778	*
bogdanm	82:6473597d706e	779	* @params setting Fast Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	780	*/
bogdanm	82:6473597d706e	781	static inline void clock_set_fctrim(uint8_t setting)
bogdanm	82:6473597d706e	782	{
bogdanm	82:6473597d706e	783	BW_MCG_C4_FCTRIM(setting);
bogdanm	82:6473597d706e	784	}
bogdanm	82:6473597d706e	785
bogdanm	82:6473597d706e	786	/*!
bogdanm	82:6473597d706e	787	* @brief Gets the Fast Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	788	*
bogdanm	82:6473597d706e	789	* This function gets the Fast Internal Reference Clock Trim Setting.
bogdanm	82:6473597d706e	790	*
bogdanm	82:6473597d706e	791	* @return setting Fast Internal Reference Clock Trim Setting
bogdanm	82:6473597d706e	792	*/
bogdanm	82:6473597d706e	793	static inline uint8_t clock_get_fctrim(void)
bogdanm	82:6473597d706e	794	{
bogdanm	82:6473597d706e	795	return BR_MCG_C4_FCTRIM;
bogdanm	82:6473597d706e	796	}
bogdanm	82:6473597d706e	797
bogdanm	82:6473597d706e	798	/*!
bogdanm	82:6473597d706e	799	* @brief Sets the Slow Internal Reference Clock Fine Trim Setting.
bogdanm	82:6473597d706e	800	*
bogdanm	82:6473597d706e	801	* This function controls the smallest adjustment of the slow internal
bogdanm	82:6473597d706e	802	* reference clock frequency. Setting the SCFTRIM increases the period and
bogdanm	82:6473597d706e	803	* clearing the SCFTRIM decreases the period by the smallest amount possible.
bogdanm	82:6473597d706e	804	* If an SCFTRIM value, stored in non-volatile memory, is to be used, it is
bogdanm	82:6473597d706e	805	* the user's responsibility to copy that value from the non-volatile memory
bogdanm	82:6473597d706e	806	* location to this bit.
bogdanm	82:6473597d706e	807	*
bogdanm	82:6473597d706e	808	* @params setting Slow Internal Reference Clock Fine Trim Setting
bogdanm	82:6473597d706e	809	*/
bogdanm	82:6473597d706e	810	static inline void clock_set_scftrim(uint8_t setting)
bogdanm	82:6473597d706e	811	{
bogdanm	82:6473597d706e	812	BW_MCG_C4_SCFTRIM(setting);
bogdanm	82:6473597d706e	813	}
bogdanm	82:6473597d706e	814
bogdanm	82:6473597d706e	815	/*!
bogdanm	82:6473597d706e	816	* @brief Gets the Slow Internal Reference Clock Fine Trim Setting.
bogdanm	82:6473597d706e	817	*
bogdanm	82:6473597d706e	818	* This function gets the Slow Internal Reference Clock Fine Trim Setting.
bogdanm	82:6473597d706e	819	*
bogdanm	82:6473597d706e	820	* @return setting Slow Internal Reference Clock Fine Trim Setting
bogdanm	82:6473597d706e	821	*/
bogdanm	82:6473597d706e	822	static inline uint8_t clock_get_scftrim(void)
bogdanm	82:6473597d706e	823	{
bogdanm	82:6473597d706e	824	return BR_MCG_C4_SCFTRIM;
bogdanm	82:6473597d706e	825	}
bogdanm	82:6473597d706e	826
bogdanm	82:6473597d706e	827	#if FSL_FEATURE_MCG_USE_PLLREFSEL
bogdanm	82:6473597d706e	828	/*!
bogdanm	82:6473597d706e	829	* @brief Sets the PLL0 External Reference Select Setting.
bogdanm	82:6473597d706e	830	*
bogdanm	82:6473597d706e	831	* This function selects the PLL0 external reference clock source.
bogdanm	82:6473597d706e	832	*
bogdanm	82:6473597d706e	833	* @params setting PLL0 External Reference Select Setting
bogdanm	82:6473597d706e	834	* - 0: Selects OSC0 clock source as its external reference clock
bogdanm	82:6473597d706e	835	* - 1: Selects OSC1 clock source as its external reference clock
bogdanm	82:6473597d706e	836	*/
bogdanm	82:6473597d706e	837	static inline void clock_set_pllrefsel0(mcg_pll_eref_clock_select_t setting)
bogdanm	82:6473597d706e	838	{
bogdanm	82:6473597d706e	839	BW_MCG_C5_PLLREFSEL0(setting);
bogdanm	82:6473597d706e	840	}
bogdanm	82:6473597d706e	841
bogdanm	82:6473597d706e	842	/*!
bogdanm	82:6473597d706e	843	* @brief Gets the PLL0 External Reference Select Setting.
bogdanm	82:6473597d706e	844	*
bogdanm	82:6473597d706e	845	* This function gets the PLL0 External Reference Select Setting.
bogdanm	82:6473597d706e	846	*
bogdanm	82:6473597d706e	847	* @return setting PLL0 External Reference Select Setting
bogdanm	82:6473597d706e	848	*/
bogdanm	82:6473597d706e	849	static inline mcg_pll_eref_clock_select_t clock_get_pllrefsel0(void)
bogdanm	82:6473597d706e	850	{
bogdanm	82:6473597d706e	851	return (mcg_pll_eref_clock_select_t)BR_MCG_C5_PLLREFSEL0;
bogdanm	82:6473597d706e	852	}
bogdanm	82:6473597d706e	853	#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	/*!
bogdanm	82:6473597d706e	856	* @brief Sets the PLL Clock Enable Setting.
bogdanm	82:6473597d706e	857	*
bogdanm	82:6473597d706e	858	* This function enables/disables the PLL0 independent of the PLLS and enables the PLL0
bogdanm	82:6473597d706e	859	* clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to
bogdanm	82:6473597d706e	860	* the correct divider to generate a PLL1 reference clock in a valid reference range
bogdanm	82:6473597d706e	861	* prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external
bogdanm	82:6473597d706e	862	* oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being
bogdanm	82:6473597d706e	863	* enabled with the PLLCLKEN0 bit, and the external oscillator is being used
bogdanm	82:6473597d706e	864	* as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
bogdanm	82:6473597d706e	865	*
bogdanm	82:6473597d706e	866	* @params enable PLL Clock Enable Setting
bogdanm	82:6473597d706e	867	* - true: MCGPLL0CLK and MCGPLL0CLK2X are active
bogdanm	82:6473597d706e	868	* - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive
bogdanm	82:6473597d706e	869	*/
bogdanm	82:6473597d706e	870	static inline void clock_set_pllclken0(bool enable)
bogdanm	82:6473597d706e	871	{
bogdanm	82:6473597d706e	872	BW_MCG_C5_PLLCLKEN0(enable ? 1 : 0);
bogdanm	82:6473597d706e	873	}
bogdanm	82:6473597d706e	874
bogdanm	82:6473597d706e	875	/*!
bogdanm	82:6473597d706e	876	* @brief Gets the PLL Clock Enable Setting.
bogdanm	82:6473597d706e	877	*
bogdanm	82:6473597d706e	878	* This function gets the PLL Clock Enable Setting.
bogdanm	82:6473597d706e	879	*
bogdanm	82:6473597d706e	880	* @return enabled True if PLL0 PLL Clock is enabled.
bogdanm	82:6473597d706e	881	*/
bogdanm	82:6473597d706e	882	static inline bool clock_get_pllclken0(void)
bogdanm	82:6473597d706e	883	{
bogdanm	82:6473597d706e	884	return BR_MCG_C5_PLLCLKEN0;
bogdanm	82:6473597d706e	885	}
bogdanm	82:6473597d706e	886
bogdanm	82:6473597d706e	887	/*!
bogdanm	82:6473597d706e	888	* @brief Sets the PLL0 Stop Enable Setting.
bogdanm	82:6473597d706e	889	*
bogdanm	82:6473597d706e	890	* This function enables/disables the PLL0 Clock during a Normal Stop (In Low
bogdanm	82:6473597d706e	891	* Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other
bogdanm	82:6473597d706e	892	* power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock
bogdanm	82:6473597d706e	893	* to run if it is written to 1.
bogdanm	82:6473597d706e	894	*
bogdanm	82:6473597d706e	895	* @params enable PLL0 Stop Enable Setting
bogdanm	82:6473597d706e	896	* - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in
bogdanm	82:6473597d706e	897	* Normal Stop mode.
bogdanm	82:6473597d706e	898	* - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the
bogdanm	82:6473597d706e	899	* Stop modes.
bogdanm	82:6473597d706e	900	*/
bogdanm	82:6473597d706e	901	static inline void clock_set_pllsten0(bool enable)
bogdanm	82:6473597d706e	902	{
bogdanm	82:6473597d706e	903	BW_MCG_C5_PLLSTEN0(enable ? 1 : 0);
bogdanm	82:6473597d706e	904	}
bogdanm	82:6473597d706e	905
bogdanm	82:6473597d706e	906	/*!
bogdanm	82:6473597d706e	907	* @brief Gets the PLL0 Stop Enable Setting.
bogdanm	82:6473597d706e	908	*
bogdanm	82:6473597d706e	909	* This function gets the PLL0 Stop Enable Setting.
bogdanm	82:6473597d706e	910	*
bogdanm	82:6473597d706e	911	* @return enabled True if the PLL0 Stop is enabled.
bogdanm	82:6473597d706e	912	*/
bogdanm	82:6473597d706e	913	static inline bool clock_get_pllsten0(void)
bogdanm	82:6473597d706e	914	{
bogdanm	82:6473597d706e	915	return BR_MCG_C5_PLLSTEN0;
bogdanm	82:6473597d706e	916	}
bogdanm	82:6473597d706e	917
bogdanm	82:6473597d706e	918	/*!
bogdanm	82:6473597d706e	919	* @brief Sets the PLL0 External Reference Divider Setting.
bogdanm	82:6473597d706e	920	*
bogdanm	82:6473597d706e	921	* This function selects the amount to divide down the external reference
bogdanm	82:6473597d706e	922	* clock for the PLL0. The resulting frequency must be in a valid reference
bogdanm	82:6473597d706e	923	* range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the
bogdanm	82:6473597d706e	924	* PRDIV0 value must not be changed when LOCK0 is zero.
bogdanm	82:6473597d706e	925	*
bogdanm	82:6473597d706e	926	* @params setting PLL0 External Reference Divider Setting
bogdanm	82:6473597d706e	927	*/
bogdanm	82:6473597d706e	928	static inline void clock_set_prdiv0(uint8_t setting)
bogdanm	82:6473597d706e	929	{
bogdanm	82:6473597d706e	930	BW_MCG_C5_PRDIV0(setting);
bogdanm	82:6473597d706e	931	}
bogdanm	82:6473597d706e	932
bogdanm	82:6473597d706e	933	/*!
bogdanm	82:6473597d706e	934	* @brief Gets the PLL0 External Reference Divider Setting.
bogdanm	82:6473597d706e	935	*
bogdanm	82:6473597d706e	936	* This function gets the PLL0 External Reference Divider Setting.
bogdanm	82:6473597d706e	937	*
bogdanm	82:6473597d706e	938	* @return setting PLL0 External Reference Divider Setting
bogdanm	82:6473597d706e	939	*/
bogdanm	82:6473597d706e	940	static inline uint8_t clock_get_prdiv0(void)
bogdanm	82:6473597d706e	941	{
bogdanm	82:6473597d706e	942	return BR_MCG_C5_PRDIV0;
bogdanm	82:6473597d706e	943	}
bogdanm	82:6473597d706e	944
bogdanm	82:6473597d706e	945	/*!
bogdanm	82:6473597d706e	946	* @brief Sets the Loss of Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	947	*
bogdanm	82:6473597d706e	948	* This function determine whether an interrupt request is made following a loss
bogdanm	82:6473597d706e	949	* of lock indication. This bit only has an effect when LOLS 0 is set.
bogdanm	82:6473597d706e	950	*
bogdanm	82:6473597d706e	951	* @params enable Loss of Lock Interrupt Enable Setting
bogdanm	82:6473597d706e	952	* - true: Generate an interrupt request on loss of lock.
bogdanm	82:6473597d706e	953	* - false: No interrupt request is generated on loss of lock.
bogdanm	82:6473597d706e	954	*/
bogdanm	82:6473597d706e	955	static inline void clock_set_lolie0(bool enable)
bogdanm	82:6473597d706e	956	{
bogdanm	82:6473597d706e	957	BW_MCG_C6_LOLIE0(enable ? 1 : 0);
bogdanm	82:6473597d706e	958	}
bogdanm	82:6473597d706e	959
bogdanm	82:6473597d706e	960	/*!
bogdanm	82:6473597d706e	961	* @brief Gets the Loss of the Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	962	*
bogdanm	82:6473597d706e	963	* This function gets the Loss of the Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	964	*
bogdanm	82:6473597d706e	965	* @return enabled True if the Loss of Lock Interrupt is enabled.
bogdanm	82:6473597d706e	966	*/
bogdanm	82:6473597d706e	967	static inline bool clock_get_lolie0(void)
bogdanm	82:6473597d706e	968	{
bogdanm	82:6473597d706e	969	return BR_MCG_C6_LOLIE0;
bogdanm	82:6473597d706e	970	}
bogdanm	82:6473597d706e	971
bogdanm	82:6473597d706e	972	/*!
bogdanm	82:6473597d706e	973	* @brief Sets the PLL Select Setting.
bogdanm	82:6473597d706e	974	*
bogdanm	82:6473597d706e	975	* This function controls whether the PLLCS or FLL output is selected as the
bogdanm	82:6473597d706e	976	* MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and
bogdanm	82:6473597d706e	977	* PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the
bogdanm	82:6473597d706e	978	* PLLS is set, the FLL is disabled in all modes.
bogdanm	82:6473597d706e	979	*
bogdanm	82:6473597d706e	980	* @params setting PLL Select Setting
bogdanm	82:6473597d706e	981	* - 0: FLL is selected.
bogdanm	82:6473597d706e	982	* - 1: PLLCS output clock is selected (PRDIV0 bits of PLL in
bogdanm	82:6473597d706e	983	* control need to be programmed to the correct divider to
bogdanm	82:6473597d706e	984	* generate a PLL reference clock in the range of 1 - 32 MHz
bogdanm	82:6473597d706e	985	* prior to setting the PLLS bit).
bogdanm	82:6473597d706e	986	*/
bogdanm	82:6473597d706e	987	static inline void clock_set_plls(mcg_pll_select_t setting)
bogdanm	82:6473597d706e	988	{
bogdanm	82:6473597d706e	989	BW_MCG_C6_PLLS(setting);
bogdanm	82:6473597d706e	990	}
bogdanm	82:6473597d706e	991
bogdanm	82:6473597d706e	992	/*!
bogdanm	82:6473597d706e	993	* @brief Gets the PLL Select Setting.
bogdanm	82:6473597d706e	994	*
bogdanm	82:6473597d706e	995	* This function gets the PLL Select Setting.
bogdanm	82:6473597d706e	996	*
bogdanm	82:6473597d706e	997	* @return setting PLL Select Setting
bogdanm	82:6473597d706e	998	*/
bogdanm	82:6473597d706e	999	static inline mcg_pll_select_t clock_get_plls(void)
bogdanm	82:6473597d706e	1000	{
bogdanm	82:6473597d706e	1001	return (mcg_pll_select_t)BR_MCG_C6_PLLS;
bogdanm	82:6473597d706e	1002	}
bogdanm	82:6473597d706e	1003
bogdanm	82:6473597d706e	1004	/*!
bogdanm	82:6473597d706e	1005	* @brief Sets the Clock Monitor Enable Setting.
bogdanm	82:6473597d706e	1006	*
bogdanm	82:6473597d706e	1007	* This function enables/disables the loss of clock monitoring circuit for
bogdanm	82:6473597d706e	1008	* the OSC0 external reference mux select. The LOCRE0 bit determines whether an
bogdanm	82:6473597d706e	1009	* interrupt or a reset request is generated following a loss of the OSC0 indication.
bogdanm	82:6473597d706e	1010	* The CME0 bit should only be set to a logic 1 when the MCG is in an operational
bogdanm	82:6473597d706e	1011	* mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the
bogdanm	82:6473597d706e	1012	* CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register
bogdanm	82:6473597d706e	1013	* should not be changed. CME0 bit should be set to a logic 0 before the MCG
bogdanm	82:6473597d706e	1014	* enters any Stop mode. Otherwise, a reset request may occur while in Stop mode.
bogdanm	82:6473597d706e	1015	* CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes
bogdanm	82:6473597d706e	1016	* if the MCG is in BLPE mode.
bogdanm	82:6473597d706e	1017	*
bogdanm	82:6473597d706e	1018	* @params enable Clock Monitor Enable Setting
bogdanm	82:6473597d706e	1019	* - true: External clock monitor is enabled for OSC0.
bogdanm	82:6473597d706e	1020	* - false: External clock monitor is disabled for OSC0.
bogdanm	82:6473597d706e	1021	*/
bogdanm	82:6473597d706e	1022	static inline void clock_set_cme0(bool enable)
bogdanm	82:6473597d706e	1023	{
bogdanm	82:6473597d706e	1024	BW_MCG_C6_CME0(enable ? 1 : 0);
bogdanm	82:6473597d706e	1025	}
bogdanm	82:6473597d706e	1026
bogdanm	82:6473597d706e	1027	/*!
bogdanm	82:6473597d706e	1028	* @brief Gets the Clock Monitor Enable Setting.
bogdanm	82:6473597d706e	1029	*
bogdanm	82:6473597d706e	1030	* This function gets the Clock Monitor Enable Setting.
bogdanm	82:6473597d706e	1031	*
bogdanm	82:6473597d706e	1032	* @return enabled True if Clock Monitor is enabled
bogdanm	82:6473597d706e	1033	*/
bogdanm	82:6473597d706e	1034	static inline bool clock_get_cme0(void)
bogdanm	82:6473597d706e	1035	{
bogdanm	82:6473597d706e	1036	return BR_MCG_C6_CME0;
bogdanm	82:6473597d706e	1037	}
bogdanm	82:6473597d706e	1038
bogdanm	82:6473597d706e	1039	/*!
bogdanm	82:6473597d706e	1040	* @brief Sets the VCO0 Divider Setting.
bogdanm	82:6473597d706e	1041	*
bogdanm	82:6473597d706e	1042	* This function selects the amount to divide the VCO output of the PLL0.
bogdanm	82:6473597d706e	1043	* The VDIV0 bits establish the multiplication factor (M) applied to the
bogdanm	82:6473597d706e	1044	* reference clock frequency. After the PLL0 is enabled (by setting either
bogdanm	82:6473597d706e	1045	* PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero.
bogdanm	82:6473597d706e	1046	*
bogdanm	82:6473597d706e	1047	* @params setting VCO0 Divider Setting
bogdanm	82:6473597d706e	1048	*/
bogdanm	82:6473597d706e	1049	static inline void clock_set_vdiv0(uint8_t setting)
bogdanm	82:6473597d706e	1050	{
bogdanm	82:6473597d706e	1051	BW_MCG_C6_VDIV0(setting);
bogdanm	82:6473597d706e	1052	}
bogdanm	82:6473597d706e	1053
bogdanm	82:6473597d706e	1054	/*!
bogdanm	82:6473597d706e	1055	* @brief Gets the VCO0 Divider Setting.
bogdanm	82:6473597d706e	1056	*
bogdanm	82:6473597d706e	1057	* This function gets the VCO0 Divider Setting.
bogdanm	82:6473597d706e	1058	*
bogdanm	82:6473597d706e	1059	* @return setting VCO0 Divider Setting
bogdanm	82:6473597d706e	1060	*/
bogdanm	82:6473597d706e	1061	static inline uint8_t clock_get_vdiv0(void)
bogdanm	82:6473597d706e	1062	{
bogdanm	82:6473597d706e	1063	return BR_MCG_C6_VDIV0;
bogdanm	82:6473597d706e	1064	}
bogdanm	82:6473597d706e	1065
bogdanm	82:6473597d706e	1066	/*!
bogdanm	82:6473597d706e	1067	* @brief Gets the Loss of the Lock Status.
bogdanm	82:6473597d706e	1068	*
bogdanm	82:6473597d706e	1069	* This function gets the Loss of Lock Status. This bit is a sticky bit indicating
bogdanm	82:6473597d706e	1070	* the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL
bogdanm	82:6473597d706e	1071	* output frequency has fallen outside the lock exit frequency tolerance, D unl .
bogdanm	82:6473597d706e	1072	* LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set.
bogdanm	82:6473597d706e	1073	* This bit is cleared by reset or by writing a logic 1 to it when set. Writing a
bogdanm	82:6473597d706e	1074	* logic 0 to this bit has no effect.
bogdanm	82:6473597d706e	1075	*
bogdanm	82:6473597d706e	1076	* @return status Loss of Lock Status
bogdanm	82:6473597d706e	1077	* - 0: PLL has not lost lock since LOLS 0 was last cleared
bogdanm	82:6473597d706e	1078	* - 1: PLL has lost lock since LOLS 0 was last cleared
bogdanm	82:6473597d706e	1079	*/
bogdanm	82:6473597d706e	1080	static inline mcg_lols_status_t clock_get_lols0(void)
bogdanm	82:6473597d706e	1081	{
bogdanm	82:6473597d706e	1082	return (mcg_lols_status_t)BR_MCG_S_LOLS0;
bogdanm	82:6473597d706e	1083	}
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	/*!
bogdanm	82:6473597d706e	1086	* @brief Gets the Lock Status.
bogdanm	82:6473597d706e	1087	*
bogdanm	82:6473597d706e	1088	* This function gets the Lock Status. This bit indicates whether the PLL0 has
bogdanm	82:6473597d706e	1089	* acquired the lock. Lock detection is disabled when not operating in either the PBE or the
bogdanm	82:6473597d706e	1090	* PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode.
bogdanm	82:6473597d706e	1091	* While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and
bogdanm	82:6473597d706e	1092	* MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock
bogdanm	82:6473597d706e	1093	* status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register
bogdanm	82:6473597d706e	1094	* or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear
bogdanm	82:6473597d706e	1095	* and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference
bogdanm	82:6473597d706e	1096	* clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS,
bogdanm	82:6473597d706e	1097	* VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear
bogdanm	82:6473597d706e	1098	* and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock.
bogdanm	82:6473597d706e	1099	* Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and
bogdanm	82:6473597d706e	1100	* MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted.
bogdanm	82:6473597d706e	1101	*
bogdanm	82:6473597d706e	1102	* @return status Lock Status
bogdanm	82:6473597d706e	1103	* - 0: PLL is currently unlocked
bogdanm	82:6473597d706e	1104	* - 1: PLL is currently locked
bogdanm	82:6473597d706e	1105	*/
bogdanm	82:6473597d706e	1106	static inline mcg_lock_status_t clock_get_lock0(void)
bogdanm	82:6473597d706e	1107	{
bogdanm	82:6473597d706e	1108	return (mcg_lock_status_t)BR_MCG_S_LOCK0;
bogdanm	82:6473597d706e	1109	}
bogdanm	82:6473597d706e	1110
bogdanm	82:6473597d706e	1111	/*!
bogdanm	82:6473597d706e	1112	* @brief Gets the PLL Select Status.
bogdanm	82:6473597d706e	1113	*
bogdanm	82:6473597d706e	1114	* This function gets the PLL Select Status. This bit indicates the clock source
bogdanm	82:6473597d706e	1115	* selected by PLLS . The PLLST bit does not update immediately after a write to
bogdanm	82:6473597d706e	1116	* the PLLS bit due to the internal synchronization between the clock domains.
bogdanm	82:6473597d706e	1117	*
bogdanm	82:6473597d706e	1118	* @return status PLL Select Status
bogdanm	82:6473597d706e	1119	* - 0: Source of PLLS clock is FLL clock.
bogdanm	82:6473597d706e	1120	* - 1: Source of PLLS clock is PLLCS output clock.
bogdanm	82:6473597d706e	1121	*/
bogdanm	82:6473597d706e	1122	static inline mcg_pllst_status_t clock_get_pllst(void)
bogdanm	82:6473597d706e	1123	{
bogdanm	82:6473597d706e	1124	return (mcg_pllst_status_t)BR_MCG_S_PLLST;
bogdanm	82:6473597d706e	1125	}
bogdanm	82:6473597d706e	1126
bogdanm	82:6473597d706e	1127	/*!
bogdanm	82:6473597d706e	1128	* @brief Gets the Internal Reference Status.
bogdanm	82:6473597d706e	1129	*
bogdanm	82:6473597d706e	1130	* This function gets the Internal Reference Status. This bit indicates the current
bogdanm	82:6473597d706e	1131	* source for the FLL reference clock. The IREFST bit does not update immediately
bogdanm	82:6473597d706e	1132	* after a write to the IREFS bit due to internal synchronization between the clock
bogdanm	82:6473597d706e	1133	* domains.
bogdanm	82:6473597d706e	1134	*
bogdanm	82:6473597d706e	1135	* @return status Internal Reference Status
bogdanm	82:6473597d706e	1136	* - 0: Source of FLL reference clock is the external reference clock.
bogdanm	82:6473597d706e	1137	* - 1: Source of FLL reference clock is the internal reference clock.
bogdanm	82:6473597d706e	1138	*/
bogdanm	82:6473597d706e	1139	static inline mcg_irefst_status_t clock_get_irefst(void)
bogdanm	82:6473597d706e	1140	{
bogdanm	82:6473597d706e	1141	return (mcg_irefst_status_t)BR_MCG_S_IREFST;
bogdanm	82:6473597d706e	1142	}
bogdanm	82:6473597d706e	1143
bogdanm	82:6473597d706e	1144	/*!
bogdanm	82:6473597d706e	1145	* @brief Gets the Clock Mode Status.
bogdanm	82:6473597d706e	1146	*
bogdanm	82:6473597d706e	1147	* This function gets the Clock Mode Status. These bits indicate the current clock mode.
bogdanm	82:6473597d706e	1148	* The CLKST bits do not update immediately after a write to the CLKS bits due to
bogdanm	82:6473597d706e	1149	* internal synchronization between clock domains.
bogdanm	82:6473597d706e	1150	*
bogdanm	82:6473597d706e	1151	* @return status Clock Mode Status
bogdanm	82:6473597d706e	1152	* - 00: Output of the FLL is selected (reset default).
bogdanm	82:6473597d706e	1153	* - 01: Internal reference clock is selected.
bogdanm	82:6473597d706e	1154	* - 10: External reference clock is selected.
bogdanm	82:6473597d706e	1155	* - 11: Output of the PLL is selected.
bogdanm	82:6473597d706e	1156	*/
bogdanm	82:6473597d706e	1157	static inline mcg_clkst_status_t clock_get_clkst(void)
bogdanm	82:6473597d706e	1158	{
bogdanm	82:6473597d706e	1159	return (mcg_clkst_status_t)BR_MCG_S_CLKST;
bogdanm	82:6473597d706e	1160	}
bogdanm	82:6473597d706e	1161
bogdanm	82:6473597d706e	1162	/*!
bogdanm	82:6473597d706e	1163	* @brief Gets the OSC Initialization Status.
bogdanm	82:6473597d706e	1164	*
bogdanm	82:6473597d706e	1165	* This function gets the OSC Initialization Status. This bit, which resets to 0, is set
bogdanm	82:6473597d706e	1166	* to 1 after the initialization cycles of the crystal oscillator clock have completed.
bogdanm	82:6473597d706e	1167	* After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the
bogdanm	82:6473597d706e	1168	* OSC module's detailed description for more information.
bogdanm	82:6473597d706e	1169	*
bogdanm	82:6473597d706e	1170	* @return status OSC Initialization Status
bogdanm	82:6473597d706e	1171	*/
bogdanm	82:6473597d706e	1172	static inline uint8_t clock_get_oscinit0(void)
bogdanm	82:6473597d706e	1173	{
bogdanm	82:6473597d706e	1174	return BR_MCG_S_OSCINIT0;
bogdanm	82:6473597d706e	1175	}
bogdanm	82:6473597d706e	1176
bogdanm	82:6473597d706e	1177	/*!
bogdanm	82:6473597d706e	1178	* @brief Gets the Internal Reference Clock Status.
bogdanm	82:6473597d706e	1179	*
bogdanm	82:6473597d706e	1180	* This function gets the Internal Reference Clock Status. The IRCST bit indicates the
bogdanm	82:6473597d706e	1181	* current source for the internal reference clock select clock (IRCSCLK). The IRCST bit
bogdanm	82:6473597d706e	1182	* does not update immediately after a write to the IRCS bit due to the internal
bogdanm	82:6473597d706e	1183	* synchronization between clock domains. The IRCST bit is only updated if the
bogdanm	82:6473597d706e	1184	* internal reference clock is enabled, either by the MCG being in a mode that uses the
bogdanm	82:6473597d706e	1185	* IRC or by setting the C1[IRCLKEN] bit.
bogdanm	82:6473597d706e	1186	*
bogdanm	82:6473597d706e	1187	* @return status Internal Reference Clock Status
bogdanm	82:6473597d706e	1188	* - 0: Source of internal reference clock is the slow clock (32 kHz IRC).
bogdanm	82:6473597d706e	1189	* - 1: Source of internal reference clock is the fast clock (2 MHz IRC).
bogdanm	82:6473597d706e	1190	*/
bogdanm	82:6473597d706e	1191	static inline mcg_ircst_status_t clock_get_ircst(void)
bogdanm	82:6473597d706e	1192	{
bogdanm	82:6473597d706e	1193	return (mcg_ircst_status_t)BR_MCG_S_IRCST;
bogdanm	82:6473597d706e	1194	}
bogdanm	82:6473597d706e	1195
bogdanm	82:6473597d706e	1196	/*!
bogdanm	82:6473597d706e	1197	* @brief Gets the Automatic Trim machine Fail Flag.
bogdanm	82:6473597d706e	1198	*
bogdanm	82:6473597d706e	1199	* This function gets the Automatic Trim machine Fail Flag. This Fail flag for the
bogdanm	82:6473597d706e	1200	* Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is
bogdanm	82:6473597d706e	1201	* enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG
bogdanm	82:6473597d706e	1202	* enters into any Stop mode. A write to ATMF clears the flag.
bogdanm	82:6473597d706e	1203	*
bogdanm	82:6473597d706e	1204	* @return flag Automatic Trim machine Fail Flag
bogdanm	82:6473597d706e	1205	* - 0: Automatic Trim Machine completed normally.
bogdanm	82:6473597d706e	1206	* - 1: Automatic Trim Machine failed.
bogdanm	82:6473597d706e	1207	*/
bogdanm	82:6473597d706e	1208	static inline mcg_atmf_status_t clock_get_atmf(void)
bogdanm	82:6473597d706e	1209	{
bogdanm	82:6473597d706e	1210	return (mcg_atmf_status_t)BR_MCG_SC_ATMF;
bogdanm	82:6473597d706e	1211	}
bogdanm	82:6473597d706e	1212
bogdanm	82:6473597d706e	1213	/*!
bogdanm	82:6473597d706e	1214	* @brief Sets the Automatic Trim machine Fail Flag.
bogdanm	82:6473597d706e	1215	*
bogdanm	82:6473597d706e	1216	* This function clears the ATMF flag.
bogdanm	82:6473597d706e	1217	*/
bogdanm	82:6473597d706e	1218	static inline void clock_set_atmf(void)
bogdanm	82:6473597d706e	1219	{
bogdanm	82:6473597d706e	1220	BW_MCG_SC_ATMF(1);
bogdanm	82:6473597d706e	1221	}
bogdanm	82:6473597d706e	1222
bogdanm	82:6473597d706e	1223	/*!
bogdanm	82:6473597d706e	1224	* @brief Gets the OSC0 Loss of Clock Status.
bogdanm	82:6473597d706e	1225	*
bogdanm	82:6473597d706e	1226	* This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of
bogdanm	82:6473597d706e	1227	* OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set.
bogdanm	82:6473597d706e	1228	* This bit is cleared by writing a logic 1 to it when set.
bogdanm	82:6473597d706e	1229	*
bogdanm	82:6473597d706e	1230	* @return status OSC0 Loss of Clock Status
bogdanm	82:6473597d706e	1231	* - 0: Loss of OSC0 has not occurred.
bogdanm	82:6473597d706e	1232	* - 1: Loss of OSC0 has occurred.
bogdanm	82:6473597d706e	1233	*/
bogdanm	82:6473597d706e	1234	static inline mcg_locs0_status_t clock_get_locs0(void)
bogdanm	82:6473597d706e	1235	{
bogdanm	82:6473597d706e	1236	return (mcg_locs0_status_t)BR_MCG_SC_LOCS0;
bogdanm	82:6473597d706e	1237	}
bogdanm	82:6473597d706e	1238
bogdanm	82:6473597d706e	1239	/*!
bogdanm	82:6473597d706e	1240	* @brief Sets the Automatic Trim Machine Enable Setting.
bogdanm	82:6473597d706e	1241	*
bogdanm	82:6473597d706e	1242	* This function enables/disables the Auto Trim Machine to start automatically
bogdanm	82:6473597d706e	1243	* trimming the selected Internal Reference Clock.
bogdanm	82:6473597d706e	1244	* ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits
bogdanm	82:6473597d706e	1245	* of the IRCS clock selected by the ATMS bit.
bogdanm	82:6473597d706e	1246	* Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto
bogdanm	82:6473597d706e	1247	* trim operation and clears this bit.
bogdanm	82:6473597d706e	1248	*
bogdanm	82:6473597d706e	1249	* @params enable Automatic Trim Machine Enable Setting
bogdanm	82:6473597d706e	1250	* - true: Auto Trim Machine enabled
bogdanm	82:6473597d706e	1251	* - false: Auto Trim Machine disabled
bogdanm	82:6473597d706e	1252	*/
bogdanm	82:6473597d706e	1253	static inline void clock_set_atme(bool enable)
bogdanm	82:6473597d706e	1254	{
bogdanm	82:6473597d706e	1255	BW_MCG_SC_ATME(enable ? 1 : 0);
bogdanm	82:6473597d706e	1256	}
bogdanm	82:6473597d706e	1257
bogdanm	82:6473597d706e	1258	/*!
bogdanm	82:6473597d706e	1259	* @brief Gets the Automatic Trim Machine Enable Setting.
bogdanm	82:6473597d706e	1260	*
bogdanm	82:6473597d706e	1261	* This function gets the Automatic Trim Machine Enable Setting.
bogdanm	82:6473597d706e	1262	*
bogdanm	82:6473597d706e	1263	* @return enabled True if Automatic Trim Machine is enabled
bogdanm	82:6473597d706e	1264	*/
bogdanm	82:6473597d706e	1265	static inline bool clock_get_atme(void)
bogdanm	82:6473597d706e	1266	{
bogdanm	82:6473597d706e	1267	return BR_MCG_SC_ATME;
bogdanm	82:6473597d706e	1268	}
bogdanm	82:6473597d706e	1269
bogdanm	82:6473597d706e	1270	/*!
bogdanm	82:6473597d706e	1271	* @brief Sets the Automatic Trim Machine Select Setting.
bogdanm	82:6473597d706e	1272	*
bogdanm	82:6473597d706e	1273	* This function selects the IRCS clock for Auto Trim Test.
bogdanm	82:6473597d706e	1274	*
bogdanm	82:6473597d706e	1275	* @params setting Automatic Trim Machine Select Setting
bogdanm	82:6473597d706e	1276	* - 0: 32 kHz Internal Reference Clock selected
bogdanm	82:6473597d706e	1277	* - 1: 4 MHz Internal Reference Clock selected
bogdanm	82:6473597d706e	1278	*/
bogdanm	82:6473597d706e	1279	static inline void clock_set_atms(mcg_atms_select_t setting)
bogdanm	82:6473597d706e	1280	{
bogdanm	82:6473597d706e	1281	BW_MCG_SC_ATMS(setting);
bogdanm	82:6473597d706e	1282	}
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	/*!
bogdanm	82:6473597d706e	1285	* @brief Gets the Automatic Trim Machine Select Setting.
bogdanm	82:6473597d706e	1286	*
bogdanm	82:6473597d706e	1287	* This function gets the Automatic Trim Machine Select Setting.
bogdanm	82:6473597d706e	1288	*
bogdanm	82:6473597d706e	1289	* @return setting Automatic Trim Machine Select Setting
bogdanm	82:6473597d706e	1290	*/
bogdanm	82:6473597d706e	1291	static inline mcg_atms_select_t clock_get_atms(void)
bogdanm	82:6473597d706e	1292	{
bogdanm	82:6473597d706e	1293	return (mcg_atms_select_t)BR_MCG_SC_ATMS;
bogdanm	82:6473597d706e	1294	}
bogdanm	82:6473597d706e	1295
bogdanm	82:6473597d706e	1296	/*!
bogdanm	82:6473597d706e	1297	* @brief Sets the FLL Filter Preserve Enable Setting.
bogdanm	82:6473597d706e	1298	*
bogdanm	82:6473597d706e	1299	* This function sets the FLL Filter Preserve Enable. This bit prevents the
bogdanm	82:6473597d706e	1300	* FLL filter values from resetting allowing the FLL output frequency to remain the
bogdanm	82:6473597d706e	1301	* same during the clock mode changes where the FLL/DCO output is still valid.
bogdanm	82:6473597d706e	1302	* (Note: This requires that the FLL reference frequency remain the same as
bogdanm	82:6473597d706e	1303	* the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency
bogdanm	82:6473597d706e	1304	* values change.)
bogdanm	82:6473597d706e	1305	*
bogdanm	82:6473597d706e	1306	* @params enable FLL Filter Preserve Enable Setting
bogdanm	82:6473597d706e	1307	* - true: FLL filter and FLL frequency retain their previous values
bogdanm	82:6473597d706e	1308	* during new clock mode change
bogdanm	82:6473597d706e	1309	* - false: FLL filter and FLL frequency will reset on changes to correct
bogdanm	82:6473597d706e	1310	* clock mode
bogdanm	82:6473597d706e	1311	*/
bogdanm	82:6473597d706e	1312	static inline void clock_set_fltprsrv(bool enable)
bogdanm	82:6473597d706e	1313	{
bogdanm	82:6473597d706e	1314	BW_MCG_SC_FLTPRSRV(enable ? 1 : 0);
bogdanm	82:6473597d706e	1315	}
bogdanm	82:6473597d706e	1316
bogdanm	82:6473597d706e	1317	/*!
bogdanm	82:6473597d706e	1318	* @brief Gets the FLL Filter Preserve Enable Setting.
bogdanm	82:6473597d706e	1319	*
bogdanm	82:6473597d706e	1320	* This function gets the FLL Filter Preserve Enable Setting.
bogdanm	82:6473597d706e	1321	*
bogdanm	82:6473597d706e	1322	* @return enabled True if FLL Filter Preserve is enabled.
bogdanm	82:6473597d706e	1323	*/
bogdanm	82:6473597d706e	1324	static inline bool clock_get_fltprsrv(void)
bogdanm	82:6473597d706e	1325	{
bogdanm	82:6473597d706e	1326	return BR_MCG_SC_FLTPRSRV;
bogdanm	82:6473597d706e	1327	}
bogdanm	82:6473597d706e	1328
bogdanm	82:6473597d706e	1329	/*!
bogdanm	82:6473597d706e	1330	* @brief Sets the Fast Clock Internal Reference Divider Setting.
bogdanm	82:6473597d706e	1331	*
bogdanm	82:6473597d706e	1332	* This function selects the amount to divide down the fast internal reference
bogdanm	82:6473597d706e	1333	* clock. The resulting frequency is in the range 31.25 kHz to 4 MHz.
bogdanm	82:6473597d706e	1334	* (Note: Changing the divider when the Fast IRC is enabled is not supported).
bogdanm	82:6473597d706e	1335	*
bogdanm	82:6473597d706e	1336	* @params setting Fast Clock Internal Reference Divider Setting
bogdanm	82:6473597d706e	1337	*/
bogdanm	82:6473597d706e	1338	static inline void clock_set_fcrdiv(uint8_t setting)
bogdanm	82:6473597d706e	1339	{
bogdanm	82:6473597d706e	1340	BW_MCG_SC_FCRDIV(setting);
bogdanm	82:6473597d706e	1341	}
bogdanm	82:6473597d706e	1342
bogdanm	82:6473597d706e	1343	/*!
bogdanm	82:6473597d706e	1344	* @brief Gets the Fast Clock Internal Reference Divider Setting.
bogdanm	82:6473597d706e	1345	*
bogdanm	82:6473597d706e	1346	* This function gets the Fast Clock Internal Reference Divider Setting.
bogdanm	82:6473597d706e	1347	*
bogdanm	82:6473597d706e	1348	* @return setting Fast Clock Internal Reference Divider Setting
bogdanm	82:6473597d706e	1349	*/
bogdanm	82:6473597d706e	1350	static inline uint8_t clock_get_fcrdiv(void)
bogdanm	82:6473597d706e	1351	{
bogdanm	82:6473597d706e	1352	return BR_MCG_SC_FCRDIV;
bogdanm	82:6473597d706e	1353	}
bogdanm	82:6473597d706e	1354
bogdanm	82:6473597d706e	1355	/*!
bogdanm	82:6473597d706e	1356	* @brief Sets the ATM Compare Value High Setting.
bogdanm	82:6473597d706e	1357	*
bogdanm	82:6473597d706e	1358	* This function sets the ATM compare value high setting. The values are used by the
bogdanm	82:6473597d706e	1359	* Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM
bogdanm	82:6473597d706e	1360	* SAR conversion.
bogdanm	82:6473597d706e	1361	*
bogdanm	82:6473597d706e	1362	* @params setting ATM Compare Value High Setting
bogdanm	82:6473597d706e	1363	*/
bogdanm	82:6473597d706e	1364	static inline void clock_set_atcvh(uint8_t setting)
bogdanm	82:6473597d706e	1365	{
bogdanm	82:6473597d706e	1366	BW_MCG_ATCVH_ATCVH(setting);
bogdanm	82:6473597d706e	1367	}
bogdanm	82:6473597d706e	1368
bogdanm	82:6473597d706e	1369	/*!
bogdanm	82:6473597d706e	1370	* @brief Gets the ATM Compare Value High Setting.
bogdanm	82:6473597d706e	1371	*
bogdanm	82:6473597d706e	1372	* This function gets the ATM Compare Value High Setting.
bogdanm	82:6473597d706e	1373	*
bogdanm	82:6473597d706e	1374	* @return setting ATM Compare Value High Setting
bogdanm	82:6473597d706e	1375	*/
bogdanm	82:6473597d706e	1376	static inline uint8_t clock_get_atcvh(void)
bogdanm	82:6473597d706e	1377	{
bogdanm	82:6473597d706e	1378	return BR_MCG_ATCVH_ATCVH;
bogdanm	82:6473597d706e	1379	}
bogdanm	82:6473597d706e	1380
bogdanm	82:6473597d706e	1381	/*!
bogdanm	82:6473597d706e	1382	* @brief Sets the ATM Compare Value Low Setting.
bogdanm	82:6473597d706e	1383	*
bogdanm	82:6473597d706e	1384	* This function sets the ATM compare value low setting. The values are used by the
bogdanm	82:6473597d706e	1385	* Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM
bogdanm	82:6473597d706e	1386	* SAR conversion.
bogdanm	82:6473597d706e	1387	*
bogdanm	82:6473597d706e	1388	* @params setting ATM Compare Value Low Setting
bogdanm	82:6473597d706e	1389	*/
bogdanm	82:6473597d706e	1390	static inline void clock_set_atcvl(uint8_t setting)
bogdanm	82:6473597d706e	1391	{
bogdanm	82:6473597d706e	1392	BW_MCG_ATCVL_ATCVL(setting);
bogdanm	82:6473597d706e	1393	}
bogdanm	82:6473597d706e	1394
bogdanm	82:6473597d706e	1395	/*!
bogdanm	82:6473597d706e	1396	* @brief Gets the ATM Compare Value Low Setting.
bogdanm	82:6473597d706e	1397	*
bogdanm	82:6473597d706e	1398	* This function gets the ATM Compare Value Low Setting.
bogdanm	82:6473597d706e	1399	*
bogdanm	82:6473597d706e	1400	* @return setting ATM Compare Value Low Setting
bogdanm	82:6473597d706e	1401	*/
bogdanm	82:6473597d706e	1402	static inline uint8_t clock_get_atcvl(void)
bogdanm	82:6473597d706e	1403	{
bogdanm	82:6473597d706e	1404	return BR_MCG_ATCVL_ATCVL;
bogdanm	82:6473597d706e	1405	}
bogdanm	82:6473597d706e	1406
bogdanm	82:6473597d706e	1407	#if FSL_FEATURE_MCG_USE_OSCSEL
bogdanm	82:6473597d706e	1408	/*!
bogdanm	82:6473597d706e	1409	* @brief Sets the MCG OSC Clock Select Setting.
bogdanm	82:6473597d706e	1410	*
bogdanm	82:6473597d706e	1411	* This function selects the MCG FLL external reference clock.
bogdanm	82:6473597d706e	1412	*
bogdanm	82:6473597d706e	1413	* @params setting MCG OSC Clock Select Setting
bogdanm	82:6473597d706e	1414	* - 0: Selects System Oscillator (OSCCLK).
bogdanm	82:6473597d706e	1415	* - 1: Selects 32 kHz RTC Oscillator.
bogdanm	82:6473597d706e	1416	*/
bogdanm	82:6473597d706e	1417	static inline void clock_set_oscsel(mcg_oscsel_select_t setting)
bogdanm	82:6473597d706e	1418	{
bogdanm	82:6473597d706e	1419	BW_MCG_C7_OSCSEL(setting);
bogdanm	82:6473597d706e	1420	}
bogdanm	82:6473597d706e	1421
bogdanm	82:6473597d706e	1422	/*!
bogdanm	82:6473597d706e	1423	* @brief Gets the MCG OSC Clock Select Setting.
bogdanm	82:6473597d706e	1424	*
bogdanm	82:6473597d706e	1425	* This function gets the MCG OSC Clock Select Setting.
bogdanm	82:6473597d706e	1426	*
bogdanm	82:6473597d706e	1427	* @return setting MCG OSC Clock Select Setting
bogdanm	82:6473597d706e	1428	*/
bogdanm	82:6473597d706e	1429	static inline mcg_oscsel_select_t clock_get_oscsel(void)
bogdanm	82:6473597d706e	1430	{
bogdanm	82:6473597d706e	1431	return (mcg_oscsel_select_t)BR_MCG_C7_OSCSEL;
bogdanm	82:6473597d706e	1432	}
bogdanm	82:6473597d706e	1433	#endif /* FSL_FEATURE_MCG_USE_OSCSEL */
bogdanm	82:6473597d706e	1434
bogdanm	82:6473597d706e	1435	#if FSL_FEATURE_MCG_HAS_LOLRE
bogdanm	82:6473597d706e	1436	/*!
bogdanm	82:6473597d706e	1437	* @brief Sets the PLL Loss of Lock Reset Enable Setting.
bogdanm	82:6473597d706e	1438	*
bogdanm	82:6473597d706e	1439	* This function determines whether an interrupt or a reset request is made
bogdanm	82:6473597d706e	1440	* following a PLL loss of lock.
bogdanm	82:6473597d706e	1441	*
bogdanm	82:6473597d706e	1442	* @params enable PLL Loss of Lock Reset Enable Setting
bogdanm	82:6473597d706e	1443	* - true: Generate a reset request on a PLL loss of lock indication.
bogdanm	82:6473597d706e	1444	* - false: Interrupt request is generated on a PLL loss of lock
bogdanm	82:6473597d706e	1445	* indication. The PLL loss of lock interrupt enable bit
bogdanm	82:6473597d706e	1446	* must also be set to generate the interrupt request.
bogdanm	82:6473597d706e	1447	*/
bogdanm	82:6473597d706e	1448	static inline void clock_set_lolre(bool enable)
bogdanm	82:6473597d706e	1449	{
bogdanm	82:6473597d706e	1450	BW_MCG_C8_LOLRE(enable ? 1 : 0);
bogdanm	82:6473597d706e	1451	}
bogdanm	82:6473597d706e	1452
bogdanm	82:6473597d706e	1453	/*!
bogdanm	82:6473597d706e	1454	* @brief Gets the PLL Loss of Lock Reset Enable Setting.
bogdanm	82:6473597d706e	1455	*
bogdanm	82:6473597d706e	1456	* This function gets the PLL Loss of Lock Reset Enable Setting.
bogdanm	82:6473597d706e	1457	*
bogdanm	82:6473597d706e	1458	* @return enabled True if the PLL Loss of Lock Reset is enabled.
bogdanm	82:6473597d706e	1459	*/
bogdanm	82:6473597d706e	1460	static inline bool clock_get_lolre(void)
bogdanm	82:6473597d706e	1461	{
bogdanm	82:6473597d706e	1462	return BR_MCG_C8_LOLRE;
bogdanm	82:6473597d706e	1463	}
bogdanm	82:6473597d706e	1464	#endif /* FSL_FEATURE_MCG_HAS_LOLRE */
bogdanm	82:6473597d706e	1465
bogdanm	82:6473597d706e	1466
bogdanm	82:6473597d706e	1467	#if FSL_FEATURE_MCG_HAS_RTC_32K
bogdanm	82:6473597d706e	1468	/*!
bogdanm	82:6473597d706e	1469	* @brief Sets the Loss of Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1470	*
bogdanm	82:6473597d706e	1471	* This function determines whether an interrupt or a reset request is made following
bogdanm	82:6473597d706e	1472	* a loss of the RTC external reference clock. The LOCRE1 only has an affect when CME1
bogdanm	82:6473597d706e	1473	* is set.
bogdanm	82:6473597d706e	1474	*
bogdanm	82:6473597d706e	1475	* @params enable Loss of Clock Reset Enable Setting
bogdanm	82:6473597d706e	1476	* - true: Generate a reset request on a loss of RTC external reference clock.
bogdanm	82:6473597d706e	1477	* - false: Interrupt request is generated on a loss of RTC external
bogdanm	82:6473597d706e	1478	* reference clock.
bogdanm	82:6473597d706e	1479	*/
bogdanm	82:6473597d706e	1480	static inline void clock_set_locre1(bool enable)
bogdanm	82:6473597d706e	1481	{
bogdanm	82:6473597d706e	1482	BW_MCG_C8_LOCRE1(enable ? 1 : 0);
bogdanm	82:6473597d706e	1483	}
bogdanm	82:6473597d706e	1484
bogdanm	82:6473597d706e	1485	/*!
bogdanm	82:6473597d706e	1486	* @brief Gets the Loss of Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1487	*
bogdanm	82:6473597d706e	1488	* This function gets the Loss of Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1489	*
bogdanm	82:6473597d706e	1490	* @return enabled True if Loss of Clock Reset is enabled.
bogdanm	82:6473597d706e	1491	*/
bogdanm	82:6473597d706e	1492	static inline bool clock_get_locre1(void)
bogdanm	82:6473597d706e	1493	{
bogdanm	82:6473597d706e	1494	return BR_MCG_C8_LOCRE1;
bogdanm	82:6473597d706e	1495	}
bogdanm	82:6473597d706e	1496
bogdanm	82:6473597d706e	1497	/*!
bogdanm	82:6473597d706e	1498	* @brief Sets the Clock Monitor Enable1 Setting.
bogdanm	82:6473597d706e	1499	*
bogdanm	82:6473597d706e	1500	* This function enables/disables the loss of the clock monitoring circuit for the
bogdanm	82:6473597d706e	1501	* output of the RTC external reference clock. The LOCRE1 bit determines whether an
bogdanm	82:6473597d706e	1502	* interrupt or a reset request is generated following a loss of the RTC clock indication.
bogdanm	82:6473597d706e	1503	* The CME1 bit should only be set to a logic 1 when the MCG is in an operational mode
bogdanm	82:6473597d706e	1504	* that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). CME1 bit must be set to
bogdanm	82:6473597d706e	1505	* a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur
bogdanm	82:6473597d706e	1506	* while in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or
bogdanm	82:6473597d706e	1507	* VLPW power modes if the MCG is in BLPE mode.
bogdanm	82:6473597d706e	1508	*
bogdanm	82:6473597d706e	1509	* @params enable Clock Monitor Enable1 Setting
bogdanm	82:6473597d706e	1510	* - true: External clock monitor is enabled for RTC clock.
bogdanm	82:6473597d706e	1511	* - false: External clock monitor is disabled for RTC clock.
bogdanm	82:6473597d706e	1512	*/
bogdanm	82:6473597d706e	1513	static inline void clock_set_cme1(bool enable)
bogdanm	82:6473597d706e	1514	{
bogdanm	82:6473597d706e	1515	BW_MCG_C8_CME1(enable ? 1 : 0);
bogdanm	82:6473597d706e	1516	}
bogdanm	82:6473597d706e	1517
bogdanm	82:6473597d706e	1518	/*!
bogdanm	82:6473597d706e	1519	* @brief Gets the Clock Monitor Enable1 Setting.
bogdanm	82:6473597d706e	1520	*
bogdanm	82:6473597d706e	1521	* This function gets the Clock Monitor Enable1 Setting.
bogdanm	82:6473597d706e	1522	*
bogdanm	82:6473597d706e	1523	* @return enabled True if Clock Monitor Enable1 is enabled
bogdanm	82:6473597d706e	1524	*/
bogdanm	82:6473597d706e	1525	static inline bool clock_get_cme1(void)
bogdanm	82:6473597d706e	1526	{
bogdanm	82:6473597d706e	1527	return BR_MCG_C8_CME1;
bogdanm	82:6473597d706e	1528	}
bogdanm	82:6473597d706e	1529
bogdanm	82:6473597d706e	1530	/*!
bogdanm	82:6473597d706e	1531	* @brief Gets the RTC Loss of Clock Status.
bogdanm	82:6473597d706e	1532	*
bogdanm	82:6473597d706e	1533	* This function gets the RTC Loss of Clock Status. This bit indicates when a loss
bogdanm	82:6473597d706e	1534	* of clock has occurred. This bit is cleared by writing a logic 1 to it when set.
bogdanm	82:6473597d706e	1535	*
bogdanm	82:6473597d706e	1536	* @return status RTC Loss of Clock Status
bogdanm	82:6473597d706e	1537	* - 0: Loss of RTC has not occurred
bogdanm	82:6473597d706e	1538	* - 1: Loss of RTC has occurred
bogdanm	82:6473597d706e	1539	*/
bogdanm	82:6473597d706e	1540	static inline mcg_locs1_status_t clock_get_locs1(void)
bogdanm	82:6473597d706e	1541	{
bogdanm	82:6473597d706e	1542	return (mcg_locs1_status_t)BR_MCG_C8_LOCS1;
bogdanm	82:6473597d706e	1543	}
bogdanm	82:6473597d706e	1544	#endif /* FSL_FEATURE_MCG_HAS_RTC_32K */
bogdanm	82:6473597d706e	1545
bogdanm	82:6473597d706e	1546	#if FSL_FEATURE_MCG_USE_PLLREFSEL
bogdanm	82:6473597d706e	1547	/*!
bogdanm	82:6473597d706e	1548	* @brief Sets the OSC1 Loss of Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1549	*
bogdanm	82:6473597d706e	1550	* This function determines whether an interrupt or reset request is made following
bogdanm	82:6473597d706e	1551	* a loss of OSC1 external reference clock. The LOCRE2 only has an affect when
bogdanm	82:6473597d706e	1552	* LOCS2 is set.
bogdanm	82:6473597d706e	1553	*
bogdanm	82:6473597d706e	1554	* @params enable OSC1 Loss of Clock Reset Enable Setting
bogdanm	82:6473597d706e	1555	* - true: Reset request is generated on a loss of OSC1 external
bogdanm	82:6473597d706e	1556	* reference clock..
bogdanm	82:6473597d706e	1557	* - false: Interrupt request is generated on a loss of OSC1 external
bogdanm	82:6473597d706e	1558	* reference clock.
bogdanm	82:6473597d706e	1559	*/
bogdanm	82:6473597d706e	1560	static inline void clock_set_locre2(bool enable)
bogdanm	82:6473597d706e	1561	{
bogdanm	82:6473597d706e	1562	BW_MCG_C10_LOCRE2(enable ? 1 : 0);
bogdanm	82:6473597d706e	1563	}
bogdanm	82:6473597d706e	1564
bogdanm	82:6473597d706e	1565	/*!
bogdanm	82:6473597d706e	1566	* @brief Gets the OSC1 Loss of the Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1567	*
bogdanm	82:6473597d706e	1568	* This function gets the OSC1 Loss of Clock Reset Enable Setting.
bogdanm	82:6473597d706e	1569	*
bogdanm	82:6473597d706e	1570	* @return enabled True if OSC1 Loss of Clock Reset is enabled.
bogdanm	82:6473597d706e	1571	*/
bogdanm	82:6473597d706e	1572	static inline bool clock_get_locre2(void)
bogdanm	82:6473597d706e	1573	{
bogdanm	82:6473597d706e	1574	return BR_MCG_C10_LOCRE2;
bogdanm	82:6473597d706e	1575	}
bogdanm	82:6473597d706e	1576
bogdanm	82:6473597d706e	1577	/*!
bogdanm	82:6473597d706e	1578	* @brief Sets the Frequency Range1 Select Setting.
bogdanm	82:6473597d706e	1579	*
bogdanm	82:6473597d706e	1580	* This function selects the frequency range for the OSC1 crystal oscillator
bogdanm	82:6473597d706e	1581	* or an external clock source. See the Oscillator chapter for more details and
bogdanm	82:6473597d706e	1582	* the device data sheet for the frequency ranges used.
bogdanm	82:6473597d706e	1583	*
bogdanm	82:6473597d706e	1584	* @params setting Frequency Range1 Select Setting
bogdanm	82:6473597d706e	1585	* - 00: Low frequency range selected for the crystal oscillator.
bogdanm	82:6473597d706e	1586	* - 01: High frequency range selected for the crystal oscillator.
bogdanm	82:6473597d706e	1587	* - 1X: Very high frequency range selected for the crystal oscillator.
bogdanm	82:6473597d706e	1588	*/
bogdanm	82:6473597d706e	1589	static inline void clock_set_range1(mcg_freq_range_select_t setting)
bogdanm	82:6473597d706e	1590	{
bogdanm	82:6473597d706e	1591	BW_MCG_C10_RANGE1(setting);
bogdanm	82:6473597d706e	1592	}
bogdanm	82:6473597d706e	1593
bogdanm	82:6473597d706e	1594	/*!
bogdanm	82:6473597d706e	1595	* @brief Gets the Frequency Range1 Select Setting.
bogdanm	82:6473597d706e	1596	*
bogdanm	82:6473597d706e	1597	* This function gets the Frequency Range1 Select Setting.
bogdanm	82:6473597d706e	1598	*
bogdanm	82:6473597d706e	1599	* @return setting Frequency Range1 Select Setting
bogdanm	82:6473597d706e	1600	*/
bogdanm	82:6473597d706e	1601	static inline mcg_freq_range_select_t clock_get_range1(void)
bogdanm	82:6473597d706e	1602	{
bogdanm	82:6473597d706e	1603	return (mcg_freq_range_select_t)BR_MCG_C10_RANGE1;
bogdanm	82:6473597d706e	1604	}
bogdanm	82:6473597d706e	1605
bogdanm	82:6473597d706e	1606	/*!
bogdanm	82:6473597d706e	1607	* @brief Sets the High Gain Oscillator1 Select Setting.
bogdanm	82:6473597d706e	1608	*
bogdanm	82:6473597d706e	1609	* This function controls the OSC1 crystal oscillator mode of operation.
bogdanm	82:6473597d706e	1610	* See the Oscillator chapter for more details.
bogdanm	82:6473597d706e	1611	*
bogdanm	82:6473597d706e	1612	* @params setting High Gain Oscillator1 Select Setting
bogdanm	82:6473597d706e	1613	* - 0: Configure crystal oscillator for low-power operation.
bogdanm	82:6473597d706e	1614	* - 1: Configure crystal oscillator for high-gain operation.
bogdanm	82:6473597d706e	1615	*/
bogdanm	82:6473597d706e	1616	static inline void clock_set_hgo1(mcg_hgo_select_t setting)
bogdanm	82:6473597d706e	1617	{
bogdanm	82:6473597d706e	1618	BW_MCG_C10_HGO1(setting);
bogdanm	82:6473597d706e	1619	}
bogdanm	82:6473597d706e	1620
bogdanm	82:6473597d706e	1621	/*!
bogdanm	82:6473597d706e	1622	* @brief Gets the High Gain Oscillator1 Select Setting.
bogdanm	82:6473597d706e	1623	*
bogdanm	82:6473597d706e	1624	* This function gets the High Gain Oscillator1 Select Setting.
bogdanm	82:6473597d706e	1625	*
bogdanm	82:6473597d706e	1626	* @return setting High Gain Oscillator1 Select Setting
bogdanm	82:6473597d706e	1627	*/
bogdanm	82:6473597d706e	1628	static inline mcg_hgo_select_t clock_get_hgo1(void)
bogdanm	82:6473597d706e	1629	{
bogdanm	82:6473597d706e	1630	return (mcg_hgo_select_t)BR_MCG_C10_HGO1;
bogdanm	82:6473597d706e	1631	}
bogdanm	82:6473597d706e	1632
bogdanm	82:6473597d706e	1633	/*!
bogdanm	82:6473597d706e	1634	* @brief Sets the External Reference Select Setting.
bogdanm	82:6473597d706e	1635	*
bogdanm	82:6473597d706e	1636	* This function selects the source for the OSC1 external reference clock.
bogdanm	82:6473597d706e	1637	* See the Oscillator chapter for more details.
bogdanm	82:6473597d706e	1638	*
bogdanm	82:6473597d706e	1639	* @params setting External Reference Select Setting
bogdanm	82:6473597d706e	1640	* - 0: External reference clock requested.
bogdanm	82:6473597d706e	1641	* - 1: Oscillator requested.
bogdanm	82:6473597d706e	1642	*/
bogdanm	82:6473597d706e	1643	static inline void clock_set_erefs1(mcg_eref_clock_select_t setting)
bogdanm	82:6473597d706e	1644	{
bogdanm	82:6473597d706e	1645	BW_MCG_C10_EREFS1(setting);
bogdanm	82:6473597d706e	1646	}
bogdanm	82:6473597d706e	1647
bogdanm	82:6473597d706e	1648	/*!
bogdanm	82:6473597d706e	1649	* @brief Gets the External Reference Select Setting.
bogdanm	82:6473597d706e	1650	*
bogdanm	82:6473597d706e	1651	* This function gets the External Reference Select Setting.
bogdanm	82:6473597d706e	1652	*
bogdanm	82:6473597d706e	1653	* @return setting External Reference Select Setting
bogdanm	82:6473597d706e	1654	*/
bogdanm	82:6473597d706e	1655	static inline mcg_eref_clock_select_t clock_get_erefs1(void)
bogdanm	82:6473597d706e	1656	{
bogdanm	82:6473597d706e	1657	return (mcg_eref_clock_select_t)BR_MCG_C10_EREFS1;
bogdanm	82:6473597d706e	1658	}
bogdanm	82:6473597d706e	1659
bogdanm	82:6473597d706e	1660	/*!
bogdanm	82:6473597d706e	1661	* @brief Sets the PLL1 External Reference Select Setting.
bogdanm	82:6473597d706e	1662	*
bogdanm	82:6473597d706e	1663	* This function selects the PLL1 external reference clock source.
bogdanm	82:6473597d706e	1664	*
bogdanm	82:6473597d706e	1665	* @params setting PLL1 External Reference Select Setting
bogdanm	82:6473597d706e	1666	* - 0: Selects OSC0 clock source as its external reference clock.
bogdanm	82:6473597d706e	1667	* - 1: Selects OSC1 clock source as its external reference clock.
bogdanm	82:6473597d706e	1668	*/
bogdanm	82:6473597d706e	1669	static inline void clock_set_pllrefsel1(mcg_pll_eref_clock_select_t setting)
bogdanm	82:6473597d706e	1670	{
bogdanm	82:6473597d706e	1671	BW_MCG_C11_PLLREFSEL1(setting);
bogdanm	82:6473597d706e	1672	}
bogdanm	82:6473597d706e	1673
bogdanm	82:6473597d706e	1674	/*!
bogdanm	82:6473597d706e	1675	* @brief Gets the PLL1 External Reference Select Setting.
bogdanm	82:6473597d706e	1676	*
bogdanm	82:6473597d706e	1677	* This function gets the PLL1 External Reference Select Setting.
bogdanm	82:6473597d706e	1678	*
bogdanm	82:6473597d706e	1679	* @return setting PLL1 External Reference Select Setting
bogdanm	82:6473597d706e	1680	*/
bogdanm	82:6473597d706e	1681	static inline mcg_pll_eref_clock_select_t clock_get_pllrefsel1(void)
bogdanm	82:6473597d706e	1682	{
bogdanm	82:6473597d706e	1683	return (mcg_pll_eref_clock_select_t)BR_MCG_C11_PLLREFSEL1;
bogdanm	82:6473597d706e	1684	}
bogdanm	82:6473597d706e	1685
bogdanm	82:6473597d706e	1686	/*!
bogdanm	82:6473597d706e	1687	* @brief Sets the PLL1 Clock Enable Setting.
bogdanm	82:6473597d706e	1688	*
bogdanm	82:6473597d706e	1689	* This function enables/disables the PLL1 independent of PLLS and enables the
bogdanm	82:6473597d706e	1690	* PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs
bogdanm	82:6473597d706e	1691	* to be programmed to the correct divider to generate a PLL1 reference clock in a
bogdanm	82:6473597d706e	1692	* valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1
bogdanm	82:6473597d706e	1693	* enables the PLL1 selected external oscillator if not already enabled.
bogdanm	82:6473597d706e	1694	* Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the
bogdanm	82:6473597d706e	1695	* external oscillator is used as the reference clock, the OSCINIT1 bit should
bogdanm	82:6473597d706e	1696	* be checked to make sure it is set.
bogdanm	82:6473597d706e	1697	*
bogdanm	82:6473597d706e	1698	* @params enable PLL1 Clock Enable Setting
bogdanm	82:6473597d706e	1699	* - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless
bogdanm	82:6473597d706e	1700	* MCG is in a bypass mode with LP=1 (BLPI or BLPE).
bogdanm	82:6473597d706e	1701	* - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive.
bogdanm	82:6473597d706e	1702	*/
bogdanm	82:6473597d706e	1703	static inline void clock_set_pllclken1(bool enable)
bogdanm	82:6473597d706e	1704	{
bogdanm	82:6473597d706e	1705	BW_MCG_C11_PLLCLKEN1(enable ? 1 : 0);
bogdanm	82:6473597d706e	1706	}
bogdanm	82:6473597d706e	1707
bogdanm	82:6473597d706e	1708	/*!
bogdanm	82:6473597d706e	1709	* @brief Gets the PLL1 Clock Enable Setting.
bogdanm	82:6473597d706e	1710	*
bogdanm	82:6473597d706e	1711	* This function gets the PLL1 Clock Enable Setting.
bogdanm	82:6473597d706e	1712	*
bogdanm	82:6473597d706e	1713	* @return enabled True if the PLL1 Clock is enabled.
bogdanm	82:6473597d706e	1714	*/
bogdanm	82:6473597d706e	1715	static inline bool clock_get_pllclken1(void)
bogdanm	82:6473597d706e	1716	{
bogdanm	82:6473597d706e	1717	return BR_MCG_C11_PLLCLKEN1;
bogdanm	82:6473597d706e	1718	}
bogdanm	82:6473597d706e	1719
bogdanm	82:6473597d706e	1720	/*!
bogdanm	82:6473597d706e	1721	* @brief Sets the PLL1 Stop Enable Setting.
bogdanm	82:6473597d706e	1722	*
bogdanm	82:6473597d706e	1723	* This function enables/disables the PLL1 Clock during the Normal Stop (In Low
bogdanm	82:6473597d706e	1724	* Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other
bogdanm	82:6473597d706e	1725	* power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to
bogdanm	82:6473597d706e	1726	* run if it is written to 1.
bogdanm	82:6473597d706e	1727	*
bogdanm	82:6473597d706e	1728	* @params enable PLL1 Stop Enable Setting
bogdanm	82:6473597d706e	1729	* - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and
bogdanm	82:6473597d706e	1730	* MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
bogdanm	82:6473597d706e	1731	* - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X)
bogdanm	82:6473597d706e	1732	* are disabled in any of the Stop modes.
bogdanm	82:6473597d706e	1733	*/
bogdanm	82:6473597d706e	1734	static inline void clock_set_pllsten1(bool enable)
bogdanm	82:6473597d706e	1735	{
bogdanm	82:6473597d706e	1736	BW_MCG_C11_PLLSTEN1(enable ? 1 : 0);
bogdanm	82:6473597d706e	1737	}
bogdanm	82:6473597d706e	1738
bogdanm	82:6473597d706e	1739	/*!
bogdanm	82:6473597d706e	1740	* @brief Gets the PLL1 Stop Enable Setting.
bogdanm	82:6473597d706e	1741	*
bogdanm	82:6473597d706e	1742	* This function gets the PLL1 Stop Enable Setting.
bogdanm	82:6473597d706e	1743	*
bogdanm	82:6473597d706e	1744	* @return enabled True if PLL1 Stop is enabled.
bogdanm	82:6473597d706e	1745	*/
bogdanm	82:6473597d706e	1746	static inline bool clock_get_pllsten1(void)
bogdanm	82:6473597d706e	1747	{
bogdanm	82:6473597d706e	1748	return BR_MCG_C11_PLLSTEN1;
bogdanm	82:6473597d706e	1749	}
bogdanm	82:6473597d706e	1750
bogdanm	82:6473597d706e	1751	/*!
bogdanm	82:6473597d706e	1752	* @brief Sets the PLL Clock Select Setting.
bogdanm	82:6473597d706e	1753	*
bogdanm	82:6473597d706e	1754	* This function controls whether the PLL0 or PLL1 output is selected as the
bogdanm	82:6473597d706e	1755	* MCG source when CLKS are programmed in PLL Engaged External (PEE) mode
bogdanm	82:6473597d706e	1756	* (CLKS[1:0]=00 and IREFS=0 and PLLS=1).
bogdanm	82:6473597d706e	1757	*
bogdanm	82:6473597d706e	1758	* @params setting PLL Clock Select Setting
bogdanm	82:6473597d706e	1759	* - 0: PLL0 output clock is selected.
bogdanm	82:6473597d706e	1760	* - 1: PLL1 output clock is selected.
bogdanm	82:6473597d706e	1761	*/
bogdanm	82:6473597d706e	1762	static inline void clock_set_pllcs(mcg_pllcs_select_t setting)
bogdanm	82:6473597d706e	1763	{
bogdanm	82:6473597d706e	1764	BW_MCG_C11_PLLCS(setting);
bogdanm	82:6473597d706e	1765	}
bogdanm	82:6473597d706e	1766
bogdanm	82:6473597d706e	1767	/*!
bogdanm	82:6473597d706e	1768	* @brief Gets the PLL Clock Select Setting.
bogdanm	82:6473597d706e	1769	*
bogdanm	82:6473597d706e	1770	* This function gets the PLL Clock Select Setting.
bogdanm	82:6473597d706e	1771	*
bogdanm	82:6473597d706e	1772	* @return setting PLL Clock Select Setting
bogdanm	82:6473597d706e	1773	*/
bogdanm	82:6473597d706e	1774	static inline mcg_pllcs_select_t clock_get_pllcs(void)
bogdanm	82:6473597d706e	1775	{
bogdanm	82:6473597d706e	1776	return (mcg_pllcs_select_t)BR_MCG_C11_PLLCS;
bogdanm	82:6473597d706e	1777	}
bogdanm	82:6473597d706e	1778
bogdanm	82:6473597d706e	1779	/*!
bogdanm	82:6473597d706e	1780	* @brief Sets the PLL1 External Reference Divider Setting.
bogdanm	82:6473597d706e	1781	*
bogdanm	82:6473597d706e	1782	* This function selects the amount to divide down the external reference
bogdanm	82:6473597d706e	1783	* clock selected by REFSEL2 for PLL1. The resulting frequency must be in a valid
bogdanm	82:6473597d706e	1784	* reference range. After the PLL1 is enabled (by setting either PLLCLKEN1 or PLLS),
bogdanm	82:6473597d706e	1785	* the PRDIV1 value must not be changed when LOCK1 is zero.
bogdanm	82:6473597d706e	1786	*
bogdanm	82:6473597d706e	1787	* @params setting PLL1 External Reference Divider Setting
bogdanm	82:6473597d706e	1788	*/
bogdanm	82:6473597d706e	1789	static inline void clock_set_prdiv1(uint8_t setting)
bogdanm	82:6473597d706e	1790	{
bogdanm	82:6473597d706e	1791	BW_MCG_C11_PRDIV1(setting);
bogdanm	82:6473597d706e	1792	}
bogdanm	82:6473597d706e	1793
bogdanm	82:6473597d706e	1794	/*!
bogdanm	82:6473597d706e	1795	* @brief Gets the PLL1 External Reference Divider Setting.
bogdanm	82:6473597d706e	1796	*
bogdanm	82:6473597d706e	1797	* This function gets the PLL1 External Reference Divider Setting.
bogdanm	82:6473597d706e	1798	*
bogdanm	82:6473597d706e	1799	* @return setting PLL1 External Reference Divider Setting
bogdanm	82:6473597d706e	1800	*/
bogdanm	82:6473597d706e	1801	static inline uint8_t clock_get_prdiv1(void)
bogdanm	82:6473597d706e	1802	{
bogdanm	82:6473597d706e	1803	return BR_MCG_C11_PRDIV1;
bogdanm	82:6473597d706e	1804	}
bogdanm	82:6473597d706e	1805
bogdanm	82:6473597d706e	1806	/*!
bogdanm	82:6473597d706e	1807	* @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	1808	*
bogdanm	82:6473597d706e	1809	* This function determines whether an interrupt request is made following a
bogdanm	82:6473597d706e	1810	* loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set.
bogdanm	82:6473597d706e	1811	*
bogdanm	82:6473597d706e	1812	* @params enable PLL1 Loss of Lock Interrupt Enable Setting
bogdanm	82:6473597d706e	1813	* - true: Generate an interrupt request on loss of lock on PLL1.
bogdanm	82:6473597d706e	1814	* - false: No interrupt request is generated on loss of lock on PLL1.
bogdanm	82:6473597d706e	1815	*/
bogdanm	82:6473597d706e	1816	static inline void clock_set_lolie1(bool enable)
bogdanm	82:6473597d706e	1817	{
bogdanm	82:6473597d706e	1818	BW_MCG_C12_LOLIE1(enable ? 1 : 0);
bogdanm	82:6473597d706e	1819	}
bogdanm	82:6473597d706e	1820
bogdanm	82:6473597d706e	1821	/*!
bogdanm	82:6473597d706e	1822	* @brief Gets the PLL1 Loss of Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	1823	*
bogdanm	82:6473597d706e	1824	* This function gets the PLL1 Loss of Lock Interrupt Enable Setting.
bogdanm	82:6473597d706e	1825	*
bogdanm	82:6473597d706e	1826	* @return enabled true if PLL1 Loss of Lock Interrupt is enabled.
bogdanm	82:6473597d706e	1827	*/
bogdanm	82:6473597d706e	1828	static inline bool clock_get_lolie1(void)
bogdanm	82:6473597d706e	1829	{
bogdanm	82:6473597d706e	1830	return BR_MCG_C12_LOLIE1;
bogdanm	82:6473597d706e	1831	}
bogdanm	82:6473597d706e	1832
bogdanm	82:6473597d706e	1833	/*!
bogdanm	82:6473597d706e	1834	* @brief Sets the Clock Monitor Enable2 Setting
bogdanm	82:6473597d706e	1835	*
bogdanm	82:6473597d706e	1836	* This function enables/disables the loss of the clock monitor for the OSC1 external
bogdanm	82:6473597d706e	1837	* reference clock. LOCRE2 determines whether a reset or interrupt request is generated
bogdanm	82:6473597d706e	1838	* following a loss of OSC1 external reference clock. The CME2 bit should only be set
bogdanm	82:6473597d706e	1839	* to a logic 1 when the MCG is in an operational mode that uses the external clock
bogdanm	82:6473597d706e	1840	* (PEE or PBE) . Whenever the CME2 bit is set to a logic 1, the value of the RANGE1
bogdanm	82:6473597d706e	1841	* bits in the C10 register should not be changed. CME2 bit should be set to a logic 0
bogdanm	82:6473597d706e	1842	* before the MCG enters any Stop mode. Otherwise, a reset request may occur while in
bogdanm	82:6473597d706e	1843	* Stop mode.
bogdanm	82:6473597d706e	1844	*
bogdanm	82:6473597d706e	1845	* @params enable Clock Monitor Enable2 Setting
bogdanm	82:6473597d706e	1846	* - true: Generate a reset request on loss of external clock on OSC1.
bogdanm	82:6473597d706e	1847	* - false: External clock monitor for OSC1 is disabled.
bogdanm	82:6473597d706e	1848	*/
bogdanm	82:6473597d706e	1849	static inline void clock_set_cme2(bool enable)
bogdanm	82:6473597d706e	1850	{
bogdanm	82:6473597d706e	1851	BW_MCG_C12_CME2(enable ? 1 : 0);
bogdanm	82:6473597d706e	1852	}
bogdanm	82:6473597d706e	1853
bogdanm	82:6473597d706e	1854	/*!
bogdanm	82:6473597d706e	1855	* @brief Gets the Clock Monitor Enable2 Setting.
bogdanm	82:6473597d706e	1856	*
bogdanm	82:6473597d706e	1857	* This function gets the Clock Monitor Enable2 Setting.
bogdanm	82:6473597d706e	1858	*
bogdanm	82:6473597d706e	1859	* @return enabled True if Clock Monitor Enable2 is enabled.
bogdanm	82:6473597d706e	1860	*/
bogdanm	82:6473597d706e	1861	static inline bool clock_get_cme2(void)
bogdanm	82:6473597d706e	1862	{
bogdanm	82:6473597d706e	1863	return BR_MCG_C12_CME2;
bogdanm	82:6473597d706e	1864	}
bogdanm	82:6473597d706e	1865
bogdanm	82:6473597d706e	1866	/*!
bogdanm	82:6473597d706e	1867	* @brief Sets the VCO1 Divider Setting.
bogdanm	82:6473597d706e	1868	*
bogdanm	82:6473597d706e	1869	* This function selects the amount to divide the VCO output of the PLL1.
bogdanm	82:6473597d706e	1870	* The VDIV1 bits establishes the multiplication factor (M) applied to the reference
bogdanm	82:6473597d706e	1871	* clock frequency. After the PLL1 is enabled (by setting either PLLCLKEN1 or
bogdanm	82:6473597d706e	1872	* PLLS), the VDIV1 value must not be changed when LOCK1 is zero.
bogdanm	82:6473597d706e	1873	*
bogdanm	82:6473597d706e	1874	* @params setting VCO1 Divider Setting
bogdanm	82:6473597d706e	1875	*/
bogdanm	82:6473597d706e	1876	static inline void clock_set_vdiv1(uint8_t setting)
bogdanm	82:6473597d706e	1877	{
bogdanm	82:6473597d706e	1878	BW_MCG_C12_VDIV1(setting);
bogdanm	82:6473597d706e	1879	}
bogdanm	82:6473597d706e	1880
bogdanm	82:6473597d706e	1881	/*!
bogdanm	82:6473597d706e	1882	* @brief Gets the VCO1 Divider Setting.
bogdanm	82:6473597d706e	1883	*
bogdanm	82:6473597d706e	1884	* This function gets the VCO1 Divider Setting.
bogdanm	82:6473597d706e	1885	*
bogdanm	82:6473597d706e	1886	* @return setting VCO1 Divider Setting
bogdanm	82:6473597d706e	1887	*/
bogdanm	82:6473597d706e	1888	static inline uint8_t clock_get_vdiv1(void)
bogdanm	82:6473597d706e	1889	{
bogdanm	82:6473597d706e	1890	return BR_MCG_C12_VDIV1;
bogdanm	82:6473597d706e	1891	}
bogdanm	82:6473597d706e	1892
bogdanm	82:6473597d706e	1893	/*!
bogdanm	82:6473597d706e	1894	* @brief Gets the Loss of the Lock2 Status.
bogdanm	82:6473597d706e	1895	*
bogdanm	82:6473597d706e	1896	* This function gets the Loss of the Lock2 Status. This bit is a sticky bit indicating
bogdanm	82:6473597d706e	1897	* the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1
bogdanm	82:6473597d706e	1898	* output frequency has fallen outside the lock exit frequency tolerance, D unl.
bogdanm	82:6473597d706e	1899	* LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This
bogdanm	82:6473597d706e	1900	* bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0
bogdanm	82:6473597d706e	1901	* to this bit has no effect.
bogdanm	82:6473597d706e	1902	*
bogdanm	82:6473597d706e	1903	* @return status Loss of Lock2 Status
bogdanm	82:6473597d706e	1904	* - 0: PLL1 has not lost lock since LOLS1 was last cleared.
bogdanm	82:6473597d706e	1905	* - 1: PLL1 has lost lock since LOLS1 was last cleared.
bogdanm	82:6473597d706e	1906	*/
bogdanm	82:6473597d706e	1907	static inline mcg_lols_status_t clock_get_lols1(void)
bogdanm	82:6473597d706e	1908	{
bogdanm	82:6473597d706e	1909	return (mcg_lols_status_t)BR_MCG_S2_LOLS1;
bogdanm	82:6473597d706e	1910	}
bogdanm	82:6473597d706e	1911
bogdanm	82:6473597d706e	1912	/*!
bogdanm	82:6473597d706e	1913	* @brief Gets the Lock1 Status.
bogdanm	82:6473597d706e	1914	*
bogdanm	82:6473597d706e	1915	* This function gets the Lock1 Status. This bit indicates whether PLL1 has
bogdanm	82:6473597d706e	1916	* acquired the lock. PLL1 Lock detection is disabled when not operating in either
bogdanm	82:6473597d706e	1917	* PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the
bogdanm	82:6473597d706e	1918	* BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK,
bogdanm	82:6473597d706e	1919	* MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets
bogdanm	82:6473597d706e	1920	* asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0]
bogdanm	82:6473597d706e	1921	* bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the
bogdanm	82:6473597d706e	1922	* lock status bit to clear and stay cleared until the PLL1 has reacquired lock.
bogdanm	82:6473597d706e	1923	* Loss of PLL1 reference clock will also causes the LOCK1 bit to clear until the PLL1
bogdanm	82:6473597d706e	1924	* has reacquired lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also
bogdanm	82:6473597d706e	1925	* causes the lock status bit to clear and stay cleared until the Stop mode is exited
bogdanm	82:6473597d706e	1926	* and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit
bogdanm	82:6473597d706e	1927	* is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off
bogdanm	82:6473597d706e	1928	* until the LOCK1 bit is asserted again.
bogdanm	82:6473597d706e	1929	*
bogdanm	82:6473597d706e	1930	* @return status Lock1 Status
bogdanm	82:6473597d706e	1931	* - 0: PLL1 is currently unlocked.
bogdanm	82:6473597d706e	1932	* - 1: PLL1 is currently locked.
bogdanm	82:6473597d706e	1933	*/
bogdanm	82:6473597d706e	1934	static inline mcg_lock_status_t clock_get_lock1(void)
bogdanm	82:6473597d706e	1935	{
bogdanm	82:6473597d706e	1936	return (mcg_lock_status_t)BR_MCG_S2_LOCK1;
bogdanm	82:6473597d706e	1937	}
bogdanm	82:6473597d706e	1938
bogdanm	82:6473597d706e	1939	/*!
bogdanm	82:6473597d706e	1940	* @brief Gets the PLL Clock Select Status.
bogdanm	82:6473597d706e	1941	*
bogdanm	82:6473597d706e	1942	* This function gets the PLL Clock Select Status. The PLLCST indicates the PLL
bogdanm	82:6473597d706e	1943	* clock selected by PLLCS. The PLLCST bit is not updated immediately after a
bogdanm	82:6473597d706e	1944	* write to the PLLCS bit due internal synchronization between clock domains.
bogdanm	82:6473597d706e	1945	*
bogdanm	82:6473597d706e	1946	* @return status PLL Clock Select Status
bogdanm	82:6473597d706e	1947	* - 0: Source of PLLCS is PLL0 clock.
bogdanm	82:6473597d706e	1948	* - 1: Source of PLLCS is PLL1 clock.
bogdanm	82:6473597d706e	1949	*/
bogdanm	82:6473597d706e	1950	static inline mcg_pllcs_select_t clock_get_pllcst(void)
bogdanm	82:6473597d706e	1951	{
bogdanm	82:6473597d706e	1952	return (mcg_pllcs_select_t)BR_MCG_S2_PLLCST;
bogdanm	82:6473597d706e	1953	}
bogdanm	82:6473597d706e	1954
bogdanm	82:6473597d706e	1955	/*!
bogdanm	82:6473597d706e	1956	* @brief Gets the OSC1 Initialization Status.
bogdanm	82:6473597d706e	1957	*
bogdanm	82:6473597d706e	1958	* This function gets the OSC1 Initialization Status. This bit is set after the
bogdanm	82:6473597d706e	1959	* initialization cycles of the 2nd crystal oscillator clock have completed. See
bogdanm	82:6473597d706e	1960	* the Oscillator block guide for more details.
bogdanm	82:6473597d706e	1961	*
bogdanm	82:6473597d706e	1962	* @return status OSC1 Initialization Status
bogdanm	82:6473597d706e	1963	*/
bogdanm	82:6473597d706e	1964	static inline uint8_t clock_get_oscinit1(void)
bogdanm	82:6473597d706e	1965	{
bogdanm	82:6473597d706e	1966	return BR_MCG_S2_OSCINIT1;
bogdanm	82:6473597d706e	1967	}
bogdanm	82:6473597d706e	1968
bogdanm	82:6473597d706e	1969	/*!
bogdanm	82:6473597d706e	1970	* @brief Gets the OSC1 Loss of Clock Status.
bogdanm	82:6473597d706e	1971	*
bogdanm	82:6473597d706e	1972	* This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss
bogdanm	82:6473597d706e	1973	* of the OSC1 external reference clock has occurred. LOCRE2 determines if a reset or
bogdanm	82:6473597d706e	1974	* interrupt is generated when LOCS2 is set. This bit is cleared by writing a
bogdanm	82:6473597d706e	1975	* logic 1 to it when set.
bogdanm	82:6473597d706e	1976	*
bogdanm	82:6473597d706e	1977	* @return status OSC1 Loss of Clock Status
bogdanm	82:6473597d706e	1978	* - 0: No loss of OSC1 external reference clock has occurred.
bogdanm	82:6473597d706e	1979	* - 1: Loss of OSC1 external reference clock has occurred.
bogdanm	82:6473597d706e	1980	*/
bogdanm	82:6473597d706e	1981	static inline mcg_locs2_status_t clock_get_locs2(void)
bogdanm	82:6473597d706e	1982	{
bogdanm	82:6473597d706e	1983	return (mcg_locs2_status_t)BR_MCG_S2_LOCS2;
bogdanm	82:6473597d706e	1984	}
bogdanm	82:6473597d706e	1985	#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
bogdanm	82:6473597d706e	1986
bogdanm	82:6473597d706e	1987	/@}/
bogdanm	82:6473597d706e	1988
bogdanm	82:6473597d706e	1989	#if defined(__cplusplus)
bogdanm	82:6473597d706e	1990	}
bogdanm	82:6473597d706e	1991	#endif /* __cplusplus*/
bogdanm	82:6473597d706e	1992
bogdanm	82:6473597d706e	1993	/! @}/
bogdanm	82:6473597d706e	1994
bogdanm	82:6473597d706e	1995	#endif /* __FSL_MCG_HAL_H__*/
bogdanm	82:6473597d706e	1996	/*******************************************************************************
bogdanm	82:6473597d706e	1997	* EOF
bogdanm	82:6473597d706e	1998	******************************************************************************/
bogdanm	82:6473597d706e	1999

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
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The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h@82:6473597d706e, 2014-04-07 (annotated)

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