frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #ifndef __EDMA_HAL_H__
bogdanm 82:6473597d706e 31 #define __EDMA_HAL_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33 #include <stdint.h>
bogdanm 82:6473597d706e 34 #include <stdbool.h>
bogdanm 82:6473597d706e 35 #include <assert.h>
bogdanm 82:6473597d706e 36 #include "fsl_edma_features.h"
bogdanm 82:6473597d706e 37 #include "fsl_device_registers.h"
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39 /*!
bogdanm 82:6473597d706e 40 * @addtogroup edma_hal
bogdanm 82:6473597d706e 41 * @{
bogdanm 82:6473597d706e 42 */
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 /*******************************************************************************
bogdanm 82:6473597d706e 45 * Definitions
bogdanm 82:6473597d706e 46 ******************************************************************************/
bogdanm 82:6473597d706e 47 /*! @brief eDMA status */
bogdanm 82:6473597d706e 48 typedef enum _edma_status
bogdanm 82:6473597d706e 49 {
bogdanm 82:6473597d706e 50 kStatus_EDMA_Success = 0U,
bogdanm 82:6473597d706e 51 kStatus_EDMA_InvalidArgument = 1U, /*!< Parameter is not available for the current configuration.*/
bogdanm 82:6473597d706e 52 kStatus_EDMA_Fail = 2U /*!< Function operation failed.*/
bogdanm 82:6473597d706e 53 } edma_status_t;
bogdanm 82:6473597d706e 54
bogdanm 82:6473597d706e 55 /*! @brief eDMA TCD control configuration */
bogdanm 82:6473597d706e 56 typedef union EdmaTCDControl {
bogdanm 82:6473597d706e 57 struct {
bogdanm 82:6473597d706e 58 uint16_t reserve1 : 1;
bogdanm 82:6473597d706e 59 uint16_t majorInterrupt : 1; /*!< Interrupt after the major loop is complete. */
bogdanm 82:6473597d706e 60 uint16_t halfInterrupt : 1; /*!< Interrupt after half of the major loop is complete. */
bogdanm 82:6473597d706e 61 uint16_t disabledDmaRequest : 1; /*!< Disabled DMA request after the major loop is complete. */
bogdanm 82:6473597d706e 62 uint16_t enabledScatterGather : 1; /*!< Enable scatter/gather processing. */
bogdanm 82:6473597d706e 63 uint16_t enableMajorLink : 1; /*!< Enabled major link after the major loop is complete. */
bogdanm 82:6473597d706e 64 uint16_t reserve2 : 1;
bogdanm 82:6473597d706e 65 uint16_t reserve3 : 1;
bogdanm 82:6473597d706e 66 uint16_t majorLinkChannel : 4; /*!< Major link channel number*/
bogdanm 82:6473597d706e 67 uint16_t reserve4 : 2;
bogdanm 82:6473597d706e 68 uint16_t bandwidthControl : 2; /*!< Bandwidth control configuration */
bogdanm 82:6473597d706e 69 } U;
bogdanm 82:6473597d706e 70 uint16_t B;
bogdanm 82:6473597d706e 71 } edma_tcd_control_t;
bogdanm 82:6473597d706e 72
bogdanm 82:6473597d706e 73 /*! @brief eDMA TCD Minor loop mapping configuration */
bogdanm 82:6473597d706e 74 typedef struct EdmaMinorLoopOffset {
bogdanm 82:6473597d706e 75 bool isEnableSourceMinorloop;
bogdanm 82:6473597d706e 76 bool isEnableDestMinorloop;
bogdanm 82:6473597d706e 77 uint32_t offset;
bogdanm 82:6473597d706e 78 } edma_minorloop_offset_config_t;
bogdanm 82:6473597d706e 79
bogdanm 82:6473597d706e 80 /*! @brief Priority limitation of the eDMA channel */
bogdanm 82:6473597d706e 81 typedef enum _edma_channel_priority {
bogdanm 82:6473597d706e 82 kEdmaChannelPriority = 16
bogdanm 82:6473597d706e 83 } edma_channel_priority_t;
bogdanm 82:6473597d706e 84
bogdanm 82:6473597d706e 85 /*! @brief eDMA modulo configuration */
bogdanm 82:6473597d706e 86 typedef enum _edma_modulo {
bogdanm 82:6473597d706e 87 kEdmaModuloDisable = 0x0U,
bogdanm 82:6473597d706e 88 kEdmaModulo2bytes = 0x1U,
bogdanm 82:6473597d706e 89 kEdmaModulo4bytes = 0x2U,
bogdanm 82:6473597d706e 90 kEdmaModulo8bytes = 0x3U,
bogdanm 82:6473597d706e 91 kEdmaModulo16bytes = 0x4U,
bogdanm 82:6473597d706e 92 kEdmaModulo32bytes = 0x5U,
bogdanm 82:6473597d706e 93 kEdmaModulo64bytes = 0x6U,
bogdanm 82:6473597d706e 94 kEdmaModulo128bytes = 0x7U,
bogdanm 82:6473597d706e 95 kEdmaModulo256bytes = 0x8U,
bogdanm 82:6473597d706e 96 kEdmaModulo512bytes = 0x9U,
bogdanm 82:6473597d706e 97 kEdmaModulo1Kbytes = 0xaU,
bogdanm 82:6473597d706e 98 kEdmaModulo2Kbytes = 0xbU,
bogdanm 82:6473597d706e 99 kEdmaModulo4Kbytes = 0xcU,
bogdanm 82:6473597d706e 100 kEdmaModulo8Kbytes = 0xdU,
bogdanm 82:6473597d706e 101 kEdmaModulo16Kbytes = 0xeU,
bogdanm 82:6473597d706e 102 kEdmaModulo32Kbytes = 0xfU,
bogdanm 82:6473597d706e 103 kEdmaModulo64Kbytes = 0x10U,
bogdanm 82:6473597d706e 104 kEdmaModulo128Kbytes = 0x11U,
bogdanm 82:6473597d706e 105 kEdmaModulo256Kbytes = 0x12U,
bogdanm 82:6473597d706e 106 kEdmaModulo512Kbytes = 0x13U,
bogdanm 82:6473597d706e 107 kEdmaModulo1Mbytes = 0x14U,
bogdanm 82:6473597d706e 108 kEdmaModulo2Mbytes = 0x15U,
bogdanm 82:6473597d706e 109 kEdmaModulo4Mbytes = 0x16U,
bogdanm 82:6473597d706e 110 kEdmaModulo8Mbytes = 0x17U,
bogdanm 82:6473597d706e 111 kEdmaModulo16Mbytes = 0x18U,
bogdanm 82:6473597d706e 112 kEdmaModulo32Mbytes = 0x19U,
bogdanm 82:6473597d706e 113 kEdmaModulo64Mbytes = 0x1aU,
bogdanm 82:6473597d706e 114 kEdmaModulo128Mbytes = 0x1bU,
bogdanm 82:6473597d706e 115 kEdmaModulo256Mbytes = 0x1cU,
bogdanm 82:6473597d706e 116 kEdmaModulo512Mbytes = 0x1dU,
bogdanm 82:6473597d706e 117 kEdmaModulo1Gbytes = 0x1eU,
bogdanm 82:6473597d706e 118 kEdmaModulo2Gbytes = 0x1fU
bogdanm 82:6473597d706e 119 } edma_modulo_t;
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 /*! @brief eDMA transfer size configuration */
bogdanm 82:6473597d706e 122 typedef enum _edma_transfer_size {
bogdanm 82:6473597d706e 123 kEdmaTransferSize1bytes = 0x0U,
bogdanm 82:6473597d706e 124 kEdmaTransferSize2bytes = 0x1U,
bogdanm 82:6473597d706e 125 kEdmaTransferSize4bytes = 0x2U,
bogdanm 82:6473597d706e 126 kEdmaTransferSize16bytes = 0x4U,
bogdanm 82:6473597d706e 127 kEdmaTransferSize32bytes = 0x5U
bogdanm 82:6473597d706e 128 } edma_transfer_size_t;
bogdanm 82:6473597d706e 129
bogdanm 82:6473597d706e 130 /*! @brief Error status of the eDMA module */
bogdanm 82:6473597d706e 131 typedef union EdmaErrorStatusAll {
bogdanm 82:6473597d706e 132 struct {
bogdanm 82:6473597d706e 133 uint32_t destinationBusError : 1; /*!< Bus error on destination address */
bogdanm 82:6473597d706e 134 uint32_t sourceBusError : 1; /*!< Bus error on the SRC address */
bogdanm 82:6473597d706e 135 uint32_t scatterOrGatherConfigurationError : 1; /*!< Error on the Scatter/Gather address */
bogdanm 82:6473597d706e 136 uint32_t nbyteOrCiterConfigurationError : 1; /*!< NBYTES/CITER configuration error */
bogdanm 82:6473597d706e 137 uint32_t destinationOffsetError : 1; /*!< Destination offset error */
bogdanm 82:6473597d706e 138 uint32_t destinationAddressError : 1; /*!< Destination address error */
bogdanm 82:6473597d706e 139 uint32_t sourceOffsetError : 1; /*!< Source offset error */
bogdanm 82:6473597d706e 140 uint32_t sourceAddressError : 1; /*!< Source address error */
bogdanm 82:6473597d706e 141 uint32_t errorChannel : 5; /*!< Error channel number of the cancelled
bogdanm 82:6473597d706e 142 channel number */
bogdanm 82:6473597d706e 143 uint32_t _reserved1 : 1;
bogdanm 82:6473597d706e 144 uint32_t channelPriorityError : 1; /*!< Channel priority error */
bogdanm 82:6473597d706e 145 uint32_t groupPriorityError : 1; /*!< Group priority error */
bogdanm 82:6473597d706e 146 uint32_t transferCancelledError : 1; /*!< Transfer cancelled */
bogdanm 82:6473597d706e 147 uint32_t _reserved0 : 14;
bogdanm 82:6473597d706e 148 uint32_t orOfAllError : 1; /*!< Logical OR all ERR status bits */
bogdanm 82:6473597d706e 149 } U;
bogdanm 82:6473597d706e 150 uint32_t B;
bogdanm 82:6473597d706e 151 } edma_error_status_all_t;
bogdanm 82:6473597d706e 152
bogdanm 82:6473597d706e 153 /*! @brief Bandwidth control configuration */
bogdanm 82:6473597d706e 154 typedef enum _edma_bandwidth_configuration {
bogdanm 82:6473597d706e 155 kEdmaBandwidthStallNone = 0, /*!< No eDMA engine stalls. */
bogdanm 82:6473597d706e 156 kEdmaBandwidthStall4Cycle = 2, /*!< eDMA engine stalls for 4 cycles after each read/write. */
bogdanm 82:6473597d706e 157 kEdmaBandwidthStall8Cycle = 3 /*!< eDMA engine stalls for 4 cycles after each read/write. */
bogdanm 82:6473597d706e 158 } edma_bandwidth_configuration_t;
bogdanm 82:6473597d706e 159
bogdanm 82:6473597d706e 160 /*! @brief eDMA TCD */
bogdanm 82:6473597d706e 161 typedef struct EdmaSoftwareTcd {
bogdanm 82:6473597d706e 162 uint32_t SADDR;
bogdanm 82:6473597d706e 163 uint16_t SOFF;
bogdanm 82:6473597d706e 164 uint16_t ATTR;
bogdanm 82:6473597d706e 165 union {
bogdanm 82:6473597d706e 166 uint32_t NBYTES_MLNO;
bogdanm 82:6473597d706e 167 uint32_t NBYTES_MLOFFNO;
bogdanm 82:6473597d706e 168 uint32_t NBYTES_MLOFFYES;
bogdanm 82:6473597d706e 169 };
bogdanm 82:6473597d706e 170 uint32_t SLAST;
bogdanm 82:6473597d706e 171 uint32_t DADDR;
bogdanm 82:6473597d706e 172 uint16_t DOFF;
bogdanm 82:6473597d706e 173 union {
bogdanm 82:6473597d706e 174 uint16_t CITER_ELINKNO;
bogdanm 82:6473597d706e 175 uint16_t CITER_ELINKYES;
bogdanm 82:6473597d706e 176 };
bogdanm 82:6473597d706e 177 uint32_t DLAST_SGA;
bogdanm 82:6473597d706e 178 uint16_t CSR;
bogdanm 82:6473597d706e 179 union {
bogdanm 82:6473597d706e 180 uint16_t BITER_ELINKNO;
bogdanm 82:6473597d706e 181 uint16_t BITER_ELINKYES;
bogdanm 82:6473597d706e 182 };
bogdanm 82:6473597d706e 183 } edma_software_tcd_t;
bogdanm 82:6473597d706e 184
bogdanm 82:6473597d706e 185 /*! @brief eDMA group priority */
bogdanm 82:6473597d706e 186 typedef enum _edma_group_priority {
bogdanm 82:6473597d706e 187 kEdmaGroup0Priority0Group1Priority1,
bogdanm 82:6473597d706e 188 kEdmaGroup0Priority1Group1Priority0
bogdanm 82:6473597d706e 189 } edma_group_priority_t;
bogdanm 82:6473597d706e 190
bogdanm 82:6473597d706e 191 /*! @brief DMA configuration structure */
bogdanm 82:6473597d706e 192 typedef struct EdmaConfiguration {
bogdanm 82:6473597d706e 193 bool isEnableMinorLoopping; /*!< Enabled the minor loop mapping. */
bogdanm 82:6473597d706e 194 bool isEnableContinuousMode; /*!< Enabled the continuous mode. */
bogdanm 82:6473597d706e 195 bool isHaltOnError; /*!< Halt if error happens. */
bogdanm 82:6473597d706e 196 bool isEnableRoundrobinArbitration; /*!< Enabled round robin or fixed priority arbitration. */
bogdanm 82:6473597d706e 197 bool isEnableDebug; /*!< Enabled Debug mode. */
bogdanm 82:6473597d706e 198 #if (FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT > 0x1U)
bogdanm 82:6473597d706e 199 edma_group_priority_t groupPriority;
bogdanm 82:6473597d706e 200 bool isEnableGroupRoundrobinArbitration;
bogdanm 82:6473597d706e 201 #endif
bogdanm 82:6473597d706e 202 } edma_config_t;
bogdanm 82:6473597d706e 203
bogdanm 82:6473597d706e 204 /*******************************************************************************
bogdanm 82:6473597d706e 205 * API
bogdanm 82:6473597d706e 206 ******************************************************************************/
bogdanm 82:6473597d706e 207
bogdanm 82:6473597d706e 208 #if defined(__cplusplus)
bogdanm 82:6473597d706e 209 extern "C" {
bogdanm 82:6473597d706e 210 #endif
bogdanm 82:6473597d706e 211
bogdanm 82:6473597d706e 212 /*!
bogdanm 82:6473597d706e 213 * @name EDMA HAL common configuration
bogdanm 82:6473597d706e 214 * @{
bogdanm 82:6473597d706e 215 */
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 /*!
bogdanm 82:6473597d706e 218 * @brief Initializes the eDMA module.
bogdanm 82:6473597d706e 219 *
bogdanm 82:6473597d706e 220 * The function configures the eDMA module with the corresponding global configuration. The
bogdanm 82:6473597d706e 221 * configuration is for all channels in this module.
bogdanm 82:6473597d706e 222 *
bogdanm 82:6473597d706e 223 * @param module eDMA module
bogdanm 82:6473597d706e 224 * @param init Init data structure
bogdanm 82:6473597d706e 225 */
bogdanm 82:6473597d706e 226 void edma_hal_init(uint32_t instance, const edma_config_t *init);
bogdanm 82:6473597d706e 227
bogdanm 82:6473597d706e 228 /*!
bogdanm 82:6473597d706e 229 * @brief Cancels the remaining data transfer. Stops the executing channel and forces the minor loop
bogdanm 82:6473597d706e 230 * to finish. The cancellation takes effect after the last write of the current read/write sequence.
bogdanm 82:6473597d706e 231 * The CX clears itself after the cancel has been honored. This cancel retires the channel
bogdanm 82:6473597d706e 232 * normally as if the minor loop had completed.
bogdanm 82:6473597d706e 233 *
bogdanm 82:6473597d706e 234 * @param instance eDMA module
bogdanm 82:6473597d706e 235 */
bogdanm 82:6473597d706e 236 static inline void edma_hal_cancel_transfer(uint32_t instance)
bogdanm 82:6473597d706e 237 {
bogdanm 82:6473597d706e 238 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 239 BW_DMA_CR_CX(instance, 1U);
bogdanm 82:6473597d706e 240 while (BR_DMA_CR_CX(instance))
bogdanm 82:6473597d706e 241 {}
bogdanm 82:6473597d706e 242 }
bogdanm 82:6473597d706e 243
bogdanm 82:6473597d706e 244 /*!
bogdanm 82:6473597d706e 245 * @brief Cancels the remaining data transfer. Stops the executing channel and forces the minor loop to
bogdanm 82:6473597d706e 246 * finish. The cancellation takes effect after the last write of the current read/write sequence. The
bogdanm 82:6473597d706e 247 * ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
bogdanm 82:6473597d706e 248 * treats the cancel as an error condition.
bogdanm 82:6473597d706e 249 *
bogdanm 82:6473597d706e 250 * @param instance eDMA module
bogdanm 82:6473597d706e 251 */
bogdanm 82:6473597d706e 252 static inline void edma_hal_error_cancel_transfer(uint32_t instance)
bogdanm 82:6473597d706e 253 {
bogdanm 82:6473597d706e 254 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 255 BW_DMA_CR_ECX(instance, 1U);
bogdanm 82:6473597d706e 256 while(BR_DMA_CR_ECX(instance))
bogdanm 82:6473597d706e 257 {}
bogdanm 82:6473597d706e 258 }
bogdanm 82:6473597d706e 259
bogdanm 82:6473597d706e 260 /*!
bogdanm 82:6473597d706e 261 * @brief Enables/Disables the minor loop mapping.
bogdanm 82:6473597d706e 262 *
bogdanm 82:6473597d706e 263 * If enabled, the NBYTES is redefined to include individual enable fields. And the NBYTES field. The
bogdanm 82:6473597d706e 264 * individual enable fields allow the minor loop offset to be applied to the source address, the
bogdanm 82:6473597d706e 265 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
bogdanm 82:6473597d706e 266 *
bogdanm 82:6473597d706e 267 * @param instance eDMA module
bogdanm 82:6473597d706e 268 * @param isEnabled Enable or disable.
bogdanm 82:6473597d706e 269 */
bogdanm 82:6473597d706e 270 static inline void edma_hal_set_minor_loop_mapping(uint32_t instance, bool isEnabled)
bogdanm 82:6473597d706e 271 {
bogdanm 82:6473597d706e 272 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 273 BW_DMA_CR_EMLM(instance, isEnabled);
bogdanm 82:6473597d706e 274 }
bogdanm 82:6473597d706e 275
bogdanm 82:6473597d706e 276
bogdanm 82:6473597d706e 277 #if (FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT > 0x1U)
bogdanm 82:6473597d706e 278 /*!
bogdanm 82:6473597d706e 279 * @brief Configures the group priority.
bogdanm 82:6473597d706e 280 *
bogdanm 82:6473597d706e 281 * @param module eDMA module
bogdanm 82:6473597d706e 282 * @param isContinuous Whether the minor loop finish triggers itself.
bogdanm 82:6473597d706e 283 */
bogdanm 82:6473597d706e 284 static inline void edma_hal_set_group_priority(uint32_t instance, edma_group_priority_t groupPriority)
bogdanm 82:6473597d706e 285 {
bogdanm 82:6473597d706e 286 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 287
bogdanm 82:6473597d706e 288 if (groupPriority == kEdmaGroup0Priority0Group1Priority1)
bogdanm 82:6473597d706e 289 {
bogdanm 82:6473597d706e 290 BW_DMA_CR_GRP0PRI(instance, 0U);
bogdanm 82:6473597d706e 291 BW_DMA_CR_GRP1PRI(instance, 1U);
bogdanm 82:6473597d706e 292 }
bogdanm 82:6473597d706e 293 else
bogdanm 82:6473597d706e 294 {
bogdanm 82:6473597d706e 295 BW_DMA_CR_GRP0PRI(instance, 1U);
bogdanm 82:6473597d706e 296 BW_DMA_CR_GRP1PRI(instance, 0U);
bogdanm 82:6473597d706e 297
bogdanm 82:6473597d706e 298 }
bogdanm 82:6473597d706e 299 }
bogdanm 82:6473597d706e 300
bogdanm 82:6473597d706e 301 /*!
bogdanm 82:6473597d706e 302 * @brief The fixed priority arbitration is used for the group selection.
bogdanm 82:6473597d706e 303 *
bogdanm 82:6473597d706e 304 * @param instance eDMA module
bogdanm 82:6473597d706e 305 */
bogdanm 82:6473597d706e 306 static inline void edma_hal_set_fixed_priority_group_arbitration(uint32_t instance)
bogdanm 82:6473597d706e 307 {
bogdanm 82:6473597d706e 308 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 309 BW_DMA_CR_ERGA(instance, 0U);
bogdanm 82:6473597d706e 310 }
bogdanm 82:6473597d706e 311
bogdanm 82:6473597d706e 312 /*!
bogdanm 82:6473597d706e 313 * @brief The round robin arbitration is used for the group selection.
bogdanm 82:6473597d706e 314 *
bogdanm 82:6473597d706e 315 * @param instance eDMA module
bogdanm 82:6473597d706e 316 */
bogdanm 82:6473597d706e 317 static inline void edma_hal_set_roundrobin_group_arbitration(uint32_t instance)
bogdanm 82:6473597d706e 318 {
bogdanm 82:6473597d706e 319 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 320 BW_DMA_CR_ERGA(instance, 1U);
bogdanm 82:6473597d706e 321 }
bogdanm 82:6473597d706e 322
bogdanm 82:6473597d706e 323 #endif
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325 /*!
bogdanm 82:6473597d706e 326 * @brief Configures the continuous mode. If set, a minor loop channel link does not
bogdanm 82:6473597d706e 327 * go through the channel arbitration before being activated again. Upon minor loop completion, the
bogdanm 82:6473597d706e 328 * channel activates again if that channel has a minor loop channel link enabled and the link
bogdanm 82:6473597d706e 329 * channel is itself.
bogdanm 82:6473597d706e 330 *
bogdanm 82:6473597d706e 331 * @param module eDMA module
bogdanm 82:6473597d706e 332 * @param isContinuous Whether the minor loop finish triggers itself.
bogdanm 82:6473597d706e 333 */
bogdanm 82:6473597d706e 334 static inline void edma_hal_set_continuous_mode(uint32_t instance, bool isContinuous)
bogdanm 82:6473597d706e 335 {
bogdanm 82:6473597d706e 336 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 337 BW_DMA_CR_CLM(instance, isContinuous);
bogdanm 82:6473597d706e 338 }
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 /*!
bogdanm 82:6473597d706e 341 * @brief Halts the DMA Operations.
bogdanm 82:6473597d706e 342 *
bogdanm 82:6473597d706e 343 * Stalls the start of any new channels. Executing channels are allowed to complete.
bogdanm 82:6473597d706e 344 *
bogdanm 82:6473597d706e 345 * @param instance eDMA module.
bogdanm 82:6473597d706e 346 */
bogdanm 82:6473597d706e 347 static inline void edma_hal_halt(uint32_t instance)
bogdanm 82:6473597d706e 348 {
bogdanm 82:6473597d706e 349 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 350 BW_DMA_CR_HALT(instance, 1U);
bogdanm 82:6473597d706e 351 }
bogdanm 82:6473597d706e 352
bogdanm 82:6473597d706e 353 /*!
bogdanm 82:6473597d706e 354 * @brief Clears the halt bit.
bogdanm 82:6473597d706e 355 *
bogdanm 82:6473597d706e 356 * If a previous eDMA channel is halted, clear operation would resume it back to executing.
bogdanm 82:6473597d706e 357 *
bogdanm 82:6473597d706e 358 * @param instance eDMA module.
bogdanm 82:6473597d706e 359 */
bogdanm 82:6473597d706e 360 static inline void edma_hal_clear_halt(uint32_t instance)
bogdanm 82:6473597d706e 361 {
bogdanm 82:6473597d706e 362 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 363 BW_DMA_CR_HALT(instance, 0U);
bogdanm 82:6473597d706e 364 }
bogdanm 82:6473597d706e 365
bogdanm 82:6473597d706e 366 /*!
bogdanm 82:6473597d706e 367 * @brief Halts the eDMA module when an error occurs.
bogdanm 82:6473597d706e 368 *
bogdanm 82:6473597d706e 369 * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the
bogdanm 82:6473597d706e 370 * HALT bit is cleared.
bogdanm 82:6473597d706e 371 *
bogdanm 82:6473597d706e 372 * @param instance eDMA module.
bogdanm 82:6473597d706e 373 * @param isHaltOnError halts or does not halt when an error occurs.
bogdanm 82:6473597d706e 374 */
bogdanm 82:6473597d706e 375 static inline void edma_hal_set_halt_on_error(uint32_t instance, bool isHaltOnError)
bogdanm 82:6473597d706e 376 {
bogdanm 82:6473597d706e 377 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 378 BW_DMA_CR_HOE(instance, isHaltOnError);
bogdanm 82:6473597d706e 379 }
bogdanm 82:6473597d706e 380
bogdanm 82:6473597d706e 381 /*!
bogdanm 82:6473597d706e 382 * @brief The fixed priority arbitration is used for the channel selection.
bogdanm 82:6473597d706e 383 *
bogdanm 82:6473597d706e 384 * @param instance eDMA module.
bogdanm 82:6473597d706e 385 */
bogdanm 82:6473597d706e 386 static inline void edma_hal_set_fixed_priority_channel_arbitration(uint32_t instance)
bogdanm 82:6473597d706e 387 {
bogdanm 82:6473597d706e 388 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 389 BW_DMA_CR_ERCA(instance, 0U);
bogdanm 82:6473597d706e 390 }
bogdanm 82:6473597d706e 391
bogdanm 82:6473597d706e 392 /*!
bogdanm 82:6473597d706e 393 * @brief The round robin arbitration is used for the channel selection.
bogdanm 82:6473597d706e 394 *
bogdanm 82:6473597d706e 395 * @param instance eDMA module.
bogdanm 82:6473597d706e 396 */
bogdanm 82:6473597d706e 397 static inline void edma_hal_set_roundrobin_channel_arbitration(uint32_t instance)
bogdanm 82:6473597d706e 398 {
bogdanm 82:6473597d706e 399 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 400 BW_DMA_CR_ERCA(instance, 1U);
bogdanm 82:6473597d706e 401 }
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 /*!
bogdanm 82:6473597d706e 404 * @brief Enables/Disables the eDMA DEBUG mode.
bogdanm 82:6473597d706e 405 *
bogdanm 82:6473597d706e 406 * When in debug mode, the DMA stalls the start of a new
bogdanm 82:6473597d706e 407 * channel. Executing channels are allowed to complete. Channel execution resumes
bogdanm 82:6473597d706e 408 * either when the system exits debug mode or when the EDBG bit is cleared.
bogdanm 82:6473597d706e 409 *
bogdanm 82:6473597d706e 410 * @param instance eDMA module.
bogdanm 82:6473597d706e 411 */
bogdanm 82:6473597d706e 412 static inline void edma_hal_set_debug_mode(uint32_t instance, bool isEnabled)
bogdanm 82:6473597d706e 413 {
bogdanm 82:6473597d706e 414 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 415 BW_DMA_CR_EDBG(instance, isEnabled);
bogdanm 82:6473597d706e 416 }
bogdanm 82:6473597d706e 417
bogdanm 82:6473597d706e 418 /*!
bogdanm 82:6473597d706e 419 * @brief Gets the error status of the eDMA module. The detailed reason is listed along with the error
bogdanm 82:6473597d706e 420 * channel.
bogdanm 82:6473597d706e 421 *
bogdanm 82:6473597d706e 422 * @param instance eDMA module
bogdanm 82:6473597d706e 423 * @return Detailed information of the error type in the eDMA module.
bogdanm 82:6473597d706e 424 */
bogdanm 82:6473597d706e 425 static inline uint32_t edma_hal_get_error_status(uint32_t instance)
bogdanm 82:6473597d706e 426 {
bogdanm 82:6473597d706e 427 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 428 return HW_DMA_ES_RD(instance);
bogdanm 82:6473597d706e 429 }
bogdanm 82:6473597d706e 430
bogdanm 82:6473597d706e 431 /*!
bogdanm 82:6473597d706e 432 * @brief Disables the interrupt when an error happens on any of channel in the eDMA module.
bogdanm 82:6473597d706e 433 *
bogdanm 82:6473597d706e 434 * @param instance eDMA module
bogdanm 82:6473597d706e 435 */
bogdanm 82:6473597d706e 436 static inline void edma_hal_disable_all_enabled_error_interrupt(uint32_t instance)
bogdanm 82:6473597d706e 437 {
bogdanm 82:6473597d706e 438 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 439 BW_DMA_CEEI_CAEE(instance, 1U);
bogdanm 82:6473597d706e 440 }
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 /*!
bogdanm 82:6473597d706e 443 * @brief Enables an interrupt when an error happens on any channel in the eDMA module.
bogdanm 82:6473597d706e 444 *
bogdanm 82:6473597d706e 445 * @param instance eDMA module
bogdanm 82:6473597d706e 446 */
bogdanm 82:6473597d706e 447 static inline void edma_hal_enable_all_channel_error_interrupt(uint32_t instance)
bogdanm 82:6473597d706e 448 {
bogdanm 82:6473597d706e 449 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 450
bogdanm 82:6473597d706e 451 BW_DMA_SEEI_SAEE(instance, 1U);
bogdanm 82:6473597d706e 452 }
bogdanm 82:6473597d706e 453
bogdanm 82:6473597d706e 454 /*!
bogdanm 82:6473597d706e 455 * @brief Disables the DMA request for all eDMA channels.
bogdanm 82:6473597d706e 456 *
bogdanm 82:6473597d706e 457 * @param instance eDMA module
bogdanm 82:6473597d706e 458 */
bogdanm 82:6473597d706e 459 static inline void edma_hal_disable_all_channel_dma_request(uint32_t instance)
bogdanm 82:6473597d706e 460 {
bogdanm 82:6473597d706e 461 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 462 HW_DMA_CERQ_WR(instance, DMA_CERQ_CAER_MASK);
bogdanm 82:6473597d706e 463 }
bogdanm 82:6473597d706e 464
bogdanm 82:6473597d706e 465 /*!
bogdanm 82:6473597d706e 466 * @brief Enables the DMA request for all eDMA channels.
bogdanm 82:6473597d706e 467 *
bogdanm 82:6473597d706e 468 * @param instance eDMA module
bogdanm 82:6473597d706e 469 */
bogdanm 82:6473597d706e 470 static inline void edma_hal_enable_all_channel_dma_request(uint32_t instance)
bogdanm 82:6473597d706e 471 {
bogdanm 82:6473597d706e 472 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 473 HW_DMA_SERQ_WR(instance, DMA_SERQ_SAER_MASK);
bogdanm 82:6473597d706e 474 }
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 /*!
bogdanm 82:6473597d706e 477 * @brief Clears the done status for all eDMA channels.
bogdanm 82:6473597d706e 478 *
bogdanm 82:6473597d706e 479 * @param instance eDMA module
bogdanm 82:6473597d706e 480 */
bogdanm 82:6473597d706e 481 static inline void edma_hal_clear_all_channel_done_status(uint32_t instance)
bogdanm 82:6473597d706e 482 {
bogdanm 82:6473597d706e 483 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 484 HW_DMA_CDNE_WR(instance, DMA_CDNE_CADN_MASK);
bogdanm 82:6473597d706e 485 }
bogdanm 82:6473597d706e 486
bogdanm 82:6473597d706e 487 /*!
bogdanm 82:6473597d706e 488 * @brief Triggers all channel start bits.
bogdanm 82:6473597d706e 489 *
bogdanm 82:6473597d706e 490 * @param instance eDMA module
bogdanm 82:6473597d706e 491 */
bogdanm 82:6473597d706e 492 static inline void edma_hal_trigger_all_channel_start_bit(uint32_t instance)
bogdanm 82:6473597d706e 493 {
bogdanm 82:6473597d706e 494 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 495 HW_DMA_SSRT_WR(instance, DMA_SSRT_SAST_MASK);
bogdanm 82:6473597d706e 496 }
bogdanm 82:6473597d706e 497
bogdanm 82:6473597d706e 498 /*!
bogdanm 82:6473597d706e 499 * @brief Clears the error status for all eDMA channels.
bogdanm 82:6473597d706e 500 *
bogdanm 82:6473597d706e 501 * @param instance eDMA module
bogdanm 82:6473597d706e 502 */
bogdanm 82:6473597d706e 503 static inline void edma_hal_clear_all_channel_error_status(uint32_t instance)
bogdanm 82:6473597d706e 504 {
bogdanm 82:6473597d706e 505 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 506 HW_DMA_CERR_WR(instance, DMA_CERR_CAEI_MASK);
bogdanm 82:6473597d706e 507 }
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 /*!
bogdanm 82:6473597d706e 510 * @brief Clears an interrupt request for all eDMA channels.
bogdanm 82:6473597d706e 511 *
bogdanm 82:6473597d706e 512 * @param instance eDMA module
bogdanm 82:6473597d706e 513 */
bogdanm 82:6473597d706e 514 static inline void edma_hal_clear_all_channel_interrupt_request(uint32_t instance)
bogdanm 82:6473597d706e 515 {
bogdanm 82:6473597d706e 516 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 517 HW_DMA_CINT_WR(instance, DMA_CINT_CAIR_MASK);
bogdanm 82:6473597d706e 518 }
bogdanm 82:6473597d706e 519
bogdanm 82:6473597d706e 520 /*!
bogdanm 82:6473597d706e 521 * @brief Gets the interrupt status for all eDMA channels.
bogdanm 82:6473597d706e 522 *
bogdanm 82:6473597d706e 523 * @param instance eDMA module
bogdanm 82:6473597d706e 524 * @return 32 bit data. Every bit stands for an eDMA channel. For example, bit 0 stands for channel 0 and so on.
bogdanm 82:6473597d706e 525 */
bogdanm 82:6473597d706e 526 static inline uint32_t edma_hal_get_all_channel_interrupt_request_status(uint32_t instance)
bogdanm 82:6473597d706e 527 {
bogdanm 82:6473597d706e 528 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 529 return HW_DMA_INT_RD(instance);
bogdanm 82:6473597d706e 530 }
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 /*!
bogdanm 82:6473597d706e 533 * @brief Gets the channel error status for all eDMA channels.
bogdanm 82:6473597d706e 534 *
bogdanm 82:6473597d706e 535 * @param instance eDMA module
bogdanm 82:6473597d706e 536 * @return 32 bit data. Every bit stands for an eDMA channel. For example, bit 0 stands for channel 0 and so on.
bogdanm 82:6473597d706e 537 */
bogdanm 82:6473597d706e 538 static inline uint32_t edma_hal_get_all_channel_error_status(uint32_t instance)
bogdanm 82:6473597d706e 539 {
bogdanm 82:6473597d706e 540 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 541 return HW_DMA_ERR_RD(instance);
bogdanm 82:6473597d706e 542 }
bogdanm 82:6473597d706e 543
bogdanm 82:6473597d706e 544 /*!
bogdanm 82:6473597d706e 545 * @brief Gets the status of the DMA request for all DMA channels.
bogdanm 82:6473597d706e 546 *
bogdanm 82:6473597d706e 547 * @param instance eDMA module
bogdanm 82:6473597d706e 548 * @return 32 bit data. Every bit stands for an eDMA channel. For example, bit 0 stands for channel 0 and so on.
bogdanm 82:6473597d706e 549 */
bogdanm 82:6473597d706e 550 static inline uint32_t edma_hal_get_all_channel_dma_request_status(uint32_t instance)
bogdanm 82:6473597d706e 551 {
bogdanm 82:6473597d706e 552 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 553 return HW_DMA_HRS_RD(instance);
bogdanm 82:6473597d706e 554 }
bogdanm 82:6473597d706e 555
bogdanm 82:6473597d706e 556 /* @} */
bogdanm 82:6473597d706e 557
bogdanm 82:6473597d706e 558 /*!
bogdanm 82:6473597d706e 559 * @name EDMA HAL channel configuration.
bogdanm 82:6473597d706e 560 * @{
bogdanm 82:6473597d706e 561 */
bogdanm 82:6473597d706e 562
bogdanm 82:6473597d706e 563 /*!
bogdanm 82:6473597d706e 564 * @brief Check whether the channel DMA request is enabled.
bogdanm 82:6473597d706e 565 *
bogdanm 82:6473597d706e 566 * Check whether the DMA request of a specified channel is enabled.
bogdanm 82:6473597d706e 567 *
bogdanm 82:6473597d706e 568 * @param instance eDMA module
bogdanm 82:6473597d706e 569 * @param channel eDMA channel
bogdanm 82:6473597d706e 570 *
bogdanm 82:6473597d706e 571 * @return True stands for enabled. False stands for disabled.
bogdanm 82:6473597d706e 572 */
bogdanm 82:6473597d706e 573 static inline bool edma_hal_check_dma_request_enable_status(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 574 {
bogdanm 82:6473597d706e 575 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 576 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 577
bogdanm 82:6473597d706e 578 return ((HW_DMA_ERQ_RD(instance)>>channel) & 1U);
bogdanm 82:6473597d706e 579 }
bogdanm 82:6473597d706e 580
bogdanm 82:6473597d706e 581 /*!
bogdanm 82:6473597d706e 582 * @brief Disables an interrupt when an error happens in the eDMA channel.
bogdanm 82:6473597d706e 583 *
bogdanm 82:6473597d706e 584 * Disables an error interrupt for the eDMA module.
bogdanm 82:6473597d706e 585 *
bogdanm 82:6473597d706e 586 * @param instance eDMA module
bogdanm 82:6473597d706e 587 * @param channel eDMA channel
bogdanm 82:6473597d706e 588 */
bogdanm 82:6473597d706e 589 static inline void edma_hal_disable_error_interrupt(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 590 {
bogdanm 82:6473597d706e 591 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 592 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 593 HW_DMA_CEEI_WR(instance, DMA_CEEI_CEEI(channel));
bogdanm 82:6473597d706e 594 }
bogdanm 82:6473597d706e 595
bogdanm 82:6473597d706e 596 /*!
bogdanm 82:6473597d706e 597 * @brief Enables an interrupt when an error happens in the eDMA channel.
bogdanm 82:6473597d706e 598 *
bogdanm 82:6473597d706e 599 * @param instance eDMA module
bogdanm 82:6473597d706e 600 * @param channel eDMA channel
bogdanm 82:6473597d706e 601 */
bogdanm 82:6473597d706e 602 static inline void edma_hal_enable_error_interrupt(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 603 {
bogdanm 82:6473597d706e 604 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 605 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 606 HW_DMA_SEEI_WR(instance, DMA_SEEI_SEEI(channel));
bogdanm 82:6473597d706e 607 }
bogdanm 82:6473597d706e 608
bogdanm 82:6473597d706e 609 /*!
bogdanm 82:6473597d706e 610 * @brief Disables the DMA request for an eDMA channel.
bogdanm 82:6473597d706e 611 *
bogdanm 82:6473597d706e 612 * @param instance eDMA module
bogdanm 82:6473597d706e 613 * @param channel eDMA channel
bogdanm 82:6473597d706e 614 */
bogdanm 82:6473597d706e 615 static inline void edma_hal_disable_dma_request(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 616 {
bogdanm 82:6473597d706e 617 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 618 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 619 HW_DMA_CERQ_WR(instance, DMA_CERQ_CERQ(channel));
bogdanm 82:6473597d706e 620 }
bogdanm 82:6473597d706e 621
bogdanm 82:6473597d706e 622 /*!
bogdanm 82:6473597d706e 623 * @brief Enables the DMA request for a specified eDMA channel.
bogdanm 82:6473597d706e 624 *
bogdanm 82:6473597d706e 625 * @param instance eDMA module
bogdanm 82:6473597d706e 626 * @param channel eDMA channel
bogdanm 82:6473597d706e 627 */
bogdanm 82:6473597d706e 628 static inline void edma_hal_enable_dma_request(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 629 {
bogdanm 82:6473597d706e 630 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 631 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 632 HW_DMA_SERQ_WR(instance, DMA_SERQ_SERQ(channel));
bogdanm 82:6473597d706e 633 }
bogdanm 82:6473597d706e 634
bogdanm 82:6473597d706e 635 /*!
bogdanm 82:6473597d706e 636 * @brief Clears the done status for an eDMA channel.
bogdanm 82:6473597d706e 637 *
bogdanm 82:6473597d706e 638 * The DONE status of the DMA channel is cleared. If the scatter/gather state is
bogdanm 82:6473597d706e 639 * enabled, the DONE status in CSR can be cleared but the global DONE statue is
bogdanm 82:6473597d706e 640 * still set. This function is to clear the global done state.
bogdanm 82:6473597d706e 641 *
bogdanm 82:6473597d706e 642 * @param instance eDMA module
bogdanm 82:6473597d706e 643 * @param channel eDMA channel
bogdanm 82:6473597d706e 644 */
bogdanm 82:6473597d706e 645 static inline void edma_hal_clear_done_status(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 646 {
bogdanm 82:6473597d706e 647 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 648 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 649 HW_DMA_CDNE_WR(instance, DMA_CDNE_CDNE(channel));
bogdanm 82:6473597d706e 650 }
bogdanm 82:6473597d706e 651
bogdanm 82:6473597d706e 652 /*!
bogdanm 82:6473597d706e 653 * @brief Starts an eDMA channel manually.
bogdanm 82:6473597d706e 654 *
bogdanm 82:6473597d706e 655 * @param instance eDMA module
bogdanm 82:6473597d706e 656 * @param channel eDMA channel
bogdanm 82:6473597d706e 657 */
bogdanm 82:6473597d706e 658 static inline void edma_hal_trigger_start_bit(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 659 {
bogdanm 82:6473597d706e 660 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 661 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 662 HW_DMA_SSRT_WR(instance, DMA_SSRT_SSRT(channel));
bogdanm 82:6473597d706e 663 }
bogdanm 82:6473597d706e 664
bogdanm 82:6473597d706e 665 /*! * @brief Clears an error status for the eDMA channel.
bogdanm 82:6473597d706e 666 *
bogdanm 82:6473597d706e 667 * @param instance eDMA module
bogdanm 82:6473597d706e 668 * @param channel eDMA channel
bogdanm 82:6473597d706e 669 */
bogdanm 82:6473597d706e 670 static inline void edma_hal_clear_error_status(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 671 {
bogdanm 82:6473597d706e 672 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 673 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 674 HW_DMA_CERR_WR(instance, DMA_CERR_CERR(channel));
bogdanm 82:6473597d706e 675 }
bogdanm 82:6473597d706e 676
bogdanm 82:6473597d706e 677 /*!
bogdanm 82:6473597d706e 678 * @brief Clears an interrupt request for the eDMA channel.
bogdanm 82:6473597d706e 679 *
bogdanm 82:6473597d706e 680 * @param instance eDMA module
bogdanm 82:6473597d706e 681 * @param channel eDMA channel
bogdanm 82:6473597d706e 682 */
bogdanm 82:6473597d706e 683 static inline void edma_hal_clear_interrupt_request(uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 684 {
bogdanm 82:6473597d706e 685 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 686 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 687 HW_DMA_CINT_WR(instance, DMA_CINT_CINT(channel));
bogdanm 82:6473597d706e 688 }
bogdanm 82:6473597d706e 689
bogdanm 82:6473597d706e 690 #if (FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
bogdanm 82:6473597d706e 691 /*!
bogdanm 82:6473597d706e 692 * @brief Enables/Disables an asynchronous request in stop mode.
bogdanm 82:6473597d706e 693 *
bogdanm 82:6473597d706e 694 * @param instance eDMA module
bogdanm 82:6473597d706e 695 * @param channel eDMA channel
bogdanm 82:6473597d706e 696 */
bogdanm 82:6473597d706e 697 static inline void edma_hal_set_asynchronous_request_in_stop_mode(
bogdanm 82:6473597d706e 698 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 699 {
bogdanm 82:6473597d706e 700 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 701 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 702 if(isEnabled)
bogdanm 82:6473597d706e 703 {
bogdanm 82:6473597d706e 704 HW_DMA_EARS_SET(instance, 1U << channel);
bogdanm 82:6473597d706e 705 }
bogdanm 82:6473597d706e 706 else
bogdanm 82:6473597d706e 707 {
bogdanm 82:6473597d706e 708 HW_DMA_EARS_CLR(instance, 1U << channel);
bogdanm 82:6473597d706e 709 }
bogdanm 82:6473597d706e 710 }
bogdanm 82:6473597d706e 711 #endif
bogdanm 82:6473597d706e 712
bogdanm 82:6473597d706e 713 /*!
bogdanm 82:6473597d706e 714 * @brief Configures the preempt feature for an eDMA channel.
bogdanm 82:6473597d706e 715 *
bogdanm 82:6473597d706e 716 * If it is disabled, the DMA channel can't suspend a lower priority channel.
bogdanm 82:6473597d706e 717 *
bogdanm 82:6473597d706e 718 * @param instance eDMA module
bogdanm 82:6473597d706e 719 * @param channel eDMA channel
bogdanm 82:6473597d706e 720 * @param preempt configuration mode for preempt
bogdanm 82:6473597d706e 721 */
bogdanm 82:6473597d706e 722 static inline void edma_hal_set_channel_preemp_ability(
bogdanm 82:6473597d706e 723 uint32_t instance, uint32_t channel, bool isDisabled)
bogdanm 82:6473597d706e 724 {
bogdanm 82:6473597d706e 725 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 726 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 727 BW_DMA_DCHPRIn_DPA(instance, HW_DMA_DCHPRIn_CHANNEL(channel), isDisabled);
bogdanm 82:6473597d706e 728 }
bogdanm 82:6473597d706e 729
bogdanm 82:6473597d706e 730 /*!
bogdanm 82:6473597d706e 731 * @brief Configures the preempt feature for the eDMA channel.
bogdanm 82:6473597d706e 732 *
bogdanm 82:6473597d706e 733 * If enabled, channel can be temporarily suspended by a higher priority channel.
bogdanm 82:6473597d706e 734 *
bogdanm 82:6473597d706e 735 * @param instance eDMA module
bogdanm 82:6473597d706e 736 * @param channel eDMA channel
bogdanm 82:6473597d706e 737 * @param preempt configuration mode for preempt
bogdanm 82:6473597d706e 738 */
bogdanm 82:6473597d706e 739 static inline void edma_hal_set_channel_preemption_ability(uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 740 {
bogdanm 82:6473597d706e 741 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 742 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 743 BW_DMA_DCHPRIn_ECP(instance, HW_DMA_DCHPRIn_CHANNEL(channel), isEnabled);
bogdanm 82:6473597d706e 744 }
bogdanm 82:6473597d706e 745
bogdanm 82:6473597d706e 746 /*!
bogdanm 82:6473597d706e 747 * @brief Configures the eDMA channel priority.
bogdanm 82:6473597d706e 748 *
bogdanm 82:6473597d706e 749 * @param instance eDMA module
bogdanm 82:6473597d706e 750 * @param channel eDMA channel
bogdanm 82:6473597d706e 751 * @param priority Priority of the DMA channel. Different channels should have different priority inside a
bogdanm 82:6473597d706e 752 * group.
bogdanm 82:6473597d706e 753 */
bogdanm 82:6473597d706e 754 static inline void edma_hal_set_channel_priority(
bogdanm 82:6473597d706e 755 uint32_t instance, uint32_t channel, uint32_t priority)
bogdanm 82:6473597d706e 756 {
bogdanm 82:6473597d706e 757 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 758 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 759
bogdanm 82:6473597d706e 760 BW_DMA_DCHPRIn_CHPRI(instance, HW_DMA_DCHPRIn_CHANNEL(channel), priority);
bogdanm 82:6473597d706e 761 }
bogdanm 82:6473597d706e 762
bogdanm 82:6473597d706e 763 /* @} */
bogdanm 82:6473597d706e 764
bogdanm 82:6473597d706e 765 /*!
bogdanm 82:6473597d706e 766 * @name eDMA HAL hardware TCD configuration
bogdanm 82:6473597d706e 767 * @{
bogdanm 82:6473597d706e 768 */
bogdanm 82:6473597d706e 769
bogdanm 82:6473597d706e 770 /*!
bogdanm 82:6473597d706e 771 * @brief Configures the source address for the hardware TCD.
bogdanm 82:6473597d706e 772 *
bogdanm 82:6473597d706e 773 * @param instance eDMA module
bogdanm 82:6473597d706e 774 * @param channel eDMA channel
bogdanm 82:6473597d706e 775 * @param address memory address pointing to the source data
bogdanm 82:6473597d706e 776 */
bogdanm 82:6473597d706e 777 static inline void edma_hal_htcd_configure_source_address(
bogdanm 82:6473597d706e 778 uint32_t instance, uint32_t channel, uint32_t address)
bogdanm 82:6473597d706e 779 {
bogdanm 82:6473597d706e 780 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 781 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 782 BW_DMA_TCDn_SADDR_SADDR(instance, channel, address);
bogdanm 82:6473597d706e 783 }
bogdanm 82:6473597d706e 784
bogdanm 82:6473597d706e 785 /*!
bogdanm 82:6473597d706e 786 * @brief Configures the source address signed offset for the hardware TCD.
bogdanm 82:6473597d706e 787 *
bogdanm 82:6473597d706e 788 * Sign-extended offset applied to the current source address to form the next-state value as each
bogdanm 82:6473597d706e 789 * source read is complete.
bogdanm 82:6473597d706e 790 *
bogdanm 82:6473597d706e 791 * @param instance eDMA module
bogdanm 82:6473597d706e 792 * @param channel eDMA channel
bogdanm 82:6473597d706e 793 * @param offset signed-offset
bogdanm 82:6473597d706e 794 */
bogdanm 82:6473597d706e 795 static inline void edma_hal_htcd_configure_source_offset(
bogdanm 82:6473597d706e 796 uint32_t instance, uint32_t channel, int16_t offset)
bogdanm 82:6473597d706e 797 {
bogdanm 82:6473597d706e 798 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 799 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 800 BW_DMA_TCDn_SOFF_SOFF(instance, channel, offset);
bogdanm 82:6473597d706e 801 }
bogdanm 82:6473597d706e 802
bogdanm 82:6473597d706e 803 /*!
bogdanm 82:6473597d706e 804 * @brief Configures the source modulo for the hardware TCD.
bogdanm 82:6473597d706e 805 *
bogdanm 82:6473597d706e 806 * The value defines a specific address range specified as the value after the SADDR + SOFF
bogdanm 82:6473597d706e 807 * calculation is performed on the original register value. Setting this field provides the ability
bogdanm 82:6473597d706e 808 * to implement a circular data. For data queues requiring power-of-2 size bytes, the
bogdanm 82:6473597d706e 809 * queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate
bogdanm 82:6473597d706e 810 * value for the queue, freezing the desired number of upper address bits. The value programmed into
bogdanm 82:6473597d706e 811 * this field specifies the number of the lower address bits allowed to change. For a circular queue
bogdanm 82:6473597d706e 812 * application, the SOFF is typically set to the transfer size to implement post-increment addressing
bogdanm 82:6473597d706e 813 * with SMOD function restricting the addresses to a 0-modulo-size range.
bogdanm 82:6473597d706e 814 *
bogdanm 82:6473597d706e 815 * @param instance eDMA module
bogdanm 82:6473597d706e 816 * @param channel eDMA channel
bogdanm 82:6473597d706e 817 * @param modulo enum type for an allowed modulo
bogdanm 82:6473597d706e 818 */
bogdanm 82:6473597d706e 819 static inline void edma_hal_htcd_configure_source_modulo(
bogdanm 82:6473597d706e 820 uint32_t instance, uint32_t channel, edma_modulo_t modulo)
bogdanm 82:6473597d706e 821 {
bogdanm 82:6473597d706e 822 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 823 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 824 BW_DMA_TCDn_ATTR_SMOD(instance, channel, modulo);
bogdanm 82:6473597d706e 825 }
bogdanm 82:6473597d706e 826
bogdanm 82:6473597d706e 827 /*!
bogdanm 82:6473597d706e 828 * @brief Configures the source data transfersize for the hardware TCD.
bogdanm 82:6473597d706e 829 *
bogdanm 82:6473597d706e 830 * @param instance eDMA module
bogdanm 82:6473597d706e 831 * @param channel eDMA channel
bogdanm 82:6473597d706e 832 * @param size enum type for transfer size
bogdanm 82:6473597d706e 833 */
bogdanm 82:6473597d706e 834 static inline void edma_hal_htcd_configure_source_transfersize(
bogdanm 82:6473597d706e 835 uint32_t instance, uint32_t channel, edma_transfer_size_t size)
bogdanm 82:6473597d706e 836 {
bogdanm 82:6473597d706e 837 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 838 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 839 BW_DMA_TCDn_ATTR_SSIZE(instance, channel, size);
bogdanm 82:6473597d706e 840 }
bogdanm 82:6473597d706e 841
bogdanm 82:6473597d706e 842 /*!
bogdanm 82:6473597d706e 843 * @brief Configures the destination modulo for the hardware TCD.
bogdanm 82:6473597d706e 844 *
bogdanm 82:6473597d706e 845 * The value defines a specific address range as the value after the DADDR + DOFF
bogdanm 82:6473597d706e 846 * calculation is performed on the original register value. Setting this field provides the ability
bogdanm 82:6473597d706e 847 * to implement a circular data. For data queues requiring power-of-2 size bytes, the
bogdanm 82:6473597d706e 848 * queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate
bogdanm 82:6473597d706e 849 * value for the queue, freezing the desired number of upper address bits. The value programmed into
bogdanm 82:6473597d706e 850 * this field specifies the number of lower address bits allowed to change. For a circular queue
bogdanm 82:6473597d706e 851 * application, the SOFF is typically set to the transfer size to implement post-increment addressing
bogdanm 82:6473597d706e 852 * with DMOD function restricting the addresses to a 0-modulo-size range.
bogdanm 82:6473597d706e 853 *
bogdanm 82:6473597d706e 854 * @param instance eDMA module
bogdanm 82:6473597d706e 855 * @param channel eDMA channel
bogdanm 82:6473597d706e 856 * @param modulo enum type for an allowed modulo
bogdanm 82:6473597d706e 857 */
bogdanm 82:6473597d706e 858 static inline void edma_hal_htcd_configure_dest_modulo(
bogdanm 82:6473597d706e 859 uint32_t instance, uint32_t channel, edma_modulo_t modulo)
bogdanm 82:6473597d706e 860 {
bogdanm 82:6473597d706e 861 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 862 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 863 BW_DMA_TCDn_ATTR_DMOD(instance, channel, modulo);
bogdanm 82:6473597d706e 864 }
bogdanm 82:6473597d706e 865
bogdanm 82:6473597d706e 866 /*!
bogdanm 82:6473597d706e 867 * @brief Configures the destination data transfersize for the hardware TCD.
bogdanm 82:6473597d706e 868 *
bogdanm 82:6473597d706e 869 * @param instance eDMA module
bogdanm 82:6473597d706e 870 * @param channel eDMA channel
bogdanm 82:6473597d706e 871 * @param size enum type for the transfer size
bogdanm 82:6473597d706e 872 */
bogdanm 82:6473597d706e 873 static inline void edma_hal_htcd_configure_dest_transfersize(
bogdanm 82:6473597d706e 874 uint32_t instance, uint32_t channel, edma_transfer_size_t size)
bogdanm 82:6473597d706e 875 {
bogdanm 82:6473597d706e 876 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 877 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 878 BW_DMA_TCDn_ATTR_DSIZE(instance, channel, size);
bogdanm 82:6473597d706e 879 }
bogdanm 82:6473597d706e 880
bogdanm 82:6473597d706e 881 /*!
bogdanm 82:6473597d706e 882 * @brief Configures the nbytes if minor loop mapping is disabled for the hardware TCD.
bogdanm 82:6473597d706e 883 *
bogdanm 82:6473597d706e 884 * @param instance eDMA module
bogdanm 82:6473597d706e 885 * @param channel eDMA channel
bogdanm 82:6473597d706e 886 * @param nbytes Number of bytes to be transferred in each service request of the channel
bogdanm 82:6473597d706e 887 */
bogdanm 82:6473597d706e 888 static inline void edma_hal_htcd_configure_nbytes_minorloop_disabled(
bogdanm 82:6473597d706e 889 uint32_t instance, uint32_t channel, uint32_t nbytes)
bogdanm 82:6473597d706e 890 {
bogdanm 82:6473597d706e 891 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 892 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 893 BW_DMA_TCDn_NBYTES_MLNO_NBYTES(instance, channel, nbytes);
bogdanm 82:6473597d706e 894 }
bogdanm 82:6473597d706e 895
bogdanm 82:6473597d706e 896 /*!
bogdanm 82:6473597d706e 897 * @brief Configures the nbytes if the minor loop mapping is enabled and offset is disabled for the hardware TCD.
bogdanm 82:6473597d706e 898 *
bogdanm 82:6473597d706e 899 * @param instance eDMA module
bogdanm 82:6473597d706e 900 * @param channel eDMA channel
bogdanm 82:6473597d706e 901 * @param nbytes Number of bytes to be transferred in each service request of the channel
bogdanm 82:6473597d706e 902 */
bogdanm 82:6473597d706e 903 static inline void edma_hal_htcd_configure_nbytes_minorloop_enabled_offset_disabled(
bogdanm 82:6473597d706e 904 uint32_t instance, uint32_t channel, uint32_t nbytes)
bogdanm 82:6473597d706e 905 {
bogdanm 82:6473597d706e 906 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 907 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 908 BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(instance, channel, nbytes);
bogdanm 82:6473597d706e 909 }
bogdanm 82:6473597d706e 910
bogdanm 82:6473597d706e 911 /*!
bogdanm 82:6473597d706e 912 * @brief Configures the nbytes if the minor loop mapping is enabled and offset is enabled for the hardware TCD.
bogdanm 82:6473597d706e 913 *
bogdanm 82:6473597d706e 914 * @param instance eDMA module
bogdanm 82:6473597d706e 915 * @param channel eDMA channel
bogdanm 82:6473597d706e 916 * @param nbytes Number of bytes to be transferred in each service request of the channel
bogdanm 82:6473597d706e 917 */
bogdanm 82:6473597d706e 918 static inline void edma_hal_htcd_configure_nbytes_minorloop_enabled_offset_enabled(
bogdanm 82:6473597d706e 919 uint32_t instance, uint32_t channel, uint32_t nbytes)
bogdanm 82:6473597d706e 920 {
bogdanm 82:6473597d706e 921 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 922 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 923 BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(instance, channel, nbytes);
bogdanm 82:6473597d706e 924 }
bogdanm 82:6473597d706e 925
bogdanm 82:6473597d706e 926 /*!
bogdanm 82:6473597d706e 927 * @brief Gets the nbytes configuration data.
bogdanm 82:6473597d706e 928 *
bogdanm 82:6473597d706e 929 * This function decides whether the minor loop mapping is enabled or whether the source/dest
bogdanm 82:6473597d706e 930 * minor loop mapping is enabled. Then, the nbytes are returned accordingly.
bogdanm 82:6473597d706e 931 *
bogdanm 82:6473597d706e 932 * @param instance eDMA module
bogdanm 82:6473597d706e 933 * @param channel eDMA channel
bogdanm 82:6473597d706e 934 * @return nbytes configuration
bogdanm 82:6473597d706e 935 */
bogdanm 82:6473597d706e 936 uint32_t edma_hal_htcd_get_nbytes_configuration(uint32_t instance, uint32_t channel);
bogdanm 82:6473597d706e 937
bogdanm 82:6473597d706e 938
bogdanm 82:6473597d706e 939 /*!
bogdanm 82:6473597d706e 940 * @brief Configures the minorloop offset for the hardware TCD.
bogdanm 82:6473597d706e 941 *
bogdanm 82:6473597d706e 942 * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled,
bogdanm 82:6473597d706e 943 * offset is not configured.
bogdanm 82:6473597d706e 944 *
bogdanm 82:6473597d706e 945 * @param instance eDMA module
bogdanm 82:6473597d706e 946 * @param channel eDMA channel
bogdanm 82:6473597d706e 947 * @param config Configuration data structure for the minorloop offset
bogdanm 82:6473597d706e 948 */
bogdanm 82:6473597d706e 949 static inline void edma_hal_htcd_configure_minorloop_offset(
bogdanm 82:6473597d706e 950 uint32_t instance, uint32_t channel, edma_minorloop_offset_config_t config)
bogdanm 82:6473597d706e 951 {
bogdanm 82:6473597d706e 952 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 953 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 954 BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(instance, channel, config.isEnableSourceMinorloop);
bogdanm 82:6473597d706e 955 BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(instance, channel, config.isEnableDestMinorloop);
bogdanm 82:6473597d706e 956 if ((config.isEnableSourceMinorloop == true) || (config.isEnableDestMinorloop == true))
bogdanm 82:6473597d706e 957 {
bogdanm 82:6473597d706e 958 BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(instance, channel, config.offset);
bogdanm 82:6473597d706e 959 }
bogdanm 82:6473597d706e 960 }
bogdanm 82:6473597d706e 961
bogdanm 82:6473597d706e 962 /*!
bogdanm 82:6473597d706e 963 * @brief Configures the last source address adjustment for the hardware TCD.
bogdanm 82:6473597d706e 964 *
bogdanm 82:6473597d706e 965 * Adjustment value added to the source address at the completion of the major iteration count. This
bogdanm 82:6473597d706e 966 * value can be applied to restore the source address to the initial value, or adjust the address to
bogdanm 82:6473597d706e 967 * reference the next data structure.
bogdanm 82:6473597d706e 968 *
bogdanm 82:6473597d706e 969 * @param instance eDMA module
bogdanm 82:6473597d706e 970 * @param channel eDMA channel
bogdanm 82:6473597d706e 971 * @param size adjustment value
bogdanm 82:6473597d706e 972 */
bogdanm 82:6473597d706e 973 static inline void edma_hal_htcd_configure_source_last_adjustment(
bogdanm 82:6473597d706e 974 uint32_t instance, uint32_t channel, int32_t size)
bogdanm 82:6473597d706e 975 {
bogdanm 82:6473597d706e 976 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 977 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 978 BW_DMA_TCDn_SLAST_SLAST(instance, channel, size);
bogdanm 82:6473597d706e 979 }
bogdanm 82:6473597d706e 980
bogdanm 82:6473597d706e 981 /*!
bogdanm 82:6473597d706e 982 * @brief Configures the destination address for the hardware TCD.
bogdanm 82:6473597d706e 983 *
bogdanm 82:6473597d706e 984 * @param instance eDMA module
bogdanm 82:6473597d706e 985 * @param channel eDMA channel
bogdanm 82:6473597d706e 986 * @param address memory address pointing to destination data
bogdanm 82:6473597d706e 987 */
bogdanm 82:6473597d706e 988 static inline void edma_hal_htcd_configure_dest_address(
bogdanm 82:6473597d706e 989 uint32_t instance, uint32_t channel, uint32_t address)
bogdanm 82:6473597d706e 990 {
bogdanm 82:6473597d706e 991 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 992 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 993 BW_DMA_TCDn_DADDR_DADDR(instance, channel, address);
bogdanm 82:6473597d706e 994 }
bogdanm 82:6473597d706e 995
bogdanm 82:6473597d706e 996 /*!
bogdanm 82:6473597d706e 997 * @brief Configures the destination address signed offset for the hardware TCD.
bogdanm 82:6473597d706e 998 *
bogdanm 82:6473597d706e 999 * Sign-extended offset applied to the current source address to form the next-state value as each
bogdanm 82:6473597d706e 1000 * destination write is complete.
bogdanm 82:6473597d706e 1001 *
bogdanm 82:6473597d706e 1002 * @param instance eDMA module
bogdanm 82:6473597d706e 1003 * @param channel eDMA channel
bogdanm 82:6473597d706e 1004 * @param offset signed-offset
bogdanm 82:6473597d706e 1005 */
bogdanm 82:6473597d706e 1006 static inline void edma_hal_htcd_configure_dest_offset(
bogdanm 82:6473597d706e 1007 uint32_t instance, uint32_t channel, int16_t offset)
bogdanm 82:6473597d706e 1008 {
bogdanm 82:6473597d706e 1009 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1010 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1011 BW_DMA_TCDn_DOFF_DOFF(instance, channel, offset);
bogdanm 82:6473597d706e 1012 }
bogdanm 82:6473597d706e 1013
bogdanm 82:6473597d706e 1014 /*!
bogdanm 82:6473597d706e 1015 * @brief Configures the last source address adjustment or the memory address for the next transfer
bogdanm 82:6473597d706e 1016 * control for the hardware TCD.
bogdanm 82:6473597d706e 1017 *
bogdanm 82:6473597d706e 1018 * If a scatter/gather feature is enabled (edma_hal_htcd_set_scatter_gather_process()):
bogdanm 82:6473597d706e 1019 *
bogdanm 82:6473597d706e 1020 * This address points to the beginning of a 0-modulo-32 byte region containing the next transfer
bogdanm 82:6473597d706e 1021 * control descriptor to be loaded into this channel. The channel reload is performed as the major
bogdanm 82:6473597d706e 1022 * iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, a
bogdanm 82:6473597d706e 1023 * configuration error is reported.
bogdanm 82:6473597d706e 1024 *
bogdanm 82:6473597d706e 1025 * else:
bogdanm 82:6473597d706e 1026 *
bogdanm 82:6473597d706e 1027 * An adjustment value added to the source address at the completion of the major iteration count. This
bogdanm 82:6473597d706e 1028 * value can be applied to restore the source address to the initial value, or adjust the address to
bogdanm 82:6473597d706e 1029 * reference the next data structure.
bogdanm 82:6473597d706e 1030 *
bogdanm 82:6473597d706e 1031 * @param instance eDMA module
bogdanm 82:6473597d706e 1032 * @param channel eDMA channel
bogdanm 82:6473597d706e 1033 * @param size adjustment value
bogdanm 82:6473597d706e 1034 */
bogdanm 82:6473597d706e 1035 static inline void edma_hal_htcd_configure_dest_last_adjustment_or_scatter_address(
bogdanm 82:6473597d706e 1036 uint32_t instance, uint32_t channel, uint32_t address)
bogdanm 82:6473597d706e 1037 {
bogdanm 82:6473597d706e 1038 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1039 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1040 BW_DMA_TCDn_DLASTSGA_DLASTSGA(instance, channel, address);
bogdanm 82:6473597d706e 1041 }
bogdanm 82:6473597d706e 1042
bogdanm 82:6473597d706e 1043 /*!
bogdanm 82:6473597d706e 1044 * @brief Configures the bandwidth for the hardware TCD.
bogdanm 82:6473597d706e 1045 *
bogdanm 82:6473597d706e 1046 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
bogdanm 82:6473597d706e 1047 * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
bogdanm 82:6473597d706e 1048 * This field forces the eDMA to stall after the completion of each read/write access to control the
bogdanm 82:6473597d706e 1049 * bus request bandwidth seen by the crossbar switch.
bogdanm 82:6473597d706e 1050 *
bogdanm 82:6473597d706e 1051 * @param instance eDMA module
bogdanm 82:6473597d706e 1052 * @param channel eDMA channel
bogdanm 82:6473597d706e 1053 * @param bandwidth enum type for bandwidth control
bogdanm 82:6473597d706e 1054 */
bogdanm 82:6473597d706e 1055 static inline void edma_hal_htcd_configure_bandwidth(
bogdanm 82:6473597d706e 1056 uint32_t instance, uint32_t channel, edma_bandwidth_configuration_t bandwidth)
bogdanm 82:6473597d706e 1057 {
bogdanm 82:6473597d706e 1058 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1059 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1060 BW_DMA_TCDn_CSR_BWC(instance, channel, bandwidth);
bogdanm 82:6473597d706e 1061 }
bogdanm 82:6473597d706e 1062
bogdanm 82:6473597d706e 1063 /*!
bogdanm 82:6473597d706e 1064 * @brief Configures the major link channel number for the hardware TCD.
bogdanm 82:6473597d706e 1065 *
bogdanm 82:6473597d706e 1066 * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
bogdanm 82:6473597d706e 1067 * channel service request at the channel defined by these six bits by setting that channel start
bogdanm 82:6473597d706e 1068 * bits.
bogdanm 82:6473597d706e 1069 *
bogdanm 82:6473597d706e 1070 * @param instance eDMA module
bogdanm 82:6473597d706e 1071 * @param channel eDMA channel
bogdanm 82:6473597d706e 1072 * @param majorchannel channel number for major link
bogdanm 82:6473597d706e 1073 */
bogdanm 82:6473597d706e 1074 static inline void edma_hal_htcd_configure_majorlink_channel(
bogdanm 82:6473597d706e 1075 uint32_t instance, uint32_t channel, uint32_t majorchannel)
bogdanm 82:6473597d706e 1076 {
bogdanm 82:6473597d706e 1077 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1078 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1079 BW_DMA_TCDn_CSR_MAJORLINKCH(instance, channel, majorchannel);
bogdanm 82:6473597d706e 1080 }
bogdanm 82:6473597d706e 1081
bogdanm 82:6473597d706e 1082 /*!
bogdanm 82:6473597d706e 1083 * @brief Gets the major link channel for the hardware TCD.
bogdanm 82:6473597d706e 1084 *
bogdanm 82:6473597d706e 1085 * @param instance eDMA module
bogdanm 82:6473597d706e 1086 * @param channel eDMA channel
bogdanm 82:6473597d706e 1087 * @return major link channel number
bogdanm 82:6473597d706e 1088 */
bogdanm 82:6473597d706e 1089 static inline uint32_t edma_hal_htcd_get_majorlink_channel(
bogdanm 82:6473597d706e 1090 uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 1091 {
bogdanm 82:6473597d706e 1092 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1093 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1094 return BR_DMA_TCDn_CSR_MAJORLINKCH(instance, channel);
bogdanm 82:6473597d706e 1095 }
bogdanm 82:6473597d706e 1096
bogdanm 82:6473597d706e 1097 /*!
bogdanm 82:6473597d706e 1098 * @brief Enables/Disables the major link channel feature for the hardware TCD.
bogdanm 82:6473597d706e 1099 *
bogdanm 82:6473597d706e 1100 * @param instance eDMA module
bogdanm 82:6473597d706e 1101 * @param channel eDMA channel
bogdanm 82:6473597d706e 1102 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1103 */
bogdanm 82:6473597d706e 1104 static inline void edma_hal_htcd_set_majorlink(uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1105 {
bogdanm 82:6473597d706e 1106 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1107 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1108 BW_DMA_TCDn_CSR_MAJORELINK(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1109 }
bogdanm 82:6473597d706e 1110
bogdanm 82:6473597d706e 1111 /*!
bogdanm 82:6473597d706e 1112 * @brief Enables/Disables the scatter/gather feature for the hardware TCD.
bogdanm 82:6473597d706e 1113 *
bogdanm 82:6473597d706e 1114 * @param instance eDMA module
bogdanm 82:6473597d706e 1115 * @param channel eDMA channel
bogdanm 82:6473597d706e 1116 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1117 */
bogdanm 82:6473597d706e 1118 static inline void edma_hal_htcd_set_scatter_gather_process(
bogdanm 82:6473597d706e 1119 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1120 {
bogdanm 82:6473597d706e 1121 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1122 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1123 BW_DMA_TCDn_CSR_ESG(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1124 }
bogdanm 82:6473597d706e 1125
bogdanm 82:6473597d706e 1126 /*!
bogdanm 82:6473597d706e 1127 * @brief Checks whether the scatter/gather feature is enabled for the hardware TCD.
bogdanm 82:6473597d706e 1128 *
bogdanm 82:6473597d706e 1129 * @param instance eDMA module
bogdanm 82:6473597d706e 1130 * @param channel eDMA channel
bogdanm 82:6473597d706e 1131 * @return True stand for enabled. False stands for disabled.
bogdanm 82:6473597d706e 1132 */
bogdanm 82:6473597d706e 1133 static inline bool edma_hal_htcd_is_gather_scatter_enabled(
bogdanm 82:6473597d706e 1134 uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 1135 {
bogdanm 82:6473597d706e 1136 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1137 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1138 return BR_DMA_TCDn_CSR_ESG(instance, channel);
bogdanm 82:6473597d706e 1139
bogdanm 82:6473597d706e 1140 }
bogdanm 82:6473597d706e 1141
bogdanm 82:6473597d706e 1142 /*!
bogdanm 82:6473597d706e 1143 * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD.
bogdanm 82:6473597d706e 1144 *
bogdanm 82:6473597d706e 1145 * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
bogdanm 82:6473597d706e 1146 * current major iteration count reaches zero.
bogdanm 82:6473597d706e 1147 *
bogdanm 82:6473597d706e 1148 * @param instance eDMA module
bogdanm 82:6473597d706e 1149 * @param channel eDMA channel
bogdanm 82:6473597d706e 1150 * @param isDisabled Disable/Enable.
bogdanm 82:6473597d706e 1151 */
bogdanm 82:6473597d706e 1152 static inline void edma_hal_htcd_set_disable_dma_request_after_tcd_done(
bogdanm 82:6473597d706e 1153 uint32_t instance, uint32_t channel, bool isDisabled)
bogdanm 82:6473597d706e 1154 {
bogdanm 82:6473597d706e 1155 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1156 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1157 BW_DMA_TCDn_CSR_DREQ(instance, channel, isDisabled);
bogdanm 82:6473597d706e 1158 }
bogdanm 82:6473597d706e 1159
bogdanm 82:6473597d706e 1160 /*!
bogdanm 82:6473597d706e 1161 * @brief Enables/Disables the half complete interrupt for the hardware TCD.
bogdanm 82:6473597d706e 1162 *
bogdanm 82:6473597d706e 1163 * If set, the channel generates an interrupt request by setting the appropriate bit in the
bogdanm 82:6473597d706e 1164 * interrupt register when the current major iteration count reaches the halfway point. Specifically,
bogdanm 82:6473597d706e 1165 * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point
bogdanm 82:6473597d706e 1166 * interrupt request is provided to support the double-buffered schemes or other types of data movement
bogdanm 82:6473597d706e 1167 * where the processor needs an early indication of the transfer's process.
bogdanm 82:6473597d706e 1168 *
bogdanm 82:6473597d706e 1169 * @param instance eDMA module
bogdanm 82:6473597d706e 1170 * @param channel eDMA channel
bogdanm 82:6473597d706e 1171 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1172 */
bogdanm 82:6473597d706e 1173 static inline void edma_hal_htcd_set_half_complete_interrupt(
bogdanm 82:6473597d706e 1174 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1175 {
bogdanm 82:6473597d706e 1176 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1177 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1178 BW_DMA_TCDn_CSR_INTHALF(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1179 }
bogdanm 82:6473597d706e 1180
bogdanm 82:6473597d706e 1181 /*!
bogdanm 82:6473597d706e 1182 * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD.
bogdanm 82:6473597d706e 1183 *
bogdanm 82:6473597d706e 1184 * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
bogdanm 82:6473597d706e 1185 * interrupt register when the current major iteration count reaches zero.
bogdanm 82:6473597d706e 1186 *
bogdanm 82:6473597d706e 1187 * @param instance eDMA module
bogdanm 82:6473597d706e 1188 * @param channel eDMA channel
bogdanm 82:6473597d706e 1189 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1190 */
bogdanm 82:6473597d706e 1191 static inline void edma_hal_htcd_set_complete_interrupt(
bogdanm 82:6473597d706e 1192 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1193 {
bogdanm 82:6473597d706e 1194 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1195 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1196 BW_DMA_TCDn_CSR_INTMAJOR(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1197 }
bogdanm 82:6473597d706e 1198
bogdanm 82:6473597d706e 1199 /*!
bogdanm 82:6473597d706e 1200 * @brief Triggers the start bits for the hardware TCD.
bogdanm 82:6473597d706e 1201 *
bogdanm 82:6473597d706e 1202 * The eDMA hardware automatically clears this flag after the channel begins execution.
bogdanm 82:6473597d706e 1203 *
bogdanm 82:6473597d706e 1204 * @param instance eDMA module
bogdanm 82:6473597d706e 1205 * @param channel eDMA channel
bogdanm 82:6473597d706e 1206 */
bogdanm 82:6473597d706e 1207 static inline void edma_hal_htcd_trigger_channel_start(
bogdanm 82:6473597d706e 1208 uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 1209 {
bogdanm 82:6473597d706e 1210 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1211 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1212 BW_DMA_TCDn_CSR_START(instance, channel, 1);
bogdanm 82:6473597d706e 1213 }
bogdanm 82:6473597d706e 1214
bogdanm 82:6473597d706e 1215 /*!
bogdanm 82:6473597d706e 1216 * @brief Checks whether the channel is running for the hardware TCD.
bogdanm 82:6473597d706e 1217 *
bogdanm 82:6473597d706e 1218 * @param instance eDMA module
bogdanm 82:6473597d706e 1219 * @param channel eDMA channel
bogdanm 82:6473597d706e 1220 * @return True stands for running. False stands for not.
bogdanm 82:6473597d706e 1221 */
bogdanm 82:6473597d706e 1222 static inline bool edma_hal_htcd_is_channel_active(
bogdanm 82:6473597d706e 1223 uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 1224 {
bogdanm 82:6473597d706e 1225 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1226 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1227 return BR_DMA_TCDn_CSR_ACTIVE(instance, channel);
bogdanm 82:6473597d706e 1228 }
bogdanm 82:6473597d706e 1229
bogdanm 82:6473597d706e 1230 /*!
bogdanm 82:6473597d706e 1231 * @brief Checks whether the major loop is exhausted for the hardware TCD.
bogdanm 82:6473597d706e 1232 *
bogdanm 82:6473597d706e 1233 * @param instance eDMA module
bogdanm 82:6473597d706e 1234 * @param channel eDMA channel
bogdanm 82:6473597d706e 1235 * @return True stands for running. False stands for not.
bogdanm 82:6473597d706e 1236 */
bogdanm 82:6473597d706e 1237 static inline bool edma_hal_htcd_is_channel_done(
bogdanm 82:6473597d706e 1238 uint32_t instance, uint32_t channel)
bogdanm 82:6473597d706e 1239 {
bogdanm 82:6473597d706e 1240 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1241 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1242 return BR_DMA_TCDn_CSR_DONE(instance, channel);
bogdanm 82:6473597d706e 1243 }
bogdanm 82:6473597d706e 1244
bogdanm 82:6473597d706e 1245 /*!
bogdanm 82:6473597d706e 1246 * @brief Enables/Disables the channel link after the minor loop for the hardware TCD.
bogdanm 82:6473597d706e 1247 *
bogdanm 82:6473597d706e 1248 * @param instance eDMA module
bogdanm 82:6473597d706e 1249 * @param channel eDMA channel
bogdanm 82:6473597d706e 1250 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1251 */
bogdanm 82:6473597d706e 1252 static inline void edma_hal_htcd_set_minor_link(
bogdanm 82:6473597d706e 1253 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1254 {
bogdanm 82:6473597d706e 1255 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1256 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1257 BW_DMA_TCDn_BITER_ELINKYES_ELINK(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1258 }
bogdanm 82:6473597d706e 1259
bogdanm 82:6473597d706e 1260 /*!
bogdanm 82:6473597d706e 1261 * @brief Enables/Disables the channel link after the minor loop in the current register for the hardware TCD.
bogdanm 82:6473597d706e 1262 *
bogdanm 82:6473597d706e 1263 * @param instance eDMA module
bogdanm 82:6473597d706e 1264 * @param channel eDMA channel
bogdanm 82:6473597d706e 1265 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1266 */
bogdanm 82:6473597d706e 1267 static inline void edma_hal_htcd_set_current_minor_link(
bogdanm 82:6473597d706e 1268 uint32_t instance, uint32_t channel, bool isEnabled)
bogdanm 82:6473597d706e 1269 {
bogdanm 82:6473597d706e 1270 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1271 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1272 BW_DMA_TCDn_CITER_ELINKYES_ELINK(instance, channel, isEnabled);
bogdanm 82:6473597d706e 1273 }
bogdanm 82:6473597d706e 1274
bogdanm 82:6473597d706e 1275 /*!
bogdanm 82:6473597d706e 1276 * @brief Configures the minor loop link channel for the hardware TCD.
bogdanm 82:6473597d706e 1277 *
bogdanm 82:6473597d706e 1278 * @param instance eDMA module
bogdanm 82:6473597d706e 1279 * @param channel eDMA channel
bogdanm 82:6473597d706e 1280 * @param minorchannel minor loop link channel
bogdanm 82:6473597d706e 1281 */
bogdanm 82:6473597d706e 1282 static inline void edma_hal_htcd_configure_minor_link_channel(
bogdanm 82:6473597d706e 1283 uint32_t instance, uint32_t channel, uint32_t minorchannel)
bogdanm 82:6473597d706e 1284 {
bogdanm 82:6473597d706e 1285 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1286 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1287 BW_DMA_TCDn_BITER_ELINKYES_LINKCH(instance, channel, minorchannel);
bogdanm 82:6473597d706e 1288 }
bogdanm 82:6473597d706e 1289
bogdanm 82:6473597d706e 1290 /*!
bogdanm 82:6473597d706e 1291 * @brief Configures the minor loop link channel in the current register for the hardware TCD.
bogdanm 82:6473597d706e 1292 *
bogdanm 82:6473597d706e 1293 * @param instance eDMA module
bogdanm 82:6473597d706e 1294 * @param channel eDMA channel
bogdanm 82:6473597d706e 1295 * @param minorchannel minor loop link channel
bogdanm 82:6473597d706e 1296 */
bogdanm 82:6473597d706e 1297 static inline void edma_hal_htcd_configure_current_minor_link_channel(
bogdanm 82:6473597d706e 1298 uint32_t instance, uint32_t channel, uint32_t minorchannel)
bogdanm 82:6473597d706e 1299 {
bogdanm 82:6473597d706e 1300 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1301 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1302 BW_DMA_TCDn_CITER_ELINKYES_LINKCH(instance, channel, minorchannel);
bogdanm 82:6473597d706e 1303 }
bogdanm 82:6473597d706e 1304
bogdanm 82:6473597d706e 1305 /*!
bogdanm 82:6473597d706e 1306 * @brief Configures the major count if the minor loop channel link is disabled for the hardware TCD.
bogdanm 82:6473597d706e 1307 *
bogdanm 82:6473597d706e 1308 * @param instance eDMA module
bogdanm 82:6473597d706e 1309 * @param channel eDMA channel
bogdanm 82:6473597d706e 1310 * @param count major loop count
bogdanm 82:6473597d706e 1311 */
bogdanm 82:6473597d706e 1312 static inline void edma_hal_htcd_configure_majorcount_minorlink_disabled(
bogdanm 82:6473597d706e 1313 uint32_t instance, uint32_t channel, uint32_t count)
bogdanm 82:6473597d706e 1314 {
bogdanm 82:6473597d706e 1315 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1316 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1317 BW_DMA_TCDn_BITER_ELINKNO_BITER(instance, channel, count);
bogdanm 82:6473597d706e 1318 }
bogdanm 82:6473597d706e 1319
bogdanm 82:6473597d706e 1320 /*!
bogdanm 82:6473597d706e 1321 * @brief Configures the current major count if the minor loop channel link is disabled for the hardware TCD.
bogdanm 82:6473597d706e 1322 *
bogdanm 82:6473597d706e 1323 * @param instance eDMA module
bogdanm 82:6473597d706e 1324 * @param channel eDMA channel
bogdanm 82:6473597d706e 1325 * @param count major loop count
bogdanm 82:6473597d706e 1326 */
bogdanm 82:6473597d706e 1327 static inline void edma_hal_htcd_configure_current_majorcount_minorlink_disabled(
bogdanm 82:6473597d706e 1328 uint32_t instance, uint32_t channel, uint32_t count)
bogdanm 82:6473597d706e 1329 {
bogdanm 82:6473597d706e 1330 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1331 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1332 BW_DMA_TCDn_CITER_ELINKNO_CITER(instance, channel, count);
bogdanm 82:6473597d706e 1333 }
bogdanm 82:6473597d706e 1334
bogdanm 82:6473597d706e 1335 /*!
bogdanm 82:6473597d706e 1336 * @brief Configures the major count if the minor loop channel link is enabled for the hardware TCD.
bogdanm 82:6473597d706e 1337 *
bogdanm 82:6473597d706e 1338 * @param instance eDMA module
bogdanm 82:6473597d706e 1339 * @param channel eDMA channel
bogdanm 82:6473597d706e 1340 * @param count major loop count
bogdanm 82:6473597d706e 1341 */
bogdanm 82:6473597d706e 1342 static inline void edma_hal_htcd_configure_majorcount_minorlink_enabled(
bogdanm 82:6473597d706e 1343 uint32_t instance, uint32_t channel, uint32_t count)
bogdanm 82:6473597d706e 1344 {
bogdanm 82:6473597d706e 1345 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1346 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1347 BW_DMA_TCDn_BITER_ELINKYES_BITER(instance, channel, count);
bogdanm 82:6473597d706e 1348 }
bogdanm 82:6473597d706e 1349
bogdanm 82:6473597d706e 1350 /*!
bogdanm 82:6473597d706e 1351 * @brief Configures the current major count if the minor loop channel link is enabled for the hardware TCD.
bogdanm 82:6473597d706e 1352 *
bogdanm 82:6473597d706e 1353 * @param instance eDMA module
bogdanm 82:6473597d706e 1354 * @param channel eDMA channel
bogdanm 82:6473597d706e 1355 * @param count major loop count
bogdanm 82:6473597d706e 1356 */
bogdanm 82:6473597d706e 1357 static inline void edma_hal_htcd_configure_current_majorcount_minorlink_enabled(
bogdanm 82:6473597d706e 1358 uint32_t instance, uint32_t channel, uint32_t count)
bogdanm 82:6473597d706e 1359 {
bogdanm 82:6473597d706e 1360 assert(instance < HW_DMA_INSTANCE_COUNT);
bogdanm 82:6473597d706e 1361 assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
bogdanm 82:6473597d706e 1362 BW_DMA_TCDn_CITER_ELINKYES_CITER(instance, channel, count);
bogdanm 82:6473597d706e 1363 }
bogdanm 82:6473597d706e 1364
bogdanm 82:6473597d706e 1365 /*!
bogdanm 82:6473597d706e 1366 * @brief Gets the current major loop count.
bogdanm 82:6473597d706e 1367 *
bogdanm 82:6473597d706e 1368 * @param instance eDMA module
bogdanm 82:6473597d706e 1369 * @param channel eDMA channel
bogdanm 82:6473597d706e 1370 * @return current major loop count
bogdanm 82:6473597d706e 1371 */
bogdanm 82:6473597d706e 1372 uint32_t edma_hal_htcd_get_current_major_count(uint32_t instance, uint32_t channel);
bogdanm 82:6473597d706e 1373
bogdanm 82:6473597d706e 1374 /*!
bogdanm 82:6473597d706e 1375 * @brief Gets the beginning major loop count.
bogdanm 82:6473597d706e 1376 *
bogdanm 82:6473597d706e 1377 * @param instance eDMA module
bogdanm 82:6473597d706e 1378 * @param channel eDMA channel
bogdanm 82:6473597d706e 1379 * @return begin major loop count
bogdanm 82:6473597d706e 1380 */
bogdanm 82:6473597d706e 1381 uint32_t edma_hal_htcd_get_begin_major_count(uint32_t instance, uint32_t channel);
bogdanm 82:6473597d706e 1382
bogdanm 82:6473597d706e 1383 /*!
bogdanm 82:6473597d706e 1384 * @brief Gets the bytes number not to be transferred for the hardware TCD.
bogdanm 82:6473597d706e 1385 *
bogdanm 82:6473597d706e 1386 * @param instance eDMA module
bogdanm 82:6473597d706e 1387 * @param channel eDMA channel
bogdanm 82:6473597d706e 1388 * @return data bytes to be transferred
bogdanm 82:6473597d706e 1389 */
bogdanm 82:6473597d706e 1390 uint32_t edma_hal_htcd_get_unfinished_bytes(uint32_t instance, uint32_t channel);
bogdanm 82:6473597d706e 1391
bogdanm 82:6473597d706e 1392 /*!
bogdanm 82:6473597d706e 1393 * @brief Gets the number of already transferred bytes for the hardware TCD.
bogdanm 82:6473597d706e 1394 *
bogdanm 82:6473597d706e 1395 * @param instance eDMA module
bogdanm 82:6473597d706e 1396 * @param channel eDMA channel
bogdanm 82:6473597d706e 1397 * @return data bytes to be transferred
bogdanm 82:6473597d706e 1398 */
bogdanm 82:6473597d706e 1399 uint32_t edma_hal_htcd_get_finished_bytes(uint32_t instance, uint32_t channel);
bogdanm 82:6473597d706e 1400 /* @} */
bogdanm 82:6473597d706e 1401
bogdanm 82:6473597d706e 1402 /*!
bogdanm 82:6473597d706e 1403 * @name eDMA HAL software TCD configuration
bogdanm 82:6473597d706e 1404 * @{
bogdanm 82:6473597d706e 1405 */
bogdanm 82:6473597d706e 1406
bogdanm 82:6473597d706e 1407 /*!
bogdanm 82:6473597d706e 1408 * @brief Configures the source address for the software TCD.
bogdanm 82:6473597d706e 1409 *
bogdanm 82:6473597d706e 1410 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1411 * @param address memory address pointing to the source data
bogdanm 82:6473597d706e 1412 */
bogdanm 82:6473597d706e 1413 static inline void edma_hal_stcd_configure_source_address(
bogdanm 82:6473597d706e 1414 edma_software_tcd_t *stcd, uint32_t address)
bogdanm 82:6473597d706e 1415 {
bogdanm 82:6473597d706e 1416 assert(stcd);
bogdanm 82:6473597d706e 1417 stcd->SADDR = DMA_SADDR_SADDR(address);
bogdanm 82:6473597d706e 1418 }
bogdanm 82:6473597d706e 1419
bogdanm 82:6473597d706e 1420 /*!
bogdanm 82:6473597d706e 1421 * @brief Configures the source address for the software TCD.
bogdanm 82:6473597d706e 1422 *
bogdanm 82:6473597d706e 1423 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1424 * @param address memory address pointing to the source data
bogdanm 82:6473597d706e 1425 */
bogdanm 82:6473597d706e 1426 static inline void edma_hal_stcd_configure_source_offset(
bogdanm 82:6473597d706e 1427 edma_software_tcd_t *stcd, uint32_t offset)
bogdanm 82:6473597d706e 1428 {
bogdanm 82:6473597d706e 1429 assert(stcd);
bogdanm 82:6473597d706e 1430 stcd->SOFF = DMA_SOFF_SOFF(offset);
bogdanm 82:6473597d706e 1431 }
bogdanm 82:6473597d706e 1432
bogdanm 82:6473597d706e 1433 /*!
bogdanm 82:6473597d706e 1434 * @brief Configures the source modulo for the software TCD.
bogdanm 82:6473597d706e 1435 *
bogdanm 82:6473597d706e 1436 * The value defines a specific address range as the value after the SADDR + SOFF
bogdanm 82:6473597d706e 1437 * calculation is performed on the original register value. Setting this field provides the ability
bogdanm 82:6473597d706e 1438 * to implement a circular data queue. For data queues requiring power-of-2 size bytes, the
bogdanm 82:6473597d706e 1439 * queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate
bogdanm 82:6473597d706e 1440 * value for the queue, freezing the desired number of upper address bits. The value programmed into
bogdanm 82:6473597d706e 1441 * this field specifies the number of lower address bits allowed to change. For a circular queue
bogdanm 82:6473597d706e 1442 * application, the SOFF is typically set to the transfer size to implement post-increment addressing
bogdanm 82:6473597d706e 1443 * with SMOD function restricting the addresses to a 0-modulo-size range.
bogdanm 82:6473597d706e 1444 *
bogdanm 82:6473597d706e 1445 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1446 * @param modulo enum type for the allowed modulo
bogdanm 82:6473597d706e 1447 */
bogdanm 82:6473597d706e 1448 static inline void edma_hal_stcd_configure_source_modulo(
bogdanm 82:6473597d706e 1449 edma_software_tcd_t *stcd, edma_modulo_t modulo)
bogdanm 82:6473597d706e 1450 {
bogdanm 82:6473597d706e 1451 assert(stcd);
bogdanm 82:6473597d706e 1452 stcd->ATTR = (stcd->ATTR & ~DMA_ATTR_SMOD_MASK) | DMA_ATTR_SMOD(modulo);
bogdanm 82:6473597d706e 1453 }
bogdanm 82:6473597d706e 1454
bogdanm 82:6473597d706e 1455 /*!
bogdanm 82:6473597d706e 1456 * @brief Configures the source data transfersize for the software TCD.
bogdanm 82:6473597d706e 1457 *
bogdanm 82:6473597d706e 1458 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1459 * @param size enum type for transfer size
bogdanm 82:6473597d706e 1460 */
bogdanm 82:6473597d706e 1461 static inline void edma_hal_stcd_configure_source_transfersize(
bogdanm 82:6473597d706e 1462 edma_software_tcd_t *stcd, edma_transfer_size_t size)
bogdanm 82:6473597d706e 1463 {
bogdanm 82:6473597d706e 1464 assert(stcd);
bogdanm 82:6473597d706e 1465 stcd->ATTR = (stcd->ATTR & ~DMA_ATTR_SSIZE_MASK) | DMA_ATTR_SSIZE(size);
bogdanm 82:6473597d706e 1466 }
bogdanm 82:6473597d706e 1467
bogdanm 82:6473597d706e 1468 /*!
bogdanm 82:6473597d706e 1469 * @brief Configures the destination modulo for the software TCD.
bogdanm 82:6473597d706e 1470 *
bogdanm 82:6473597d706e 1471 * The value defines a specific address range as the value after the DADDR + DOFF
bogdanm 82:6473597d706e 1472 * calculation is performed on the original register value. Setting this field provides the ability
bogdanm 82:6473597d706e 1473 * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
bogdanm 82:6473597d706e 1474 * queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate
bogdanm 82:6473597d706e 1475 * value for the queue, freezing the desired number of upper address bits. The value programmed into
bogdanm 82:6473597d706e 1476 * this field specifies the number of lower address bits allowed to change. For a circular queue
bogdanm 82:6473597d706e 1477 * application, the SOFF is typically set to the transfer size to implement post-increment addressing
bogdanm 82:6473597d706e 1478 * with DMOD function restricting the addresses to a 0-modulo-size range.
bogdanm 82:6473597d706e 1479 *
bogdanm 82:6473597d706e 1480 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1481 * @param modulo enum type for allowed modulo
bogdanm 82:6473597d706e 1482 */
bogdanm 82:6473597d706e 1483 static inline void edma_hal_stcd_configure_dest_modulo(
bogdanm 82:6473597d706e 1484 edma_software_tcd_t *stcd, edma_modulo_t modulo)
bogdanm 82:6473597d706e 1485 {
bogdanm 82:6473597d706e 1486 assert(stcd);
bogdanm 82:6473597d706e 1487 stcd->ATTR = (stcd->ATTR & ~DMA_ATTR_DMOD_MASK) | DMA_ATTR_DMOD(modulo);
bogdanm 82:6473597d706e 1488 }
bogdanm 82:6473597d706e 1489
bogdanm 82:6473597d706e 1490 /*!
bogdanm 82:6473597d706e 1491 * @brief Configures the destination data transfersize for the software TCD.
bogdanm 82:6473597d706e 1492 *
bogdanm 82:6473597d706e 1493 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1494 * @param size enum type for transfer size
bogdanm 82:6473597d706e 1495 */
bogdanm 82:6473597d706e 1496 static inline void edma_hal_stcd_configure_dest_transfersize(
bogdanm 82:6473597d706e 1497 edma_software_tcd_t *stcd, edma_transfer_size_t size)
bogdanm 82:6473597d706e 1498 {
bogdanm 82:6473597d706e 1499 assert(stcd);
bogdanm 82:6473597d706e 1500 stcd->ATTR = (stcd->ATTR & ~DMA_ATTR_DSIZE_MASK) | DMA_ATTR_DSIZE(size);
bogdanm 82:6473597d706e 1501 }
bogdanm 82:6473597d706e 1502
bogdanm 82:6473597d706e 1503 /*!
bogdanm 82:6473597d706e 1504 * @brief Configures the nbytes if minor loop mapping is disabled the for software TCD.
bogdanm 82:6473597d706e 1505 *
bogdanm 82:6473597d706e 1506 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1507 * @param nbytes Number of bytes to be transferred in each service request of the channel
bogdanm 82:6473597d706e 1508 */
bogdanm 82:6473597d706e 1509 static inline void edma_hal_stcd_configure_nbytes_minorloop_disabled(
bogdanm 82:6473597d706e 1510 edma_software_tcd_t *stcd, uint32_t nbytes)
bogdanm 82:6473597d706e 1511 {
bogdanm 82:6473597d706e 1512 assert(stcd);
bogdanm 82:6473597d706e 1513 stcd->NBYTES_MLNO =
bogdanm 82:6473597d706e 1514 (stcd->NBYTES_MLNO & ~DMA_NBYTES_MLNO_NBYTES_MASK) | DMA_NBYTES_MLNO_NBYTES(nbytes);
bogdanm 82:6473597d706e 1515 }
bogdanm 82:6473597d706e 1516
bogdanm 82:6473597d706e 1517 /*!
bogdanm 82:6473597d706e 1518 * @brief Configures the nbytes if the minor loop mapping is enabled and offset is disabled for the software TCD.
bogdanm 82:6473597d706e 1519 *
bogdanm 82:6473597d706e 1520 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1521 * @param nbytes Number of bytes to be transferred in each service request of the channel
bogdanm 82:6473597d706e 1522 */
bogdanm 82:6473597d706e 1523 static inline void edma_hal_stcd_configure_nbytes_minorloop_enabled_offset_disabled(
bogdanm 82:6473597d706e 1524 edma_software_tcd_t *stcd, uint32_t nbytes)
bogdanm 82:6473597d706e 1525 {
bogdanm 82:6473597d706e 1526 assert(stcd);
bogdanm 82:6473597d706e 1527 stcd->NBYTES_MLOFFNO =
bogdanm 82:6473597d706e 1528 (stcd->NBYTES_MLOFFNO & ~DMA_NBYTES_MLOFFNO_NBYTES_MASK) | DMA_NBYTES_MLOFFNO_NBYTES(nbytes);
bogdanm 82:6473597d706e 1529 }
bogdanm 82:6473597d706e 1530
bogdanm 82:6473597d706e 1531 /*!
bogdanm 82:6473597d706e 1532 * @brief Configures the nbytes if minor loop mapping is enabled and offset is enabled for the software TCD.
bogdanm 82:6473597d706e 1533 *
bogdanm 82:6473597d706e 1534 * @param STCD memory pointing to the eDMA software TCD.
bogdanm 82:6473597d706e 1535 * @param nbytes Number of bytes to be transferred in each service request of the channel.
bogdanm 82:6473597d706e 1536 */
bogdanm 82:6473597d706e 1537 static inline void edma_hal_stcd_configure_nbytes_minorloop_enabled_offset_enabled(
bogdanm 82:6473597d706e 1538 edma_software_tcd_t *stcd, uint32_t nbytes)
bogdanm 82:6473597d706e 1539 {
bogdanm 82:6473597d706e 1540 assert(stcd);
bogdanm 82:6473597d706e 1541 stcd->NBYTES_MLOFFYES =
bogdanm 82:6473597d706e 1542 (stcd->NBYTES_MLOFFYES & ~DMA_NBYTES_MLOFFYES_NBYTES_MASK) | DMA_NBYTES_MLOFFYES_NBYTES(nbytes);
bogdanm 82:6473597d706e 1543 }
bogdanm 82:6473597d706e 1544
bogdanm 82:6473597d706e 1545 /*!
bogdanm 82:6473597d706e 1546 * @brief Configures the minorloop offset for the software TCD.
bogdanm 82:6473597d706e 1547 *
bogdanm 82:6473597d706e 1548 * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled,
bogdanm 82:6473597d706e 1549 * offset can't be configured.
bogdanm 82:6473597d706e 1550 *
bogdanm 82:6473597d706e 1551 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1552 * @param config Configuration data structure for the minorloop offset
bogdanm 82:6473597d706e 1553 */
bogdanm 82:6473597d706e 1554 static inline void edma_hal_stcd_configure_minorloop_offset(
bogdanm 82:6473597d706e 1555 edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config)
bogdanm 82:6473597d706e 1556 {
bogdanm 82:6473597d706e 1557 assert(stcd);
bogdanm 82:6473597d706e 1558 stcd->NBYTES_MLOFFYES =
bogdanm 82:6473597d706e 1559 (stcd->NBYTES_MLOFFYES & ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK)) |
bogdanm 82:6473597d706e 1560 (((uint32_t)config->isEnableSourceMinorloop << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) |
bogdanm 82:6473597d706e 1561 ((uint32_t)config->isEnableDestMinorloop << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT));
bogdanm 82:6473597d706e 1562
bogdanm 82:6473597d706e 1563 if ((config->isEnableSourceMinorloop == true) || (config->isEnableDestMinorloop == true))
bogdanm 82:6473597d706e 1564 {
bogdanm 82:6473597d706e 1565 stcd->NBYTES_MLOFFYES =
bogdanm 82:6473597d706e 1566 (stcd->NBYTES_MLOFFYES & ~DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
bogdanm 82:6473597d706e 1567 DMA_NBYTES_MLOFFYES_MLOFF(config->offset);
bogdanm 82:6473597d706e 1568 }
bogdanm 82:6473597d706e 1569 }
bogdanm 82:6473597d706e 1570
bogdanm 82:6473597d706e 1571 /*!
bogdanm 82:6473597d706e 1572 * @brief Configures the last source address adjustment for the software TCD.
bogdanm 82:6473597d706e 1573 *
bogdanm 82:6473597d706e 1574 * Adjustment value added to the source address at the completion of the major iteration count. This
bogdanm 82:6473597d706e 1575 * value can be applied to restore the source address to the initial value, or adjust the address to
bogdanm 82:6473597d706e 1576 * reference the next data structure.
bogdanm 82:6473597d706e 1577 *
bogdanm 82:6473597d706e 1578 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1579 * @param size adjustment value
bogdanm 82:6473597d706e 1580 */
bogdanm 82:6473597d706e 1581 static inline void edma_hal_stcd_configure_source_last_adjustment(
bogdanm 82:6473597d706e 1582 edma_software_tcd_t *stcd, int32_t size)
bogdanm 82:6473597d706e 1583 {
bogdanm 82:6473597d706e 1584 assert(stcd);
bogdanm 82:6473597d706e 1585 stcd->SLAST = (stcd->SLAST & ~DMA_SLAST_SLAST_MASK) | DMA_SLAST_SLAST(size);
bogdanm 82:6473597d706e 1586 }
bogdanm 82:6473597d706e 1587
bogdanm 82:6473597d706e 1588 /*!
bogdanm 82:6473597d706e 1589 * @brief Configures the destination address for the software TCD.
bogdanm 82:6473597d706e 1590 *
bogdanm 82:6473597d706e 1591 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1592 * @param address memory address pointing to destination data
bogdanm 82:6473597d706e 1593 */
bogdanm 82:6473597d706e 1594 static inline void edma_hal_stcd_configure_dest_address(
bogdanm 82:6473597d706e 1595 edma_software_tcd_t *stcd, uint32_t address)
bogdanm 82:6473597d706e 1596 {
bogdanm 82:6473597d706e 1597 assert(stcd);
bogdanm 82:6473597d706e 1598 stcd->DADDR = DMA_DADDR_DADDR(address);
bogdanm 82:6473597d706e 1599 }
bogdanm 82:6473597d706e 1600
bogdanm 82:6473597d706e 1601 /*!
bogdanm 82:6473597d706e 1602 * @brief Configures the destination address signed offset for the software TCD.
bogdanm 82:6473597d706e 1603 *
bogdanm 82:6473597d706e 1604 * Sign-extended offset applied to the current source address to form the next-state value as each
bogdanm 82:6473597d706e 1605 * destination write is complete.
bogdanm 82:6473597d706e 1606 *
bogdanm 82:6473597d706e 1607 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1608 * @param offset signed-offset
bogdanm 82:6473597d706e 1609 */
bogdanm 82:6473597d706e 1610 static inline void edma_hal_stcd_configure_dest_offset(
bogdanm 82:6473597d706e 1611 edma_software_tcd_t *stcd, uint32_t offset)
bogdanm 82:6473597d706e 1612 {
bogdanm 82:6473597d706e 1613 assert(stcd);
bogdanm 82:6473597d706e 1614 stcd->DOFF = DMA_DOFF_DOFF(offset);
bogdanm 82:6473597d706e 1615 }
bogdanm 82:6473597d706e 1616
bogdanm 82:6473597d706e 1617 /*!
bogdanm 82:6473597d706e 1618 * @brief Configures the last source address adjustment or the memory address for the next transfer
bogdanm 82:6473597d706e 1619 * control for the software TCD.
bogdanm 82:6473597d706e 1620 *
bogdanm 82:6473597d706e 1621 * If the scatter/gather feature is enabled(edma_hal_htcd_set_scatter_gather_process()):
bogdanm 82:6473597d706e 1622 *
bogdanm 82:6473597d706e 1623 * This address points to the beginning of a 0-modulo-32 byte region containing the next transfer
bogdanm 82:6473597d706e 1624 * control descriptor to be loaded into this channel. The channel reload is performed as the major
bogdanm 82:6473597d706e 1625 * iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, a
bogdanm 82:6473597d706e 1626 * configuration error is reported.
bogdanm 82:6473597d706e 1627 *
bogdanm 82:6473597d706e 1628 * else:
bogdanm 82:6473597d706e 1629 *
bogdanm 82:6473597d706e 1630 * Adjustment value added to the source address at the completion of the major iteration count. This
bogdanm 82:6473597d706e 1631 * value can be applied to restore the source address to the initial value, or adjust the address to
bogdanm 82:6473597d706e 1632 * reference the next data structure.
bogdanm 82:6473597d706e 1633 *
bogdanm 82:6473597d706e 1634 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1635 * @param size adjustment value
bogdanm 82:6473597d706e 1636 */
bogdanm 82:6473597d706e 1637 static inline void edma_hal_stcd_configure_dest_last_adjustment_or_scatter_address(
bogdanm 82:6473597d706e 1638 edma_software_tcd_t *stcd, uint32_t address)
bogdanm 82:6473597d706e 1639 {
bogdanm 82:6473597d706e 1640 assert(stcd);
bogdanm 82:6473597d706e 1641 stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(address);
bogdanm 82:6473597d706e 1642 }
bogdanm 82:6473597d706e 1643
bogdanm 82:6473597d706e 1644 /*!
bogdanm 82:6473597d706e 1645 * @brief Configures the bandwidth for the software TCD.
bogdanm 82:6473597d706e 1646 *
bogdanm 82:6473597d706e 1647 * Throttles the amount of bus bandwidth consumed by the eDMA. As the eDMA processes the
bogdanm 82:6473597d706e 1648 * minor loop, it continuously generates read/write sequences until the minor count is exhausted.
bogdanm 82:6473597d706e 1649 * This field forces the eDMA to stall after the completion of each read/write access to control the
bogdanm 82:6473597d706e 1650 * bus request bandwidth seen by the crossbar switch.
bogdanm 82:6473597d706e 1651 *
bogdanm 82:6473597d706e 1652 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1653 * @param bandwidth enum type for bandwidth control
bogdanm 82:6473597d706e 1654 */
bogdanm 82:6473597d706e 1655 static inline void edma_hal_stcd_configure_bandwidth(
bogdanm 82:6473597d706e 1656 edma_software_tcd_t *stcd, edma_bandwidth_configuration_t bandwidth)
bogdanm 82:6473597d706e 1657 {
bogdanm 82:6473597d706e 1658 assert(stcd);
bogdanm 82:6473597d706e 1659 stcd->CSR = (stcd->CSR & ~DMA_CSR_BWC_MASK) | DMA_CSR_BWC(bandwidth);
bogdanm 82:6473597d706e 1660 }
bogdanm 82:6473597d706e 1661
bogdanm 82:6473597d706e 1662 /*!
bogdanm 82:6473597d706e 1663 * @brief Configures the major link channel number for the software TCD.
bogdanm 82:6473597d706e 1664 *
bogdanm 82:6473597d706e 1665 * If majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a
bogdanm 82:6473597d706e 1666 * channel service request at the channel defined by these six bits by setting that channel start
bogdanm 82:6473597d706e 1667 * bits.
bogdanm 82:6473597d706e 1668 *
bogdanm 82:6473597d706e 1669 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1670 * @param majorchannel channel number for major link
bogdanm 82:6473597d706e 1671 */
bogdanm 82:6473597d706e 1672 static inline void edma_hal_stcd_configure_majorlink_channel(
bogdanm 82:6473597d706e 1673 edma_software_tcd_t *stcd, uint32_t majorchannel)
bogdanm 82:6473597d706e 1674 {
bogdanm 82:6473597d706e 1675 assert(stcd);
bogdanm 82:6473597d706e 1676 stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORLINKCH_MASK) | DMA_CSR_MAJORLINKCH(majorchannel);
bogdanm 82:6473597d706e 1677 }
bogdanm 82:6473597d706e 1678
bogdanm 82:6473597d706e 1679 /*!
bogdanm 82:6473597d706e 1680 * @brief Enables/Disables the major link channel feature for the software TCD.
bogdanm 82:6473597d706e 1681 *
bogdanm 82:6473597d706e 1682 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1683 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1684 */
bogdanm 82:6473597d706e 1685 static inline void edma_hal_stcd_set_majorlink(edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1686 {
bogdanm 82:6473597d706e 1687 assert(stcd);
bogdanm 82:6473597d706e 1688 stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORELINK_MASK) |
bogdanm 82:6473597d706e 1689 ((uint32_t)isEnabled << DMA_CSR_MAJORELINK_SHIFT);
bogdanm 82:6473597d706e 1690 }
bogdanm 82:6473597d706e 1691
bogdanm 82:6473597d706e 1692 /*!
bogdanm 82:6473597d706e 1693 * @brief Enables/Disables the scatter/gather feature for the software TCD.
bogdanm 82:6473597d706e 1694 *
bogdanm 82:6473597d706e 1695 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1696 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1697 */
bogdanm 82:6473597d706e 1698 static inline void edma_hal_stcd_set_scatter_gather_process(
bogdanm 82:6473597d706e 1699 edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1700 {
bogdanm 82:6473597d706e 1701 assert(stcd);
bogdanm 82:6473597d706e 1702 stcd->CSR = (stcd->CSR & ~DMA_CSR_ESG_MASK) | ((uint32_t)isEnabled << DMA_CSR_ESG_SHIFT);
bogdanm 82:6473597d706e 1703 }
bogdanm 82:6473597d706e 1704
bogdanm 82:6473597d706e 1705 /*!
bogdanm 82:6473597d706e 1706 * @brief Disables/Enables the DMA request after the major loop completes for the software TCD.
bogdanm 82:6473597d706e 1707 *
bogdanm 82:6473597d706e 1708 * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the
bogdanm 82:6473597d706e 1709 * current major iteration count reaches zero.
bogdanm 82:6473597d706e 1710 *
bogdanm 82:6473597d706e 1711 * @param STCD memory pointing to the eDMA software TCD.
bogdanm 82:6473597d706e 1712 * @param isDisabled Disable/Enable
bogdanm 82:6473597d706e 1713 */
bogdanm 82:6473597d706e 1714 static inline void edma_hal_stcd_set_disable_dma_request_after_tcd_done(
bogdanm 82:6473597d706e 1715 edma_software_tcd_t *stcd, bool isDisabled)
bogdanm 82:6473597d706e 1716 {
bogdanm 82:6473597d706e 1717 assert(stcd);
bogdanm 82:6473597d706e 1718 stcd->CSR = (stcd->CSR & ~DMA_CSR_DREQ_MASK) | ((uint32_t)isDisabled << DMA_CSR_DREQ_SHIFT);
bogdanm 82:6473597d706e 1719 }
bogdanm 82:6473597d706e 1720
bogdanm 82:6473597d706e 1721 /*!
bogdanm 82:6473597d706e 1722 * @brief Enables/Disables the half complete interrupt for the software TCD.
bogdanm 82:6473597d706e 1723 *
bogdanm 82:6473597d706e 1724 * If set, the channel generates an interrupt request by setting the appropriate bit in the
bogdanm 82:6473597d706e 1725 * interrupt register when the current major iteration count reaches the halfway point. Specifically,
bogdanm 82:6473597d706e 1726 * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half way point
bogdanm 82:6473597d706e 1727 * interrupt request is provided to support the double-buffered schemes or other types of data movement
bogdanm 82:6473597d706e 1728 * where the processor needs an early indication of the transfer process.
bogdanm 82:6473597d706e 1729 *
bogdanm 82:6473597d706e 1730 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1731 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1732 */
bogdanm 82:6473597d706e 1733 static inline void edma_hal_stcd_set_half_complete_interrupt(
bogdanm 82:6473597d706e 1734 edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1735 {
bogdanm 82:6473597d706e 1736 assert(stcd);
bogdanm 82:6473597d706e 1737 stcd->CSR = (stcd->CSR & ~DMA_CSR_INTHALF_MASK) | ((uint32_t)isEnabled << DMA_CSR_INTHALF_SHIFT);
bogdanm 82:6473597d706e 1738 }
bogdanm 82:6473597d706e 1739
bogdanm 82:6473597d706e 1740 /*!
bogdanm 82:6473597d706e 1741 * @brief Enables/Disables the interrupt after major loop complete for the software TCD.
bogdanm 82:6473597d706e 1742 *
bogdanm 82:6473597d706e 1743 * If enabled, the channel generates an interrupt request by setting the appropriate bit in the
bogdanm 82:6473597d706e 1744 * interrupt register when the current major iteration count reaches zero.
bogdanm 82:6473597d706e 1745 *
bogdanm 82:6473597d706e 1746 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1747 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1748 */
bogdanm 82:6473597d706e 1749 static inline void edma_hal_stcd_set_complete_interrupt(
bogdanm 82:6473597d706e 1750 edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1751 {
bogdanm 82:6473597d706e 1752 assert(stcd);
bogdanm 82:6473597d706e 1753 stcd->CSR = (stcd->CSR & ~DMA_CSR_INTMAJOR_MASK) | ((uint32_t)isEnabled << DMA_CSR_INTMAJOR_SHIFT);
bogdanm 82:6473597d706e 1754 }
bogdanm 82:6473597d706e 1755
bogdanm 82:6473597d706e 1756 /*!
bogdanm 82:6473597d706e 1757 * @brief Sets the trigger start bits for the software TCD.
bogdanm 82:6473597d706e 1758 *
bogdanm 82:6473597d706e 1759 */
bogdanm 82:6473597d706e 1760 static inline void edma_hal_stcd_trigger_channel_start(
bogdanm 82:6473597d706e 1761 edma_software_tcd_t *stcd)
bogdanm 82:6473597d706e 1762 {
bogdanm 82:6473597d706e 1763 assert(stcd);
bogdanm 82:6473597d706e 1764 stcd->CSR |= DMA_CSR_START_MASK;
bogdanm 82:6473597d706e 1765 }
bogdanm 82:6473597d706e 1766
bogdanm 82:6473597d706e 1767 /*!
bogdanm 82:6473597d706e 1768 * @brief Enables/Disables the channel link after the minor loop for the software TCD.
bogdanm 82:6473597d706e 1769 *
bogdanm 82:6473597d706e 1770 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1771 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1772 */
bogdanm 82:6473597d706e 1773 static inline void edma_hal_stcd_set_minor_link(
bogdanm 82:6473597d706e 1774 edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1775 {
bogdanm 82:6473597d706e 1776 assert(stcd);
bogdanm 82:6473597d706e 1777 stcd->BITER_ELINKYES = (stcd->BITER_ELINKYES & ~DMA_BITER_ELINKYES_ELINK_MASK) |
bogdanm 82:6473597d706e 1778 ((uint32_t)isEnabled << DMA_BITER_ELINKYES_ELINK_SHIFT);
bogdanm 82:6473597d706e 1779 }
bogdanm 82:6473597d706e 1780
bogdanm 82:6473597d706e 1781 /*!
bogdanm 82:6473597d706e 1782 * @brief Enables/Disables the current channel link after the minor loop for the software TCD.
bogdanm 82:6473597d706e 1783 *
bogdanm 82:6473597d706e 1784 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1785 * @param isEnabled Enable/Disable
bogdanm 82:6473597d706e 1786 */
bogdanm 82:6473597d706e 1787 static inline void edma_hal_stcd_set_current_minor_link(
bogdanm 82:6473597d706e 1788 edma_software_tcd_t *stcd, bool isEnabled)
bogdanm 82:6473597d706e 1789 {
bogdanm 82:6473597d706e 1790 assert(stcd);
bogdanm 82:6473597d706e 1791 stcd->CITER_ELINKYES = (stcd->CITER_ELINKYES & ~DMA_CITER_ELINKYES_ELINK_MASK) |
bogdanm 82:6473597d706e 1792 ((uint32_t)isEnabled << DMA_CITER_ELINKYES_ELINK_SHIFT);
bogdanm 82:6473597d706e 1793 }
bogdanm 82:6473597d706e 1794
bogdanm 82:6473597d706e 1795 /*!
bogdanm 82:6473597d706e 1796 * @brief Configures the minor loop link channel for the software TCD.
bogdanm 82:6473597d706e 1797 *
bogdanm 82:6473597d706e 1798 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1799 * @param minorchannel minor loop link channel
bogdanm 82:6473597d706e 1800 */
bogdanm 82:6473597d706e 1801 static inline void edma_hal_stcd_configure_minor_link_channel(
bogdanm 82:6473597d706e 1802 edma_software_tcd_t *stcd, uint32_t minorchannel)
bogdanm 82:6473597d706e 1803 {
bogdanm 82:6473597d706e 1804 assert(stcd);
bogdanm 82:6473597d706e 1805 stcd->BITER_ELINKYES = (stcd->BITER_ELINKYES & ~DMA_BITER_ELINKYES_LINKCH_MASK) |
bogdanm 82:6473597d706e 1806 DMA_BITER_ELINKYES_LINKCH(minorchannel);
bogdanm 82:6473597d706e 1807 }
bogdanm 82:6473597d706e 1808
bogdanm 82:6473597d706e 1809 /*!
bogdanm 82:6473597d706e 1810 * @brief Configures the minor loop link channel for the software TCD.
bogdanm 82:6473597d706e 1811 *
bogdanm 82:6473597d706e 1812 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1813 * @param minorchannel minor loop link channel.
bogdanm 82:6473597d706e 1814 */
bogdanm 82:6473597d706e 1815 static inline void edma_hal_stcd_configure_current_minor_link_channel(
bogdanm 82:6473597d706e 1816 edma_software_tcd_t *stcd, uint32_t minorchannel)
bogdanm 82:6473597d706e 1817 {
bogdanm 82:6473597d706e 1818 assert(stcd);
bogdanm 82:6473597d706e 1819 stcd->CITER_ELINKYES = (stcd->CITER_ELINKYES & ~DMA_CITER_ELINKYES_LINKCH_MASK) |
bogdanm 82:6473597d706e 1820 DMA_CITER_ELINKYES_LINKCH(minorchannel);
bogdanm 82:6473597d706e 1821 }
bogdanm 82:6473597d706e 1822
bogdanm 82:6473597d706e 1823 /*!
bogdanm 82:6473597d706e 1824 * @brief Configures the major count if the minor loop channel link is disabled for the software TCD.
bogdanm 82:6473597d706e 1825 *
bogdanm 82:6473597d706e 1826 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1827 * @param count major loop count
bogdanm 82:6473597d706e 1828 */
bogdanm 82:6473597d706e 1829 static inline void edma_hal_stcd_configure_majorcount_minorlink_disabled(
bogdanm 82:6473597d706e 1830 edma_software_tcd_t *stcd, uint32_t count)
bogdanm 82:6473597d706e 1831 {
bogdanm 82:6473597d706e 1832 assert(stcd);
bogdanm 82:6473597d706e 1833 stcd->BITER_ELINKNO = (stcd->BITER_ELINKNO & ~DMA_BITER_ELINKNO_BITER_MASK) |
bogdanm 82:6473597d706e 1834 DMA_BITER_ELINKNO_BITER(count);
bogdanm 82:6473597d706e 1835 }
bogdanm 82:6473597d706e 1836
bogdanm 82:6473597d706e 1837 /*!
bogdanm 82:6473597d706e 1838 * @brief Configure current major count if minor loop channel link is disabled for software TCD.
bogdanm 82:6473597d706e 1839 *
bogdanm 82:6473597d706e 1840 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1841 * @param count major loop count
bogdanm 82:6473597d706e 1842 */
bogdanm 82:6473597d706e 1843 static inline void edma_hal_stcd_configure_current_majorcount_minorlink_disabled(
bogdanm 82:6473597d706e 1844 edma_software_tcd_t *stcd, uint32_t count)
bogdanm 82:6473597d706e 1845 {
bogdanm 82:6473597d706e 1846 assert(stcd);
bogdanm 82:6473597d706e 1847 stcd->CITER_ELINKNO = (stcd->CITER_ELINKNO & ~DMA_CITER_ELINKNO_CITER_MASK) |
bogdanm 82:6473597d706e 1848 DMA_CITER_ELINKNO_CITER(count);
bogdanm 82:6473597d706e 1849 }
bogdanm 82:6473597d706e 1850
bogdanm 82:6473597d706e 1851 /*!
bogdanm 82:6473597d706e 1852 * @brief Configures the major count if the minor loop channel link is enabled for the software TCD.
bogdanm 82:6473597d706e 1853 *
bogdanm 82:6473597d706e 1854 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1855 * @param count major loop count
bogdanm 82:6473597d706e 1856 */
bogdanm 82:6473597d706e 1857 static inline void edma_hal_stcd_configure_majorcount_minorlink_enabled(
bogdanm 82:6473597d706e 1858 edma_software_tcd_t *stcd, uint32_t count)
bogdanm 82:6473597d706e 1859 {
bogdanm 82:6473597d706e 1860 assert(stcd);
bogdanm 82:6473597d706e 1861 stcd->BITER_ELINKYES = (stcd->BITER_ELINKYES & ~DMA_BITER_ELINKYES_BITER_MASK) |
bogdanm 82:6473597d706e 1862 DMA_BITER_ELINKYES_BITER(count);
bogdanm 82:6473597d706e 1863 }
bogdanm 82:6473597d706e 1864
bogdanm 82:6473597d706e 1865 /*!
bogdanm 82:6473597d706e 1866 * @brief Configures the current major count if the minor loop channel link is enabled for the software TCD.
bogdanm 82:6473597d706e 1867 *
bogdanm 82:6473597d706e 1868 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1869 * @param count major loop count
bogdanm 82:6473597d706e 1870 */
bogdanm 82:6473597d706e 1871 static inline void edma_hal_stcd_configure_current_majorcount_minorlink_enabled(
bogdanm 82:6473597d706e 1872 edma_software_tcd_t *stcd, uint32_t count)
bogdanm 82:6473597d706e 1873 {
bogdanm 82:6473597d706e 1874 assert(stcd);
bogdanm 82:6473597d706e 1875 stcd->CITER_ELINKYES = (stcd->CITER_ELINKYES & ~DMA_CITER_ELINKYES_CITER_MASK) |
bogdanm 82:6473597d706e 1876 DMA_CITER_ELINKYES_CITER(count);
bogdanm 82:6473597d706e 1877 }
bogdanm 82:6473597d706e 1878
bogdanm 82:6473597d706e 1879 /*!
bogdanm 82:6473597d706e 1880 * @brief Copy the software TCD configuration to the hardware TCD.
bogdanm 82:6473597d706e 1881 *
bogdanm 82:6473597d706e 1882 * @param STCD memory pointing to the eDMA software TCD
bogdanm 82:6473597d706e 1883 * @param instance eDMA module
bogdanm 82:6473597d706e 1884 * @param channel eDMA channel
bogdanm 82:6473597d706e 1885 * @param STCD memory pointing to the software TCD
bogdanm 82:6473597d706e 1886 */
bogdanm 82:6473597d706e 1887 void edma_hal_stcd_push_to_htcd(uint32_t instance, uint32_t channel, edma_software_tcd_t *stcd);
bogdanm 82:6473597d706e 1888
bogdanm 82:6473597d706e 1889 /* @} */
bogdanm 82:6473597d706e 1890
bogdanm 82:6473597d706e 1891 #if defined(__cplusplus)
bogdanm 82:6473597d706e 1892 }
bogdanm 82:6473597d706e 1893 #endif
bogdanm 82:6473597d706e 1894
bogdanm 82:6473597d706e 1895 /*! @} */
bogdanm 82:6473597d706e 1896
bogdanm 82:6473597d706e 1897 #endif /* __EDMA_HAL_H__ */
bogdanm 82:6473597d706e 1898
bogdanm 82:6473597d706e 1899 /*******************************************************************************
bogdanm 82:6473597d706e 1900 * EOF
bogdanm 82:6473597d706e 1901 ******************************************************************************/
bogdanm 82:6473597d706e 1902