frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #if !defined(__FSL_DSPI_HAL_H__)
bogdanm 82:6473597d706e 31 #define __FSL_DSPI_HAL_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33 #include <assert.h>
bogdanm 82:6473597d706e 34 #include <stdint.h>
bogdanm 82:6473597d706e 35 #include <stdbool.h>
bogdanm 82:6473597d706e 36 #include "fsl_dspi_features.h"
bogdanm 82:6473597d706e 37 #include "fsl_device_registers.h"
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39 /*!
bogdanm 82:6473597d706e 40 * @addtogroup dspi_hal
bogdanm 82:6473597d706e 41 * @{
bogdanm 82:6473597d706e 42 */
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 /*! @file*/
bogdanm 82:6473597d706e 45
bogdanm 82:6473597d706e 46 /*******************************************************************************
bogdanm 82:6473597d706e 47 * Definitions
bogdanm 82:6473597d706e 48 ******************************************************************************/
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50 /* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
bogdanm 82:6473597d706e 51 static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
bogdanm 82:6473597d706e 52 static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
bogdanm 82:6473597d706e 53 4096, 8192, 16384, 32768 };
bogdanm 82:6473597d706e 54
bogdanm 82:6473597d706e 55 /*! @brief Error codes for the DSPI driver.*/
bogdanm 82:6473597d706e 56 typedef enum _dspi_status
bogdanm 82:6473597d706e 57 {
bogdanm 82:6473597d706e 58 kStatus_DSPI_Success = 0,
bogdanm 82:6473597d706e 59 kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/
bogdanm 82:6473597d706e 60 kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/
bogdanm 82:6473597d706e 61 kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/
bogdanm 82:6473597d706e 62 kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a
bogdanm 82:6473597d706e 63 transfer.*/
bogdanm 82:6473597d706e 64 kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer
bogdanm 82:6473597d706e 65 was in progress*/
bogdanm 82:6473597d706e 66 kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
bogdanm 82:6473597d706e 67 kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
bogdanm 82:6473597d706e 68 kStatus_DSPI_OutOfRange /*< DSPI out-of-range error used in slave callback */
bogdanm 82:6473597d706e 69 } dspi_status_t;
bogdanm 82:6473597d706e 70
bogdanm 82:6473597d706e 71 /*! @brief DSPI master or slave configuration*/
bogdanm 82:6473597d706e 72 typedef enum _dspi_master_slave_mode {
bogdanm 82:6473597d706e 73 kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/
bogdanm 82:6473597d706e 74 kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/
bogdanm 82:6473597d706e 75 } dspi_master_slave_mode_t;
bogdanm 82:6473597d706e 76
bogdanm 82:6473597d706e 77 /*! @brief DSPI clock polarity configuration for a given CTAR*/
bogdanm 82:6473597d706e 78 typedef enum _dspi_clock_polarity {
bogdanm 82:6473597d706e 79 kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/
bogdanm 82:6473597d706e 80 kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/
bogdanm 82:6473597d706e 81 } dspi_clock_polarity_t;
bogdanm 82:6473597d706e 82
bogdanm 82:6473597d706e 83 /*! @brief DSPI clock phase configuration for a given CTAR*/
bogdanm 82:6473597d706e 84 typedef enum _dspi_clock_phase {
bogdanm 82:6473597d706e 85 kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and
bogdanm 82:6473597d706e 86 changed on the following edge.*/
bogdanm 82:6473597d706e 87 kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and
bogdanm 82:6473597d706e 88 captured on the following edge.*/
bogdanm 82:6473597d706e 89 } dspi_clock_phase_t;
bogdanm 82:6473597d706e 90
bogdanm 82:6473597d706e 91 /*! @brief DSPI data shifter direction options for a given CTAR*/
bogdanm 82:6473597d706e 92 typedef enum _dspi_shift_direction {
bogdanm 82:6473597d706e 93 kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/
bogdanm 82:6473597d706e 94 kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/
bogdanm 82:6473597d706e 95 } dspi_shift_direction_t;
bogdanm 82:6473597d706e 96
bogdanm 82:6473597d706e 97 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/
bogdanm 82:6473597d706e 98 typedef enum _dspi_ctar_selection {
bogdanm 82:6473597d706e 99 kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode*/
bogdanm 82:6473597d706e 100 kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only*/
bogdanm 82:6473597d706e 101 } dspi_ctar_selection_t;
bogdanm 82:6473597d706e 102
bogdanm 82:6473597d706e 103 /*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/
bogdanm 82:6473597d706e 104 typedef enum _dspi_pcs_polarity_config {
bogdanm 82:6473597d706e 105 kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low)*/
bogdanm 82:6473597d706e 106 kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high)*/
bogdanm 82:6473597d706e 107 } dspi_pcs_polarity_config_t;
bogdanm 82:6473597d706e 108
bogdanm 82:6473597d706e 109 /*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/
bogdanm 82:6473597d706e 110 typedef enum _dspi_which_pcs_config {
bogdanm 82:6473597d706e 111 kDspiPcs0 = 1 << 0, /*!< PCS[0] */
bogdanm 82:6473597d706e 112 kDspiPcs1 = 1 << 1, /*!< PCS[1] */
bogdanm 82:6473597d706e 113 kDspiPcs2 = 1 << 2, /*!< PCS[2] */
bogdanm 82:6473597d706e 114 kDspiPcs3 = 1 << 3, /*!< PCS[3] */
bogdanm 82:6473597d706e 115 kDspiPcs4 = 1 << 4, /*!< PCS[4] */
bogdanm 82:6473597d706e 116 kDspiPcs5 = 1 << 5 /*!< PCS[5] */
bogdanm 82:6473597d706e 117 } dspi_which_pcs_config_t;
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 /*!
bogdanm 82:6473597d706e 120 * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer
bogdanm 82:6473597d706e 121 * Format. This field is valid only when CPHA bit in CTAR register is 0.
bogdanm 82:6473597d706e 122 */
bogdanm 82:6473597d706e 123 typedef enum _dspi_master_sample_point {
bogdanm 82:6473597d706e 124 kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/
bogdanm 82:6473597d706e 125 kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/
bogdanm 82:6473597d706e 126 kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/
bogdanm 82:6473597d706e 127 } dspi_master_sample_point_t;
bogdanm 82:6473597d706e 128
bogdanm 82:6473597d706e 129 /*! @brief DSPI FIFO selects*/
bogdanm 82:6473597d706e 130 typedef enum _dspi_fifo {
bogdanm 82:6473597d706e 131 kDspiTxFifo = 0, /*!< DSPI Tx FIFO*/
bogdanm 82:6473597d706e 132 kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/
bogdanm 82:6473597d706e 133 } dspi_fifo_t;
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 /*! @brief DSPI status flags and interrupt request enable*/
bogdanm 82:6473597d706e 136 typedef enum _dspi_status_and_interrupt_request {
bogdanm 82:6473597d706e 137 kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */
bogdanm 82:6473597d706e 138 kDspiTxAndRxStatus = BP_SPI_SR_TXRXS, /*!< TXRXS status only, no interrupt*/
bogdanm 82:6473597d706e 139 kDspiEndOfQueue = BP_SPI_RSER_EOQF_RE, /*!< EOQF status/interrupt enable*/
bogdanm 82:6473597d706e 140 kDspiTxFifoUnderflow = BP_SPI_RSER_TFUF_RE, /*!< TFUF status/interrupt enable*/
bogdanm 82:6473597d706e 141 kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/
bogdanm 82:6473597d706e 142 kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/
bogdanm 82:6473597d706e 143 kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/
bogdanm 82:6473597d706e 144
bogdanm 82:6473597d706e 145 } dspi_status_and_interrupt_request_t;
bogdanm 82:6473597d706e 146
bogdanm 82:6473597d706e 147 /*! @brief DSPI FIFO counter or pointer defines based on bit positions*/
bogdanm 82:6473597d706e 148 typedef enum _dspi_fifo_counter_pointer {
bogdanm 82:6473597d706e 149 kDspiRxFifoPointer = BP_SPI_SR_POPNXTPTR, /*!< Rx FIFO pointer*/
bogdanm 82:6473597d706e 150 kDspiRxFifoCounter = BP_SPI_SR_RXCTR, /*!< Rx FIFO counter*/
bogdanm 82:6473597d706e 151 kDspiTxFifoPointer = BP_SPI_SR_TXNXTPTR, /*!< Tx FIFO pointer*/
bogdanm 82:6473597d706e 152 kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/
bogdanm 82:6473597d706e 153 } dspi_fifo_counter_pointer_t;
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 /*!
bogdanm 82:6473597d706e 156 * @brief DSPI data format settings configuration structure
bogdanm 82:6473597d706e 157 *
bogdanm 82:6473597d706e 158 * This structure contains the data format settings. These settings apply to a specific
bogdanm 82:6473597d706e 159 * CTARn register, which the user must provide in this structure.
bogdanm 82:6473597d706e 160 */
bogdanm 82:6473597d706e 161 typedef struct DspiDataFormatConfig {
bogdanm 82:6473597d706e 162 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 (master), 32 (slave) */
bogdanm 82:6473597d706e 163 dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/
bogdanm 82:6473597d706e 164 dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/
bogdanm 82:6473597d706e 165 dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction
bogdanm 82:6473597d706e 166 This setting relevant only in master mode and
bogdanm 82:6473597d706e 167 can be ignored in slave mode */
bogdanm 82:6473597d706e 168 } dspi_data_format_config_t;
bogdanm 82:6473597d706e 169
bogdanm 82:6473597d706e 170 /*!
bogdanm 82:6473597d706e 171 * @brief DSPI hardware configuration settings for master mode
bogdanm 82:6473597d706e 172 *
bogdanm 82:6473597d706e 173 * Use an instance of this structure with the dspi_hal_master_init() to configure the
bogdanm 82:6473597d706e 174 * most common settings of the DSPI peripheral in master mode with a single function call.
bogdanm 82:6473597d706e 175 *
bogdanm 82:6473597d706e 176 * The @c bitsPerSec member is handled in a special way. If this value is set to 0, then the baud is
bogdanm 82:6473597d706e 177 * not set by the dspi_hal_master_init(), and must be set with a separate call to either the
bogdanm 82:6473597d706e 178 * dspi_hal_set_baud() or the dspi_hal_set_baud_divisors(). This can be useful when you know the
bogdanm 82:6473597d706e 179 * divisors in advance and don't want to spend the time to compute them for the provided rate
bogdanm 82:6473597d706e 180 * in bits/sec.
bogdanm 82:6473597d706e 181 *
bogdanm 82:6473597d706e 182 * This structure also contains another structure template as a member:
bogdanm 82:6473597d706e 183 * @c dspi_data_format_config_t @c dataConfig.
bogdanm 82:6473597d706e 184 * An example usage for this is assuming declaration @c dspi_master_config_t
bogdanm 82:6473597d706e 185 * @c dspiConfig:
bogdanm 82:6473597d706e 186 @code
bogdanm 82:6473597d706e 187 dspiConfig.dataConfig.bitsPerFrame = 16;
bogdanm 82:6473597d706e 188 dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
bogdanm 82:6473597d706e 189 dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
bogdanm 82:6473597d706e 190 dspiConfig.dataConfig.direction = kDspiMsbFirst;
bogdanm 82:6473597d706e 191 @endcode
bogdanm 82:6473597d706e 192 */
bogdanm 82:6473597d706e 193 typedef struct DspiMasterConfig {
bogdanm 82:6473597d706e 194 bool isEnabled; /*!< Set to true to enable the DSPI peripheral.*/
bogdanm 82:6473597d706e 195 dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register (CTAR)*/
bogdanm 82:6473597d706e 196 uint32_t bitsPerSec; /*!< Baud rate in bits per second*/
bogdanm 82:6473597d706e 197 uint32_t sourceClockInHz; /*!< Module source clock */
bogdanm 82:6473597d706e 198 dspi_data_format_config_t dataConfig; /*!< Data format configuration structure*/
bogdanm 82:6473597d706e 199 bool isSckContinuous; /*!< Disable(0) or Enable(1) continuous SCK operation*/
bogdanm 82:6473597d706e 200 dspi_which_pcs_config_t whichPcs; /*!< Desired Peripheral Chip Select (PCS) */
bogdanm 82:6473597d706e 201 dspi_pcs_polarity_config_t pcsPolarity; /*!< Peripheral Chip Select (PCS) polarity setting.*/
bogdanm 82:6473597d706e 202 dspi_master_sample_point_t masterInSample; /*!< Master data-in (SIN) sample point setting.*/
bogdanm 82:6473597d706e 203 bool isModifiedTimingFormatEnabled; /*!< Disable(0) or Enable(1) modified timing format.*/
bogdanm 82:6473597d706e 204 bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
bogdanm 82:6473597d706e 205 bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
bogdanm 82:6473597d706e 206 } dspi_master_config_t;
bogdanm 82:6473597d706e 207
bogdanm 82:6473597d706e 208 /*!
bogdanm 82:6473597d706e 209 * @brief DSPI hardware configuration settings for slave mode.
bogdanm 82:6473597d706e 210 *
bogdanm 82:6473597d706e 211 * Use an instance of this structure with the dspi_hal_slave_init() to configure the
bogdanm 82:6473597d706e 212 * most common settings of the DSPI peripheral in slave mode with a single function call.
bogdanm 82:6473597d706e 213 */
bogdanm 82:6473597d706e 214 typedef struct DspiSlaveConfig {
bogdanm 82:6473597d706e 215 bool isEnabled; /*!< Set to true to enable the DSPI peripheral. */
bogdanm 82:6473597d706e 216 dspi_data_format_config_t dataConfig; /*!< Data format configuration structure */
bogdanm 82:6473597d706e 217 bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
bogdanm 82:6473597d706e 218 bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
bogdanm 82:6473597d706e 219 } dspi_slave_config_t;
bogdanm 82:6473597d706e 220
bogdanm 82:6473597d706e 221 /*!
bogdanm 82:6473597d706e 222 * @brief DSPI baud rate divisors settings configuration structure.
bogdanm 82:6473597d706e 223 *
bogdanm 82:6473597d706e 224 * Note: These settings are relevant only in master mode.
bogdanm 82:6473597d706e 225 * This structure contains the baud rate divisor settings, which provides the user with the option to
bogdanm 82:6473597d706e 226 * explicitly set these baud rate divisors. In addition, the user must also set the
bogdanm 82:6473597d706e 227 * CTARn register with the divisor settings.
bogdanm 82:6473597d706e 228 */
bogdanm 82:6473597d706e 229 typedef struct DspiBaudRateDivisors {
bogdanm 82:6473597d706e 230 bool doubleBaudRate; /*!< Double Baud rate parameter setting */
bogdanm 82:6473597d706e 231 uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/
bogdanm 82:6473597d706e 232 uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */
bogdanm 82:6473597d706e 233 } dspi_baud_rate_divisors_t;
bogdanm 82:6473597d706e 234
bogdanm 82:6473597d706e 235 /*!
bogdanm 82:6473597d706e 236 * @brief DSPI delay settings configuration structure
bogdanm 82:6473597d706e 237 *
bogdanm 82:6473597d706e 238 * Note: These settings are relevant only in master mode.
bogdanm 82:6473597d706e 239 * This structure contains the various delay settings. These settings apply to a specific
bogdanm 82:6473597d706e 240 * CTARn register, which the user must provide in this structure.
bogdanm 82:6473597d706e 241 */
bogdanm 82:6473597d706e 242 typedef struct DspiDelaySettingsConfig {
bogdanm 82:6473597d706e 243 uint32_t pcsToSckPre; /*!< PCS to SCK delay pre-scalar (PCSSCK) */
bogdanm 82:6473597d706e 244 uint32_t pcsToSck; /*!< PCS to SCK Delay scalar (CSSCK) */
bogdanm 82:6473597d706e 245 uint32_t afterSckPre; /*!< After SCK delay pre-scalar (PASC)*/
bogdanm 82:6473597d706e 246 uint32_t afterSck; /*!< After SCK delay scalar (ASC)*/
bogdanm 82:6473597d706e 247 uint32_t afterTransferPre; /*!< Delay after transfer pre-scalar (PDT)*/
bogdanm 82:6473597d706e 248 uint32_t afterTransfer; /*!< Delay after transfer scalar (DT) */
bogdanm 82:6473597d706e 249 } dspi_delay_settings_config_t;
bogdanm 82:6473597d706e 250
bogdanm 82:6473597d706e 251 /*!
bogdanm 82:6473597d706e 252 * @brief DSPI command and data configuration structure
bogdanm 82:6473597d706e 253 *
bogdanm 82:6473597d706e 254 * Note: This structure is used with the PUSHR register, which
bogdanm 82:6473597d706e 255 * provides the means to write to the Tx FIFO. Data written to this register is
bogdanm 82:6473597d706e 256 * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all
bogdanm 82:6473597d706e 257 * 32 register bits to the Tx FIFO. The register structure is different in master and slave
bogdanm 82:6473597d706e 258 * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx
bogdanm 82:6473597d706e 259 * FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
bogdanm 82:6473597d706e 260 * frame operation.
bogdanm 82:6473597d706e 261 */
bogdanm 82:6473597d706e 262 typedef struct DspiCommandDataConfig {
bogdanm 82:6473597d706e 263 bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select
bogdanm 82:6473597d706e 264 between transfers*/
bogdanm 82:6473597d706e 265 dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
bogdanm 82:6473597d706e 266 Register (CTAR) to use for CTAS*/
bogdanm 82:6473597d706e 267 dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/
bogdanm 82:6473597d706e 268 bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/
bogdanm 82:6473597d706e 269 bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/
bogdanm 82:6473597d706e 270 } dspi_command_config_t;
bogdanm 82:6473597d706e 271
bogdanm 82:6473597d706e 272 /*******************************************************************************
bogdanm 82:6473597d706e 273 * API
bogdanm 82:6473597d706e 274 ******************************************************************************/
bogdanm 82:6473597d706e 275
bogdanm 82:6473597d706e 276 #if defined(__cplusplus)
bogdanm 82:6473597d706e 277 extern "C" {
bogdanm 82:6473597d706e 278 #endif
bogdanm 82:6473597d706e 279
bogdanm 82:6473597d706e 280 /*!
bogdanm 82:6473597d706e 281 * @name Configuration
bogdanm 82:6473597d706e 282 * @{
bogdanm 82:6473597d706e 283 */
bogdanm 82:6473597d706e 284
bogdanm 82:6473597d706e 285 /*!
bogdanm 82:6473597d706e 286 * @brief Configure the DSPI peripheral in master mode
bogdanm 82:6473597d706e 287 *
bogdanm 82:6473597d706e 288 * This function initializes the module to the user defined settings and default settings in master
bogdanm 82:6473597d706e 289 * mode. This is an example demonstrating how to define the dspi_master_config_t structure and call
bogdanm 82:6473597d706e 290 * the dspi_hal_master_init function:
bogdanm 82:6473597d706e 291 @code
bogdanm 82:6473597d706e 292 dspi_master_config_t dspiConfig;
bogdanm 82:6473597d706e 293 dspiConfig.isEnabled = false;
bogdanm 82:6473597d706e 294 dspiConfig.whichCtar = kDspiCtar0;
bogdanm 82:6473597d706e 295 dspiConfig.bitsPerSec = 0;
bogdanm 82:6473597d706e 296 dspiConfig.sourceClockInHz = dspiSourceClock;
bogdanm 82:6473597d706e 297 dspiConfig.isSckContinuous = false;
bogdanm 82:6473597d706e 298 dspiConfig.whichPcs = kDspiPcs0;
bogdanm 82:6473597d706e 299 dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
bogdanm 82:6473597d706e 300 dspiConfig.masterInSample = kDspiSckToSin_0Clock;
bogdanm 82:6473597d706e 301 dspiConfig.isModifiedTimingFormatEnabled = false;
bogdanm 82:6473597d706e 302 dspiConfig.isTxFifoDisabled = false;
bogdanm 82:6473597d706e 303 dspiConfig.isRxFifoDisabled = false;
bogdanm 82:6473597d706e 304 dspiConfig.dataConfig.bitsPerFrame = 16;
bogdanm 82:6473597d706e 305 dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
bogdanm 82:6473597d706e 306 dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
bogdanm 82:6473597d706e 307 dspiConfig.dataConfig.direction = kDspiMsbFirst;
bogdanm 82:6473597d706e 308 dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
bogdanm 82:6473597d706e 309 @endcode
bogdanm 82:6473597d706e 310 *
bogdanm 82:6473597d706e 311 * @param instance Module instance number
bogdanm 82:6473597d706e 312 * @param config Pointer to the master mode configuration data structure
bogdanm 82:6473597d706e 313 * @param calculatedBaudRate The calculated baud rate passed back to the user for them to determine
bogdanm 82:6473597d706e 314 * if the calculated baud rate is close enough to meet their needs.
bogdanm 82:6473597d706e 315 * @return An error code or kStatus_DSPI_Success.
bogdanm 82:6473597d706e 316 */
bogdanm 82:6473597d706e 317 dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
bogdanm 82:6473597d706e 318 uint32_t * calculatedBaudRate);
bogdanm 82:6473597d706e 319
bogdanm 82:6473597d706e 320 /*!
bogdanm 82:6473597d706e 321 * @brief Configures the DSPI peripheral in slave mode.
bogdanm 82:6473597d706e 322 *
bogdanm 82:6473597d706e 323 * This function initializes the DSPI module for slave mode. This is an example demonstrating how
bogdanm 82:6473597d706e 324 * to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
bogdanm 82:6473597d706e 325 @code
bogdanm 82:6473597d706e 326 dspi_slave_config_t dspiConfig;
bogdanm 82:6473597d706e 327 dspiConfig.isEnabled = false;
bogdanm 82:6473597d706e 328 dspiConfig.isTxFifoDisabled = false;
bogdanm 82:6473597d706e 329 dspiConfig.isRxFifoDisabled = false;
bogdanm 82:6473597d706e 330 dspiConfig.dataConfig.bitsPerFrame = 16;
bogdanm 82:6473597d706e 331 dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
bogdanm 82:6473597d706e 332 dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
bogdanm 82:6473597d706e 333 dspi_hal_slave_init(instance, &dspiConfig);
bogdanm 82:6473597d706e 334 @endcode
bogdanm 82:6473597d706e 335 *
bogdanm 82:6473597d706e 336 * @param instance Module instance number
bogdanm 82:6473597d706e 337 * @param config Pointer to the slave mode configuration data structure
bogdanm 82:6473597d706e 338 * @return An error code or kStatus_DSPI_Success.
bogdanm 82:6473597d706e 339 */
bogdanm 82:6473597d706e 340 dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config);
bogdanm 82:6473597d706e 341
bogdanm 82:6473597d706e 342 /*!
bogdanm 82:6473597d706e 343 * @brief Restores the DSPI to reset the configuration.
bogdanm 82:6473597d706e 344 *
bogdanm 82:6473597d706e 345 * This function basically resets all of the DSPI registers to their default setting including
bogdanm 82:6473597d706e 346 * disabling the module.
bogdanm 82:6473597d706e 347 *
bogdanm 82:6473597d706e 348 * @param instance Module instance number
bogdanm 82:6473597d706e 349 */
bogdanm 82:6473597d706e 350 void dspi_hal_reset(uint32_t instance);
bogdanm 82:6473597d706e 351
bogdanm 82:6473597d706e 352 /*!
bogdanm 82:6473597d706e 353 * @brief Enable the DSPI peripheral, set MCR MDIS to 0.
bogdanm 82:6473597d706e 354 *
bogdanm 82:6473597d706e 355 * @param instance Module instance number
bogdanm 82:6473597d706e 356 */
bogdanm 82:6473597d706e 357 static inline void dspi_hal_enable(uint32_t instance)
bogdanm 82:6473597d706e 358 {
bogdanm 82:6473597d706e 359 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 360 HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
bogdanm 82:6473597d706e 361 }
bogdanm 82:6473597d706e 362
bogdanm 82:6473597d706e 363 /*!
bogdanm 82:6473597d706e 364 * @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
bogdanm 82:6473597d706e 365 *
bogdanm 82:6473597d706e 366 * @param instance Module instance number
bogdanm 82:6473597d706e 367 */
bogdanm 82:6473597d706e 368 static inline void dspi_hal_disable(uint32_t instance)
bogdanm 82:6473597d706e 369 {
bogdanm 82:6473597d706e 370 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 371 HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
bogdanm 82:6473597d706e 372 }
bogdanm 82:6473597d706e 373
bogdanm 82:6473597d706e 374 /*!
bogdanm 82:6473597d706e 375 * @brief Sets the DSPI baud rate in bits per second.
bogdanm 82:6473597d706e 376 *
bogdanm 82:6473597d706e 377 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
bogdanm 82:6473597d706e 378 * possible baud rate without exceeding the desired baud rate, and returns the calculated
bogdanm 82:6473597d706e 379 * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
bogdanm 82:6473597d706e 380 * module source clock (in Hertz).
bogdanm 82:6473597d706e 381 *
bogdanm 82:6473597d706e 382 * @param instance Module instance number
bogdanm 82:6473597d706e 383 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
bogdanm 82:6473597d706e 384 * dspi_ctar_selection_t
bogdanm 82:6473597d706e 385 * @param bitsPerSec The desired baud rate in bits per second
bogdanm 82:6473597d706e 386 * @param sourceClockInHz Module source input clock in Hertz
bogdanm 82:6473597d706e 387 * @return The actual calculated baud rate
bogdanm 82:6473597d706e 388 */
bogdanm 82:6473597d706e 389 uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
bogdanm 82:6473597d706e 390 uint32_t sourceClockInHz);
bogdanm 82:6473597d706e 391
bogdanm 82:6473597d706e 392 /*!
bogdanm 82:6473597d706e 393 * @brief Configures the baud rate divisors manually.
bogdanm 82:6473597d706e 394 *
bogdanm 82:6473597d706e 395 * This function allows the caller to manually set the baud rate divisors in the event that
bogdanm 82:6473597d706e 396 * these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
bogdanm 82:6473597d706e 397 *
bogdanm 82:6473597d706e 398 * @param instance Module instance number
bogdanm 82:6473597d706e 399 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
bogdanm 82:6473597d706e 400 * dspi_ctar_selection_t
bogdanm 82:6473597d706e 401 * @param divisors Pointer to a structure containing the user defined baud rate divisor settings
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403 void dspi_hal_set_baud_divisors(uint32_t instance,
bogdanm 82:6473597d706e 404 dspi_ctar_selection_t whichCtar,
bogdanm 82:6473597d706e 405 const dspi_baud_rate_divisors_t * divisors);
bogdanm 82:6473597d706e 406
bogdanm 82:6473597d706e 407 /*!
bogdanm 82:6473597d706e 408 * @brief Configures the DSPI for master or slave.
bogdanm 82:6473597d706e 409 *
bogdanm 82:6473597d706e 410 * @param instance Module instance number
bogdanm 82:6473597d706e 411 * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
bogdanm 82:6473597d706e 412 */
bogdanm 82:6473597d706e 413 static inline void dspi_hal_set_master_slave(uint32_t instance, dspi_master_slave_mode_t mode)
bogdanm 82:6473597d706e 414 {
bogdanm 82:6473597d706e 415 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 416 BW_SPI_MCR_MSTR(instance, (uint32_t)mode);
bogdanm 82:6473597d706e 417 }
bogdanm 82:6473597d706e 418
bogdanm 82:6473597d706e 419 /*!
bogdanm 82:6473597d706e 420 * @brief Configures the DSPI for the continuous SCK operation.
bogdanm 82:6473597d706e 421 *
bogdanm 82:6473597d706e 422 * @param instance Module instance number
bogdanm 82:6473597d706e 423 * @param enable Enables (true) or disables(false) continuous SCK operation.
bogdanm 82:6473597d706e 424 */
bogdanm 82:6473597d706e 425 static inline void dspi_hal_configure_continuous_sck(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 426 {
bogdanm 82:6473597d706e 427 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 428 BW_SPI_MCR_CONT_SCKE(instance, (enable == true));
bogdanm 82:6473597d706e 429 }
bogdanm 82:6473597d706e 430
bogdanm 82:6473597d706e 431 /*!
bogdanm 82:6473597d706e 432 * @brief Configures the DSPI to enable modified timing format.
bogdanm 82:6473597d706e 433 *
bogdanm 82:6473597d706e 434 * @param instance Module instance number
bogdanm 82:6473597d706e 435 * @param enable Enables (true) or disables(false) modified timing format.
bogdanm 82:6473597d706e 436 */
bogdanm 82:6473597d706e 437 static inline void dspi_hal_configure_modified_timing_format(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 438 {
bogdanm 82:6473597d706e 439 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 440 BW_SPI_MCR_MTFE(instance, (enable == true));
bogdanm 82:6473597d706e 441 }
bogdanm 82:6473597d706e 442
bogdanm 82:6473597d706e 443 /*!
bogdanm 82:6473597d706e 444 * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the
bogdanm 82:6473597d706e 445 * active-low PCS Strobe output.
bogdanm 82:6473597d706e 446 *
bogdanm 82:6473597d706e 447 * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral
bogdanm 82:6473597d706e 448 * Chip Select in master mode. When configured as a strobe, it provides a signal to an external
bogdanm 82:6473597d706e 449 * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
bogdanm 82:6473597d706e 450 *
bogdanm 82:6473597d706e 451 * @param instance Module instance number
bogdanm 82:6473597d706e 452 * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
bogdanm 82:6473597d706e 453 * If disable (false), PCS[5] operates as a peripheral chip select
bogdanm 82:6473597d706e 454 */
bogdanm 82:6473597d706e 455 static inline void dspi_hal_configure_pcs_strobe(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 456 {
bogdanm 82:6473597d706e 457 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 458 BW_SPI_MCR_PCSSE(instance, (enable == true));
bogdanm 82:6473597d706e 459 }
bogdanm 82:6473597d706e 460
bogdanm 82:6473597d706e 461 /*!
bogdanm 82:6473597d706e 462 * @brief Configures the DSPI received FIFO overflow overwrite enable.
bogdanm 82:6473597d706e 463 *
bogdanm 82:6473597d706e 464 * When enabled, this function allows incoming receive data to overwrite the existing data in the
bogdanm 82:6473597d706e 465 * receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data
bogdanm 82:6473597d706e 466 * is ignored when the RX FIFO is full.
bogdanm 82:6473597d706e 467 *
bogdanm 82:6473597d706e 468 * @param instance Module instance number.
bogdanm 82:6473597d706e 469 * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
bogdanm 82:6473597d706e 470 * else incoming data is ignored.
bogdanm 82:6473597d706e 471 */
bogdanm 82:6473597d706e 472 static inline void dspi_hal_configure_rx_fifo_overwrite(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 473 {
bogdanm 82:6473597d706e 474 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 475 BW_SPI_MCR_ROOE(instance, (enable == true));
bogdanm 82:6473597d706e 476 }
bogdanm 82:6473597d706e 477
bogdanm 82:6473597d706e 478 /*!
bogdanm 82:6473597d706e 479 * @brief Configures the DSPI peripheral chip select polarity.
bogdanm 82:6473597d706e 480 *
bogdanm 82:6473597d706e 481 * This function takes in the desired peripheral chip select (PCS) and it's
bogdanm 82:6473597d706e 482 * corresponding desired polarity and configures the PCS signal to operate with the
bogdanm 82:6473597d706e 483 * desired characteristic.
bogdanm 82:6473597d706e 484 *
bogdanm 82:6473597d706e 485 * @param instance Module instance number
bogdanm 82:6473597d706e 486 * @param pcs The particular peripheral chip select (parameter value is of type
bogdanm 82:6473597d706e 487 * dspi_which_pcs_config_t) for which we wish to apply the active high or active
bogdanm 82:6473597d706e 488 * low characteristic.
bogdanm 82:6473597d706e 489 * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or
bogdanm 82:6473597d706e 490 * "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
bogdanm 82:6473597d706e 491 */
bogdanm 82:6473597d706e 492 void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
bogdanm 82:6473597d706e 493 dspi_pcs_polarity_config_t activeLowOrHigh);
bogdanm 82:6473597d706e 494
bogdanm 82:6473597d706e 495 /*!
bogdanm 82:6473597d706e 496 * @brief Configures the DSPI FIFOs.
bogdanm 82:6473597d706e 497 *
bogdanm 82:6473597d706e 498 * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
bogdanm 82:6473597d706e 499 * Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
bogdanm 82:6473597d706e 500 * configuration. To enable, the caller must pass in a logic 0 (false). For example, to enable
bogdanm 82:6473597d706e 501 * both the Tx and Rx FIFOs, the caller makes this function call (where instance is the
bogdanm 82:6473597d706e 502 * desired module instance number):
bogdanm 82:6473597d706e 503 @code
bogdanm 82:6473597d706e 504 dspi_hal_configure_fifos(instance, false, false);
bogdanm 82:6473597d706e 505 @endcode
bogdanm 82:6473597d706e 506 *
bogdanm 82:6473597d706e 507 * @param instance Module instance number
bogdanm 82:6473597d706e 508 * @param disableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
bogdanm 82:6473597d706e 509 * @param disableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
bogdanm 82:6473597d706e 510 */
bogdanm 82:6473597d706e 511 void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo);
bogdanm 82:6473597d706e 512
bogdanm 82:6473597d706e 513 /*!
bogdanm 82:6473597d706e 514 * @brief Flushes the DSPI FIFOs.
bogdanm 82:6473597d706e 515 *
bogdanm 82:6473597d706e 516 * @param instance Module instance number
bogdanm 82:6473597d706e 517 * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
bogdanm 82:6473597d706e 518 * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
bogdanm 82:6473597d706e 519 */
bogdanm 82:6473597d706e 520 void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo);
bogdanm 82:6473597d706e 521
bogdanm 82:6473597d706e 522
bogdanm 82:6473597d706e 523 /*!
bogdanm 82:6473597d706e 524 * @brief Configures when the DSPI master samples SIN in the Modified Transfer Format
bogdanm 82:6473597d706e 525 *
bogdanm 82:6473597d706e 526 * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
bogdanm 82:6473597d706e 527 * Format. Note that this is valid only when the CPHA bit in the CTAR register is 0.
bogdanm 82:6473597d706e 528 *
bogdanm 82:6473597d706e 529 * @param instance Module instance number
bogdanm 82:6473597d706e 530 * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
bogdanm 82:6473597d706e 531 * This value selects either 0, 1, or 2 system clocks between the SCK edge
bogdanm 82:6473597d706e 532 * and the SIN (data in) sample.
bogdanm 82:6473597d706e 533 */
bogdanm 82:6473597d706e 534 static inline void dspi_hal_set_datain_samplepoint(uint32_t instance,
bogdanm 82:6473597d706e 535 dspi_master_sample_point_t samplePnt)
bogdanm 82:6473597d706e 536 {
bogdanm 82:6473597d706e 537 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 538 BW_SPI_MCR_SMPL_PT(instance, samplePnt);
bogdanm 82:6473597d706e 539 }
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541
bogdanm 82:6473597d706e 542 /*!
bogdanm 82:6473597d706e 543 * @brief Starts the DSPI transfers, clears HALT bit in MCR.
bogdanm 82:6473597d706e 544 *
bogdanm 82:6473597d706e 545 * This function call called whenever the module is ready to begin data transfers in either master
bogdanm 82:6473597d706e 546 * or slave mode.
bogdanm 82:6473597d706e 547 *
bogdanm 82:6473597d706e 548 * @param instance Module instance number
bogdanm 82:6473597d706e 549 */
bogdanm 82:6473597d706e 550 static inline void dspi_hal_start_transfer(uint32_t instance)
bogdanm 82:6473597d706e 551 {
bogdanm 82:6473597d706e 552 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 553 HW_SPI_MCR_CLR(instance, BM_SPI_MCR_HALT);
bogdanm 82:6473597d706e 554 }
bogdanm 82:6473597d706e 555
bogdanm 82:6473597d706e 556 /*!
bogdanm 82:6473597d706e 557 * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR.
bogdanm 82:6473597d706e 558 *
bogdanm 82:6473597d706e 559 * This function call stops data transfers in either master or slave mode.
bogdanm 82:6473597d706e 560 *
bogdanm 82:6473597d706e 561 * @param instance Module instance number
bogdanm 82:6473597d706e 562 */
bogdanm 82:6473597d706e 563 static inline void dspi_hal_stop_transfer(uint32_t instance)
bogdanm 82:6473597d706e 564 {
bogdanm 82:6473597d706e 565 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 566 HW_SPI_MCR_SET(instance, BM_SPI_MCR_HALT);
bogdanm 82:6473597d706e 567 }
bogdanm 82:6473597d706e 568
bogdanm 82:6473597d706e 569 /*!
bogdanm 82:6473597d706e 570 * @brief Configures the data format for a particular CTAR.
bogdanm 82:6473597d706e 571 *
bogdanm 82:6473597d706e 572 * This function configures the bits-per-frame, polarity, phase, and shift direction for a
bogdanm 82:6473597d706e 573 * particular CTAR. An example use case is as follows:
bogdanm 82:6473597d706e 574 @code
bogdanm 82:6473597d706e 575 dspi_data_format_config_t dataFormat;
bogdanm 82:6473597d706e 576 dataFormat.bitsPerFrame = 16;
bogdanm 82:6473597d706e 577 dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
bogdanm 82:6473597d706e 578 dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
bogdanm 82:6473597d706e 579 dataFormat.direction = kDspiMsbFirst;
bogdanm 82:6473597d706e 580 dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
bogdanm 82:6473597d706e 581 @endcode
bogdanm 82:6473597d706e 582 *
bogdanm 82:6473597d706e 583 * @param instance Module instance number
bogdanm 82:6473597d706e 584 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
bogdanm 82:6473597d706e 585 * dspi_ctar_selection_t.
bogdanm 82:6473597d706e 586 * @param config Pointer to a structure containing the user defined data format configuration settings.
bogdanm 82:6473597d706e 587 * @return An error code or kStatus_DSPI_Success
bogdanm 82:6473597d706e 588 */
bogdanm 82:6473597d706e 589 dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
bogdanm 82:6473597d706e 590 dspi_ctar_selection_t whichCtar,
bogdanm 82:6473597d706e 591 const dspi_data_format_config_t * config);
bogdanm 82:6473597d706e 592
bogdanm 82:6473597d706e 593 /*!
bogdanm 82:6473597d706e 594 * @brief Configures the delays for a particular CTAR, master mode only.
bogdanm 82:6473597d706e 595 *
bogdanm 82:6473597d706e 596 * This function configures the PCS to SCK delay pre-scalar (PCSSCK),
bogdanm 82:6473597d706e 597 * the PCS to SCK Delay scalar (CSSCK),
bogdanm 82:6473597d706e 598 * the After SCK delay pre-scalar (PASC),
bogdanm 82:6473597d706e 599 * the After SCK delay scalar (ASC),
bogdanm 82:6473597d706e 600 * the Delay after transfer pre-scalar (PDT),
bogdanm 82:6473597d706e 601 * and the Delay after transfer scalar (DT).
bogdanm 82:6473597d706e 602 * The following is an example use case of this function:
bogdanm 82:6473597d706e 603 * @code
bogdanm 82:6473597d706e 604 dspi_delay_settings_config_t delayConfig;
bogdanm 82:6473597d706e 605 delayConfig.pcsToSckPre = 0x3;
bogdanm 82:6473597d706e 606 delayConfig.pcsToSck = 0xF;
bogdanm 82:6473597d706e 607 delayConfig.afterSckPre = 0x2;
bogdanm 82:6473597d706e 608 delayConfig.afterSck = 0xA;
bogdanm 82:6473597d706e 609 delayConfig.afterTransferPre = 0x1;
bogdanm 82:6473597d706e 610 delayConfig.afterTransfer = 0x5;
bogdanm 82:6473597d706e 611 dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
bogdanm 82:6473597d706e 612 * @endcode
bogdanm 82:6473597d706e 613 *
bogdanm 82:6473597d706e 614 * @param instance Module instance number
bogdanm 82:6473597d706e 615 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
bogdanm 82:6473597d706e 616 * dspi_ctar_selection_t.
bogdanm 82:6473597d706e 617 * @param config Pointer to a structure containing the user defined delay configuration settings.
bogdanm 82:6473597d706e 618 */
bogdanm 82:6473597d706e 619 void dspi_hal_configure_delays(uint32_t instance,
bogdanm 82:6473597d706e 620 dspi_ctar_selection_t whichCtar,
bogdanm 82:6473597d706e 621 const dspi_delay_settings_config_t * config);
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 /*@}*/
bogdanm 82:6473597d706e 624
bogdanm 82:6473597d706e 625 /*!
bogdanm 82:6473597d706e 626 * @name DMA
bogdanm 82:6473597d706e 627 * @{
bogdanm 82:6473597d706e 628 */
bogdanm 82:6473597d706e 629
bogdanm 82:6473597d706e 630 /*!
bogdanm 82:6473597d706e 631 * @brief Configures transmit and receive DMA requests.
bogdanm 82:6473597d706e 632 *
bogdanm 82:6473597d706e 633 * This function configures the FIFOs to generate a DMA or an interrupt request. Note that the
bogdanm 82:6473597d706e 634 * corresponding request enable must also be set. For the Transmit FIFO Fill, in order
bogdanm 82:6473597d706e 635 * to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
bogdanm 82:6473597d706e 636 * Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
bogdanm 82:6473597d706e 637 * Request Enable (RFDF_RE) must also be set. These requests can be configured with
bogdanm 82:6473597d706e 638 * the function dspi_hal_configure_interrupt(). To enable DMA operation, first enable
bogdanm 82:6473597d706e 639 * the desired request enable by using the dspi_hal_configure_interrupt() function and then use
bogdanm 82:6473597d706e 640 * the dspi_hal_configure_dma() to configure the request and generate a DMA request.
bogdanm 82:6473597d706e 641 *
bogdanm 82:6473597d706e 642 * @param enableTransmit Configures Tx FIFO fill request to generate a DMA or interrupt request
bogdanm 82:6473597d706e 643 * @param enableReceive Configures Rx FIFO fill request to generate a DMA or interrupt request
bogdanm 82:6473597d706e 644 */
bogdanm 82:6473597d706e 645 void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive);
bogdanm 82:6473597d706e 646
bogdanm 82:6473597d706e 647 /*@}*/
bogdanm 82:6473597d706e 648
bogdanm 82:6473597d706e 649 /*!
bogdanm 82:6473597d706e 650 * @name Low power
bogdanm 82:6473597d706e 651 * @{
bogdanm 82:6473597d706e 652 */
bogdanm 82:6473597d706e 653
bogdanm 82:6473597d706e 654 /*!
bogdanm 82:6473597d706e 655 * @brief Configures the DSPI operation during doze mode.
bogdanm 82:6473597d706e 656 *
bogdanm 82:6473597d706e 657 * This function provides support for an externally controlled doze mode, power-saving, mechanism.
bogdanm 82:6473597d706e 658 * When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode
bogdanm 82:6473597d706e 659 * disables the DSPI.
bogdanm 82:6473597d706e 660 *
bogdanm 82:6473597d706e 661 * @param instance Module instance number
bogdanm 82:6473597d706e 662 * @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true), the doze mode
bogdanm 82:6473597d706e 663 * disables the DSPI.
bogdanm 82:6473597d706e 664 */
bogdanm 82:6473597d706e 665 static inline void dspi_hal_configure_doze_mode(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 666 {
bogdanm 82:6473597d706e 667 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 668 BW_SPI_MCR_DOZE(instance, (enable == true));
bogdanm 82:6473597d706e 669 }
bogdanm 82:6473597d706e 670
bogdanm 82:6473597d706e 671 /*@}*/
bogdanm 82:6473597d706e 672
bogdanm 82:6473597d706e 673 /*!
bogdanm 82:6473597d706e 674 * @name Interrupts
bogdanm 82:6473597d706e 675 * @{
bogdanm 82:6473597d706e 676 */
bogdanm 82:6473597d706e 677
bogdanm 82:6473597d706e 678 /*!
bogdanm 82:6473597d706e 679 * @brief Configures the DSPI interrupts.
bogdanm 82:6473597d706e 680 *
bogdanm 82:6473597d706e 681 * This function configures the various interrupt sources of the DSPI. The parameters are instance, interrupt source, and enable/disable setting.
bogdanm 82:6473597d706e 682 * The interrupt source is a typedef enum whose value is the bit position of the
bogdanm 82:6473597d706e 683 * interrupt source setting within the RSER register. In the DSPI, all interrupt
bogdanm 82:6473597d706e 684 * configuration settings are in one register. The typedef enum equates each
bogdanm 82:6473597d706e 685 * interrupt source to the bit position defined in the device header file.
bogdanm 82:6473597d706e 686 * The function uses these bit positions in its algorithm to enable/disable the
bogdanm 82:6473597d706e 687 * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
bogdanm 82:6473597d706e 688 * @code
bogdanm 82:6473597d706e 689 temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
bogdanm 82:6473597d706e 690 HW_SPI_RSER_WR(instance, temp);
bogdanm 82:6473597d706e 691
bogdanm 82:6473597d706e 692 dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
bogdanm 82:6473597d706e 693 * @endcode
bogdanm 82:6473597d706e 694 *
bogdanm 82:6473597d706e 695 * @param instance Module instance number
bogdanm 82:6473597d706e 696 * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
bogdanm 82:6473597d706e 697 * @param enable Enable (true) or disable (false) the interrupt source to generate requests
bogdanm 82:6473597d706e 698 */
bogdanm 82:6473597d706e 699 void dspi_hal_configure_interrupt(uint32_t instance,
bogdanm 82:6473597d706e 700 dspi_status_and_interrupt_request_t interruptSrc,
bogdanm 82:6473597d706e 701 bool enable);
bogdanm 82:6473597d706e 702
bogdanm 82:6473597d706e 703
bogdanm 82:6473597d706e 704 /*!
bogdanm 82:6473597d706e 705 * @brief Gets the DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
bogdanm 82:6473597d706e 706 *
bogdanm 82:6473597d706e 707 * This function returns the requested interrupt source setting (enabled or disabled, of
bogdanm 82:6473597d706e 708 * type bool). The parameters to pass in are instance and interrupt source. It utilizes the
bogdanm 82:6473597d706e 709 * same enum definitions for the interrupt sources as described in the "interrupt configuration"
bogdanm 82:6473597d706e 710 * function. The function uses these bit positions in its algorithm to obtain the desired
bogdanm 82:6473597d706e 711 * interrupt source setting.
bogdanm 82:6473597d706e 712 * @code
bogdanm 82:6473597d706e 713 return ((HW_SPI_RSER_RD(instance) & interruptSrc) >> interruptSrc);
bogdanm 82:6473597d706e 714
bogdanm 82:6473597d706e 715 getInterruptSetting = dspi_hal_get_interrupt_config(instance, kDspiTxComplete);
bogdanm 82:6473597d706e 716 * @endcode
bogdanm 82:6473597d706e 717 *
bogdanm 82:6473597d706e 718 * @param instance Module instance number
bogdanm 82:6473597d706e 719 * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
bogdanm 82:6473597d706e 720 * @return Configuration of interrupt request: enable (true) or disable (false).
bogdanm 82:6473597d706e 721 */
bogdanm 82:6473597d706e 722 static inline bool dspi_hal_get_interrupt_config(uint32_t instance,
bogdanm 82:6473597d706e 723 dspi_status_and_interrupt_request_t interruptSrc)
bogdanm 82:6473597d706e 724 {
bogdanm 82:6473597d706e 725 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 726 return ((HW_SPI_RSER_RD(instance) >> interruptSrc) & 0x1);
bogdanm 82:6473597d706e 727 }
bogdanm 82:6473597d706e 728
bogdanm 82:6473597d706e 729 /*@}*/
bogdanm 82:6473597d706e 730
bogdanm 82:6473597d706e 731 /*!
bogdanm 82:6473597d706e 732 * @name Status
bogdanm 82:6473597d706e 733 * @{
bogdanm 82:6473597d706e 734 */
bogdanm 82:6473597d706e 735
bogdanm 82:6473597d706e 736 /*!
bogdanm 82:6473597d706e 737 * @brief Gets the DSPI status flag state.
bogdanm 82:6473597d706e 738 *
bogdanm 82:6473597d706e 739 * The status flag is defined in the same enum as the interrupt source enable because the bit
bogdanm 82:6473597d706e 740 * position of the interrupt source and corresponding status flag are the same in the RSER and
bogdanm 82:6473597d706e 741 * SR registers. The function uses these bit positions in its algorithm to obtain the desired
bogdanm 82:6473597d706e 742 * flag state, similar to the dspi_get_interrupt_config function.
bogdanm 82:6473597d706e 743 * @code
bogdanm 82:6473597d706e 744 return ((HW_SPI_SR_RD(instance) & statusFlag) >> statusFlag);
bogdanm 82:6473597d706e 745
bogdanm 82:6473597d706e 746 getStatus = dspi_hal_get_status_flag(instance, kDspiTxComplete);
bogdanm 82:6473597d706e 747 * @endcode
bogdanm 82:6473597d706e 748 *
bogdanm 82:6473597d706e 749 * @param instance Module instance number
bogdanm 82:6473597d706e 750 * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
bogdanm 82:6473597d706e 751 * @return State of the status flag: asserted (true) or not-asserted (false)
bogdanm 82:6473597d706e 752 */
bogdanm 82:6473597d706e 753 static inline bool dspi_hal_get_status_flag(uint32_t instance,
bogdanm 82:6473597d706e 754 dspi_status_and_interrupt_request_t statusFlag)
bogdanm 82:6473597d706e 755 {
bogdanm 82:6473597d706e 756 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 757 return ((HW_SPI_SR_RD(instance) >> statusFlag) & 0x1);
bogdanm 82:6473597d706e 758 }
bogdanm 82:6473597d706e 759
bogdanm 82:6473597d706e 760 /*!
bogdanm 82:6473597d706e 761 * @brief Clears the DSPI status flag.
bogdanm 82:6473597d706e 762 *
bogdanm 82:6473597d706e 763 * This function clears the desired status bit by using a write-1-to-clear. The user passes in
bogdanm 82:6473597d706e 764 * the instance and the desired status bit to clear. The list of status bits is defined in the
bogdanm 82:6473597d706e 765 * dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm
bogdanm 82:6473597d706e 766 * to clear the desired flag state. It uses this macro:
bogdanm 82:6473597d706e 767 * @code
bogdanm 82:6473597d706e 768 HW_SPI_SR_WR(instance, statusFlag);
bogdanm 82:6473597d706e 769
bogdanm 82:6473597d706e 770 dspi_hal_clear_status_flag(instance, kDspiTxComplete);
bogdanm 82:6473597d706e 771 * @endcode
bogdanm 82:6473597d706e 772 *
bogdanm 82:6473597d706e 773 * @param instance Module instance number
bogdanm 82:6473597d706e 774 * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
bogdanm 82:6473597d706e 775 */
bogdanm 82:6473597d706e 776 static inline void dspi_hal_clear_status_flag(uint32_t instance,
bogdanm 82:6473597d706e 777 dspi_status_and_interrupt_request_t statusFlag)
bogdanm 82:6473597d706e 778 {
bogdanm 82:6473597d706e 779 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 780 HW_SPI_SR_SET(instance, (0x1U << statusFlag));
bogdanm 82:6473597d706e 781 }
bogdanm 82:6473597d706e 782
bogdanm 82:6473597d706e 783
bogdanm 82:6473597d706e 784 /*!
bogdanm 82:6473597d706e 785 * @brief Gets the DSPI FIFO counter or pointer.
bogdanm 82:6473597d706e 786 *
bogdanm 82:6473597d706e 787 * This function returns the number of entries or the next pointer in the Tx or Rx FIFO.
bogdanm 82:6473597d706e 788 * The parameters to pass in are the instance and either the Tx or Rx FIFO counter or a
bogdanm 82:6473597d706e 789 * pointer. The latter is an enum type defined as the bitmask of
bogdanm 82:6473597d706e 790 * those particular bit fields found in the device header file. For example:
bogdanm 82:6473597d706e 791 * @code
bogdanm 82:6473597d706e 792 return ((HW_SPI_SR_RD(instance) >> desiredParamter) & 0xF);
bogdanm 82:6473597d706e 793
bogdanm 82:6473597d706e 794 dspi_hal_get_fifo_counter_or_pointer(instance, kDspiRxFifoCounter);
bogdanm 82:6473597d706e 795 * @endcode
bogdanm 82:6473597d706e 796 *
bogdanm 82:6473597d706e 797 * @param instance Module instance number
bogdanm 82:6473597d706e 798 * @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t
bogdanm 82:6473597d706e 799 */
bogdanm 82:6473597d706e 800 static inline uint32_t dspi_hal_get_fifo_counter_or_pointer(uint32_t instance,
bogdanm 82:6473597d706e 801 dspi_fifo_counter_pointer_t desiredParameter)
bogdanm 82:6473597d706e 802 {
bogdanm 82:6473597d706e 803 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 804 return ((HW_SPI_SR_RD(instance) >> desiredParameter) & 0xFU);
bogdanm 82:6473597d706e 805 }
bogdanm 82:6473597d706e 806
bogdanm 82:6473597d706e 807
bogdanm 82:6473597d706e 808 /*@}*/
bogdanm 82:6473597d706e 809
bogdanm 82:6473597d706e 810 /*!
bogdanm 82:6473597d706e 811 * @name Data transfer
bogdanm 82:6473597d706e 812 * @{
bogdanm 82:6473597d706e 813 */
bogdanm 82:6473597d706e 814
bogdanm 82:6473597d706e 815 /*!
bogdanm 82:6473597d706e 816 * @brief Reads data from the data buffer.
bogdanm 82:6473597d706e 817 *
bogdanm 82:6473597d706e 818 * @param instance Module instance number
bogdanm 82:6473597d706e 819 */
bogdanm 82:6473597d706e 820 static inline uint32_t dspi_hal_read_data(uint32_t instance)
bogdanm 82:6473597d706e 821 {
bogdanm 82:6473597d706e 822 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 823 return HW_SPI_POPR_RD(instance);
bogdanm 82:6473597d706e 824 }
bogdanm 82:6473597d706e 825
bogdanm 82:6473597d706e 826 /*!
bogdanm 82:6473597d706e 827 * @brief Writes data into the data buffer, slave mode.
bogdanm 82:6473597d706e 828 *
bogdanm 82:6473597d706e 829 * In slave mode, up to 32-bit words may be written.
bogdanm 82:6473597d706e 830 *
bogdanm 82:6473597d706e 831 * @param instance Module instance number
bogdanm 82:6473597d706e 832 * @param data The data to send
bogdanm 82:6473597d706e 833 */
bogdanm 82:6473597d706e 834 static inline void dspi_hal_write_data_slave_mode(uint32_t instance, uint32_t data)
bogdanm 82:6473597d706e 835 {
bogdanm 82:6473597d706e 836 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 837 HW_SPI_PUSHR_SLAVE_WR(instance, data);
bogdanm 82:6473597d706e 838 }
bogdanm 82:6473597d706e 839
bogdanm 82:6473597d706e 840 /*!
bogdanm 82:6473597d706e 841 * @brief Writes data into the data buffer, master mode.
bogdanm 82:6473597d706e 842 *
bogdanm 82:6473597d706e 843 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
bogdanm 82:6473597d706e 844 * provides characteristics of the data such as: optional continuous chip select
bogdanm 82:6473597d706e 845 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
bogdanm 82:6473597d706e 846 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
bogdanm 82:6473597d706e 847 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
bogdanm 82:6473597d706e 848 * sending the first frame of a data packet). This is an example:
bogdanm 82:6473597d706e 849 * @code
bogdanm 82:6473597d706e 850 dspi_command_config_t commandConfig;
bogdanm 82:6473597d706e 851 commandConfig.isChipSelectContinuous = true;
bogdanm 82:6473597d706e 852 commandConfig.whichCtar = kDspiCtar0;
bogdanm 82:6473597d706e 853 commandConfig.whichPcs = kDspiPcs1;
bogdanm 82:6473597d706e 854 commandConfig.clearTransferCount = false;
bogdanm 82:6473597d706e 855 commandConfig.isEndOfQueue = false;
bogdanm 82:6473597d706e 856 dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
bogdanm 82:6473597d706e 857 * endcode
bogdanm 82:6473597d706e 858 *
bogdanm 82:6473597d706e 859 * @param instance Module instance number
bogdanm 82:6473597d706e 860 * @param command Pointer to command structure
bogdanm 82:6473597d706e 861 * @param data The data word to be sent
bogdanm 82:6473597d706e 862 */
bogdanm 82:6473597d706e 863 void dspi_hal_write_data_master_mode(uint32_t instance,
bogdanm 82:6473597d706e 864 dspi_command_config_t * command,
bogdanm 82:6473597d706e 865 uint16_t data);
bogdanm 82:6473597d706e 866
bogdanm 82:6473597d706e 867 /*!
bogdanm 82:6473597d706e 868 * @brief Gets the transfer count.
bogdanm 82:6473597d706e 869 *
bogdanm 82:6473597d706e 870 * This function returns the current value of the DSPI Transfer Count Register.
bogdanm 82:6473597d706e 871 *
bogdanm 82:6473597d706e 872 * @param instance Module instance number
bogdanm 82:6473597d706e 873 * @return The current transfer count
bogdanm 82:6473597d706e 874 */
bogdanm 82:6473597d706e 875 static inline uint32_t dspi_hal_get_transfer_count(uint32_t instance)
bogdanm 82:6473597d706e 876 {
bogdanm 82:6473597d706e 877 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 878 return BR_SPI_TCR_SPI_TCNT(instance);
bogdanm 82:6473597d706e 879 }
bogdanm 82:6473597d706e 880
bogdanm 82:6473597d706e 881 /*!
bogdanm 82:6473597d706e 882 * @brief Pre-sets the transfer count.
bogdanm 82:6473597d706e 883 *
bogdanm 82:6473597d706e 884 * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
bogdanm 82:6473597d706e 885 * to 65535; Incrementing past this resets the counter back to 0.
bogdanm 82:6473597d706e 886 *
bogdanm 82:6473597d706e 887 * @param instance Module instance number
bogdanm 82:6473597d706e 888 * @param presetValue The desired pre-set value for the transfer counter
bogdanm 82:6473597d706e 889 */
bogdanm 82:6473597d706e 890 static inline void dspi_hal_preset_transfer_count(uint32_t instance, uint16_t presetValue)
bogdanm 82:6473597d706e 891 {
bogdanm 82:6473597d706e 892 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 893 BW_SPI_TCR_SPI_TCNT(instance, presetValue);
bogdanm 82:6473597d706e 894 }
bogdanm 82:6473597d706e 895
bogdanm 82:6473597d706e 896 /*@}*/
bogdanm 82:6473597d706e 897
bogdanm 82:6473597d706e 898 /*!
bogdanm 82:6473597d706e 899 * @name Debug
bogdanm 82:6473597d706e 900 * @{
bogdanm 82:6473597d706e 901 */
bogdanm 82:6473597d706e 902
bogdanm 82:6473597d706e 903 /*!
bogdanm 82:6473597d706e 904 * @brief Read FIFO registers for debug purposes.
bogdanm 82:6473597d706e 905 *
bogdanm 82:6473597d706e 906 * @param instance Module instance number
bogdanm 82:6473597d706e 907 * @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t.
bogdanm 82:6473597d706e 908 * @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3.
bogdanm 82:6473597d706e 909 * @retrun The desired FIFO register contents
bogdanm 82:6473597d706e 910 */
bogdanm 82:6473597d706e 911 uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
bogdanm 82:6473597d706e 912
bogdanm 82:6473597d706e 913 /*!
bogdanm 82:6473597d706e 914 * @brief Configures the DSPI to halt during debug mode.
bogdanm 82:6473597d706e 915 *
bogdanm 82:6473597d706e 916 * @param instance Module instance number
bogdanm 82:6473597d706e 917 * @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer
bogdanm 82:6473597d706e 918 * in debug mode.
bogdanm 82:6473597d706e 919 */
bogdanm 82:6473597d706e 920 static inline void dspi_hal_configure_halt_in_debug_mode(uint32_t instance, bool enable)
bogdanm 82:6473597d706e 921 {
bogdanm 82:6473597d706e 922 assert(instance < HW_SPI_INSTANCE_COUNT);
bogdanm 82:6473597d706e 923 BW_SPI_MCR_FRZ(instance, (enable == true));
bogdanm 82:6473597d706e 924 }
bogdanm 82:6473597d706e 925
bogdanm 82:6473597d706e 926 /* @}*/
bogdanm 82:6473597d706e 927
bogdanm 82:6473597d706e 928 #if defined(__cplusplus)
bogdanm 82:6473597d706e 929 }
bogdanm 82:6473597d706e 930 #endif
bogdanm 82:6473597d706e 931
bogdanm 82:6473597d706e 932 /*! @}*/
bogdanm 82:6473597d706e 933
bogdanm 82:6473597d706e 934 #endif /* __FSL_DSPI_HAL_H__*/
bogdanm 82:6473597d706e 935 /*******************************************************************************
bogdanm 82:6473597d706e 936 * EOF
bogdanm 82:6473597d706e 937 ******************************************************************************/
bogdanm 82:6473597d706e 938