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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_wdog.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_WDOG_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_WDOG_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 WDOG
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Generation 2008 Watchdog Timer
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
bogdanm	82:6473597d706e	33	* - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
bogdanm	82:6473597d706e	34	* - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
bogdanm	82:6473597d706e	35	* - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
bogdanm	82:6473597d706e	36	* - HW_WDOG_WINH - Watchdog Window Register High
bogdanm	82:6473597d706e	37	* - HW_WDOG_WINL - Watchdog Window Register Low
bogdanm	82:6473597d706e	38	* - HW_WDOG_REFRESH - Watchdog Refresh register
bogdanm	82:6473597d706e	39	* - HW_WDOG_UNLOCK - Watchdog Unlock register
bogdanm	82:6473597d706e	40	* - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
bogdanm	82:6473597d706e	41	* - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
bogdanm	82:6473597d706e	42	* - HW_WDOG_RSTCNT - Watchdog Reset Count register
bogdanm	82:6473597d706e	43	* - HW_WDOG_PRESC - Watchdog Prescaler register
bogdanm	82:6473597d706e	44	*
bogdanm	82:6473597d706e	45	* - hw_wdog_t - Struct containing all module registers.
bogdanm	82:6473597d706e	46	*/
bogdanm	82:6473597d706e	47
bogdanm	82:6473597d706e	48	//! @name Module base addresses
bogdanm	82:6473597d706e	49	//@{
bogdanm	82:6473597d706e	50	#ifndef REGS_WDOG_BASE
bogdanm	82:6473597d706e	51	#define HW_WDOG_INSTANCE_COUNT (1U) //!< Number of instances of the WDOG module.
bogdanm	82:6473597d706e	52	#define REGS_WDOG_BASE (0x40052000U) //!< Base address for WDOG.
bogdanm	82:6473597d706e	53	#endif
bogdanm	82:6473597d706e	54	//@}
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	57	// HW_WDOG_STCTRLH - Watchdog Status and Control Register High
bogdanm	82:6473597d706e	58	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	59
bogdanm	82:6473597d706e	60	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	61	/*!
bogdanm	82:6473597d706e	62	* @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
bogdanm	82:6473597d706e	63	*
bogdanm	82:6473597d706e	64	* Reset value: 0x01D3U
bogdanm	82:6473597d706e	65	*/
bogdanm	82:6473597d706e	66	typedef union _hw_wdog_stctrlh
bogdanm	82:6473597d706e	67	{
bogdanm	82:6473597d706e	68	uint16_t U;
bogdanm	82:6473597d706e	69	struct _hw_wdog_stctrlh_bitfields
bogdanm	82:6473597d706e	70	{
bogdanm	82:6473597d706e	71	uint16_t WDOGEN : 1; //!< [0]
bogdanm	82:6473597d706e	72	uint16_t CLKSRC : 1; //!< [1]
bogdanm	82:6473597d706e	73	uint16_t IRQRSTEN : 1; //!< [2]
bogdanm	82:6473597d706e	74	uint16_t WINEN : 1; //!< [3]
bogdanm	82:6473597d706e	75	uint16_t ALLOWUPDATE : 1; //!< [4]
bogdanm	82:6473597d706e	76	uint16_t DBGEN : 1; //!< [5]
bogdanm	82:6473597d706e	77	uint16_t STOPEN : 1; //!< [6]
bogdanm	82:6473597d706e	78	uint16_t WAITEN : 1; //!< [7]
bogdanm	82:6473597d706e	79	uint16_t RESERVED0 : 2; //!< [9:8]
bogdanm	82:6473597d706e	80	uint16_t TESTWDOG : 1; //!< [10]
bogdanm	82:6473597d706e	81	uint16_t TESTSEL : 1; //!< [11]
bogdanm	82:6473597d706e	82	uint16_t BYTESEL : 2; //!< [13:12]
bogdanm	82:6473597d706e	83	uint16_t DISTESTWDOG : 1; //!< [14]
bogdanm	82:6473597d706e	84	uint16_t RESERVED1 : 1; //!< [15]
bogdanm	82:6473597d706e	85	} B;
bogdanm	82:6473597d706e	86	} hw_wdog_stctrlh_t;
bogdanm	82:6473597d706e	87	#endif
bogdanm	82:6473597d706e	88
bogdanm	82:6473597d706e	89	/*!
bogdanm	82:6473597d706e	90	* @name Constants and macros for entire WDOG_STCTRLH register
bogdanm	82:6473597d706e	91	*/
bogdanm	82:6473597d706e	92	//@{
bogdanm	82:6473597d706e	93	#define HW_WDOG_STCTRLH_ADDR (REGS_WDOG_BASE + 0x0U)
bogdanm	82:6473597d706e	94
bogdanm	82:6473597d706e	95	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	96	#define HW_WDOG_STCTRLH ((__IO hw_wdog_stctrlh_t ) HW_WDOG_STCTRLH_ADDR)
bogdanm	82:6473597d706e	97	#define HW_WDOG_STCTRLH_RD() (HW_WDOG_STCTRLH.U)
bogdanm	82:6473597d706e	98	#define HW_WDOG_STCTRLH_WR(v) (HW_WDOG_STCTRLH.U = (v))
bogdanm	82:6473597d706e	99	#define HW_WDOG_STCTRLH_SET(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() \| (v)))
bogdanm	82:6473597d706e	100	#define HW_WDOG_STCTRLH_CLR(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() & ~(v)))
bogdanm	82:6473597d706e	101	#define HW_WDOG_STCTRLH_TOG(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() ^ (v)))
bogdanm	82:6473597d706e	102	#endif
bogdanm	82:6473597d706e	103	//@}
bogdanm	82:6473597d706e	104
bogdanm	82:6473597d706e	105	/*
bogdanm	82:6473597d706e	106	* Constants & macros for individual WDOG_STCTRLH bitfields
bogdanm	82:6473597d706e	107	*/
bogdanm	82:6473597d706e	108
bogdanm	82:6473597d706e	109	/*!
bogdanm	82:6473597d706e	110	* @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
bogdanm	82:6473597d706e	111	*
bogdanm	82:6473597d706e	112	* Enables or disables the WDOG's operation. In the disabled state, the watchdog
bogdanm	82:6473597d706e	113	* timer is kept in the reset state, but the other exception conditions can
bogdanm	82:6473597d706e	114	* still trigger a reset/interrupt. A change in the value of this bit must be held
bogdanm	82:6473597d706e	115	* for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
bogdanm	82:6473597d706e	116	*
bogdanm	82:6473597d706e	117	* Values:
bogdanm	82:6473597d706e	118	* - 0 - WDOG is disabled.
bogdanm	82:6473597d706e	119	* - 1 - WDOG is enabled.
bogdanm	82:6473597d706e	120	*/
bogdanm	82:6473597d706e	121	//@{
bogdanm	82:6473597d706e	122	#define BP_WDOG_STCTRLH_WDOGEN (0U) //!< Bit position for WDOG_STCTRLH_WDOGEN.
bogdanm	82:6473597d706e	123	#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) //!< Bit mask for WDOG_STCTRLH_WDOGEN.
bogdanm	82:6473597d706e	124	#define BS_WDOG_STCTRLH_WDOGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WDOGEN.
bogdanm	82:6473597d706e	125
bogdanm	82:6473597d706e	126	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	127	//! @brief Read current value of the WDOG_STCTRLH_WDOGEN field.
bogdanm	82:6473597d706e	128	#define BR_WDOG_STCTRLH_WDOGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN))
bogdanm	82:6473597d706e	129	#endif
bogdanm	82:6473597d706e	130
bogdanm	82:6473597d706e	131	//! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN.
bogdanm	82:6473597d706e	132	#define BF_WDOG_STCTRLH_WDOGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WDOGEN), uint16_t) & BM_WDOG_STCTRLH_WDOGEN)
bogdanm	82:6473597d706e	133
bogdanm	82:6473597d706e	134	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	135	//! @brief Set the WDOGEN field to a new value.
bogdanm	82:6473597d706e	136	#define BW_WDOG_STCTRLH_WDOGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN) = (v))
bogdanm	82:6473597d706e	137	#endif
bogdanm	82:6473597d706e	138	//@}
bogdanm	82:6473597d706e	139
bogdanm	82:6473597d706e	140	/*!
bogdanm	82:6473597d706e	141	* @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
bogdanm	82:6473597d706e	142	*
bogdanm	82:6473597d706e	143	* Selects clock source for the WDOG timer and other internal timing operations.
bogdanm	82:6473597d706e	144	*
bogdanm	82:6473597d706e	145	* Values:
bogdanm	82:6473597d706e	146	* - 0 - WDOG clock sourced from LPO .
bogdanm	82:6473597d706e	147	* - 1 - WDOG clock sourced from alternate clock source.
bogdanm	82:6473597d706e	148	*/
bogdanm	82:6473597d706e	149	//@{
bogdanm	82:6473597d706e	150	#define BP_WDOG_STCTRLH_CLKSRC (1U) //!< Bit position for WDOG_STCTRLH_CLKSRC.
bogdanm	82:6473597d706e	151	#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) //!< Bit mask for WDOG_STCTRLH_CLKSRC.
bogdanm	82:6473597d706e	152	#define BS_WDOG_STCTRLH_CLKSRC (1U) //!< Bit field size in bits for WDOG_STCTRLH_CLKSRC.
bogdanm	82:6473597d706e	153
bogdanm	82:6473597d706e	154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	155	//! @brief Read current value of the WDOG_STCTRLH_CLKSRC field.
bogdanm	82:6473597d706e	156	#define BR_WDOG_STCTRLH_CLKSRC (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC))
bogdanm	82:6473597d706e	157	#endif
bogdanm	82:6473597d706e	158
bogdanm	82:6473597d706e	159	//! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC.
bogdanm	82:6473597d706e	160	#define BF_WDOG_STCTRLH_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_CLKSRC), uint16_t) & BM_WDOG_STCTRLH_CLKSRC)
bogdanm	82:6473597d706e	161
bogdanm	82:6473597d706e	162	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	163	//! @brief Set the CLKSRC field to a new value.
bogdanm	82:6473597d706e	164	#define BW_WDOG_STCTRLH_CLKSRC(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC) = (v))
bogdanm	82:6473597d706e	165	#endif
bogdanm	82:6473597d706e	166	//@}
bogdanm	82:6473597d706e	167
bogdanm	82:6473597d706e	168	/*!
bogdanm	82:6473597d706e	169	* @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
bogdanm	82:6473597d706e	170	*
bogdanm	82:6473597d706e	171	* Used to enable the debug breadcrumbs feature. A change in this bit is updated
bogdanm	82:6473597d706e	172	* immediately, as opposed to updating after WCT.
bogdanm	82:6473597d706e	173	*
bogdanm	82:6473597d706e	174	* Values:
bogdanm	82:6473597d706e	175	* - 0 - WDOG time-out generates reset only.
bogdanm	82:6473597d706e	176	* - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
bogdanm	82:6473597d706e	177	* a reset.
bogdanm	82:6473597d706e	178	*/
bogdanm	82:6473597d706e	179	//@{
bogdanm	82:6473597d706e	180	#define BP_WDOG_STCTRLH_IRQRSTEN (2U) //!< Bit position for WDOG_STCTRLH_IRQRSTEN.
bogdanm	82:6473597d706e	181	#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) //!< Bit mask for WDOG_STCTRLH_IRQRSTEN.
bogdanm	82:6473597d706e	182	#define BS_WDOG_STCTRLH_IRQRSTEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN.
bogdanm	82:6473597d706e	183
bogdanm	82:6473597d706e	184	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	185	//! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field.
bogdanm	82:6473597d706e	186	#define BR_WDOG_STCTRLH_IRQRSTEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN))
bogdanm	82:6473597d706e	187	#endif
bogdanm	82:6473597d706e	188
bogdanm	82:6473597d706e	189	//! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN.
bogdanm	82:6473597d706e	190	#define BF_WDOG_STCTRLH_IRQRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_IRQRSTEN), uint16_t) & BM_WDOG_STCTRLH_IRQRSTEN)
bogdanm	82:6473597d706e	191
bogdanm	82:6473597d706e	192	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	193	//! @brief Set the IRQRSTEN field to a new value.
bogdanm	82:6473597d706e	194	#define BW_WDOG_STCTRLH_IRQRSTEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN) = (v))
bogdanm	82:6473597d706e	195	#endif
bogdanm	82:6473597d706e	196	//@}
bogdanm	82:6473597d706e	197
bogdanm	82:6473597d706e	198	/*!
bogdanm	82:6473597d706e	199	* @name Register WDOG_STCTRLH, field WINEN[3] (RW)
bogdanm	82:6473597d706e	200	*
bogdanm	82:6473597d706e	201	* Enables Windowing mode.
bogdanm	82:6473597d706e	202	*
bogdanm	82:6473597d706e	203	* Values:
bogdanm	82:6473597d706e	204	* - 0 - Windowing mode is disabled.
bogdanm	82:6473597d706e	205	* - 1 - Windowing mode is enabled.
bogdanm	82:6473597d706e	206	*/
bogdanm	82:6473597d706e	207	//@{
bogdanm	82:6473597d706e	208	#define BP_WDOG_STCTRLH_WINEN (3U) //!< Bit position for WDOG_STCTRLH_WINEN.
bogdanm	82:6473597d706e	209	#define BM_WDOG_STCTRLH_WINEN (0x0008U) //!< Bit mask for WDOG_STCTRLH_WINEN.
bogdanm	82:6473597d706e	210	#define BS_WDOG_STCTRLH_WINEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WINEN.
bogdanm	82:6473597d706e	211
bogdanm	82:6473597d706e	212	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	213	//! @brief Read current value of the WDOG_STCTRLH_WINEN field.
bogdanm	82:6473597d706e	214	#define BR_WDOG_STCTRLH_WINEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN))
bogdanm	82:6473597d706e	215	#endif
bogdanm	82:6473597d706e	216
bogdanm	82:6473597d706e	217	//! @brief Format value for bitfield WDOG_STCTRLH_WINEN.
bogdanm	82:6473597d706e	218	#define BF_WDOG_STCTRLH_WINEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WINEN), uint16_t) & BM_WDOG_STCTRLH_WINEN)
bogdanm	82:6473597d706e	219
bogdanm	82:6473597d706e	220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	221	//! @brief Set the WINEN field to a new value.
bogdanm	82:6473597d706e	222	#define BW_WDOG_STCTRLH_WINEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN) = (v))
bogdanm	82:6473597d706e	223	#endif
bogdanm	82:6473597d706e	224	//@}
bogdanm	82:6473597d706e	225
bogdanm	82:6473597d706e	226	/*!
bogdanm	82:6473597d706e	227	* @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
bogdanm	82:6473597d706e	228	*
bogdanm	82:6473597d706e	229	* Enables updates to watchdog write-once registers, after the reset-triggered
bogdanm	82:6473597d706e	230	* initial configuration window (WCT) closes, through unlock sequence.
bogdanm	82:6473597d706e	231	*
bogdanm	82:6473597d706e	232	* Values:
bogdanm	82:6473597d706e	233	* - 0 - No further updates allowed to WDOG write-once registers.
bogdanm	82:6473597d706e	234	* - 1 - WDOG write-once registers can be unlocked for updating.
bogdanm	82:6473597d706e	235	*/
bogdanm	82:6473597d706e	236	//@{
bogdanm	82:6473597d706e	237	#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) //!< Bit position for WDOG_STCTRLH_ALLOWUPDATE.
bogdanm	82:6473597d706e	238	#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) //!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE.
bogdanm	82:6473597d706e	239	#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) //!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE.
bogdanm	82:6473597d706e	240
bogdanm	82:6473597d706e	241	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	242	//! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field.
bogdanm	82:6473597d706e	243	#define BR_WDOG_STCTRLH_ALLOWUPDATE (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE))
bogdanm	82:6473597d706e	244	#endif
bogdanm	82:6473597d706e	245
bogdanm	82:6473597d706e	246	//! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE.
bogdanm	82:6473597d706e	247	#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_ALLOWUPDATE), uint16_t) & BM_WDOG_STCTRLH_ALLOWUPDATE)
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	250	//! @brief Set the ALLOWUPDATE field to a new value.
bogdanm	82:6473597d706e	251	#define BW_WDOG_STCTRLH_ALLOWUPDATE(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
bogdanm	82:6473597d706e	252	#endif
bogdanm	82:6473597d706e	253	//@}
bogdanm	82:6473597d706e	254
bogdanm	82:6473597d706e	255	/*!
bogdanm	82:6473597d706e	256	* @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
bogdanm	82:6473597d706e	257	*
bogdanm	82:6473597d706e	258	* Enables or disables WDOG in Debug mode.
bogdanm	82:6473597d706e	259	*
bogdanm	82:6473597d706e	260	* Values:
bogdanm	82:6473597d706e	261	* - 0 - WDOG is disabled in CPU Debug mode.
bogdanm	82:6473597d706e	262	* - 1 - WDOG is enabled in CPU Debug mode.
bogdanm	82:6473597d706e	263	*/
bogdanm	82:6473597d706e	264	//@{
bogdanm	82:6473597d706e	265	#define BP_WDOG_STCTRLH_DBGEN (5U) //!< Bit position for WDOG_STCTRLH_DBGEN.
bogdanm	82:6473597d706e	266	#define BM_WDOG_STCTRLH_DBGEN (0x0020U) //!< Bit mask for WDOG_STCTRLH_DBGEN.
bogdanm	82:6473597d706e	267	#define BS_WDOG_STCTRLH_DBGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_DBGEN.
bogdanm	82:6473597d706e	268
bogdanm	82:6473597d706e	269	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	270	//! @brief Read current value of the WDOG_STCTRLH_DBGEN field.
bogdanm	82:6473597d706e	271	#define BR_WDOG_STCTRLH_DBGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN))
bogdanm	82:6473597d706e	272	#endif
bogdanm	82:6473597d706e	273
bogdanm	82:6473597d706e	274	//! @brief Format value for bitfield WDOG_STCTRLH_DBGEN.
bogdanm	82:6473597d706e	275	#define BF_WDOG_STCTRLH_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DBGEN), uint16_t) & BM_WDOG_STCTRLH_DBGEN)
bogdanm	82:6473597d706e	276
bogdanm	82:6473597d706e	277	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	278	//! @brief Set the DBGEN field to a new value.
bogdanm	82:6473597d706e	279	#define BW_WDOG_STCTRLH_DBGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN) = (v))
bogdanm	82:6473597d706e	280	#endif
bogdanm	82:6473597d706e	281	//@}
bogdanm	82:6473597d706e	282
bogdanm	82:6473597d706e	283	/*!
bogdanm	82:6473597d706e	284	* @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
bogdanm	82:6473597d706e	285	*
bogdanm	82:6473597d706e	286	* Enables or disables WDOG in Stop mode.
bogdanm	82:6473597d706e	287	*
bogdanm	82:6473597d706e	288	* Values:
bogdanm	82:6473597d706e	289	* - 0 - WDOG is disabled in CPU Stop mode.
bogdanm	82:6473597d706e	290	* - 1 - WDOG is enabled in CPU Stop mode.
bogdanm	82:6473597d706e	291	*/
bogdanm	82:6473597d706e	292	//@{
bogdanm	82:6473597d706e	293	#define BP_WDOG_STCTRLH_STOPEN (6U) //!< Bit position for WDOG_STCTRLH_STOPEN.
bogdanm	82:6473597d706e	294	#define BM_WDOG_STCTRLH_STOPEN (0x0040U) //!< Bit mask for WDOG_STCTRLH_STOPEN.
bogdanm	82:6473597d706e	295	#define BS_WDOG_STCTRLH_STOPEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_STOPEN.
bogdanm	82:6473597d706e	296
bogdanm	82:6473597d706e	297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	298	//! @brief Read current value of the WDOG_STCTRLH_STOPEN field.
bogdanm	82:6473597d706e	299	#define BR_WDOG_STCTRLH_STOPEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN))
bogdanm	82:6473597d706e	300	#endif
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	//! @brief Format value for bitfield WDOG_STCTRLH_STOPEN.
bogdanm	82:6473597d706e	303	#define BF_WDOG_STCTRLH_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_STOPEN), uint16_t) & BM_WDOG_STCTRLH_STOPEN)
bogdanm	82:6473597d706e	304
bogdanm	82:6473597d706e	305	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	306	//! @brief Set the STOPEN field to a new value.
bogdanm	82:6473597d706e	307	#define BW_WDOG_STCTRLH_STOPEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN) = (v))
bogdanm	82:6473597d706e	308	#endif
bogdanm	82:6473597d706e	309	//@}
bogdanm	82:6473597d706e	310
bogdanm	82:6473597d706e	311	/*!
bogdanm	82:6473597d706e	312	* @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
bogdanm	82:6473597d706e	313	*
bogdanm	82:6473597d706e	314	* Enables or disables WDOG in Wait mode.
bogdanm	82:6473597d706e	315	*
bogdanm	82:6473597d706e	316	* Values:
bogdanm	82:6473597d706e	317	* - 0 - WDOG is disabled in CPU Wait mode.
bogdanm	82:6473597d706e	318	* - 1 - WDOG is enabled in CPU Wait mode.
bogdanm	82:6473597d706e	319	*/
bogdanm	82:6473597d706e	320	//@{
bogdanm	82:6473597d706e	321	#define BP_WDOG_STCTRLH_WAITEN (7U) //!< Bit position for WDOG_STCTRLH_WAITEN.
bogdanm	82:6473597d706e	322	#define BM_WDOG_STCTRLH_WAITEN (0x0080U) //!< Bit mask for WDOG_STCTRLH_WAITEN.
bogdanm	82:6473597d706e	323	#define BS_WDOG_STCTRLH_WAITEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WAITEN.
bogdanm	82:6473597d706e	324
bogdanm	82:6473597d706e	325	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	326	//! @brief Read current value of the WDOG_STCTRLH_WAITEN field.
bogdanm	82:6473597d706e	327	#define BR_WDOG_STCTRLH_WAITEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN))
bogdanm	82:6473597d706e	328	#endif
bogdanm	82:6473597d706e	329
bogdanm	82:6473597d706e	330	//! @brief Format value for bitfield WDOG_STCTRLH_WAITEN.
bogdanm	82:6473597d706e	331	#define BF_WDOG_STCTRLH_WAITEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WAITEN), uint16_t) & BM_WDOG_STCTRLH_WAITEN)
bogdanm	82:6473597d706e	332
bogdanm	82:6473597d706e	333	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	334	//! @brief Set the WAITEN field to a new value.
bogdanm	82:6473597d706e	335	#define BW_WDOG_STCTRLH_WAITEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN) = (v))
bogdanm	82:6473597d706e	336	#endif
bogdanm	82:6473597d706e	337	//@}
bogdanm	82:6473597d706e	338
bogdanm	82:6473597d706e	339	/*!
bogdanm	82:6473597d706e	340	* @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
bogdanm	82:6473597d706e	341	*
bogdanm	82:6473597d706e	342	* Puts the watchdog in the functional test mode. In this mode, the watchdog
bogdanm	82:6473597d706e	343	* timer and the associated compare and reset generation logic is tested for correct
bogdanm	82:6473597d706e	344	* operation. The clock for the timer is switched from the main watchdog clock
bogdanm	82:6473597d706e	345	* to the fast clock input for watchdog functional test. The TESTSEL bit selects
bogdanm	82:6473597d706e	346	* the test to be run.
bogdanm	82:6473597d706e	347	*/
bogdanm	82:6473597d706e	348	//@{
bogdanm	82:6473597d706e	349	#define BP_WDOG_STCTRLH_TESTWDOG (10U) //!< Bit position for WDOG_STCTRLH_TESTWDOG.
bogdanm	82:6473597d706e	350	#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) //!< Bit mask for WDOG_STCTRLH_TESTWDOG.
bogdanm	82:6473597d706e	351	#define BS_WDOG_STCTRLH_TESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG.
bogdanm	82:6473597d706e	352
bogdanm	82:6473597d706e	353	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	354	//! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field.
bogdanm	82:6473597d706e	355	#define BR_WDOG_STCTRLH_TESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG))
bogdanm	82:6473597d706e	356	#endif
bogdanm	82:6473597d706e	357
bogdanm	82:6473597d706e	358	//! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG.
bogdanm	82:6473597d706e	359	#define BF_WDOG_STCTRLH_TESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTWDOG), uint16_t) & BM_WDOG_STCTRLH_TESTWDOG)
bogdanm	82:6473597d706e	360
bogdanm	82:6473597d706e	361	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	362	//! @brief Set the TESTWDOG field to a new value.
bogdanm	82:6473597d706e	363	#define BW_WDOG_STCTRLH_TESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG) = (v))
bogdanm	82:6473597d706e	364	#endif
bogdanm	82:6473597d706e	365	//@}
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	/*!
bogdanm	82:6473597d706e	368	* @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
bogdanm	82:6473597d706e	369	*
bogdanm	82:6473597d706e	370	* Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
bogdanm	82:6473597d706e	371	* timer.
bogdanm	82:6473597d706e	372	*
bogdanm	82:6473597d706e	373	* Values:
bogdanm	82:6473597d706e	374	* - 0 - Quick test. The timer runs in normal operation. You can load a small
bogdanm	82:6473597d706e	375	* time-out value to do a quick test.
bogdanm	82:6473597d706e	376	* - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
bogdanm	82:6473597d706e	377	* of the timer are enabled for operation and are compared for time-out
bogdanm	82:6473597d706e	378	* against the corresponding byte of the programmed time-out value. Select the
bogdanm	82:6473597d706e	379	* byte through BYTESEL[1:0] for testing.
bogdanm	82:6473597d706e	380	*/
bogdanm	82:6473597d706e	381	//@{
bogdanm	82:6473597d706e	382	#define BP_WDOG_STCTRLH_TESTSEL (11U) //!< Bit position for WDOG_STCTRLH_TESTSEL.
bogdanm	82:6473597d706e	383	#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) //!< Bit mask for WDOG_STCTRLH_TESTSEL.
bogdanm	82:6473597d706e	384	#define BS_WDOG_STCTRLH_TESTSEL (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTSEL.
bogdanm	82:6473597d706e	385
bogdanm	82:6473597d706e	386	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	387	//! @brief Read current value of the WDOG_STCTRLH_TESTSEL field.
bogdanm	82:6473597d706e	388	#define BR_WDOG_STCTRLH_TESTSEL (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL))
bogdanm	82:6473597d706e	389	#endif
bogdanm	82:6473597d706e	390
bogdanm	82:6473597d706e	391	//! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL.
bogdanm	82:6473597d706e	392	#define BF_WDOG_STCTRLH_TESTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTSEL), uint16_t) & BM_WDOG_STCTRLH_TESTSEL)
bogdanm	82:6473597d706e	393
bogdanm	82:6473597d706e	394	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	395	//! @brief Set the TESTSEL field to a new value.
bogdanm	82:6473597d706e	396	#define BW_WDOG_STCTRLH_TESTSEL(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL) = (v))
bogdanm	82:6473597d706e	397	#endif
bogdanm	82:6473597d706e	398	//@}
bogdanm	82:6473597d706e	399
bogdanm	82:6473597d706e	400	/*!
bogdanm	82:6473597d706e	401	* @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
bogdanm	82:6473597d706e	402	*
bogdanm	82:6473597d706e	403	* This 2-bit field selects the byte to be tested when the watchdog is in the
bogdanm	82:6473597d706e	404	* byte test mode.
bogdanm	82:6473597d706e	405	*
bogdanm	82:6473597d706e	406	* Values:
bogdanm	82:6473597d706e	407	* - 00 - Byte 0 selected
bogdanm	82:6473597d706e	408	* - 01 - Byte 1 selected
bogdanm	82:6473597d706e	409	* - 10 - Byte 2 selected
bogdanm	82:6473597d706e	410	* - 11 - Byte 3 selected
bogdanm	82:6473597d706e	411	*/
bogdanm	82:6473597d706e	412	//@{
bogdanm	82:6473597d706e	413	#define BP_WDOG_STCTRLH_BYTESEL (12U) //!< Bit position for WDOG_STCTRLH_BYTESEL.
bogdanm	82:6473597d706e	414	#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) //!< Bit mask for WDOG_STCTRLH_BYTESEL.
bogdanm	82:6473597d706e	415	#define BS_WDOG_STCTRLH_BYTESEL (2U) //!< Bit field size in bits for WDOG_STCTRLH_BYTESEL.
bogdanm	82:6473597d706e	416
bogdanm	82:6473597d706e	417	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	418	//! @brief Read current value of the WDOG_STCTRLH_BYTESEL field.
bogdanm	82:6473597d706e	419	#define BR_WDOG_STCTRLH_BYTESEL (HW_WDOG_STCTRLH.B.BYTESEL)
bogdanm	82:6473597d706e	420	#endif
bogdanm	82:6473597d706e	421
bogdanm	82:6473597d706e	422	//! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL.
bogdanm	82:6473597d706e	423	#define BF_WDOG_STCTRLH_BYTESEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_BYTESEL), uint16_t) & BM_WDOG_STCTRLH_BYTESEL)
bogdanm	82:6473597d706e	424
bogdanm	82:6473597d706e	425	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	426	//! @brief Set the BYTESEL field to a new value.
bogdanm	82:6473597d706e	427	#define BW_WDOG_STCTRLH_BYTESEL(v) (HW_WDOG_STCTRLH_WR((HW_WDOG_STCTRLH_RD() & ~BM_WDOG_STCTRLH_BYTESEL) \| BF_WDOG_STCTRLH_BYTESEL(v)))
bogdanm	82:6473597d706e	428	#endif
bogdanm	82:6473597d706e	429	//@}
bogdanm	82:6473597d706e	430
bogdanm	82:6473597d706e	431	/*!
bogdanm	82:6473597d706e	432	* @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
bogdanm	82:6473597d706e	433	*
bogdanm	82:6473597d706e	434	* Allows the WDOG's functional test mode to be disabled permanently. After it
bogdanm	82:6473597d706e	435	* is set, it can only be cleared by a reset. It cannot be unlocked for editing
bogdanm	82:6473597d706e	436	* after it is set.
bogdanm	82:6473597d706e	437	*
bogdanm	82:6473597d706e	438	* Values:
bogdanm	82:6473597d706e	439	* - 0 - WDOG functional test mode is not disabled.
bogdanm	82:6473597d706e	440	* - 1 - WDOG functional test mode is disabled permanently until reset.
bogdanm	82:6473597d706e	441	*/
bogdanm	82:6473597d706e	442	//@{
bogdanm	82:6473597d706e	443	#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) //!< Bit position for WDOG_STCTRLH_DISTESTWDOG.
bogdanm	82:6473597d706e	444	#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) //!< Bit mask for WDOG_STCTRLH_DISTESTWDOG.
bogdanm	82:6473597d706e	445	#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG.
bogdanm	82:6473597d706e	446
bogdanm	82:6473597d706e	447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	448	//! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field.
bogdanm	82:6473597d706e	449	#define BR_WDOG_STCTRLH_DISTESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG))
bogdanm	82:6473597d706e	450	#endif
bogdanm	82:6473597d706e	451
bogdanm	82:6473597d706e	452	//! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG.
bogdanm	82:6473597d706e	453	#define BF_WDOG_STCTRLH_DISTESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DISTESTWDOG), uint16_t) & BM_WDOG_STCTRLH_DISTESTWDOG)
bogdanm	82:6473597d706e	454
bogdanm	82:6473597d706e	455	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	456	//! @brief Set the DISTESTWDOG field to a new value.
bogdanm	82:6473597d706e	457	#define BW_WDOG_STCTRLH_DISTESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
bogdanm	82:6473597d706e	458	#endif
bogdanm	82:6473597d706e	459	//@}
bogdanm	82:6473597d706e	460
bogdanm	82:6473597d706e	461	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	462	// HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
bogdanm	82:6473597d706e	463	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	464
bogdanm	82:6473597d706e	465	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	466	/*!
bogdanm	82:6473597d706e	467	* @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
bogdanm	82:6473597d706e	468	*
bogdanm	82:6473597d706e	469	* Reset value: 0x0001U
bogdanm	82:6473597d706e	470	*/
bogdanm	82:6473597d706e	471	typedef union _hw_wdog_stctrll
bogdanm	82:6473597d706e	472	{
bogdanm	82:6473597d706e	473	uint16_t U;
bogdanm	82:6473597d706e	474	struct _hw_wdog_stctrll_bitfields
bogdanm	82:6473597d706e	475	{
bogdanm	82:6473597d706e	476	uint16_t RESERVED0 : 15; //!< [14:0]
bogdanm	82:6473597d706e	477	uint16_t INTFLG : 1; //!< [15]
bogdanm	82:6473597d706e	478	} B;
bogdanm	82:6473597d706e	479	} hw_wdog_stctrll_t;
bogdanm	82:6473597d706e	480	#endif
bogdanm	82:6473597d706e	481
bogdanm	82:6473597d706e	482	/*!
bogdanm	82:6473597d706e	483	* @name Constants and macros for entire WDOG_STCTRLL register
bogdanm	82:6473597d706e	484	*/
bogdanm	82:6473597d706e	485	//@{
bogdanm	82:6473597d706e	486	#define HW_WDOG_STCTRLL_ADDR (REGS_WDOG_BASE + 0x2U)
bogdanm	82:6473597d706e	487
bogdanm	82:6473597d706e	488	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	489	#define HW_WDOG_STCTRLL ((__IO hw_wdog_stctrll_t ) HW_WDOG_STCTRLL_ADDR)
bogdanm	82:6473597d706e	490	#define HW_WDOG_STCTRLL_RD() (HW_WDOG_STCTRLL.U)
bogdanm	82:6473597d706e	491	#define HW_WDOG_STCTRLL_WR(v) (HW_WDOG_STCTRLL.U = (v))
bogdanm	82:6473597d706e	492	#define HW_WDOG_STCTRLL_SET(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() \| (v)))
bogdanm	82:6473597d706e	493	#define HW_WDOG_STCTRLL_CLR(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() & ~(v)))
bogdanm	82:6473597d706e	494	#define HW_WDOG_STCTRLL_TOG(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() ^ (v)))
bogdanm	82:6473597d706e	495	#endif
bogdanm	82:6473597d706e	496	//@}
bogdanm	82:6473597d706e	497
bogdanm	82:6473597d706e	498	/*
bogdanm	82:6473597d706e	499	* Constants & macros for individual WDOG_STCTRLL bitfields
bogdanm	82:6473597d706e	500	*/
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	/*!
bogdanm	82:6473597d706e	503	* @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
bogdanm	82:6473597d706e	504	*
bogdanm	82:6473597d706e	505	* Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
bogdanm	82:6473597d706e	506	* precondition to set this flag. INTFLG = 1 results in an interrupt being issued
bogdanm	82:6473597d706e	507	* followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
bogdanm	82:6473597d706e	508	* bit. It also gets cleared on a system reset.
bogdanm	82:6473597d706e	509	*/
bogdanm	82:6473597d706e	510	//@{
bogdanm	82:6473597d706e	511	#define BP_WDOG_STCTRLL_INTFLG (15U) //!< Bit position for WDOG_STCTRLL_INTFLG.
bogdanm	82:6473597d706e	512	#define BM_WDOG_STCTRLL_INTFLG (0x8000U) //!< Bit mask for WDOG_STCTRLL_INTFLG.
bogdanm	82:6473597d706e	513	#define BS_WDOG_STCTRLL_INTFLG (1U) //!< Bit field size in bits for WDOG_STCTRLL_INTFLG.
bogdanm	82:6473597d706e	514
bogdanm	82:6473597d706e	515	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	516	//! @brief Read current value of the WDOG_STCTRLL_INTFLG field.
bogdanm	82:6473597d706e	517	#define BR_WDOG_STCTRLL_INTFLG (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG))
bogdanm	82:6473597d706e	518	#endif
bogdanm	82:6473597d706e	519
bogdanm	82:6473597d706e	520	//! @brief Format value for bitfield WDOG_STCTRLL_INTFLG.
bogdanm	82:6473597d706e	521	#define BF_WDOG_STCTRLL_INTFLG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLL_INTFLG), uint16_t) & BM_WDOG_STCTRLL_INTFLG)
bogdanm	82:6473597d706e	522
bogdanm	82:6473597d706e	523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	524	//! @brief Set the INTFLG field to a new value.
bogdanm	82:6473597d706e	525	#define BW_WDOG_STCTRLL_INTFLG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG) = (v))
bogdanm	82:6473597d706e	526	#endif
bogdanm	82:6473597d706e	527	//@}
bogdanm	82:6473597d706e	528
bogdanm	82:6473597d706e	529	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	530	// HW_WDOG_TOVALH - Watchdog Time-out Value Register High
bogdanm	82:6473597d706e	531	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	532
bogdanm	82:6473597d706e	533	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	534	/*!
bogdanm	82:6473597d706e	535	* @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
bogdanm	82:6473597d706e	536	*
bogdanm	82:6473597d706e	537	* Reset value: 0x004CU
bogdanm	82:6473597d706e	538	*/
bogdanm	82:6473597d706e	539	typedef union _hw_wdog_tovalh
bogdanm	82:6473597d706e	540	{
bogdanm	82:6473597d706e	541	uint16_t U;
bogdanm	82:6473597d706e	542	struct _hw_wdog_tovalh_bitfields
bogdanm	82:6473597d706e	543	{
bogdanm	82:6473597d706e	544	uint16_t TOVALHIGH : 16; //!< [15:0]
bogdanm	82:6473597d706e	545	} B;
bogdanm	82:6473597d706e	546	} hw_wdog_tovalh_t;
bogdanm	82:6473597d706e	547	#endif
bogdanm	82:6473597d706e	548
bogdanm	82:6473597d706e	549	/*!
bogdanm	82:6473597d706e	550	* @name Constants and macros for entire WDOG_TOVALH register
bogdanm	82:6473597d706e	551	*/
bogdanm	82:6473597d706e	552	//@{
bogdanm	82:6473597d706e	553	#define HW_WDOG_TOVALH_ADDR (REGS_WDOG_BASE + 0x4U)
bogdanm	82:6473597d706e	554
bogdanm	82:6473597d706e	555	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	556	#define HW_WDOG_TOVALH ((__IO hw_wdog_tovalh_t ) HW_WDOG_TOVALH_ADDR)
bogdanm	82:6473597d706e	557	#define HW_WDOG_TOVALH_RD() (HW_WDOG_TOVALH.U)
bogdanm	82:6473597d706e	558	#define HW_WDOG_TOVALH_WR(v) (HW_WDOG_TOVALH.U = (v))
bogdanm	82:6473597d706e	559	#define HW_WDOG_TOVALH_SET(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() \| (v)))
bogdanm	82:6473597d706e	560	#define HW_WDOG_TOVALH_CLR(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() & ~(v)))
bogdanm	82:6473597d706e	561	#define HW_WDOG_TOVALH_TOG(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() ^ (v)))
bogdanm	82:6473597d706e	562	#endif
bogdanm	82:6473597d706e	563	//@}
bogdanm	82:6473597d706e	564
bogdanm	82:6473597d706e	565	/*
bogdanm	82:6473597d706e	566	* Constants & macros for individual WDOG_TOVALH bitfields
bogdanm	82:6473597d706e	567	*/
bogdanm	82:6473597d706e	568
bogdanm	82:6473597d706e	569	/*!
bogdanm	82:6473597d706e	570	* @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
bogdanm	82:6473597d706e	571	*
bogdanm	82:6473597d706e	572	* Defines the upper 16 bits of the 32-bit time-out value for the watchdog
bogdanm	82:6473597d706e	573	* timer. It is defined in terms of cycles of the watchdog clock.
bogdanm	82:6473597d706e	574	*/
bogdanm	82:6473597d706e	575	//@{
bogdanm	82:6473597d706e	576	#define BP_WDOG_TOVALH_TOVALHIGH (0U) //!< Bit position for WDOG_TOVALH_TOVALHIGH.
bogdanm	82:6473597d706e	577	#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) //!< Bit mask for WDOG_TOVALH_TOVALHIGH.
bogdanm	82:6473597d706e	578	#define BS_WDOG_TOVALH_TOVALHIGH (16U) //!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH.
bogdanm	82:6473597d706e	579
bogdanm	82:6473597d706e	580	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	581	//! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field.
bogdanm	82:6473597d706e	582	#define BR_WDOG_TOVALH_TOVALHIGH (HW_WDOG_TOVALH.U)
bogdanm	82:6473597d706e	583	#endif
bogdanm	82:6473597d706e	584
bogdanm	82:6473597d706e	585	//! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH.
bogdanm	82:6473597d706e	586	#define BF_WDOG_TOVALH_TOVALHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALH_TOVALHIGH), uint16_t) & BM_WDOG_TOVALH_TOVALHIGH)
bogdanm	82:6473597d706e	587
bogdanm	82:6473597d706e	588	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	589	//! @brief Set the TOVALHIGH field to a new value.
bogdanm	82:6473597d706e	590	#define BW_WDOG_TOVALH_TOVALHIGH(v) (HW_WDOG_TOVALH_WR(v))
bogdanm	82:6473597d706e	591	#endif
bogdanm	82:6473597d706e	592	//@}
bogdanm	82:6473597d706e	593
bogdanm	82:6473597d706e	594	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	595	// HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
bogdanm	82:6473597d706e	596	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	597
bogdanm	82:6473597d706e	598	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	599	/*!
bogdanm	82:6473597d706e	600	* @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
bogdanm	82:6473597d706e	601	*
bogdanm	82:6473597d706e	602	* Reset value: 0x4B4CU
bogdanm	82:6473597d706e	603	*
bogdanm	82:6473597d706e	604	* The time-out value of the watchdog must be set to a minimum of four watchdog
bogdanm	82:6473597d706e	605	* clock cycles. This is to take into account the delay in new settings taking
bogdanm	82:6473597d706e	606	* effect in the watchdog clock domain.
bogdanm	82:6473597d706e	607	*/
bogdanm	82:6473597d706e	608	typedef union _hw_wdog_tovall
bogdanm	82:6473597d706e	609	{
bogdanm	82:6473597d706e	610	uint16_t U;
bogdanm	82:6473597d706e	611	struct _hw_wdog_tovall_bitfields
bogdanm	82:6473597d706e	612	{
bogdanm	82:6473597d706e	613	uint16_t TOVALLOW : 16; //!< [15:0]
bogdanm	82:6473597d706e	614	} B;
bogdanm	82:6473597d706e	615	} hw_wdog_tovall_t;
bogdanm	82:6473597d706e	616	#endif
bogdanm	82:6473597d706e	617
bogdanm	82:6473597d706e	618	/*!
bogdanm	82:6473597d706e	619	* @name Constants and macros for entire WDOG_TOVALL register
bogdanm	82:6473597d706e	620	*/
bogdanm	82:6473597d706e	621	//@{
bogdanm	82:6473597d706e	622	#define HW_WDOG_TOVALL_ADDR (REGS_WDOG_BASE + 0x6U)
bogdanm	82:6473597d706e	623
bogdanm	82:6473597d706e	624	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	625	#define HW_WDOG_TOVALL ((__IO hw_wdog_tovall_t ) HW_WDOG_TOVALL_ADDR)
bogdanm	82:6473597d706e	626	#define HW_WDOG_TOVALL_RD() (HW_WDOG_TOVALL.U)
bogdanm	82:6473597d706e	627	#define HW_WDOG_TOVALL_WR(v) (HW_WDOG_TOVALL.U = (v))
bogdanm	82:6473597d706e	628	#define HW_WDOG_TOVALL_SET(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() \| (v)))
bogdanm	82:6473597d706e	629	#define HW_WDOG_TOVALL_CLR(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() & ~(v)))
bogdanm	82:6473597d706e	630	#define HW_WDOG_TOVALL_TOG(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() ^ (v)))
bogdanm	82:6473597d706e	631	#endif
bogdanm	82:6473597d706e	632	//@}
bogdanm	82:6473597d706e	633
bogdanm	82:6473597d706e	634	/*
bogdanm	82:6473597d706e	635	* Constants & macros for individual WDOG_TOVALL bitfields
bogdanm	82:6473597d706e	636	*/
bogdanm	82:6473597d706e	637
bogdanm	82:6473597d706e	638	/*!
bogdanm	82:6473597d706e	639	* @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
bogdanm	82:6473597d706e	640	*
bogdanm	82:6473597d706e	641	* Defines the lower 16 bits of the 32-bit time-out value for the watchdog
bogdanm	82:6473597d706e	642	* timer. It is defined in terms of cycles of the watchdog clock.
bogdanm	82:6473597d706e	643	*/
bogdanm	82:6473597d706e	644	//@{
bogdanm	82:6473597d706e	645	#define BP_WDOG_TOVALL_TOVALLOW (0U) //!< Bit position for WDOG_TOVALL_TOVALLOW.
bogdanm	82:6473597d706e	646	#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) //!< Bit mask for WDOG_TOVALL_TOVALLOW.
bogdanm	82:6473597d706e	647	#define BS_WDOG_TOVALL_TOVALLOW (16U) //!< Bit field size in bits for WDOG_TOVALL_TOVALLOW.
bogdanm	82:6473597d706e	648
bogdanm	82:6473597d706e	649	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	650	//! @brief Read current value of the WDOG_TOVALL_TOVALLOW field.
bogdanm	82:6473597d706e	651	#define BR_WDOG_TOVALL_TOVALLOW (HW_WDOG_TOVALL.U)
bogdanm	82:6473597d706e	652	#endif
bogdanm	82:6473597d706e	653
bogdanm	82:6473597d706e	654	//! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW.
bogdanm	82:6473597d706e	655	#define BF_WDOG_TOVALL_TOVALLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALL_TOVALLOW), uint16_t) & BM_WDOG_TOVALL_TOVALLOW)
bogdanm	82:6473597d706e	656
bogdanm	82:6473597d706e	657	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	658	//! @brief Set the TOVALLOW field to a new value.
bogdanm	82:6473597d706e	659	#define BW_WDOG_TOVALL_TOVALLOW(v) (HW_WDOG_TOVALL_WR(v))
bogdanm	82:6473597d706e	660	#endif
bogdanm	82:6473597d706e	661	//@}
bogdanm	82:6473597d706e	662
bogdanm	82:6473597d706e	663	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	664	// HW_WDOG_WINH - Watchdog Window Register High
bogdanm	82:6473597d706e	665	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	666
bogdanm	82:6473597d706e	667	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	668	/*!
bogdanm	82:6473597d706e	669	* @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
bogdanm	82:6473597d706e	670	*
bogdanm	82:6473597d706e	671	* Reset value: 0x0000U
bogdanm	82:6473597d706e	672	*
bogdanm	82:6473597d706e	673	* You must set the Window Register value lower than the Time-out Value Register.
bogdanm	82:6473597d706e	674	*/
bogdanm	82:6473597d706e	675	typedef union _hw_wdog_winh
bogdanm	82:6473597d706e	676	{
bogdanm	82:6473597d706e	677	uint16_t U;
bogdanm	82:6473597d706e	678	struct _hw_wdog_winh_bitfields
bogdanm	82:6473597d706e	679	{
bogdanm	82:6473597d706e	680	uint16_t WINHIGH : 16; //!< [15:0]
bogdanm	82:6473597d706e	681	} B;
bogdanm	82:6473597d706e	682	} hw_wdog_winh_t;
bogdanm	82:6473597d706e	683	#endif
bogdanm	82:6473597d706e	684
bogdanm	82:6473597d706e	685	/*!
bogdanm	82:6473597d706e	686	* @name Constants and macros for entire WDOG_WINH register
bogdanm	82:6473597d706e	687	*/
bogdanm	82:6473597d706e	688	//@{
bogdanm	82:6473597d706e	689	#define HW_WDOG_WINH_ADDR (REGS_WDOG_BASE + 0x8U)
bogdanm	82:6473597d706e	690
bogdanm	82:6473597d706e	691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	692	#define HW_WDOG_WINH ((__IO hw_wdog_winh_t ) HW_WDOG_WINH_ADDR)
bogdanm	82:6473597d706e	693	#define HW_WDOG_WINH_RD() (HW_WDOG_WINH.U)
bogdanm	82:6473597d706e	694	#define HW_WDOG_WINH_WR(v) (HW_WDOG_WINH.U = (v))
bogdanm	82:6473597d706e	695	#define HW_WDOG_WINH_SET(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() \| (v)))
bogdanm	82:6473597d706e	696	#define HW_WDOG_WINH_CLR(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() & ~(v)))
bogdanm	82:6473597d706e	697	#define HW_WDOG_WINH_TOG(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() ^ (v)))
bogdanm	82:6473597d706e	698	#endif
bogdanm	82:6473597d706e	699	//@}
bogdanm	82:6473597d706e	700
bogdanm	82:6473597d706e	701	/*
bogdanm	82:6473597d706e	702	* Constants & macros for individual WDOG_WINH bitfields
bogdanm	82:6473597d706e	703	*/
bogdanm	82:6473597d706e	704
bogdanm	82:6473597d706e	705	/*!
bogdanm	82:6473597d706e	706	* @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
bogdanm	82:6473597d706e	707	*
bogdanm	82:6473597d706e	708	* Defines the upper 16 bits of the 32-bit window for the windowed mode of
bogdanm	82:6473597d706e	709	* operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
bogdanm	82:6473597d706e	710	* In this mode, the watchdog can be refreshed only when the timer has reached a
bogdanm	82:6473597d706e	711	* value greater than or equal to this window length. A refresh outside this
bogdanm	82:6473597d706e	712	* window resets the system or if IRQRSTEN is set, it interrupts and then resets the
bogdanm	82:6473597d706e	713	* system.
bogdanm	82:6473597d706e	714	*/
bogdanm	82:6473597d706e	715	//@{
bogdanm	82:6473597d706e	716	#define BP_WDOG_WINH_WINHIGH (0U) //!< Bit position for WDOG_WINH_WINHIGH.
bogdanm	82:6473597d706e	717	#define BM_WDOG_WINH_WINHIGH (0xFFFFU) //!< Bit mask for WDOG_WINH_WINHIGH.
bogdanm	82:6473597d706e	718	#define BS_WDOG_WINH_WINHIGH (16U) //!< Bit field size in bits for WDOG_WINH_WINHIGH.
bogdanm	82:6473597d706e	719
bogdanm	82:6473597d706e	720	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	721	//! @brief Read current value of the WDOG_WINH_WINHIGH field.
bogdanm	82:6473597d706e	722	#define BR_WDOG_WINH_WINHIGH (HW_WDOG_WINH.U)
bogdanm	82:6473597d706e	723	#endif
bogdanm	82:6473597d706e	724
bogdanm	82:6473597d706e	725	//! @brief Format value for bitfield WDOG_WINH_WINHIGH.
bogdanm	82:6473597d706e	726	#define BF_WDOG_WINH_WINHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINH_WINHIGH), uint16_t) & BM_WDOG_WINH_WINHIGH)
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	729	//! @brief Set the WINHIGH field to a new value.
bogdanm	82:6473597d706e	730	#define BW_WDOG_WINH_WINHIGH(v) (HW_WDOG_WINH_WR(v))
bogdanm	82:6473597d706e	731	#endif
bogdanm	82:6473597d706e	732	//@}
bogdanm	82:6473597d706e	733
bogdanm	82:6473597d706e	734	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	735	// HW_WDOG_WINL - Watchdog Window Register Low
bogdanm	82:6473597d706e	736	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	737
bogdanm	82:6473597d706e	738	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	739	/*!
bogdanm	82:6473597d706e	740	* @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
bogdanm	82:6473597d706e	741	*
bogdanm	82:6473597d706e	742	* Reset value: 0x0010U
bogdanm	82:6473597d706e	743	*
bogdanm	82:6473597d706e	744	* You must set the Window Register value lower than the Time-out Value Register.
bogdanm	82:6473597d706e	745	*/
bogdanm	82:6473597d706e	746	typedef union _hw_wdog_winl
bogdanm	82:6473597d706e	747	{
bogdanm	82:6473597d706e	748	uint16_t U;
bogdanm	82:6473597d706e	749	struct _hw_wdog_winl_bitfields
bogdanm	82:6473597d706e	750	{
bogdanm	82:6473597d706e	751	uint16_t WINLOW : 16; //!< [15:0]
bogdanm	82:6473597d706e	752	} B;
bogdanm	82:6473597d706e	753	} hw_wdog_winl_t;
bogdanm	82:6473597d706e	754	#endif
bogdanm	82:6473597d706e	755
bogdanm	82:6473597d706e	756	/*!
bogdanm	82:6473597d706e	757	* @name Constants and macros for entire WDOG_WINL register
bogdanm	82:6473597d706e	758	*/
bogdanm	82:6473597d706e	759	//@{
bogdanm	82:6473597d706e	760	#define HW_WDOG_WINL_ADDR (REGS_WDOG_BASE + 0xAU)
bogdanm	82:6473597d706e	761
bogdanm	82:6473597d706e	762	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	763	#define HW_WDOG_WINL ((__IO hw_wdog_winl_t ) HW_WDOG_WINL_ADDR)
bogdanm	82:6473597d706e	764	#define HW_WDOG_WINL_RD() (HW_WDOG_WINL.U)
bogdanm	82:6473597d706e	765	#define HW_WDOG_WINL_WR(v) (HW_WDOG_WINL.U = (v))
bogdanm	82:6473597d706e	766	#define HW_WDOG_WINL_SET(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() \| (v)))
bogdanm	82:6473597d706e	767	#define HW_WDOG_WINL_CLR(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() & ~(v)))
bogdanm	82:6473597d706e	768	#define HW_WDOG_WINL_TOG(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() ^ (v)))
bogdanm	82:6473597d706e	769	#endif
bogdanm	82:6473597d706e	770	//@}
bogdanm	82:6473597d706e	771
bogdanm	82:6473597d706e	772	/*
bogdanm	82:6473597d706e	773	* Constants & macros for individual WDOG_WINL bitfields
bogdanm	82:6473597d706e	774	*/
bogdanm	82:6473597d706e	775
bogdanm	82:6473597d706e	776	/*!
bogdanm	82:6473597d706e	777	* @name Register WDOG_WINL, field WINLOW[15:0] (RW)
bogdanm	82:6473597d706e	778	*
bogdanm	82:6473597d706e	779	* Defines the lower 16 bits of the 32-bit window for the windowed mode of
bogdanm	82:6473597d706e	780	* operation of the watchdog. It is defined in terms of cycles of the pre-scaled
bogdanm	82:6473597d706e	781	* watchdog clock. In this mode, the watchdog can be refreshed only when the timer
bogdanm	82:6473597d706e	782	* reaches a value greater than or equal to this window length value. A refresh
bogdanm	82:6473597d706e	783	* outside of this window resets the system or if IRQRSTEN is set, it interrupts and
bogdanm	82:6473597d706e	784	* then resets the system.
bogdanm	82:6473597d706e	785	*/
bogdanm	82:6473597d706e	786	//@{
bogdanm	82:6473597d706e	787	#define BP_WDOG_WINL_WINLOW (0U) //!< Bit position for WDOG_WINL_WINLOW.
bogdanm	82:6473597d706e	788	#define BM_WDOG_WINL_WINLOW (0xFFFFU) //!< Bit mask for WDOG_WINL_WINLOW.
bogdanm	82:6473597d706e	789	#define BS_WDOG_WINL_WINLOW (16U) //!< Bit field size in bits for WDOG_WINL_WINLOW.
bogdanm	82:6473597d706e	790
bogdanm	82:6473597d706e	791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	792	//! @brief Read current value of the WDOG_WINL_WINLOW field.
bogdanm	82:6473597d706e	793	#define BR_WDOG_WINL_WINLOW (HW_WDOG_WINL.U)
bogdanm	82:6473597d706e	794	#endif
bogdanm	82:6473597d706e	795
bogdanm	82:6473597d706e	796	//! @brief Format value for bitfield WDOG_WINL_WINLOW.
bogdanm	82:6473597d706e	797	#define BF_WDOG_WINL_WINLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINL_WINLOW), uint16_t) & BM_WDOG_WINL_WINLOW)
bogdanm	82:6473597d706e	798
bogdanm	82:6473597d706e	799	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	800	//! @brief Set the WINLOW field to a new value.
bogdanm	82:6473597d706e	801	#define BW_WDOG_WINL_WINLOW(v) (HW_WDOG_WINL_WR(v))
bogdanm	82:6473597d706e	802	#endif
bogdanm	82:6473597d706e	803	//@}
bogdanm	82:6473597d706e	804
bogdanm	82:6473597d706e	805	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	806	// HW_WDOG_REFRESH - Watchdog Refresh register
bogdanm	82:6473597d706e	807	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	808
bogdanm	82:6473597d706e	809	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	810	/*!
bogdanm	82:6473597d706e	811	* @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
bogdanm	82:6473597d706e	812	*
bogdanm	82:6473597d706e	813	* Reset value: 0xB480U
bogdanm	82:6473597d706e	814	*/
bogdanm	82:6473597d706e	815	typedef union _hw_wdog_refresh
bogdanm	82:6473597d706e	816	{
bogdanm	82:6473597d706e	817	uint16_t U;
bogdanm	82:6473597d706e	818	struct _hw_wdog_refresh_bitfields
bogdanm	82:6473597d706e	819	{
bogdanm	82:6473597d706e	820	uint16_t WDOGREFRESH : 16; //!< [15:0]
bogdanm	82:6473597d706e	821	} B;
bogdanm	82:6473597d706e	822	} hw_wdog_refresh_t;
bogdanm	82:6473597d706e	823	#endif
bogdanm	82:6473597d706e	824
bogdanm	82:6473597d706e	825	/*!
bogdanm	82:6473597d706e	826	* @name Constants and macros for entire WDOG_REFRESH register
bogdanm	82:6473597d706e	827	*/
bogdanm	82:6473597d706e	828	//@{
bogdanm	82:6473597d706e	829	#define HW_WDOG_REFRESH_ADDR (REGS_WDOG_BASE + 0xCU)
bogdanm	82:6473597d706e	830
bogdanm	82:6473597d706e	831	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	832	#define HW_WDOG_REFRESH ((__IO hw_wdog_refresh_t ) HW_WDOG_REFRESH_ADDR)
bogdanm	82:6473597d706e	833	#define HW_WDOG_REFRESH_RD() (HW_WDOG_REFRESH.U)
bogdanm	82:6473597d706e	834	#define HW_WDOG_REFRESH_WR(v) (HW_WDOG_REFRESH.U = (v))
bogdanm	82:6473597d706e	835	#define HW_WDOG_REFRESH_SET(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() \| (v)))
bogdanm	82:6473597d706e	836	#define HW_WDOG_REFRESH_CLR(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() & ~(v)))
bogdanm	82:6473597d706e	837	#define HW_WDOG_REFRESH_TOG(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() ^ (v)))
bogdanm	82:6473597d706e	838	#endif
bogdanm	82:6473597d706e	839	//@}
bogdanm	82:6473597d706e	840
bogdanm	82:6473597d706e	841	/*
bogdanm	82:6473597d706e	842	* Constants & macros for individual WDOG_REFRESH bitfields
bogdanm	82:6473597d706e	843	*/
bogdanm	82:6473597d706e	844
bogdanm	82:6473597d706e	845	/*!
bogdanm	82:6473597d706e	846	* @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
bogdanm	82:6473597d706e	847	*
bogdanm	82:6473597d706e	848	* Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
bogdanm	82:6473597d706e	849	* bus clock cycles written to this register refreshes the WDOG and prevents it
bogdanm	82:6473597d706e	850	* from resetting the system. Writing a value other than the above mentioned
bogdanm	82:6473597d706e	851	* sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
bogdanm	82:6473597d706e	852	* IRQRSTEN is set, it interrupts and then resets the system.
bogdanm	82:6473597d706e	853	*/
bogdanm	82:6473597d706e	854	//@{
bogdanm	82:6473597d706e	855	#define BP_WDOG_REFRESH_WDOGREFRESH (0U) //!< Bit position for WDOG_REFRESH_WDOGREFRESH.
bogdanm	82:6473597d706e	856	#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) //!< Bit mask for WDOG_REFRESH_WDOGREFRESH.
bogdanm	82:6473597d706e	857	#define BS_WDOG_REFRESH_WDOGREFRESH (16U) //!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH.
bogdanm	82:6473597d706e	858
bogdanm	82:6473597d706e	859	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	860	//! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field.
bogdanm	82:6473597d706e	861	#define BR_WDOG_REFRESH_WDOGREFRESH (HW_WDOG_REFRESH.U)
bogdanm	82:6473597d706e	862	#endif
bogdanm	82:6473597d706e	863
bogdanm	82:6473597d706e	864	//! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH.
bogdanm	82:6473597d706e	865	#define BF_WDOG_REFRESH_WDOGREFRESH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_REFRESH_WDOGREFRESH), uint16_t) & BM_WDOG_REFRESH_WDOGREFRESH)
bogdanm	82:6473597d706e	866
bogdanm	82:6473597d706e	867	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	868	//! @brief Set the WDOGREFRESH field to a new value.
bogdanm	82:6473597d706e	869	#define BW_WDOG_REFRESH_WDOGREFRESH(v) (HW_WDOG_REFRESH_WR(v))
bogdanm	82:6473597d706e	870	#endif
bogdanm	82:6473597d706e	871	//@}
bogdanm	82:6473597d706e	872
bogdanm	82:6473597d706e	873	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	874	// HW_WDOG_UNLOCK - Watchdog Unlock register
bogdanm	82:6473597d706e	875	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	876
bogdanm	82:6473597d706e	877	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	878	/*!
bogdanm	82:6473597d706e	879	* @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
bogdanm	82:6473597d706e	880	*
bogdanm	82:6473597d706e	881	* Reset value: 0xD928U
bogdanm	82:6473597d706e	882	*/
bogdanm	82:6473597d706e	883	typedef union _hw_wdog_unlock
bogdanm	82:6473597d706e	884	{
bogdanm	82:6473597d706e	885	uint16_t U;
bogdanm	82:6473597d706e	886	struct _hw_wdog_unlock_bitfields
bogdanm	82:6473597d706e	887	{
bogdanm	82:6473597d706e	888	uint16_t WDOGUNLOCK : 16; //!< [15:0]
bogdanm	82:6473597d706e	889	} B;
bogdanm	82:6473597d706e	890	} hw_wdog_unlock_t;
bogdanm	82:6473597d706e	891	#endif
bogdanm	82:6473597d706e	892
bogdanm	82:6473597d706e	893	/*!
bogdanm	82:6473597d706e	894	* @name Constants and macros for entire WDOG_UNLOCK register
bogdanm	82:6473597d706e	895	*/
bogdanm	82:6473597d706e	896	//@{
bogdanm	82:6473597d706e	897	#define HW_WDOG_UNLOCK_ADDR (REGS_WDOG_BASE + 0xEU)
bogdanm	82:6473597d706e	898
bogdanm	82:6473597d706e	899	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	900	#define HW_WDOG_UNLOCK ((__IO hw_wdog_unlock_t ) HW_WDOG_UNLOCK_ADDR)
bogdanm	82:6473597d706e	901	#define HW_WDOG_UNLOCK_RD() (HW_WDOG_UNLOCK.U)
bogdanm	82:6473597d706e	902	#define HW_WDOG_UNLOCK_WR(v) (HW_WDOG_UNLOCK.U = (v))
bogdanm	82:6473597d706e	903	#define HW_WDOG_UNLOCK_SET(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() \| (v)))
bogdanm	82:6473597d706e	904	#define HW_WDOG_UNLOCK_CLR(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() & ~(v)))
bogdanm	82:6473597d706e	905	#define HW_WDOG_UNLOCK_TOG(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() ^ (v)))
bogdanm	82:6473597d706e	906	#endif
bogdanm	82:6473597d706e	907	//@}
bogdanm	82:6473597d706e	908
bogdanm	82:6473597d706e	909	/*
bogdanm	82:6473597d706e	910	* Constants & macros for individual WDOG_UNLOCK bitfields
bogdanm	82:6473597d706e	911	*/
bogdanm	82:6473597d706e	912
bogdanm	82:6473597d706e	913	/*!
bogdanm	82:6473597d706e	914	* @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
bogdanm	82:6473597d706e	915	*
bogdanm	82:6473597d706e	916	* Writing the unlock sequence values to this register to makes the watchdog
bogdanm	82:6473597d706e	917	* write-once registers writable again. The required unlock sequence is 0xC520
bogdanm	82:6473597d706e	918	* followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
bogdanm	82:6473597d706e	919	* window equal in length to the WCT within which you can update the registers.
bogdanm	82:6473597d706e	920	* Writing a value other than the above mentioned sequence or if the sequence is
bogdanm	82:6473597d706e	921	* longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
bogdanm	82:6473597d706e	922	* and then resets the system. The unlock sequence is effective only if
bogdanm	82:6473597d706e	923	* ALLOWUPDATE is set.
bogdanm	82:6473597d706e	924	*/
bogdanm	82:6473597d706e	925	//@{
bogdanm	82:6473597d706e	926	#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) //!< Bit position for WDOG_UNLOCK_WDOGUNLOCK.
bogdanm	82:6473597d706e	927	#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) //!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK.
bogdanm	82:6473597d706e	928	#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) //!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK.
bogdanm	82:6473597d706e	929
bogdanm	82:6473597d706e	930	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	931	//! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field.
bogdanm	82:6473597d706e	932	#define BR_WDOG_UNLOCK_WDOGUNLOCK (HW_WDOG_UNLOCK.U)
bogdanm	82:6473597d706e	933	#endif
bogdanm	82:6473597d706e	934
bogdanm	82:6473597d706e	935	//! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK.
bogdanm	82:6473597d706e	936	#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_UNLOCK_WDOGUNLOCK), uint16_t) & BM_WDOG_UNLOCK_WDOGUNLOCK)
bogdanm	82:6473597d706e	937
bogdanm	82:6473597d706e	938	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	939	//! @brief Set the WDOGUNLOCK field to a new value.
bogdanm	82:6473597d706e	940	#define BW_WDOG_UNLOCK_WDOGUNLOCK(v) (HW_WDOG_UNLOCK_WR(v))
bogdanm	82:6473597d706e	941	#endif
bogdanm	82:6473597d706e	942	//@}
bogdanm	82:6473597d706e	943
bogdanm	82:6473597d706e	944	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	945	// HW_WDOG_TMROUTH - Watchdog Timer Output Register High
bogdanm	82:6473597d706e	946	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	947
bogdanm	82:6473597d706e	948	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	949	/*!
bogdanm	82:6473597d706e	950	* @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
bogdanm	82:6473597d706e	951	*
bogdanm	82:6473597d706e	952	* Reset value: 0x0000U
bogdanm	82:6473597d706e	953	*/
bogdanm	82:6473597d706e	954	typedef union _hw_wdog_tmrouth
bogdanm	82:6473597d706e	955	{
bogdanm	82:6473597d706e	956	uint16_t U;
bogdanm	82:6473597d706e	957	struct _hw_wdog_tmrouth_bitfields
bogdanm	82:6473597d706e	958	{
bogdanm	82:6473597d706e	959	uint16_t TIMEROUTHIGH : 16; //!< [15:0]
bogdanm	82:6473597d706e	960	} B;
bogdanm	82:6473597d706e	961	} hw_wdog_tmrouth_t;
bogdanm	82:6473597d706e	962	#endif
bogdanm	82:6473597d706e	963
bogdanm	82:6473597d706e	964	/*!
bogdanm	82:6473597d706e	965	* @name Constants and macros for entire WDOG_TMROUTH register
bogdanm	82:6473597d706e	966	*/
bogdanm	82:6473597d706e	967	//@{
bogdanm	82:6473597d706e	968	#define HW_WDOG_TMROUTH_ADDR (REGS_WDOG_BASE + 0x10U)
bogdanm	82:6473597d706e	969
bogdanm	82:6473597d706e	970	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	971	#define HW_WDOG_TMROUTH ((__IO hw_wdog_tmrouth_t ) HW_WDOG_TMROUTH_ADDR)
bogdanm	82:6473597d706e	972	#define HW_WDOG_TMROUTH_RD() (HW_WDOG_TMROUTH.U)
bogdanm	82:6473597d706e	973	#define HW_WDOG_TMROUTH_WR(v) (HW_WDOG_TMROUTH.U = (v))
bogdanm	82:6473597d706e	974	#define HW_WDOG_TMROUTH_SET(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() \| (v)))
bogdanm	82:6473597d706e	975	#define HW_WDOG_TMROUTH_CLR(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() & ~(v)))
bogdanm	82:6473597d706e	976	#define HW_WDOG_TMROUTH_TOG(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() ^ (v)))
bogdanm	82:6473597d706e	977	#endif
bogdanm	82:6473597d706e	978	//@}
bogdanm	82:6473597d706e	979
bogdanm	82:6473597d706e	980	/*
bogdanm	82:6473597d706e	981	* Constants & macros for individual WDOG_TMROUTH bitfields
bogdanm	82:6473597d706e	982	*/
bogdanm	82:6473597d706e	983
bogdanm	82:6473597d706e	984	/*!
bogdanm	82:6473597d706e	985	* @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
bogdanm	82:6473597d706e	986	*
bogdanm	82:6473597d706e	987	* Shows the value of the upper 16 bits of the watchdog timer.
bogdanm	82:6473597d706e	988	*/
bogdanm	82:6473597d706e	989	//@{
bogdanm	82:6473597d706e	990	#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) //!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH.
bogdanm	82:6473597d706e	991	#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) //!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH.
bogdanm	82:6473597d706e	992	#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) //!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH.
bogdanm	82:6473597d706e	993
bogdanm	82:6473597d706e	994	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	995	//! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field.
bogdanm	82:6473597d706e	996	#define BR_WDOG_TMROUTH_TIMEROUTHIGH (HW_WDOG_TMROUTH.U)
bogdanm	82:6473597d706e	997	#endif
bogdanm	82:6473597d706e	998
bogdanm	82:6473597d706e	999	//! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH.
bogdanm	82:6473597d706e	1000	#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTH_TIMEROUTHIGH), uint16_t) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
bogdanm	82:6473597d706e	1001
bogdanm	82:6473597d706e	1002	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1003	//! @brief Set the TIMEROUTHIGH field to a new value.
bogdanm	82:6473597d706e	1004	#define BW_WDOG_TMROUTH_TIMEROUTHIGH(v) (HW_WDOG_TMROUTH_WR(v))
bogdanm	82:6473597d706e	1005	#endif
bogdanm	82:6473597d706e	1006	//@}
bogdanm	82:6473597d706e	1007
bogdanm	82:6473597d706e	1008	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1009	// HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
bogdanm	82:6473597d706e	1010	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1011
bogdanm	82:6473597d706e	1012	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1013	/*!
bogdanm	82:6473597d706e	1014	* @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
bogdanm	82:6473597d706e	1015	*
bogdanm	82:6473597d706e	1016	* Reset value: 0x0000U
bogdanm	82:6473597d706e	1017	*
bogdanm	82:6473597d706e	1018	* During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
bogdanm	82:6473597d706e	1019	* the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
bogdanm	82:6473597d706e	1020	* cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
bogdanm	82:6473597d706e	1021	* the watchdog timer.
bogdanm	82:6473597d706e	1022	*/
bogdanm	82:6473597d706e	1023	typedef union _hw_wdog_tmroutl
bogdanm	82:6473597d706e	1024	{
bogdanm	82:6473597d706e	1025	uint16_t U;
bogdanm	82:6473597d706e	1026	struct _hw_wdog_tmroutl_bitfields
bogdanm	82:6473597d706e	1027	{
bogdanm	82:6473597d706e	1028	uint16_t TIMEROUTLOW : 16; //!< [15:0]
bogdanm	82:6473597d706e	1029	} B;
bogdanm	82:6473597d706e	1030	} hw_wdog_tmroutl_t;
bogdanm	82:6473597d706e	1031	#endif
bogdanm	82:6473597d706e	1032
bogdanm	82:6473597d706e	1033	/*!
bogdanm	82:6473597d706e	1034	* @name Constants and macros for entire WDOG_TMROUTL register
bogdanm	82:6473597d706e	1035	*/
bogdanm	82:6473597d706e	1036	//@{
bogdanm	82:6473597d706e	1037	#define HW_WDOG_TMROUTL_ADDR (REGS_WDOG_BASE + 0x12U)
bogdanm	82:6473597d706e	1038
bogdanm	82:6473597d706e	1039	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1040	#define HW_WDOG_TMROUTL ((__IO hw_wdog_tmroutl_t ) HW_WDOG_TMROUTL_ADDR)
bogdanm	82:6473597d706e	1041	#define HW_WDOG_TMROUTL_RD() (HW_WDOG_TMROUTL.U)
bogdanm	82:6473597d706e	1042	#define HW_WDOG_TMROUTL_WR(v) (HW_WDOG_TMROUTL.U = (v))
bogdanm	82:6473597d706e	1043	#define HW_WDOG_TMROUTL_SET(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() \| (v)))
bogdanm	82:6473597d706e	1044	#define HW_WDOG_TMROUTL_CLR(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() & ~(v)))
bogdanm	82:6473597d706e	1045	#define HW_WDOG_TMROUTL_TOG(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() ^ (v)))
bogdanm	82:6473597d706e	1046	#endif
bogdanm	82:6473597d706e	1047	//@}
bogdanm	82:6473597d706e	1048
bogdanm	82:6473597d706e	1049	/*
bogdanm	82:6473597d706e	1050	* Constants & macros for individual WDOG_TMROUTL bitfields
bogdanm	82:6473597d706e	1051	*/
bogdanm	82:6473597d706e	1052
bogdanm	82:6473597d706e	1053	/*!
bogdanm	82:6473597d706e	1054	* @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
bogdanm	82:6473597d706e	1055	*
bogdanm	82:6473597d706e	1056	* Shows the value of the lower 16 bits of the watchdog timer.
bogdanm	82:6473597d706e	1057	*/
bogdanm	82:6473597d706e	1058	//@{
bogdanm	82:6473597d706e	1059	#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) //!< Bit position for WDOG_TMROUTL_TIMEROUTLOW.
bogdanm	82:6473597d706e	1060	#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) //!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW.
bogdanm	82:6473597d706e	1061	#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) //!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW.
bogdanm	82:6473597d706e	1062
bogdanm	82:6473597d706e	1063	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1064	//! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field.
bogdanm	82:6473597d706e	1065	#define BR_WDOG_TMROUTL_TIMEROUTLOW (HW_WDOG_TMROUTL.U)
bogdanm	82:6473597d706e	1066	#endif
bogdanm	82:6473597d706e	1067
bogdanm	82:6473597d706e	1068	//! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW.
bogdanm	82:6473597d706e	1069	#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTL_TIMEROUTLOW), uint16_t) & BM_WDOG_TMROUTL_TIMEROUTLOW)
bogdanm	82:6473597d706e	1070
bogdanm	82:6473597d706e	1071	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1072	//! @brief Set the TIMEROUTLOW field to a new value.
bogdanm	82:6473597d706e	1073	#define BW_WDOG_TMROUTL_TIMEROUTLOW(v) (HW_WDOG_TMROUTL_WR(v))
bogdanm	82:6473597d706e	1074	#endif
bogdanm	82:6473597d706e	1075	//@}
bogdanm	82:6473597d706e	1076
bogdanm	82:6473597d706e	1077	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1078	// HW_WDOG_RSTCNT - Watchdog Reset Count register
bogdanm	82:6473597d706e	1079	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1080
bogdanm	82:6473597d706e	1081	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1082	/*!
bogdanm	82:6473597d706e	1083	* @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
bogdanm	82:6473597d706e	1084	*
bogdanm	82:6473597d706e	1085	* Reset value: 0x0000U
bogdanm	82:6473597d706e	1086	*/
bogdanm	82:6473597d706e	1087	typedef union _hw_wdog_rstcnt
bogdanm	82:6473597d706e	1088	{
bogdanm	82:6473597d706e	1089	uint16_t U;
bogdanm	82:6473597d706e	1090	struct _hw_wdog_rstcnt_bitfields
bogdanm	82:6473597d706e	1091	{
bogdanm	82:6473597d706e	1092	uint16_t RSTCNT : 16; //!< [15:0]
bogdanm	82:6473597d706e	1093	} B;
bogdanm	82:6473597d706e	1094	} hw_wdog_rstcnt_t;
bogdanm	82:6473597d706e	1095	#endif
bogdanm	82:6473597d706e	1096
bogdanm	82:6473597d706e	1097	/*!
bogdanm	82:6473597d706e	1098	* @name Constants and macros for entire WDOG_RSTCNT register
bogdanm	82:6473597d706e	1099	*/
bogdanm	82:6473597d706e	1100	//@{
bogdanm	82:6473597d706e	1101	#define HW_WDOG_RSTCNT_ADDR (REGS_WDOG_BASE + 0x14U)
bogdanm	82:6473597d706e	1102
bogdanm	82:6473597d706e	1103	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1104	#define HW_WDOG_RSTCNT ((__IO hw_wdog_rstcnt_t ) HW_WDOG_RSTCNT_ADDR)
bogdanm	82:6473597d706e	1105	#define HW_WDOG_RSTCNT_RD() (HW_WDOG_RSTCNT.U)
bogdanm	82:6473597d706e	1106	#define HW_WDOG_RSTCNT_WR(v) (HW_WDOG_RSTCNT.U = (v))
bogdanm	82:6473597d706e	1107	#define HW_WDOG_RSTCNT_SET(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() \| (v)))
bogdanm	82:6473597d706e	1108	#define HW_WDOG_RSTCNT_CLR(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() & ~(v)))
bogdanm	82:6473597d706e	1109	#define HW_WDOG_RSTCNT_TOG(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() ^ (v)))
bogdanm	82:6473597d706e	1110	#endif
bogdanm	82:6473597d706e	1111	//@}
bogdanm	82:6473597d706e	1112
bogdanm	82:6473597d706e	1113	/*
bogdanm	82:6473597d706e	1114	* Constants & macros for individual WDOG_RSTCNT bitfields
bogdanm	82:6473597d706e	1115	*/
bogdanm	82:6473597d706e	1116
bogdanm	82:6473597d706e	1117	/*!
bogdanm	82:6473597d706e	1118	* @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
bogdanm	82:6473597d706e	1119	*
bogdanm	82:6473597d706e	1120	* Counts the number of times the watchdog resets the system. This register is
bogdanm	82:6473597d706e	1121	* reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
bogdanm	82:6473597d706e	1122	* the contents of this register.
bogdanm	82:6473597d706e	1123	*/
bogdanm	82:6473597d706e	1124	//@{
bogdanm	82:6473597d706e	1125	#define BP_WDOG_RSTCNT_RSTCNT (0U) //!< Bit position for WDOG_RSTCNT_RSTCNT.
bogdanm	82:6473597d706e	1126	#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) //!< Bit mask for WDOG_RSTCNT_RSTCNT.
bogdanm	82:6473597d706e	1127	#define BS_WDOG_RSTCNT_RSTCNT (16U) //!< Bit field size in bits for WDOG_RSTCNT_RSTCNT.
bogdanm	82:6473597d706e	1128
bogdanm	82:6473597d706e	1129	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1130	//! @brief Read current value of the WDOG_RSTCNT_RSTCNT field.
bogdanm	82:6473597d706e	1131	#define BR_WDOG_RSTCNT_RSTCNT (HW_WDOG_RSTCNT.U)
bogdanm	82:6473597d706e	1132	#endif
bogdanm	82:6473597d706e	1133
bogdanm	82:6473597d706e	1134	//! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT.
bogdanm	82:6473597d706e	1135	#define BF_WDOG_RSTCNT_RSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_RSTCNT_RSTCNT), uint16_t) & BM_WDOG_RSTCNT_RSTCNT)
bogdanm	82:6473597d706e	1136
bogdanm	82:6473597d706e	1137	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1138	//! @brief Set the RSTCNT field to a new value.
bogdanm	82:6473597d706e	1139	#define BW_WDOG_RSTCNT_RSTCNT(v) (HW_WDOG_RSTCNT_WR(v))
bogdanm	82:6473597d706e	1140	#endif
bogdanm	82:6473597d706e	1141	//@}
bogdanm	82:6473597d706e	1142
bogdanm	82:6473597d706e	1143	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1144	// HW_WDOG_PRESC - Watchdog Prescaler register
bogdanm	82:6473597d706e	1145	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1146
bogdanm	82:6473597d706e	1147	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1148	/*!
bogdanm	82:6473597d706e	1149	* @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
bogdanm	82:6473597d706e	1150	*
bogdanm	82:6473597d706e	1151	* Reset value: 0x0400U
bogdanm	82:6473597d706e	1152	*/
bogdanm	82:6473597d706e	1153	typedef union _hw_wdog_presc
bogdanm	82:6473597d706e	1154	{
bogdanm	82:6473597d706e	1155	uint16_t U;
bogdanm	82:6473597d706e	1156	struct _hw_wdog_presc_bitfields
bogdanm	82:6473597d706e	1157	{
bogdanm	82:6473597d706e	1158	uint16_t RESERVED0 : 8; //!< [7:0]
bogdanm	82:6473597d706e	1159	uint16_t PRESCVAL : 3; //!< [10:8]
bogdanm	82:6473597d706e	1160	uint16_t RESERVED1 : 5; //!< [15:11]
bogdanm	82:6473597d706e	1161	} B;
bogdanm	82:6473597d706e	1162	} hw_wdog_presc_t;
bogdanm	82:6473597d706e	1163	#endif
bogdanm	82:6473597d706e	1164
bogdanm	82:6473597d706e	1165	/*!
bogdanm	82:6473597d706e	1166	* @name Constants and macros for entire WDOG_PRESC register
bogdanm	82:6473597d706e	1167	*/
bogdanm	82:6473597d706e	1168	//@{
bogdanm	82:6473597d706e	1169	#define HW_WDOG_PRESC_ADDR (REGS_WDOG_BASE + 0x16U)
bogdanm	82:6473597d706e	1170
bogdanm	82:6473597d706e	1171	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1172	#define HW_WDOG_PRESC ((__IO hw_wdog_presc_t ) HW_WDOG_PRESC_ADDR)
bogdanm	82:6473597d706e	1173	#define HW_WDOG_PRESC_RD() (HW_WDOG_PRESC.U)
bogdanm	82:6473597d706e	1174	#define HW_WDOG_PRESC_WR(v) (HW_WDOG_PRESC.U = (v))
bogdanm	82:6473597d706e	1175	#define HW_WDOG_PRESC_SET(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() \| (v)))
bogdanm	82:6473597d706e	1176	#define HW_WDOG_PRESC_CLR(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() & ~(v)))
bogdanm	82:6473597d706e	1177	#define HW_WDOG_PRESC_TOG(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() ^ (v)))
bogdanm	82:6473597d706e	1178	#endif
bogdanm	82:6473597d706e	1179	//@}
bogdanm	82:6473597d706e	1180
bogdanm	82:6473597d706e	1181	/*
bogdanm	82:6473597d706e	1182	* Constants & macros for individual WDOG_PRESC bitfields
bogdanm	82:6473597d706e	1183	*/
bogdanm	82:6473597d706e	1184
bogdanm	82:6473597d706e	1185	/*!
bogdanm	82:6473597d706e	1186	* @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
bogdanm	82:6473597d706e	1187	*
bogdanm	82:6473597d706e	1188	* 3-bit prescaler for the watchdog clock source. A value of zero indicates no
bogdanm	82:6473597d706e	1189	* division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
bogdanm	82:6473597d706e	1190	* 1) to provide the prescaled WDOG_CLK.
bogdanm	82:6473597d706e	1191	*/
bogdanm	82:6473597d706e	1192	//@{
bogdanm	82:6473597d706e	1193	#define BP_WDOG_PRESC_PRESCVAL (8U) //!< Bit position for WDOG_PRESC_PRESCVAL.
bogdanm	82:6473597d706e	1194	#define BM_WDOG_PRESC_PRESCVAL (0x0700U) //!< Bit mask for WDOG_PRESC_PRESCVAL.
bogdanm	82:6473597d706e	1195	#define BS_WDOG_PRESC_PRESCVAL (3U) //!< Bit field size in bits for WDOG_PRESC_PRESCVAL.
bogdanm	82:6473597d706e	1196
bogdanm	82:6473597d706e	1197	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1198	//! @brief Read current value of the WDOG_PRESC_PRESCVAL field.
bogdanm	82:6473597d706e	1199	#define BR_WDOG_PRESC_PRESCVAL (HW_WDOG_PRESC.B.PRESCVAL)
bogdanm	82:6473597d706e	1200	#endif
bogdanm	82:6473597d706e	1201
bogdanm	82:6473597d706e	1202	//! @brief Format value for bitfield WDOG_PRESC_PRESCVAL.
bogdanm	82:6473597d706e	1203	#define BF_WDOG_PRESC_PRESCVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_PRESC_PRESCVAL), uint16_t) & BM_WDOG_PRESC_PRESCVAL)
bogdanm	82:6473597d706e	1204
bogdanm	82:6473597d706e	1205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1206	//! @brief Set the PRESCVAL field to a new value.
bogdanm	82:6473597d706e	1207	#define BW_WDOG_PRESC_PRESCVAL(v) (HW_WDOG_PRESC_WR((HW_WDOG_PRESC_RD() & ~BM_WDOG_PRESC_PRESCVAL) \| BF_WDOG_PRESC_PRESCVAL(v)))
bogdanm	82:6473597d706e	1208	#endif
bogdanm	82:6473597d706e	1209	//@}
bogdanm	82:6473597d706e	1210
bogdanm	82:6473597d706e	1211	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1212	// hw_wdog_t - module struct
bogdanm	82:6473597d706e	1213	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1214	/*!
bogdanm	82:6473597d706e	1215	* @brief All WDOG module registers.
bogdanm	82:6473597d706e	1216	*/
bogdanm	82:6473597d706e	1217	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1218	#pragma pack(1)
bogdanm	82:6473597d706e	1219	typedef struct _hw_wdog
bogdanm	82:6473597d706e	1220	{
bogdanm	82:6473597d706e	1221	__IO hw_wdog_stctrlh_t STCTRLH; //!< [0x0] Watchdog Status and Control Register High
bogdanm	82:6473597d706e	1222	__IO hw_wdog_stctrll_t STCTRLL; //!< [0x2] Watchdog Status and Control Register Low
bogdanm	82:6473597d706e	1223	__IO hw_wdog_tovalh_t TOVALH; //!< [0x4] Watchdog Time-out Value Register High
bogdanm	82:6473597d706e	1224	__IO hw_wdog_tovall_t TOVALL; //!< [0x6] Watchdog Time-out Value Register Low
bogdanm	82:6473597d706e	1225	__IO hw_wdog_winh_t WINH; //!< [0x8] Watchdog Window Register High
bogdanm	82:6473597d706e	1226	__IO hw_wdog_winl_t WINL; //!< [0xA] Watchdog Window Register Low
bogdanm	82:6473597d706e	1227	__IO hw_wdog_refresh_t REFRESH; //!< [0xC] Watchdog Refresh register
bogdanm	82:6473597d706e	1228	__IO hw_wdog_unlock_t UNLOCK; //!< [0xE] Watchdog Unlock register
bogdanm	82:6473597d706e	1229	__IO hw_wdog_tmrouth_t TMROUTH; //!< [0x10] Watchdog Timer Output Register High
bogdanm	82:6473597d706e	1230	__IO hw_wdog_tmroutl_t TMROUTL; //!< [0x12] Watchdog Timer Output Register Low
bogdanm	82:6473597d706e	1231	__IO hw_wdog_rstcnt_t RSTCNT; //!< [0x14] Watchdog Reset Count register
bogdanm	82:6473597d706e	1232	__IO hw_wdog_presc_t PRESC; //!< [0x16] Watchdog Prescaler register
bogdanm	82:6473597d706e	1233	} hw_wdog_t;
bogdanm	82:6473597d706e	1234	#pragma pack()
bogdanm	82:6473597d706e	1235
bogdanm	82:6473597d706e	1236	//! @brief Macro to access all WDOG registers.
bogdanm	82:6473597d706e	1237	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1238	//! use the '&' operator, like <code>&HW_WDOG</code>.
bogdanm	82:6473597d706e	1239	#define HW_WDOG ((hw_wdog_t ) REGS_WDOG_BASE)
bogdanm	82:6473597d706e	1240	#endif
bogdanm	82:6473597d706e	1241
bogdanm	82:6473597d706e	1242	#endif // __HW_WDOG_REGISTERS_H__
bogdanm	82:6473597d706e	1243	// v22/130726/0.9
bogdanm	82:6473597d706e	1244	// EOF

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
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The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_wdog.h@82:6473597d706e, 2014-04-07 (annotated)

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