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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pdb.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_PDB_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_PDB_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 PDB
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Programmable Delay Block
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_PDB_SC - Status and Control register
bogdanm	82:6473597d706e	33	* - HW_PDB_MOD - Modulus register
bogdanm	82:6473597d706e	34	* - HW_PDB_CNT - Counter register
bogdanm	82:6473597d706e	35	* - HW_PDB_IDLY - Interrupt Delay register
bogdanm	82:6473597d706e	36	* - HW_PDB_CHnC1 - Channel n Control register 1
bogdanm	82:6473597d706e	37	* - HW_PDB_CHnS - Channel n Status register
bogdanm	82:6473597d706e	38	* - HW_PDB_CHnDLY0 - Channel n Delay 0 register
bogdanm	82:6473597d706e	39	* - HW_PDB_CHnDLY1 - Channel n Delay 1 register
bogdanm	82:6473597d706e	40	* - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
bogdanm	82:6473597d706e	41	* - HW_PDB_DACINTn - DAC Interval n register
bogdanm	82:6473597d706e	42	* - HW_PDB_POEN - Pulse-Out n Enable register
bogdanm	82:6473597d706e	43	* - HW_PDB_POnDLY - Pulse-Out n Delay register
bogdanm	82:6473597d706e	44	*
bogdanm	82:6473597d706e	45	* - hw_pdb_t - Struct containing all module registers.
bogdanm	82:6473597d706e	46	*/
bogdanm	82:6473597d706e	47
bogdanm	82:6473597d706e	48	//! @name Module base addresses
bogdanm	82:6473597d706e	49	//@{
bogdanm	82:6473597d706e	50	#ifndef REGS_PDB_BASE
bogdanm	82:6473597d706e	51	#define HW_PDB_INSTANCE_COUNT (1U) //!< Number of instances of the PDB module.
bogdanm	82:6473597d706e	52	#define REGS_PDB_BASE (0x40036000U) //!< Base address for PDB0.
bogdanm	82:6473597d706e	53	#endif
bogdanm	82:6473597d706e	54	//@}
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	57	// HW_PDB_SC - Status and Control register
bogdanm	82:6473597d706e	58	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	59
bogdanm	82:6473597d706e	60	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	61	/*!
bogdanm	82:6473597d706e	62	* @brief HW_PDB_SC - Status and Control register (RW)
bogdanm	82:6473597d706e	63	*
bogdanm	82:6473597d706e	64	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	65	*/
bogdanm	82:6473597d706e	66	typedef union _hw_pdb_sc
bogdanm	82:6473597d706e	67	{
bogdanm	82:6473597d706e	68	uint32_t U;
bogdanm	82:6473597d706e	69	struct _hw_pdb_sc_bitfields
bogdanm	82:6473597d706e	70	{
bogdanm	82:6473597d706e	71	uint32_t LDOK : 1; //!< [0] Load OK
bogdanm	82:6473597d706e	72	uint32_t CONT : 1; //!< [1] Continuous Mode Enable
bogdanm	82:6473597d706e	73	uint32_t MULT : 2; //!< [3:2] Multiplication Factor Select for
bogdanm	82:6473597d706e	74	//! Prescaler
bogdanm	82:6473597d706e	75	uint32_t RESERVED0 : 1; //!< [4]
bogdanm	82:6473597d706e	76	uint32_t PDBIE : 1; //!< [5] PDB Interrupt Enable
bogdanm	82:6473597d706e	77	uint32_t PDBIF : 1; //!< [6] PDB Interrupt Flag
bogdanm	82:6473597d706e	78	uint32_t PDBEN : 1; //!< [7] PDB Enable
bogdanm	82:6473597d706e	79	uint32_t TRGSEL : 4; //!< [11:8] Trigger Input Source Select
bogdanm	82:6473597d706e	80	uint32_t PRESCALER : 3; //!< [14:12] Prescaler Divider Select
bogdanm	82:6473597d706e	81	uint32_t DMAEN : 1; //!< [15] DMA Enable
bogdanm	82:6473597d706e	82	uint32_t SWTRIG : 1; //!< [16] Software Trigger
bogdanm	82:6473597d706e	83	uint32_t PDBEIE : 1; //!< [17] PDB Sequence Error Interrupt Enable
bogdanm	82:6473597d706e	84	uint32_t LDMOD : 2; //!< [19:18] Load Mode Select
bogdanm	82:6473597d706e	85	uint32_t RESERVED1 : 12; //!< [31:20]
bogdanm	82:6473597d706e	86	} B;
bogdanm	82:6473597d706e	87	} hw_pdb_sc_t;
bogdanm	82:6473597d706e	88	#endif
bogdanm	82:6473597d706e	89
bogdanm	82:6473597d706e	90	/*!
bogdanm	82:6473597d706e	91	* @name Constants and macros for entire PDB_SC register
bogdanm	82:6473597d706e	92	*/
bogdanm	82:6473597d706e	93	//@{
bogdanm	82:6473597d706e	94	#define HW_PDB_SC_ADDR (REGS_PDB_BASE + 0x0U)
bogdanm	82:6473597d706e	95
bogdanm	82:6473597d706e	96	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	97	#define HW_PDB_SC ((__IO hw_pdb_sc_t ) HW_PDB_SC_ADDR)
bogdanm	82:6473597d706e	98	#define HW_PDB_SC_RD() (HW_PDB_SC.U)
bogdanm	82:6473597d706e	99	#define HW_PDB_SC_WR(v) (HW_PDB_SC.U = (v))
bogdanm	82:6473597d706e	100	#define HW_PDB_SC_SET(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() \| (v)))
bogdanm	82:6473597d706e	101	#define HW_PDB_SC_CLR(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() & ~(v)))
bogdanm	82:6473597d706e	102	#define HW_PDB_SC_TOG(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() ^ (v)))
bogdanm	82:6473597d706e	103	#endif
bogdanm	82:6473597d706e	104	//@}
bogdanm	82:6473597d706e	105
bogdanm	82:6473597d706e	106	/*
bogdanm	82:6473597d706e	107	* Constants & macros for individual PDB_SC bitfields
bogdanm	82:6473597d706e	108	*/
bogdanm	82:6473597d706e	109
bogdanm	82:6473597d706e	110	/*!
bogdanm	82:6473597d706e	111	* @name Register PDB_SC, field LDOK[0] (RW)
bogdanm	82:6473597d706e	112	*
bogdanm	82:6473597d706e	113	* Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
bogdanm	82:6473597d706e	114	* DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
bogdanm	82:6473597d706e	115	* CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
bogdanm	82:6473597d706e	116	* written to the LDOK field, the values in the buffers of above registers are
bogdanm	82:6473597d706e	117	* not effective and the buffers cannot be written until the values in buffers are
bogdanm	82:6473597d706e	118	* loaded into their internal registers. LDOK can be written only when PDBEN is
bogdanm	82:6473597d706e	119	* set or it can be written at the same time with PDBEN being written to 1. It is
bogdanm	82:6473597d706e	120	* automatically cleared when the values in buffers are loaded into the internal
bogdanm	82:6473597d706e	121	* registers or the PDBEN is cleared. Writing 0 to it has no effect.
bogdanm	82:6473597d706e	122	*/
bogdanm	82:6473597d706e	123	//@{
bogdanm	82:6473597d706e	124	#define BP_PDB_SC_LDOK (0U) //!< Bit position for PDB_SC_LDOK.
bogdanm	82:6473597d706e	125	#define BM_PDB_SC_LDOK (0x00000001U) //!< Bit mask for PDB_SC_LDOK.
bogdanm	82:6473597d706e	126	#define BS_PDB_SC_LDOK (1U) //!< Bit field size in bits for PDB_SC_LDOK.
bogdanm	82:6473597d706e	127
bogdanm	82:6473597d706e	128	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	129	//! @brief Read current value of the PDB_SC_LDOK field.
bogdanm	82:6473597d706e	130	#define BR_PDB_SC_LDOK (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK))
bogdanm	82:6473597d706e	131	#endif
bogdanm	82:6473597d706e	132
bogdanm	82:6473597d706e	133	//! @brief Format value for bitfield PDB_SC_LDOK.
bogdanm	82:6473597d706e	134	#define BF_PDB_SC_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDOK), uint32_t) & BM_PDB_SC_LDOK)
bogdanm	82:6473597d706e	135
bogdanm	82:6473597d706e	136	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	137	//! @brief Set the LDOK field to a new value.
bogdanm	82:6473597d706e	138	#define BW_PDB_SC_LDOK(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK) = (v))
bogdanm	82:6473597d706e	139	#endif
bogdanm	82:6473597d706e	140	//@}
bogdanm	82:6473597d706e	141
bogdanm	82:6473597d706e	142	/*!
bogdanm	82:6473597d706e	143	* @name Register PDB_SC, field CONT[1] (RW)
bogdanm	82:6473597d706e	144	*
bogdanm	82:6473597d706e	145	* Enables the PDB operation in Continuous mode.
bogdanm	82:6473597d706e	146	*
bogdanm	82:6473597d706e	147	* Values:
bogdanm	82:6473597d706e	148	* - 0 - PDB operation in One-Shot mode
bogdanm	82:6473597d706e	149	* - 1 - PDB operation in Continuous mode
bogdanm	82:6473597d706e	150	*/
bogdanm	82:6473597d706e	151	//@{
bogdanm	82:6473597d706e	152	#define BP_PDB_SC_CONT (1U) //!< Bit position for PDB_SC_CONT.
bogdanm	82:6473597d706e	153	#define BM_PDB_SC_CONT (0x00000002U) //!< Bit mask for PDB_SC_CONT.
bogdanm	82:6473597d706e	154	#define BS_PDB_SC_CONT (1U) //!< Bit field size in bits for PDB_SC_CONT.
bogdanm	82:6473597d706e	155
bogdanm	82:6473597d706e	156	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	157	//! @brief Read current value of the PDB_SC_CONT field.
bogdanm	82:6473597d706e	158	#define BR_PDB_SC_CONT (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT))
bogdanm	82:6473597d706e	159	#endif
bogdanm	82:6473597d706e	160
bogdanm	82:6473597d706e	161	//! @brief Format value for bitfield PDB_SC_CONT.
bogdanm	82:6473597d706e	162	#define BF_PDB_SC_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_CONT), uint32_t) & BM_PDB_SC_CONT)
bogdanm	82:6473597d706e	163
bogdanm	82:6473597d706e	164	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	165	//! @brief Set the CONT field to a new value.
bogdanm	82:6473597d706e	166	#define BW_PDB_SC_CONT(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT) = (v))
bogdanm	82:6473597d706e	167	#endif
bogdanm	82:6473597d706e	168	//@}
bogdanm	82:6473597d706e	169
bogdanm	82:6473597d706e	170	/*!
bogdanm	82:6473597d706e	171	* @name Register PDB_SC, field MULT[3:2] (RW)
bogdanm	82:6473597d706e	172	*
bogdanm	82:6473597d706e	173	* Selects the multiplication factor of the prescaler divider for the counter
bogdanm	82:6473597d706e	174	* clock.
bogdanm	82:6473597d706e	175	*
bogdanm	82:6473597d706e	176	* Values:
bogdanm	82:6473597d706e	177	* - 00 - Multiplication factor is 1.
bogdanm	82:6473597d706e	178	* - 01 - Multiplication factor is 10.
bogdanm	82:6473597d706e	179	* - 10 - Multiplication factor is 20.
bogdanm	82:6473597d706e	180	* - 11 - Multiplication factor is 40.
bogdanm	82:6473597d706e	181	*/
bogdanm	82:6473597d706e	182	//@{
bogdanm	82:6473597d706e	183	#define BP_PDB_SC_MULT (2U) //!< Bit position for PDB_SC_MULT.
bogdanm	82:6473597d706e	184	#define BM_PDB_SC_MULT (0x0000000CU) //!< Bit mask for PDB_SC_MULT.
bogdanm	82:6473597d706e	185	#define BS_PDB_SC_MULT (2U) //!< Bit field size in bits for PDB_SC_MULT.
bogdanm	82:6473597d706e	186
bogdanm	82:6473597d706e	187	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	188	//! @brief Read current value of the PDB_SC_MULT field.
bogdanm	82:6473597d706e	189	#define BR_PDB_SC_MULT (HW_PDB_SC.B.MULT)
bogdanm	82:6473597d706e	190	#endif
bogdanm	82:6473597d706e	191
bogdanm	82:6473597d706e	192	//! @brief Format value for bitfield PDB_SC_MULT.
bogdanm	82:6473597d706e	193	#define BF_PDB_SC_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_MULT), uint32_t) & BM_PDB_SC_MULT)
bogdanm	82:6473597d706e	194
bogdanm	82:6473597d706e	195	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	196	//! @brief Set the MULT field to a new value.
bogdanm	82:6473597d706e	197	#define BW_PDB_SC_MULT(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_MULT) \| BF_PDB_SC_MULT(v)))
bogdanm	82:6473597d706e	198	#endif
bogdanm	82:6473597d706e	199	//@}
bogdanm	82:6473597d706e	200
bogdanm	82:6473597d706e	201	/*!
bogdanm	82:6473597d706e	202	* @name Register PDB_SC, field PDBIE[5] (RW)
bogdanm	82:6473597d706e	203	*
bogdanm	82:6473597d706e	204	* Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
bogdanm	82:6473597d706e	205	* generates a PDB interrupt.
bogdanm	82:6473597d706e	206	*
bogdanm	82:6473597d706e	207	* Values:
bogdanm	82:6473597d706e	208	* - 0 - PDB interrupt disabled.
bogdanm	82:6473597d706e	209	* - 1 - PDB interrupt enabled.
bogdanm	82:6473597d706e	210	*/
bogdanm	82:6473597d706e	211	//@{
bogdanm	82:6473597d706e	212	#define BP_PDB_SC_PDBIE (5U) //!< Bit position for PDB_SC_PDBIE.
bogdanm	82:6473597d706e	213	#define BM_PDB_SC_PDBIE (0x00000020U) //!< Bit mask for PDB_SC_PDBIE.
bogdanm	82:6473597d706e	214	#define BS_PDB_SC_PDBIE (1U) //!< Bit field size in bits for PDB_SC_PDBIE.
bogdanm	82:6473597d706e	215
bogdanm	82:6473597d706e	216	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	217	//! @brief Read current value of the PDB_SC_PDBIE field.
bogdanm	82:6473597d706e	218	#define BR_PDB_SC_PDBIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE))
bogdanm	82:6473597d706e	219	#endif
bogdanm	82:6473597d706e	220
bogdanm	82:6473597d706e	221	//! @brief Format value for bitfield PDB_SC_PDBIE.
bogdanm	82:6473597d706e	222	#define BF_PDB_SC_PDBIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIE), uint32_t) & BM_PDB_SC_PDBIE)
bogdanm	82:6473597d706e	223
bogdanm	82:6473597d706e	224	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	225	//! @brief Set the PDBIE field to a new value.
bogdanm	82:6473597d706e	226	#define BW_PDB_SC_PDBIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE) = (v))
bogdanm	82:6473597d706e	227	#endif
bogdanm	82:6473597d706e	228	//@}
bogdanm	82:6473597d706e	229
bogdanm	82:6473597d706e	230	/*!
bogdanm	82:6473597d706e	231	* @name Register PDB_SC, field PDBIF[6] (RW)
bogdanm	82:6473597d706e	232	*
bogdanm	82:6473597d706e	233	* This field is set when the counter value is equal to the IDLY register.
bogdanm	82:6473597d706e	234	* Writing zero clears this field.
bogdanm	82:6473597d706e	235	*/
bogdanm	82:6473597d706e	236	//@{
bogdanm	82:6473597d706e	237	#define BP_PDB_SC_PDBIF (6U) //!< Bit position for PDB_SC_PDBIF.
bogdanm	82:6473597d706e	238	#define BM_PDB_SC_PDBIF (0x00000040U) //!< Bit mask for PDB_SC_PDBIF.
bogdanm	82:6473597d706e	239	#define BS_PDB_SC_PDBIF (1U) //!< Bit field size in bits for PDB_SC_PDBIF.
bogdanm	82:6473597d706e	240
bogdanm	82:6473597d706e	241	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	242	//! @brief Read current value of the PDB_SC_PDBIF field.
bogdanm	82:6473597d706e	243	#define BR_PDB_SC_PDBIF (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF))
bogdanm	82:6473597d706e	244	#endif
bogdanm	82:6473597d706e	245
bogdanm	82:6473597d706e	246	//! @brief Format value for bitfield PDB_SC_PDBIF.
bogdanm	82:6473597d706e	247	#define BF_PDB_SC_PDBIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIF), uint32_t) & BM_PDB_SC_PDBIF)
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	250	//! @brief Set the PDBIF field to a new value.
bogdanm	82:6473597d706e	251	#define BW_PDB_SC_PDBIF(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF) = (v))
bogdanm	82:6473597d706e	252	#endif
bogdanm	82:6473597d706e	253	//@}
bogdanm	82:6473597d706e	254
bogdanm	82:6473597d706e	255	/*!
bogdanm	82:6473597d706e	256	* @name Register PDB_SC, field PDBEN[7] (RW)
bogdanm	82:6473597d706e	257	*
bogdanm	82:6473597d706e	258	* Values:
bogdanm	82:6473597d706e	259	* - 0 - PDB disabled. Counter is off.
bogdanm	82:6473597d706e	260	* - 1 - PDB enabled.
bogdanm	82:6473597d706e	261	*/
bogdanm	82:6473597d706e	262	//@{
bogdanm	82:6473597d706e	263	#define BP_PDB_SC_PDBEN (7U) //!< Bit position for PDB_SC_PDBEN.
bogdanm	82:6473597d706e	264	#define BM_PDB_SC_PDBEN (0x00000080U) //!< Bit mask for PDB_SC_PDBEN.
bogdanm	82:6473597d706e	265	#define BS_PDB_SC_PDBEN (1U) //!< Bit field size in bits for PDB_SC_PDBEN.
bogdanm	82:6473597d706e	266
bogdanm	82:6473597d706e	267	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	268	//! @brief Read current value of the PDB_SC_PDBEN field.
bogdanm	82:6473597d706e	269	#define BR_PDB_SC_PDBEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN))
bogdanm	82:6473597d706e	270	#endif
bogdanm	82:6473597d706e	271
bogdanm	82:6473597d706e	272	//! @brief Format value for bitfield PDB_SC_PDBEN.
bogdanm	82:6473597d706e	273	#define BF_PDB_SC_PDBEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEN), uint32_t) & BM_PDB_SC_PDBEN)
bogdanm	82:6473597d706e	274
bogdanm	82:6473597d706e	275	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	276	//! @brief Set the PDBEN field to a new value.
bogdanm	82:6473597d706e	277	#define BW_PDB_SC_PDBEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN) = (v))
bogdanm	82:6473597d706e	278	#endif
bogdanm	82:6473597d706e	279	//@}
bogdanm	82:6473597d706e	280
bogdanm	82:6473597d706e	281	/*!
bogdanm	82:6473597d706e	282	* @name Register PDB_SC, field TRGSEL[11:8] (RW)
bogdanm	82:6473597d706e	283	*
bogdanm	82:6473597d706e	284	* Selects the trigger input source for the PDB. The trigger input source can be
bogdanm	82:6473597d706e	285	* internal or external (EXTRG pin), or the software trigger. Refer to chip
bogdanm	82:6473597d706e	286	* configuration details for the actual PDB input trigger connections.
bogdanm	82:6473597d706e	287	*
bogdanm	82:6473597d706e	288	* Values:
bogdanm	82:6473597d706e	289	* - 0000 - Trigger-In 0 is selected.
bogdanm	82:6473597d706e	290	* - 0001 - Trigger-In 1 is selected.
bogdanm	82:6473597d706e	291	* - 0010 - Trigger-In 2 is selected.
bogdanm	82:6473597d706e	292	* - 0011 - Trigger-In 3 is selected.
bogdanm	82:6473597d706e	293	* - 0100 - Trigger-In 4 is selected.
bogdanm	82:6473597d706e	294	* - 0101 - Trigger-In 5 is selected.
bogdanm	82:6473597d706e	295	* - 0110 - Trigger-In 6 is selected.
bogdanm	82:6473597d706e	296	* - 0111 - Trigger-In 7 is selected.
bogdanm	82:6473597d706e	297	* - 1000 - Trigger-In 8 is selected.
bogdanm	82:6473597d706e	298	* - 1001 - Trigger-In 9 is selected.
bogdanm	82:6473597d706e	299	* - 1010 - Trigger-In 10 is selected.
bogdanm	82:6473597d706e	300	* - 1011 - Trigger-In 11 is selected.
bogdanm	82:6473597d706e	301	* - 1100 - Trigger-In 12 is selected.
bogdanm	82:6473597d706e	302	* - 1101 - Trigger-In 13 is selected.
bogdanm	82:6473597d706e	303	* - 1110 - Trigger-In 14 is selected.
bogdanm	82:6473597d706e	304	* - 1111 - Software trigger is selected.
bogdanm	82:6473597d706e	305	*/
bogdanm	82:6473597d706e	306	//@{
bogdanm	82:6473597d706e	307	#define BP_PDB_SC_TRGSEL (8U) //!< Bit position for PDB_SC_TRGSEL.
bogdanm	82:6473597d706e	308	#define BM_PDB_SC_TRGSEL (0x00000F00U) //!< Bit mask for PDB_SC_TRGSEL.
bogdanm	82:6473597d706e	309	#define BS_PDB_SC_TRGSEL (4U) //!< Bit field size in bits for PDB_SC_TRGSEL.
bogdanm	82:6473597d706e	310
bogdanm	82:6473597d706e	311	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	312	//! @brief Read current value of the PDB_SC_TRGSEL field.
bogdanm	82:6473597d706e	313	#define BR_PDB_SC_TRGSEL (HW_PDB_SC.B.TRGSEL)
bogdanm	82:6473597d706e	314	#endif
bogdanm	82:6473597d706e	315
bogdanm	82:6473597d706e	316	//! @brief Format value for bitfield PDB_SC_TRGSEL.
bogdanm	82:6473597d706e	317	#define BF_PDB_SC_TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_TRGSEL), uint32_t) & BM_PDB_SC_TRGSEL)
bogdanm	82:6473597d706e	318
bogdanm	82:6473597d706e	319	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	320	//! @brief Set the TRGSEL field to a new value.
bogdanm	82:6473597d706e	321	#define BW_PDB_SC_TRGSEL(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_TRGSEL) \| BF_PDB_SC_TRGSEL(v)))
bogdanm	82:6473597d706e	322	#endif
bogdanm	82:6473597d706e	323	//@}
bogdanm	82:6473597d706e	324
bogdanm	82:6473597d706e	325	/*!
bogdanm	82:6473597d706e	326	* @name Register PDB_SC, field PRESCALER[14:12] (RW)
bogdanm	82:6473597d706e	327	*
bogdanm	82:6473597d706e	328	* Values:
bogdanm	82:6473597d706e	329	* - 000 - Counting uses the peripheral clock divided by multiplication factor
bogdanm	82:6473597d706e	330	* selected by MULT.
bogdanm	82:6473597d706e	331	* - 001 - Counting uses the peripheral clock divided by twice of the
bogdanm	82:6473597d706e	332	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	333	* - 010 - Counting uses the peripheral clock divided by four times of the
bogdanm	82:6473597d706e	334	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	335	* - 011 - Counting uses the peripheral clock divided by eight times of the
bogdanm	82:6473597d706e	336	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	337	* - 100 - Counting uses the peripheral clock divided by 16 times of the
bogdanm	82:6473597d706e	338	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	339	* - 101 - Counting uses the peripheral clock divided by 32 times of the
bogdanm	82:6473597d706e	340	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	341	* - 110 - Counting uses the peripheral clock divided by 64 times of the
bogdanm	82:6473597d706e	342	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	343	* - 111 - Counting uses the peripheral clock divided by 128 times of the
bogdanm	82:6473597d706e	344	* multiplication factor selected by MULT.
bogdanm	82:6473597d706e	345	*/
bogdanm	82:6473597d706e	346	//@{
bogdanm	82:6473597d706e	347	#define BP_PDB_SC_PRESCALER (12U) //!< Bit position for PDB_SC_PRESCALER.
bogdanm	82:6473597d706e	348	#define BM_PDB_SC_PRESCALER (0x00007000U) //!< Bit mask for PDB_SC_PRESCALER.
bogdanm	82:6473597d706e	349	#define BS_PDB_SC_PRESCALER (3U) //!< Bit field size in bits for PDB_SC_PRESCALER.
bogdanm	82:6473597d706e	350
bogdanm	82:6473597d706e	351	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	352	//! @brief Read current value of the PDB_SC_PRESCALER field.
bogdanm	82:6473597d706e	353	#define BR_PDB_SC_PRESCALER (HW_PDB_SC.B.PRESCALER)
bogdanm	82:6473597d706e	354	#endif
bogdanm	82:6473597d706e	355
bogdanm	82:6473597d706e	356	//! @brief Format value for bitfield PDB_SC_PRESCALER.
bogdanm	82:6473597d706e	357	#define BF_PDB_SC_PRESCALER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PRESCALER), uint32_t) & BM_PDB_SC_PRESCALER)
bogdanm	82:6473597d706e	358
bogdanm	82:6473597d706e	359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	360	//! @brief Set the PRESCALER field to a new value.
bogdanm	82:6473597d706e	361	#define BW_PDB_SC_PRESCALER(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_PRESCALER) \| BF_PDB_SC_PRESCALER(v)))
bogdanm	82:6473597d706e	362	#endif
bogdanm	82:6473597d706e	363	//@}
bogdanm	82:6473597d706e	364
bogdanm	82:6473597d706e	365	/*!
bogdanm	82:6473597d706e	366	* @name Register PDB_SC, field DMAEN[15] (RW)
bogdanm	82:6473597d706e	367	*
bogdanm	82:6473597d706e	368	* When DMA is enabled, the PDBIF flag generates a DMA request instead of an
bogdanm	82:6473597d706e	369	* interrupt.
bogdanm	82:6473597d706e	370	*
bogdanm	82:6473597d706e	371	* Values:
bogdanm	82:6473597d706e	372	* - 0 - DMA disabled.
bogdanm	82:6473597d706e	373	* - 1 - DMA enabled.
bogdanm	82:6473597d706e	374	*/
bogdanm	82:6473597d706e	375	//@{
bogdanm	82:6473597d706e	376	#define BP_PDB_SC_DMAEN (15U) //!< Bit position for PDB_SC_DMAEN.
bogdanm	82:6473597d706e	377	#define BM_PDB_SC_DMAEN (0x00008000U) //!< Bit mask for PDB_SC_DMAEN.
bogdanm	82:6473597d706e	378	#define BS_PDB_SC_DMAEN (1U) //!< Bit field size in bits for PDB_SC_DMAEN.
bogdanm	82:6473597d706e	379
bogdanm	82:6473597d706e	380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	381	//! @brief Read current value of the PDB_SC_DMAEN field.
bogdanm	82:6473597d706e	382	#define BR_PDB_SC_DMAEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN))
bogdanm	82:6473597d706e	383	#endif
bogdanm	82:6473597d706e	384
bogdanm	82:6473597d706e	385	//! @brief Format value for bitfield PDB_SC_DMAEN.
bogdanm	82:6473597d706e	386	#define BF_PDB_SC_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_DMAEN), uint32_t) & BM_PDB_SC_DMAEN)
bogdanm	82:6473597d706e	387
bogdanm	82:6473597d706e	388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	389	//! @brief Set the DMAEN field to a new value.
bogdanm	82:6473597d706e	390	#define BW_PDB_SC_DMAEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN) = (v))
bogdanm	82:6473597d706e	391	#endif
bogdanm	82:6473597d706e	392	//@}
bogdanm	82:6473597d706e	393
bogdanm	82:6473597d706e	394	/*!
bogdanm	82:6473597d706e	395	* @name Register PDB_SC, field SWTRIG[16] (WORZ)
bogdanm	82:6473597d706e	396	*
bogdanm	82:6473597d706e	397	* When PDB is enabled and the software trigger is selected as the trigger input
bogdanm	82:6473597d706e	398	* source, writing 1 to this field resets and restarts the counter. Writing 0 to
bogdanm	82:6473597d706e	399	* this field has no effect. Reading this field results 0.
bogdanm	82:6473597d706e	400	*/
bogdanm	82:6473597d706e	401	//@{
bogdanm	82:6473597d706e	402	#define BP_PDB_SC_SWTRIG (16U) //!< Bit position for PDB_SC_SWTRIG.
bogdanm	82:6473597d706e	403	#define BM_PDB_SC_SWTRIG (0x00010000U) //!< Bit mask for PDB_SC_SWTRIG.
bogdanm	82:6473597d706e	404	#define BS_PDB_SC_SWTRIG (1U) //!< Bit field size in bits for PDB_SC_SWTRIG.
bogdanm	82:6473597d706e	405
bogdanm	82:6473597d706e	406	//! @brief Format value for bitfield PDB_SC_SWTRIG.
bogdanm	82:6473597d706e	407	#define BF_PDB_SC_SWTRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_SWTRIG), uint32_t) & BM_PDB_SC_SWTRIG)
bogdanm	82:6473597d706e	408
bogdanm	82:6473597d706e	409	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	410	//! @brief Set the SWTRIG field to a new value.
bogdanm	82:6473597d706e	411	#define BW_PDB_SC_SWTRIG(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_SWTRIG) = (v))
bogdanm	82:6473597d706e	412	#endif
bogdanm	82:6473597d706e	413	//@}
bogdanm	82:6473597d706e	414
bogdanm	82:6473597d706e	415	/*!
bogdanm	82:6473597d706e	416	* @name Register PDB_SC, field PDBEIE[17] (RW)
bogdanm	82:6473597d706e	417	*
bogdanm	82:6473597d706e	418	* Enables the PDB sequence error interrupt. When this field is set, any of the
bogdanm	82:6473597d706e	419	* PDB channel sequence error flags generates a PDB sequence error interrupt.
bogdanm	82:6473597d706e	420	*
bogdanm	82:6473597d706e	421	* Values:
bogdanm	82:6473597d706e	422	* - 0 - PDB sequence error interrupt disabled.
bogdanm	82:6473597d706e	423	* - 1 - PDB sequence error interrupt enabled.
bogdanm	82:6473597d706e	424	*/
bogdanm	82:6473597d706e	425	//@{
bogdanm	82:6473597d706e	426	#define BP_PDB_SC_PDBEIE (17U) //!< Bit position for PDB_SC_PDBEIE.
bogdanm	82:6473597d706e	427	#define BM_PDB_SC_PDBEIE (0x00020000U) //!< Bit mask for PDB_SC_PDBEIE.
bogdanm	82:6473597d706e	428	#define BS_PDB_SC_PDBEIE (1U) //!< Bit field size in bits for PDB_SC_PDBEIE.
bogdanm	82:6473597d706e	429
bogdanm	82:6473597d706e	430	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	431	//! @brief Read current value of the PDB_SC_PDBEIE field.
bogdanm	82:6473597d706e	432	#define BR_PDB_SC_PDBEIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE))
bogdanm	82:6473597d706e	433	#endif
bogdanm	82:6473597d706e	434
bogdanm	82:6473597d706e	435	//! @brief Format value for bitfield PDB_SC_PDBEIE.
bogdanm	82:6473597d706e	436	#define BF_PDB_SC_PDBEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEIE), uint32_t) & BM_PDB_SC_PDBEIE)
bogdanm	82:6473597d706e	437
bogdanm	82:6473597d706e	438	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	439	//! @brief Set the PDBEIE field to a new value.
bogdanm	82:6473597d706e	440	#define BW_PDB_SC_PDBEIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE) = (v))
bogdanm	82:6473597d706e	441	#endif
bogdanm	82:6473597d706e	442	//@}
bogdanm	82:6473597d706e	443
bogdanm	82:6473597d706e	444	/*!
bogdanm	82:6473597d706e	445	* @name Register PDB_SC, field LDMOD[19:18] (RW)
bogdanm	82:6473597d706e	446	*
bogdanm	82:6473597d706e	447	* Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
bogdanm	82:6473597d706e	448	* after 1 is written to LDOK.
bogdanm	82:6473597d706e	449	*
bogdanm	82:6473597d706e	450	* Values:
bogdanm	82:6473597d706e	451	* - 00 - The internal registers are loaded with the values from their buffers
bogdanm	82:6473597d706e	452	* immediately after 1 is written to LDOK.
bogdanm	82:6473597d706e	453	* - 01 - The internal registers are loaded with the values from their buffers
bogdanm	82:6473597d706e	454	* when the PDB counter reaches the MOD register value after 1 is written to
bogdanm	82:6473597d706e	455	* LDOK.
bogdanm	82:6473597d706e	456	* - 10 - The internal registers are loaded with the values from their buffers
bogdanm	82:6473597d706e	457	* when a trigger input event is detected after 1 is written to LDOK.
bogdanm	82:6473597d706e	458	* - 11 - The internal registers are loaded with the values from their buffers
bogdanm	82:6473597d706e	459	* when either the PDB counter reaches the MOD register value or a trigger
bogdanm	82:6473597d706e	460	* input event is detected, after 1 is written to LDOK.
bogdanm	82:6473597d706e	461	*/
bogdanm	82:6473597d706e	462	//@{
bogdanm	82:6473597d706e	463	#define BP_PDB_SC_LDMOD (18U) //!< Bit position for PDB_SC_LDMOD.
bogdanm	82:6473597d706e	464	#define BM_PDB_SC_LDMOD (0x000C0000U) //!< Bit mask for PDB_SC_LDMOD.
bogdanm	82:6473597d706e	465	#define BS_PDB_SC_LDMOD (2U) //!< Bit field size in bits for PDB_SC_LDMOD.
bogdanm	82:6473597d706e	466
bogdanm	82:6473597d706e	467	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	468	//! @brief Read current value of the PDB_SC_LDMOD field.
bogdanm	82:6473597d706e	469	#define BR_PDB_SC_LDMOD (HW_PDB_SC.B.LDMOD)
bogdanm	82:6473597d706e	470	#endif
bogdanm	82:6473597d706e	471
bogdanm	82:6473597d706e	472	//! @brief Format value for bitfield PDB_SC_LDMOD.
bogdanm	82:6473597d706e	473	#define BF_PDB_SC_LDMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDMOD), uint32_t) & BM_PDB_SC_LDMOD)
bogdanm	82:6473597d706e	474
bogdanm	82:6473597d706e	475	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	476	//! @brief Set the LDMOD field to a new value.
bogdanm	82:6473597d706e	477	#define BW_PDB_SC_LDMOD(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_LDMOD) \| BF_PDB_SC_LDMOD(v)))
bogdanm	82:6473597d706e	478	#endif
bogdanm	82:6473597d706e	479	//@}
bogdanm	82:6473597d706e	480
bogdanm	82:6473597d706e	481	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	482	// HW_PDB_MOD - Modulus register
bogdanm	82:6473597d706e	483	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	484
bogdanm	82:6473597d706e	485	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	486	/*!
bogdanm	82:6473597d706e	487	* @brief HW_PDB_MOD - Modulus register (RW)
bogdanm	82:6473597d706e	488	*
bogdanm	82:6473597d706e	489	* Reset value: 0x0000FFFFU
bogdanm	82:6473597d706e	490	*/
bogdanm	82:6473597d706e	491	typedef union _hw_pdb_mod
bogdanm	82:6473597d706e	492	{
bogdanm	82:6473597d706e	493	uint32_t U;
bogdanm	82:6473597d706e	494	struct _hw_pdb_mod_bitfields
bogdanm	82:6473597d706e	495	{
bogdanm	82:6473597d706e	496	uint32_t MOD : 16; //!< [15:0] PDB Modulus
bogdanm	82:6473597d706e	497	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	498	} B;
bogdanm	82:6473597d706e	499	} hw_pdb_mod_t;
bogdanm	82:6473597d706e	500	#endif
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	/*!
bogdanm	82:6473597d706e	503	* @name Constants and macros for entire PDB_MOD register
bogdanm	82:6473597d706e	504	*/
bogdanm	82:6473597d706e	505	//@{
bogdanm	82:6473597d706e	506	#define HW_PDB_MOD_ADDR (REGS_PDB_BASE + 0x4U)
bogdanm	82:6473597d706e	507
bogdanm	82:6473597d706e	508	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	509	#define HW_PDB_MOD ((__IO hw_pdb_mod_t ) HW_PDB_MOD_ADDR)
bogdanm	82:6473597d706e	510	#define HW_PDB_MOD_RD() (HW_PDB_MOD.U)
bogdanm	82:6473597d706e	511	#define HW_PDB_MOD_WR(v) (HW_PDB_MOD.U = (v))
bogdanm	82:6473597d706e	512	#define HW_PDB_MOD_SET(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() \| (v)))
bogdanm	82:6473597d706e	513	#define HW_PDB_MOD_CLR(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() & ~(v)))
bogdanm	82:6473597d706e	514	#define HW_PDB_MOD_TOG(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() ^ (v)))
bogdanm	82:6473597d706e	515	#endif
bogdanm	82:6473597d706e	516	//@}
bogdanm	82:6473597d706e	517
bogdanm	82:6473597d706e	518	/*
bogdanm	82:6473597d706e	519	* Constants & macros for individual PDB_MOD bitfields
bogdanm	82:6473597d706e	520	*/
bogdanm	82:6473597d706e	521
bogdanm	82:6473597d706e	522	/*!
bogdanm	82:6473597d706e	523	* @name Register PDB_MOD, field MOD[15:0] (RW)
bogdanm	82:6473597d706e	524	*
bogdanm	82:6473597d706e	525	* Specifies the period of the counter. When the counter reaches this value, it
bogdanm	82:6473597d706e	526	* will be reset back to zero. If the PDB is in Continuous mode, the count begins
bogdanm	82:6473597d706e	527	* anew. Reading this field returns the value of the internal register that is
bogdanm	82:6473597d706e	528	* effective for the current cycle of PDB.
bogdanm	82:6473597d706e	529	*/
bogdanm	82:6473597d706e	530	//@{
bogdanm	82:6473597d706e	531	#define BP_PDB_MOD_MOD (0U) //!< Bit position for PDB_MOD_MOD.
bogdanm	82:6473597d706e	532	#define BM_PDB_MOD_MOD (0x0000FFFFU) //!< Bit mask for PDB_MOD_MOD.
bogdanm	82:6473597d706e	533	#define BS_PDB_MOD_MOD (16U) //!< Bit field size in bits for PDB_MOD_MOD.
bogdanm	82:6473597d706e	534
bogdanm	82:6473597d706e	535	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	536	//! @brief Read current value of the PDB_MOD_MOD field.
bogdanm	82:6473597d706e	537	#define BR_PDB_MOD_MOD (HW_PDB_MOD.B.MOD)
bogdanm	82:6473597d706e	538	#endif
bogdanm	82:6473597d706e	539
bogdanm	82:6473597d706e	540	//! @brief Format value for bitfield PDB_MOD_MOD.
bogdanm	82:6473597d706e	541	#define BF_PDB_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_MOD_MOD), uint32_t) & BM_PDB_MOD_MOD)
bogdanm	82:6473597d706e	542
bogdanm	82:6473597d706e	543	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	544	//! @brief Set the MOD field to a new value.
bogdanm	82:6473597d706e	545	#define BW_PDB_MOD_MOD(v) (HW_PDB_MOD_WR((HW_PDB_MOD_RD() & ~BM_PDB_MOD_MOD) \| BF_PDB_MOD_MOD(v)))
bogdanm	82:6473597d706e	546	#endif
bogdanm	82:6473597d706e	547	//@}
bogdanm	82:6473597d706e	548
bogdanm	82:6473597d706e	549	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	550	// HW_PDB_CNT - Counter register
bogdanm	82:6473597d706e	551	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	552
bogdanm	82:6473597d706e	553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	554	/*!
bogdanm	82:6473597d706e	555	* @brief HW_PDB_CNT - Counter register (RO)
bogdanm	82:6473597d706e	556	*
bogdanm	82:6473597d706e	557	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	558	*/
bogdanm	82:6473597d706e	559	typedef union _hw_pdb_cnt
bogdanm	82:6473597d706e	560	{
bogdanm	82:6473597d706e	561	uint32_t U;
bogdanm	82:6473597d706e	562	struct _hw_pdb_cnt_bitfields
bogdanm	82:6473597d706e	563	{
bogdanm	82:6473597d706e	564	uint32_t CNT : 16; //!< [15:0] PDB Counter
bogdanm	82:6473597d706e	565	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	566	} B;
bogdanm	82:6473597d706e	567	} hw_pdb_cnt_t;
bogdanm	82:6473597d706e	568	#endif
bogdanm	82:6473597d706e	569
bogdanm	82:6473597d706e	570	/*!
bogdanm	82:6473597d706e	571	* @name Constants and macros for entire PDB_CNT register
bogdanm	82:6473597d706e	572	*/
bogdanm	82:6473597d706e	573	//@{
bogdanm	82:6473597d706e	574	#define HW_PDB_CNT_ADDR (REGS_PDB_BASE + 0x8U)
bogdanm	82:6473597d706e	575
bogdanm	82:6473597d706e	576	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	577	#define HW_PDB_CNT ((__I hw_pdb_cnt_t ) HW_PDB_CNT_ADDR)
bogdanm	82:6473597d706e	578	#define HW_PDB_CNT_RD() (HW_PDB_CNT.U)
bogdanm	82:6473597d706e	579	#endif
bogdanm	82:6473597d706e	580	//@}
bogdanm	82:6473597d706e	581
bogdanm	82:6473597d706e	582	/*
bogdanm	82:6473597d706e	583	* Constants & macros for individual PDB_CNT bitfields
bogdanm	82:6473597d706e	584	*/
bogdanm	82:6473597d706e	585
bogdanm	82:6473597d706e	586	/*!
bogdanm	82:6473597d706e	587	* @name Register PDB_CNT, field CNT[15:0] (RO)
bogdanm	82:6473597d706e	588	*
bogdanm	82:6473597d706e	589	* Contains the current value of the counter.
bogdanm	82:6473597d706e	590	*/
bogdanm	82:6473597d706e	591	//@{
bogdanm	82:6473597d706e	592	#define BP_PDB_CNT_CNT (0U) //!< Bit position for PDB_CNT_CNT.
bogdanm	82:6473597d706e	593	#define BM_PDB_CNT_CNT (0x0000FFFFU) //!< Bit mask for PDB_CNT_CNT.
bogdanm	82:6473597d706e	594	#define BS_PDB_CNT_CNT (16U) //!< Bit field size in bits for PDB_CNT_CNT.
bogdanm	82:6473597d706e	595
bogdanm	82:6473597d706e	596	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	597	//! @brief Read current value of the PDB_CNT_CNT field.
bogdanm	82:6473597d706e	598	#define BR_PDB_CNT_CNT (HW_PDB_CNT.B.CNT)
bogdanm	82:6473597d706e	599	#endif
bogdanm	82:6473597d706e	600	//@}
bogdanm	82:6473597d706e	601
bogdanm	82:6473597d706e	602	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	603	// HW_PDB_IDLY - Interrupt Delay register
bogdanm	82:6473597d706e	604	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	605
bogdanm	82:6473597d706e	606	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	607	/*!
bogdanm	82:6473597d706e	608	* @brief HW_PDB_IDLY - Interrupt Delay register (RW)
bogdanm	82:6473597d706e	609	*
bogdanm	82:6473597d706e	610	* Reset value: 0x0000FFFFU
bogdanm	82:6473597d706e	611	*/
bogdanm	82:6473597d706e	612	typedef union _hw_pdb_idly
bogdanm	82:6473597d706e	613	{
bogdanm	82:6473597d706e	614	uint32_t U;
bogdanm	82:6473597d706e	615	struct _hw_pdb_idly_bitfields
bogdanm	82:6473597d706e	616	{
bogdanm	82:6473597d706e	617	uint32_t IDLY : 16; //!< [15:0] PDB Interrupt Delay
bogdanm	82:6473597d706e	618	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	619	} B;
bogdanm	82:6473597d706e	620	} hw_pdb_idly_t;
bogdanm	82:6473597d706e	621	#endif
bogdanm	82:6473597d706e	622
bogdanm	82:6473597d706e	623	/*!
bogdanm	82:6473597d706e	624	* @name Constants and macros for entire PDB_IDLY register
bogdanm	82:6473597d706e	625	*/
bogdanm	82:6473597d706e	626	//@{
bogdanm	82:6473597d706e	627	#define HW_PDB_IDLY_ADDR (REGS_PDB_BASE + 0xCU)
bogdanm	82:6473597d706e	628
bogdanm	82:6473597d706e	629	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	630	#define HW_PDB_IDLY ((__IO hw_pdb_idly_t ) HW_PDB_IDLY_ADDR)
bogdanm	82:6473597d706e	631	#define HW_PDB_IDLY_RD() (HW_PDB_IDLY.U)
bogdanm	82:6473597d706e	632	#define HW_PDB_IDLY_WR(v) (HW_PDB_IDLY.U = (v))
bogdanm	82:6473597d706e	633	#define HW_PDB_IDLY_SET(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() \| (v)))
bogdanm	82:6473597d706e	634	#define HW_PDB_IDLY_CLR(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() & ~(v)))
bogdanm	82:6473597d706e	635	#define HW_PDB_IDLY_TOG(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() ^ (v)))
bogdanm	82:6473597d706e	636	#endif
bogdanm	82:6473597d706e	637	//@}
bogdanm	82:6473597d706e	638
bogdanm	82:6473597d706e	639	/*
bogdanm	82:6473597d706e	640	* Constants & macros for individual PDB_IDLY bitfields
bogdanm	82:6473597d706e	641	*/
bogdanm	82:6473597d706e	642
bogdanm	82:6473597d706e	643	/*!
bogdanm	82:6473597d706e	644	* @name Register PDB_IDLY, field IDLY[15:0] (RW)
bogdanm	82:6473597d706e	645	*
bogdanm	82:6473597d706e	646	* Specifies the delay value to schedule the PDB interrupt. It can be used to
bogdanm	82:6473597d706e	647	* schedule an independent interrupt at some point in the PDB cycle. If enabled, a
bogdanm	82:6473597d706e	648	* PDB interrupt is generated, when the counter is equal to the IDLY. Reading
bogdanm	82:6473597d706e	649	* this field returns the value of internal register that is effective for the
bogdanm	82:6473597d706e	650	* current cycle of the PDB.
bogdanm	82:6473597d706e	651	*/
bogdanm	82:6473597d706e	652	//@{
bogdanm	82:6473597d706e	653	#define BP_PDB_IDLY_IDLY (0U) //!< Bit position for PDB_IDLY_IDLY.
bogdanm	82:6473597d706e	654	#define BM_PDB_IDLY_IDLY (0x0000FFFFU) //!< Bit mask for PDB_IDLY_IDLY.
bogdanm	82:6473597d706e	655	#define BS_PDB_IDLY_IDLY (16U) //!< Bit field size in bits for PDB_IDLY_IDLY.
bogdanm	82:6473597d706e	656
bogdanm	82:6473597d706e	657	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	658	//! @brief Read current value of the PDB_IDLY_IDLY field.
bogdanm	82:6473597d706e	659	#define BR_PDB_IDLY_IDLY (HW_PDB_IDLY.B.IDLY)
bogdanm	82:6473597d706e	660	#endif
bogdanm	82:6473597d706e	661
bogdanm	82:6473597d706e	662	//! @brief Format value for bitfield PDB_IDLY_IDLY.
bogdanm	82:6473597d706e	663	#define BF_PDB_IDLY_IDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_IDLY_IDLY), uint32_t) & BM_PDB_IDLY_IDLY)
bogdanm	82:6473597d706e	664
bogdanm	82:6473597d706e	665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	666	//! @brief Set the IDLY field to a new value.
bogdanm	82:6473597d706e	667	#define BW_PDB_IDLY_IDLY(v) (HW_PDB_IDLY_WR((HW_PDB_IDLY_RD() & ~BM_PDB_IDLY_IDLY) \| BF_PDB_IDLY_IDLY(v)))
bogdanm	82:6473597d706e	668	#endif
bogdanm	82:6473597d706e	669	//@}
bogdanm	82:6473597d706e	670
bogdanm	82:6473597d706e	671	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	672	// HW_PDB_CHnC1 - Channel n Control register 1
bogdanm	82:6473597d706e	673	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	674
bogdanm	82:6473597d706e	675	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	676	/*!
bogdanm	82:6473597d706e	677	* @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
bogdanm	82:6473597d706e	678	*
bogdanm	82:6473597d706e	679	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	680	*
bogdanm	82:6473597d706e	681	* Each PDB channel has one control register, CHnC1. The bits in this register
bogdanm	82:6473597d706e	682	* control the functionality of each PDB channel operation.
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684	typedef union _hw_pdb_chnc1
bogdanm	82:6473597d706e	685	{
bogdanm	82:6473597d706e	686	uint32_t U;
bogdanm	82:6473597d706e	687	struct _hw_pdb_chnc1_bitfields
bogdanm	82:6473597d706e	688	{
bogdanm	82:6473597d706e	689	uint32_t EN : 8; //!< [7:0] PDB Channel Pre-Trigger Enable
bogdanm	82:6473597d706e	690	uint32_t TOS : 8; //!< [15:8] PDB Channel Pre-Trigger Output Select
bogdanm	82:6473597d706e	691	uint32_t BB : 8; //!< [23:16] PDB Channel Pre-Trigger Back-to-Back
bogdanm	82:6473597d706e	692	//! Operation Enable
bogdanm	82:6473597d706e	693	uint32_t RESERVED0 : 8; //!< [31:24]
bogdanm	82:6473597d706e	694	} B;
bogdanm	82:6473597d706e	695	} hw_pdb_chnc1_t;
bogdanm	82:6473597d706e	696	#endif
bogdanm	82:6473597d706e	697
bogdanm	82:6473597d706e	698	/*!
bogdanm	82:6473597d706e	699	* @name Constants and macros for entire PDB_CHnC1 register
bogdanm	82:6473597d706e	700	*/
bogdanm	82:6473597d706e	701	//@{
bogdanm	82:6473597d706e	702	#define HW_PDB_CHnC1_COUNT (2U)
bogdanm	82:6473597d706e	703
bogdanm	82:6473597d706e	704	#define HW_PDB_CHnC1_ADDR(n) (REGS_PDB_BASE + 0x10U + (0x28U * n))
bogdanm	82:6473597d706e	705
bogdanm	82:6473597d706e	706	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	707	#define HW_PDB_CHnC1(n) ((__IO hw_pdb_chnc1_t ) HW_PDB_CHnC1_ADDR(n))
bogdanm	82:6473597d706e	708	#define HW_PDB_CHnC1_RD(n) (HW_PDB_CHnC1(n).U)
bogdanm	82:6473597d706e	709	#define HW_PDB_CHnC1_WR(n, v) (HW_PDB_CHnC1(n).U = (v))
bogdanm	82:6473597d706e	710	#define HW_PDB_CHnC1_SET(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) \| (v)))
bogdanm	82:6473597d706e	711	#define HW_PDB_CHnC1_CLR(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) & ~(v)))
bogdanm	82:6473597d706e	712	#define HW_PDB_CHnC1_TOG(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) ^ (v)))
bogdanm	82:6473597d706e	713	#endif
bogdanm	82:6473597d706e	714	//@}
bogdanm	82:6473597d706e	715
bogdanm	82:6473597d706e	716	/*
bogdanm	82:6473597d706e	717	* Constants & macros for individual PDB_CHnC1 bitfields
bogdanm	82:6473597d706e	718	*/
bogdanm	82:6473597d706e	719
bogdanm	82:6473597d706e	720	/*!
bogdanm	82:6473597d706e	721	* @name Register PDB_CHnC1, field EN[7:0] (RW)
bogdanm	82:6473597d706e	722	*
bogdanm	82:6473597d706e	723	* These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
bogdanm	82:6473597d706e	724	* bits are implemented in this MCU.
bogdanm	82:6473597d706e	725	*
bogdanm	82:6473597d706e	726	* Values:
bogdanm	82:6473597d706e	727	* - 0 - PDB channel's corresponding pre-trigger disabled.
bogdanm	82:6473597d706e	728	* - 1 - PDB channel's corresponding pre-trigger enabled.
bogdanm	82:6473597d706e	729	*/
bogdanm	82:6473597d706e	730	//@{
bogdanm	82:6473597d706e	731	#define BP_PDB_CHnC1_EN (0U) //!< Bit position for PDB_CHnC1_EN.
bogdanm	82:6473597d706e	732	#define BM_PDB_CHnC1_EN (0x000000FFU) //!< Bit mask for PDB_CHnC1_EN.
bogdanm	82:6473597d706e	733	#define BS_PDB_CHnC1_EN (8U) //!< Bit field size in bits for PDB_CHnC1_EN.
bogdanm	82:6473597d706e	734
bogdanm	82:6473597d706e	735	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	736	//! @brief Read current value of the PDB_CHnC1_EN field.
bogdanm	82:6473597d706e	737	#define BR_PDB_CHnC1_EN(n) (HW_PDB_CHnC1(n).B.EN)
bogdanm	82:6473597d706e	738	#endif
bogdanm	82:6473597d706e	739
bogdanm	82:6473597d706e	740	//! @brief Format value for bitfield PDB_CHnC1_EN.
bogdanm	82:6473597d706e	741	#define BF_PDB_CHnC1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_EN), uint32_t) & BM_PDB_CHnC1_EN)
bogdanm	82:6473597d706e	742
bogdanm	82:6473597d706e	743	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	744	//! @brief Set the EN field to a new value.
bogdanm	82:6473597d706e	745	#define BW_PDB_CHnC1_EN(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_EN) \| BF_PDB_CHnC1_EN(v)))
bogdanm	82:6473597d706e	746	#endif
bogdanm	82:6473597d706e	747	//@}
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	/*!
bogdanm	82:6473597d706e	750	* @name Register PDB_CHnC1, field TOS[15:8] (RW)
bogdanm	82:6473597d706e	751	*
bogdanm	82:6473597d706e	752	* Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
bogdanm	82:6473597d706e	753	* implemented in this MCU.
bogdanm	82:6473597d706e	754	*
bogdanm	82:6473597d706e	755	* Values:
bogdanm	82:6473597d706e	756	* - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
bogdanm	82:6473597d706e	757	* pre-trigger asserts one peripheral clock cycle after a rising edge is detected
bogdanm	82:6473597d706e	758	* on selected trigger input source or software trigger is selected and SWTRIG
bogdanm	82:6473597d706e	759	* is written with 1.
bogdanm	82:6473597d706e	760	* - 1 - PDB channel's corresponding pre-trigger asserts when the counter
bogdanm	82:6473597d706e	761	* reaches the channel delay register and one peripheral clock cycle after a rising
bogdanm	82:6473597d706e	762	* edge is detected on selected trigger input source or software trigger is
bogdanm	82:6473597d706e	763	* selected and SETRIG is written with 1.
bogdanm	82:6473597d706e	764	*/
bogdanm	82:6473597d706e	765	//@{
bogdanm	82:6473597d706e	766	#define BP_PDB_CHnC1_TOS (8U) //!< Bit position for PDB_CHnC1_TOS.
bogdanm	82:6473597d706e	767	#define BM_PDB_CHnC1_TOS (0x0000FF00U) //!< Bit mask for PDB_CHnC1_TOS.
bogdanm	82:6473597d706e	768	#define BS_PDB_CHnC1_TOS (8U) //!< Bit field size in bits for PDB_CHnC1_TOS.
bogdanm	82:6473597d706e	769
bogdanm	82:6473597d706e	770	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	771	//! @brief Read current value of the PDB_CHnC1_TOS field.
bogdanm	82:6473597d706e	772	#define BR_PDB_CHnC1_TOS(n) (HW_PDB_CHnC1(n).B.TOS)
bogdanm	82:6473597d706e	773	#endif
bogdanm	82:6473597d706e	774
bogdanm	82:6473597d706e	775	//! @brief Format value for bitfield PDB_CHnC1_TOS.
bogdanm	82:6473597d706e	776	#define BF_PDB_CHnC1_TOS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_TOS), uint32_t) & BM_PDB_CHnC1_TOS)
bogdanm	82:6473597d706e	777
bogdanm	82:6473597d706e	778	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	779	//! @brief Set the TOS field to a new value.
bogdanm	82:6473597d706e	780	#define BW_PDB_CHnC1_TOS(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_TOS) \| BF_PDB_CHnC1_TOS(v)))
bogdanm	82:6473597d706e	781	#endif
bogdanm	82:6473597d706e	782	//@}
bogdanm	82:6473597d706e	783
bogdanm	82:6473597d706e	784	/*!
bogdanm	82:6473597d706e	785	* @name Register PDB_CHnC1, field BB[23:16] (RW)
bogdanm	82:6473597d706e	786	*
bogdanm	82:6473597d706e	787	* These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
bogdanm	82:6473597d706e	788	* Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
bogdanm	82:6473597d706e	789	* enables the ADC conversions complete to trigger the next PDB channel
bogdanm	82:6473597d706e	790	* pre-trigger and trigger output, so that the ADC conversions can be triggered on next
bogdanm	82:6473597d706e	791	* set of configuration and results registers. Application code must only enable
bogdanm	82:6473597d706e	792	* the back-to-back operation of the PDB pre-triggers at the leading of the
bogdanm	82:6473597d706e	793	* back-to-back connection chain.
bogdanm	82:6473597d706e	794	*
bogdanm	82:6473597d706e	795	* Values:
bogdanm	82:6473597d706e	796	* - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
bogdanm	82:6473597d706e	797	* - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
bogdanm	82:6473597d706e	798	*/
bogdanm	82:6473597d706e	799	//@{
bogdanm	82:6473597d706e	800	#define BP_PDB_CHnC1_BB (16U) //!< Bit position for PDB_CHnC1_BB.
bogdanm	82:6473597d706e	801	#define BM_PDB_CHnC1_BB (0x00FF0000U) //!< Bit mask for PDB_CHnC1_BB.
bogdanm	82:6473597d706e	802	#define BS_PDB_CHnC1_BB (8U) //!< Bit field size in bits for PDB_CHnC1_BB.
bogdanm	82:6473597d706e	803
bogdanm	82:6473597d706e	804	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	805	//! @brief Read current value of the PDB_CHnC1_BB field.
bogdanm	82:6473597d706e	806	#define BR_PDB_CHnC1_BB(n) (HW_PDB_CHnC1(n).B.BB)
bogdanm	82:6473597d706e	807	#endif
bogdanm	82:6473597d706e	808
bogdanm	82:6473597d706e	809	//! @brief Format value for bitfield PDB_CHnC1_BB.
bogdanm	82:6473597d706e	810	#define BF_PDB_CHnC1_BB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_BB), uint32_t) & BM_PDB_CHnC1_BB)
bogdanm	82:6473597d706e	811
bogdanm	82:6473597d706e	812	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	813	//! @brief Set the BB field to a new value.
bogdanm	82:6473597d706e	814	#define BW_PDB_CHnC1_BB(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_BB) \| BF_PDB_CHnC1_BB(v)))
bogdanm	82:6473597d706e	815	#endif
bogdanm	82:6473597d706e	816	//@}
bogdanm	82:6473597d706e	817	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	818	// HW_PDB_CHnS - Channel n Status register
bogdanm	82:6473597d706e	819	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	820
bogdanm	82:6473597d706e	821	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	822	/*!
bogdanm	82:6473597d706e	823	* @brief HW_PDB_CHnS - Channel n Status register (RW)
bogdanm	82:6473597d706e	824	*
bogdanm	82:6473597d706e	825	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	826	*/
bogdanm	82:6473597d706e	827	typedef union _hw_pdb_chns
bogdanm	82:6473597d706e	828	{
bogdanm	82:6473597d706e	829	uint32_t U;
bogdanm	82:6473597d706e	830	struct _hw_pdb_chns_bitfields
bogdanm	82:6473597d706e	831	{
bogdanm	82:6473597d706e	832	uint32_t ERR : 8; //!< [7:0] PDB Channel Sequence Error Flags
bogdanm	82:6473597d706e	833	uint32_t RESERVED0 : 8; //!< [15:8]
bogdanm	82:6473597d706e	834	uint32_t CF : 8; //!< [23:16] PDB Channel Flags
bogdanm	82:6473597d706e	835	uint32_t RESERVED1 : 8; //!< [31:24]
bogdanm	82:6473597d706e	836	} B;
bogdanm	82:6473597d706e	837	} hw_pdb_chns_t;
bogdanm	82:6473597d706e	838	#endif
bogdanm	82:6473597d706e	839
bogdanm	82:6473597d706e	840	/*!
bogdanm	82:6473597d706e	841	* @name Constants and macros for entire PDB_CHnS register
bogdanm	82:6473597d706e	842	*/
bogdanm	82:6473597d706e	843	//@{
bogdanm	82:6473597d706e	844	#define HW_PDB_CHnS_COUNT (2U)
bogdanm	82:6473597d706e	845
bogdanm	82:6473597d706e	846	#define HW_PDB_CHnS_ADDR(n) (REGS_PDB_BASE + 0x14U + (0x28U * n))
bogdanm	82:6473597d706e	847
bogdanm	82:6473597d706e	848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	849	#define HW_PDB_CHnS(n) ((__IO hw_pdb_chns_t ) HW_PDB_CHnS_ADDR(n))
bogdanm	82:6473597d706e	850	#define HW_PDB_CHnS_RD(n) (HW_PDB_CHnS(n).U)
bogdanm	82:6473597d706e	851	#define HW_PDB_CHnS_WR(n, v) (HW_PDB_CHnS(n).U = (v))
bogdanm	82:6473597d706e	852	#define HW_PDB_CHnS_SET(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) \| (v)))
bogdanm	82:6473597d706e	853	#define HW_PDB_CHnS_CLR(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) & ~(v)))
bogdanm	82:6473597d706e	854	#define HW_PDB_CHnS_TOG(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) ^ (v)))
bogdanm	82:6473597d706e	855	#endif
bogdanm	82:6473597d706e	856	//@}
bogdanm	82:6473597d706e	857
bogdanm	82:6473597d706e	858	/*
bogdanm	82:6473597d706e	859	* Constants & macros for individual PDB_CHnS bitfields
bogdanm	82:6473597d706e	860	*/
bogdanm	82:6473597d706e	861
bogdanm	82:6473597d706e	862	/*!
bogdanm	82:6473597d706e	863	* @name Register PDB_CHnS, field ERR[7:0] (RW)
bogdanm	82:6473597d706e	864	*
bogdanm	82:6473597d706e	865	* Only the lower M bits are implemented in this MCU.
bogdanm	82:6473597d706e	866	*
bogdanm	82:6473597d706e	867	* Values:
bogdanm	82:6473597d706e	868	* - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
bogdanm	82:6473597d706e	869	* - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
bogdanm	82:6473597d706e	870	* ADCn block can be triggered for a conversion by one pre-trigger from PDB
bogdanm	82:6473597d706e	871	* channel n. When one conversion, which is triggered by one of the pre-triggers
bogdanm	82:6473597d706e	872	* from PDB channel n, is in progress, new trigger from PDB channel's
bogdanm	82:6473597d706e	873	* corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
bogdanm	82:6473597d706e	874	* Writing 0's to clear the sequence error flags.
bogdanm	82:6473597d706e	875	*/
bogdanm	82:6473597d706e	876	//@{
bogdanm	82:6473597d706e	877	#define BP_PDB_CHnS_ERR (0U) //!< Bit position for PDB_CHnS_ERR.
bogdanm	82:6473597d706e	878	#define BM_PDB_CHnS_ERR (0x000000FFU) //!< Bit mask for PDB_CHnS_ERR.
bogdanm	82:6473597d706e	879	#define BS_PDB_CHnS_ERR (8U) //!< Bit field size in bits for PDB_CHnS_ERR.
bogdanm	82:6473597d706e	880
bogdanm	82:6473597d706e	881	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	882	//! @brief Read current value of the PDB_CHnS_ERR field.
bogdanm	82:6473597d706e	883	#define BR_PDB_CHnS_ERR(n) (HW_PDB_CHnS(n).B.ERR)
bogdanm	82:6473597d706e	884	#endif
bogdanm	82:6473597d706e	885
bogdanm	82:6473597d706e	886	//! @brief Format value for bitfield PDB_CHnS_ERR.
bogdanm	82:6473597d706e	887	#define BF_PDB_CHnS_ERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_ERR), uint32_t) & BM_PDB_CHnS_ERR)
bogdanm	82:6473597d706e	888
bogdanm	82:6473597d706e	889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	890	//! @brief Set the ERR field to a new value.
bogdanm	82:6473597d706e	891	#define BW_PDB_CHnS_ERR(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_ERR) \| BF_PDB_CHnS_ERR(v)))
bogdanm	82:6473597d706e	892	#endif
bogdanm	82:6473597d706e	893	//@}
bogdanm	82:6473597d706e	894
bogdanm	82:6473597d706e	895	/*!
bogdanm	82:6473597d706e	896	* @name Register PDB_CHnS, field CF[23:16] (RW)
bogdanm	82:6473597d706e	897	*
bogdanm	82:6473597d706e	898	* The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
bogdanm	82:6473597d706e	899	* clear these bits.
bogdanm	82:6473597d706e	900	*/
bogdanm	82:6473597d706e	901	//@{
bogdanm	82:6473597d706e	902	#define BP_PDB_CHnS_CF (16U) //!< Bit position for PDB_CHnS_CF.
bogdanm	82:6473597d706e	903	#define BM_PDB_CHnS_CF (0x00FF0000U) //!< Bit mask for PDB_CHnS_CF.
bogdanm	82:6473597d706e	904	#define BS_PDB_CHnS_CF (8U) //!< Bit field size in bits for PDB_CHnS_CF.
bogdanm	82:6473597d706e	905
bogdanm	82:6473597d706e	906	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	907	//! @brief Read current value of the PDB_CHnS_CF field.
bogdanm	82:6473597d706e	908	#define BR_PDB_CHnS_CF(n) (HW_PDB_CHnS(n).B.CF)
bogdanm	82:6473597d706e	909	#endif
bogdanm	82:6473597d706e	910
bogdanm	82:6473597d706e	911	//! @brief Format value for bitfield PDB_CHnS_CF.
bogdanm	82:6473597d706e	912	#define BF_PDB_CHnS_CF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_CF), uint32_t) & BM_PDB_CHnS_CF)
bogdanm	82:6473597d706e	913
bogdanm	82:6473597d706e	914	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	915	//! @brief Set the CF field to a new value.
bogdanm	82:6473597d706e	916	#define BW_PDB_CHnS_CF(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_CF) \| BF_PDB_CHnS_CF(v)))
bogdanm	82:6473597d706e	917	#endif
bogdanm	82:6473597d706e	918	//@}
bogdanm	82:6473597d706e	919	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	920	// HW_PDB_CHnDLY0 - Channel n Delay 0 register
bogdanm	82:6473597d706e	921	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	924	/*!
bogdanm	82:6473597d706e	925	* @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
bogdanm	82:6473597d706e	926	*
bogdanm	82:6473597d706e	927	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	928	*/
bogdanm	82:6473597d706e	929	typedef union _hw_pdb_chndly0
bogdanm	82:6473597d706e	930	{
bogdanm	82:6473597d706e	931	uint32_t U;
bogdanm	82:6473597d706e	932	struct _hw_pdb_chndly0_bitfields
bogdanm	82:6473597d706e	933	{
bogdanm	82:6473597d706e	934	uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
bogdanm	82:6473597d706e	935	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	936	} B;
bogdanm	82:6473597d706e	937	} hw_pdb_chndly0_t;
bogdanm	82:6473597d706e	938	#endif
bogdanm	82:6473597d706e	939
bogdanm	82:6473597d706e	940	/*!
bogdanm	82:6473597d706e	941	* @name Constants and macros for entire PDB_CHnDLY0 register
bogdanm	82:6473597d706e	942	*/
bogdanm	82:6473597d706e	943	//@{
bogdanm	82:6473597d706e	944	#define HW_PDB_CHnDLY0_COUNT (2U)
bogdanm	82:6473597d706e	945
bogdanm	82:6473597d706e	946	#define HW_PDB_CHnDLY0_ADDR(n) (REGS_PDB_BASE + 0x18U + (0x28U * n))
bogdanm	82:6473597d706e	947
bogdanm	82:6473597d706e	948	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	949	#define HW_PDB_CHnDLY0(n) ((__IO hw_pdb_chndly0_t ) HW_PDB_CHnDLY0_ADDR(n))
bogdanm	82:6473597d706e	950	#define HW_PDB_CHnDLY0_RD(n) (HW_PDB_CHnDLY0(n).U)
bogdanm	82:6473597d706e	951	#define HW_PDB_CHnDLY0_WR(n, v) (HW_PDB_CHnDLY0(n).U = (v))
bogdanm	82:6473597d706e	952	#define HW_PDB_CHnDLY0_SET(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) \| (v)))
bogdanm	82:6473597d706e	953	#define HW_PDB_CHnDLY0_CLR(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) & ~(v)))
bogdanm	82:6473597d706e	954	#define HW_PDB_CHnDLY0_TOG(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) ^ (v)))
bogdanm	82:6473597d706e	955	#endif
bogdanm	82:6473597d706e	956	//@}
bogdanm	82:6473597d706e	957
bogdanm	82:6473597d706e	958	/*
bogdanm	82:6473597d706e	959	* Constants & macros for individual PDB_CHnDLY0 bitfields
bogdanm	82:6473597d706e	960	*/
bogdanm	82:6473597d706e	961
bogdanm	82:6473597d706e	962	/*!
bogdanm	82:6473597d706e	963	* @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
bogdanm	82:6473597d706e	964	*
bogdanm	82:6473597d706e	965	* Specifies the delay value for the channel's corresponding pre-trigger. The
bogdanm	82:6473597d706e	966	* pre-trigger asserts when the counter is equal to DLY. Reading this field returns
bogdanm	82:6473597d706e	967	* the value of internal register that is effective for the current PDB cycle.
bogdanm	82:6473597d706e	968	*/
bogdanm	82:6473597d706e	969	//@{
bogdanm	82:6473597d706e	970	#define BP_PDB_CHnDLY0_DLY (0U) //!< Bit position for PDB_CHnDLY0_DLY.
bogdanm	82:6473597d706e	971	#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY0_DLY.
bogdanm	82:6473597d706e	972	#define BS_PDB_CHnDLY0_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY0_DLY.
bogdanm	82:6473597d706e	973
bogdanm	82:6473597d706e	974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	975	//! @brief Read current value of the PDB_CHnDLY0_DLY field.
bogdanm	82:6473597d706e	976	#define BR_PDB_CHnDLY0_DLY(n) (HW_PDB_CHnDLY0(n).B.DLY)
bogdanm	82:6473597d706e	977	#endif
bogdanm	82:6473597d706e	978
bogdanm	82:6473597d706e	979	//! @brief Format value for bitfield PDB_CHnDLY0_DLY.
bogdanm	82:6473597d706e	980	#define BF_PDB_CHnDLY0_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY0_DLY), uint32_t) & BM_PDB_CHnDLY0_DLY)
bogdanm	82:6473597d706e	981
bogdanm	82:6473597d706e	982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	983	//! @brief Set the DLY field to a new value.
bogdanm	82:6473597d706e	984	#define BW_PDB_CHnDLY0_DLY(n, v) (HW_PDB_CHnDLY0_WR(n, (HW_PDB_CHnDLY0_RD(n) & ~BM_PDB_CHnDLY0_DLY) \| BF_PDB_CHnDLY0_DLY(v)))
bogdanm	82:6473597d706e	985	#endif
bogdanm	82:6473597d706e	986	//@}
bogdanm	82:6473597d706e	987	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	988	// HW_PDB_CHnDLY1 - Channel n Delay 1 register
bogdanm	82:6473597d706e	989	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	990
bogdanm	82:6473597d706e	991	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	992	/*!
bogdanm	82:6473597d706e	993	* @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
bogdanm	82:6473597d706e	994	*
bogdanm	82:6473597d706e	995	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	996	*/
bogdanm	82:6473597d706e	997	typedef union _hw_pdb_chndly1
bogdanm	82:6473597d706e	998	{
bogdanm	82:6473597d706e	999	uint32_t U;
bogdanm	82:6473597d706e	1000	struct _hw_pdb_chndly1_bitfields
bogdanm	82:6473597d706e	1001	{
bogdanm	82:6473597d706e	1002	uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
bogdanm	82:6473597d706e	1003	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1004	} B;
bogdanm	82:6473597d706e	1005	} hw_pdb_chndly1_t;
bogdanm	82:6473597d706e	1006	#endif
bogdanm	82:6473597d706e	1007
bogdanm	82:6473597d706e	1008	/*!
bogdanm	82:6473597d706e	1009	* @name Constants and macros for entire PDB_CHnDLY1 register
bogdanm	82:6473597d706e	1010	*/
bogdanm	82:6473597d706e	1011	//@{
bogdanm	82:6473597d706e	1012	#define HW_PDB_CHnDLY1_COUNT (2U)
bogdanm	82:6473597d706e	1013
bogdanm	82:6473597d706e	1014	#define HW_PDB_CHnDLY1_ADDR(n) (REGS_PDB_BASE + 0x1CU + (0x28U * n))
bogdanm	82:6473597d706e	1015
bogdanm	82:6473597d706e	1016	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1017	#define HW_PDB_CHnDLY1(n) ((__IO hw_pdb_chndly1_t ) HW_PDB_CHnDLY1_ADDR(n))
bogdanm	82:6473597d706e	1018	#define HW_PDB_CHnDLY1_RD(n) (HW_PDB_CHnDLY1(n).U)
bogdanm	82:6473597d706e	1019	#define HW_PDB_CHnDLY1_WR(n, v) (HW_PDB_CHnDLY1(n).U = (v))
bogdanm	82:6473597d706e	1020	#define HW_PDB_CHnDLY1_SET(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) \| (v)))
bogdanm	82:6473597d706e	1021	#define HW_PDB_CHnDLY1_CLR(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1022	#define HW_PDB_CHnDLY1_TOG(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1023	#endif
bogdanm	82:6473597d706e	1024	//@}
bogdanm	82:6473597d706e	1025
bogdanm	82:6473597d706e	1026	/*
bogdanm	82:6473597d706e	1027	* Constants & macros for individual PDB_CHnDLY1 bitfields
bogdanm	82:6473597d706e	1028	*/
bogdanm	82:6473597d706e	1029
bogdanm	82:6473597d706e	1030	/*!
bogdanm	82:6473597d706e	1031	* @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
bogdanm	82:6473597d706e	1032	*
bogdanm	82:6473597d706e	1033	* These bits specify the delay value for the channel's corresponding
bogdanm	82:6473597d706e	1034	* pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
bogdanm	82:6473597d706e	1035	* bits returns the value of internal register that is effective for the current PDB
bogdanm	82:6473597d706e	1036	* cycle.
bogdanm	82:6473597d706e	1037	*/
bogdanm	82:6473597d706e	1038	//@{
bogdanm	82:6473597d706e	1039	#define BP_PDB_CHnDLY1_DLY (0U) //!< Bit position for PDB_CHnDLY1_DLY.
bogdanm	82:6473597d706e	1040	#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY1_DLY.
bogdanm	82:6473597d706e	1041	#define BS_PDB_CHnDLY1_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY1_DLY.
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1044	//! @brief Read current value of the PDB_CHnDLY1_DLY field.
bogdanm	82:6473597d706e	1045	#define BR_PDB_CHnDLY1_DLY(n) (HW_PDB_CHnDLY1(n).B.DLY)
bogdanm	82:6473597d706e	1046	#endif
bogdanm	82:6473597d706e	1047
bogdanm	82:6473597d706e	1048	//! @brief Format value for bitfield PDB_CHnDLY1_DLY.
bogdanm	82:6473597d706e	1049	#define BF_PDB_CHnDLY1_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY1_DLY), uint32_t) & BM_PDB_CHnDLY1_DLY)
bogdanm	82:6473597d706e	1050
bogdanm	82:6473597d706e	1051	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1052	//! @brief Set the DLY field to a new value.
bogdanm	82:6473597d706e	1053	#define BW_PDB_CHnDLY1_DLY(n, v) (HW_PDB_CHnDLY1_WR(n, (HW_PDB_CHnDLY1_RD(n) & ~BM_PDB_CHnDLY1_DLY) \| BF_PDB_CHnDLY1_DLY(v)))
bogdanm	82:6473597d706e	1054	#endif
bogdanm	82:6473597d706e	1055	//@}
bogdanm	82:6473597d706e	1056
bogdanm	82:6473597d706e	1057	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1058	// HW_PDB_DACINTCn - DAC Interval Trigger n Control register
bogdanm	82:6473597d706e	1059	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1060
bogdanm	82:6473597d706e	1061	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1062	/*!
bogdanm	82:6473597d706e	1063	* @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
bogdanm	82:6473597d706e	1064	*
bogdanm	82:6473597d706e	1065	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1066	*/
bogdanm	82:6473597d706e	1067	typedef union _hw_pdb_dacintcn
bogdanm	82:6473597d706e	1068	{
bogdanm	82:6473597d706e	1069	uint32_t U;
bogdanm	82:6473597d706e	1070	struct _hw_pdb_dacintcn_bitfields
bogdanm	82:6473597d706e	1071	{
bogdanm	82:6473597d706e	1072	uint32_t TOE : 1; //!< [0] DAC Interval Trigger Enable
bogdanm	82:6473597d706e	1073	uint32_t EXT : 1; //!< [1] DAC External Trigger Input Enable
bogdanm	82:6473597d706e	1074	uint32_t RESERVED0 : 30; //!< [31:2]
bogdanm	82:6473597d706e	1075	} B;
bogdanm	82:6473597d706e	1076	} hw_pdb_dacintcn_t;
bogdanm	82:6473597d706e	1077	#endif
bogdanm	82:6473597d706e	1078
bogdanm	82:6473597d706e	1079	/*!
bogdanm	82:6473597d706e	1080	* @name Constants and macros for entire PDB_DACINTCn register
bogdanm	82:6473597d706e	1081	*/
bogdanm	82:6473597d706e	1082	//@{
bogdanm	82:6473597d706e	1083	#define HW_PDB_DACINTCn_COUNT (2U)
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	#define HW_PDB_DACINTCn_ADDR(n) (REGS_PDB_BASE + 0x150U + (0x8U * n))
bogdanm	82:6473597d706e	1086
bogdanm	82:6473597d706e	1087	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1088	#define HW_PDB_DACINTCn(n) ((__IO hw_pdb_dacintcn_t ) HW_PDB_DACINTCn_ADDR(n))
bogdanm	82:6473597d706e	1089	#define HW_PDB_DACINTCn_RD(n) (HW_PDB_DACINTCn(n).U)
bogdanm	82:6473597d706e	1090	#define HW_PDB_DACINTCn_WR(n, v) (HW_PDB_DACINTCn(n).U = (v))
bogdanm	82:6473597d706e	1091	#define HW_PDB_DACINTCn_SET(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1092	#define HW_PDB_DACINTCn_CLR(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1093	#define HW_PDB_DACINTCn_TOG(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1094	#endif
bogdanm	82:6473597d706e	1095	//@}
bogdanm	82:6473597d706e	1096
bogdanm	82:6473597d706e	1097	/*
bogdanm	82:6473597d706e	1098	* Constants & macros for individual PDB_DACINTCn bitfields
bogdanm	82:6473597d706e	1099	*/
bogdanm	82:6473597d706e	1100
bogdanm	82:6473597d706e	1101	/*!
bogdanm	82:6473597d706e	1102	* @name Register PDB_DACINTCn, field TOE[0] (RW)
bogdanm	82:6473597d706e	1103	*
bogdanm	82:6473597d706e	1104	* This bit enables the DAC interval trigger.
bogdanm	82:6473597d706e	1105	*
bogdanm	82:6473597d706e	1106	* Values:
bogdanm	82:6473597d706e	1107	* - 0 - DAC interval trigger disabled.
bogdanm	82:6473597d706e	1108	* - 1 - DAC interval trigger enabled.
bogdanm	82:6473597d706e	1109	*/
bogdanm	82:6473597d706e	1110	//@{
bogdanm	82:6473597d706e	1111	#define BP_PDB_DACINTCn_TOE (0U) //!< Bit position for PDB_DACINTCn_TOE.
bogdanm	82:6473597d706e	1112	#define BM_PDB_DACINTCn_TOE (0x00000001U) //!< Bit mask for PDB_DACINTCn_TOE.
bogdanm	82:6473597d706e	1113	#define BS_PDB_DACINTCn_TOE (1U) //!< Bit field size in bits for PDB_DACINTCn_TOE.
bogdanm	82:6473597d706e	1114
bogdanm	82:6473597d706e	1115	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1116	//! @brief Read current value of the PDB_DACINTCn_TOE field.
bogdanm	82:6473597d706e	1117	#define BR_PDB_DACINTCn_TOE(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE))
bogdanm	82:6473597d706e	1118	#endif
bogdanm	82:6473597d706e	1119
bogdanm	82:6473597d706e	1120	//! @brief Format value for bitfield PDB_DACINTCn_TOE.
bogdanm	82:6473597d706e	1121	#define BF_PDB_DACINTCn_TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_TOE), uint32_t) & BM_PDB_DACINTCn_TOE)
bogdanm	82:6473597d706e	1122
bogdanm	82:6473597d706e	1123	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1124	//! @brief Set the TOE field to a new value.
bogdanm	82:6473597d706e	1125	#define BW_PDB_DACINTCn_TOE(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE) = (v))
bogdanm	82:6473597d706e	1126	#endif
bogdanm	82:6473597d706e	1127	//@}
bogdanm	82:6473597d706e	1128
bogdanm	82:6473597d706e	1129	/*!
bogdanm	82:6473597d706e	1130	* @name Register PDB_DACINTCn, field EXT[1] (RW)
bogdanm	82:6473597d706e	1131	*
bogdanm	82:6473597d706e	1132	* Enables the external trigger for DAC interval counter.
bogdanm	82:6473597d706e	1133	*
bogdanm	82:6473597d706e	1134	* Values:
bogdanm	82:6473597d706e	1135	* - 0 - DAC external trigger input disabled. DAC interval counter is reset and
bogdanm	82:6473597d706e	1136	* counting starts when a rising edge is detected on selected trigger input
bogdanm	82:6473597d706e	1137	* source or software trigger is selected and SWTRIG is written with 1.
bogdanm	82:6473597d706e	1138	* - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
bogdanm	82:6473597d706e	1139	* and DAC external trigger input triggers the DAC interval trigger.
bogdanm	82:6473597d706e	1140	*/
bogdanm	82:6473597d706e	1141	//@{
bogdanm	82:6473597d706e	1142	#define BP_PDB_DACINTCn_EXT (1U) //!< Bit position for PDB_DACINTCn_EXT.
bogdanm	82:6473597d706e	1143	#define BM_PDB_DACINTCn_EXT (0x00000002U) //!< Bit mask for PDB_DACINTCn_EXT.
bogdanm	82:6473597d706e	1144	#define BS_PDB_DACINTCn_EXT (1U) //!< Bit field size in bits for PDB_DACINTCn_EXT.
bogdanm	82:6473597d706e	1145
bogdanm	82:6473597d706e	1146	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1147	//! @brief Read current value of the PDB_DACINTCn_EXT field.
bogdanm	82:6473597d706e	1148	#define BR_PDB_DACINTCn_EXT(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT))
bogdanm	82:6473597d706e	1149	#endif
bogdanm	82:6473597d706e	1150
bogdanm	82:6473597d706e	1151	//! @brief Format value for bitfield PDB_DACINTCn_EXT.
bogdanm	82:6473597d706e	1152	#define BF_PDB_DACINTCn_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_EXT), uint32_t) & BM_PDB_DACINTCn_EXT)
bogdanm	82:6473597d706e	1153
bogdanm	82:6473597d706e	1154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1155	//! @brief Set the EXT field to a new value.
bogdanm	82:6473597d706e	1156	#define BW_PDB_DACINTCn_EXT(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT) = (v))
bogdanm	82:6473597d706e	1157	#endif
bogdanm	82:6473597d706e	1158	//@}
bogdanm	82:6473597d706e	1159	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1160	// HW_PDB_DACINTn - DAC Interval n register
bogdanm	82:6473597d706e	1161	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1162
bogdanm	82:6473597d706e	1163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1164	/*!
bogdanm	82:6473597d706e	1165	* @brief HW_PDB_DACINTn - DAC Interval n register (RW)
bogdanm	82:6473597d706e	1166	*
bogdanm	82:6473597d706e	1167	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1168	*/
bogdanm	82:6473597d706e	1169	typedef union _hw_pdb_dacintn
bogdanm	82:6473597d706e	1170	{
bogdanm	82:6473597d706e	1171	uint32_t U;
bogdanm	82:6473597d706e	1172	struct _hw_pdb_dacintn_bitfields
bogdanm	82:6473597d706e	1173	{
bogdanm	82:6473597d706e	1174	uint32_t INT : 16; //!< [15:0] DAC Interval
bogdanm	82:6473597d706e	1175	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1176	} B;
bogdanm	82:6473597d706e	1177	} hw_pdb_dacintn_t;
bogdanm	82:6473597d706e	1178	#endif
bogdanm	82:6473597d706e	1179
bogdanm	82:6473597d706e	1180	/*!
bogdanm	82:6473597d706e	1181	* @name Constants and macros for entire PDB_DACINTn register
bogdanm	82:6473597d706e	1182	*/
bogdanm	82:6473597d706e	1183	//@{
bogdanm	82:6473597d706e	1184	#define HW_PDB_DACINTn_COUNT (2U)
bogdanm	82:6473597d706e	1185
bogdanm	82:6473597d706e	1186	#define HW_PDB_DACINTn_ADDR(n) (REGS_PDB_BASE + 0x154U + (0x8U * n))
bogdanm	82:6473597d706e	1187
bogdanm	82:6473597d706e	1188	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1189	#define HW_PDB_DACINTn(n) ((__IO hw_pdb_dacintn_t ) HW_PDB_DACINTn_ADDR(n))
bogdanm	82:6473597d706e	1190	#define HW_PDB_DACINTn_RD(n) (HW_PDB_DACINTn(n).U)
bogdanm	82:6473597d706e	1191	#define HW_PDB_DACINTn_WR(n, v) (HW_PDB_DACINTn(n).U = (v))
bogdanm	82:6473597d706e	1192	#define HW_PDB_DACINTn_SET(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1193	#define HW_PDB_DACINTn_CLR(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1194	#define HW_PDB_DACINTn_TOG(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1195	#endif
bogdanm	82:6473597d706e	1196	//@}
bogdanm	82:6473597d706e	1197
bogdanm	82:6473597d706e	1198	/*
bogdanm	82:6473597d706e	1199	* Constants & macros for individual PDB_DACINTn bitfields
bogdanm	82:6473597d706e	1200	*/
bogdanm	82:6473597d706e	1201
bogdanm	82:6473597d706e	1202	/*!
bogdanm	82:6473597d706e	1203	* @name Register PDB_DACINTn, field INT[15:0] (RW)
bogdanm	82:6473597d706e	1204	*
bogdanm	82:6473597d706e	1205	* Specifies the interval value for DAC interval trigger. DAC interval trigger
bogdanm	82:6473597d706e	1206	* triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
bogdanm	82:6473597d706e	1207	* Reading this field returns the value of internal register that is effective
bogdanm	82:6473597d706e	1208	* for the current PDB cycle.
bogdanm	82:6473597d706e	1209	*/
bogdanm	82:6473597d706e	1210	//@{
bogdanm	82:6473597d706e	1211	#define BP_PDB_DACINTn_INT (0U) //!< Bit position for PDB_DACINTn_INT.
bogdanm	82:6473597d706e	1212	#define BM_PDB_DACINTn_INT (0x0000FFFFU) //!< Bit mask for PDB_DACINTn_INT.
bogdanm	82:6473597d706e	1213	#define BS_PDB_DACINTn_INT (16U) //!< Bit field size in bits for PDB_DACINTn_INT.
bogdanm	82:6473597d706e	1214
bogdanm	82:6473597d706e	1215	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1216	//! @brief Read current value of the PDB_DACINTn_INT field.
bogdanm	82:6473597d706e	1217	#define BR_PDB_DACINTn_INT(n) (HW_PDB_DACINTn(n).B.INT)
bogdanm	82:6473597d706e	1218	#endif
bogdanm	82:6473597d706e	1219
bogdanm	82:6473597d706e	1220	//! @brief Format value for bitfield PDB_DACINTn_INT.
bogdanm	82:6473597d706e	1221	#define BF_PDB_DACINTn_INT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTn_INT), uint32_t) & BM_PDB_DACINTn_INT)
bogdanm	82:6473597d706e	1222
bogdanm	82:6473597d706e	1223	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1224	//! @brief Set the INT field to a new value.
bogdanm	82:6473597d706e	1225	#define BW_PDB_DACINTn_INT(n, v) (HW_PDB_DACINTn_WR(n, (HW_PDB_DACINTn_RD(n) & ~BM_PDB_DACINTn_INT) \| BF_PDB_DACINTn_INT(v)))
bogdanm	82:6473597d706e	1226	#endif
bogdanm	82:6473597d706e	1227	//@}
bogdanm	82:6473597d706e	1228
bogdanm	82:6473597d706e	1229	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1230	// HW_PDB_POEN - Pulse-Out n Enable register
bogdanm	82:6473597d706e	1231	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1232
bogdanm	82:6473597d706e	1233	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1234	/*!
bogdanm	82:6473597d706e	1235	* @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
bogdanm	82:6473597d706e	1236	*
bogdanm	82:6473597d706e	1237	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1238	*/
bogdanm	82:6473597d706e	1239	typedef union _hw_pdb_poen
bogdanm	82:6473597d706e	1240	{
bogdanm	82:6473597d706e	1241	uint32_t U;
bogdanm	82:6473597d706e	1242	struct _hw_pdb_poen_bitfields
bogdanm	82:6473597d706e	1243	{
bogdanm	82:6473597d706e	1244	uint32_t POEN : 8; //!< [7:0] PDB Pulse-Out Enable
bogdanm	82:6473597d706e	1245	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1246	} B;
bogdanm	82:6473597d706e	1247	} hw_pdb_poen_t;
bogdanm	82:6473597d706e	1248	#endif
bogdanm	82:6473597d706e	1249
bogdanm	82:6473597d706e	1250	/*!
bogdanm	82:6473597d706e	1251	* @name Constants and macros for entire PDB_POEN register
bogdanm	82:6473597d706e	1252	*/
bogdanm	82:6473597d706e	1253	//@{
bogdanm	82:6473597d706e	1254	#define HW_PDB_POEN_ADDR (REGS_PDB_BASE + 0x190U)
bogdanm	82:6473597d706e	1255
bogdanm	82:6473597d706e	1256	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1257	#define HW_PDB_POEN ((__IO hw_pdb_poen_t ) HW_PDB_POEN_ADDR)
bogdanm	82:6473597d706e	1258	#define HW_PDB_POEN_RD() (HW_PDB_POEN.U)
bogdanm	82:6473597d706e	1259	#define HW_PDB_POEN_WR(v) (HW_PDB_POEN.U = (v))
bogdanm	82:6473597d706e	1260	#define HW_PDB_POEN_SET(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() \| (v)))
bogdanm	82:6473597d706e	1261	#define HW_PDB_POEN_CLR(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() & ~(v)))
bogdanm	82:6473597d706e	1262	#define HW_PDB_POEN_TOG(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() ^ (v)))
bogdanm	82:6473597d706e	1263	#endif
bogdanm	82:6473597d706e	1264	//@}
bogdanm	82:6473597d706e	1265
bogdanm	82:6473597d706e	1266	/*
bogdanm	82:6473597d706e	1267	* Constants & macros for individual PDB_POEN bitfields
bogdanm	82:6473597d706e	1268	*/
bogdanm	82:6473597d706e	1269
bogdanm	82:6473597d706e	1270	/*!
bogdanm	82:6473597d706e	1271	* @name Register PDB_POEN, field POEN[7:0] (RW)
bogdanm	82:6473597d706e	1272	*
bogdanm	82:6473597d706e	1273	* Enables the pulse output. Only lower Y bits are implemented in this MCU.
bogdanm	82:6473597d706e	1274	*
bogdanm	82:6473597d706e	1275	* Values:
bogdanm	82:6473597d706e	1276	* - 0 - PDB Pulse-Out disabled
bogdanm	82:6473597d706e	1277	* - 1 - PDB Pulse-Out enabled
bogdanm	82:6473597d706e	1278	*/
bogdanm	82:6473597d706e	1279	//@{
bogdanm	82:6473597d706e	1280	#define BP_PDB_POEN_POEN (0U) //!< Bit position for PDB_POEN_POEN.
bogdanm	82:6473597d706e	1281	#define BM_PDB_POEN_POEN (0x000000FFU) //!< Bit mask for PDB_POEN_POEN.
bogdanm	82:6473597d706e	1282	#define BS_PDB_POEN_POEN (8U) //!< Bit field size in bits for PDB_POEN_POEN.
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1285	//! @brief Read current value of the PDB_POEN_POEN field.
bogdanm	82:6473597d706e	1286	#define BR_PDB_POEN_POEN (HW_PDB_POEN.B.POEN)
bogdanm	82:6473597d706e	1287	#endif
bogdanm	82:6473597d706e	1288
bogdanm	82:6473597d706e	1289	//! @brief Format value for bitfield PDB_POEN_POEN.
bogdanm	82:6473597d706e	1290	#define BF_PDB_POEN_POEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POEN_POEN), uint32_t) & BM_PDB_POEN_POEN)
bogdanm	82:6473597d706e	1291
bogdanm	82:6473597d706e	1292	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1293	//! @brief Set the POEN field to a new value.
bogdanm	82:6473597d706e	1294	#define BW_PDB_POEN_POEN(v) (HW_PDB_POEN_WR((HW_PDB_POEN_RD() & ~BM_PDB_POEN_POEN) \| BF_PDB_POEN_POEN(v)))
bogdanm	82:6473597d706e	1295	#endif
bogdanm	82:6473597d706e	1296	//@}
bogdanm	82:6473597d706e	1297
bogdanm	82:6473597d706e	1298	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1299	// HW_PDB_POnDLY - Pulse-Out n Delay register
bogdanm	82:6473597d706e	1300	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1301
bogdanm	82:6473597d706e	1302	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1303	/*!
bogdanm	82:6473597d706e	1304	* @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
bogdanm	82:6473597d706e	1305	*
bogdanm	82:6473597d706e	1306	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1307	*/
bogdanm	82:6473597d706e	1308	typedef union _hw_pdb_pondly
bogdanm	82:6473597d706e	1309	{
bogdanm	82:6473597d706e	1310	uint32_t U;
bogdanm	82:6473597d706e	1311	struct _hw_pdb_pondly_bitfields
bogdanm	82:6473597d706e	1312	{
bogdanm	82:6473597d706e	1313	uint32_t DLY2 : 16; //!< [15:0] PDB Pulse-Out Delay 2
bogdanm	82:6473597d706e	1314	uint32_t DLY1 : 16; //!< [31:16] PDB Pulse-Out Delay 1
bogdanm	82:6473597d706e	1315	} B;
bogdanm	82:6473597d706e	1316	} hw_pdb_pondly_t;
bogdanm	82:6473597d706e	1317	#endif
bogdanm	82:6473597d706e	1318
bogdanm	82:6473597d706e	1319	/*!
bogdanm	82:6473597d706e	1320	* @name Constants and macros for entire PDB_POnDLY register
bogdanm	82:6473597d706e	1321	*/
bogdanm	82:6473597d706e	1322	//@{
bogdanm	82:6473597d706e	1323	#define HW_PDB_POnDLY_COUNT (3U)
bogdanm	82:6473597d706e	1324
bogdanm	82:6473597d706e	1325	#define HW_PDB_POnDLY_ADDR(n) (REGS_PDB_BASE + 0x194U + (0x4U * n))
bogdanm	82:6473597d706e	1326
bogdanm	82:6473597d706e	1327	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1328	#define HW_PDB_POnDLY(n) ((__IO hw_pdb_pondly_t ) HW_PDB_POnDLY_ADDR(n))
bogdanm	82:6473597d706e	1329	#define HW_PDB_POnDLY_RD(n) (HW_PDB_POnDLY(n).U)
bogdanm	82:6473597d706e	1330	#define HW_PDB_POnDLY_WR(n, v) (HW_PDB_POnDLY(n).U = (v))
bogdanm	82:6473597d706e	1331	#define HW_PDB_POnDLY_SET(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) \| (v)))
bogdanm	82:6473597d706e	1332	#define HW_PDB_POnDLY_CLR(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1333	#define HW_PDB_POnDLY_TOG(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1334	#endif
bogdanm	82:6473597d706e	1335	//@}
bogdanm	82:6473597d706e	1336
bogdanm	82:6473597d706e	1337	/*
bogdanm	82:6473597d706e	1338	* Constants & macros for individual PDB_POnDLY bitfields
bogdanm	82:6473597d706e	1339	*/
bogdanm	82:6473597d706e	1340
bogdanm	82:6473597d706e	1341	/*!
bogdanm	82:6473597d706e	1342	* @name Register PDB_POnDLY, field DLY2[15:0] (RW)
bogdanm	82:6473597d706e	1343	*
bogdanm	82:6473597d706e	1344	* These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
bogdanm	82:6473597d706e	1345	* low when the PDB counter is equal to the DLY2. Reading these bits returns the
bogdanm	82:6473597d706e	1346	* value of internal register that is effective for the current PDB cycle.
bogdanm	82:6473597d706e	1347	*/
bogdanm	82:6473597d706e	1348	//@{
bogdanm	82:6473597d706e	1349	#define BP_PDB_POnDLY_DLY2 (0U) //!< Bit position for PDB_POnDLY_DLY2.
bogdanm	82:6473597d706e	1350	#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) //!< Bit mask for PDB_POnDLY_DLY2.
bogdanm	82:6473597d706e	1351	#define BS_PDB_POnDLY_DLY2 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY2.
bogdanm	82:6473597d706e	1352
bogdanm	82:6473597d706e	1353	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1354	//! @brief Read current value of the PDB_POnDLY_DLY2 field.
bogdanm	82:6473597d706e	1355	#define BR_PDB_POnDLY_DLY2(n) (HW_PDB_POnDLY(n).B.DLY2)
bogdanm	82:6473597d706e	1356	#endif
bogdanm	82:6473597d706e	1357
bogdanm	82:6473597d706e	1358	//! @brief Format value for bitfield PDB_POnDLY_DLY2.
bogdanm	82:6473597d706e	1359	#define BF_PDB_POnDLY_DLY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY2), uint32_t) & BM_PDB_POnDLY_DLY2)
bogdanm	82:6473597d706e	1360
bogdanm	82:6473597d706e	1361	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1362	//! @brief Set the DLY2 field to a new value.
bogdanm	82:6473597d706e	1363	#define BW_PDB_POnDLY_DLY2(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY2) \| BF_PDB_POnDLY_DLY2(v)))
bogdanm	82:6473597d706e	1364	#endif
bogdanm	82:6473597d706e	1365	//@}
bogdanm	82:6473597d706e	1366
bogdanm	82:6473597d706e	1367	/*!
bogdanm	82:6473597d706e	1368	* @name Register PDB_POnDLY, field DLY1[31:16] (RW)
bogdanm	82:6473597d706e	1369	*
bogdanm	82:6473597d706e	1370	* These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
bogdanm	82:6473597d706e	1371	* high when the PDB counter is equal to the DLY1. Reading these bits returns the
bogdanm	82:6473597d706e	1372	* value of internal register that is effective for the current PDB cycle.
bogdanm	82:6473597d706e	1373	*/
bogdanm	82:6473597d706e	1374	//@{
bogdanm	82:6473597d706e	1375	#define BP_PDB_POnDLY_DLY1 (16U) //!< Bit position for PDB_POnDLY_DLY1.
bogdanm	82:6473597d706e	1376	#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) //!< Bit mask for PDB_POnDLY_DLY1.
bogdanm	82:6473597d706e	1377	#define BS_PDB_POnDLY_DLY1 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY1.
bogdanm	82:6473597d706e	1378
bogdanm	82:6473597d706e	1379	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1380	//! @brief Read current value of the PDB_POnDLY_DLY1 field.
bogdanm	82:6473597d706e	1381	#define BR_PDB_POnDLY_DLY1(n) (HW_PDB_POnDLY(n).B.DLY1)
bogdanm	82:6473597d706e	1382	#endif
bogdanm	82:6473597d706e	1383
bogdanm	82:6473597d706e	1384	//! @brief Format value for bitfield PDB_POnDLY_DLY1.
bogdanm	82:6473597d706e	1385	#define BF_PDB_POnDLY_DLY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY1), uint32_t) & BM_PDB_POnDLY_DLY1)
bogdanm	82:6473597d706e	1386
bogdanm	82:6473597d706e	1387	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1388	//! @brief Set the DLY1 field to a new value.
bogdanm	82:6473597d706e	1389	#define BW_PDB_POnDLY_DLY1(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY1) \| BF_PDB_POnDLY_DLY1(v)))
bogdanm	82:6473597d706e	1390	#endif
bogdanm	82:6473597d706e	1391	//@}
bogdanm	82:6473597d706e	1392
bogdanm	82:6473597d706e	1393	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1394	// hw_pdb_t - module struct
bogdanm	82:6473597d706e	1395	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1396	/*!
bogdanm	82:6473597d706e	1397	* @brief All PDB module registers.
bogdanm	82:6473597d706e	1398	*/
bogdanm	82:6473597d706e	1399	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1400	#pragma pack(1)
bogdanm	82:6473597d706e	1401	typedef struct _hw_pdb
bogdanm	82:6473597d706e	1402	{
bogdanm	82:6473597d706e	1403	__IO hw_pdb_sc_t SC; //!< [0x0] Status and Control register
bogdanm	82:6473597d706e	1404	__IO hw_pdb_mod_t MOD; //!< [0x4] Modulus register
bogdanm	82:6473597d706e	1405	__I hw_pdb_cnt_t CNT; //!< [0x8] Counter register
bogdanm	82:6473597d706e	1406	__IO hw_pdb_idly_t IDLY; //!< [0xC] Interrupt Delay register
bogdanm	82:6473597d706e	1407	struct {
bogdanm	82:6473597d706e	1408	__IO hw_pdb_chnc1_t CHnC1; //!< [0x10] Channel n Control register 1
bogdanm	82:6473597d706e	1409	__IO hw_pdb_chns_t CHnS; //!< [0x14] Channel n Status register
bogdanm	82:6473597d706e	1410	__IO hw_pdb_chndly0_t CHnDLY0; //!< [0x18] Channel n Delay 0 register
bogdanm	82:6473597d706e	1411	__IO hw_pdb_chndly1_t CHnDLY1; //!< [0x1C] Channel n Delay 1 register
bogdanm	82:6473597d706e	1412	uint8_t _reserved0[24];
bogdanm	82:6473597d706e	1413	} CH[2];
bogdanm	82:6473597d706e	1414	uint8_t _reserved0[240];
bogdanm	82:6473597d706e	1415	struct {
bogdanm	82:6473597d706e	1416	__IO hw_pdb_dacintcn_t DACINTCn; //!< [0x150] DAC Interval Trigger n Control register
bogdanm	82:6473597d706e	1417	__IO hw_pdb_dacintn_t DACINTn; //!< [0x154] DAC Interval n register
bogdanm	82:6473597d706e	1418	} DAC[2];
bogdanm	82:6473597d706e	1419	uint8_t _reserved1[48];
bogdanm	82:6473597d706e	1420	__IO hw_pdb_poen_t POEN; //!< [0x190] Pulse-Out n Enable register
bogdanm	82:6473597d706e	1421	__IO hw_pdb_pondly_t POnDLY[3]; //!< [0x194] Pulse-Out n Delay register
bogdanm	82:6473597d706e	1422	} hw_pdb_t;
bogdanm	82:6473597d706e	1423	#pragma pack()
bogdanm	82:6473597d706e	1424
bogdanm	82:6473597d706e	1425	//! @brief Macro to access all PDB registers.
bogdanm	82:6473597d706e	1426	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1427	//! use the '&' operator, like <code>&HW_PDB</code>.
bogdanm	82:6473597d706e	1428	#define HW_PDB ((hw_pdb_t ) REGS_PDB_BASE)
bogdanm	82:6473597d706e	1429	#endif
bogdanm	82:6473597d706e	1430
bogdanm	82:6473597d706e	1431	#endif // __HW_PDB_REGISTERS_H__
bogdanm	82:6473597d706e	1432	// v22/130726/0.9
bogdanm	82:6473597d706e	1433	// EOF

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
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The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pdb.h@82:6473597d706e, 2014-04-07 (annotated)

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