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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2c.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_I2C_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_I2C_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 I2C
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Inter-Integrated Circuit
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_I2C_A1 - I2C Address Register 1
bogdanm	82:6473597d706e	33	* - HW_I2C_F - I2C Frequency Divider register
bogdanm	82:6473597d706e	34	* - HW_I2C_C1 - I2C Control Register 1
bogdanm	82:6473597d706e	35	* - HW_I2C_S - I2C Status register
bogdanm	82:6473597d706e	36	* - HW_I2C_D - I2C Data I/O register
bogdanm	82:6473597d706e	37	* - HW_I2C_C2 - I2C Control Register 2
bogdanm	82:6473597d706e	38	* - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
bogdanm	82:6473597d706e	39	* - HW_I2C_RA - I2C Range Address register
bogdanm	82:6473597d706e	40	* - HW_I2C_SMB - I2C SMBus Control and Status register
bogdanm	82:6473597d706e	41	* - HW_I2C_A2 - I2C Address Register 2
bogdanm	82:6473597d706e	42	* - HW_I2C_SLTH - I2C SCL Low Timeout Register High
bogdanm	82:6473597d706e	43	* - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
bogdanm	82:6473597d706e	44	*
bogdanm	82:6473597d706e	45	* - hw_i2c_t - Struct containing all module registers.
bogdanm	82:6473597d706e	46	*/
bogdanm	82:6473597d706e	47
bogdanm	82:6473597d706e	48	//! @name Module base addresses
bogdanm	82:6473597d706e	49	//@{
bogdanm	82:6473597d706e	50	#ifndef REGS_I2C_BASE
bogdanm	82:6473597d706e	51	#define HW_I2C_INSTANCE_COUNT (3U) //!< Number of instances of the I2C module.
bogdanm	82:6473597d706e	52	#define HW_I2C0 (0U) //!< Instance number for I2C0.
bogdanm	82:6473597d706e	53	#define HW_I2C1 (1U) //!< Instance number for I2C1.
bogdanm	82:6473597d706e	54	#define HW_I2C2 (2U) //!< Instance number for I2C2.
bogdanm	82:6473597d706e	55	#define REGS_I2C0_BASE (0x40066000U) //!< Base address for I2C0.
bogdanm	82:6473597d706e	56	#define REGS_I2C1_BASE (0x40067000U) //!< Base address for I2C1.
bogdanm	82:6473597d706e	57	#define REGS_I2C2_BASE (0x400E6000U) //!< Base address for I2C2.
bogdanm	82:6473597d706e	58
bogdanm	82:6473597d706e	59	//! @brief Table of base addresses for I2C instances.
bogdanm	82:6473597d706e	60	static const uint32_t __g_regs_I2C_base_addresses[] = {
bogdanm	82:6473597d706e	61	REGS_I2C0_BASE,
bogdanm	82:6473597d706e	62	REGS_I2C1_BASE,
bogdanm	82:6473597d706e	63	REGS_I2C2_BASE,
bogdanm	82:6473597d706e	64	};
bogdanm	82:6473597d706e	65
bogdanm	82:6473597d706e	66	//! @brief Get the base address of I2C by instance number.
bogdanm	82:6473597d706e	67	//! @param x I2C instance number, from 0 through 2.
bogdanm	82:6473597d706e	68	#define REGS_I2C_BASE(x) (__g_regs_I2C_base_addresses[(x)])
bogdanm	82:6473597d706e	69
bogdanm	82:6473597d706e	70	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	71	//! @param b Base address for an instance of I2C.
bogdanm	82:6473597d706e	72	#define REGS_I2C_INSTANCE(b) ((b) == REGS_I2C0_BASE ? HW_I2C0 : (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : 0)
bogdanm	82:6473597d706e	73	#endif
bogdanm	82:6473597d706e	74	//@}
bogdanm	82:6473597d706e	75
bogdanm	82:6473597d706e	76	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	77	// HW_I2C_A1 - I2C Address Register 1
bogdanm	82:6473597d706e	78	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	79
bogdanm	82:6473597d706e	80	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	81	/*!
bogdanm	82:6473597d706e	82	* @brief HW_I2C_A1 - I2C Address Register 1 (RW)
bogdanm	82:6473597d706e	83	*
bogdanm	82:6473597d706e	84	* Reset value: 0x00U
bogdanm	82:6473597d706e	85	*
bogdanm	82:6473597d706e	86	* This register contains the slave address to be used by the I2C module.
bogdanm	82:6473597d706e	87	*/
bogdanm	82:6473597d706e	88	typedef union _hw_i2c_a1
bogdanm	82:6473597d706e	89	{
bogdanm	82:6473597d706e	90	uint8_t U;
bogdanm	82:6473597d706e	91	struct _hw_i2c_a1_bitfields
bogdanm	82:6473597d706e	92	{
bogdanm	82:6473597d706e	93	uint8_t RESERVED0 : 1; //!< [0]
bogdanm	82:6473597d706e	94	uint8_t AD : 7; //!< [7:1] Address
bogdanm	82:6473597d706e	95	} B;
bogdanm	82:6473597d706e	96	} hw_i2c_a1_t;
bogdanm	82:6473597d706e	97	#endif
bogdanm	82:6473597d706e	98
bogdanm	82:6473597d706e	99	/*!
bogdanm	82:6473597d706e	100	* @name Constants and macros for entire I2C_A1 register
bogdanm	82:6473597d706e	101	*/
bogdanm	82:6473597d706e	102	//@{
bogdanm	82:6473597d706e	103	#define HW_I2C_A1_ADDR(x) (REGS_I2C_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	104
bogdanm	82:6473597d706e	105	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	106	#define HW_I2C_A1(x) ((__IO hw_i2c_a1_t ) HW_I2C_A1_ADDR(x))
bogdanm	82:6473597d706e	107	#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U)
bogdanm	82:6473597d706e	108	#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v))
bogdanm	82:6473597d706e	109	#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) \| (v)))
bogdanm	82:6473597d706e	110	#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	111	#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	112	#endif
bogdanm	82:6473597d706e	113	//@}
bogdanm	82:6473597d706e	114
bogdanm	82:6473597d706e	115	/*
bogdanm	82:6473597d706e	116	* Constants & macros for individual I2C_A1 bitfields
bogdanm	82:6473597d706e	117	*/
bogdanm	82:6473597d706e	118
bogdanm	82:6473597d706e	119	/*!
bogdanm	82:6473597d706e	120	* @name Register I2C_A1, field AD[7:1] (RW)
bogdanm	82:6473597d706e	121	*
bogdanm	82:6473597d706e	122	* Contains the primary slave address used by the I2C module when it is
bogdanm	82:6473597d706e	123	* addressed as a slave. This field is used in the 7-bit address scheme and the lower
bogdanm	82:6473597d706e	124	* seven bits in the 10-bit address scheme.
bogdanm	82:6473597d706e	125	*/
bogdanm	82:6473597d706e	126	//@{
bogdanm	82:6473597d706e	127	#define BP_I2C_A1_AD (1U) //!< Bit position for I2C_A1_AD.
bogdanm	82:6473597d706e	128	#define BM_I2C_A1_AD (0xFEU) //!< Bit mask for I2C_A1_AD.
bogdanm	82:6473597d706e	129	#define BS_I2C_A1_AD (7U) //!< Bit field size in bits for I2C_A1_AD.
bogdanm	82:6473597d706e	130
bogdanm	82:6473597d706e	131	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	132	//! @brief Read current value of the I2C_A1_AD field.
bogdanm	82:6473597d706e	133	#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD)
bogdanm	82:6473597d706e	134	#endif
bogdanm	82:6473597d706e	135
bogdanm	82:6473597d706e	136	//! @brief Format value for bitfield I2C_A1_AD.
bogdanm	82:6473597d706e	137	#define BF_I2C_A1_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A1_AD), uint8_t) & BM_I2C_A1_AD)
bogdanm	82:6473597d706e	138
bogdanm	82:6473597d706e	139	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	140	//! @brief Set the AD field to a new value.
bogdanm	82:6473597d706e	141	#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) \| BF_I2C_A1_AD(v)))
bogdanm	82:6473597d706e	142	#endif
bogdanm	82:6473597d706e	143	//@}
bogdanm	82:6473597d706e	144
bogdanm	82:6473597d706e	145	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	146	// HW_I2C_F - I2C Frequency Divider register
bogdanm	82:6473597d706e	147	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	148
bogdanm	82:6473597d706e	149	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	150	/*!
bogdanm	82:6473597d706e	151	* @brief HW_I2C_F - I2C Frequency Divider register (RW)
bogdanm	82:6473597d706e	152	*
bogdanm	82:6473597d706e	153	* Reset value: 0x00U
bogdanm	82:6473597d706e	154	*/
bogdanm	82:6473597d706e	155	typedef union _hw_i2c_f
bogdanm	82:6473597d706e	156	{
bogdanm	82:6473597d706e	157	uint8_t U;
bogdanm	82:6473597d706e	158	struct _hw_i2c_f_bitfields
bogdanm	82:6473597d706e	159	{
bogdanm	82:6473597d706e	160	uint8_t ICR : 6; //!< [5:0] ClockRate
bogdanm	82:6473597d706e	161	uint8_t MULT : 2; //!< [7:6] Multiplier Factor
bogdanm	82:6473597d706e	162	} B;
bogdanm	82:6473597d706e	163	} hw_i2c_f_t;
bogdanm	82:6473597d706e	164	#endif
bogdanm	82:6473597d706e	165
bogdanm	82:6473597d706e	166	/*!
bogdanm	82:6473597d706e	167	* @name Constants and macros for entire I2C_F register
bogdanm	82:6473597d706e	168	*/
bogdanm	82:6473597d706e	169	//@{
bogdanm	82:6473597d706e	170	#define HW_I2C_F_ADDR(x) (REGS_I2C_BASE(x) + 0x1U)
bogdanm	82:6473597d706e	171
bogdanm	82:6473597d706e	172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	173	#define HW_I2C_F(x) ((__IO hw_i2c_f_t ) HW_I2C_F_ADDR(x))
bogdanm	82:6473597d706e	174	#define HW_I2C_F_RD(x) (HW_I2C_F(x).U)
bogdanm	82:6473597d706e	175	#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v))
bogdanm	82:6473597d706e	176	#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) \| (v)))
bogdanm	82:6473597d706e	177	#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
bogdanm	82:6473597d706e	178	#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v)))
bogdanm	82:6473597d706e	179	#endif
bogdanm	82:6473597d706e	180	//@}
bogdanm	82:6473597d706e	181
bogdanm	82:6473597d706e	182	/*
bogdanm	82:6473597d706e	183	* Constants & macros for individual I2C_F bitfields
bogdanm	82:6473597d706e	184	*/
bogdanm	82:6473597d706e	185
bogdanm	82:6473597d706e	186	/*!
bogdanm	82:6473597d706e	187	* @name Register I2C_F, field ICR[5:0] (RW)
bogdanm	82:6473597d706e	188	*
bogdanm	82:6473597d706e	189	* Prescales the I2C module clock for bit rate selection. This field and the
bogdanm	82:6473597d706e	190	* MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
bogdanm	82:6473597d706e	191	* time, and the SCL stop hold time. For a list of values corresponding to each ICR
bogdanm	82:6473597d706e	192	* setting, see I2C divider and hold values. The SCL divider multiplied by
bogdanm	82:6473597d706e	193	* multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
bogdanm	82:6473597d706e	194	* clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
bogdanm	82:6473597d706e	195	* falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
bogdanm	82:6473597d706e	196	* I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
bogdanm	82:6473597d706e	197	* the delay from the falling edge of SDA (I2C data) while SCL is high (start
bogdanm	82:6473597d706e	198	* condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
bogdanm	82:6473597d706e	199	* module clock period (s) * mul * SCL start hold value The SCL stop hold time is
bogdanm	82:6473597d706e	200	* the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
bogdanm	82:6473597d706e	201	* data) while SCL is high (stop condition). SCL stop hold time = I2C module
bogdanm	82:6473597d706e	202	* clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
bogdanm	82:6473597d706e	203	* speed is 8 MHz, the following table shows the possible hold time values with
bogdanm	82:6473597d706e	204	* different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
bogdanm	82:6473597d706e	205	* MULT ICR Hold times (μs) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h
bogdanm	82:6473597d706e	206	* 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
bogdanm	82:6473597d706e	207	* 1.125 4.750 5.125
bogdanm	82:6473597d706e	208	*/
bogdanm	82:6473597d706e	209	//@{
bogdanm	82:6473597d706e	210	#define BP_I2C_F_ICR (0U) //!< Bit position for I2C_F_ICR.
bogdanm	82:6473597d706e	211	#define BM_I2C_F_ICR (0x3FU) //!< Bit mask for I2C_F_ICR.
bogdanm	82:6473597d706e	212	#define BS_I2C_F_ICR (6U) //!< Bit field size in bits for I2C_F_ICR.
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	215	//! @brief Read current value of the I2C_F_ICR field.
bogdanm	82:6473597d706e	216	#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR)
bogdanm	82:6473597d706e	217	#endif
bogdanm	82:6473597d706e	218
bogdanm	82:6473597d706e	219	//! @brief Format value for bitfield I2C_F_ICR.
bogdanm	82:6473597d706e	220	#define BF_I2C_F_ICR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_ICR), uint8_t) & BM_I2C_F_ICR)
bogdanm	82:6473597d706e	221
bogdanm	82:6473597d706e	222	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	223	//! @brief Set the ICR field to a new value.
bogdanm	82:6473597d706e	224	#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) \| BF_I2C_F_ICR(v)))
bogdanm	82:6473597d706e	225	#endif
bogdanm	82:6473597d706e	226	//@}
bogdanm	82:6473597d706e	227
bogdanm	82:6473597d706e	228	/*!
bogdanm	82:6473597d706e	229	* @name Register I2C_F, field MULT[7:6] (RW)
bogdanm	82:6473597d706e	230	*
bogdanm	82:6473597d706e	231	* Defines the multiplier factor (mul). This factor is used along with the SCL
bogdanm	82:6473597d706e	232	* divider to generate the I2C baud rate.
bogdanm	82:6473597d706e	233	*
bogdanm	82:6473597d706e	234	* Values:
bogdanm	82:6473597d706e	235	* - 00 - mul = 1
bogdanm	82:6473597d706e	236	* - 01 - mul = 2
bogdanm	82:6473597d706e	237	* - 10 - mul = 4
bogdanm	82:6473597d706e	238	* - 11 - Reserved
bogdanm	82:6473597d706e	239	*/
bogdanm	82:6473597d706e	240	//@{
bogdanm	82:6473597d706e	241	#define BP_I2C_F_MULT (6U) //!< Bit position for I2C_F_MULT.
bogdanm	82:6473597d706e	242	#define BM_I2C_F_MULT (0xC0U) //!< Bit mask for I2C_F_MULT.
bogdanm	82:6473597d706e	243	#define BS_I2C_F_MULT (2U) //!< Bit field size in bits for I2C_F_MULT.
bogdanm	82:6473597d706e	244
bogdanm	82:6473597d706e	245	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	246	//! @brief Read current value of the I2C_F_MULT field.
bogdanm	82:6473597d706e	247	#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT)
bogdanm	82:6473597d706e	248	#endif
bogdanm	82:6473597d706e	249
bogdanm	82:6473597d706e	250	//! @brief Format value for bitfield I2C_F_MULT.
bogdanm	82:6473597d706e	251	#define BF_I2C_F_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_MULT), uint8_t) & BM_I2C_F_MULT)
bogdanm	82:6473597d706e	252
bogdanm	82:6473597d706e	253	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	254	//! @brief Set the MULT field to a new value.
bogdanm	82:6473597d706e	255	#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) \| BF_I2C_F_MULT(v)))
bogdanm	82:6473597d706e	256	#endif
bogdanm	82:6473597d706e	257	//@}
bogdanm	82:6473597d706e	258
bogdanm	82:6473597d706e	259	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	260	// HW_I2C_C1 - I2C Control Register 1
bogdanm	82:6473597d706e	261	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	262
bogdanm	82:6473597d706e	263	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	264	/*!
bogdanm	82:6473597d706e	265	* @brief HW_I2C_C1 - I2C Control Register 1 (RW)
bogdanm	82:6473597d706e	266	*
bogdanm	82:6473597d706e	267	* Reset value: 0x00U
bogdanm	82:6473597d706e	268	*/
bogdanm	82:6473597d706e	269	typedef union _hw_i2c_c1
bogdanm	82:6473597d706e	270	{
bogdanm	82:6473597d706e	271	uint8_t U;
bogdanm	82:6473597d706e	272	struct _hw_i2c_c1_bitfields
bogdanm	82:6473597d706e	273	{
bogdanm	82:6473597d706e	274	uint8_t DMAEN : 1; //!< [0] DMA Enable
bogdanm	82:6473597d706e	275	uint8_t WUEN : 1; //!< [1] Wakeup Enable
bogdanm	82:6473597d706e	276	uint8_t RSTA : 1; //!< [2] Repeat START
bogdanm	82:6473597d706e	277	uint8_t TXAK : 1; //!< [3] Transmit Acknowledge Enable
bogdanm	82:6473597d706e	278	uint8_t TX : 1; //!< [4] Transmit Mode Select
bogdanm	82:6473597d706e	279	uint8_t MST : 1; //!< [5] Master Mode Select
bogdanm	82:6473597d706e	280	uint8_t IICIE : 1; //!< [6] I2C Interrupt Enable
bogdanm	82:6473597d706e	281	uint8_t IICEN : 1; //!< [7] I2C Enable
bogdanm	82:6473597d706e	282	} B;
bogdanm	82:6473597d706e	283	} hw_i2c_c1_t;
bogdanm	82:6473597d706e	284	#endif
bogdanm	82:6473597d706e	285
bogdanm	82:6473597d706e	286	/*!
bogdanm	82:6473597d706e	287	* @name Constants and macros for entire I2C_C1 register
bogdanm	82:6473597d706e	288	*/
bogdanm	82:6473597d706e	289	//@{
bogdanm	82:6473597d706e	290	#define HW_I2C_C1_ADDR(x) (REGS_I2C_BASE(x) + 0x2U)
bogdanm	82:6473597d706e	291
bogdanm	82:6473597d706e	292	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	293	#define HW_I2C_C1(x) ((__IO hw_i2c_c1_t ) HW_I2C_C1_ADDR(x))
bogdanm	82:6473597d706e	294	#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U)
bogdanm	82:6473597d706e	295	#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v))
bogdanm	82:6473597d706e	296	#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) \| (v)))
bogdanm	82:6473597d706e	297	#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	298	#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	299	#endif
bogdanm	82:6473597d706e	300	//@}
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	/*
bogdanm	82:6473597d706e	303	* Constants & macros for individual I2C_C1 bitfields
bogdanm	82:6473597d706e	304	*/
bogdanm	82:6473597d706e	305
bogdanm	82:6473597d706e	306	/*!
bogdanm	82:6473597d706e	307	* @name Register I2C_C1, field DMAEN[0] (RW)
bogdanm	82:6473597d706e	308	*
bogdanm	82:6473597d706e	309	* Enables or disables the DMA function.
bogdanm	82:6473597d706e	310	*
bogdanm	82:6473597d706e	311	* Values:
bogdanm	82:6473597d706e	312	* - 0 - All DMA signalling disabled.
bogdanm	82:6473597d706e	313	* - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
bogdanm	82:6473597d706e	314	* trigger the DMA request: a data byte is received, and either address or
bogdanm	82:6473597d706e	315	* data is transmitted. (ACK/NACK is automatic) the first byte received matches
bogdanm	82:6473597d706e	316	* the A1 register or is a general call address. If any address matching
bogdanm	82:6473597d706e	317	* occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
bogdanm	82:6473597d706e	318	* from master to slave, then it is not required to check S[SRW]. With this
bogdanm	82:6473597d706e	319	* assumption, DMA can also be used in this case. In other cases, if the master
bogdanm	82:6473597d706e	320	* reads data from the slave, then it is required to rewrite the C1 register
bogdanm	82:6473597d706e	321	* operation. With this assumption, DMA cannot be used. When FACK = 1, an
bogdanm	82:6473597d706e	322	* address or a data byte is transmitted.
bogdanm	82:6473597d706e	323	*/
bogdanm	82:6473597d706e	324	//@{
bogdanm	82:6473597d706e	325	#define BP_I2C_C1_DMAEN (0U) //!< Bit position for I2C_C1_DMAEN.
bogdanm	82:6473597d706e	326	#define BM_I2C_C1_DMAEN (0x01U) //!< Bit mask for I2C_C1_DMAEN.
bogdanm	82:6473597d706e	327	#define BS_I2C_C1_DMAEN (1U) //!< Bit field size in bits for I2C_C1_DMAEN.
bogdanm	82:6473597d706e	328
bogdanm	82:6473597d706e	329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	330	//! @brief Read current value of the I2C_C1_DMAEN field.
bogdanm	82:6473597d706e	331	#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
bogdanm	82:6473597d706e	332	#endif
bogdanm	82:6473597d706e	333
bogdanm	82:6473597d706e	334	//! @brief Format value for bitfield I2C_C1_DMAEN.
bogdanm	82:6473597d706e	335	#define BF_I2C_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_DMAEN), uint8_t) & BM_I2C_C1_DMAEN)
bogdanm	82:6473597d706e	336
bogdanm	82:6473597d706e	337	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	338	//! @brief Set the DMAEN field to a new value.
bogdanm	82:6473597d706e	339	#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
bogdanm	82:6473597d706e	340	#endif
bogdanm	82:6473597d706e	341	//@}
bogdanm	82:6473597d706e	342
bogdanm	82:6473597d706e	343	/*!
bogdanm	82:6473597d706e	344	* @name Register I2C_C1, field WUEN[1] (RW)
bogdanm	82:6473597d706e	345	*
bogdanm	82:6473597d706e	346	* The I2C module can wake the MCU from low power mode with no peripheral bus
bogdanm	82:6473597d706e	347	* running when slave address matching occurs.
bogdanm	82:6473597d706e	348	*
bogdanm	82:6473597d706e	349	* Values:
bogdanm	82:6473597d706e	350	* - 0 - Normal operation. No interrupt generated when address matching in low
bogdanm	82:6473597d706e	351	* power mode.
bogdanm	82:6473597d706e	352	* - 1 - Enables the wakeup function in low power mode.
bogdanm	82:6473597d706e	353	*/
bogdanm	82:6473597d706e	354	//@{
bogdanm	82:6473597d706e	355	#define BP_I2C_C1_WUEN (1U) //!< Bit position for I2C_C1_WUEN.
bogdanm	82:6473597d706e	356	#define BM_I2C_C1_WUEN (0x02U) //!< Bit mask for I2C_C1_WUEN.
bogdanm	82:6473597d706e	357	#define BS_I2C_C1_WUEN (1U) //!< Bit field size in bits for I2C_C1_WUEN.
bogdanm	82:6473597d706e	358
bogdanm	82:6473597d706e	359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	360	//! @brief Read current value of the I2C_C1_WUEN field.
bogdanm	82:6473597d706e	361	#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
bogdanm	82:6473597d706e	362	#endif
bogdanm	82:6473597d706e	363
bogdanm	82:6473597d706e	364	//! @brief Format value for bitfield I2C_C1_WUEN.
bogdanm	82:6473597d706e	365	#define BF_I2C_C1_WUEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_WUEN), uint8_t) & BM_I2C_C1_WUEN)
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	368	//! @brief Set the WUEN field to a new value.
bogdanm	82:6473597d706e	369	#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
bogdanm	82:6473597d706e	370	#endif
bogdanm	82:6473597d706e	371	//@}
bogdanm	82:6473597d706e	372
bogdanm	82:6473597d706e	373	/*!
bogdanm	82:6473597d706e	374	* @name Register I2C_C1, field RSTA[2] (WORZ)
bogdanm	82:6473597d706e	375	*
bogdanm	82:6473597d706e	376	* Writing 1 to this bit generates a repeated START condition provided it is the
bogdanm	82:6473597d706e	377	* current master. This bit will always be read as 0. Attempting a repeat at the
bogdanm	82:6473597d706e	378	* wrong time results in loss of arbitration.
bogdanm	82:6473597d706e	379	*/
bogdanm	82:6473597d706e	380	//@{
bogdanm	82:6473597d706e	381	#define BP_I2C_C1_RSTA (2U) //!< Bit position for I2C_C1_RSTA.
bogdanm	82:6473597d706e	382	#define BM_I2C_C1_RSTA (0x04U) //!< Bit mask for I2C_C1_RSTA.
bogdanm	82:6473597d706e	383	#define BS_I2C_C1_RSTA (1U) //!< Bit field size in bits for I2C_C1_RSTA.
bogdanm	82:6473597d706e	384
bogdanm	82:6473597d706e	385	//! @brief Format value for bitfield I2C_C1_RSTA.
bogdanm	82:6473597d706e	386	#define BF_I2C_C1_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_RSTA), uint8_t) & BM_I2C_C1_RSTA)
bogdanm	82:6473597d706e	387
bogdanm	82:6473597d706e	388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	389	//! @brief Set the RSTA field to a new value.
bogdanm	82:6473597d706e	390	#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
bogdanm	82:6473597d706e	391	#endif
bogdanm	82:6473597d706e	392	//@}
bogdanm	82:6473597d706e	393
bogdanm	82:6473597d706e	394	/*!
bogdanm	82:6473597d706e	395	* @name Register I2C_C1, field TXAK[3] (RW)
bogdanm	82:6473597d706e	396	*
bogdanm	82:6473597d706e	397	* Specifies the value driven onto the SDA during data acknowledge cycles for
bogdanm	82:6473597d706e	398	* both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
bogdanm	82:6473597d706e	399	* generation. SCL is held low until TXAK is written.
bogdanm	82:6473597d706e	400	*
bogdanm	82:6473597d706e	401	* Values:
bogdanm	82:6473597d706e	402	* - 0 - An acknowledge signal is sent to the bus on the following receiving
bogdanm	82:6473597d706e	403	* byte (if FACK is cleared) or the current receiving byte (if FACK is set).
bogdanm	82:6473597d706e	404	* - 1 - No acknowledge signal is sent to the bus on the following receiving
bogdanm	82:6473597d706e	405	* data byte (if FACK is cleared) or the current receiving data byte (if FACK is
bogdanm	82:6473597d706e	406	* set).
bogdanm	82:6473597d706e	407	*/
bogdanm	82:6473597d706e	408	//@{
bogdanm	82:6473597d706e	409	#define BP_I2C_C1_TXAK (3U) //!< Bit position for I2C_C1_TXAK.
bogdanm	82:6473597d706e	410	#define BM_I2C_C1_TXAK (0x08U) //!< Bit mask for I2C_C1_TXAK.
bogdanm	82:6473597d706e	411	#define BS_I2C_C1_TXAK (1U) //!< Bit field size in bits for I2C_C1_TXAK.
bogdanm	82:6473597d706e	412
bogdanm	82:6473597d706e	413	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	414	//! @brief Read current value of the I2C_C1_TXAK field.
bogdanm	82:6473597d706e	415	#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
bogdanm	82:6473597d706e	416	#endif
bogdanm	82:6473597d706e	417
bogdanm	82:6473597d706e	418	//! @brief Format value for bitfield I2C_C1_TXAK.
bogdanm	82:6473597d706e	419	#define BF_I2C_C1_TXAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TXAK), uint8_t) & BM_I2C_C1_TXAK)
bogdanm	82:6473597d706e	420
bogdanm	82:6473597d706e	421	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	422	//! @brief Set the TXAK field to a new value.
bogdanm	82:6473597d706e	423	#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
bogdanm	82:6473597d706e	424	#endif
bogdanm	82:6473597d706e	425	//@}
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	/*!
bogdanm	82:6473597d706e	428	* @name Register I2C_C1, field TX[4] (RW)
bogdanm	82:6473597d706e	429	*
bogdanm	82:6473597d706e	430	* Selects the direction of master and slave transfers. In master mode this bit
bogdanm	82:6473597d706e	431	* must be set according to the type of transfer required. Therefore, for address
bogdanm	82:6473597d706e	432	* cycles, this bit is always set. When addressed as a slave this bit must be
bogdanm	82:6473597d706e	433	* set by software according to the SRW bit in the status register.
bogdanm	82:6473597d706e	434	*
bogdanm	82:6473597d706e	435	* Values:
bogdanm	82:6473597d706e	436	* - 0 - Receive
bogdanm	82:6473597d706e	437	* - 1 - Transmit
bogdanm	82:6473597d706e	438	*/
bogdanm	82:6473597d706e	439	//@{
bogdanm	82:6473597d706e	440	#define BP_I2C_C1_TX (4U) //!< Bit position for I2C_C1_TX.
bogdanm	82:6473597d706e	441	#define BM_I2C_C1_TX (0x10U) //!< Bit mask for I2C_C1_TX.
bogdanm	82:6473597d706e	442	#define BS_I2C_C1_TX (1U) //!< Bit field size in bits for I2C_C1_TX.
bogdanm	82:6473597d706e	443
bogdanm	82:6473597d706e	444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	445	//! @brief Read current value of the I2C_C1_TX field.
bogdanm	82:6473597d706e	446	#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
bogdanm	82:6473597d706e	447	#endif
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	//! @brief Format value for bitfield I2C_C1_TX.
bogdanm	82:6473597d706e	450	#define BF_I2C_C1_TX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TX), uint8_t) & BM_I2C_C1_TX)
bogdanm	82:6473597d706e	451
bogdanm	82:6473597d706e	452	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	453	//! @brief Set the TX field to a new value.
bogdanm	82:6473597d706e	454	#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
bogdanm	82:6473597d706e	455	#endif
bogdanm	82:6473597d706e	456	//@}
bogdanm	82:6473597d706e	457
bogdanm	82:6473597d706e	458	/*!
bogdanm	82:6473597d706e	459	* @name Register I2C_C1, field MST[5] (RW)
bogdanm	82:6473597d706e	460	*
bogdanm	82:6473597d706e	461	* When MST is changed from 0 to 1, a START signal is generated on the bus and
bogdanm	82:6473597d706e	462	* master mode is selected. When this bit changes from 1 to 0, a STOP signal is
bogdanm	82:6473597d706e	463	* generated and the mode of operation changes from master to slave.
bogdanm	82:6473597d706e	464	*
bogdanm	82:6473597d706e	465	* Values:
bogdanm	82:6473597d706e	466	* - 0 - Slave mode
bogdanm	82:6473597d706e	467	* - 1 - Master mode
bogdanm	82:6473597d706e	468	*/
bogdanm	82:6473597d706e	469	//@{
bogdanm	82:6473597d706e	470	#define BP_I2C_C1_MST (5U) //!< Bit position for I2C_C1_MST.
bogdanm	82:6473597d706e	471	#define BM_I2C_C1_MST (0x20U) //!< Bit mask for I2C_C1_MST.
bogdanm	82:6473597d706e	472	#define BS_I2C_C1_MST (1U) //!< Bit field size in bits for I2C_C1_MST.
bogdanm	82:6473597d706e	473
bogdanm	82:6473597d706e	474	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	475	//! @brief Read current value of the I2C_C1_MST field.
bogdanm	82:6473597d706e	476	#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
bogdanm	82:6473597d706e	477	#endif
bogdanm	82:6473597d706e	478
bogdanm	82:6473597d706e	479	//! @brief Format value for bitfield I2C_C1_MST.
bogdanm	82:6473597d706e	480	#define BF_I2C_C1_MST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_MST), uint8_t) & BM_I2C_C1_MST)
bogdanm	82:6473597d706e	481
bogdanm	82:6473597d706e	482	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	483	//! @brief Set the MST field to a new value.
bogdanm	82:6473597d706e	484	#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
bogdanm	82:6473597d706e	485	#endif
bogdanm	82:6473597d706e	486	//@}
bogdanm	82:6473597d706e	487
bogdanm	82:6473597d706e	488	/*!
bogdanm	82:6473597d706e	489	* @name Register I2C_C1, field IICIE[6] (RW)
bogdanm	82:6473597d706e	490	*
bogdanm	82:6473597d706e	491	* Enables I2C interrupt requests.
bogdanm	82:6473597d706e	492	*
bogdanm	82:6473597d706e	493	* Values:
bogdanm	82:6473597d706e	494	* - 0 - Disabled
bogdanm	82:6473597d706e	495	* - 1 - Enabled
bogdanm	82:6473597d706e	496	*/
bogdanm	82:6473597d706e	497	//@{
bogdanm	82:6473597d706e	498	#define BP_I2C_C1_IICIE (6U) //!< Bit position for I2C_C1_IICIE.
bogdanm	82:6473597d706e	499	#define BM_I2C_C1_IICIE (0x40U) //!< Bit mask for I2C_C1_IICIE.
bogdanm	82:6473597d706e	500	#define BS_I2C_C1_IICIE (1U) //!< Bit field size in bits for I2C_C1_IICIE.
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	503	//! @brief Read current value of the I2C_C1_IICIE field.
bogdanm	82:6473597d706e	504	#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
bogdanm	82:6473597d706e	505	#endif
bogdanm	82:6473597d706e	506
bogdanm	82:6473597d706e	507	//! @brief Format value for bitfield I2C_C1_IICIE.
bogdanm	82:6473597d706e	508	#define BF_I2C_C1_IICIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICIE), uint8_t) & BM_I2C_C1_IICIE)
bogdanm	82:6473597d706e	509
bogdanm	82:6473597d706e	510	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	511	//! @brief Set the IICIE field to a new value.
bogdanm	82:6473597d706e	512	#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
bogdanm	82:6473597d706e	513	#endif
bogdanm	82:6473597d706e	514	//@}
bogdanm	82:6473597d706e	515
bogdanm	82:6473597d706e	516	/*!
bogdanm	82:6473597d706e	517	* @name Register I2C_C1, field IICEN[7] (RW)
bogdanm	82:6473597d706e	518	*
bogdanm	82:6473597d706e	519	* Enables I2C module operation.
bogdanm	82:6473597d706e	520	*
bogdanm	82:6473597d706e	521	* Values:
bogdanm	82:6473597d706e	522	* - 0 - Disabled
bogdanm	82:6473597d706e	523	* - 1 - Enabled
bogdanm	82:6473597d706e	524	*/
bogdanm	82:6473597d706e	525	//@{
bogdanm	82:6473597d706e	526	#define BP_I2C_C1_IICEN (7U) //!< Bit position for I2C_C1_IICEN.
bogdanm	82:6473597d706e	527	#define BM_I2C_C1_IICEN (0x80U) //!< Bit mask for I2C_C1_IICEN.
bogdanm	82:6473597d706e	528	#define BS_I2C_C1_IICEN (1U) //!< Bit field size in bits for I2C_C1_IICEN.
bogdanm	82:6473597d706e	529
bogdanm	82:6473597d706e	530	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	531	//! @brief Read current value of the I2C_C1_IICEN field.
bogdanm	82:6473597d706e	532	#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
bogdanm	82:6473597d706e	533	#endif
bogdanm	82:6473597d706e	534
bogdanm	82:6473597d706e	535	//! @brief Format value for bitfield I2C_C1_IICEN.
bogdanm	82:6473597d706e	536	#define BF_I2C_C1_IICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICEN), uint8_t) & BM_I2C_C1_IICEN)
bogdanm	82:6473597d706e	537
bogdanm	82:6473597d706e	538	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	539	//! @brief Set the IICEN field to a new value.
bogdanm	82:6473597d706e	540	#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
bogdanm	82:6473597d706e	541	#endif
bogdanm	82:6473597d706e	542	//@}
bogdanm	82:6473597d706e	543
bogdanm	82:6473597d706e	544	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	545	// HW_I2C_S - I2C Status register
bogdanm	82:6473597d706e	546	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	547
bogdanm	82:6473597d706e	548	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	549	/*!
bogdanm	82:6473597d706e	550	* @brief HW_I2C_S - I2C Status register (RW)
bogdanm	82:6473597d706e	551	*
bogdanm	82:6473597d706e	552	* Reset value: 0x80U
bogdanm	82:6473597d706e	553	*/
bogdanm	82:6473597d706e	554	typedef union _hw_i2c_s
bogdanm	82:6473597d706e	555	{
bogdanm	82:6473597d706e	556	uint8_t U;
bogdanm	82:6473597d706e	557	struct _hw_i2c_s_bitfields
bogdanm	82:6473597d706e	558	{
bogdanm	82:6473597d706e	559	uint8_t RXAK : 1; //!< [0] Receive Acknowledge
bogdanm	82:6473597d706e	560	uint8_t IICIF : 1; //!< [1] Interrupt Flag
bogdanm	82:6473597d706e	561	uint8_t SRW : 1; //!< [2] Slave Read/Write
bogdanm	82:6473597d706e	562	uint8_t RAM : 1; //!< [3] Range Address Match
bogdanm	82:6473597d706e	563	uint8_t ARBL : 1; //!< [4] Arbitration Lost
bogdanm	82:6473597d706e	564	uint8_t BUSY : 1; //!< [5] Bus Busy
bogdanm	82:6473597d706e	565	uint8_t IAAS : 1; //!< [6] Addressed As A Slave
bogdanm	82:6473597d706e	566	uint8_t TCF : 1; //!< [7] Transfer Complete Flag
bogdanm	82:6473597d706e	567	} B;
bogdanm	82:6473597d706e	568	} hw_i2c_s_t;
bogdanm	82:6473597d706e	569	#endif
bogdanm	82:6473597d706e	570
bogdanm	82:6473597d706e	571	/*!
bogdanm	82:6473597d706e	572	* @name Constants and macros for entire I2C_S register
bogdanm	82:6473597d706e	573	*/
bogdanm	82:6473597d706e	574	//@{
bogdanm	82:6473597d706e	575	#define HW_I2C_S_ADDR(x) (REGS_I2C_BASE(x) + 0x3U)
bogdanm	82:6473597d706e	576
bogdanm	82:6473597d706e	577	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	578	#define HW_I2C_S(x) ((__IO hw_i2c_s_t ) HW_I2C_S_ADDR(x))
bogdanm	82:6473597d706e	579	#define HW_I2C_S_RD(x) (HW_I2C_S(x).U)
bogdanm	82:6473597d706e	580	#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v))
bogdanm	82:6473597d706e	581	#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) \| (v)))
bogdanm	82:6473597d706e	582	#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
bogdanm	82:6473597d706e	583	#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v)))
bogdanm	82:6473597d706e	584	#endif
bogdanm	82:6473597d706e	585	//@}
bogdanm	82:6473597d706e	586
bogdanm	82:6473597d706e	587	/*
bogdanm	82:6473597d706e	588	* Constants & macros for individual I2C_S bitfields
bogdanm	82:6473597d706e	589	*/
bogdanm	82:6473597d706e	590
bogdanm	82:6473597d706e	591	/*!
bogdanm	82:6473597d706e	592	* @name Register I2C_S, field RXAK[0] (RO)
bogdanm	82:6473597d706e	593	*
bogdanm	82:6473597d706e	594	* Values:
bogdanm	82:6473597d706e	595	* - 0 - Acknowledge signal was received after the completion of one byte of
bogdanm	82:6473597d706e	596	* data transmission on the bus
bogdanm	82:6473597d706e	597	* - 1 - No acknowledge signal detected
bogdanm	82:6473597d706e	598	*/
bogdanm	82:6473597d706e	599	//@{
bogdanm	82:6473597d706e	600	#define BP_I2C_S_RXAK (0U) //!< Bit position for I2C_S_RXAK.
bogdanm	82:6473597d706e	601	#define BM_I2C_S_RXAK (0x01U) //!< Bit mask for I2C_S_RXAK.
bogdanm	82:6473597d706e	602	#define BS_I2C_S_RXAK (1U) //!< Bit field size in bits for I2C_S_RXAK.
bogdanm	82:6473597d706e	603
bogdanm	82:6473597d706e	604	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	605	//! @brief Read current value of the I2C_S_RXAK field.
bogdanm	82:6473597d706e	606	#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
bogdanm	82:6473597d706e	607	#endif
bogdanm	82:6473597d706e	608	//@}
bogdanm	82:6473597d706e	609
bogdanm	82:6473597d706e	610	/*!
bogdanm	82:6473597d706e	611	* @name Register I2C_S, field IICIF[1] (W1C)
bogdanm	82:6473597d706e	612	*
bogdanm	82:6473597d706e	613	* This bit sets when an interrupt is pending. This bit must be cleared by
bogdanm	82:6473597d706e	614	* software by writing 1 to it, such as in the interrupt routine. One of the following
bogdanm	82:6473597d706e	615	* events can set this bit: One byte transfer, including ACK/NACK bit, completes
bogdanm	82:6473597d706e	616	* if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
bogdanm	82:6473597d706e	617	* after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
bogdanm	82:6473597d706e	618	* completes if FACK is 1. Match of slave address to calling address including
bogdanm	82:6473597d706e	619	* primary slave address, range slave address , alert response address, second
bogdanm	82:6473597d706e	620	* slave address, or general call address. Arbitration lost In SMBus mode, any
bogdanm	82:6473597d706e	621	* timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
bogdanm	82:6473597d706e	622	* SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
bogdanm	82:6473597d706e	623	* start detection interrupt: In the interrupt service routine, first clear the
bogdanm	82:6473597d706e	624	* STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
bogdanm	82:6473597d706e	625	* then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
bogdanm	82:6473597d706e	626	* asserted again.
bogdanm	82:6473597d706e	627	*
bogdanm	82:6473597d706e	628	* Values:
bogdanm	82:6473597d706e	629	* - 0 - No interrupt pending
bogdanm	82:6473597d706e	630	* - 1 - Interrupt pending
bogdanm	82:6473597d706e	631	*/
bogdanm	82:6473597d706e	632	//@{
bogdanm	82:6473597d706e	633	#define BP_I2C_S_IICIF (1U) //!< Bit position for I2C_S_IICIF.
bogdanm	82:6473597d706e	634	#define BM_I2C_S_IICIF (0x02U) //!< Bit mask for I2C_S_IICIF.
bogdanm	82:6473597d706e	635	#define BS_I2C_S_IICIF (1U) //!< Bit field size in bits for I2C_S_IICIF.
bogdanm	82:6473597d706e	636
bogdanm	82:6473597d706e	637	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	638	//! @brief Read current value of the I2C_S_IICIF field.
bogdanm	82:6473597d706e	639	#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
bogdanm	82:6473597d706e	640	#endif
bogdanm	82:6473597d706e	641
bogdanm	82:6473597d706e	642	//! @brief Format value for bitfield I2C_S_IICIF.
bogdanm	82:6473597d706e	643	#define BF_I2C_S_IICIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IICIF), uint8_t) & BM_I2C_S_IICIF)
bogdanm	82:6473597d706e	644
bogdanm	82:6473597d706e	645	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	646	//! @brief Set the IICIF field to a new value.
bogdanm	82:6473597d706e	647	#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
bogdanm	82:6473597d706e	648	#endif
bogdanm	82:6473597d706e	649	//@}
bogdanm	82:6473597d706e	650
bogdanm	82:6473597d706e	651	/*!
bogdanm	82:6473597d706e	652	* @name Register I2C_S, field SRW[2] (RO)
bogdanm	82:6473597d706e	653	*
bogdanm	82:6473597d706e	654	* When addressed as a slave, SRW indicates the value of the R/W command bit of
bogdanm	82:6473597d706e	655	* the calling address sent to the master.
bogdanm	82:6473597d706e	656	*
bogdanm	82:6473597d706e	657	* Values:
bogdanm	82:6473597d706e	658	* - 0 - Slave receive, master writing to slave
bogdanm	82:6473597d706e	659	* - 1 - Slave transmit, master reading from slave
bogdanm	82:6473597d706e	660	*/
bogdanm	82:6473597d706e	661	//@{
bogdanm	82:6473597d706e	662	#define BP_I2C_S_SRW (2U) //!< Bit position for I2C_S_SRW.
bogdanm	82:6473597d706e	663	#define BM_I2C_S_SRW (0x04U) //!< Bit mask for I2C_S_SRW.
bogdanm	82:6473597d706e	664	#define BS_I2C_S_SRW (1U) //!< Bit field size in bits for I2C_S_SRW.
bogdanm	82:6473597d706e	665
bogdanm	82:6473597d706e	666	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	667	//! @brief Read current value of the I2C_S_SRW field.
bogdanm	82:6473597d706e	668	#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
bogdanm	82:6473597d706e	669	#endif
bogdanm	82:6473597d706e	670	//@}
bogdanm	82:6473597d706e	671
bogdanm	82:6473597d706e	672	/*!
bogdanm	82:6473597d706e	673	* @name Register I2C_S, field RAM[3] (RW)
bogdanm	82:6473597d706e	674	*
bogdanm	82:6473597d706e	675	* This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
bogdanm	82:6473597d706e	676	* Any nonzero calling address is received that matches the address in the RA
bogdanm	82:6473597d706e	677	* register. The calling address is within the range of values of the A1 and RA
bogdanm	82:6473597d706e	678	* registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
bogdanm	82:6473597d706e	679	* Writing the C1 register with any value clears this bit to 0.
bogdanm	82:6473597d706e	680	*
bogdanm	82:6473597d706e	681	* Values:
bogdanm	82:6473597d706e	682	* - 0 - Not addressed
bogdanm	82:6473597d706e	683	* - 1 - Addressed as a slave
bogdanm	82:6473597d706e	684	*/
bogdanm	82:6473597d706e	685	//@{
bogdanm	82:6473597d706e	686	#define BP_I2C_S_RAM (3U) //!< Bit position for I2C_S_RAM.
bogdanm	82:6473597d706e	687	#define BM_I2C_S_RAM (0x08U) //!< Bit mask for I2C_S_RAM.
bogdanm	82:6473597d706e	688	#define BS_I2C_S_RAM (1U) //!< Bit field size in bits for I2C_S_RAM.
bogdanm	82:6473597d706e	689
bogdanm	82:6473597d706e	690	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	691	//! @brief Read current value of the I2C_S_RAM field.
bogdanm	82:6473597d706e	692	#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
bogdanm	82:6473597d706e	693	#endif
bogdanm	82:6473597d706e	694
bogdanm	82:6473597d706e	695	//! @brief Format value for bitfield I2C_S_RAM.
bogdanm	82:6473597d706e	696	#define BF_I2C_S_RAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_RAM), uint8_t) & BM_I2C_S_RAM)
bogdanm	82:6473597d706e	697
bogdanm	82:6473597d706e	698	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	699	//! @brief Set the RAM field to a new value.
bogdanm	82:6473597d706e	700	#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
bogdanm	82:6473597d706e	701	#endif
bogdanm	82:6473597d706e	702	//@}
bogdanm	82:6473597d706e	703
bogdanm	82:6473597d706e	704	/*!
bogdanm	82:6473597d706e	705	* @name Register I2C_S, field ARBL[4] (W1C)
bogdanm	82:6473597d706e	706	*
bogdanm	82:6473597d706e	707	* This bit is set by hardware when the arbitration procedure is lost. The ARBL
bogdanm	82:6473597d706e	708	* bit must be cleared by software, by writing 1 to it.
bogdanm	82:6473597d706e	709	*
bogdanm	82:6473597d706e	710	* Values:
bogdanm	82:6473597d706e	711	* - 0 - Standard bus operation.
bogdanm	82:6473597d706e	712	* - 1 - Loss of arbitration.
bogdanm	82:6473597d706e	713	*/
bogdanm	82:6473597d706e	714	//@{
bogdanm	82:6473597d706e	715	#define BP_I2C_S_ARBL (4U) //!< Bit position for I2C_S_ARBL.
bogdanm	82:6473597d706e	716	#define BM_I2C_S_ARBL (0x10U) //!< Bit mask for I2C_S_ARBL.
bogdanm	82:6473597d706e	717	#define BS_I2C_S_ARBL (1U) //!< Bit field size in bits for I2C_S_ARBL.
bogdanm	82:6473597d706e	718
bogdanm	82:6473597d706e	719	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	720	//! @brief Read current value of the I2C_S_ARBL field.
bogdanm	82:6473597d706e	721	#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
bogdanm	82:6473597d706e	722	#endif
bogdanm	82:6473597d706e	723
bogdanm	82:6473597d706e	724	//! @brief Format value for bitfield I2C_S_ARBL.
bogdanm	82:6473597d706e	725	#define BF_I2C_S_ARBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_ARBL), uint8_t) & BM_I2C_S_ARBL)
bogdanm	82:6473597d706e	726
bogdanm	82:6473597d706e	727	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	728	//! @brief Set the ARBL field to a new value.
bogdanm	82:6473597d706e	729	#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
bogdanm	82:6473597d706e	730	#endif
bogdanm	82:6473597d706e	731	//@}
bogdanm	82:6473597d706e	732
bogdanm	82:6473597d706e	733	/*!
bogdanm	82:6473597d706e	734	* @name Register I2C_S, field BUSY[5] (RO)
bogdanm	82:6473597d706e	735	*
bogdanm	82:6473597d706e	736	* Indicates the status of the bus regardless of slave or master mode. This bit
bogdanm	82:6473597d706e	737	* is set when a START signal is detected and cleared when a STOP signal is
bogdanm	82:6473597d706e	738	* detected.
bogdanm	82:6473597d706e	739	*
bogdanm	82:6473597d706e	740	* Values:
bogdanm	82:6473597d706e	741	* - 0 - Bus is idle
bogdanm	82:6473597d706e	742	* - 1 - Bus is busy
bogdanm	82:6473597d706e	743	*/
bogdanm	82:6473597d706e	744	//@{
bogdanm	82:6473597d706e	745	#define BP_I2C_S_BUSY (5U) //!< Bit position for I2C_S_BUSY.
bogdanm	82:6473597d706e	746	#define BM_I2C_S_BUSY (0x20U) //!< Bit mask for I2C_S_BUSY.
bogdanm	82:6473597d706e	747	#define BS_I2C_S_BUSY (1U) //!< Bit field size in bits for I2C_S_BUSY.
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	750	//! @brief Read current value of the I2C_S_BUSY field.
bogdanm	82:6473597d706e	751	#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
bogdanm	82:6473597d706e	752	#endif
bogdanm	82:6473597d706e	753	//@}
bogdanm	82:6473597d706e	754
bogdanm	82:6473597d706e	755	/*!
bogdanm	82:6473597d706e	756	* @name Register I2C_S, field IAAS[6] (RW)
bogdanm	82:6473597d706e	757	*
bogdanm	82:6473597d706e	758	* This bit is set by one of the following conditions: The calling address
bogdanm	82:6473597d706e	759	* matches the programmed primary slave address in the A1 register, or matches the
bogdanm	82:6473597d706e	760	* range address in the RA register (which must be set to a nonzero value and under
bogdanm	82:6473597d706e	761	* the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
bogdanm	82:6473597d706e	762	* received. SMB[SIICAEN] is set and the calling address matches the second programmed
bogdanm	82:6473597d706e	763	* slave address. ALERTEN is set and an SMBus alert response address is received
bogdanm	82:6473597d706e	764	* RMEN is set and an address is received that is within the range between the
bogdanm	82:6473597d706e	765	* values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
bogdanm	82:6473597d706e	766	* check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
bogdanm	82:6473597d706e	767	* value clears this bit.
bogdanm	82:6473597d706e	768	*
bogdanm	82:6473597d706e	769	* Values:
bogdanm	82:6473597d706e	770	* - 0 - Not addressed
bogdanm	82:6473597d706e	771	* - 1 - Addressed as a slave
bogdanm	82:6473597d706e	772	*/
bogdanm	82:6473597d706e	773	//@{
bogdanm	82:6473597d706e	774	#define BP_I2C_S_IAAS (6U) //!< Bit position for I2C_S_IAAS.
bogdanm	82:6473597d706e	775	#define BM_I2C_S_IAAS (0x40U) //!< Bit mask for I2C_S_IAAS.
bogdanm	82:6473597d706e	776	#define BS_I2C_S_IAAS (1U) //!< Bit field size in bits for I2C_S_IAAS.
bogdanm	82:6473597d706e	777
bogdanm	82:6473597d706e	778	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	779	//! @brief Read current value of the I2C_S_IAAS field.
bogdanm	82:6473597d706e	780	#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
bogdanm	82:6473597d706e	781	#endif
bogdanm	82:6473597d706e	782
bogdanm	82:6473597d706e	783	//! @brief Format value for bitfield I2C_S_IAAS.
bogdanm	82:6473597d706e	784	#define BF_I2C_S_IAAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IAAS), uint8_t) & BM_I2C_S_IAAS)
bogdanm	82:6473597d706e	785
bogdanm	82:6473597d706e	786	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	787	//! @brief Set the IAAS field to a new value.
bogdanm	82:6473597d706e	788	#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
bogdanm	82:6473597d706e	789	#endif
bogdanm	82:6473597d706e	790	//@}
bogdanm	82:6473597d706e	791
bogdanm	82:6473597d706e	792	/*!
bogdanm	82:6473597d706e	793	* @name Register I2C_S, field TCF[7] (RO)
bogdanm	82:6473597d706e	794	*
bogdanm	82:6473597d706e	795	* Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
bogdanm	82:6473597d706e	796	* This bit is valid only during or immediately following a transfer to or from
bogdanm	82:6473597d706e	797	* the I2C module. TCF is cleared by reading the I2C data register in receive mode
bogdanm	82:6473597d706e	798	* or by writing to the I2C data register in transmit mode.
bogdanm	82:6473597d706e	799	*
bogdanm	82:6473597d706e	800	* Values:
bogdanm	82:6473597d706e	801	* - 0 - Transfer in progress
bogdanm	82:6473597d706e	802	* - 1 - Transfer complete
bogdanm	82:6473597d706e	803	*/
bogdanm	82:6473597d706e	804	//@{
bogdanm	82:6473597d706e	805	#define BP_I2C_S_TCF (7U) //!< Bit position for I2C_S_TCF.
bogdanm	82:6473597d706e	806	#define BM_I2C_S_TCF (0x80U) //!< Bit mask for I2C_S_TCF.
bogdanm	82:6473597d706e	807	#define BS_I2C_S_TCF (1U) //!< Bit field size in bits for I2C_S_TCF.
bogdanm	82:6473597d706e	808
bogdanm	82:6473597d706e	809	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	810	//! @brief Read current value of the I2C_S_TCF field.
bogdanm	82:6473597d706e	811	#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
bogdanm	82:6473597d706e	812	#endif
bogdanm	82:6473597d706e	813	//@}
bogdanm	82:6473597d706e	814
bogdanm	82:6473597d706e	815	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	816	// HW_I2C_D - I2C Data I/O register
bogdanm	82:6473597d706e	817	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	818
bogdanm	82:6473597d706e	819	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	820	/*!
bogdanm	82:6473597d706e	821	* @brief HW_I2C_D - I2C Data I/O register (RW)
bogdanm	82:6473597d706e	822	*
bogdanm	82:6473597d706e	823	* Reset value: 0x00U
bogdanm	82:6473597d706e	824	*/
bogdanm	82:6473597d706e	825	typedef union _hw_i2c_d
bogdanm	82:6473597d706e	826	{
bogdanm	82:6473597d706e	827	uint8_t U;
bogdanm	82:6473597d706e	828	struct _hw_i2c_d_bitfields
bogdanm	82:6473597d706e	829	{
bogdanm	82:6473597d706e	830	uint8_t DATA : 8; //!< [7:0] Data
bogdanm	82:6473597d706e	831	} B;
bogdanm	82:6473597d706e	832	} hw_i2c_d_t;
bogdanm	82:6473597d706e	833	#endif
bogdanm	82:6473597d706e	834
bogdanm	82:6473597d706e	835	/*!
bogdanm	82:6473597d706e	836	* @name Constants and macros for entire I2C_D register
bogdanm	82:6473597d706e	837	*/
bogdanm	82:6473597d706e	838	//@{
bogdanm	82:6473597d706e	839	#define HW_I2C_D_ADDR(x) (REGS_I2C_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	840
bogdanm	82:6473597d706e	841	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	842	#define HW_I2C_D(x) ((__IO hw_i2c_d_t ) HW_I2C_D_ADDR(x))
bogdanm	82:6473597d706e	843	#define HW_I2C_D_RD(x) (HW_I2C_D(x).U)
bogdanm	82:6473597d706e	844	#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v))
bogdanm	82:6473597d706e	845	#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) \| (v)))
bogdanm	82:6473597d706e	846	#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
bogdanm	82:6473597d706e	847	#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v)))
bogdanm	82:6473597d706e	848	#endif
bogdanm	82:6473597d706e	849	//@}
bogdanm	82:6473597d706e	850
bogdanm	82:6473597d706e	851	/*
bogdanm	82:6473597d706e	852	* Constants & macros for individual I2C_D bitfields
bogdanm	82:6473597d706e	853	*/
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	/*!
bogdanm	82:6473597d706e	856	* @name Register I2C_D, field DATA[7:0] (RW)
bogdanm	82:6473597d706e	857	*
bogdanm	82:6473597d706e	858	* In master transmit mode, when data is written to this register, a data
bogdanm	82:6473597d706e	859	* transfer is initiated. The most significant bit is sent first. In master receive
bogdanm	82:6473597d706e	860	* mode, reading this register initiates receiving of the next byte of data. When
bogdanm	82:6473597d706e	861	* making the transition out of master receive mode, switch the I2C mode before
bogdanm	82:6473597d706e	862	* reading the Data register to prevent an inadvertent initiation of a master
bogdanm	82:6473597d706e	863	* receive data transfer. In slave mode, the same functions are available after an
bogdanm	82:6473597d706e	864	* address match occurs. The C1[TX] bit must correctly reflect the desired direction
bogdanm	82:6473597d706e	865	* of transfer in master and slave modes for the transmission to begin. For
bogdanm	82:6473597d706e	866	* example, if the I2C module is configured for master transmit but a master receive
bogdanm	82:6473597d706e	867	* is desired, reading the Data register does not initiate the receive. Reading
bogdanm	82:6473597d706e	868	* the Data register returns the last byte received while the I2C module is
bogdanm	82:6473597d706e	869	* configured in master receive or slave receive mode. The Data register does not
bogdanm	82:6473597d706e	870	* reflect every byte that is transmitted on the I2C bus, and neither can software
bogdanm	82:6473597d706e	871	* verify that a byte has been written to the Data register correctly by reading it
bogdanm	82:6473597d706e	872	* back. In master transmit mode, the first byte of data written to the Data
bogdanm	82:6473597d706e	873	* register following assertion of MST (start bit) or assertion of RSTA (repeated
bogdanm	82:6473597d706e	874	* start bit) is used for the address transfer and must consist of the calling
bogdanm	82:6473597d706e	875	* address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
bogdanm	82:6473597d706e	876	*/
bogdanm	82:6473597d706e	877	//@{
bogdanm	82:6473597d706e	878	#define BP_I2C_D_DATA (0U) //!< Bit position for I2C_D_DATA.
bogdanm	82:6473597d706e	879	#define BM_I2C_D_DATA (0xFFU) //!< Bit mask for I2C_D_DATA.
bogdanm	82:6473597d706e	880	#define BS_I2C_D_DATA (8U) //!< Bit field size in bits for I2C_D_DATA.
bogdanm	82:6473597d706e	881
bogdanm	82:6473597d706e	882	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	883	//! @brief Read current value of the I2C_D_DATA field.
bogdanm	82:6473597d706e	884	#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U)
bogdanm	82:6473597d706e	885	#endif
bogdanm	82:6473597d706e	886
bogdanm	82:6473597d706e	887	//! @brief Format value for bitfield I2C_D_DATA.
bogdanm	82:6473597d706e	888	#define BF_I2C_D_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_D_DATA), uint8_t) & BM_I2C_D_DATA)
bogdanm	82:6473597d706e	889
bogdanm	82:6473597d706e	890	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	891	//! @brief Set the DATA field to a new value.
bogdanm	82:6473597d706e	892	#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v))
bogdanm	82:6473597d706e	893	#endif
bogdanm	82:6473597d706e	894	//@}
bogdanm	82:6473597d706e	895
bogdanm	82:6473597d706e	896	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	897	// HW_I2C_C2 - I2C Control Register 2
bogdanm	82:6473597d706e	898	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	899
bogdanm	82:6473597d706e	900	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	901	/*!
bogdanm	82:6473597d706e	902	* @brief HW_I2C_C2 - I2C Control Register 2 (RW)
bogdanm	82:6473597d706e	903	*
bogdanm	82:6473597d706e	904	* Reset value: 0x00U
bogdanm	82:6473597d706e	905	*/
bogdanm	82:6473597d706e	906	typedef union _hw_i2c_c2
bogdanm	82:6473597d706e	907	{
bogdanm	82:6473597d706e	908	uint8_t U;
bogdanm	82:6473597d706e	909	struct _hw_i2c_c2_bitfields
bogdanm	82:6473597d706e	910	{
bogdanm	82:6473597d706e	911	uint8_t AD : 3; //!< [2:0] Slave Address
bogdanm	82:6473597d706e	912	uint8_t RMEN : 1; //!< [3] Range Address Matching Enable
bogdanm	82:6473597d706e	913	uint8_t SBRC : 1; //!< [4] Slave Baud Rate Control
bogdanm	82:6473597d706e	914	uint8_t HDRS : 1; //!< [5] High Drive Select
bogdanm	82:6473597d706e	915	uint8_t ADEXT : 1; //!< [6] Address Extension
bogdanm	82:6473597d706e	916	uint8_t GCAEN : 1; //!< [7] General Call Address Enable
bogdanm	82:6473597d706e	917	} B;
bogdanm	82:6473597d706e	918	} hw_i2c_c2_t;
bogdanm	82:6473597d706e	919	#endif
bogdanm	82:6473597d706e	920
bogdanm	82:6473597d706e	921	/*!
bogdanm	82:6473597d706e	922	* @name Constants and macros for entire I2C_C2 register
bogdanm	82:6473597d706e	923	*/
bogdanm	82:6473597d706e	924	//@{
bogdanm	82:6473597d706e	925	#define HW_I2C_C2_ADDR(x) (REGS_I2C_BASE(x) + 0x5U)
bogdanm	82:6473597d706e	926
bogdanm	82:6473597d706e	927	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	928	#define HW_I2C_C2(x) ((__IO hw_i2c_c2_t ) HW_I2C_C2_ADDR(x))
bogdanm	82:6473597d706e	929	#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U)
bogdanm	82:6473597d706e	930	#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v))
bogdanm	82:6473597d706e	931	#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) \| (v)))
bogdanm	82:6473597d706e	932	#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	933	#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	934	#endif
bogdanm	82:6473597d706e	935	//@}
bogdanm	82:6473597d706e	936
bogdanm	82:6473597d706e	937	/*
bogdanm	82:6473597d706e	938	* Constants & macros for individual I2C_C2 bitfields
bogdanm	82:6473597d706e	939	*/
bogdanm	82:6473597d706e	940
bogdanm	82:6473597d706e	941	/*!
bogdanm	82:6473597d706e	942	* @name Register I2C_C2, field AD[2:0] (RW)
bogdanm	82:6473597d706e	943	*
bogdanm	82:6473597d706e	944	* Contains the upper three bits of the slave address in the 10-bit address
bogdanm	82:6473597d706e	945	* scheme. This field is valid only while the ADEXT bit is set.
bogdanm	82:6473597d706e	946	*/
bogdanm	82:6473597d706e	947	//@{
bogdanm	82:6473597d706e	948	#define BP_I2C_C2_AD (0U) //!< Bit position for I2C_C2_AD.
bogdanm	82:6473597d706e	949	#define BM_I2C_C2_AD (0x07U) //!< Bit mask for I2C_C2_AD.
bogdanm	82:6473597d706e	950	#define BS_I2C_C2_AD (3U) //!< Bit field size in bits for I2C_C2_AD.
bogdanm	82:6473597d706e	951
bogdanm	82:6473597d706e	952	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	953	//! @brief Read current value of the I2C_C2_AD field.
bogdanm	82:6473597d706e	954	#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD)
bogdanm	82:6473597d706e	955	#endif
bogdanm	82:6473597d706e	956
bogdanm	82:6473597d706e	957	//! @brief Format value for bitfield I2C_C2_AD.
bogdanm	82:6473597d706e	958	#define BF_I2C_C2_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_AD), uint8_t) & BM_I2C_C2_AD)
bogdanm	82:6473597d706e	959
bogdanm	82:6473597d706e	960	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	961	//! @brief Set the AD field to a new value.
bogdanm	82:6473597d706e	962	#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) \| BF_I2C_C2_AD(v)))
bogdanm	82:6473597d706e	963	#endif
bogdanm	82:6473597d706e	964	//@}
bogdanm	82:6473597d706e	965
bogdanm	82:6473597d706e	966	/*!
bogdanm	82:6473597d706e	967	* @name Register I2C_C2, field RMEN[3] (RW)
bogdanm	82:6473597d706e	968	*
bogdanm	82:6473597d706e	969	* This bit controls the slave address matching for addresses between the values
bogdanm	82:6473597d706e	970	* of the A1 and RA registers. When this bit is set, a slave address matching
bogdanm	82:6473597d706e	971	* occurs for any address greater than the value of the A1 register and less than
bogdanm	82:6473597d706e	972	* or equal to the value of the RA register.
bogdanm	82:6473597d706e	973	*
bogdanm	82:6473597d706e	974	* Values:
bogdanm	82:6473597d706e	975	* - 0 - Range mode disabled. No address matching occurs for an address within
bogdanm	82:6473597d706e	976	* the range of values of the A1 and RA registers.
bogdanm	82:6473597d706e	977	* - 1 - Range mode enabled. Address matching occurs when a slave receives an
bogdanm	82:6473597d706e	978	* address within the range of values of the A1 and RA registers.
bogdanm	82:6473597d706e	979	*/
bogdanm	82:6473597d706e	980	//@{
bogdanm	82:6473597d706e	981	#define BP_I2C_C2_RMEN (3U) //!< Bit position for I2C_C2_RMEN.
bogdanm	82:6473597d706e	982	#define BM_I2C_C2_RMEN (0x08U) //!< Bit mask for I2C_C2_RMEN.
bogdanm	82:6473597d706e	983	#define BS_I2C_C2_RMEN (1U) //!< Bit field size in bits for I2C_C2_RMEN.
bogdanm	82:6473597d706e	984
bogdanm	82:6473597d706e	985	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	986	//! @brief Read current value of the I2C_C2_RMEN field.
bogdanm	82:6473597d706e	987	#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
bogdanm	82:6473597d706e	988	#endif
bogdanm	82:6473597d706e	989
bogdanm	82:6473597d706e	990	//! @brief Format value for bitfield I2C_C2_RMEN.
bogdanm	82:6473597d706e	991	#define BF_I2C_C2_RMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_RMEN), uint8_t) & BM_I2C_C2_RMEN)
bogdanm	82:6473597d706e	992
bogdanm	82:6473597d706e	993	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	994	//! @brief Set the RMEN field to a new value.
bogdanm	82:6473597d706e	995	#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
bogdanm	82:6473597d706e	996	#endif
bogdanm	82:6473597d706e	997	//@}
bogdanm	82:6473597d706e	998
bogdanm	82:6473597d706e	999	/*!
bogdanm	82:6473597d706e	1000	* @name Register I2C_C2, field SBRC[4] (RW)
bogdanm	82:6473597d706e	1001	*
bogdanm	82:6473597d706e	1002	* Enables independent slave mode baud rate at maximum frequency, which forces
bogdanm	82:6473597d706e	1003	* clock stretching on SCL in very fast I2C modes. To a slave, an example of a
bogdanm	82:6473597d706e	1004	* "very fast" mode is when the master transfers at 40 kbit/s but the slave can
bogdanm	82:6473597d706e	1005	* capture the master's data at only 10 kbit/s.
bogdanm	82:6473597d706e	1006	*
bogdanm	82:6473597d706e	1007	* Values:
bogdanm	82:6473597d706e	1008	* - 0 - The slave baud rate follows the master baud rate and clock stretching
bogdanm	82:6473597d706e	1009	* may occur
bogdanm	82:6473597d706e	1010	* - 1 - Slave baud rate is independent of the master baud rate
bogdanm	82:6473597d706e	1011	*/
bogdanm	82:6473597d706e	1012	//@{
bogdanm	82:6473597d706e	1013	#define BP_I2C_C2_SBRC (4U) //!< Bit position for I2C_C2_SBRC.
bogdanm	82:6473597d706e	1014	#define BM_I2C_C2_SBRC (0x10U) //!< Bit mask for I2C_C2_SBRC.
bogdanm	82:6473597d706e	1015	#define BS_I2C_C2_SBRC (1U) //!< Bit field size in bits for I2C_C2_SBRC.
bogdanm	82:6473597d706e	1016
bogdanm	82:6473597d706e	1017	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1018	//! @brief Read current value of the I2C_C2_SBRC field.
bogdanm	82:6473597d706e	1019	#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
bogdanm	82:6473597d706e	1020	#endif
bogdanm	82:6473597d706e	1021
bogdanm	82:6473597d706e	1022	//! @brief Format value for bitfield I2C_C2_SBRC.
bogdanm	82:6473597d706e	1023	#define BF_I2C_C2_SBRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_SBRC), uint8_t) & BM_I2C_C2_SBRC)
bogdanm	82:6473597d706e	1024
bogdanm	82:6473597d706e	1025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1026	//! @brief Set the SBRC field to a new value.
bogdanm	82:6473597d706e	1027	#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
bogdanm	82:6473597d706e	1028	#endif
bogdanm	82:6473597d706e	1029	//@}
bogdanm	82:6473597d706e	1030
bogdanm	82:6473597d706e	1031	/*!
bogdanm	82:6473597d706e	1032	* @name Register I2C_C2, field HDRS[5] (RW)
bogdanm	82:6473597d706e	1033	*
bogdanm	82:6473597d706e	1034	* Controls the drive capability of the I2C pads.
bogdanm	82:6473597d706e	1035	*
bogdanm	82:6473597d706e	1036	* Values:
bogdanm	82:6473597d706e	1037	* - 0 - Normal drive mode
bogdanm	82:6473597d706e	1038	* - 1 - High drive mode
bogdanm	82:6473597d706e	1039	*/
bogdanm	82:6473597d706e	1040	//@{
bogdanm	82:6473597d706e	1041	#define BP_I2C_C2_HDRS (5U) //!< Bit position for I2C_C2_HDRS.
bogdanm	82:6473597d706e	1042	#define BM_I2C_C2_HDRS (0x20U) //!< Bit mask for I2C_C2_HDRS.
bogdanm	82:6473597d706e	1043	#define BS_I2C_C2_HDRS (1U) //!< Bit field size in bits for I2C_C2_HDRS.
bogdanm	82:6473597d706e	1044
bogdanm	82:6473597d706e	1045	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1046	//! @brief Read current value of the I2C_C2_HDRS field.
bogdanm	82:6473597d706e	1047	#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
bogdanm	82:6473597d706e	1048	#endif
bogdanm	82:6473597d706e	1049
bogdanm	82:6473597d706e	1050	//! @brief Format value for bitfield I2C_C2_HDRS.
bogdanm	82:6473597d706e	1051	#define BF_I2C_C2_HDRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_HDRS), uint8_t) & BM_I2C_C2_HDRS)
bogdanm	82:6473597d706e	1052
bogdanm	82:6473597d706e	1053	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1054	//! @brief Set the HDRS field to a new value.
bogdanm	82:6473597d706e	1055	#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
bogdanm	82:6473597d706e	1056	#endif
bogdanm	82:6473597d706e	1057	//@}
bogdanm	82:6473597d706e	1058
bogdanm	82:6473597d706e	1059	/*!
bogdanm	82:6473597d706e	1060	* @name Register I2C_C2, field ADEXT[6] (RW)
bogdanm	82:6473597d706e	1061	*
bogdanm	82:6473597d706e	1062	* Controls the number of bits used for the slave address.
bogdanm	82:6473597d706e	1063	*
bogdanm	82:6473597d706e	1064	* Values:
bogdanm	82:6473597d706e	1065	* - 0 - 7-bit address scheme
bogdanm	82:6473597d706e	1066	* - 1 - 10-bit address scheme
bogdanm	82:6473597d706e	1067	*/
bogdanm	82:6473597d706e	1068	//@{
bogdanm	82:6473597d706e	1069	#define BP_I2C_C2_ADEXT (6U) //!< Bit position for I2C_C2_ADEXT.
bogdanm	82:6473597d706e	1070	#define BM_I2C_C2_ADEXT (0x40U) //!< Bit mask for I2C_C2_ADEXT.
bogdanm	82:6473597d706e	1071	#define BS_I2C_C2_ADEXT (1U) //!< Bit field size in bits for I2C_C2_ADEXT.
bogdanm	82:6473597d706e	1072
bogdanm	82:6473597d706e	1073	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1074	//! @brief Read current value of the I2C_C2_ADEXT field.
bogdanm	82:6473597d706e	1075	#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
bogdanm	82:6473597d706e	1076	#endif
bogdanm	82:6473597d706e	1077
bogdanm	82:6473597d706e	1078	//! @brief Format value for bitfield I2C_C2_ADEXT.
bogdanm	82:6473597d706e	1079	#define BF_I2C_C2_ADEXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_ADEXT), uint8_t) & BM_I2C_C2_ADEXT)
bogdanm	82:6473597d706e	1080
bogdanm	82:6473597d706e	1081	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1082	//! @brief Set the ADEXT field to a new value.
bogdanm	82:6473597d706e	1083	#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
bogdanm	82:6473597d706e	1084	#endif
bogdanm	82:6473597d706e	1085	//@}
bogdanm	82:6473597d706e	1086
bogdanm	82:6473597d706e	1087	/*!
bogdanm	82:6473597d706e	1088	* @name Register I2C_C2, field GCAEN[7] (RW)
bogdanm	82:6473597d706e	1089	*
bogdanm	82:6473597d706e	1090	* Enables general call address.
bogdanm	82:6473597d706e	1091	*
bogdanm	82:6473597d706e	1092	* Values:
bogdanm	82:6473597d706e	1093	* - 0 - Disabled
bogdanm	82:6473597d706e	1094	* - 1 - Enabled
bogdanm	82:6473597d706e	1095	*/
bogdanm	82:6473597d706e	1096	//@{
bogdanm	82:6473597d706e	1097	#define BP_I2C_C2_GCAEN (7U) //!< Bit position for I2C_C2_GCAEN.
bogdanm	82:6473597d706e	1098	#define BM_I2C_C2_GCAEN (0x80U) //!< Bit mask for I2C_C2_GCAEN.
bogdanm	82:6473597d706e	1099	#define BS_I2C_C2_GCAEN (1U) //!< Bit field size in bits for I2C_C2_GCAEN.
bogdanm	82:6473597d706e	1100
bogdanm	82:6473597d706e	1101	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1102	//! @brief Read current value of the I2C_C2_GCAEN field.
bogdanm	82:6473597d706e	1103	#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
bogdanm	82:6473597d706e	1104	#endif
bogdanm	82:6473597d706e	1105
bogdanm	82:6473597d706e	1106	//! @brief Format value for bitfield I2C_C2_GCAEN.
bogdanm	82:6473597d706e	1107	#define BF_I2C_C2_GCAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_GCAEN), uint8_t) & BM_I2C_C2_GCAEN)
bogdanm	82:6473597d706e	1108
bogdanm	82:6473597d706e	1109	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1110	//! @brief Set the GCAEN field to a new value.
bogdanm	82:6473597d706e	1111	#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
bogdanm	82:6473597d706e	1112	#endif
bogdanm	82:6473597d706e	1113	//@}
bogdanm	82:6473597d706e	1114
bogdanm	82:6473597d706e	1115	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1116	// HW_I2C_FLT - I2C Programmable Input Glitch Filter register
bogdanm	82:6473597d706e	1117	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1118
bogdanm	82:6473597d706e	1119	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1120	/*!
bogdanm	82:6473597d706e	1121	* @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
bogdanm	82:6473597d706e	1122	*
bogdanm	82:6473597d706e	1123	* Reset value: 0x00U
bogdanm	82:6473597d706e	1124	*/
bogdanm	82:6473597d706e	1125	typedef union _hw_i2c_flt
bogdanm	82:6473597d706e	1126	{
bogdanm	82:6473597d706e	1127	uint8_t U;
bogdanm	82:6473597d706e	1128	struct _hw_i2c_flt_bitfields
bogdanm	82:6473597d706e	1129	{
bogdanm	82:6473597d706e	1130	uint8_t FLT : 4; //!< [3:0] I2C Programmable Filter Factor
bogdanm	82:6473597d706e	1131	uint8_t STARTF : 1; //!< [4] I2C Bus Start Detect Flag
bogdanm	82:6473597d706e	1132	uint8_t SSIE : 1; //!< [5] I2C Bus Stop or Start Interrupt Enable
bogdanm	82:6473597d706e	1133	uint8_t STOPF : 1; //!< [6] I2C Bus Stop Detect Flag
bogdanm	82:6473597d706e	1134	uint8_t SHEN : 1; //!< [7] Stop Hold Enable
bogdanm	82:6473597d706e	1135	} B;
bogdanm	82:6473597d706e	1136	} hw_i2c_flt_t;
bogdanm	82:6473597d706e	1137	#endif
bogdanm	82:6473597d706e	1138
bogdanm	82:6473597d706e	1139	/*!
bogdanm	82:6473597d706e	1140	* @name Constants and macros for entire I2C_FLT register
bogdanm	82:6473597d706e	1141	*/
bogdanm	82:6473597d706e	1142	//@{
bogdanm	82:6473597d706e	1143	#define HW_I2C_FLT_ADDR(x) (REGS_I2C_BASE(x) + 0x6U)
bogdanm	82:6473597d706e	1144
bogdanm	82:6473597d706e	1145	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1146	#define HW_I2C_FLT(x) ((__IO hw_i2c_flt_t ) HW_I2C_FLT_ADDR(x))
bogdanm	82:6473597d706e	1147	#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U)
bogdanm	82:6473597d706e	1148	#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v))
bogdanm	82:6473597d706e	1149	#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) \| (v)))
bogdanm	82:6473597d706e	1150	#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1151	#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1152	#endif
bogdanm	82:6473597d706e	1153	//@}
bogdanm	82:6473597d706e	1154
bogdanm	82:6473597d706e	1155	/*
bogdanm	82:6473597d706e	1156	* Constants & macros for individual I2C_FLT bitfields
bogdanm	82:6473597d706e	1157	*/
bogdanm	82:6473597d706e	1158
bogdanm	82:6473597d706e	1159	/*!
bogdanm	82:6473597d706e	1160	* @name Register I2C_FLT, field FLT[3:0] (RW)
bogdanm	82:6473597d706e	1161	*
bogdanm	82:6473597d706e	1162	* Controls the width of the glitch, in terms of I2C module clock cycles, that
bogdanm	82:6473597d706e	1163	* the filter must absorb. For any glitch whose size is less than or equal to this
bogdanm	82:6473597d706e	1164	* width setting, the filter does not allow the glitch to pass.
bogdanm	82:6473597d706e	1165	*
bogdanm	82:6473597d706e	1166	* Values:
bogdanm	82:6473597d706e	1167	* - 0 - No filter/bypass
bogdanm	82:6473597d706e	1168	*/
bogdanm	82:6473597d706e	1169	//@{
bogdanm	82:6473597d706e	1170	#define BP_I2C_FLT_FLT (0U) //!< Bit position for I2C_FLT_FLT.
bogdanm	82:6473597d706e	1171	#define BM_I2C_FLT_FLT (0x0FU) //!< Bit mask for I2C_FLT_FLT.
bogdanm	82:6473597d706e	1172	#define BS_I2C_FLT_FLT (4U) //!< Bit field size in bits for I2C_FLT_FLT.
bogdanm	82:6473597d706e	1173
bogdanm	82:6473597d706e	1174	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1175	//! @brief Read current value of the I2C_FLT_FLT field.
bogdanm	82:6473597d706e	1176	#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT)
bogdanm	82:6473597d706e	1177	#endif
bogdanm	82:6473597d706e	1178
bogdanm	82:6473597d706e	1179	//! @brief Format value for bitfield I2C_FLT_FLT.
bogdanm	82:6473597d706e	1180	#define BF_I2C_FLT_FLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_FLT), uint8_t) & BM_I2C_FLT_FLT)
bogdanm	82:6473597d706e	1181
bogdanm	82:6473597d706e	1182	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1183	//! @brief Set the FLT field to a new value.
bogdanm	82:6473597d706e	1184	#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) \| BF_I2C_FLT_FLT(v)))
bogdanm	82:6473597d706e	1185	#endif
bogdanm	82:6473597d706e	1186	//@}
bogdanm	82:6473597d706e	1187
bogdanm	82:6473597d706e	1188	/*!
bogdanm	82:6473597d706e	1189	* @name Register I2C_FLT, field STARTF[4] (W1C)
bogdanm	82:6473597d706e	1190	*
bogdanm	82:6473597d706e	1191	* Hardware sets this bit when the I2C bus's start status is detected. The
bogdanm	82:6473597d706e	1192	* STARTF bit must be cleared by writing 1 to it.
bogdanm	82:6473597d706e	1193	*
bogdanm	82:6473597d706e	1194	* Values:
bogdanm	82:6473597d706e	1195	* - 0 - No start happens on I2C bus
bogdanm	82:6473597d706e	1196	* - 1 - Start detected on I2C bus
bogdanm	82:6473597d706e	1197	*/
bogdanm	82:6473597d706e	1198	//@{
bogdanm	82:6473597d706e	1199	#define BP_I2C_FLT_STARTF (4U) //!< Bit position for I2C_FLT_STARTF.
bogdanm	82:6473597d706e	1200	#define BM_I2C_FLT_STARTF (0x10U) //!< Bit mask for I2C_FLT_STARTF.
bogdanm	82:6473597d706e	1201	#define BS_I2C_FLT_STARTF (1U) //!< Bit field size in bits for I2C_FLT_STARTF.
bogdanm	82:6473597d706e	1202
bogdanm	82:6473597d706e	1203	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1204	//! @brief Read current value of the I2C_FLT_STARTF field.
bogdanm	82:6473597d706e	1205	#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
bogdanm	82:6473597d706e	1206	#endif
bogdanm	82:6473597d706e	1207
bogdanm	82:6473597d706e	1208	//! @brief Format value for bitfield I2C_FLT_STARTF.
bogdanm	82:6473597d706e	1209	#define BF_I2C_FLT_STARTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STARTF), uint8_t) & BM_I2C_FLT_STARTF)
bogdanm	82:6473597d706e	1210
bogdanm	82:6473597d706e	1211	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1212	//! @brief Set the STARTF field to a new value.
bogdanm	82:6473597d706e	1213	#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
bogdanm	82:6473597d706e	1214	#endif
bogdanm	82:6473597d706e	1215	//@}
bogdanm	82:6473597d706e	1216
bogdanm	82:6473597d706e	1217	/*!
bogdanm	82:6473597d706e	1218	* @name Register I2C_FLT, field SSIE[5] (RW)
bogdanm	82:6473597d706e	1219	*
bogdanm	82:6473597d706e	1220	* This bit enables the interrupt for I2C bus stop or start detection. To clear
bogdanm	82:6473597d706e	1221	* the I2C bus stop or start detection interrupt: In the interrupt service
bogdanm	82:6473597d706e	1222	* routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
bogdanm	82:6473597d706e	1223	* IICIF bit in the status register. If this sequence is reversed, the IICIF bit
bogdanm	82:6473597d706e	1224	* is asserted again.
bogdanm	82:6473597d706e	1225	*
bogdanm	82:6473597d706e	1226	* Values:
bogdanm	82:6473597d706e	1227	* - 0 - Stop or start detection interrupt is disabled
bogdanm	82:6473597d706e	1228	* - 1 - Stop or start detection interrupt is enabled
bogdanm	82:6473597d706e	1229	*/
bogdanm	82:6473597d706e	1230	//@{
bogdanm	82:6473597d706e	1231	#define BP_I2C_FLT_SSIE (5U) //!< Bit position for I2C_FLT_SSIE.
bogdanm	82:6473597d706e	1232	#define BM_I2C_FLT_SSIE (0x20U) //!< Bit mask for I2C_FLT_SSIE.
bogdanm	82:6473597d706e	1233	#define BS_I2C_FLT_SSIE (1U) //!< Bit field size in bits for I2C_FLT_SSIE.
bogdanm	82:6473597d706e	1234
bogdanm	82:6473597d706e	1235	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1236	//! @brief Read current value of the I2C_FLT_SSIE field.
bogdanm	82:6473597d706e	1237	#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
bogdanm	82:6473597d706e	1238	#endif
bogdanm	82:6473597d706e	1239
bogdanm	82:6473597d706e	1240	//! @brief Format value for bitfield I2C_FLT_SSIE.
bogdanm	82:6473597d706e	1241	#define BF_I2C_FLT_SSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SSIE), uint8_t) & BM_I2C_FLT_SSIE)
bogdanm	82:6473597d706e	1242
bogdanm	82:6473597d706e	1243	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1244	//! @brief Set the SSIE field to a new value.
bogdanm	82:6473597d706e	1245	#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
bogdanm	82:6473597d706e	1246	#endif
bogdanm	82:6473597d706e	1247	//@}
bogdanm	82:6473597d706e	1248
bogdanm	82:6473597d706e	1249	/*!
bogdanm	82:6473597d706e	1250	* @name Register I2C_FLT, field STOPF[6] (W1C)
bogdanm	82:6473597d706e	1251	*
bogdanm	82:6473597d706e	1252	* Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
bogdanm	82:6473597d706e	1253	* bit must be cleared by writing 1 to it.
bogdanm	82:6473597d706e	1254	*
bogdanm	82:6473597d706e	1255	* Values:
bogdanm	82:6473597d706e	1256	* - 0 - No stop happens on I2C bus
bogdanm	82:6473597d706e	1257	* - 1 - Stop detected on I2C bus
bogdanm	82:6473597d706e	1258	*/
bogdanm	82:6473597d706e	1259	//@{
bogdanm	82:6473597d706e	1260	#define BP_I2C_FLT_STOPF (6U) //!< Bit position for I2C_FLT_STOPF.
bogdanm	82:6473597d706e	1261	#define BM_I2C_FLT_STOPF (0x40U) //!< Bit mask for I2C_FLT_STOPF.
bogdanm	82:6473597d706e	1262	#define BS_I2C_FLT_STOPF (1U) //!< Bit field size in bits for I2C_FLT_STOPF.
bogdanm	82:6473597d706e	1263
bogdanm	82:6473597d706e	1264	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1265	//! @brief Read current value of the I2C_FLT_STOPF field.
bogdanm	82:6473597d706e	1266	#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
bogdanm	82:6473597d706e	1267	#endif
bogdanm	82:6473597d706e	1268
bogdanm	82:6473597d706e	1269	//! @brief Format value for bitfield I2C_FLT_STOPF.
bogdanm	82:6473597d706e	1270	#define BF_I2C_FLT_STOPF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STOPF), uint8_t) & BM_I2C_FLT_STOPF)
bogdanm	82:6473597d706e	1271
bogdanm	82:6473597d706e	1272	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1273	//! @brief Set the STOPF field to a new value.
bogdanm	82:6473597d706e	1274	#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
bogdanm	82:6473597d706e	1275	#endif
bogdanm	82:6473597d706e	1276	//@}
bogdanm	82:6473597d706e	1277
bogdanm	82:6473597d706e	1278	/*!
bogdanm	82:6473597d706e	1279	* @name Register I2C_FLT, field SHEN[7] (RW)
bogdanm	82:6473597d706e	1280	*
bogdanm	82:6473597d706e	1281	* Set this bit to hold off entry to stop mode when any data transmission or
bogdanm	82:6473597d706e	1282	* reception is occurring. The following scenario explains the holdoff
bogdanm	82:6473597d706e	1283	* functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
bogdanm	82:6473597d706e	1284	* to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
bogdanm	82:6473597d706e	1285	* byte currently being transferred, including both address and data, completes
bogdanm	82:6473597d706e	1286	* its transfer. The I2C slave or master acknowledges that the in-transfer byte
bogdanm	82:6473597d706e	1287	* completed its transfer and acknowledges the request to enter stop mode. After
bogdanm	82:6473597d706e	1288	* receiving the I2C module's acknowledgment of the request to enter stop mode,
bogdanm	82:6473597d706e	1289	* the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
bogdanm	82:6473597d706e	1290	* is set to 1 and the I2C module is in an idle or disabled state when the MCU
bogdanm	82:6473597d706e	1291	* signals to enter stop mode, the module immediately acknowledges the request to
bogdanm	82:6473597d706e	1292	* enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
bogdanm	82:6473597d706e	1293	* reception that was suspended by stop mode entry was incomplete: To resume the
bogdanm	82:6473597d706e	1294	* overall transmission or reception after the MCU exits stop mode, software must
bogdanm	82:6473597d706e	1295	* reinitialize the transfer by resending the address of the slave. If the I2C
bogdanm	82:6473597d706e	1296	* Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
bogdanm	82:6473597d706e	1297	* system software will receive the interrupt triggered by the I2C Status Register's
bogdanm	82:6473597d706e	1298	* TCF bit after the MCU wakes from the stop mode.
bogdanm	82:6473597d706e	1299	*
bogdanm	82:6473597d706e	1300	* Values:
bogdanm	82:6473597d706e	1301	* - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
bogdanm	82:6473597d706e	1302	* - 1 - Stop holdoff is enabled.
bogdanm	82:6473597d706e	1303	*/
bogdanm	82:6473597d706e	1304	//@{
bogdanm	82:6473597d706e	1305	#define BP_I2C_FLT_SHEN (7U) //!< Bit position for I2C_FLT_SHEN.
bogdanm	82:6473597d706e	1306	#define BM_I2C_FLT_SHEN (0x80U) //!< Bit mask for I2C_FLT_SHEN.
bogdanm	82:6473597d706e	1307	#define BS_I2C_FLT_SHEN (1U) //!< Bit field size in bits for I2C_FLT_SHEN.
bogdanm	82:6473597d706e	1308
bogdanm	82:6473597d706e	1309	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1310	//! @brief Read current value of the I2C_FLT_SHEN field.
bogdanm	82:6473597d706e	1311	#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
bogdanm	82:6473597d706e	1312	#endif
bogdanm	82:6473597d706e	1313
bogdanm	82:6473597d706e	1314	//! @brief Format value for bitfield I2C_FLT_SHEN.
bogdanm	82:6473597d706e	1315	#define BF_I2C_FLT_SHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SHEN), uint8_t) & BM_I2C_FLT_SHEN)
bogdanm	82:6473597d706e	1316
bogdanm	82:6473597d706e	1317	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1318	//! @brief Set the SHEN field to a new value.
bogdanm	82:6473597d706e	1319	#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
bogdanm	82:6473597d706e	1320	#endif
bogdanm	82:6473597d706e	1321	//@}
bogdanm	82:6473597d706e	1322
bogdanm	82:6473597d706e	1323	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1324	// HW_I2C_RA - I2C Range Address register
bogdanm	82:6473597d706e	1325	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1326
bogdanm	82:6473597d706e	1327	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1328	/*!
bogdanm	82:6473597d706e	1329	* @brief HW_I2C_RA - I2C Range Address register (RW)
bogdanm	82:6473597d706e	1330	*
bogdanm	82:6473597d706e	1331	* Reset value: 0x00U
bogdanm	82:6473597d706e	1332	*/
bogdanm	82:6473597d706e	1333	typedef union _hw_i2c_ra
bogdanm	82:6473597d706e	1334	{
bogdanm	82:6473597d706e	1335	uint8_t U;
bogdanm	82:6473597d706e	1336	struct _hw_i2c_ra_bitfields
bogdanm	82:6473597d706e	1337	{
bogdanm	82:6473597d706e	1338	uint8_t RESERVED0 : 1; //!< [0]
bogdanm	82:6473597d706e	1339	uint8_t RAD : 7; //!< [7:1] Range Slave Address
bogdanm	82:6473597d706e	1340	} B;
bogdanm	82:6473597d706e	1341	} hw_i2c_ra_t;
bogdanm	82:6473597d706e	1342	#endif
bogdanm	82:6473597d706e	1343
bogdanm	82:6473597d706e	1344	/*!
bogdanm	82:6473597d706e	1345	* @name Constants and macros for entire I2C_RA register
bogdanm	82:6473597d706e	1346	*/
bogdanm	82:6473597d706e	1347	//@{
bogdanm	82:6473597d706e	1348	#define HW_I2C_RA_ADDR(x) (REGS_I2C_BASE(x) + 0x7U)
bogdanm	82:6473597d706e	1349
bogdanm	82:6473597d706e	1350	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1351	#define HW_I2C_RA(x) ((__IO hw_i2c_ra_t ) HW_I2C_RA_ADDR(x))
bogdanm	82:6473597d706e	1352	#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U)
bogdanm	82:6473597d706e	1353	#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v))
bogdanm	82:6473597d706e	1354	#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) \| (v)))
bogdanm	82:6473597d706e	1355	#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1356	#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1357	#endif
bogdanm	82:6473597d706e	1358	//@}
bogdanm	82:6473597d706e	1359
bogdanm	82:6473597d706e	1360	/*
bogdanm	82:6473597d706e	1361	* Constants & macros for individual I2C_RA bitfields
bogdanm	82:6473597d706e	1362	*/
bogdanm	82:6473597d706e	1363
bogdanm	82:6473597d706e	1364	/*!
bogdanm	82:6473597d706e	1365	* @name Register I2C_RA, field RAD[7:1] (RW)
bogdanm	82:6473597d706e	1366	*
bogdanm	82:6473597d706e	1367	* This field contains the slave address to be used by the I2C module. The field
bogdanm	82:6473597d706e	1368	* is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
bogdanm	82:6473597d706e	1369	* value write enables this register. This register value can be considered as a
bogdanm	82:6473597d706e	1370	* maximum boundary in the range matching mode.
bogdanm	82:6473597d706e	1371	*/
bogdanm	82:6473597d706e	1372	//@{
bogdanm	82:6473597d706e	1373	#define BP_I2C_RA_RAD (1U) //!< Bit position for I2C_RA_RAD.
bogdanm	82:6473597d706e	1374	#define BM_I2C_RA_RAD (0xFEU) //!< Bit mask for I2C_RA_RAD.
bogdanm	82:6473597d706e	1375	#define BS_I2C_RA_RAD (7U) //!< Bit field size in bits for I2C_RA_RAD.
bogdanm	82:6473597d706e	1376
bogdanm	82:6473597d706e	1377	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1378	//! @brief Read current value of the I2C_RA_RAD field.
bogdanm	82:6473597d706e	1379	#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD)
bogdanm	82:6473597d706e	1380	#endif
bogdanm	82:6473597d706e	1381
bogdanm	82:6473597d706e	1382	//! @brief Format value for bitfield I2C_RA_RAD.
bogdanm	82:6473597d706e	1383	#define BF_I2C_RA_RAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_RA_RAD), uint8_t) & BM_I2C_RA_RAD)
bogdanm	82:6473597d706e	1384
bogdanm	82:6473597d706e	1385	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1386	//! @brief Set the RAD field to a new value.
bogdanm	82:6473597d706e	1387	#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) \| BF_I2C_RA_RAD(v)))
bogdanm	82:6473597d706e	1388	#endif
bogdanm	82:6473597d706e	1389	//@}
bogdanm	82:6473597d706e	1390
bogdanm	82:6473597d706e	1391	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1392	// HW_I2C_SMB - I2C SMBus Control and Status register
bogdanm	82:6473597d706e	1393	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1394
bogdanm	82:6473597d706e	1395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1396	/*!
bogdanm	82:6473597d706e	1397	* @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
bogdanm	82:6473597d706e	1398	*
bogdanm	82:6473597d706e	1399	* Reset value: 0x00U
bogdanm	82:6473597d706e	1400	*
bogdanm	82:6473597d706e	1401	* When the SCL and SDA signals are held high for a length of time greater than
bogdanm	82:6473597d706e	1402	* the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
bogdanm	82:6473597d706e	1403	* while the system is detecting how long these signals are being held high, a
bogdanm	82:6473597d706e	1404	* master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
bogdanm	82:6473597d706e	1405	* bus transmission process with the idle bus state. When the TCKSEL bit is set,
bogdanm	82:6473597d706e	1406	* there is no need to monitor the SHTF1 bit because the bus speed is too high to
bogdanm	82:6473597d706e	1407	* match the protocol of SMBus.
bogdanm	82:6473597d706e	1408	*/
bogdanm	82:6473597d706e	1409	typedef union _hw_i2c_smb
bogdanm	82:6473597d706e	1410	{
bogdanm	82:6473597d706e	1411	uint8_t U;
bogdanm	82:6473597d706e	1412	struct _hw_i2c_smb_bitfields
bogdanm	82:6473597d706e	1413	{
bogdanm	82:6473597d706e	1414	uint8_t SHTF2IE : 1; //!< [0] SHTF2 Interrupt Enable
bogdanm	82:6473597d706e	1415	uint8_t SHTF2 : 1; //!< [1] SCL High Timeout Flag 2
bogdanm	82:6473597d706e	1416	uint8_t SHTF1 : 1; //!< [2] SCL High Timeout Flag 1
bogdanm	82:6473597d706e	1417	uint8_t SLTF : 1; //!< [3] SCL Low Timeout Flag
bogdanm	82:6473597d706e	1418	uint8_t TCKSEL : 1; //!< [4] Timeout Counter Clock Select
bogdanm	82:6473597d706e	1419	uint8_t SIICAEN : 1; //!< [5] Second I2C Address Enable
bogdanm	82:6473597d706e	1420	uint8_t ALERTEN : 1; //!< [6] SMBus Alert Response Address Enable
bogdanm	82:6473597d706e	1421	uint8_t FACK : 1; //!< [7] Fast NACK/ACK Enable
bogdanm	82:6473597d706e	1422	} B;
bogdanm	82:6473597d706e	1423	} hw_i2c_smb_t;
bogdanm	82:6473597d706e	1424	#endif
bogdanm	82:6473597d706e	1425
bogdanm	82:6473597d706e	1426	/*!
bogdanm	82:6473597d706e	1427	* @name Constants and macros for entire I2C_SMB register
bogdanm	82:6473597d706e	1428	*/
bogdanm	82:6473597d706e	1429	//@{
bogdanm	82:6473597d706e	1430	#define HW_I2C_SMB_ADDR(x) (REGS_I2C_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	1431
bogdanm	82:6473597d706e	1432	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1433	#define HW_I2C_SMB(x) ((__IO hw_i2c_smb_t ) HW_I2C_SMB_ADDR(x))
bogdanm	82:6473597d706e	1434	#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U)
bogdanm	82:6473597d706e	1435	#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v))
bogdanm	82:6473597d706e	1436	#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) \| (v)))
bogdanm	82:6473597d706e	1437	#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1438	#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1439	#endif
bogdanm	82:6473597d706e	1440	//@}
bogdanm	82:6473597d706e	1441
bogdanm	82:6473597d706e	1442	/*
bogdanm	82:6473597d706e	1443	* Constants & macros for individual I2C_SMB bitfields
bogdanm	82:6473597d706e	1444	*/
bogdanm	82:6473597d706e	1445
bogdanm	82:6473597d706e	1446	/*!
bogdanm	82:6473597d706e	1447	* @name Register I2C_SMB, field SHTF2IE[0] (RW)
bogdanm	82:6473597d706e	1448	*
bogdanm	82:6473597d706e	1449	* Enables SCL high and SDA low timeout interrupt.
bogdanm	82:6473597d706e	1450	*
bogdanm	82:6473597d706e	1451	* Values:
bogdanm	82:6473597d706e	1452	* - 0 - SHTF2 interrupt is disabled
bogdanm	82:6473597d706e	1453	* - 1 - SHTF2 interrupt is enabled
bogdanm	82:6473597d706e	1454	*/
bogdanm	82:6473597d706e	1455	//@{
bogdanm	82:6473597d706e	1456	#define BP_I2C_SMB_SHTF2IE (0U) //!< Bit position for I2C_SMB_SHTF2IE.
bogdanm	82:6473597d706e	1457	#define BM_I2C_SMB_SHTF2IE (0x01U) //!< Bit mask for I2C_SMB_SHTF2IE.
bogdanm	82:6473597d706e	1458	#define BS_I2C_SMB_SHTF2IE (1U) //!< Bit field size in bits for I2C_SMB_SHTF2IE.
bogdanm	82:6473597d706e	1459
bogdanm	82:6473597d706e	1460	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1461	//! @brief Read current value of the I2C_SMB_SHTF2IE field.
bogdanm	82:6473597d706e	1462	#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
bogdanm	82:6473597d706e	1463	#endif
bogdanm	82:6473597d706e	1464
bogdanm	82:6473597d706e	1465	//! @brief Format value for bitfield I2C_SMB_SHTF2IE.
bogdanm	82:6473597d706e	1466	#define BF_I2C_SMB_SHTF2IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2IE), uint8_t) & BM_I2C_SMB_SHTF2IE)
bogdanm	82:6473597d706e	1467
bogdanm	82:6473597d706e	1468	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1469	//! @brief Set the SHTF2IE field to a new value.
bogdanm	82:6473597d706e	1470	#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
bogdanm	82:6473597d706e	1471	#endif
bogdanm	82:6473597d706e	1472	//@}
bogdanm	82:6473597d706e	1473
bogdanm	82:6473597d706e	1474	/*!
bogdanm	82:6473597d706e	1475	* @name Register I2C_SMB, field SHTF2[1] (W1C)
bogdanm	82:6473597d706e	1476	*
bogdanm	82:6473597d706e	1477	* This bit sets when SCL is held high and SDA is held low more than clock *
bogdanm	82:6473597d706e	1478	* LoValue / 512. Software clears this bit by writing 1 to it.
bogdanm	82:6473597d706e	1479	*
bogdanm	82:6473597d706e	1480	* Values:
bogdanm	82:6473597d706e	1481	* - 0 - No SCL high and SDA low timeout occurs
bogdanm	82:6473597d706e	1482	* - 1 - SCL high and SDA low timeout occurs
bogdanm	82:6473597d706e	1483	*/
bogdanm	82:6473597d706e	1484	//@{
bogdanm	82:6473597d706e	1485	#define BP_I2C_SMB_SHTF2 (1U) //!< Bit position for I2C_SMB_SHTF2.
bogdanm	82:6473597d706e	1486	#define BM_I2C_SMB_SHTF2 (0x02U) //!< Bit mask for I2C_SMB_SHTF2.
bogdanm	82:6473597d706e	1487	#define BS_I2C_SMB_SHTF2 (1U) //!< Bit field size in bits for I2C_SMB_SHTF2.
bogdanm	82:6473597d706e	1488
bogdanm	82:6473597d706e	1489	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1490	//! @brief Read current value of the I2C_SMB_SHTF2 field.
bogdanm	82:6473597d706e	1491	#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
bogdanm	82:6473597d706e	1492	#endif
bogdanm	82:6473597d706e	1493
bogdanm	82:6473597d706e	1494	//! @brief Format value for bitfield I2C_SMB_SHTF2.
bogdanm	82:6473597d706e	1495	#define BF_I2C_SMB_SHTF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2), uint8_t) & BM_I2C_SMB_SHTF2)
bogdanm	82:6473597d706e	1496
bogdanm	82:6473597d706e	1497	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1498	//! @brief Set the SHTF2 field to a new value.
bogdanm	82:6473597d706e	1499	#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
bogdanm	82:6473597d706e	1500	#endif
bogdanm	82:6473597d706e	1501	//@}
bogdanm	82:6473597d706e	1502
bogdanm	82:6473597d706e	1503	/*!
bogdanm	82:6473597d706e	1504	* @name Register I2C_SMB, field SHTF1[2] (RO)
bogdanm	82:6473597d706e	1505	*
bogdanm	82:6473597d706e	1506	* This read-only bit sets when SCL and SDA are held high more than clock *
bogdanm	82:6473597d706e	1507	* LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
bogdanm	82:6473597d706e	1508	*
bogdanm	82:6473597d706e	1509	* Values:
bogdanm	82:6473597d706e	1510	* - 0 - No SCL high and SDA high timeout occurs
bogdanm	82:6473597d706e	1511	* - 1 - SCL high and SDA high timeout occurs
bogdanm	82:6473597d706e	1512	*/
bogdanm	82:6473597d706e	1513	//@{
bogdanm	82:6473597d706e	1514	#define BP_I2C_SMB_SHTF1 (2U) //!< Bit position for I2C_SMB_SHTF1.
bogdanm	82:6473597d706e	1515	#define BM_I2C_SMB_SHTF1 (0x04U) //!< Bit mask for I2C_SMB_SHTF1.
bogdanm	82:6473597d706e	1516	#define BS_I2C_SMB_SHTF1 (1U) //!< Bit field size in bits for I2C_SMB_SHTF1.
bogdanm	82:6473597d706e	1517
bogdanm	82:6473597d706e	1518	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1519	//! @brief Read current value of the I2C_SMB_SHTF1 field.
bogdanm	82:6473597d706e	1520	#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
bogdanm	82:6473597d706e	1521	#endif
bogdanm	82:6473597d706e	1522	//@}
bogdanm	82:6473597d706e	1523
bogdanm	82:6473597d706e	1524	/*!
bogdanm	82:6473597d706e	1525	* @name Register I2C_SMB, field SLTF[3] (W1C)
bogdanm	82:6473597d706e	1526	*
bogdanm	82:6473597d706e	1527	* This bit is set when the SLT register (consisting of the SLTH and SLTL
bogdanm	82:6473597d706e	1528	* registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
bogdanm	82:6473597d706e	1529	* Software clears this bit by writing a logic 1 to it. The low timeout function
bogdanm	82:6473597d706e	1530	* is disabled when the SLT register's value is 0.
bogdanm	82:6473597d706e	1531	*
bogdanm	82:6473597d706e	1532	* Values:
bogdanm	82:6473597d706e	1533	* - 0 - No low timeout occurs
bogdanm	82:6473597d706e	1534	* - 1 - Low timeout occurs
bogdanm	82:6473597d706e	1535	*/
bogdanm	82:6473597d706e	1536	//@{
bogdanm	82:6473597d706e	1537	#define BP_I2C_SMB_SLTF (3U) //!< Bit position for I2C_SMB_SLTF.
bogdanm	82:6473597d706e	1538	#define BM_I2C_SMB_SLTF (0x08U) //!< Bit mask for I2C_SMB_SLTF.
bogdanm	82:6473597d706e	1539	#define BS_I2C_SMB_SLTF (1U) //!< Bit field size in bits for I2C_SMB_SLTF.
bogdanm	82:6473597d706e	1540
bogdanm	82:6473597d706e	1541	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1542	//! @brief Read current value of the I2C_SMB_SLTF field.
bogdanm	82:6473597d706e	1543	#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
bogdanm	82:6473597d706e	1544	#endif
bogdanm	82:6473597d706e	1545
bogdanm	82:6473597d706e	1546	//! @brief Format value for bitfield I2C_SMB_SLTF.
bogdanm	82:6473597d706e	1547	#define BF_I2C_SMB_SLTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SLTF), uint8_t) & BM_I2C_SMB_SLTF)
bogdanm	82:6473597d706e	1548
bogdanm	82:6473597d706e	1549	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1550	//! @brief Set the SLTF field to a new value.
bogdanm	82:6473597d706e	1551	#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
bogdanm	82:6473597d706e	1552	#endif
bogdanm	82:6473597d706e	1553	//@}
bogdanm	82:6473597d706e	1554
bogdanm	82:6473597d706e	1555	/*!
bogdanm	82:6473597d706e	1556	* @name Register I2C_SMB, field TCKSEL[4] (RW)
bogdanm	82:6473597d706e	1557	*
bogdanm	82:6473597d706e	1558	* Selects the clock source of the timeout counter.
bogdanm	82:6473597d706e	1559	*
bogdanm	82:6473597d706e	1560	* Values:
bogdanm	82:6473597d706e	1561	* - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
bogdanm	82:6473597d706e	1562	* - 1 - Timeout counter counts at the frequency of the I2C module clock
bogdanm	82:6473597d706e	1563	*/
bogdanm	82:6473597d706e	1564	//@{
bogdanm	82:6473597d706e	1565	#define BP_I2C_SMB_TCKSEL (4U) //!< Bit position for I2C_SMB_TCKSEL.
bogdanm	82:6473597d706e	1566	#define BM_I2C_SMB_TCKSEL (0x10U) //!< Bit mask for I2C_SMB_TCKSEL.
bogdanm	82:6473597d706e	1567	#define BS_I2C_SMB_TCKSEL (1U) //!< Bit field size in bits for I2C_SMB_TCKSEL.
bogdanm	82:6473597d706e	1568
bogdanm	82:6473597d706e	1569	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1570	//! @brief Read current value of the I2C_SMB_TCKSEL field.
bogdanm	82:6473597d706e	1571	#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
bogdanm	82:6473597d706e	1572	#endif
bogdanm	82:6473597d706e	1573
bogdanm	82:6473597d706e	1574	//! @brief Format value for bitfield I2C_SMB_TCKSEL.
bogdanm	82:6473597d706e	1575	#define BF_I2C_SMB_TCKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_TCKSEL), uint8_t) & BM_I2C_SMB_TCKSEL)
bogdanm	82:6473597d706e	1576
bogdanm	82:6473597d706e	1577	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1578	//! @brief Set the TCKSEL field to a new value.
bogdanm	82:6473597d706e	1579	#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
bogdanm	82:6473597d706e	1580	#endif
bogdanm	82:6473597d706e	1581	//@}
bogdanm	82:6473597d706e	1582
bogdanm	82:6473597d706e	1583	/*!
bogdanm	82:6473597d706e	1584	* @name Register I2C_SMB, field SIICAEN[5] (RW)
bogdanm	82:6473597d706e	1585	*
bogdanm	82:6473597d706e	1586	* Enables or disables SMBus device default address.
bogdanm	82:6473597d706e	1587	*
bogdanm	82:6473597d706e	1588	* Values:
bogdanm	82:6473597d706e	1589	* - 0 - I2C address register 2 matching is disabled
bogdanm	82:6473597d706e	1590	* - 1 - I2C address register 2 matching is enabled
bogdanm	82:6473597d706e	1591	*/
bogdanm	82:6473597d706e	1592	//@{
bogdanm	82:6473597d706e	1593	#define BP_I2C_SMB_SIICAEN (5U) //!< Bit position for I2C_SMB_SIICAEN.
bogdanm	82:6473597d706e	1594	#define BM_I2C_SMB_SIICAEN (0x20U) //!< Bit mask for I2C_SMB_SIICAEN.
bogdanm	82:6473597d706e	1595	#define BS_I2C_SMB_SIICAEN (1U) //!< Bit field size in bits for I2C_SMB_SIICAEN.
bogdanm	82:6473597d706e	1596
bogdanm	82:6473597d706e	1597	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1598	//! @brief Read current value of the I2C_SMB_SIICAEN field.
bogdanm	82:6473597d706e	1599	#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
bogdanm	82:6473597d706e	1600	#endif
bogdanm	82:6473597d706e	1601
bogdanm	82:6473597d706e	1602	//! @brief Format value for bitfield I2C_SMB_SIICAEN.
bogdanm	82:6473597d706e	1603	#define BF_I2C_SMB_SIICAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SIICAEN), uint8_t) & BM_I2C_SMB_SIICAEN)
bogdanm	82:6473597d706e	1604
bogdanm	82:6473597d706e	1605	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1606	//! @brief Set the SIICAEN field to a new value.
bogdanm	82:6473597d706e	1607	#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
bogdanm	82:6473597d706e	1608	#endif
bogdanm	82:6473597d706e	1609	//@}
bogdanm	82:6473597d706e	1610
bogdanm	82:6473597d706e	1611	/*!
bogdanm	82:6473597d706e	1612	* @name Register I2C_SMB, field ALERTEN[6] (RW)
bogdanm	82:6473597d706e	1613	*
bogdanm	82:6473597d706e	1614	* Enables or disables SMBus alert response address matching. After the host
bogdanm	82:6473597d706e	1615	* responds to a device that used the alert response address, you must use software
bogdanm	82:6473597d706e	1616	* to put the device's address on the bus. The alert protocol is described in the
bogdanm	82:6473597d706e	1617	* SMBus specification.
bogdanm	82:6473597d706e	1618	*
bogdanm	82:6473597d706e	1619	* Values:
bogdanm	82:6473597d706e	1620	* - 0 - SMBus alert response address matching is disabled
bogdanm	82:6473597d706e	1621	* - 1 - SMBus alert response address matching is enabled
bogdanm	82:6473597d706e	1622	*/
bogdanm	82:6473597d706e	1623	//@{
bogdanm	82:6473597d706e	1624	#define BP_I2C_SMB_ALERTEN (6U) //!< Bit position for I2C_SMB_ALERTEN.
bogdanm	82:6473597d706e	1625	#define BM_I2C_SMB_ALERTEN (0x40U) //!< Bit mask for I2C_SMB_ALERTEN.
bogdanm	82:6473597d706e	1626	#define BS_I2C_SMB_ALERTEN (1U) //!< Bit field size in bits for I2C_SMB_ALERTEN.
bogdanm	82:6473597d706e	1627
bogdanm	82:6473597d706e	1628	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1629	//! @brief Read current value of the I2C_SMB_ALERTEN field.
bogdanm	82:6473597d706e	1630	#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
bogdanm	82:6473597d706e	1631	#endif
bogdanm	82:6473597d706e	1632
bogdanm	82:6473597d706e	1633	//! @brief Format value for bitfield I2C_SMB_ALERTEN.
bogdanm	82:6473597d706e	1634	#define BF_I2C_SMB_ALERTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_ALERTEN), uint8_t) & BM_I2C_SMB_ALERTEN)
bogdanm	82:6473597d706e	1635
bogdanm	82:6473597d706e	1636	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1637	//! @brief Set the ALERTEN field to a new value.
bogdanm	82:6473597d706e	1638	#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
bogdanm	82:6473597d706e	1639	#endif
bogdanm	82:6473597d706e	1640	//@}
bogdanm	82:6473597d706e	1641
bogdanm	82:6473597d706e	1642	/*!
bogdanm	82:6473597d706e	1643	* @name Register I2C_SMB, field FACK[7] (RW)
bogdanm	82:6473597d706e	1644	*
bogdanm	82:6473597d706e	1645	* For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
bogdanm	82:6473597d706e	1646	* according to the result of receiving data byte.
bogdanm	82:6473597d706e	1647	*
bogdanm	82:6473597d706e	1648	* Values:
bogdanm	82:6473597d706e	1649	* - 0 - An ACK or NACK is sent on the following receiving data byte
bogdanm	82:6473597d706e	1650	* - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
bogdanm	82:6473597d706e	1651	* 1 to TXAK after receiving a data byte generates a NACK.
bogdanm	82:6473597d706e	1652	*/
bogdanm	82:6473597d706e	1653	//@{
bogdanm	82:6473597d706e	1654	#define BP_I2C_SMB_FACK (7U) //!< Bit position for I2C_SMB_FACK.
bogdanm	82:6473597d706e	1655	#define BM_I2C_SMB_FACK (0x80U) //!< Bit mask for I2C_SMB_FACK.
bogdanm	82:6473597d706e	1656	#define BS_I2C_SMB_FACK (1U) //!< Bit field size in bits for I2C_SMB_FACK.
bogdanm	82:6473597d706e	1657
bogdanm	82:6473597d706e	1658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1659	//! @brief Read current value of the I2C_SMB_FACK field.
bogdanm	82:6473597d706e	1660	#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
bogdanm	82:6473597d706e	1661	#endif
bogdanm	82:6473597d706e	1662
bogdanm	82:6473597d706e	1663	//! @brief Format value for bitfield I2C_SMB_FACK.
bogdanm	82:6473597d706e	1664	#define BF_I2C_SMB_FACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_FACK), uint8_t) & BM_I2C_SMB_FACK)
bogdanm	82:6473597d706e	1665
bogdanm	82:6473597d706e	1666	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1667	//! @brief Set the FACK field to a new value.
bogdanm	82:6473597d706e	1668	#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
bogdanm	82:6473597d706e	1669	#endif
bogdanm	82:6473597d706e	1670	//@}
bogdanm	82:6473597d706e	1671
bogdanm	82:6473597d706e	1672	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1673	// HW_I2C_A2 - I2C Address Register 2
bogdanm	82:6473597d706e	1674	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1675
bogdanm	82:6473597d706e	1676	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1677	/*!
bogdanm	82:6473597d706e	1678	* @brief HW_I2C_A2 - I2C Address Register 2 (RW)
bogdanm	82:6473597d706e	1679	*
bogdanm	82:6473597d706e	1680	* Reset value: 0xC2U
bogdanm	82:6473597d706e	1681	*/
bogdanm	82:6473597d706e	1682	typedef union _hw_i2c_a2
bogdanm	82:6473597d706e	1683	{
bogdanm	82:6473597d706e	1684	uint8_t U;
bogdanm	82:6473597d706e	1685	struct _hw_i2c_a2_bitfields
bogdanm	82:6473597d706e	1686	{
bogdanm	82:6473597d706e	1687	uint8_t RESERVED0 : 1; //!< [0]
bogdanm	82:6473597d706e	1688	uint8_t SAD : 7; //!< [7:1] SMBus Address
bogdanm	82:6473597d706e	1689	} B;
bogdanm	82:6473597d706e	1690	} hw_i2c_a2_t;
bogdanm	82:6473597d706e	1691	#endif
bogdanm	82:6473597d706e	1692
bogdanm	82:6473597d706e	1693	/*!
bogdanm	82:6473597d706e	1694	* @name Constants and macros for entire I2C_A2 register
bogdanm	82:6473597d706e	1695	*/
bogdanm	82:6473597d706e	1696	//@{
bogdanm	82:6473597d706e	1697	#define HW_I2C_A2_ADDR(x) (REGS_I2C_BASE(x) + 0x9U)
bogdanm	82:6473597d706e	1698
bogdanm	82:6473597d706e	1699	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1700	#define HW_I2C_A2(x) ((__IO hw_i2c_a2_t ) HW_I2C_A2_ADDR(x))
bogdanm	82:6473597d706e	1701	#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U)
bogdanm	82:6473597d706e	1702	#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v))
bogdanm	82:6473597d706e	1703	#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) \| (v)))
bogdanm	82:6473597d706e	1704	#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1705	#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1706	#endif
bogdanm	82:6473597d706e	1707	//@}
bogdanm	82:6473597d706e	1708
bogdanm	82:6473597d706e	1709	/*
bogdanm	82:6473597d706e	1710	* Constants & macros for individual I2C_A2 bitfields
bogdanm	82:6473597d706e	1711	*/
bogdanm	82:6473597d706e	1712
bogdanm	82:6473597d706e	1713	/*!
bogdanm	82:6473597d706e	1714	* @name Register I2C_A2, field SAD[7:1] (RW)
bogdanm	82:6473597d706e	1715	*
bogdanm	82:6473597d706e	1716	* Contains the slave address used by the SMBus. This field is used on the
bogdanm	82:6473597d706e	1717	* device default address or other related addresses.
bogdanm	82:6473597d706e	1718	*/
bogdanm	82:6473597d706e	1719	//@{
bogdanm	82:6473597d706e	1720	#define BP_I2C_A2_SAD (1U) //!< Bit position for I2C_A2_SAD.
bogdanm	82:6473597d706e	1721	#define BM_I2C_A2_SAD (0xFEU) //!< Bit mask for I2C_A2_SAD.
bogdanm	82:6473597d706e	1722	#define BS_I2C_A2_SAD (7U) //!< Bit field size in bits for I2C_A2_SAD.
bogdanm	82:6473597d706e	1723
bogdanm	82:6473597d706e	1724	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1725	//! @brief Read current value of the I2C_A2_SAD field.
bogdanm	82:6473597d706e	1726	#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD)
bogdanm	82:6473597d706e	1727	#endif
bogdanm	82:6473597d706e	1728
bogdanm	82:6473597d706e	1729	//! @brief Format value for bitfield I2C_A2_SAD.
bogdanm	82:6473597d706e	1730	#define BF_I2C_A2_SAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A2_SAD), uint8_t) & BM_I2C_A2_SAD)
bogdanm	82:6473597d706e	1731
bogdanm	82:6473597d706e	1732	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1733	//! @brief Set the SAD field to a new value.
bogdanm	82:6473597d706e	1734	#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) \| BF_I2C_A2_SAD(v)))
bogdanm	82:6473597d706e	1735	#endif
bogdanm	82:6473597d706e	1736	//@}
bogdanm	82:6473597d706e	1737
bogdanm	82:6473597d706e	1738	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1739	// HW_I2C_SLTH - I2C SCL Low Timeout Register High
bogdanm	82:6473597d706e	1740	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1741
bogdanm	82:6473597d706e	1742	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1743	/*!
bogdanm	82:6473597d706e	1744	* @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
bogdanm	82:6473597d706e	1745	*
bogdanm	82:6473597d706e	1746	* Reset value: 0x00U
bogdanm	82:6473597d706e	1747	*/
bogdanm	82:6473597d706e	1748	typedef union _hw_i2c_slth
bogdanm	82:6473597d706e	1749	{
bogdanm	82:6473597d706e	1750	uint8_t U;
bogdanm	82:6473597d706e	1751	struct _hw_i2c_slth_bitfields
bogdanm	82:6473597d706e	1752	{
bogdanm	82:6473597d706e	1753	uint8_t SSLT : 8; //!< [7:0]
bogdanm	82:6473597d706e	1754	} B;
bogdanm	82:6473597d706e	1755	} hw_i2c_slth_t;
bogdanm	82:6473597d706e	1756	#endif
bogdanm	82:6473597d706e	1757
bogdanm	82:6473597d706e	1758	/*!
bogdanm	82:6473597d706e	1759	* @name Constants and macros for entire I2C_SLTH register
bogdanm	82:6473597d706e	1760	*/
bogdanm	82:6473597d706e	1761	//@{
bogdanm	82:6473597d706e	1762	#define HW_I2C_SLTH_ADDR(x) (REGS_I2C_BASE(x) + 0xAU)
bogdanm	82:6473597d706e	1763
bogdanm	82:6473597d706e	1764	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1765	#define HW_I2C_SLTH(x) ((__IO hw_i2c_slth_t ) HW_I2C_SLTH_ADDR(x))
bogdanm	82:6473597d706e	1766	#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U)
bogdanm	82:6473597d706e	1767	#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v))
bogdanm	82:6473597d706e	1768	#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) \| (v)))
bogdanm	82:6473597d706e	1769	#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1770	#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1771	#endif
bogdanm	82:6473597d706e	1772	//@}
bogdanm	82:6473597d706e	1773
bogdanm	82:6473597d706e	1774	/*
bogdanm	82:6473597d706e	1775	* Constants & macros for individual I2C_SLTH bitfields
bogdanm	82:6473597d706e	1776	*/
bogdanm	82:6473597d706e	1777
bogdanm	82:6473597d706e	1778	/*!
bogdanm	82:6473597d706e	1779	* @name Register I2C_SLTH, field SSLT[7:0] (RW)
bogdanm	82:6473597d706e	1780	*
bogdanm	82:6473597d706e	1781	* Most significant byte of SCL low timeout value that determines the timeout
bogdanm	82:6473597d706e	1782	* period of SCL low.
bogdanm	82:6473597d706e	1783	*/
bogdanm	82:6473597d706e	1784	//@{
bogdanm	82:6473597d706e	1785	#define BP_I2C_SLTH_SSLT (0U) //!< Bit position for I2C_SLTH_SSLT.
bogdanm	82:6473597d706e	1786	#define BM_I2C_SLTH_SSLT (0xFFU) //!< Bit mask for I2C_SLTH_SSLT.
bogdanm	82:6473597d706e	1787	#define BS_I2C_SLTH_SSLT (8U) //!< Bit field size in bits for I2C_SLTH_SSLT.
bogdanm	82:6473597d706e	1788
bogdanm	82:6473597d706e	1789	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1790	//! @brief Read current value of the I2C_SLTH_SSLT field.
bogdanm	82:6473597d706e	1791	#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U)
bogdanm	82:6473597d706e	1792	#endif
bogdanm	82:6473597d706e	1793
bogdanm	82:6473597d706e	1794	//! @brief Format value for bitfield I2C_SLTH_SSLT.
bogdanm	82:6473597d706e	1795	#define BF_I2C_SLTH_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTH_SSLT), uint8_t) & BM_I2C_SLTH_SSLT)
bogdanm	82:6473597d706e	1796
bogdanm	82:6473597d706e	1797	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1798	//! @brief Set the SSLT field to a new value.
bogdanm	82:6473597d706e	1799	#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
bogdanm	82:6473597d706e	1800	#endif
bogdanm	82:6473597d706e	1801	//@}
bogdanm	82:6473597d706e	1802
bogdanm	82:6473597d706e	1803	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1804	// HW_I2C_SLTL - I2C SCL Low Timeout Register Low
bogdanm	82:6473597d706e	1805	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1806
bogdanm	82:6473597d706e	1807	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1808	/*!
bogdanm	82:6473597d706e	1809	* @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
bogdanm	82:6473597d706e	1810	*
bogdanm	82:6473597d706e	1811	* Reset value: 0x00U
bogdanm	82:6473597d706e	1812	*/
bogdanm	82:6473597d706e	1813	typedef union _hw_i2c_sltl
bogdanm	82:6473597d706e	1814	{
bogdanm	82:6473597d706e	1815	uint8_t U;
bogdanm	82:6473597d706e	1816	struct _hw_i2c_sltl_bitfields
bogdanm	82:6473597d706e	1817	{
bogdanm	82:6473597d706e	1818	uint8_t SSLT : 8; //!< [7:0]
bogdanm	82:6473597d706e	1819	} B;
bogdanm	82:6473597d706e	1820	} hw_i2c_sltl_t;
bogdanm	82:6473597d706e	1821	#endif
bogdanm	82:6473597d706e	1822
bogdanm	82:6473597d706e	1823	/*!
bogdanm	82:6473597d706e	1824	* @name Constants and macros for entire I2C_SLTL register
bogdanm	82:6473597d706e	1825	*/
bogdanm	82:6473597d706e	1826	//@{
bogdanm	82:6473597d706e	1827	#define HW_I2C_SLTL_ADDR(x) (REGS_I2C_BASE(x) + 0xBU)
bogdanm	82:6473597d706e	1828
bogdanm	82:6473597d706e	1829	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1830	#define HW_I2C_SLTL(x) ((__IO hw_i2c_sltl_t ) HW_I2C_SLTL_ADDR(x))
bogdanm	82:6473597d706e	1831	#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U)
bogdanm	82:6473597d706e	1832	#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v))
bogdanm	82:6473597d706e	1833	#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) \| (v)))
bogdanm	82:6473597d706e	1834	#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1835	#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1836	#endif
bogdanm	82:6473597d706e	1837	//@}
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	/*
bogdanm	82:6473597d706e	1840	* Constants & macros for individual I2C_SLTL bitfields
bogdanm	82:6473597d706e	1841	*/
bogdanm	82:6473597d706e	1842
bogdanm	82:6473597d706e	1843	/*!
bogdanm	82:6473597d706e	1844	* @name Register I2C_SLTL, field SSLT[7:0] (RW)
bogdanm	82:6473597d706e	1845	*
bogdanm	82:6473597d706e	1846	* Least significant byte of SCL low timeout value that determines the timeout
bogdanm	82:6473597d706e	1847	* period of SCL low.
bogdanm	82:6473597d706e	1848	*/
bogdanm	82:6473597d706e	1849	//@{
bogdanm	82:6473597d706e	1850	#define BP_I2C_SLTL_SSLT (0U) //!< Bit position for I2C_SLTL_SSLT.
bogdanm	82:6473597d706e	1851	#define BM_I2C_SLTL_SSLT (0xFFU) //!< Bit mask for I2C_SLTL_SSLT.
bogdanm	82:6473597d706e	1852	#define BS_I2C_SLTL_SSLT (8U) //!< Bit field size in bits for I2C_SLTL_SSLT.
bogdanm	82:6473597d706e	1853
bogdanm	82:6473597d706e	1854	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1855	//! @brief Read current value of the I2C_SLTL_SSLT field.
bogdanm	82:6473597d706e	1856	#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U)
bogdanm	82:6473597d706e	1857	#endif
bogdanm	82:6473597d706e	1858
bogdanm	82:6473597d706e	1859	//! @brief Format value for bitfield I2C_SLTL_SSLT.
bogdanm	82:6473597d706e	1860	#define BF_I2C_SLTL_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTL_SSLT), uint8_t) & BM_I2C_SLTL_SSLT)
bogdanm	82:6473597d706e	1861
bogdanm	82:6473597d706e	1862	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1863	//! @brief Set the SSLT field to a new value.
bogdanm	82:6473597d706e	1864	#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
bogdanm	82:6473597d706e	1865	#endif
bogdanm	82:6473597d706e	1866	//@}
bogdanm	82:6473597d706e	1867
bogdanm	82:6473597d706e	1868	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1869	// hw_i2c_t - module struct
bogdanm	82:6473597d706e	1870	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1871	/*!
bogdanm	82:6473597d706e	1872	* @brief All I2C module registers.
bogdanm	82:6473597d706e	1873	*/
bogdanm	82:6473597d706e	1874	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1875	#pragma pack(1)
bogdanm	82:6473597d706e	1876	typedef struct _hw_i2c
bogdanm	82:6473597d706e	1877	{
bogdanm	82:6473597d706e	1878	__IO hw_i2c_a1_t A1; //!< [0x0] I2C Address Register 1
bogdanm	82:6473597d706e	1879	__IO hw_i2c_f_t F; //!< [0x1] I2C Frequency Divider register
bogdanm	82:6473597d706e	1880	__IO hw_i2c_c1_t C1; //!< [0x2] I2C Control Register 1
bogdanm	82:6473597d706e	1881	__IO hw_i2c_s_t S; //!< [0x3] I2C Status register
bogdanm	82:6473597d706e	1882	__IO hw_i2c_d_t D; //!< [0x4] I2C Data I/O register
bogdanm	82:6473597d706e	1883	__IO hw_i2c_c2_t C2; //!< [0x5] I2C Control Register 2
bogdanm	82:6473597d706e	1884	__IO hw_i2c_flt_t FLT; //!< [0x6] I2C Programmable Input Glitch Filter register
bogdanm	82:6473597d706e	1885	__IO hw_i2c_ra_t RA; //!< [0x7] I2C Range Address register
bogdanm	82:6473597d706e	1886	__IO hw_i2c_smb_t SMB; //!< [0x8] I2C SMBus Control and Status register
bogdanm	82:6473597d706e	1887	__IO hw_i2c_a2_t A2; //!< [0x9] I2C Address Register 2
bogdanm	82:6473597d706e	1888	__IO hw_i2c_slth_t SLTH; //!< [0xA] I2C SCL Low Timeout Register High
bogdanm	82:6473597d706e	1889	__IO hw_i2c_sltl_t SLTL; //!< [0xB] I2C SCL Low Timeout Register Low
bogdanm	82:6473597d706e	1890	} hw_i2c_t;
bogdanm	82:6473597d706e	1891	#pragma pack()
bogdanm	82:6473597d706e	1892
bogdanm	82:6473597d706e	1893	//! @brief Macro to access all I2C registers.
bogdanm	82:6473597d706e	1894	//! @param x I2C instance number.
bogdanm	82:6473597d706e	1895	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1896	//! use the '&' operator, like <code>&HW_I2C(0)</code>.
bogdanm	82:6473597d706e	1897	#define HW_I2C(x) ((hw_i2c_t ) REGS_I2C_BASE(x))
bogdanm	82:6473597d706e	1898	#endif
bogdanm	82:6473597d706e	1899
bogdanm	82:6473597d706e	1900	#endif // __HW_I2C_REGISTERS_H__
bogdanm	82:6473597d706e	1901	// v22/130726/0.9
bogdanm	82:6473597d706e	1902	// EOF

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
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The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2c.h@82:6473597d706e, 2014-04-07 (annotated)

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