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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_can.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_CAN_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_CAN_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 CAN
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Flex Controller Area Network module
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_CAN_MCR - Module Configuration Register
bogdanm	82:6473597d706e	33	* - HW_CAN_CTRL1 - Control 1 register
bogdanm	82:6473597d706e	34	* - HW_CAN_TIMER - Free Running Timer
bogdanm	82:6473597d706e	35	* - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
bogdanm	82:6473597d706e	36	* - HW_CAN_RX14MASK - Rx 14 Mask register
bogdanm	82:6473597d706e	37	* - HW_CAN_RX15MASK - Rx 15 Mask register
bogdanm	82:6473597d706e	38	* - HW_CAN_ECR - Error Counter
bogdanm	82:6473597d706e	39	* - HW_CAN_ESR1 - Error and Status 1 register
bogdanm	82:6473597d706e	40	* - HW_CAN_IMASK1 - Interrupt Masks 1 register
bogdanm	82:6473597d706e	41	* - HW_CAN_IFLAG1 - Interrupt Flags 1 register
bogdanm	82:6473597d706e	42	* - HW_CAN_CTRL2 - Control 2 register
bogdanm	82:6473597d706e	43	* - HW_CAN_ESR2 - Error and Status 2 register
bogdanm	82:6473597d706e	44	* - HW_CAN_CRCR - CRC Register
bogdanm	82:6473597d706e	45	* - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
bogdanm	82:6473597d706e	46	* - HW_CAN_RXFIR - Rx FIFO Information Register
bogdanm	82:6473597d706e	47	* - HW_CAN_CS - Message Buffer 0 CS Register
bogdanm	82:6473597d706e	48	* - HW_CAN_ID - Message Buffer 0 ID Register
bogdanm	82:6473597d706e	49	* - HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
bogdanm	82:6473597d706e	50	* - HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
bogdanm	82:6473597d706e	51	* - HW_CAN_RXIMRn - Rx Individual Mask Registers
bogdanm	82:6473597d706e	52	*
bogdanm	82:6473597d706e	53	* - hw_can_t - Struct containing all module registers.
bogdanm	82:6473597d706e	54	*/
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	//! @name Module base addresses
bogdanm	82:6473597d706e	57	//@{
bogdanm	82:6473597d706e	58	#ifndef REGS_CAN_BASE
bogdanm	82:6473597d706e	59	#define HW_CAN_INSTANCE_COUNT (1U) //!< Number of instances of the CAN module.
bogdanm	82:6473597d706e	60	#define HW_CAN0 (0U) //!< Instance number for CAN0.
bogdanm	82:6473597d706e	61	#define REGS_CAN0_BASE (0x40024000U) //!< Base address for CAN0.
bogdanm	82:6473597d706e	62
bogdanm	82:6473597d706e	63	//! @brief Table of base addresses for CAN instances.
bogdanm	82:6473597d706e	64	static const uint32_t __g_regs_CAN_base_addresses[] = {
bogdanm	82:6473597d706e	65	REGS_CAN0_BASE,
bogdanm	82:6473597d706e	66	};
bogdanm	82:6473597d706e	67
bogdanm	82:6473597d706e	68	//! @brief Get the base address of CAN by instance number.
bogdanm	82:6473597d706e	69	//! @param x CAN instance number, from 0 through 0.
bogdanm	82:6473597d706e	70	#define REGS_CAN_BASE(x) (__g_regs_CAN_base_addresses[(x)])
bogdanm	82:6473597d706e	71
bogdanm	82:6473597d706e	72	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	73	//! @param b Base address for an instance of CAN.
bogdanm	82:6473597d706e	74	#define REGS_CAN_INSTANCE(b) ((b) == REGS_CAN0_BASE ? HW_CAN0 : 0)
bogdanm	82:6473597d706e	75	#endif
bogdanm	82:6473597d706e	76	//@}
bogdanm	82:6473597d706e	77
bogdanm	82:6473597d706e	78	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	79	// HW_CAN_MCR - Module Configuration Register
bogdanm	82:6473597d706e	80	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	81
bogdanm	82:6473597d706e	82	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	83	/*!
bogdanm	82:6473597d706e	84	* @brief HW_CAN_MCR - Module Configuration Register (RW)
bogdanm	82:6473597d706e	85	*
bogdanm	82:6473597d706e	86	* Reset value: 0xD890000FU
bogdanm	82:6473597d706e	87	*
bogdanm	82:6473597d706e	88	* This register defines global system configurations, such as the module
bogdanm	82:6473597d706e	89	* operation modes and the maximum message buffer configuration.
bogdanm	82:6473597d706e	90	*/
bogdanm	82:6473597d706e	91	typedef union _hw_can_mcr
bogdanm	82:6473597d706e	92	{
bogdanm	82:6473597d706e	93	uint32_t U;
bogdanm	82:6473597d706e	94	struct _hw_can_mcr_bitfields
bogdanm	82:6473597d706e	95	{
bogdanm	82:6473597d706e	96	uint32_t MAXMB : 7; //!< [6:0] Number Of The Last Message Buffer
bogdanm	82:6473597d706e	97	uint32_t RESERVED0 : 1; //!< [7]
bogdanm	82:6473597d706e	98	uint32_t IDAM : 2; //!< [9:8] ID Acceptance Mode
bogdanm	82:6473597d706e	99	uint32_t RESERVED1 : 2; //!< [11:10]
bogdanm	82:6473597d706e	100	uint32_t AEN : 1; //!< [12] Abort Enable
bogdanm	82:6473597d706e	101	uint32_t LPRIOEN : 1; //!< [13] Local Priority Enable
bogdanm	82:6473597d706e	102	uint32_t RESERVED2 : 2; //!< [15:14]
bogdanm	82:6473597d706e	103	uint32_t IRMQ : 1; //!< [16] Individual Rx Masking And Queue Enable
bogdanm	82:6473597d706e	104	uint32_t SRXDIS : 1; //!< [17] Self Reception Disable
bogdanm	82:6473597d706e	105	uint32_t RESERVED3 : 1; //!< [18]
bogdanm	82:6473597d706e	106	uint32_t WAKSRC : 1; //!< [19] Wake Up Source
bogdanm	82:6473597d706e	107	uint32_t LPMACK : 1; //!< [20] Low-Power Mode Acknowledge
bogdanm	82:6473597d706e	108	uint32_t WRNEN : 1; //!< [21] Warning Interrupt Enable
bogdanm	82:6473597d706e	109	uint32_t SLFWAK : 1; //!< [22] Self Wake Up
bogdanm	82:6473597d706e	110	uint32_t SUPV : 1; //!< [23] Supervisor Mode
bogdanm	82:6473597d706e	111	uint32_t FRZACK : 1; //!< [24] Freeze Mode Acknowledge
bogdanm	82:6473597d706e	112	uint32_t SOFTRST : 1; //!< [25] Soft Reset
bogdanm	82:6473597d706e	113	uint32_t WAKMSK : 1; //!< [26] Wake Up Interrupt Mask
bogdanm	82:6473597d706e	114	uint32_t NOTRDY : 1; //!< [27] FlexCAN Not Ready
bogdanm	82:6473597d706e	115	uint32_t HALT : 1; //!< [28] Halt FlexCAN
bogdanm	82:6473597d706e	116	uint32_t RFEN : 1; //!< [29] Rx FIFO Enable
bogdanm	82:6473597d706e	117	uint32_t FRZ : 1; //!< [30] Freeze Enable
bogdanm	82:6473597d706e	118	uint32_t MDIS : 1; //!< [31] Module Disable
bogdanm	82:6473597d706e	119	} B;
bogdanm	82:6473597d706e	120	} hw_can_mcr_t;
bogdanm	82:6473597d706e	121	#endif
bogdanm	82:6473597d706e	122
bogdanm	82:6473597d706e	123	/*!
bogdanm	82:6473597d706e	124	* @name Constants and macros for entire CAN_MCR register
bogdanm	82:6473597d706e	125	*/
bogdanm	82:6473597d706e	126	//@{
bogdanm	82:6473597d706e	127	#define HW_CAN_MCR_ADDR(x) (REGS_CAN_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	128
bogdanm	82:6473597d706e	129	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	130	#define HW_CAN_MCR(x) ((__IO hw_can_mcr_t ) HW_CAN_MCR_ADDR(x))
bogdanm	82:6473597d706e	131	#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
bogdanm	82:6473597d706e	132	#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
bogdanm	82:6473597d706e	133	#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	134	#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	135	#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	136	#endif
bogdanm	82:6473597d706e	137	//@}
bogdanm	82:6473597d706e	138
bogdanm	82:6473597d706e	139	/*
bogdanm	82:6473597d706e	140	* Constants & macros for individual CAN_MCR bitfields
bogdanm	82:6473597d706e	141	*/
bogdanm	82:6473597d706e	142
bogdanm	82:6473597d706e	143	/*!
bogdanm	82:6473597d706e	144	* @name Register CAN_MCR, field MAXMB[6:0] (RW)
bogdanm	82:6473597d706e	145	*
bogdanm	82:6473597d706e	146	* This 7-bit field defines the number of the last Message Buffers that will
bogdanm	82:6473597d706e	147	* take part in the matching and arbitration processes. The reset value (0x0F) is
bogdanm	82:6473597d706e	148	* equivalent to a 16 MB configuration. This field can be written only in Freeze
bogdanm	82:6473597d706e	149	* mode because it is blocked by hardware in other modes. Number of the last MB =
bogdanm	82:6473597d706e	150	* MAXMB MAXMB must be programmed with a value smaller than the parameter
bogdanm	82:6473597d706e	151	* NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
bogdanm	82:6473597d706e	152	* (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
bogdanm	82:6473597d706e	153	* defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
bogdanm	82:6473597d706e	154	* of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
bogdanm	82:6473597d706e	155	* Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
bogdanm	82:6473597d706e	156	* Matching Timing").
bogdanm	82:6473597d706e	157	*/
bogdanm	82:6473597d706e	158	//@{
bogdanm	82:6473597d706e	159	#define BP_CAN_MCR_MAXMB (0U) //!< Bit position for CAN_MCR_MAXMB.
bogdanm	82:6473597d706e	160	#define BM_CAN_MCR_MAXMB (0x0000007FU) //!< Bit mask for CAN_MCR_MAXMB.
bogdanm	82:6473597d706e	161	#define BS_CAN_MCR_MAXMB (7U) //!< Bit field size in bits for CAN_MCR_MAXMB.
bogdanm	82:6473597d706e	162
bogdanm	82:6473597d706e	163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	164	//! @brief Read current value of the CAN_MCR_MAXMB field.
bogdanm	82:6473597d706e	165	#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
bogdanm	82:6473597d706e	166	#endif
bogdanm	82:6473597d706e	167
bogdanm	82:6473597d706e	168	//! @brief Format value for bitfield CAN_MCR_MAXMB.
bogdanm	82:6473597d706e	169	#define BF_CAN_MCR_MAXMB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MAXMB), uint32_t) & BM_CAN_MCR_MAXMB)
bogdanm	82:6473597d706e	170
bogdanm	82:6473597d706e	171	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	172	//! @brief Set the MAXMB field to a new value.
bogdanm	82:6473597d706e	173	#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) \| BF_CAN_MCR_MAXMB(v)))
bogdanm	82:6473597d706e	174	#endif
bogdanm	82:6473597d706e	175	//@}
bogdanm	82:6473597d706e	176
bogdanm	82:6473597d706e	177	/*!
bogdanm	82:6473597d706e	178	* @name Register CAN_MCR, field IDAM[9:8] (RW)
bogdanm	82:6473597d706e	179	*
bogdanm	82:6473597d706e	180	* This 2-bit field identifies the format of the Rx FIFO ID Filter Table
bogdanm	82:6473597d706e	181	* elements. Note that all elements of the table are configured at the same time by this
bogdanm	82:6473597d706e	182	* field (they are all the same format). See Section "Rx FIFO Structure". This
bogdanm	82:6473597d706e	183	* field can be written only in Freeze mode because it is blocked by hardware in
bogdanm	82:6473597d706e	184	* other modes.
bogdanm	82:6473597d706e	185	*
bogdanm	82:6473597d706e	186	* Values:
bogdanm	82:6473597d706e	187	* - 00 - Format A: One full ID (standard and extended) per ID Filter Table
bogdanm	82:6473597d706e	188	* element.
bogdanm	82:6473597d706e	189	* - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
bogdanm	82:6473597d706e	190	* extended) IDs per ID Filter Table element.
bogdanm	82:6473597d706e	191	* - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
bogdanm	82:6473597d706e	192	* - 11 - Format D: All frames rejected.
bogdanm	82:6473597d706e	193	*/
bogdanm	82:6473597d706e	194	//@{
bogdanm	82:6473597d706e	195	#define BP_CAN_MCR_IDAM (8U) //!< Bit position for CAN_MCR_IDAM.
bogdanm	82:6473597d706e	196	#define BM_CAN_MCR_IDAM (0x00000300U) //!< Bit mask for CAN_MCR_IDAM.
bogdanm	82:6473597d706e	197	#define BS_CAN_MCR_IDAM (2U) //!< Bit field size in bits for CAN_MCR_IDAM.
bogdanm	82:6473597d706e	198
bogdanm	82:6473597d706e	199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	200	//! @brief Read current value of the CAN_MCR_IDAM field.
bogdanm	82:6473597d706e	201	#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
bogdanm	82:6473597d706e	202	#endif
bogdanm	82:6473597d706e	203
bogdanm	82:6473597d706e	204	//! @brief Format value for bitfield CAN_MCR_IDAM.
bogdanm	82:6473597d706e	205	#define BF_CAN_MCR_IDAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IDAM), uint32_t) & BM_CAN_MCR_IDAM)
bogdanm	82:6473597d706e	206
bogdanm	82:6473597d706e	207	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	208	//! @brief Set the IDAM field to a new value.
bogdanm	82:6473597d706e	209	#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) \| BF_CAN_MCR_IDAM(v)))
bogdanm	82:6473597d706e	210	#endif
bogdanm	82:6473597d706e	211	//@}
bogdanm	82:6473597d706e	212
bogdanm	82:6473597d706e	213	/*!
bogdanm	82:6473597d706e	214	* @name Register CAN_MCR, field AEN[12] (RW)
bogdanm	82:6473597d706e	215	*
bogdanm	82:6473597d706e	216	* This bit is supplied for backwards compatibility with legacy applications.
bogdanm	82:6473597d706e	217	* When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
bogdanm	82:6473597d706e	218	* safe procedure for aborting a pending transmission, so that no frame is sent in
bogdanm	82:6473597d706e	219	* the CAN bus without notification. This bit can be written only in Freeze mode
bogdanm	82:6473597d706e	220	* because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
bogdanm	82:6473597d706e	221	* only the abort mechanism (see Section "Transmission Abort Mechanism") must be
bogdanm	82:6473597d706e	222	* used for updating Mailboxes configured for transmission. Writing the Abort code
bogdanm	82:6473597d706e	223	* into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
bogdanm	82:6473597d706e	224	* asserted.
bogdanm	82:6473597d706e	225	*
bogdanm	82:6473597d706e	226	* Values:
bogdanm	82:6473597d706e	227	* - 0 - Abort disabled.
bogdanm	82:6473597d706e	228	* - 1 - Abort enabled.
bogdanm	82:6473597d706e	229	*/
bogdanm	82:6473597d706e	230	//@{
bogdanm	82:6473597d706e	231	#define BP_CAN_MCR_AEN (12U) //!< Bit position for CAN_MCR_AEN.
bogdanm	82:6473597d706e	232	#define BM_CAN_MCR_AEN (0x00001000U) //!< Bit mask for CAN_MCR_AEN.
bogdanm	82:6473597d706e	233	#define BS_CAN_MCR_AEN (1U) //!< Bit field size in bits for CAN_MCR_AEN.
bogdanm	82:6473597d706e	234
bogdanm	82:6473597d706e	235	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	236	//! @brief Read current value of the CAN_MCR_AEN field.
bogdanm	82:6473597d706e	237	#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
bogdanm	82:6473597d706e	238	#endif
bogdanm	82:6473597d706e	239
bogdanm	82:6473597d706e	240	//! @brief Format value for bitfield CAN_MCR_AEN.
bogdanm	82:6473597d706e	241	#define BF_CAN_MCR_AEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_AEN), uint32_t) & BM_CAN_MCR_AEN)
bogdanm	82:6473597d706e	242
bogdanm	82:6473597d706e	243	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	244	//! @brief Set the AEN field to a new value.
bogdanm	82:6473597d706e	245	#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
bogdanm	82:6473597d706e	246	#endif
bogdanm	82:6473597d706e	247	//@}
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	/*!
bogdanm	82:6473597d706e	250	* @name Register CAN_MCR, field LPRIOEN[13] (RW)
bogdanm	82:6473597d706e	251	*
bogdanm	82:6473597d706e	252	* This bit is provided for backwards compatibility with legacy applications. It
bogdanm	82:6473597d706e	253	* controls whether the local priority feature is enabled or not. It is used to
bogdanm	82:6473597d706e	254	* expand the ID used during the arbitration process. With this expanded ID
bogdanm	82:6473597d706e	255	* concept, the arbitration process is done based on the full 32-bit word, but the
bogdanm	82:6473597d706e	256	* actual transmitted ID still has 11-bit for standard frames and 29-bit for
bogdanm	82:6473597d706e	257	* extended frames. This bit can be written only in Freeze mode because it is blocked by
bogdanm	82:6473597d706e	258	* hardware in other modes.
bogdanm	82:6473597d706e	259	*
bogdanm	82:6473597d706e	260	* Values:
bogdanm	82:6473597d706e	261	* - 0 - Local Priority disabled.
bogdanm	82:6473597d706e	262	* - 1 - Local Priority enabled.
bogdanm	82:6473597d706e	263	*/
bogdanm	82:6473597d706e	264	//@{
bogdanm	82:6473597d706e	265	#define BP_CAN_MCR_LPRIOEN (13U) //!< Bit position for CAN_MCR_LPRIOEN.
bogdanm	82:6473597d706e	266	#define BM_CAN_MCR_LPRIOEN (0x00002000U) //!< Bit mask for CAN_MCR_LPRIOEN.
bogdanm	82:6473597d706e	267	#define BS_CAN_MCR_LPRIOEN (1U) //!< Bit field size in bits for CAN_MCR_LPRIOEN.
bogdanm	82:6473597d706e	268
bogdanm	82:6473597d706e	269	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	270	//! @brief Read current value of the CAN_MCR_LPRIOEN field.
bogdanm	82:6473597d706e	271	#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
bogdanm	82:6473597d706e	272	#endif
bogdanm	82:6473597d706e	273
bogdanm	82:6473597d706e	274	//! @brief Format value for bitfield CAN_MCR_LPRIOEN.
bogdanm	82:6473597d706e	275	#define BF_CAN_MCR_LPRIOEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_LPRIOEN), uint32_t) & BM_CAN_MCR_LPRIOEN)
bogdanm	82:6473597d706e	276
bogdanm	82:6473597d706e	277	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	278	//! @brief Set the LPRIOEN field to a new value.
bogdanm	82:6473597d706e	279	#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
bogdanm	82:6473597d706e	280	#endif
bogdanm	82:6473597d706e	281	//@}
bogdanm	82:6473597d706e	282
bogdanm	82:6473597d706e	283	/*!
bogdanm	82:6473597d706e	284	* @name Register CAN_MCR, field IRMQ[16] (RW)
bogdanm	82:6473597d706e	285	*
bogdanm	82:6473597d706e	286	* This bit indicates whether Rx matching process will be based either on
bogdanm	82:6473597d706e	287	* individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
bogdanm	82:6473597d706e	288	* RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
bogdanm	82:6473597d706e	289	* blocked by hardware in other modes.
bogdanm	82:6473597d706e	290	*
bogdanm	82:6473597d706e	291	* Values:
bogdanm	82:6473597d706e	292	* - 0 - Individual Rx masking and queue feature are disabled. For backward
bogdanm	82:6473597d706e	293	* compatibility with legacy applications, the reading of C/S word locks the MB
bogdanm	82:6473597d706e	294	* even if it is EMPTY.
bogdanm	82:6473597d706e	295	* - 1 - Individual Rx masking and queue feature are enabled.
bogdanm	82:6473597d706e	296	*/
bogdanm	82:6473597d706e	297	//@{
bogdanm	82:6473597d706e	298	#define BP_CAN_MCR_IRMQ (16U) //!< Bit position for CAN_MCR_IRMQ.
bogdanm	82:6473597d706e	299	#define BM_CAN_MCR_IRMQ (0x00010000U) //!< Bit mask for CAN_MCR_IRMQ.
bogdanm	82:6473597d706e	300	#define BS_CAN_MCR_IRMQ (1U) //!< Bit field size in bits for CAN_MCR_IRMQ.
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	303	//! @brief Read current value of the CAN_MCR_IRMQ field.
bogdanm	82:6473597d706e	304	#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
bogdanm	82:6473597d706e	305	#endif
bogdanm	82:6473597d706e	306
bogdanm	82:6473597d706e	307	//! @brief Format value for bitfield CAN_MCR_IRMQ.
bogdanm	82:6473597d706e	308	#define BF_CAN_MCR_IRMQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IRMQ), uint32_t) & BM_CAN_MCR_IRMQ)
bogdanm	82:6473597d706e	309
bogdanm	82:6473597d706e	310	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	311	//! @brief Set the IRMQ field to a new value.
bogdanm	82:6473597d706e	312	#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
bogdanm	82:6473597d706e	313	#endif
bogdanm	82:6473597d706e	314	//@}
bogdanm	82:6473597d706e	315
bogdanm	82:6473597d706e	316	/*!
bogdanm	82:6473597d706e	317	* @name Register CAN_MCR, field SRXDIS[17] (RW)
bogdanm	82:6473597d706e	318	*
bogdanm	82:6473597d706e	319	* This bit defines whether FlexCAN is allowed to receive frames transmitted by
bogdanm	82:6473597d706e	320	* itself. If this bit is asserted, frames transmitted by the module will not be
bogdanm	82:6473597d706e	321	* stored in any MB, regardless if the MB is programmed with an ID that matches
bogdanm	82:6473597d706e	322	* the transmitted frame, and no interrupt flag or interrupt signal will be
bogdanm	82:6473597d706e	323	* generated due to the frame reception. This bit can be written only in Freeze mode
bogdanm	82:6473597d706e	324	* because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	325	*
bogdanm	82:6473597d706e	326	* Values:
bogdanm	82:6473597d706e	327	* - 0 - Self reception enabled.
bogdanm	82:6473597d706e	328	* - 1 - Self reception disabled.
bogdanm	82:6473597d706e	329	*/
bogdanm	82:6473597d706e	330	//@{
bogdanm	82:6473597d706e	331	#define BP_CAN_MCR_SRXDIS (17U) //!< Bit position for CAN_MCR_SRXDIS.
bogdanm	82:6473597d706e	332	#define BM_CAN_MCR_SRXDIS (0x00020000U) //!< Bit mask for CAN_MCR_SRXDIS.
bogdanm	82:6473597d706e	333	#define BS_CAN_MCR_SRXDIS (1U) //!< Bit field size in bits for CAN_MCR_SRXDIS.
bogdanm	82:6473597d706e	334
bogdanm	82:6473597d706e	335	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	336	//! @brief Read current value of the CAN_MCR_SRXDIS field.
bogdanm	82:6473597d706e	337	#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
bogdanm	82:6473597d706e	338	#endif
bogdanm	82:6473597d706e	339
bogdanm	82:6473597d706e	340	//! @brief Format value for bitfield CAN_MCR_SRXDIS.
bogdanm	82:6473597d706e	341	#define BF_CAN_MCR_SRXDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SRXDIS), uint32_t) & BM_CAN_MCR_SRXDIS)
bogdanm	82:6473597d706e	342
bogdanm	82:6473597d706e	343	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	344	//! @brief Set the SRXDIS field to a new value.
bogdanm	82:6473597d706e	345	#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
bogdanm	82:6473597d706e	346	#endif
bogdanm	82:6473597d706e	347	//@}
bogdanm	82:6473597d706e	348
bogdanm	82:6473597d706e	349	/*!
bogdanm	82:6473597d706e	350	* @name Register CAN_MCR, field WAKSRC[19] (RW)
bogdanm	82:6473597d706e	351	*
bogdanm	82:6473597d706e	352	* This bit defines whether the integrated low-pass filter is applied to protect
bogdanm	82:6473597d706e	353	* the Rx CAN input from spurious wake up. This bit can be written only in
bogdanm	82:6473597d706e	354	* Freeze mode because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	355	*
bogdanm	82:6473597d706e	356	* Values:
bogdanm	82:6473597d706e	357	* - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
bogdanm	82:6473597d706e	358	* edges on the CAN bus.
bogdanm	82:6473597d706e	359	* - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
bogdanm	82:6473597d706e	360	* edges on the CAN bus.
bogdanm	82:6473597d706e	361	*/
bogdanm	82:6473597d706e	362	//@{
bogdanm	82:6473597d706e	363	#define BP_CAN_MCR_WAKSRC (19U) //!< Bit position for CAN_MCR_WAKSRC.
bogdanm	82:6473597d706e	364	#define BM_CAN_MCR_WAKSRC (0x00080000U) //!< Bit mask for CAN_MCR_WAKSRC.
bogdanm	82:6473597d706e	365	#define BS_CAN_MCR_WAKSRC (1U) //!< Bit field size in bits for CAN_MCR_WAKSRC.
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	368	//! @brief Read current value of the CAN_MCR_WAKSRC field.
bogdanm	82:6473597d706e	369	#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
bogdanm	82:6473597d706e	370	#endif
bogdanm	82:6473597d706e	371
bogdanm	82:6473597d706e	372	//! @brief Format value for bitfield CAN_MCR_WAKSRC.
bogdanm	82:6473597d706e	373	#define BF_CAN_MCR_WAKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKSRC), uint32_t) & BM_CAN_MCR_WAKSRC)
bogdanm	82:6473597d706e	374
bogdanm	82:6473597d706e	375	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	376	//! @brief Set the WAKSRC field to a new value.
bogdanm	82:6473597d706e	377	#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
bogdanm	82:6473597d706e	378	#endif
bogdanm	82:6473597d706e	379	//@}
bogdanm	82:6473597d706e	380
bogdanm	82:6473597d706e	381	/*!
bogdanm	82:6473597d706e	382	* @name Register CAN_MCR, field LPMACK[20] (RO)
bogdanm	82:6473597d706e	383	*
bogdanm	82:6473597d706e	384	* This read-only bit indicates that FlexCAN is in a low-power mode (Disable
bogdanm	82:6473597d706e	385	* mode , Stop mode ). A low-power mode cannot be entered until all current
bogdanm	82:6473597d706e	386	* transmission or reception processes have finished, so the CPU can poll the LPMACK bit
bogdanm	82:6473597d706e	387	* to know when FlexCAN has actually entered low power mode. LPMACK will be
bogdanm	82:6473597d706e	388	* asserted within 180 CAN bits from the low-power mode request by the CPU, and
bogdanm	82:6473597d706e	389	* negated within 2 CAN bits after the low-power mode request removal (see Section
bogdanm	82:6473597d706e	390	* "Protocol Timing").
bogdanm	82:6473597d706e	391	*
bogdanm	82:6473597d706e	392	* Values:
bogdanm	82:6473597d706e	393	* - 0 - FlexCAN is not in a low-power mode.
bogdanm	82:6473597d706e	394	* - 1 - FlexCAN is in a low-power mode.
bogdanm	82:6473597d706e	395	*/
bogdanm	82:6473597d706e	396	//@{
bogdanm	82:6473597d706e	397	#define BP_CAN_MCR_LPMACK (20U) //!< Bit position for CAN_MCR_LPMACK.
bogdanm	82:6473597d706e	398	#define BM_CAN_MCR_LPMACK (0x00100000U) //!< Bit mask for CAN_MCR_LPMACK.
bogdanm	82:6473597d706e	399	#define BS_CAN_MCR_LPMACK (1U) //!< Bit field size in bits for CAN_MCR_LPMACK.
bogdanm	82:6473597d706e	400
bogdanm	82:6473597d706e	401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	402	//! @brief Read current value of the CAN_MCR_LPMACK field.
bogdanm	82:6473597d706e	403	#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
bogdanm	82:6473597d706e	404	#endif
bogdanm	82:6473597d706e	405	//@}
bogdanm	82:6473597d706e	406
bogdanm	82:6473597d706e	407	/*!
bogdanm	82:6473597d706e	408	* @name Register CAN_MCR, field WRNEN[21] (RW)
bogdanm	82:6473597d706e	409	*
bogdanm	82:6473597d706e	410	* When asserted, this bit enables the generation of the TWRNINT and RWRNINT
bogdanm	82:6473597d706e	411	* flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
bogdanm	82:6473597d706e	412	* RWRNINT flags will always be zero, independent of the values of the error
bogdanm	82:6473597d706e	413	* counters, and no warning interrupt will ever be generated. This bit can be written
bogdanm	82:6473597d706e	414	* only in Freeze mode because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	415	*
bogdanm	82:6473597d706e	416	* Values:
bogdanm	82:6473597d706e	417	* - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
bogdanm	82:6473597d706e	418	* error counters.
bogdanm	82:6473597d706e	419	* - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
bogdanm	82:6473597d706e	420	* transitions from less than 96 to greater than or equal to 96.
bogdanm	82:6473597d706e	421	*/
bogdanm	82:6473597d706e	422	//@{
bogdanm	82:6473597d706e	423	#define BP_CAN_MCR_WRNEN (21U) //!< Bit position for CAN_MCR_WRNEN.
bogdanm	82:6473597d706e	424	#define BM_CAN_MCR_WRNEN (0x00200000U) //!< Bit mask for CAN_MCR_WRNEN.
bogdanm	82:6473597d706e	425	#define BS_CAN_MCR_WRNEN (1U) //!< Bit field size in bits for CAN_MCR_WRNEN.
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	428	//! @brief Read current value of the CAN_MCR_WRNEN field.
bogdanm	82:6473597d706e	429	#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
bogdanm	82:6473597d706e	430	#endif
bogdanm	82:6473597d706e	431
bogdanm	82:6473597d706e	432	//! @brief Format value for bitfield CAN_MCR_WRNEN.
bogdanm	82:6473597d706e	433	#define BF_CAN_MCR_WRNEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WRNEN), uint32_t) & BM_CAN_MCR_WRNEN)
bogdanm	82:6473597d706e	434
bogdanm	82:6473597d706e	435	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	436	//! @brief Set the WRNEN field to a new value.
bogdanm	82:6473597d706e	437	#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
bogdanm	82:6473597d706e	438	#endif
bogdanm	82:6473597d706e	439	//@}
bogdanm	82:6473597d706e	440
bogdanm	82:6473597d706e	441	/*!
bogdanm	82:6473597d706e	442	* @name Register CAN_MCR, field SLFWAK[22] (RW)
bogdanm	82:6473597d706e	443	*
bogdanm	82:6473597d706e	444	* This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
bogdanm	82:6473597d706e	445	* other than Disable mode. When this feature is enabled, the FlexCAN module
bogdanm	82:6473597d706e	446	* monitors the bus for wake up event, that is, a recessive-to-dominant transition.
bogdanm	82:6473597d706e	447	* If a wake up event is detected during Stop mode, then FlexCAN generates, if
bogdanm	82:6473597d706e	448	* enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
bogdanm	82:6473597d706e	449	* globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
bogdanm	82:6473597d706e	450	* low-power mode other than Disable mode, this bit cannot be written as it is
bogdanm	82:6473597d706e	451	* blocked by hardware.
bogdanm	82:6473597d706e	452	*
bogdanm	82:6473597d706e	453	* Values:
bogdanm	82:6473597d706e	454	* - 0 - FlexCAN Self Wake Up feature is disabled.
bogdanm	82:6473597d706e	455	* - 1 - FlexCAN Self Wake Up feature is enabled.
bogdanm	82:6473597d706e	456	*/
bogdanm	82:6473597d706e	457	//@{
bogdanm	82:6473597d706e	458	#define BP_CAN_MCR_SLFWAK (22U) //!< Bit position for CAN_MCR_SLFWAK.
bogdanm	82:6473597d706e	459	#define BM_CAN_MCR_SLFWAK (0x00400000U) //!< Bit mask for CAN_MCR_SLFWAK.
bogdanm	82:6473597d706e	460	#define BS_CAN_MCR_SLFWAK (1U) //!< Bit field size in bits for CAN_MCR_SLFWAK.
bogdanm	82:6473597d706e	461
bogdanm	82:6473597d706e	462	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	463	//! @brief Read current value of the CAN_MCR_SLFWAK field.
bogdanm	82:6473597d706e	464	#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
bogdanm	82:6473597d706e	465	#endif
bogdanm	82:6473597d706e	466
bogdanm	82:6473597d706e	467	//! @brief Format value for bitfield CAN_MCR_SLFWAK.
bogdanm	82:6473597d706e	468	#define BF_CAN_MCR_SLFWAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SLFWAK), uint32_t) & BM_CAN_MCR_SLFWAK)
bogdanm	82:6473597d706e	469
bogdanm	82:6473597d706e	470	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	471	//! @brief Set the SLFWAK field to a new value.
bogdanm	82:6473597d706e	472	#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
bogdanm	82:6473597d706e	473	#endif
bogdanm	82:6473597d706e	474	//@}
bogdanm	82:6473597d706e	475
bogdanm	82:6473597d706e	476	/*!
bogdanm	82:6473597d706e	477	* @name Register CAN_MCR, field SUPV[23] (RW)
bogdanm	82:6473597d706e	478	*
bogdanm	82:6473597d706e	479	* This bit configures the FlexCAN to be either in Supervisor or User mode. The
bogdanm	82:6473597d706e	480	* registers affected by this bit are marked as S/U in the Access Type column of
bogdanm	82:6473597d706e	481	* the module memory map. Reset value of this bit is 1, so the affected registers
bogdanm	82:6473597d706e	482	* start with Supervisor access allowance only . This bit can be written only in
bogdanm	82:6473597d706e	483	* Freeze mode because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	484	*
bogdanm	82:6473597d706e	485	* Values:
bogdanm	82:6473597d706e	486	* - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
bogdanm	82:6473597d706e	487	* Unrestricted accesses .
bogdanm	82:6473597d706e	488	* - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
bogdanm	82:6473597d706e	489	* access. Unrestricted access behaves as though the access was done to an
bogdanm	82:6473597d706e	490	* unimplemented register location .
bogdanm	82:6473597d706e	491	*/
bogdanm	82:6473597d706e	492	//@{
bogdanm	82:6473597d706e	493	#define BP_CAN_MCR_SUPV (23U) //!< Bit position for CAN_MCR_SUPV.
bogdanm	82:6473597d706e	494	#define BM_CAN_MCR_SUPV (0x00800000U) //!< Bit mask for CAN_MCR_SUPV.
bogdanm	82:6473597d706e	495	#define BS_CAN_MCR_SUPV (1U) //!< Bit field size in bits for CAN_MCR_SUPV.
bogdanm	82:6473597d706e	496
bogdanm	82:6473597d706e	497	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	498	//! @brief Read current value of the CAN_MCR_SUPV field.
bogdanm	82:6473597d706e	499	#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
bogdanm	82:6473597d706e	500	#endif
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	//! @brief Format value for bitfield CAN_MCR_SUPV.
bogdanm	82:6473597d706e	503	#define BF_CAN_MCR_SUPV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SUPV), uint32_t) & BM_CAN_MCR_SUPV)
bogdanm	82:6473597d706e	504
bogdanm	82:6473597d706e	505	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	506	//! @brief Set the SUPV field to a new value.
bogdanm	82:6473597d706e	507	#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
bogdanm	82:6473597d706e	508	#endif
bogdanm	82:6473597d706e	509	//@}
bogdanm	82:6473597d706e	510
bogdanm	82:6473597d706e	511	/*!
bogdanm	82:6473597d706e	512	* @name Register CAN_MCR, field FRZACK[24] (RO)
bogdanm	82:6473597d706e	513	*
bogdanm	82:6473597d706e	514	* This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
bogdanm	82:6473597d706e	515	* is stopped. The Freeze mode request cannot be granted until current
bogdanm	82:6473597d706e	516	* transmission or reception processes have finished. Therefore the software can poll the
bogdanm	82:6473597d706e	517	* FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
bogdanm	82:6473597d706e	518	* Mode request is negated, then this bit is negated after the FlexCAN prescaler is
bogdanm	82:6473597d706e	519	* running again. If Freeze mode is requested while FlexCAN is in a low power
bogdanm	82:6473597d706e	520	* mode, then the FRZACK bit will be set only when the low-power mode is exited.
bogdanm	82:6473597d706e	521	* See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
bogdanm	82:6473597d706e	522	* freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
bogdanm	82:6473597d706e	523	* mode request removal (see Section "Protocol Timing").
bogdanm	82:6473597d706e	524	*
bogdanm	82:6473597d706e	525	* Values:
bogdanm	82:6473597d706e	526	* - 0 - FlexCAN not in Freeze mode, prescaler running.
bogdanm	82:6473597d706e	527	* - 1 - FlexCAN in Freeze mode, prescaler stopped.
bogdanm	82:6473597d706e	528	*/
bogdanm	82:6473597d706e	529	//@{
bogdanm	82:6473597d706e	530	#define BP_CAN_MCR_FRZACK (24U) //!< Bit position for CAN_MCR_FRZACK.
bogdanm	82:6473597d706e	531	#define BM_CAN_MCR_FRZACK (0x01000000U) //!< Bit mask for CAN_MCR_FRZACK.
bogdanm	82:6473597d706e	532	#define BS_CAN_MCR_FRZACK (1U) //!< Bit field size in bits for CAN_MCR_FRZACK.
bogdanm	82:6473597d706e	533
bogdanm	82:6473597d706e	534	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	535	//! @brief Read current value of the CAN_MCR_FRZACK field.
bogdanm	82:6473597d706e	536	#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
bogdanm	82:6473597d706e	537	#endif
bogdanm	82:6473597d706e	538	//@}
bogdanm	82:6473597d706e	539
bogdanm	82:6473597d706e	540	/*!
bogdanm	82:6473597d706e	541	* @name Register CAN_MCR, field SOFTRST[25] (RW)
bogdanm	82:6473597d706e	542	*
bogdanm	82:6473597d706e	543	* When this bit is asserted, FlexCAN resets its internal state machines and
bogdanm	82:6473597d706e	544	* some of the memory mapped registers. The following registers are reset: MCR
bogdanm	82:6473597d706e	545	* (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
bogdanm	82:6473597d706e	546	* CRCR. Configuration registers that control the interface to the CAN bus are
bogdanm	82:6473597d706e	547	* not affected by soft reset. The following registers are unaffected: CTRL1,
bogdanm	82:6473597d706e	548	* CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
bogdanm	82:6473597d706e	549	* Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
bogdanm	82:6473597d706e	550	* writes to the MCR Register, but it is also asserted when global soft reset is
bogdanm	82:6473597d706e	551	* requested at MCU level . Because soft reset is synchronous and has to follow a
bogdanm	82:6473597d706e	552	* request/acknowledge procedure across clock domains, it may take some time to
bogdanm	82:6473597d706e	553	* fully propagate its effect. The SOFTRST bit remains asserted while reset is
bogdanm	82:6473597d706e	554	* pending, and is automatically negated when reset completes. Therefore, software can
bogdanm	82:6473597d706e	555	* poll this bit to know when the soft reset has completed. Soft reset cannot be
bogdanm	82:6473597d706e	556	* applied while clocks are shut down in a low power mode. The module should be
bogdanm	82:6473597d706e	557	* first removed from low power mode, and then soft reset can be applied.
bogdanm	82:6473597d706e	558	*
bogdanm	82:6473597d706e	559	* Values:
bogdanm	82:6473597d706e	560	* - 0 - No reset request.
bogdanm	82:6473597d706e	561	* - 1 - Resets the registers affected by soft reset.
bogdanm	82:6473597d706e	562	*/
bogdanm	82:6473597d706e	563	//@{
bogdanm	82:6473597d706e	564	#define BP_CAN_MCR_SOFTRST (25U) //!< Bit position for CAN_MCR_SOFTRST.
bogdanm	82:6473597d706e	565	#define BM_CAN_MCR_SOFTRST (0x02000000U) //!< Bit mask for CAN_MCR_SOFTRST.
bogdanm	82:6473597d706e	566	#define BS_CAN_MCR_SOFTRST (1U) //!< Bit field size in bits for CAN_MCR_SOFTRST.
bogdanm	82:6473597d706e	567
bogdanm	82:6473597d706e	568	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	569	//! @brief Read current value of the CAN_MCR_SOFTRST field.
bogdanm	82:6473597d706e	570	#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
bogdanm	82:6473597d706e	571	#endif
bogdanm	82:6473597d706e	572
bogdanm	82:6473597d706e	573	//! @brief Format value for bitfield CAN_MCR_SOFTRST.
bogdanm	82:6473597d706e	574	#define BF_CAN_MCR_SOFTRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SOFTRST), uint32_t) & BM_CAN_MCR_SOFTRST)
bogdanm	82:6473597d706e	575
bogdanm	82:6473597d706e	576	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	577	//! @brief Set the SOFTRST field to a new value.
bogdanm	82:6473597d706e	578	#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
bogdanm	82:6473597d706e	579	#endif
bogdanm	82:6473597d706e	580	//@}
bogdanm	82:6473597d706e	581
bogdanm	82:6473597d706e	582	/*!
bogdanm	82:6473597d706e	583	* @name Register CAN_MCR, field WAKMSK[26] (RW)
bogdanm	82:6473597d706e	584	*
bogdanm	82:6473597d706e	585	* This bit enables the Wake Up Interrupt generation under Self Wake Up
bogdanm	82:6473597d706e	586	* mechanism.
bogdanm	82:6473597d706e	587	*
bogdanm	82:6473597d706e	588	* Values:
bogdanm	82:6473597d706e	589	* - 0 - Wake Up Interrupt is disabled.
bogdanm	82:6473597d706e	590	* - 1 - Wake Up Interrupt is enabled.
bogdanm	82:6473597d706e	591	*/
bogdanm	82:6473597d706e	592	//@{
bogdanm	82:6473597d706e	593	#define BP_CAN_MCR_WAKMSK (26U) //!< Bit position for CAN_MCR_WAKMSK.
bogdanm	82:6473597d706e	594	#define BM_CAN_MCR_WAKMSK (0x04000000U) //!< Bit mask for CAN_MCR_WAKMSK.
bogdanm	82:6473597d706e	595	#define BS_CAN_MCR_WAKMSK (1U) //!< Bit field size in bits for CAN_MCR_WAKMSK.
bogdanm	82:6473597d706e	596
bogdanm	82:6473597d706e	597	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	598	//! @brief Read current value of the CAN_MCR_WAKMSK field.
bogdanm	82:6473597d706e	599	#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
bogdanm	82:6473597d706e	600	#endif
bogdanm	82:6473597d706e	601
bogdanm	82:6473597d706e	602	//! @brief Format value for bitfield CAN_MCR_WAKMSK.
bogdanm	82:6473597d706e	603	#define BF_CAN_MCR_WAKMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKMSK), uint32_t) & BM_CAN_MCR_WAKMSK)
bogdanm	82:6473597d706e	604
bogdanm	82:6473597d706e	605	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	606	//! @brief Set the WAKMSK field to a new value.
bogdanm	82:6473597d706e	607	#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
bogdanm	82:6473597d706e	608	#endif
bogdanm	82:6473597d706e	609	//@}
bogdanm	82:6473597d706e	610
bogdanm	82:6473597d706e	611	/*!
bogdanm	82:6473597d706e	612	* @name Register CAN_MCR, field NOTRDY[27] (RO)
bogdanm	82:6473597d706e	613	*
bogdanm	82:6473597d706e	614	* This read-only bit indicates that FlexCAN is either in Disable mode , Stop
bogdanm	82:6473597d706e	615	* mode or Freeze mode. It is negated once FlexCAN has exited these modes.
bogdanm	82:6473597d706e	616	*
bogdanm	82:6473597d706e	617	* Values:
bogdanm	82:6473597d706e	618	* - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
bogdanm	82:6473597d706e	619	* mode.
bogdanm	82:6473597d706e	620	* - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
bogdanm	82:6473597d706e	621	*/
bogdanm	82:6473597d706e	622	//@{
bogdanm	82:6473597d706e	623	#define BP_CAN_MCR_NOTRDY (27U) //!< Bit position for CAN_MCR_NOTRDY.
bogdanm	82:6473597d706e	624	#define BM_CAN_MCR_NOTRDY (0x08000000U) //!< Bit mask for CAN_MCR_NOTRDY.
bogdanm	82:6473597d706e	625	#define BS_CAN_MCR_NOTRDY (1U) //!< Bit field size in bits for CAN_MCR_NOTRDY.
bogdanm	82:6473597d706e	626
bogdanm	82:6473597d706e	627	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	628	//! @brief Read current value of the CAN_MCR_NOTRDY field.
bogdanm	82:6473597d706e	629	#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
bogdanm	82:6473597d706e	630	#endif
bogdanm	82:6473597d706e	631	//@}
bogdanm	82:6473597d706e	632
bogdanm	82:6473597d706e	633	/*!
bogdanm	82:6473597d706e	634	* @name Register CAN_MCR, field HALT[28] (RW)
bogdanm	82:6473597d706e	635	*
bogdanm	82:6473597d706e	636	* Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
bogdanm	82:6473597d706e	637	* should clear it after initializing the Message Buffers and Control Register. No
bogdanm	82:6473597d706e	638	* reception or transmission is performed by FlexCAN before this bit is cleared.
bogdanm	82:6473597d706e	639	* Freeze mode cannot be entered while FlexCAN is in a low power mode.
bogdanm	82:6473597d706e	640	*
bogdanm	82:6473597d706e	641	* Values:
bogdanm	82:6473597d706e	642	* - 0 - No Freeze mode request.
bogdanm	82:6473597d706e	643	* - 1 - Enters Freeze mode if the FRZ bit is asserted.
bogdanm	82:6473597d706e	644	*/
bogdanm	82:6473597d706e	645	//@{
bogdanm	82:6473597d706e	646	#define BP_CAN_MCR_HALT (28U) //!< Bit position for CAN_MCR_HALT.
bogdanm	82:6473597d706e	647	#define BM_CAN_MCR_HALT (0x10000000U) //!< Bit mask for CAN_MCR_HALT.
bogdanm	82:6473597d706e	648	#define BS_CAN_MCR_HALT (1U) //!< Bit field size in bits for CAN_MCR_HALT.
bogdanm	82:6473597d706e	649
bogdanm	82:6473597d706e	650	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	651	//! @brief Read current value of the CAN_MCR_HALT field.
bogdanm	82:6473597d706e	652	#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
bogdanm	82:6473597d706e	653	#endif
bogdanm	82:6473597d706e	654
bogdanm	82:6473597d706e	655	//! @brief Format value for bitfield CAN_MCR_HALT.
bogdanm	82:6473597d706e	656	#define BF_CAN_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_HALT), uint32_t) & BM_CAN_MCR_HALT)
bogdanm	82:6473597d706e	657
bogdanm	82:6473597d706e	658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	659	//! @brief Set the HALT field to a new value.
bogdanm	82:6473597d706e	660	#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
bogdanm	82:6473597d706e	661	#endif
bogdanm	82:6473597d706e	662	//@}
bogdanm	82:6473597d706e	663
bogdanm	82:6473597d706e	664	/*!
bogdanm	82:6473597d706e	665	* @name Register CAN_MCR, field RFEN[29] (RW)
bogdanm	82:6473597d706e	666	*
bogdanm	82:6473597d706e	667	* This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
bogdanm	82:6473597d706e	668	* set, MBs 0 to 5 cannot be used for normal reception and transmission because
bogdanm	82:6473597d706e	669	* the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
bogdanm	82:6473597d706e	670	* as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
bogdanm	82:6473597d706e	671	* as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
bogdanm	82:6473597d706e	672	* minimum number of peripheral clocks per CAN bit as described in the table
bogdanm	82:6473597d706e	673	* "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
bogdanm	82:6473597d706e	674	* "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
bogdanm	82:6473597d706e	675	* because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	676	*
bogdanm	82:6473597d706e	677	* Values:
bogdanm	82:6473597d706e	678	* - 0 - Rx FIFO not enabled.
bogdanm	82:6473597d706e	679	* - 1 - Rx FIFO enabled.
bogdanm	82:6473597d706e	680	*/
bogdanm	82:6473597d706e	681	//@{
bogdanm	82:6473597d706e	682	#define BP_CAN_MCR_RFEN (29U) //!< Bit position for CAN_MCR_RFEN.
bogdanm	82:6473597d706e	683	#define BM_CAN_MCR_RFEN (0x20000000U) //!< Bit mask for CAN_MCR_RFEN.
bogdanm	82:6473597d706e	684	#define BS_CAN_MCR_RFEN (1U) //!< Bit field size in bits for CAN_MCR_RFEN.
bogdanm	82:6473597d706e	685
bogdanm	82:6473597d706e	686	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	687	//! @brief Read current value of the CAN_MCR_RFEN field.
bogdanm	82:6473597d706e	688	#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
bogdanm	82:6473597d706e	689	#endif
bogdanm	82:6473597d706e	690
bogdanm	82:6473597d706e	691	//! @brief Format value for bitfield CAN_MCR_RFEN.
bogdanm	82:6473597d706e	692	#define BF_CAN_MCR_RFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_RFEN), uint32_t) & BM_CAN_MCR_RFEN)
bogdanm	82:6473597d706e	693
bogdanm	82:6473597d706e	694	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	695	//! @brief Set the RFEN field to a new value.
bogdanm	82:6473597d706e	696	#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
bogdanm	82:6473597d706e	697	#endif
bogdanm	82:6473597d706e	698	//@}
bogdanm	82:6473597d706e	699
bogdanm	82:6473597d706e	700	/*!
bogdanm	82:6473597d706e	701	* @name Register CAN_MCR, field FRZ[30] (RW)
bogdanm	82:6473597d706e	702	*
bogdanm	82:6473597d706e	703	* The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
bogdanm	82:6473597d706e	704	* Register is set or when Debug mode is requested at MCU level . When FRZ is
bogdanm	82:6473597d706e	705	* asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
bogdanm	82:6473597d706e	706	* FlexCAN to exit from Freeze mode.
bogdanm	82:6473597d706e	707	*
bogdanm	82:6473597d706e	708	* Values:
bogdanm	82:6473597d706e	709	* - 0 - Not enabled to enter Freeze mode.
bogdanm	82:6473597d706e	710	* - 1 - Enabled to enter Freeze mode.
bogdanm	82:6473597d706e	711	*/
bogdanm	82:6473597d706e	712	//@{
bogdanm	82:6473597d706e	713	#define BP_CAN_MCR_FRZ (30U) //!< Bit position for CAN_MCR_FRZ.
bogdanm	82:6473597d706e	714	#define BM_CAN_MCR_FRZ (0x40000000U) //!< Bit mask for CAN_MCR_FRZ.
bogdanm	82:6473597d706e	715	#define BS_CAN_MCR_FRZ (1U) //!< Bit field size in bits for CAN_MCR_FRZ.
bogdanm	82:6473597d706e	716
bogdanm	82:6473597d706e	717	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	718	//! @brief Read current value of the CAN_MCR_FRZ field.
bogdanm	82:6473597d706e	719	#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
bogdanm	82:6473597d706e	720	#endif
bogdanm	82:6473597d706e	721
bogdanm	82:6473597d706e	722	//! @brief Format value for bitfield CAN_MCR_FRZ.
bogdanm	82:6473597d706e	723	#define BF_CAN_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_FRZ), uint32_t) & BM_CAN_MCR_FRZ)
bogdanm	82:6473597d706e	724
bogdanm	82:6473597d706e	725	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	726	//! @brief Set the FRZ field to a new value.
bogdanm	82:6473597d706e	727	#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
bogdanm	82:6473597d706e	728	#endif
bogdanm	82:6473597d706e	729	//@}
bogdanm	82:6473597d706e	730
bogdanm	82:6473597d706e	731	/*!
bogdanm	82:6473597d706e	732	* @name Register CAN_MCR, field MDIS[31] (RW)
bogdanm	82:6473597d706e	733	*
bogdanm	82:6473597d706e	734	* This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
bogdanm	82:6473597d706e	735	* disables the clocks to the CAN Protocol Engine and Controller Host Interface
bogdanm	82:6473597d706e	736	* sub-modules. This is the only bit within this register not affected by soft
bogdanm	82:6473597d706e	737	* reset.
bogdanm	82:6473597d706e	738	*
bogdanm	82:6473597d706e	739	* Values:
bogdanm	82:6473597d706e	740	* - 0 - Enable the FlexCAN module.
bogdanm	82:6473597d706e	741	* - 1 - Disable the FlexCAN module.
bogdanm	82:6473597d706e	742	*/
bogdanm	82:6473597d706e	743	//@{
bogdanm	82:6473597d706e	744	#define BP_CAN_MCR_MDIS (31U) //!< Bit position for CAN_MCR_MDIS.
bogdanm	82:6473597d706e	745	#define BM_CAN_MCR_MDIS (0x80000000U) //!< Bit mask for CAN_MCR_MDIS.
bogdanm	82:6473597d706e	746	#define BS_CAN_MCR_MDIS (1U) //!< Bit field size in bits for CAN_MCR_MDIS.
bogdanm	82:6473597d706e	747
bogdanm	82:6473597d706e	748	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	749	//! @brief Read current value of the CAN_MCR_MDIS field.
bogdanm	82:6473597d706e	750	#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
bogdanm	82:6473597d706e	751	#endif
bogdanm	82:6473597d706e	752
bogdanm	82:6473597d706e	753	//! @brief Format value for bitfield CAN_MCR_MDIS.
bogdanm	82:6473597d706e	754	#define BF_CAN_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MDIS), uint32_t) & BM_CAN_MCR_MDIS)
bogdanm	82:6473597d706e	755
bogdanm	82:6473597d706e	756	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	757	//! @brief Set the MDIS field to a new value.
bogdanm	82:6473597d706e	758	#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
bogdanm	82:6473597d706e	759	#endif
bogdanm	82:6473597d706e	760	//@}
bogdanm	82:6473597d706e	761
bogdanm	82:6473597d706e	762	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	763	// HW_CAN_CTRL1 - Control 1 register
bogdanm	82:6473597d706e	764	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	765
bogdanm	82:6473597d706e	766	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	767	/*!
bogdanm	82:6473597d706e	768	* @brief HW_CAN_CTRL1 - Control 1 register (RW)
bogdanm	82:6473597d706e	769	*
bogdanm	82:6473597d706e	770	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	771	*
bogdanm	82:6473597d706e	772	* This register is defined for specific FlexCAN control features related to the
bogdanm	82:6473597d706e	773	* CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
bogdanm	82:6473597d706e	774	* Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
bogdanm	82:6473597d706e	775	* (Bus-Off, Error, Warning). It also determines the Division Factor for the
bogdanm	82:6473597d706e	776	* clock prescaler.
bogdanm	82:6473597d706e	777	*/
bogdanm	82:6473597d706e	778	typedef union _hw_can_ctrl1
bogdanm	82:6473597d706e	779	{
bogdanm	82:6473597d706e	780	uint32_t U;
bogdanm	82:6473597d706e	781	struct _hw_can_ctrl1_bitfields
bogdanm	82:6473597d706e	782	{
bogdanm	82:6473597d706e	783	uint32_t PROPSEG : 3; //!< [2:0] Propagation Segment
bogdanm	82:6473597d706e	784	uint32_t LOM : 1; //!< [3] Listen-Only Mode
bogdanm	82:6473597d706e	785	uint32_t LBUF : 1; //!< [4] Lowest Buffer Transmitted First
bogdanm	82:6473597d706e	786	uint32_t TSYN : 1; //!< [5] Timer Sync
bogdanm	82:6473597d706e	787	uint32_t BOFFREC : 1; //!< [6] Bus Off Recovery
bogdanm	82:6473597d706e	788	uint32_t SMP : 1; //!< [7] CAN Bit Sampling
bogdanm	82:6473597d706e	789	uint32_t RESERVED0 : 2; //!< [9:8]
bogdanm	82:6473597d706e	790	uint32_t RWRNMSK : 1; //!< [10] Rx Warning Interrupt Mask
bogdanm	82:6473597d706e	791	uint32_t TWRNMSK : 1; //!< [11] Tx Warning Interrupt Mask
bogdanm	82:6473597d706e	792	uint32_t LPB : 1; //!< [12] Loop Back Mode
bogdanm	82:6473597d706e	793	uint32_t CLKSRC : 1; //!< [13] CAN Engine Clock Source
bogdanm	82:6473597d706e	794	uint32_t ERRMSK : 1; //!< [14] Error Mask
bogdanm	82:6473597d706e	795	uint32_t BOFFMSK : 1; //!< [15] Bus Off Mask
bogdanm	82:6473597d706e	796	uint32_t PSEG2 : 3; //!< [18:16] Phase Segment 2
bogdanm	82:6473597d706e	797	uint32_t PSEG1 : 3; //!< [21:19] Phase Segment 1
bogdanm	82:6473597d706e	798	uint32_t RJW : 2; //!< [23:22] Resync Jump Width
bogdanm	82:6473597d706e	799	uint32_t PRESDIV : 8; //!< [31:24] Prescaler Division Factor
bogdanm	82:6473597d706e	800	} B;
bogdanm	82:6473597d706e	801	} hw_can_ctrl1_t;
bogdanm	82:6473597d706e	802	#endif
bogdanm	82:6473597d706e	803
bogdanm	82:6473597d706e	804	/*!
bogdanm	82:6473597d706e	805	* @name Constants and macros for entire CAN_CTRL1 register
bogdanm	82:6473597d706e	806	*/
bogdanm	82:6473597d706e	807	//@{
bogdanm	82:6473597d706e	808	#define HW_CAN_CTRL1_ADDR(x) (REGS_CAN_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	809
bogdanm	82:6473597d706e	810	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	811	#define HW_CAN_CTRL1(x) ((__IO hw_can_ctrl1_t ) HW_CAN_CTRL1_ADDR(x))
bogdanm	82:6473597d706e	812	#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
bogdanm	82:6473597d706e	813	#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
bogdanm	82:6473597d706e	814	#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) \| (v)))
bogdanm	82:6473597d706e	815	#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	816	#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	817	#endif
bogdanm	82:6473597d706e	818	//@}
bogdanm	82:6473597d706e	819
bogdanm	82:6473597d706e	820	/*
bogdanm	82:6473597d706e	821	* Constants & macros for individual CAN_CTRL1 bitfields
bogdanm	82:6473597d706e	822	*/
bogdanm	82:6473597d706e	823
bogdanm	82:6473597d706e	824	/*!
bogdanm	82:6473597d706e	825	* @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
bogdanm	82:6473597d706e	826	*
bogdanm	82:6473597d706e	827	* This 3-bit field defines the length of the Propagation Segment in the bit
bogdanm	82:6473597d706e	828	* time. The valid programmable values are 0-7. This field can be written only in
bogdanm	82:6473597d706e	829	* Freeze mode because it is blocked by hardware in other modes. Propagation
bogdanm	82:6473597d706e	830	* Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
bogdanm	82:6473597d706e	831	*/
bogdanm	82:6473597d706e	832	//@{
bogdanm	82:6473597d706e	833	#define BP_CAN_CTRL1_PROPSEG (0U) //!< Bit position for CAN_CTRL1_PROPSEG.
bogdanm	82:6473597d706e	834	#define BM_CAN_CTRL1_PROPSEG (0x00000007U) //!< Bit mask for CAN_CTRL1_PROPSEG.
bogdanm	82:6473597d706e	835	#define BS_CAN_CTRL1_PROPSEG (3U) //!< Bit field size in bits for CAN_CTRL1_PROPSEG.
bogdanm	82:6473597d706e	836
bogdanm	82:6473597d706e	837	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	838	//! @brief Read current value of the CAN_CTRL1_PROPSEG field.
bogdanm	82:6473597d706e	839	#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
bogdanm	82:6473597d706e	840	#endif
bogdanm	82:6473597d706e	841
bogdanm	82:6473597d706e	842	//! @brief Format value for bitfield CAN_CTRL1_PROPSEG.
bogdanm	82:6473597d706e	843	#define BF_CAN_CTRL1_PROPSEG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PROPSEG), uint32_t) & BM_CAN_CTRL1_PROPSEG)
bogdanm	82:6473597d706e	844
bogdanm	82:6473597d706e	845	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	846	//! @brief Set the PROPSEG field to a new value.
bogdanm	82:6473597d706e	847	#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) \| BF_CAN_CTRL1_PROPSEG(v)))
bogdanm	82:6473597d706e	848	#endif
bogdanm	82:6473597d706e	849	//@}
bogdanm	82:6473597d706e	850
bogdanm	82:6473597d706e	851	/*!
bogdanm	82:6473597d706e	852	* @name Register CAN_CTRL1, field LOM[3] (RW)
bogdanm	82:6473597d706e	853	*
bogdanm	82:6473597d706e	854	* This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
bogdanm	82:6473597d706e	855	* transmission is disabled, all error counters are frozen and the module operates
bogdanm	82:6473597d706e	856	* in a CAN Error Passive mode. Only messages acknowledged by another CAN station
bogdanm	82:6473597d706e	857	* will be received. If FlexCAN detects a message that has not been acknowledged,
bogdanm	82:6473597d706e	858	* it will flag a BIT0 error without changing the REC, as if it was trying to
bogdanm	82:6473597d706e	859	* acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
bogdanm	82:6473597d706e	860	* state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
bogdanm	82:6473597d706e	861	* entered. There can be some delay between the Listen-Only mode request and
bogdanm	82:6473597d706e	862	* acknowledge. This bit can be written only in Freeze mode because it is blocked by
bogdanm	82:6473597d706e	863	* hardware in other modes.
bogdanm	82:6473597d706e	864	*
bogdanm	82:6473597d706e	865	* Values:
bogdanm	82:6473597d706e	866	* - 0 - Listen-Only mode is deactivated.
bogdanm	82:6473597d706e	867	* - 1 - FlexCAN module operates in Listen-Only mode.
bogdanm	82:6473597d706e	868	*/
bogdanm	82:6473597d706e	869	//@{
bogdanm	82:6473597d706e	870	#define BP_CAN_CTRL1_LOM (3U) //!< Bit position for CAN_CTRL1_LOM.
bogdanm	82:6473597d706e	871	#define BM_CAN_CTRL1_LOM (0x00000008U) //!< Bit mask for CAN_CTRL1_LOM.
bogdanm	82:6473597d706e	872	#define BS_CAN_CTRL1_LOM (1U) //!< Bit field size in bits for CAN_CTRL1_LOM.
bogdanm	82:6473597d706e	873
bogdanm	82:6473597d706e	874	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	875	//! @brief Read current value of the CAN_CTRL1_LOM field.
bogdanm	82:6473597d706e	876	#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
bogdanm	82:6473597d706e	877	#endif
bogdanm	82:6473597d706e	878
bogdanm	82:6473597d706e	879	//! @brief Format value for bitfield CAN_CTRL1_LOM.
bogdanm	82:6473597d706e	880	#define BF_CAN_CTRL1_LOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LOM), uint32_t) & BM_CAN_CTRL1_LOM)
bogdanm	82:6473597d706e	881
bogdanm	82:6473597d706e	882	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	883	//! @brief Set the LOM field to a new value.
bogdanm	82:6473597d706e	884	#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
bogdanm	82:6473597d706e	885	#endif
bogdanm	82:6473597d706e	886	//@}
bogdanm	82:6473597d706e	887
bogdanm	82:6473597d706e	888	/*!
bogdanm	82:6473597d706e	889	* @name Register CAN_CTRL1, field LBUF[4] (RW)
bogdanm	82:6473597d706e	890	*
bogdanm	82:6473597d706e	891	* This bit defines the ordering mechanism for Message Buffer transmission. When
bogdanm	82:6473597d706e	892	* asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
bogdanm	82:6473597d706e	893	* can be written only in Freeze mode because it is blocked by hardware in other
bogdanm	82:6473597d706e	894	* modes.
bogdanm	82:6473597d706e	895	*
bogdanm	82:6473597d706e	896	* Values:
bogdanm	82:6473597d706e	897	* - 0 - Buffer with highest priority is transmitted first.
bogdanm	82:6473597d706e	898	* - 1 - Lowest number buffer is transmitted first.
bogdanm	82:6473597d706e	899	*/
bogdanm	82:6473597d706e	900	//@{
bogdanm	82:6473597d706e	901	#define BP_CAN_CTRL1_LBUF (4U) //!< Bit position for CAN_CTRL1_LBUF.
bogdanm	82:6473597d706e	902	#define BM_CAN_CTRL1_LBUF (0x00000010U) //!< Bit mask for CAN_CTRL1_LBUF.
bogdanm	82:6473597d706e	903	#define BS_CAN_CTRL1_LBUF (1U) //!< Bit field size in bits for CAN_CTRL1_LBUF.
bogdanm	82:6473597d706e	904
bogdanm	82:6473597d706e	905	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	906	//! @brief Read current value of the CAN_CTRL1_LBUF field.
bogdanm	82:6473597d706e	907	#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
bogdanm	82:6473597d706e	908	#endif
bogdanm	82:6473597d706e	909
bogdanm	82:6473597d706e	910	//! @brief Format value for bitfield CAN_CTRL1_LBUF.
bogdanm	82:6473597d706e	911	#define BF_CAN_CTRL1_LBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LBUF), uint32_t) & BM_CAN_CTRL1_LBUF)
bogdanm	82:6473597d706e	912
bogdanm	82:6473597d706e	913	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	914	//! @brief Set the LBUF field to a new value.
bogdanm	82:6473597d706e	915	#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
bogdanm	82:6473597d706e	916	#endif
bogdanm	82:6473597d706e	917	//@}
bogdanm	82:6473597d706e	918
bogdanm	82:6473597d706e	919	/*!
bogdanm	82:6473597d706e	920	* @name Register CAN_CTRL1, field TSYN[5] (RW)
bogdanm	82:6473597d706e	921	*
bogdanm	82:6473597d706e	922	* This bit enables a mechanism that resets the free-running timer each time a
bogdanm	82:6473597d706e	923	* message is received in Message Buffer 0. This feature provides means to
bogdanm	82:6473597d706e	924	* synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
bogdanm	82:6473597d706e	925	* network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
bogdanm	82:6473597d706e	926	* available Mailbox, according to CTRL2[RFFN] setting, is used for timer
bogdanm	82:6473597d706e	927	* synchronization instead of MB0. This bit can be written only in Freeze mode because it is
bogdanm	82:6473597d706e	928	* blocked by hardware in other modes.
bogdanm	82:6473597d706e	929	*
bogdanm	82:6473597d706e	930	* Values:
bogdanm	82:6473597d706e	931	* - 0 - Timer Sync feature disabled
bogdanm	82:6473597d706e	932	* - 1 - Timer Sync feature enabled
bogdanm	82:6473597d706e	933	*/
bogdanm	82:6473597d706e	934	//@{
bogdanm	82:6473597d706e	935	#define BP_CAN_CTRL1_TSYN (5U) //!< Bit position for CAN_CTRL1_TSYN.
bogdanm	82:6473597d706e	936	#define BM_CAN_CTRL1_TSYN (0x00000020U) //!< Bit mask for CAN_CTRL1_TSYN.
bogdanm	82:6473597d706e	937	#define BS_CAN_CTRL1_TSYN (1U) //!< Bit field size in bits for CAN_CTRL1_TSYN.
bogdanm	82:6473597d706e	938
bogdanm	82:6473597d706e	939	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	940	//! @brief Read current value of the CAN_CTRL1_TSYN field.
bogdanm	82:6473597d706e	941	#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
bogdanm	82:6473597d706e	942	#endif
bogdanm	82:6473597d706e	943
bogdanm	82:6473597d706e	944	//! @brief Format value for bitfield CAN_CTRL1_TSYN.
bogdanm	82:6473597d706e	945	#define BF_CAN_CTRL1_TSYN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TSYN), uint32_t) & BM_CAN_CTRL1_TSYN)
bogdanm	82:6473597d706e	946
bogdanm	82:6473597d706e	947	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	948	//! @brief Set the TSYN field to a new value.
bogdanm	82:6473597d706e	949	#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
bogdanm	82:6473597d706e	950	#endif
bogdanm	82:6473597d706e	951	//@}
bogdanm	82:6473597d706e	952
bogdanm	82:6473597d706e	953	/*!
bogdanm	82:6473597d706e	954	* @name Register CAN_CTRL1, field BOFFREC[6] (RW)
bogdanm	82:6473597d706e	955	*
bogdanm	82:6473597d706e	956	* This bit defines how FlexCAN recovers from Bus Off state. If this bit is
bogdanm	82:6473597d706e	957	* negated, automatic recovering from Bus Off state occurs according to the CAN
bogdanm	82:6473597d706e	958	* Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
bogdanm	82:6473597d706e	959	* disabled and the module remains in Bus Off state until the bit is negated by the
bogdanm	82:6473597d706e	960	* user. If the negation occurs before 128 sequences of 11 recessive bits are
bogdanm	82:6473597d706e	961	* detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
bogdanm	82:6473597d706e	962	* never been asserted. If the negation occurs after 128 sequences of 11
bogdanm	82:6473597d706e	963	* recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
bogdanm	82:6473597d706e	964	* 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
bogdanm	82:6473597d706e	965	* be re-asserted again during Bus Off, but it will be effective only the next
bogdanm	82:6473597d706e	966	* time the module enters Bus Off. If BOFFREC was negated when the module entered
bogdanm	82:6473597d706e	967	* Bus Off, asserting it during Bus Off will not be effective for the current Bus
bogdanm	82:6473597d706e	968	* Off recovery.
bogdanm	82:6473597d706e	969	*
bogdanm	82:6473597d706e	970	* Values:
bogdanm	82:6473597d706e	971	* - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
bogdanm	82:6473597d706e	972	* 2.0 part B.
bogdanm	82:6473597d706e	973	* - 1 - Automatic recovering from Bus Off state disabled.
bogdanm	82:6473597d706e	974	*/
bogdanm	82:6473597d706e	975	//@{
bogdanm	82:6473597d706e	976	#define BP_CAN_CTRL1_BOFFREC (6U) //!< Bit position for CAN_CTRL1_BOFFREC.
bogdanm	82:6473597d706e	977	#define BM_CAN_CTRL1_BOFFREC (0x00000040U) //!< Bit mask for CAN_CTRL1_BOFFREC.
bogdanm	82:6473597d706e	978	#define BS_CAN_CTRL1_BOFFREC (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFREC.
bogdanm	82:6473597d706e	979
bogdanm	82:6473597d706e	980	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	981	//! @brief Read current value of the CAN_CTRL1_BOFFREC field.
bogdanm	82:6473597d706e	982	#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
bogdanm	82:6473597d706e	983	#endif
bogdanm	82:6473597d706e	984
bogdanm	82:6473597d706e	985	//! @brief Format value for bitfield CAN_CTRL1_BOFFREC.
bogdanm	82:6473597d706e	986	#define BF_CAN_CTRL1_BOFFREC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFREC), uint32_t) & BM_CAN_CTRL1_BOFFREC)
bogdanm	82:6473597d706e	987
bogdanm	82:6473597d706e	988	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	989	//! @brief Set the BOFFREC field to a new value.
bogdanm	82:6473597d706e	990	#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
bogdanm	82:6473597d706e	991	#endif
bogdanm	82:6473597d706e	992	//@}
bogdanm	82:6473597d706e	993
bogdanm	82:6473597d706e	994	/*!
bogdanm	82:6473597d706e	995	* @name Register CAN_CTRL1, field SMP[7] (RW)
bogdanm	82:6473597d706e	996	*
bogdanm	82:6473597d706e	997	* This bit defines the sampling mode of CAN bits at the Rx input. This bit can
bogdanm	82:6473597d706e	998	* be written only in Freeze mode because it is blocked by hardware in other
bogdanm	82:6473597d706e	999	* modes.
bogdanm	82:6473597d706e	1000	*
bogdanm	82:6473597d706e	1001	* Values:
bogdanm	82:6473597d706e	1002	* - 0 - Just one sample is used to determine the bit value.
bogdanm	82:6473597d706e	1003	* - 1 - Three samples are used to determine the value of the received bit: the
bogdanm	82:6473597d706e	1004	* regular one (sample point) and 2 preceding samples; a majority rule is
bogdanm	82:6473597d706e	1005	* used.
bogdanm	82:6473597d706e	1006	*/
bogdanm	82:6473597d706e	1007	//@{
bogdanm	82:6473597d706e	1008	#define BP_CAN_CTRL1_SMP (7U) //!< Bit position for CAN_CTRL1_SMP.
bogdanm	82:6473597d706e	1009	#define BM_CAN_CTRL1_SMP (0x00000080U) //!< Bit mask for CAN_CTRL1_SMP.
bogdanm	82:6473597d706e	1010	#define BS_CAN_CTRL1_SMP (1U) //!< Bit field size in bits for CAN_CTRL1_SMP.
bogdanm	82:6473597d706e	1011
bogdanm	82:6473597d706e	1012	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1013	//! @brief Read current value of the CAN_CTRL1_SMP field.
bogdanm	82:6473597d706e	1014	#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
bogdanm	82:6473597d706e	1015	#endif
bogdanm	82:6473597d706e	1016
bogdanm	82:6473597d706e	1017	//! @brief Format value for bitfield CAN_CTRL1_SMP.
bogdanm	82:6473597d706e	1018	#define BF_CAN_CTRL1_SMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_SMP), uint32_t) & BM_CAN_CTRL1_SMP)
bogdanm	82:6473597d706e	1019
bogdanm	82:6473597d706e	1020	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1021	//! @brief Set the SMP field to a new value.
bogdanm	82:6473597d706e	1022	#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
bogdanm	82:6473597d706e	1023	#endif
bogdanm	82:6473597d706e	1024	//@}
bogdanm	82:6473597d706e	1025
bogdanm	82:6473597d706e	1026	/*!
bogdanm	82:6473597d706e	1027	* @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
bogdanm	82:6473597d706e	1028	*
bogdanm	82:6473597d706e	1029	* This bit provides a mask for the Rx Warning Interrupt associated with the
bogdanm	82:6473597d706e	1030	* RWRNINT flag in the Error and Status Register. This bit is read as zero when
bogdanm	82:6473597d706e	1031	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
bogdanm	82:6473597d706e	1032	* asserted.
bogdanm	82:6473597d706e	1033	*
bogdanm	82:6473597d706e	1034	* Values:
bogdanm	82:6473597d706e	1035	* - 0 - Rx Warning Interrupt disabled.
bogdanm	82:6473597d706e	1036	* - 1 - Rx Warning Interrupt enabled.
bogdanm	82:6473597d706e	1037	*/
bogdanm	82:6473597d706e	1038	//@{
bogdanm	82:6473597d706e	1039	#define BP_CAN_CTRL1_RWRNMSK (10U) //!< Bit position for CAN_CTRL1_RWRNMSK.
bogdanm	82:6473597d706e	1040	#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) //!< Bit mask for CAN_CTRL1_RWRNMSK.
bogdanm	82:6473597d706e	1041	#define BS_CAN_CTRL1_RWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_RWRNMSK.
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1044	//! @brief Read current value of the CAN_CTRL1_RWRNMSK field.
bogdanm	82:6473597d706e	1045	#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
bogdanm	82:6473597d706e	1046	#endif
bogdanm	82:6473597d706e	1047
bogdanm	82:6473597d706e	1048	//! @brief Format value for bitfield CAN_CTRL1_RWRNMSK.
bogdanm	82:6473597d706e	1049	#define BF_CAN_CTRL1_RWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RWRNMSK), uint32_t) & BM_CAN_CTRL1_RWRNMSK)
bogdanm	82:6473597d706e	1050
bogdanm	82:6473597d706e	1051	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1052	//! @brief Set the RWRNMSK field to a new value.
bogdanm	82:6473597d706e	1053	#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
bogdanm	82:6473597d706e	1054	#endif
bogdanm	82:6473597d706e	1055	//@}
bogdanm	82:6473597d706e	1056
bogdanm	82:6473597d706e	1057	/*!
bogdanm	82:6473597d706e	1058	* @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
bogdanm	82:6473597d706e	1059	*
bogdanm	82:6473597d706e	1060	* This bit provides a mask for the Tx Warning Interrupt associated with the
bogdanm	82:6473597d706e	1061	* TWRNINT flag in the Error and Status Register. This bit is read as zero when
bogdanm	82:6473597d706e	1062	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
bogdanm	82:6473597d706e	1063	* asserted.
bogdanm	82:6473597d706e	1064	*
bogdanm	82:6473597d706e	1065	* Values:
bogdanm	82:6473597d706e	1066	* - 0 - Tx Warning Interrupt disabled.
bogdanm	82:6473597d706e	1067	* - 1 - Tx Warning Interrupt enabled.
bogdanm	82:6473597d706e	1068	*/
bogdanm	82:6473597d706e	1069	//@{
bogdanm	82:6473597d706e	1070	#define BP_CAN_CTRL1_TWRNMSK (11U) //!< Bit position for CAN_CTRL1_TWRNMSK.
bogdanm	82:6473597d706e	1071	#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) //!< Bit mask for CAN_CTRL1_TWRNMSK.
bogdanm	82:6473597d706e	1072	#define BS_CAN_CTRL1_TWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_TWRNMSK.
bogdanm	82:6473597d706e	1073
bogdanm	82:6473597d706e	1074	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1075	//! @brief Read current value of the CAN_CTRL1_TWRNMSK field.
bogdanm	82:6473597d706e	1076	#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
bogdanm	82:6473597d706e	1077	#endif
bogdanm	82:6473597d706e	1078
bogdanm	82:6473597d706e	1079	//! @brief Format value for bitfield CAN_CTRL1_TWRNMSK.
bogdanm	82:6473597d706e	1080	#define BF_CAN_CTRL1_TWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TWRNMSK), uint32_t) & BM_CAN_CTRL1_TWRNMSK)
bogdanm	82:6473597d706e	1081
bogdanm	82:6473597d706e	1082	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1083	//! @brief Set the TWRNMSK field to a new value.
bogdanm	82:6473597d706e	1084	#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
bogdanm	82:6473597d706e	1085	#endif
bogdanm	82:6473597d706e	1086	//@}
bogdanm	82:6473597d706e	1087
bogdanm	82:6473597d706e	1088	/*!
bogdanm	82:6473597d706e	1089	* @name Register CAN_CTRL1, field LPB[12] (RW)
bogdanm	82:6473597d706e	1090	*
bogdanm	82:6473597d706e	1091	* This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
bogdanm	82:6473597d706e	1092	* FlexCAN performs an internal loop back that can be used for self test operation.
bogdanm	82:6473597d706e	1093	* The bit stream output of the transmitter is fed back internally to the receiver
bogdanm	82:6473597d706e	1094	* input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
bogdanm	82:6473597d706e	1095	* recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
bogdanm	82:6473597d706e	1096	* and treats its own transmitted message as a message received from a remote
bogdanm	82:6473597d706e	1097	* node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
bogdanm	82:6473597d706e	1098	* frame acknowledge field, generating an internal acknowledge bit to ensure proper
bogdanm	82:6473597d706e	1099	* reception of its own message. Both transmit and receive interrupts are
bogdanm	82:6473597d706e	1100	* generated. This bit can be written only in Freeze mode because it is blocked by
bogdanm	82:6473597d706e	1101	* hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
bogdanm	82:6473597d706e	1102	* this will impede the self reception of a transmitted message.
bogdanm	82:6473597d706e	1103	*
bogdanm	82:6473597d706e	1104	* Values:
bogdanm	82:6473597d706e	1105	* - 0 - Loop Back disabled.
bogdanm	82:6473597d706e	1106	* - 1 - Loop Back enabled.
bogdanm	82:6473597d706e	1107	*/
bogdanm	82:6473597d706e	1108	//@{
bogdanm	82:6473597d706e	1109	#define BP_CAN_CTRL1_LPB (12U) //!< Bit position for CAN_CTRL1_LPB.
bogdanm	82:6473597d706e	1110	#define BM_CAN_CTRL1_LPB (0x00001000U) //!< Bit mask for CAN_CTRL1_LPB.
bogdanm	82:6473597d706e	1111	#define BS_CAN_CTRL1_LPB (1U) //!< Bit field size in bits for CAN_CTRL1_LPB.
bogdanm	82:6473597d706e	1112
bogdanm	82:6473597d706e	1113	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1114	//! @brief Read current value of the CAN_CTRL1_LPB field.
bogdanm	82:6473597d706e	1115	#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
bogdanm	82:6473597d706e	1116	#endif
bogdanm	82:6473597d706e	1117
bogdanm	82:6473597d706e	1118	//! @brief Format value for bitfield CAN_CTRL1_LPB.
bogdanm	82:6473597d706e	1119	#define BF_CAN_CTRL1_LPB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LPB), uint32_t) & BM_CAN_CTRL1_LPB)
bogdanm	82:6473597d706e	1120
bogdanm	82:6473597d706e	1121	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1122	//! @brief Set the LPB field to a new value.
bogdanm	82:6473597d706e	1123	#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
bogdanm	82:6473597d706e	1124	#endif
bogdanm	82:6473597d706e	1125	//@}
bogdanm	82:6473597d706e	1126
bogdanm	82:6473597d706e	1127	/*!
bogdanm	82:6473597d706e	1128	* @name Register CAN_CTRL1, field CLKSRC[13] (RW)
bogdanm	82:6473597d706e	1129	*
bogdanm	82:6473597d706e	1130	* This bit selects the clock source to the CAN Protocol Engine (PE) to be
bogdanm	82:6473597d706e	1131	* either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
bogdanm	82:6473597d706e	1132	* The selected clock is the one fed to the prescaler to generate the Serial Clock
bogdanm	82:6473597d706e	1133	* (Sclock). In order to guarantee reliable operation, this bit can be written
bogdanm	82:6473597d706e	1134	* only in Disable mode because it is blocked by hardware in other modes. See
bogdanm	82:6473597d706e	1135	* Section "Protocol Timing".
bogdanm	82:6473597d706e	1136	*
bogdanm	82:6473597d706e	1137	* Values:
bogdanm	82:6473597d706e	1138	* - 0 - The CAN engine clock source is the oscillator clock. Under this
bogdanm	82:6473597d706e	1139	* condition, the oscillator clock frequency must be lower than the bus clock.
bogdanm	82:6473597d706e	1140	* - 1 - The CAN engine clock source is the peripheral clock.
bogdanm	82:6473597d706e	1141	*/
bogdanm	82:6473597d706e	1142	//@{
bogdanm	82:6473597d706e	1143	#define BP_CAN_CTRL1_CLKSRC (13U) //!< Bit position for CAN_CTRL1_CLKSRC.
bogdanm	82:6473597d706e	1144	#define BM_CAN_CTRL1_CLKSRC (0x00002000U) //!< Bit mask for CAN_CTRL1_CLKSRC.
bogdanm	82:6473597d706e	1145	#define BS_CAN_CTRL1_CLKSRC (1U) //!< Bit field size in bits for CAN_CTRL1_CLKSRC.
bogdanm	82:6473597d706e	1146
bogdanm	82:6473597d706e	1147	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1148	//! @brief Read current value of the CAN_CTRL1_CLKSRC field.
bogdanm	82:6473597d706e	1149	#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
bogdanm	82:6473597d706e	1150	#endif
bogdanm	82:6473597d706e	1151
bogdanm	82:6473597d706e	1152	//! @brief Format value for bitfield CAN_CTRL1_CLKSRC.
bogdanm	82:6473597d706e	1153	#define BF_CAN_CTRL1_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_CLKSRC), uint32_t) & BM_CAN_CTRL1_CLKSRC)
bogdanm	82:6473597d706e	1154
bogdanm	82:6473597d706e	1155	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1156	//! @brief Set the CLKSRC field to a new value.
bogdanm	82:6473597d706e	1157	#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
bogdanm	82:6473597d706e	1158	#endif
bogdanm	82:6473597d706e	1159	//@}
bogdanm	82:6473597d706e	1160
bogdanm	82:6473597d706e	1161	/*!
bogdanm	82:6473597d706e	1162	* @name Register CAN_CTRL1, field ERRMSK[14] (RW)
bogdanm	82:6473597d706e	1163	*
bogdanm	82:6473597d706e	1164	* This bit provides a mask for the Error Interrupt.
bogdanm	82:6473597d706e	1165	*
bogdanm	82:6473597d706e	1166	* Values:
bogdanm	82:6473597d706e	1167	* - 0 - Error interrupt disabled.
bogdanm	82:6473597d706e	1168	* - 1 - Error interrupt enabled.
bogdanm	82:6473597d706e	1169	*/
bogdanm	82:6473597d706e	1170	//@{
bogdanm	82:6473597d706e	1171	#define BP_CAN_CTRL1_ERRMSK (14U) //!< Bit position for CAN_CTRL1_ERRMSK.
bogdanm	82:6473597d706e	1172	#define BM_CAN_CTRL1_ERRMSK (0x00004000U) //!< Bit mask for CAN_CTRL1_ERRMSK.
bogdanm	82:6473597d706e	1173	#define BS_CAN_CTRL1_ERRMSK (1U) //!< Bit field size in bits for CAN_CTRL1_ERRMSK.
bogdanm	82:6473597d706e	1174
bogdanm	82:6473597d706e	1175	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1176	//! @brief Read current value of the CAN_CTRL1_ERRMSK field.
bogdanm	82:6473597d706e	1177	#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
bogdanm	82:6473597d706e	1178	#endif
bogdanm	82:6473597d706e	1179
bogdanm	82:6473597d706e	1180	//! @brief Format value for bitfield CAN_CTRL1_ERRMSK.
bogdanm	82:6473597d706e	1181	#define BF_CAN_CTRL1_ERRMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_ERRMSK), uint32_t) & BM_CAN_CTRL1_ERRMSK)
bogdanm	82:6473597d706e	1182
bogdanm	82:6473597d706e	1183	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1184	//! @brief Set the ERRMSK field to a new value.
bogdanm	82:6473597d706e	1185	#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
bogdanm	82:6473597d706e	1186	#endif
bogdanm	82:6473597d706e	1187	//@}
bogdanm	82:6473597d706e	1188
bogdanm	82:6473597d706e	1189	/*!
bogdanm	82:6473597d706e	1190	* @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
bogdanm	82:6473597d706e	1191	*
bogdanm	82:6473597d706e	1192	* This bit provides a mask for the Bus Off Interrupt.
bogdanm	82:6473597d706e	1193	*
bogdanm	82:6473597d706e	1194	* Values:
bogdanm	82:6473597d706e	1195	* - 0 - Bus Off interrupt disabled.
bogdanm	82:6473597d706e	1196	* - 1 - Bus Off interrupt enabled.
bogdanm	82:6473597d706e	1197	*/
bogdanm	82:6473597d706e	1198	//@{
bogdanm	82:6473597d706e	1199	#define BP_CAN_CTRL1_BOFFMSK (15U) //!< Bit position for CAN_CTRL1_BOFFMSK.
bogdanm	82:6473597d706e	1200	#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) //!< Bit mask for CAN_CTRL1_BOFFMSK.
bogdanm	82:6473597d706e	1201	#define BS_CAN_CTRL1_BOFFMSK (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFMSK.
bogdanm	82:6473597d706e	1202
bogdanm	82:6473597d706e	1203	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1204	//! @brief Read current value of the CAN_CTRL1_BOFFMSK field.
bogdanm	82:6473597d706e	1205	#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
bogdanm	82:6473597d706e	1206	#endif
bogdanm	82:6473597d706e	1207
bogdanm	82:6473597d706e	1208	//! @brief Format value for bitfield CAN_CTRL1_BOFFMSK.
bogdanm	82:6473597d706e	1209	#define BF_CAN_CTRL1_BOFFMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFMSK), uint32_t) & BM_CAN_CTRL1_BOFFMSK)
bogdanm	82:6473597d706e	1210
bogdanm	82:6473597d706e	1211	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1212	//! @brief Set the BOFFMSK field to a new value.
bogdanm	82:6473597d706e	1213	#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
bogdanm	82:6473597d706e	1214	#endif
bogdanm	82:6473597d706e	1215	//@}
bogdanm	82:6473597d706e	1216
bogdanm	82:6473597d706e	1217	/*!
bogdanm	82:6473597d706e	1218	* @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
bogdanm	82:6473597d706e	1219	*
bogdanm	82:6473597d706e	1220	* This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
bogdanm	82:6473597d706e	1221	* time. The valid programmable values are 1-7. This field can be written only in
bogdanm	82:6473597d706e	1222	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
bogdanm	82:6473597d706e	1223	* Segment 2 = (PSEG2 + 1) * Time-Quanta.
bogdanm	82:6473597d706e	1224	*/
bogdanm	82:6473597d706e	1225	//@{
bogdanm	82:6473597d706e	1226	#define BP_CAN_CTRL1_PSEG2 (16U) //!< Bit position for CAN_CTRL1_PSEG2.
bogdanm	82:6473597d706e	1227	#define BM_CAN_CTRL1_PSEG2 (0x00070000U) //!< Bit mask for CAN_CTRL1_PSEG2.
bogdanm	82:6473597d706e	1228	#define BS_CAN_CTRL1_PSEG2 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG2.
bogdanm	82:6473597d706e	1229
bogdanm	82:6473597d706e	1230	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1231	//! @brief Read current value of the CAN_CTRL1_PSEG2 field.
bogdanm	82:6473597d706e	1232	#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
bogdanm	82:6473597d706e	1233	#endif
bogdanm	82:6473597d706e	1234
bogdanm	82:6473597d706e	1235	//! @brief Format value for bitfield CAN_CTRL1_PSEG2.
bogdanm	82:6473597d706e	1236	#define BF_CAN_CTRL1_PSEG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG2), uint32_t) & BM_CAN_CTRL1_PSEG2)
bogdanm	82:6473597d706e	1237
bogdanm	82:6473597d706e	1238	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1239	//! @brief Set the PSEG2 field to a new value.
bogdanm	82:6473597d706e	1240	#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) \| BF_CAN_CTRL1_PSEG2(v)))
bogdanm	82:6473597d706e	1241	#endif
bogdanm	82:6473597d706e	1242	//@}
bogdanm	82:6473597d706e	1243
bogdanm	82:6473597d706e	1244	/*!
bogdanm	82:6473597d706e	1245	* @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
bogdanm	82:6473597d706e	1246	*
bogdanm	82:6473597d706e	1247	* This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
bogdanm	82:6473597d706e	1248	* time. The valid programmable values are 0-7. This field can be written only in
bogdanm	82:6473597d706e	1249	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
bogdanm	82:6473597d706e	1250	* Segment 1 = (PSEG1 + 1) * Time-Quanta.
bogdanm	82:6473597d706e	1251	*/
bogdanm	82:6473597d706e	1252	//@{
bogdanm	82:6473597d706e	1253	#define BP_CAN_CTRL1_PSEG1 (19U) //!< Bit position for CAN_CTRL1_PSEG1.
bogdanm	82:6473597d706e	1254	#define BM_CAN_CTRL1_PSEG1 (0x00380000U) //!< Bit mask for CAN_CTRL1_PSEG1.
bogdanm	82:6473597d706e	1255	#define BS_CAN_CTRL1_PSEG1 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG1.
bogdanm	82:6473597d706e	1256
bogdanm	82:6473597d706e	1257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1258	//! @brief Read current value of the CAN_CTRL1_PSEG1 field.
bogdanm	82:6473597d706e	1259	#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
bogdanm	82:6473597d706e	1260	#endif
bogdanm	82:6473597d706e	1261
bogdanm	82:6473597d706e	1262	//! @brief Format value for bitfield CAN_CTRL1_PSEG1.
bogdanm	82:6473597d706e	1263	#define BF_CAN_CTRL1_PSEG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG1), uint32_t) & BM_CAN_CTRL1_PSEG1)
bogdanm	82:6473597d706e	1264
bogdanm	82:6473597d706e	1265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1266	//! @brief Set the PSEG1 field to a new value.
bogdanm	82:6473597d706e	1267	#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) \| BF_CAN_CTRL1_PSEG1(v)))
bogdanm	82:6473597d706e	1268	#endif
bogdanm	82:6473597d706e	1269	//@}
bogdanm	82:6473597d706e	1270
bogdanm	82:6473597d706e	1271	/*!
bogdanm	82:6473597d706e	1272	* @name Register CAN_CTRL1, field RJW[23:22] (RW)
bogdanm	82:6473597d706e	1273	*
bogdanm	82:6473597d706e	1274	* This 2-bit field defines the maximum number of time quanta that a bit time
bogdanm	82:6473597d706e	1275	* can be changed by one re-synchronization. One time quantum is equal to the
bogdanm	82:6473597d706e	1276	* Sclock period. The valid programmable values are 0-3. This field can be written
bogdanm	82:6473597d706e	1277	* only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
bogdanm	82:6473597d706e	1278	* Width = RJW + 1.
bogdanm	82:6473597d706e	1279	*/
bogdanm	82:6473597d706e	1280	//@{
bogdanm	82:6473597d706e	1281	#define BP_CAN_CTRL1_RJW (22U) //!< Bit position for CAN_CTRL1_RJW.
bogdanm	82:6473597d706e	1282	#define BM_CAN_CTRL1_RJW (0x00C00000U) //!< Bit mask for CAN_CTRL1_RJW.
bogdanm	82:6473597d706e	1283	#define BS_CAN_CTRL1_RJW (2U) //!< Bit field size in bits for CAN_CTRL1_RJW.
bogdanm	82:6473597d706e	1284
bogdanm	82:6473597d706e	1285	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1286	//! @brief Read current value of the CAN_CTRL1_RJW field.
bogdanm	82:6473597d706e	1287	#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
bogdanm	82:6473597d706e	1288	#endif
bogdanm	82:6473597d706e	1289
bogdanm	82:6473597d706e	1290	//! @brief Format value for bitfield CAN_CTRL1_RJW.
bogdanm	82:6473597d706e	1291	#define BF_CAN_CTRL1_RJW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RJW), uint32_t) & BM_CAN_CTRL1_RJW)
bogdanm	82:6473597d706e	1292
bogdanm	82:6473597d706e	1293	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1294	//! @brief Set the RJW field to a new value.
bogdanm	82:6473597d706e	1295	#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) \| BF_CAN_CTRL1_RJW(v)))
bogdanm	82:6473597d706e	1296	#endif
bogdanm	82:6473597d706e	1297	//@}
bogdanm	82:6473597d706e	1298
bogdanm	82:6473597d706e	1299	/*!
bogdanm	82:6473597d706e	1300	* @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
bogdanm	82:6473597d706e	1301	*
bogdanm	82:6473597d706e	1302	* This 8-bit field defines the ratio between the PE clock frequency and the
bogdanm	82:6473597d706e	1303	* Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
bogdanm	82:6473597d706e	1304	* the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
bogdanm	82:6473597d706e	1305	* clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
bogdanm	82:6473597d706e	1306	* Sclock frequency equal to the PE clock frequency divided by 256. See Section
bogdanm	82:6473597d706e	1307	* "Protocol Timing". This field can be written only in Freeze mode because it is
bogdanm	82:6473597d706e	1308	* blocked by hardware in other modes. Sclock frequency = PE clock frequency /
bogdanm	82:6473597d706e	1309	* (PRESDIV + 1)
bogdanm	82:6473597d706e	1310	*/
bogdanm	82:6473597d706e	1311	//@{
bogdanm	82:6473597d706e	1312	#define BP_CAN_CTRL1_PRESDIV (24U) //!< Bit position for CAN_CTRL1_PRESDIV.
bogdanm	82:6473597d706e	1313	#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) //!< Bit mask for CAN_CTRL1_PRESDIV.
bogdanm	82:6473597d706e	1314	#define BS_CAN_CTRL1_PRESDIV (8U) //!< Bit field size in bits for CAN_CTRL1_PRESDIV.
bogdanm	82:6473597d706e	1315
bogdanm	82:6473597d706e	1316	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1317	//! @brief Read current value of the CAN_CTRL1_PRESDIV field.
bogdanm	82:6473597d706e	1318	#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
bogdanm	82:6473597d706e	1319	#endif
bogdanm	82:6473597d706e	1320
bogdanm	82:6473597d706e	1321	//! @brief Format value for bitfield CAN_CTRL1_PRESDIV.
bogdanm	82:6473597d706e	1322	#define BF_CAN_CTRL1_PRESDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PRESDIV), uint32_t) & BM_CAN_CTRL1_PRESDIV)
bogdanm	82:6473597d706e	1323
bogdanm	82:6473597d706e	1324	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1325	//! @brief Set the PRESDIV field to a new value.
bogdanm	82:6473597d706e	1326	#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) \| BF_CAN_CTRL1_PRESDIV(v)))
bogdanm	82:6473597d706e	1327	#endif
bogdanm	82:6473597d706e	1328	//@}
bogdanm	82:6473597d706e	1329
bogdanm	82:6473597d706e	1330	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1331	// HW_CAN_TIMER - Free Running Timer
bogdanm	82:6473597d706e	1332	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1333
bogdanm	82:6473597d706e	1334	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1335	/*!
bogdanm	82:6473597d706e	1336	* @brief HW_CAN_TIMER - Free Running Timer (RW)
bogdanm	82:6473597d706e	1337	*
bogdanm	82:6473597d706e	1338	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1339	*
bogdanm	82:6473597d706e	1340	* This register represents a 16-bit free running counter that can be read and
bogdanm	82:6473597d706e	1341	* written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
bogdanm	82:6473597d706e	1342	* 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
bogdanm	82:6473597d706e	1343	* defines the baud rate on the CAN bus. During a message transmission/reception,
bogdanm	82:6473597d706e	1344	* it increments by one for each bit that is received or transmitted. When there
bogdanm	82:6473597d706e	1345	* is no message on the bus, it counts using the previously programmed baud
bogdanm	82:6473597d706e	1346	* rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
bogdanm	82:6473597d706e	1347	* timer value is captured when the second bit of the identifier field of any frame
bogdanm	82:6473597d706e	1348	* is on the CAN bus. This captured value is written into the Time Stamp entry
bogdanm	82:6473597d706e	1349	* in a message buffer after a successful reception or transmission of a message.
bogdanm	82:6473597d706e	1350	* If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
bogdanm	82:6473597d706e	1351	* received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
bogdanm	82:6473597d706e	1352	* can write to this register anytime. However, if the write occurs at the same
bogdanm	82:6473597d706e	1353	* time that the Timer is being reset by a reception in the first Mailbox, then
bogdanm	82:6473597d706e	1354	* the write value is discarded. Reading this register affects the Mailbox
bogdanm	82:6473597d706e	1355	* Unlocking procedure; see Section "Mailbox Lock Mechanism".
bogdanm	82:6473597d706e	1356	*/
bogdanm	82:6473597d706e	1357	typedef union _hw_can_timer
bogdanm	82:6473597d706e	1358	{
bogdanm	82:6473597d706e	1359	uint32_t U;
bogdanm	82:6473597d706e	1360	struct _hw_can_timer_bitfields
bogdanm	82:6473597d706e	1361	{
bogdanm	82:6473597d706e	1362	uint32_t TIMER : 16; //!< [15:0] Timer Value
bogdanm	82:6473597d706e	1363	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1364	} B;
bogdanm	82:6473597d706e	1365	} hw_can_timer_t;
bogdanm	82:6473597d706e	1366	#endif
bogdanm	82:6473597d706e	1367
bogdanm	82:6473597d706e	1368	/*!
bogdanm	82:6473597d706e	1369	* @name Constants and macros for entire CAN_TIMER register
bogdanm	82:6473597d706e	1370	*/
bogdanm	82:6473597d706e	1371	//@{
bogdanm	82:6473597d706e	1372	#define HW_CAN_TIMER_ADDR(x) (REGS_CAN_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	1373
bogdanm	82:6473597d706e	1374	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1375	#define HW_CAN_TIMER(x) ((__IO hw_can_timer_t ) HW_CAN_TIMER_ADDR(x))
bogdanm	82:6473597d706e	1376	#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
bogdanm	82:6473597d706e	1377	#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
bogdanm	82:6473597d706e	1378	#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) \| (v)))
bogdanm	82:6473597d706e	1379	#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1380	#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1381	#endif
bogdanm	82:6473597d706e	1382	//@}
bogdanm	82:6473597d706e	1383
bogdanm	82:6473597d706e	1384	/*
bogdanm	82:6473597d706e	1385	* Constants & macros for individual CAN_TIMER bitfields
bogdanm	82:6473597d706e	1386	*/
bogdanm	82:6473597d706e	1387
bogdanm	82:6473597d706e	1388	/*!
bogdanm	82:6473597d706e	1389	* @name Register CAN_TIMER, field TIMER[15:0] (RW)
bogdanm	82:6473597d706e	1390	*
bogdanm	82:6473597d706e	1391	* Contains the free-running counter value.
bogdanm	82:6473597d706e	1392	*/
bogdanm	82:6473597d706e	1393	//@{
bogdanm	82:6473597d706e	1394	#define BP_CAN_TIMER_TIMER (0U) //!< Bit position for CAN_TIMER_TIMER.
bogdanm	82:6473597d706e	1395	#define BM_CAN_TIMER_TIMER (0x0000FFFFU) //!< Bit mask for CAN_TIMER_TIMER.
bogdanm	82:6473597d706e	1396	#define BS_CAN_TIMER_TIMER (16U) //!< Bit field size in bits for CAN_TIMER_TIMER.
bogdanm	82:6473597d706e	1397
bogdanm	82:6473597d706e	1398	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1399	//! @brief Read current value of the CAN_TIMER_TIMER field.
bogdanm	82:6473597d706e	1400	#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
bogdanm	82:6473597d706e	1401	#endif
bogdanm	82:6473597d706e	1402
bogdanm	82:6473597d706e	1403	//! @brief Format value for bitfield CAN_TIMER_TIMER.
bogdanm	82:6473597d706e	1404	#define BF_CAN_TIMER_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_TIMER_TIMER), uint32_t) & BM_CAN_TIMER_TIMER)
bogdanm	82:6473597d706e	1405
bogdanm	82:6473597d706e	1406	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1407	//! @brief Set the TIMER field to a new value.
bogdanm	82:6473597d706e	1408	#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) \| BF_CAN_TIMER_TIMER(v)))
bogdanm	82:6473597d706e	1409	#endif
bogdanm	82:6473597d706e	1410	//@}
bogdanm	82:6473597d706e	1411
bogdanm	82:6473597d706e	1412	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1413	// HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
bogdanm	82:6473597d706e	1414	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1415
bogdanm	82:6473597d706e	1416	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1417	/*!
bogdanm	82:6473597d706e	1418	* @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
bogdanm	82:6473597d706e	1419	*
bogdanm	82:6473597d706e	1420	* Reset value: 0xFFFFFFFFU
bogdanm	82:6473597d706e	1421	*
bogdanm	82:6473597d706e	1422	* This register is located in RAM. RXMGMASK is provided for legacy application
bogdanm	82:6473597d706e	1423	* support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
bogdanm	82:6473597d706e	1424	* the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
bogdanm	82:6473597d706e	1425	* mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
bogdanm	82:6473597d706e	1426	* mask registers. This register can only be written in Freeze mode as it is
bogdanm	82:6473597d706e	1427	* blocked by hardware in other modes.
bogdanm	82:6473597d706e	1428	*/
bogdanm	82:6473597d706e	1429	typedef union _hw_can_rxmgmask
bogdanm	82:6473597d706e	1430	{
bogdanm	82:6473597d706e	1431	uint32_t U;
bogdanm	82:6473597d706e	1432	struct _hw_can_rxmgmask_bitfields
bogdanm	82:6473597d706e	1433	{
bogdanm	82:6473597d706e	1434	uint32_t MG : 32; //!< [31:0] Rx Mailboxes Global Mask Bits
bogdanm	82:6473597d706e	1435	} B;
bogdanm	82:6473597d706e	1436	} hw_can_rxmgmask_t;
bogdanm	82:6473597d706e	1437	#endif
bogdanm	82:6473597d706e	1438
bogdanm	82:6473597d706e	1439	/*!
bogdanm	82:6473597d706e	1440	* @name Constants and macros for entire CAN_RXMGMASK register
bogdanm	82:6473597d706e	1441	*/
bogdanm	82:6473597d706e	1442	//@{
bogdanm	82:6473597d706e	1443	#define HW_CAN_RXMGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x10U)
bogdanm	82:6473597d706e	1444
bogdanm	82:6473597d706e	1445	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1446	#define HW_CAN_RXMGMASK(x) ((__IO hw_can_rxmgmask_t ) HW_CAN_RXMGMASK_ADDR(x))
bogdanm	82:6473597d706e	1447	#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
bogdanm	82:6473597d706e	1448	#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
bogdanm	82:6473597d706e	1449	#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) \| (v)))
bogdanm	82:6473597d706e	1450	#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1451	#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1452	#endif
bogdanm	82:6473597d706e	1453	//@}
bogdanm	82:6473597d706e	1454
bogdanm	82:6473597d706e	1455	/*
bogdanm	82:6473597d706e	1456	* Constants & macros for individual CAN_RXMGMASK bitfields
bogdanm	82:6473597d706e	1457	*/
bogdanm	82:6473597d706e	1458
bogdanm	82:6473597d706e	1459	/*!
bogdanm	82:6473597d706e	1460	* @name Register CAN_RXMGMASK, field MG[31:0] (RW)
bogdanm	82:6473597d706e	1461	*
bogdanm	82:6473597d706e	1462	* These bits mask the Mailbox filter bits. Note that the alignment with the ID
bogdanm	82:6473597d706e	1463	* word of the Mailbox is not perfect as the two most significant MG bits affect
bogdanm	82:6473597d706e	1464	* the fields RTR and IDE, which are located in the Control and Status word of
bogdanm	82:6473597d706e	1465	* the Mailbox. The following table shows in detail which MG bits mask each Mailbox
bogdanm	82:6473597d706e	1466	* filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
bogdanm	82:6473597d706e	1467	* auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
bogdanm	82:6473597d706e	1468	* Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
bogdanm	82:6473597d706e	1469	* CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
bogdanm	82:6473597d706e	1470	* of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
bogdanm	82:6473597d706e	1471	* of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
bogdanm	82:6473597d706e	1472	* MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
bogdanm	82:6473597d706e	1473	* MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
bogdanm	82:6473597d706e	1474	*
bogdanm	82:6473597d706e	1475	* Values:
bogdanm	82:6473597d706e	1476	* - 0 - The corresponding bit in the filter is "don't care."
bogdanm	82:6473597d706e	1477	* - 1 - The corresponding bit in the filter is checked.
bogdanm	82:6473597d706e	1478	*/
bogdanm	82:6473597d706e	1479	//@{
bogdanm	82:6473597d706e	1480	#define BP_CAN_RXMGMASK_MG (0U) //!< Bit position for CAN_RXMGMASK_MG.
bogdanm	82:6473597d706e	1481	#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) //!< Bit mask for CAN_RXMGMASK_MG.
bogdanm	82:6473597d706e	1482	#define BS_CAN_RXMGMASK_MG (32U) //!< Bit field size in bits for CAN_RXMGMASK_MG.
bogdanm	82:6473597d706e	1483
bogdanm	82:6473597d706e	1484	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1485	//! @brief Read current value of the CAN_RXMGMASK_MG field.
bogdanm	82:6473597d706e	1486	#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
bogdanm	82:6473597d706e	1487	#endif
bogdanm	82:6473597d706e	1488
bogdanm	82:6473597d706e	1489	//! @brief Format value for bitfield CAN_RXMGMASK_MG.
bogdanm	82:6473597d706e	1490	#define BF_CAN_RXMGMASK_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXMGMASK_MG), uint32_t) & BM_CAN_RXMGMASK_MG)
bogdanm	82:6473597d706e	1491
bogdanm	82:6473597d706e	1492	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1493	//! @brief Set the MG field to a new value.
bogdanm	82:6473597d706e	1494	#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
bogdanm	82:6473597d706e	1495	#endif
bogdanm	82:6473597d706e	1496	//@}
bogdanm	82:6473597d706e	1497
bogdanm	82:6473597d706e	1498	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1499	// HW_CAN_RX14MASK - Rx 14 Mask register
bogdanm	82:6473597d706e	1500	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1501
bogdanm	82:6473597d706e	1502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1503	/*!
bogdanm	82:6473597d706e	1504	* @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
bogdanm	82:6473597d706e	1505	*
bogdanm	82:6473597d706e	1506	* Reset value: 0xFFFFFFFFU
bogdanm	82:6473597d706e	1507	*
bogdanm	82:6473597d706e	1508	* This register is located in RAM. RX14MASK is provided for legacy application
bogdanm	82:6473597d706e	1509	* support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
bogdanm	82:6473597d706e	1510	* is used to mask the filter fields of Message Buffer 14. This register can only
bogdanm	82:6473597d706e	1511	* be programmed while the module is in Freeze mode as it is blocked by hardware
bogdanm	82:6473597d706e	1512	* in other modes.
bogdanm	82:6473597d706e	1513	*/
bogdanm	82:6473597d706e	1514	typedef union _hw_can_rx14mask
bogdanm	82:6473597d706e	1515	{
bogdanm	82:6473597d706e	1516	uint32_t U;
bogdanm	82:6473597d706e	1517	struct _hw_can_rx14mask_bitfields
bogdanm	82:6473597d706e	1518	{
bogdanm	82:6473597d706e	1519	uint32_t RX14M : 32; //!< [31:0] Rx Buffer 14 Mask Bits
bogdanm	82:6473597d706e	1520	} B;
bogdanm	82:6473597d706e	1521	} hw_can_rx14mask_t;
bogdanm	82:6473597d706e	1522	#endif
bogdanm	82:6473597d706e	1523
bogdanm	82:6473597d706e	1524	/*!
bogdanm	82:6473597d706e	1525	* @name Constants and macros for entire CAN_RX14MASK register
bogdanm	82:6473597d706e	1526	*/
bogdanm	82:6473597d706e	1527	//@{
bogdanm	82:6473597d706e	1528	#define HW_CAN_RX14MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x14U)
bogdanm	82:6473597d706e	1529
bogdanm	82:6473597d706e	1530	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1531	#define HW_CAN_RX14MASK(x) ((__IO hw_can_rx14mask_t ) HW_CAN_RX14MASK_ADDR(x))
bogdanm	82:6473597d706e	1532	#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
bogdanm	82:6473597d706e	1533	#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
bogdanm	82:6473597d706e	1534	#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) \| (v)))
bogdanm	82:6473597d706e	1535	#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1536	#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1537	#endif
bogdanm	82:6473597d706e	1538	//@}
bogdanm	82:6473597d706e	1539
bogdanm	82:6473597d706e	1540	/*
bogdanm	82:6473597d706e	1541	* Constants & macros for individual CAN_RX14MASK bitfields
bogdanm	82:6473597d706e	1542	*/
bogdanm	82:6473597d706e	1543
bogdanm	82:6473597d706e	1544	/*!
bogdanm	82:6473597d706e	1545	* @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
bogdanm	82:6473597d706e	1546	*
bogdanm	82:6473597d706e	1547	* Each mask bit masks the corresponding Mailbox 14 filter field in the same way
bogdanm	82:6473597d706e	1548	* that RXMGMASK masks other Mailboxes' filters. See the description of the
bogdanm	82:6473597d706e	1549	* CAN_RXMGMASK register.
bogdanm	82:6473597d706e	1550	*
bogdanm	82:6473597d706e	1551	* Values:
bogdanm	82:6473597d706e	1552	* - 0 - The corresponding bit in the filter is "don't care."
bogdanm	82:6473597d706e	1553	* - 1 - The corresponding bit in the filter is checked.
bogdanm	82:6473597d706e	1554	*/
bogdanm	82:6473597d706e	1555	//@{
bogdanm	82:6473597d706e	1556	#define BP_CAN_RX14MASK_RX14M (0U) //!< Bit position for CAN_RX14MASK_RX14M.
bogdanm	82:6473597d706e	1557	#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) //!< Bit mask for CAN_RX14MASK_RX14M.
bogdanm	82:6473597d706e	1558	#define BS_CAN_RX14MASK_RX14M (32U) //!< Bit field size in bits for CAN_RX14MASK_RX14M.
bogdanm	82:6473597d706e	1559
bogdanm	82:6473597d706e	1560	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1561	//! @brief Read current value of the CAN_RX14MASK_RX14M field.
bogdanm	82:6473597d706e	1562	#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
bogdanm	82:6473597d706e	1563	#endif
bogdanm	82:6473597d706e	1564
bogdanm	82:6473597d706e	1565	//! @brief Format value for bitfield CAN_RX14MASK_RX14M.
bogdanm	82:6473597d706e	1566	#define BF_CAN_RX14MASK_RX14M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX14MASK_RX14M), uint32_t) & BM_CAN_RX14MASK_RX14M)
bogdanm	82:6473597d706e	1567
bogdanm	82:6473597d706e	1568	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1569	//! @brief Set the RX14M field to a new value.
bogdanm	82:6473597d706e	1570	#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
bogdanm	82:6473597d706e	1571	#endif
bogdanm	82:6473597d706e	1572	//@}
bogdanm	82:6473597d706e	1573
bogdanm	82:6473597d706e	1574	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1575	// HW_CAN_RX15MASK - Rx 15 Mask register
bogdanm	82:6473597d706e	1576	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1577
bogdanm	82:6473597d706e	1578	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1579	/*!
bogdanm	82:6473597d706e	1580	* @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
bogdanm	82:6473597d706e	1581	*
bogdanm	82:6473597d706e	1582	* Reset value: 0xFFFFFFFFU
bogdanm	82:6473597d706e	1583	*
bogdanm	82:6473597d706e	1584	* This register is located in RAM. RX15MASK is provided for legacy application
bogdanm	82:6473597d706e	1585	* support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
bogdanm	82:6473597d706e	1586	* is used to mask the filter fields of Message Buffer 15. This register can be
bogdanm	82:6473597d706e	1587	* programmed only while the module is in Freeze mode because it is blocked by
bogdanm	82:6473597d706e	1588	* hardware in other modes.
bogdanm	82:6473597d706e	1589	*/
bogdanm	82:6473597d706e	1590	typedef union _hw_can_rx15mask
bogdanm	82:6473597d706e	1591	{
bogdanm	82:6473597d706e	1592	uint32_t U;
bogdanm	82:6473597d706e	1593	struct _hw_can_rx15mask_bitfields
bogdanm	82:6473597d706e	1594	{
bogdanm	82:6473597d706e	1595	uint32_t RX15M : 32; //!< [31:0] Rx Buffer 15 Mask Bits
bogdanm	82:6473597d706e	1596	} B;
bogdanm	82:6473597d706e	1597	} hw_can_rx15mask_t;
bogdanm	82:6473597d706e	1598	#endif
bogdanm	82:6473597d706e	1599
bogdanm	82:6473597d706e	1600	/*!
bogdanm	82:6473597d706e	1601	* @name Constants and macros for entire CAN_RX15MASK register
bogdanm	82:6473597d706e	1602	*/
bogdanm	82:6473597d706e	1603	//@{
bogdanm	82:6473597d706e	1604	#define HW_CAN_RX15MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x18U)
bogdanm	82:6473597d706e	1605
bogdanm	82:6473597d706e	1606	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1607	#define HW_CAN_RX15MASK(x) ((__IO hw_can_rx15mask_t ) HW_CAN_RX15MASK_ADDR(x))
bogdanm	82:6473597d706e	1608	#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
bogdanm	82:6473597d706e	1609	#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
bogdanm	82:6473597d706e	1610	#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) \| (v)))
bogdanm	82:6473597d706e	1611	#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1612	#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1613	#endif
bogdanm	82:6473597d706e	1614	//@}
bogdanm	82:6473597d706e	1615
bogdanm	82:6473597d706e	1616	/*
bogdanm	82:6473597d706e	1617	* Constants & macros for individual CAN_RX15MASK bitfields
bogdanm	82:6473597d706e	1618	*/
bogdanm	82:6473597d706e	1619
bogdanm	82:6473597d706e	1620	/*!
bogdanm	82:6473597d706e	1621	* @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
bogdanm	82:6473597d706e	1622	*
bogdanm	82:6473597d706e	1623	* Each mask bit masks the corresponding Mailbox 15 filter field in the same way
bogdanm	82:6473597d706e	1624	* that RXMGMASK masks other Mailboxes' filters. See the description of the
bogdanm	82:6473597d706e	1625	* CAN_RXMGMASK register.
bogdanm	82:6473597d706e	1626	*
bogdanm	82:6473597d706e	1627	* Values:
bogdanm	82:6473597d706e	1628	* - 0 - The corresponding bit in the filter is "don't care."
bogdanm	82:6473597d706e	1629	* - 1 - The corresponding bit in the filter is checked.
bogdanm	82:6473597d706e	1630	*/
bogdanm	82:6473597d706e	1631	//@{
bogdanm	82:6473597d706e	1632	#define BP_CAN_RX15MASK_RX15M (0U) //!< Bit position for CAN_RX15MASK_RX15M.
bogdanm	82:6473597d706e	1633	#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) //!< Bit mask for CAN_RX15MASK_RX15M.
bogdanm	82:6473597d706e	1634	#define BS_CAN_RX15MASK_RX15M (32U) //!< Bit field size in bits for CAN_RX15MASK_RX15M.
bogdanm	82:6473597d706e	1635
bogdanm	82:6473597d706e	1636	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1637	//! @brief Read current value of the CAN_RX15MASK_RX15M field.
bogdanm	82:6473597d706e	1638	#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
bogdanm	82:6473597d706e	1639	#endif
bogdanm	82:6473597d706e	1640
bogdanm	82:6473597d706e	1641	//! @brief Format value for bitfield CAN_RX15MASK_RX15M.
bogdanm	82:6473597d706e	1642	#define BF_CAN_RX15MASK_RX15M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX15MASK_RX15M), uint32_t) & BM_CAN_RX15MASK_RX15M)
bogdanm	82:6473597d706e	1643
bogdanm	82:6473597d706e	1644	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1645	//! @brief Set the RX15M field to a new value.
bogdanm	82:6473597d706e	1646	#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
bogdanm	82:6473597d706e	1647	#endif
bogdanm	82:6473597d706e	1648	//@}
bogdanm	82:6473597d706e	1649
bogdanm	82:6473597d706e	1650	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1651	// HW_CAN_ECR - Error Counter
bogdanm	82:6473597d706e	1652	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1653
bogdanm	82:6473597d706e	1654	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1655	/*!
bogdanm	82:6473597d706e	1656	* @brief HW_CAN_ECR - Error Counter (RW)
bogdanm	82:6473597d706e	1657	*
bogdanm	82:6473597d706e	1658	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1659	*
bogdanm	82:6473597d706e	1660	* This register has two 8-bit fields reflecting the value of two FlexCAN error
bogdanm	82:6473597d706e	1661	* counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
bogdanm	82:6473597d706e	1662	* (RXERRCNT field). The rules for increasing and decreasing these counters are
bogdanm	82:6473597d706e	1663	* described in the CAN protocol and are completely implemented in the FlexCAN
bogdanm	82:6473597d706e	1664	* module. Both counters are read-only except in Freeze mode, where they can be
bogdanm	82:6473597d706e	1665	* written by the CPU. FlexCAN responds to any bus state as described in the protocol,
bogdanm	82:6473597d706e	1666	* for example, transmit Error Active or Error Passive flag, delay its
bogdanm	82:6473597d706e	1667	* transmission start time (Error Passive) and avoid any influence on the bus when in Bus
bogdanm	82:6473597d706e	1668	* Off state. The following are the basic rules for FlexCAN bus state transitions:
bogdanm	82:6473597d706e	1669	* If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
bogdanm	82:6473597d706e	1670	* 128, the FLTCONF field in the Error and Status Register is updated to reflect
bogdanm	82:6473597d706e	1671	* 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
bogdanm	82:6473597d706e	1672	* TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
bogdanm	82:6473597d706e	1673	* other already satisfies this condition, the FLTCONF field in the Error and
bogdanm	82:6473597d706e	1674	* Status Register is updated to reflect 'Error Active' state. If the value of
bogdanm	82:6473597d706e	1675	* TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
bogdanm	82:6473597d706e	1676	* Register is updated to reflect 'Bus Off' state, and an interrupt may be
bogdanm	82:6473597d706e	1677	* issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
bogdanm	82:6473597d706e	1678	* state, then TXERRCNT is cascaded together with another internal counter to count
bogdanm	82:6473597d706e	1679	* the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
bogdanm	82:6473597d706e	1680	* TXERRCNT is reset to zero and counts in a manner where the internal counter counts
bogdanm	82:6473597d706e	1681	* 11 such bits and then wraps around while incrementing the TXERRCNT. When
bogdanm	82:6473597d706e	1682	* TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
bogdanm	82:6473597d706e	1683	* Register is updated to be 'Error Active' and both error counters are reset to zero.
bogdanm	82:6473597d706e	1684	* At any instance of dominant bit following a stream of less than 11
bogdanm	82:6473597d706e	1685	* consecutive recessive bits, the internal counter resets itself to zero without affecting
bogdanm	82:6473597d706e	1686	* the TXERRCNT value. If during system start-up, only one node is operating,
bogdanm	82:6473597d706e	1687	* then its TXERRCNT increases in each message it is trying to transmit, as a
bogdanm	82:6473597d706e	1688	* result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
bogdanm	82:6473597d706e	1689	* Register). After the transition to 'Error Passive' state, the TXERRCNT does not
bogdanm	82:6473597d706e	1690	* increment anymore by acknowledge errors. Therefore the device never goes to
bogdanm	82:6473597d706e	1691	* the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
bogdanm	82:6473597d706e	1692	* is not incremented further, even if more errors are detected while being a
bogdanm	82:6473597d706e	1693	* receiver. At the next successful message reception, the counter is set to a value
bogdanm	82:6473597d706e	1694	* between 119 and 127 to resume to 'Error Active' state.
bogdanm	82:6473597d706e	1695	*/
bogdanm	82:6473597d706e	1696	typedef union _hw_can_ecr
bogdanm	82:6473597d706e	1697	{
bogdanm	82:6473597d706e	1698	uint32_t U;
bogdanm	82:6473597d706e	1699	struct _hw_can_ecr_bitfields
bogdanm	82:6473597d706e	1700	{
bogdanm	82:6473597d706e	1701	uint32_t TXERRCNT : 8; //!< [7:0] Transmit Error Counter
bogdanm	82:6473597d706e	1702	uint32_t RXERRCNT : 8; //!< [15:8] Receive Error Counter
bogdanm	82:6473597d706e	1703	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1704	} B;
bogdanm	82:6473597d706e	1705	} hw_can_ecr_t;
bogdanm	82:6473597d706e	1706	#endif
bogdanm	82:6473597d706e	1707
bogdanm	82:6473597d706e	1708	/*!
bogdanm	82:6473597d706e	1709	* @name Constants and macros for entire CAN_ECR register
bogdanm	82:6473597d706e	1710	*/
bogdanm	82:6473597d706e	1711	//@{
bogdanm	82:6473597d706e	1712	#define HW_CAN_ECR_ADDR(x) (REGS_CAN_BASE(x) + 0x1CU)
bogdanm	82:6473597d706e	1713
bogdanm	82:6473597d706e	1714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1715	#define HW_CAN_ECR(x) ((__IO hw_can_ecr_t ) HW_CAN_ECR_ADDR(x))
bogdanm	82:6473597d706e	1716	#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
bogdanm	82:6473597d706e	1717	#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
bogdanm	82:6473597d706e	1718	#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1719	#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1720	#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1721	#endif
bogdanm	82:6473597d706e	1722	//@}
bogdanm	82:6473597d706e	1723
bogdanm	82:6473597d706e	1724	/*
bogdanm	82:6473597d706e	1725	* Constants & macros for individual CAN_ECR bitfields
bogdanm	82:6473597d706e	1726	*/
bogdanm	82:6473597d706e	1727
bogdanm	82:6473597d706e	1728	/*!
bogdanm	82:6473597d706e	1729	* @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
bogdanm	82:6473597d706e	1730	*/
bogdanm	82:6473597d706e	1731	//@{
bogdanm	82:6473597d706e	1732	#define BP_CAN_ECR_TXERRCNT (0U) //!< Bit position for CAN_ECR_TXERRCNT.
bogdanm	82:6473597d706e	1733	#define BM_CAN_ECR_TXERRCNT (0x000000FFU) //!< Bit mask for CAN_ECR_TXERRCNT.
bogdanm	82:6473597d706e	1734	#define BS_CAN_ECR_TXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_TXERRCNT.
bogdanm	82:6473597d706e	1735
bogdanm	82:6473597d706e	1736	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1737	//! @brief Read current value of the CAN_ECR_TXERRCNT field.
bogdanm	82:6473597d706e	1738	#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
bogdanm	82:6473597d706e	1739	#endif
bogdanm	82:6473597d706e	1740
bogdanm	82:6473597d706e	1741	//! @brief Format value for bitfield CAN_ECR_TXERRCNT.
bogdanm	82:6473597d706e	1742	#define BF_CAN_ECR_TXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_TXERRCNT), uint32_t) & BM_CAN_ECR_TXERRCNT)
bogdanm	82:6473597d706e	1743
bogdanm	82:6473597d706e	1744	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1745	//! @brief Set the TXERRCNT field to a new value.
bogdanm	82:6473597d706e	1746	#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) \| BF_CAN_ECR_TXERRCNT(v)))
bogdanm	82:6473597d706e	1747	#endif
bogdanm	82:6473597d706e	1748	//@}
bogdanm	82:6473597d706e	1749
bogdanm	82:6473597d706e	1750	/*!
bogdanm	82:6473597d706e	1751	* @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
bogdanm	82:6473597d706e	1752	*/
bogdanm	82:6473597d706e	1753	//@{
bogdanm	82:6473597d706e	1754	#define BP_CAN_ECR_RXERRCNT (8U) //!< Bit position for CAN_ECR_RXERRCNT.
bogdanm	82:6473597d706e	1755	#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) //!< Bit mask for CAN_ECR_RXERRCNT.
bogdanm	82:6473597d706e	1756	#define BS_CAN_ECR_RXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_RXERRCNT.
bogdanm	82:6473597d706e	1757
bogdanm	82:6473597d706e	1758	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1759	//! @brief Read current value of the CAN_ECR_RXERRCNT field.
bogdanm	82:6473597d706e	1760	#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
bogdanm	82:6473597d706e	1761	#endif
bogdanm	82:6473597d706e	1762
bogdanm	82:6473597d706e	1763	//! @brief Format value for bitfield CAN_ECR_RXERRCNT.
bogdanm	82:6473597d706e	1764	#define BF_CAN_ECR_RXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_RXERRCNT), uint32_t) & BM_CAN_ECR_RXERRCNT)
bogdanm	82:6473597d706e	1765
bogdanm	82:6473597d706e	1766	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1767	//! @brief Set the RXERRCNT field to a new value.
bogdanm	82:6473597d706e	1768	#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) \| BF_CAN_ECR_RXERRCNT(v)))
bogdanm	82:6473597d706e	1769	#endif
bogdanm	82:6473597d706e	1770	//@}
bogdanm	82:6473597d706e	1771
bogdanm	82:6473597d706e	1772	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1773	// HW_CAN_ESR1 - Error and Status 1 register
bogdanm	82:6473597d706e	1774	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1775
bogdanm	82:6473597d706e	1776	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1777	/*!
bogdanm	82:6473597d706e	1778	* @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
bogdanm	82:6473597d706e	1779	*
bogdanm	82:6473597d706e	1780	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1781	*
bogdanm	82:6473597d706e	1782	* This register reflects various error conditions, some general status of the
bogdanm	82:6473597d706e	1783	* device and it is the source of interrupts to the CPU. The CPU read action
bogdanm	82:6473597d706e	1784	* clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
bogdanm	82:6473597d706e	1785	* that occurred since the last time the CPU read this register. Bits 9-3 are
bogdanm	82:6473597d706e	1786	* status bits. The following table shows the FlexCAN state variables and their
bogdanm	82:6473597d706e	1787	* meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
bogdanm	82:6473597d706e	1788	* FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
bogdanm	82:6473597d706e	1789	* Transmitting 1 0 0 1 Receiving
bogdanm	82:6473597d706e	1790	*/
bogdanm	82:6473597d706e	1791	typedef union _hw_can_esr1
bogdanm	82:6473597d706e	1792	{
bogdanm	82:6473597d706e	1793	uint32_t U;
bogdanm	82:6473597d706e	1794	struct _hw_can_esr1_bitfields
bogdanm	82:6473597d706e	1795	{
bogdanm	82:6473597d706e	1796	uint32_t WAKINT : 1; //!< [0] Wake-Up Interrupt
bogdanm	82:6473597d706e	1797	uint32_t ERRINT : 1; //!< [1] Error Interrupt
bogdanm	82:6473597d706e	1798	uint32_t BOFFINT : 1; //!< [2] Bus Off Interrupt
bogdanm	82:6473597d706e	1799	uint32_t RX : 1; //!< [3] FlexCAN In Reception
bogdanm	82:6473597d706e	1800	uint32_t FLTCONF : 2; //!< [5:4] Fault Confinement State
bogdanm	82:6473597d706e	1801	uint32_t TX : 1; //!< [6] FlexCAN In Transmission
bogdanm	82:6473597d706e	1802	uint32_t IDLE : 1; //!< [7]
bogdanm	82:6473597d706e	1803	uint32_t RXWRN : 1; //!< [8] Rx Error Warning
bogdanm	82:6473597d706e	1804	uint32_t TXWRN : 1; //!< [9] TX Error Warning
bogdanm	82:6473597d706e	1805	uint32_t STFERR : 1; //!< [10] Stuffing Error
bogdanm	82:6473597d706e	1806	uint32_t FRMERR : 1; //!< [11] Form Error
bogdanm	82:6473597d706e	1807	uint32_t CRCERR : 1; //!< [12] Cyclic Redundancy Check Error
bogdanm	82:6473597d706e	1808	uint32_t ACKERR : 1; //!< [13] Acknowledge Error
bogdanm	82:6473597d706e	1809	uint32_t BIT0ERR : 1; //!< [14] Bit0 Error
bogdanm	82:6473597d706e	1810	uint32_t BIT1ERR : 1; //!< [15] Bit1 Error
bogdanm	82:6473597d706e	1811	uint32_t RWRNINT : 1; //!< [16] Rx Warning Interrupt Flag
bogdanm	82:6473597d706e	1812	uint32_t TWRNINT : 1; //!< [17] Tx Warning Interrupt Flag
bogdanm	82:6473597d706e	1813	uint32_t SYNCH : 1; //!< [18] CAN Synchronization Status
bogdanm	82:6473597d706e	1814	uint32_t RESERVED0 : 13; //!< [31:19]
bogdanm	82:6473597d706e	1815	} B;
bogdanm	82:6473597d706e	1816	} hw_can_esr1_t;
bogdanm	82:6473597d706e	1817	#endif
bogdanm	82:6473597d706e	1818
bogdanm	82:6473597d706e	1819	/*!
bogdanm	82:6473597d706e	1820	* @name Constants and macros for entire CAN_ESR1 register
bogdanm	82:6473597d706e	1821	*/
bogdanm	82:6473597d706e	1822	//@{
bogdanm	82:6473597d706e	1823	#define HW_CAN_ESR1_ADDR(x) (REGS_CAN_BASE(x) + 0x20U)
bogdanm	82:6473597d706e	1824
bogdanm	82:6473597d706e	1825	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1826	#define HW_CAN_ESR1(x) ((__IO hw_can_esr1_t ) HW_CAN_ESR1_ADDR(x))
bogdanm	82:6473597d706e	1827	#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
bogdanm	82:6473597d706e	1828	#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
bogdanm	82:6473597d706e	1829	#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) \| (v)))
bogdanm	82:6473597d706e	1830	#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1831	#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1832	#endif
bogdanm	82:6473597d706e	1833	//@}
bogdanm	82:6473597d706e	1834
bogdanm	82:6473597d706e	1835	/*
bogdanm	82:6473597d706e	1836	* Constants & macros for individual CAN_ESR1 bitfields
bogdanm	82:6473597d706e	1837	*/
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	/*!
bogdanm	82:6473597d706e	1840	* @name Register CAN_ESR1, field WAKINT[0] (W1C)
bogdanm	82:6473597d706e	1841	*
bogdanm	82:6473597d706e	1842	* This field applies when FlexCAN is in low-power mode under Self Wake Up
bogdanm	82:6473597d706e	1843	* mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
bogdanm	82:6473597d706e	1844	* bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
bogdanm	82:6473597d706e	1845	* This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
bogdanm	82:6473597d706e	1846	* is masked. The CPU must clear this flag before disabling the bit. Otherwise
bogdanm	82:6473597d706e	1847	* it will be set when the SLFWAK is set again. Writing 0 has no effect.
bogdanm	82:6473597d706e	1848	*
bogdanm	82:6473597d706e	1849	* Values:
bogdanm	82:6473597d706e	1850	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	1851	* - 1 - Indicates a recessive to dominant transition was received on the CAN
bogdanm	82:6473597d706e	1852	* bus.
bogdanm	82:6473597d706e	1853	*/
bogdanm	82:6473597d706e	1854	//@{
bogdanm	82:6473597d706e	1855	#define BP_CAN_ESR1_WAKINT (0U) //!< Bit position for CAN_ESR1_WAKINT.
bogdanm	82:6473597d706e	1856	#define BM_CAN_ESR1_WAKINT (0x00000001U) //!< Bit mask for CAN_ESR1_WAKINT.
bogdanm	82:6473597d706e	1857	#define BS_CAN_ESR1_WAKINT (1U) //!< Bit field size in bits for CAN_ESR1_WAKINT.
bogdanm	82:6473597d706e	1858
bogdanm	82:6473597d706e	1859	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1860	//! @brief Read current value of the CAN_ESR1_WAKINT field.
bogdanm	82:6473597d706e	1861	#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
bogdanm	82:6473597d706e	1862	#endif
bogdanm	82:6473597d706e	1863
bogdanm	82:6473597d706e	1864	//! @brief Format value for bitfield CAN_ESR1_WAKINT.
bogdanm	82:6473597d706e	1865	#define BF_CAN_ESR1_WAKINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_WAKINT), uint32_t) & BM_CAN_ESR1_WAKINT)
bogdanm	82:6473597d706e	1866
bogdanm	82:6473597d706e	1867	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1868	//! @brief Set the WAKINT field to a new value.
bogdanm	82:6473597d706e	1869	#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
bogdanm	82:6473597d706e	1870	#endif
bogdanm	82:6473597d706e	1871	//@}
bogdanm	82:6473597d706e	1872
bogdanm	82:6473597d706e	1873	/*!
bogdanm	82:6473597d706e	1874	* @name Register CAN_ESR1, field ERRINT[1] (W1C)
bogdanm	82:6473597d706e	1875	*
bogdanm	82:6473597d706e	1876	* This bit indicates that at least one of the Error Bits (bits 15-10) is set.
bogdanm	82:6473597d706e	1877	* If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
bogdanm	82:6473597d706e	1878	* to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
bogdanm	82:6473597d706e	1879	*
bogdanm	82:6473597d706e	1880	* Values:
bogdanm	82:6473597d706e	1881	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	1882	* - 1 - Indicates setting of any Error Bit in the Error and Status Register.
bogdanm	82:6473597d706e	1883	*/
bogdanm	82:6473597d706e	1884	//@{
bogdanm	82:6473597d706e	1885	#define BP_CAN_ESR1_ERRINT (1U) //!< Bit position for CAN_ESR1_ERRINT.
bogdanm	82:6473597d706e	1886	#define BM_CAN_ESR1_ERRINT (0x00000002U) //!< Bit mask for CAN_ESR1_ERRINT.
bogdanm	82:6473597d706e	1887	#define BS_CAN_ESR1_ERRINT (1U) //!< Bit field size in bits for CAN_ESR1_ERRINT.
bogdanm	82:6473597d706e	1888
bogdanm	82:6473597d706e	1889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1890	//! @brief Read current value of the CAN_ESR1_ERRINT field.
bogdanm	82:6473597d706e	1891	#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
bogdanm	82:6473597d706e	1892	#endif
bogdanm	82:6473597d706e	1893
bogdanm	82:6473597d706e	1894	//! @brief Format value for bitfield CAN_ESR1_ERRINT.
bogdanm	82:6473597d706e	1895	#define BF_CAN_ESR1_ERRINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_ERRINT), uint32_t) & BM_CAN_ESR1_ERRINT)
bogdanm	82:6473597d706e	1896
bogdanm	82:6473597d706e	1897	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1898	//! @brief Set the ERRINT field to a new value.
bogdanm	82:6473597d706e	1899	#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
bogdanm	82:6473597d706e	1900	#endif
bogdanm	82:6473597d706e	1901	//@}
bogdanm	82:6473597d706e	1902
bogdanm	82:6473597d706e	1903	/*!
bogdanm	82:6473597d706e	1904	* @name Register CAN_ESR1, field BOFFINT[2] (W1C)
bogdanm	82:6473597d706e	1905	*
bogdanm	82:6473597d706e	1906	* This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
bogdanm	82:6473597d706e	1907	* mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
bogdanm	82:6473597d706e	1908	* the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
bogdanm	82:6473597d706e	1909	*
bogdanm	82:6473597d706e	1910	* Values:
bogdanm	82:6473597d706e	1911	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	1912	* - 1 - FlexCAN module entered Bus Off state.
bogdanm	82:6473597d706e	1913	*/
bogdanm	82:6473597d706e	1914	//@{
bogdanm	82:6473597d706e	1915	#define BP_CAN_ESR1_BOFFINT (2U) //!< Bit position for CAN_ESR1_BOFFINT.
bogdanm	82:6473597d706e	1916	#define BM_CAN_ESR1_BOFFINT (0x00000004U) //!< Bit mask for CAN_ESR1_BOFFINT.
bogdanm	82:6473597d706e	1917	#define BS_CAN_ESR1_BOFFINT (1U) //!< Bit field size in bits for CAN_ESR1_BOFFINT.
bogdanm	82:6473597d706e	1918
bogdanm	82:6473597d706e	1919	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1920	//! @brief Read current value of the CAN_ESR1_BOFFINT field.
bogdanm	82:6473597d706e	1921	#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
bogdanm	82:6473597d706e	1922	#endif
bogdanm	82:6473597d706e	1923
bogdanm	82:6473597d706e	1924	//! @brief Format value for bitfield CAN_ESR1_BOFFINT.
bogdanm	82:6473597d706e	1925	#define BF_CAN_ESR1_BOFFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_BOFFINT), uint32_t) & BM_CAN_ESR1_BOFFINT)
bogdanm	82:6473597d706e	1926
bogdanm	82:6473597d706e	1927	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1928	//! @brief Set the BOFFINT field to a new value.
bogdanm	82:6473597d706e	1929	#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
bogdanm	82:6473597d706e	1930	#endif
bogdanm	82:6473597d706e	1931	//@}
bogdanm	82:6473597d706e	1932
bogdanm	82:6473597d706e	1933	/*!
bogdanm	82:6473597d706e	1934	* @name Register CAN_ESR1, field RX[3] (RO)
bogdanm	82:6473597d706e	1935	*
bogdanm	82:6473597d706e	1936	* This bit indicates if FlexCAN is receiving a message. See the table in the
bogdanm	82:6473597d706e	1937	* overall CAN_ESR1 register description.
bogdanm	82:6473597d706e	1938	*
bogdanm	82:6473597d706e	1939	* Values:
bogdanm	82:6473597d706e	1940	* - 0 - FlexCAN is not receiving a message.
bogdanm	82:6473597d706e	1941	* - 1 - FlexCAN is receiving a message.
bogdanm	82:6473597d706e	1942	*/
bogdanm	82:6473597d706e	1943	//@{
bogdanm	82:6473597d706e	1944	#define BP_CAN_ESR1_RX (3U) //!< Bit position for CAN_ESR1_RX.
bogdanm	82:6473597d706e	1945	#define BM_CAN_ESR1_RX (0x00000008U) //!< Bit mask for CAN_ESR1_RX.
bogdanm	82:6473597d706e	1946	#define BS_CAN_ESR1_RX (1U) //!< Bit field size in bits for CAN_ESR1_RX.
bogdanm	82:6473597d706e	1947
bogdanm	82:6473597d706e	1948	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1949	//! @brief Read current value of the CAN_ESR1_RX field.
bogdanm	82:6473597d706e	1950	#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
bogdanm	82:6473597d706e	1951	#endif
bogdanm	82:6473597d706e	1952	//@}
bogdanm	82:6473597d706e	1953
bogdanm	82:6473597d706e	1954	/*!
bogdanm	82:6473597d706e	1955	* @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
bogdanm	82:6473597d706e	1956	*
bogdanm	82:6473597d706e	1957	* This 2-bit field indicates the Confinement State of the FlexCAN module. If
bogdanm	82:6473597d706e	1958	* the LOM bit in the Control Register is asserted, after some delay that depends
bogdanm	82:6473597d706e	1959	* on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
bogdanm	82:6473597d706e	1960	* same delay affects the way how FLTCONF reflects an update to ECR register by
bogdanm	82:6473597d706e	1961	* the CPU. It may be necessary up to one CAN bit time to get them coherent
bogdanm	82:6473597d706e	1962	* again. Because the Control Register is not affected by soft reset, the FLTCONF
bogdanm	82:6473597d706e	1963	* field will not be affected by soft reset if the LOM bit is asserted.
bogdanm	82:6473597d706e	1964	*
bogdanm	82:6473597d706e	1965	* Values:
bogdanm	82:6473597d706e	1966	* - 00 - Error Active
bogdanm	82:6473597d706e	1967	* - 01 - Error Passive
bogdanm	82:6473597d706e	1968	* - 1x - Bus Off
bogdanm	82:6473597d706e	1969	*/
bogdanm	82:6473597d706e	1970	//@{
bogdanm	82:6473597d706e	1971	#define BP_CAN_ESR1_FLTCONF (4U) //!< Bit position for CAN_ESR1_FLTCONF.
bogdanm	82:6473597d706e	1972	#define BM_CAN_ESR1_FLTCONF (0x00000030U) //!< Bit mask for CAN_ESR1_FLTCONF.
bogdanm	82:6473597d706e	1973	#define BS_CAN_ESR1_FLTCONF (2U) //!< Bit field size in bits for CAN_ESR1_FLTCONF.
bogdanm	82:6473597d706e	1974
bogdanm	82:6473597d706e	1975	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1976	//! @brief Read current value of the CAN_ESR1_FLTCONF field.
bogdanm	82:6473597d706e	1977	#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
bogdanm	82:6473597d706e	1978	#endif
bogdanm	82:6473597d706e	1979	//@}
bogdanm	82:6473597d706e	1980
bogdanm	82:6473597d706e	1981	/*!
bogdanm	82:6473597d706e	1982	* @name Register CAN_ESR1, field TX[6] (RO)
bogdanm	82:6473597d706e	1983	*
bogdanm	82:6473597d706e	1984	* This bit indicates if FlexCAN is transmitting a message. See the table in the
bogdanm	82:6473597d706e	1985	* overall CAN_ESR1 register description.
bogdanm	82:6473597d706e	1986	*
bogdanm	82:6473597d706e	1987	* Values:
bogdanm	82:6473597d706e	1988	* - 0 - FlexCAN is not transmitting a message.
bogdanm	82:6473597d706e	1989	* - 1 - FlexCAN is transmitting a message.
bogdanm	82:6473597d706e	1990	*/
bogdanm	82:6473597d706e	1991	//@{
bogdanm	82:6473597d706e	1992	#define BP_CAN_ESR1_TX (6U) //!< Bit position for CAN_ESR1_TX.
bogdanm	82:6473597d706e	1993	#define BM_CAN_ESR1_TX (0x00000040U) //!< Bit mask for CAN_ESR1_TX.
bogdanm	82:6473597d706e	1994	#define BS_CAN_ESR1_TX (1U) //!< Bit field size in bits for CAN_ESR1_TX.
bogdanm	82:6473597d706e	1995
bogdanm	82:6473597d706e	1996	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1997	//! @brief Read current value of the CAN_ESR1_TX field.
bogdanm	82:6473597d706e	1998	#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
bogdanm	82:6473597d706e	1999	#endif
bogdanm	82:6473597d706e	2000	//@}
bogdanm	82:6473597d706e	2001
bogdanm	82:6473597d706e	2002	/*!
bogdanm	82:6473597d706e	2003	* @name Register CAN_ESR1, field IDLE[7] (RO)
bogdanm	82:6473597d706e	2004	*
bogdanm	82:6473597d706e	2005	* This bit indicates when CAN bus is in IDLE state. See the table in the
bogdanm	82:6473597d706e	2006	* overall CAN_ESR1 register description.
bogdanm	82:6473597d706e	2007	*
bogdanm	82:6473597d706e	2008	* Values:
bogdanm	82:6473597d706e	2009	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2010	* - 1 - CAN bus is now IDLE.
bogdanm	82:6473597d706e	2011	*/
bogdanm	82:6473597d706e	2012	//@{
bogdanm	82:6473597d706e	2013	#define BP_CAN_ESR1_IDLE (7U) //!< Bit position for CAN_ESR1_IDLE.
bogdanm	82:6473597d706e	2014	#define BM_CAN_ESR1_IDLE (0x00000080U) //!< Bit mask for CAN_ESR1_IDLE.
bogdanm	82:6473597d706e	2015	#define BS_CAN_ESR1_IDLE (1U) //!< Bit field size in bits for CAN_ESR1_IDLE.
bogdanm	82:6473597d706e	2016
bogdanm	82:6473597d706e	2017	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2018	//! @brief Read current value of the CAN_ESR1_IDLE field.
bogdanm	82:6473597d706e	2019	#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
bogdanm	82:6473597d706e	2020	#endif
bogdanm	82:6473597d706e	2021	//@}
bogdanm	82:6473597d706e	2022
bogdanm	82:6473597d706e	2023	/*!
bogdanm	82:6473597d706e	2024	* @name Register CAN_ESR1, field RXWRN[8] (RO)
bogdanm	82:6473597d706e	2025	*
bogdanm	82:6473597d706e	2026	* This bit indicates when repetitive errors are occurring during message
bogdanm	82:6473597d706e	2027	* reception. This bit is not updated during Freeze mode.
bogdanm	82:6473597d706e	2028	*
bogdanm	82:6473597d706e	2029	* Values:
bogdanm	82:6473597d706e	2030	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2031	* - 1 - RXERRCNT is greater than or equal to 96.
bogdanm	82:6473597d706e	2032	*/
bogdanm	82:6473597d706e	2033	//@{
bogdanm	82:6473597d706e	2034	#define BP_CAN_ESR1_RXWRN (8U) //!< Bit position for CAN_ESR1_RXWRN.
bogdanm	82:6473597d706e	2035	#define BM_CAN_ESR1_RXWRN (0x00000100U) //!< Bit mask for CAN_ESR1_RXWRN.
bogdanm	82:6473597d706e	2036	#define BS_CAN_ESR1_RXWRN (1U) //!< Bit field size in bits for CAN_ESR1_RXWRN.
bogdanm	82:6473597d706e	2037
bogdanm	82:6473597d706e	2038	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2039	//! @brief Read current value of the CAN_ESR1_RXWRN field.
bogdanm	82:6473597d706e	2040	#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
bogdanm	82:6473597d706e	2041	#endif
bogdanm	82:6473597d706e	2042	//@}
bogdanm	82:6473597d706e	2043
bogdanm	82:6473597d706e	2044	/*!
bogdanm	82:6473597d706e	2045	* @name Register CAN_ESR1, field TXWRN[9] (RO)
bogdanm	82:6473597d706e	2046	*
bogdanm	82:6473597d706e	2047	* This bit indicates when repetitive errors are occurring during message
bogdanm	82:6473597d706e	2048	* transmission. This bit is not updated during Freeze mode.
bogdanm	82:6473597d706e	2049	*
bogdanm	82:6473597d706e	2050	* Values:
bogdanm	82:6473597d706e	2051	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2052	* - 1 - TXERRCNT is greater than or equal to 96.
bogdanm	82:6473597d706e	2053	*/
bogdanm	82:6473597d706e	2054	//@{
bogdanm	82:6473597d706e	2055	#define BP_CAN_ESR1_TXWRN (9U) //!< Bit position for CAN_ESR1_TXWRN.
bogdanm	82:6473597d706e	2056	#define BM_CAN_ESR1_TXWRN (0x00000200U) //!< Bit mask for CAN_ESR1_TXWRN.
bogdanm	82:6473597d706e	2057	#define BS_CAN_ESR1_TXWRN (1U) //!< Bit field size in bits for CAN_ESR1_TXWRN.
bogdanm	82:6473597d706e	2058
bogdanm	82:6473597d706e	2059	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2060	//! @brief Read current value of the CAN_ESR1_TXWRN field.
bogdanm	82:6473597d706e	2061	#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
bogdanm	82:6473597d706e	2062	#endif
bogdanm	82:6473597d706e	2063	//@}
bogdanm	82:6473597d706e	2064
bogdanm	82:6473597d706e	2065	/*!
bogdanm	82:6473597d706e	2066	* @name Register CAN_ESR1, field STFERR[10] (RO)
bogdanm	82:6473597d706e	2067	*
bogdanm	82:6473597d706e	2068	* This bit indicates that a Stuffing Error has been etected.
bogdanm	82:6473597d706e	2069	*
bogdanm	82:6473597d706e	2070	* Values:
bogdanm	82:6473597d706e	2071	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2072	* - 1 - A Stuffing Error occurred since last read of this register.
bogdanm	82:6473597d706e	2073	*/
bogdanm	82:6473597d706e	2074	//@{
bogdanm	82:6473597d706e	2075	#define BP_CAN_ESR1_STFERR (10U) //!< Bit position for CAN_ESR1_STFERR.
bogdanm	82:6473597d706e	2076	#define BM_CAN_ESR1_STFERR (0x00000400U) //!< Bit mask for CAN_ESR1_STFERR.
bogdanm	82:6473597d706e	2077	#define BS_CAN_ESR1_STFERR (1U) //!< Bit field size in bits for CAN_ESR1_STFERR.
bogdanm	82:6473597d706e	2078
bogdanm	82:6473597d706e	2079	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2080	//! @brief Read current value of the CAN_ESR1_STFERR field.
bogdanm	82:6473597d706e	2081	#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
bogdanm	82:6473597d706e	2082	#endif
bogdanm	82:6473597d706e	2083	//@}
bogdanm	82:6473597d706e	2084
bogdanm	82:6473597d706e	2085	/*!
bogdanm	82:6473597d706e	2086	* @name Register CAN_ESR1, field FRMERR[11] (RO)
bogdanm	82:6473597d706e	2087	*
bogdanm	82:6473597d706e	2088	* This bit indicates that a Form Error has been detected by the receiver node,
bogdanm	82:6473597d706e	2089	* that is, a fixed-form bit field contains at least one illegal bit.
bogdanm	82:6473597d706e	2090	*
bogdanm	82:6473597d706e	2091	* Values:
bogdanm	82:6473597d706e	2092	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2093	* - 1 - A Form Error occurred since last read of this register.
bogdanm	82:6473597d706e	2094	*/
bogdanm	82:6473597d706e	2095	//@{
bogdanm	82:6473597d706e	2096	#define BP_CAN_ESR1_FRMERR (11U) //!< Bit position for CAN_ESR1_FRMERR.
bogdanm	82:6473597d706e	2097	#define BM_CAN_ESR1_FRMERR (0x00000800U) //!< Bit mask for CAN_ESR1_FRMERR.
bogdanm	82:6473597d706e	2098	#define BS_CAN_ESR1_FRMERR (1U) //!< Bit field size in bits for CAN_ESR1_FRMERR.
bogdanm	82:6473597d706e	2099
bogdanm	82:6473597d706e	2100	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2101	//! @brief Read current value of the CAN_ESR1_FRMERR field.
bogdanm	82:6473597d706e	2102	#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
bogdanm	82:6473597d706e	2103	#endif
bogdanm	82:6473597d706e	2104	//@}
bogdanm	82:6473597d706e	2105
bogdanm	82:6473597d706e	2106	/*!
bogdanm	82:6473597d706e	2107	* @name Register CAN_ESR1, field CRCERR[12] (RO)
bogdanm	82:6473597d706e	2108	*
bogdanm	82:6473597d706e	2109	* This bit indicates that a CRC Error has been detected by the receiver node,
bogdanm	82:6473597d706e	2110	* that is, the calculated CRC is different from the received.
bogdanm	82:6473597d706e	2111	*
bogdanm	82:6473597d706e	2112	* Values:
bogdanm	82:6473597d706e	2113	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2114	* - 1 - A CRC error occurred since last read of this register.
bogdanm	82:6473597d706e	2115	*/
bogdanm	82:6473597d706e	2116	//@{
bogdanm	82:6473597d706e	2117	#define BP_CAN_ESR1_CRCERR (12U) //!< Bit position for CAN_ESR1_CRCERR.
bogdanm	82:6473597d706e	2118	#define BM_CAN_ESR1_CRCERR (0x00001000U) //!< Bit mask for CAN_ESR1_CRCERR.
bogdanm	82:6473597d706e	2119	#define BS_CAN_ESR1_CRCERR (1U) //!< Bit field size in bits for CAN_ESR1_CRCERR.
bogdanm	82:6473597d706e	2120
bogdanm	82:6473597d706e	2121	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2122	//! @brief Read current value of the CAN_ESR1_CRCERR field.
bogdanm	82:6473597d706e	2123	#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
bogdanm	82:6473597d706e	2124	#endif
bogdanm	82:6473597d706e	2125	//@}
bogdanm	82:6473597d706e	2126
bogdanm	82:6473597d706e	2127	/*!
bogdanm	82:6473597d706e	2128	* @name Register CAN_ESR1, field ACKERR[13] (RO)
bogdanm	82:6473597d706e	2129	*
bogdanm	82:6473597d706e	2130	* This bit indicates that an Acknowledge Error has been detected by the
bogdanm	82:6473597d706e	2131	* transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
bogdanm	82:6473597d706e	2132	*
bogdanm	82:6473597d706e	2133	* Values:
bogdanm	82:6473597d706e	2134	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2135	* - 1 - An ACK error occurred since last read of this register.
bogdanm	82:6473597d706e	2136	*/
bogdanm	82:6473597d706e	2137	//@{
bogdanm	82:6473597d706e	2138	#define BP_CAN_ESR1_ACKERR (13U) //!< Bit position for CAN_ESR1_ACKERR.
bogdanm	82:6473597d706e	2139	#define BM_CAN_ESR1_ACKERR (0x00002000U) //!< Bit mask for CAN_ESR1_ACKERR.
bogdanm	82:6473597d706e	2140	#define BS_CAN_ESR1_ACKERR (1U) //!< Bit field size in bits for CAN_ESR1_ACKERR.
bogdanm	82:6473597d706e	2141
bogdanm	82:6473597d706e	2142	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2143	//! @brief Read current value of the CAN_ESR1_ACKERR field.
bogdanm	82:6473597d706e	2144	#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
bogdanm	82:6473597d706e	2145	#endif
bogdanm	82:6473597d706e	2146	//@}
bogdanm	82:6473597d706e	2147
bogdanm	82:6473597d706e	2148	/*!
bogdanm	82:6473597d706e	2149	* @name Register CAN_ESR1, field BIT0ERR[14] (RO)
bogdanm	82:6473597d706e	2150	*
bogdanm	82:6473597d706e	2151	* This bit indicates when an inconsistency occurs between the transmitted and
bogdanm	82:6473597d706e	2152	* the received bit in a message.
bogdanm	82:6473597d706e	2153	*
bogdanm	82:6473597d706e	2154	* Values:
bogdanm	82:6473597d706e	2155	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2156	* - 1 - At least one bit sent as dominant is received as recessive.
bogdanm	82:6473597d706e	2157	*/
bogdanm	82:6473597d706e	2158	//@{
bogdanm	82:6473597d706e	2159	#define BP_CAN_ESR1_BIT0ERR (14U) //!< Bit position for CAN_ESR1_BIT0ERR.
bogdanm	82:6473597d706e	2160	#define BM_CAN_ESR1_BIT0ERR (0x00004000U) //!< Bit mask for CAN_ESR1_BIT0ERR.
bogdanm	82:6473597d706e	2161	#define BS_CAN_ESR1_BIT0ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT0ERR.
bogdanm	82:6473597d706e	2162
bogdanm	82:6473597d706e	2163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2164	//! @brief Read current value of the CAN_ESR1_BIT0ERR field.
bogdanm	82:6473597d706e	2165	#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
bogdanm	82:6473597d706e	2166	#endif
bogdanm	82:6473597d706e	2167	//@}
bogdanm	82:6473597d706e	2168
bogdanm	82:6473597d706e	2169	/*!
bogdanm	82:6473597d706e	2170	* @name Register CAN_ESR1, field BIT1ERR[15] (RO)
bogdanm	82:6473597d706e	2171	*
bogdanm	82:6473597d706e	2172	* This bit indicates when an inconsistency occurs between the transmitted and
bogdanm	82:6473597d706e	2173	* the received bit in a message. This bit is not set by a transmitter in case of
bogdanm	82:6473597d706e	2174	* arbitration field or ACK slot, or in case of a node sending a passive error
bogdanm	82:6473597d706e	2175	* flag that detects dominant bits.
bogdanm	82:6473597d706e	2176	*
bogdanm	82:6473597d706e	2177	* Values:
bogdanm	82:6473597d706e	2178	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2179	* - 1 - At least one bit sent as recessive is received as dominant.
bogdanm	82:6473597d706e	2180	*/
bogdanm	82:6473597d706e	2181	//@{
bogdanm	82:6473597d706e	2182	#define BP_CAN_ESR1_BIT1ERR (15U) //!< Bit position for CAN_ESR1_BIT1ERR.
bogdanm	82:6473597d706e	2183	#define BM_CAN_ESR1_BIT1ERR (0x00008000U) //!< Bit mask for CAN_ESR1_BIT1ERR.
bogdanm	82:6473597d706e	2184	#define BS_CAN_ESR1_BIT1ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT1ERR.
bogdanm	82:6473597d706e	2185
bogdanm	82:6473597d706e	2186	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2187	//! @brief Read current value of the CAN_ESR1_BIT1ERR field.
bogdanm	82:6473597d706e	2188	#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
bogdanm	82:6473597d706e	2189	#endif
bogdanm	82:6473597d706e	2190	//@}
bogdanm	82:6473597d706e	2191
bogdanm	82:6473597d706e	2192	/*!
bogdanm	82:6473597d706e	2193	* @name Register CAN_ESR1, field RWRNINT[16] (W1C)
bogdanm	82:6473597d706e	2194	*
bogdanm	82:6473597d706e	2195	* If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
bogdanm	82:6473597d706e	2196	* flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
bogdanm	82:6473597d706e	2197	* the corresponding mask bit in the Control Register (RWRNMSK) is set, an
bogdanm	82:6473597d706e	2198	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
bogdanm	82:6473597d706e	2199	* WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
bogdanm	82:6473597d706e	2200	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
bogdanm	82:6473597d706e	2201	* effect. This bit is not updated during Freeze mode.
bogdanm	82:6473597d706e	2202	*
bogdanm	82:6473597d706e	2203	* Values:
bogdanm	82:6473597d706e	2204	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2205	* - 1 - The Rx error counter transitioned from less than 96 to greater than or
bogdanm	82:6473597d706e	2206	* equal to 96.
bogdanm	82:6473597d706e	2207	*/
bogdanm	82:6473597d706e	2208	//@{
bogdanm	82:6473597d706e	2209	#define BP_CAN_ESR1_RWRNINT (16U) //!< Bit position for CAN_ESR1_RWRNINT.
bogdanm	82:6473597d706e	2210	#define BM_CAN_ESR1_RWRNINT (0x00010000U) //!< Bit mask for CAN_ESR1_RWRNINT.
bogdanm	82:6473597d706e	2211	#define BS_CAN_ESR1_RWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_RWRNINT.
bogdanm	82:6473597d706e	2212
bogdanm	82:6473597d706e	2213	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2214	//! @brief Read current value of the CAN_ESR1_RWRNINT field.
bogdanm	82:6473597d706e	2215	#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
bogdanm	82:6473597d706e	2216	#endif
bogdanm	82:6473597d706e	2217
bogdanm	82:6473597d706e	2218	//! @brief Format value for bitfield CAN_ESR1_RWRNINT.
bogdanm	82:6473597d706e	2219	#define BF_CAN_ESR1_RWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_RWRNINT), uint32_t) & BM_CAN_ESR1_RWRNINT)
bogdanm	82:6473597d706e	2220
bogdanm	82:6473597d706e	2221	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2222	//! @brief Set the RWRNINT field to a new value.
bogdanm	82:6473597d706e	2223	#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
bogdanm	82:6473597d706e	2224	#endif
bogdanm	82:6473597d706e	2225	//@}
bogdanm	82:6473597d706e	2226
bogdanm	82:6473597d706e	2227	/*!
bogdanm	82:6473597d706e	2228	* @name Register CAN_ESR1, field TWRNINT[17] (W1C)
bogdanm	82:6473597d706e	2229	*
bogdanm	82:6473597d706e	2230	* If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
bogdanm	82:6473597d706e	2231	* flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
bogdanm	82:6473597d706e	2232	* the corresponding mask bit in the Control Register (TWRNMSK) is set, an
bogdanm	82:6473597d706e	2233	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
bogdanm	82:6473597d706e	2234	* is negated, this flag is masked. CPU must clear this flag before disabling
bogdanm	82:6473597d706e	2235	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
bogdanm	82:6473597d706e	2236	* effect. This flag is not generated during Bus Off state. This bit is not
bogdanm	82:6473597d706e	2237	* updated during Freeze mode.
bogdanm	82:6473597d706e	2238	*
bogdanm	82:6473597d706e	2239	* Values:
bogdanm	82:6473597d706e	2240	* - 0 - No such occurrence.
bogdanm	82:6473597d706e	2241	* - 1 - The Tx error counter transitioned from less than 96 to greater than or
bogdanm	82:6473597d706e	2242	* equal to 96.
bogdanm	82:6473597d706e	2243	*/
bogdanm	82:6473597d706e	2244	//@{
bogdanm	82:6473597d706e	2245	#define BP_CAN_ESR1_TWRNINT (17U) //!< Bit position for CAN_ESR1_TWRNINT.
bogdanm	82:6473597d706e	2246	#define BM_CAN_ESR1_TWRNINT (0x00020000U) //!< Bit mask for CAN_ESR1_TWRNINT.
bogdanm	82:6473597d706e	2247	#define BS_CAN_ESR1_TWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_TWRNINT.
bogdanm	82:6473597d706e	2248
bogdanm	82:6473597d706e	2249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2250	//! @brief Read current value of the CAN_ESR1_TWRNINT field.
bogdanm	82:6473597d706e	2251	#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
bogdanm	82:6473597d706e	2252	#endif
bogdanm	82:6473597d706e	2253
bogdanm	82:6473597d706e	2254	//! @brief Format value for bitfield CAN_ESR1_TWRNINT.
bogdanm	82:6473597d706e	2255	#define BF_CAN_ESR1_TWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_TWRNINT), uint32_t) & BM_CAN_ESR1_TWRNINT)
bogdanm	82:6473597d706e	2256
bogdanm	82:6473597d706e	2257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2258	//! @brief Set the TWRNINT field to a new value.
bogdanm	82:6473597d706e	2259	#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
bogdanm	82:6473597d706e	2260	#endif
bogdanm	82:6473597d706e	2261	//@}
bogdanm	82:6473597d706e	2262
bogdanm	82:6473597d706e	2263	/*!
bogdanm	82:6473597d706e	2264	* @name Register CAN_ESR1, field SYNCH[18] (RO)
bogdanm	82:6473597d706e	2265	*
bogdanm	82:6473597d706e	2266	* This read-only flag indicates whether the FlexCAN is synchronized to the CAN
bogdanm	82:6473597d706e	2267	* bus and able to participate in the communication process. It is set and
bogdanm	82:6473597d706e	2268	* cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
bogdanm	82:6473597d706e	2269	*
bogdanm	82:6473597d706e	2270	* Values:
bogdanm	82:6473597d706e	2271	* - 0 - FlexCAN is not synchronized to the CAN bus.
bogdanm	82:6473597d706e	2272	* - 1 - FlexCAN is synchronized to the CAN bus.
bogdanm	82:6473597d706e	2273	*/
bogdanm	82:6473597d706e	2274	//@{
bogdanm	82:6473597d706e	2275	#define BP_CAN_ESR1_SYNCH (18U) //!< Bit position for CAN_ESR1_SYNCH.
bogdanm	82:6473597d706e	2276	#define BM_CAN_ESR1_SYNCH (0x00040000U) //!< Bit mask for CAN_ESR1_SYNCH.
bogdanm	82:6473597d706e	2277	#define BS_CAN_ESR1_SYNCH (1U) //!< Bit field size in bits for CAN_ESR1_SYNCH.
bogdanm	82:6473597d706e	2278
bogdanm	82:6473597d706e	2279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2280	//! @brief Read current value of the CAN_ESR1_SYNCH field.
bogdanm	82:6473597d706e	2281	#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
bogdanm	82:6473597d706e	2282	#endif
bogdanm	82:6473597d706e	2283	//@}
bogdanm	82:6473597d706e	2284
bogdanm	82:6473597d706e	2285	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2286	// HW_CAN_IMASK1 - Interrupt Masks 1 register
bogdanm	82:6473597d706e	2287	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2288
bogdanm	82:6473597d706e	2289	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2290	/*!
bogdanm	82:6473597d706e	2291	* @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
bogdanm	82:6473597d706e	2292	*
bogdanm	82:6473597d706e	2293	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2294	*
bogdanm	82:6473597d706e	2295	* This register allows any number of a range of the 32 Message Buffer
bogdanm	82:6473597d706e	2296	* Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
bogdanm	82:6473597d706e	2297	* bit per buffer, enabling the CPU to determine which buffer generates an
bogdanm	82:6473597d706e	2298	* interrupt after a successful transmission or reception, that is, when the
bogdanm	82:6473597d706e	2299	* corresponding IFLAG1 bit is set.
bogdanm	82:6473597d706e	2300	*/
bogdanm	82:6473597d706e	2301	typedef union _hw_can_imask1
bogdanm	82:6473597d706e	2302	{
bogdanm	82:6473597d706e	2303	uint32_t U;
bogdanm	82:6473597d706e	2304	struct _hw_can_imask1_bitfields
bogdanm	82:6473597d706e	2305	{
bogdanm	82:6473597d706e	2306	uint32_t BUFLM : 32; //!< [31:0] Buffer MB i Mask
bogdanm	82:6473597d706e	2307	} B;
bogdanm	82:6473597d706e	2308	} hw_can_imask1_t;
bogdanm	82:6473597d706e	2309	#endif
bogdanm	82:6473597d706e	2310
bogdanm	82:6473597d706e	2311	/*!
bogdanm	82:6473597d706e	2312	* @name Constants and macros for entire CAN_IMASK1 register
bogdanm	82:6473597d706e	2313	*/
bogdanm	82:6473597d706e	2314	//@{
bogdanm	82:6473597d706e	2315	#define HW_CAN_IMASK1_ADDR(x) (REGS_CAN_BASE(x) + 0x28U)
bogdanm	82:6473597d706e	2316
bogdanm	82:6473597d706e	2317	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2318	#define HW_CAN_IMASK1(x) ((__IO hw_can_imask1_t ) HW_CAN_IMASK1_ADDR(x))
bogdanm	82:6473597d706e	2319	#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
bogdanm	82:6473597d706e	2320	#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
bogdanm	82:6473597d706e	2321	#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) \| (v)))
bogdanm	82:6473597d706e	2322	#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2323	#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2324	#endif
bogdanm	82:6473597d706e	2325	//@}
bogdanm	82:6473597d706e	2326
bogdanm	82:6473597d706e	2327	/*
bogdanm	82:6473597d706e	2328	* Constants & macros for individual CAN_IMASK1 bitfields
bogdanm	82:6473597d706e	2329	*/
bogdanm	82:6473597d706e	2330
bogdanm	82:6473597d706e	2331	/*!
bogdanm	82:6473597d706e	2332	* @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
bogdanm	82:6473597d706e	2333	*
bogdanm	82:6473597d706e	2334	* Each bit enables or disables the corresponding FlexCAN Message Buffer
bogdanm	82:6473597d706e	2335	* Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
bogdanm	82:6473597d706e	2336	* assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
bogdanm	82:6473597d706e	2337	*
bogdanm	82:6473597d706e	2338	* Values:
bogdanm	82:6473597d706e	2339	* - 0 - The corresponding buffer Interrupt is disabled.
bogdanm	82:6473597d706e	2340	* - 1 - The corresponding buffer Interrupt is enabled.
bogdanm	82:6473597d706e	2341	*/
bogdanm	82:6473597d706e	2342	//@{
bogdanm	82:6473597d706e	2343	#define BP_CAN_IMASK1_BUFLM (0U) //!< Bit position for CAN_IMASK1_BUFLM.
bogdanm	82:6473597d706e	2344	#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) //!< Bit mask for CAN_IMASK1_BUFLM.
bogdanm	82:6473597d706e	2345	#define BS_CAN_IMASK1_BUFLM (32U) //!< Bit field size in bits for CAN_IMASK1_BUFLM.
bogdanm	82:6473597d706e	2346
bogdanm	82:6473597d706e	2347	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2348	//! @brief Read current value of the CAN_IMASK1_BUFLM field.
bogdanm	82:6473597d706e	2349	#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
bogdanm	82:6473597d706e	2350	#endif
bogdanm	82:6473597d706e	2351
bogdanm	82:6473597d706e	2352	//! @brief Format value for bitfield CAN_IMASK1_BUFLM.
bogdanm	82:6473597d706e	2353	#define BF_CAN_IMASK1_BUFLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IMASK1_BUFLM), uint32_t) & BM_CAN_IMASK1_BUFLM)
bogdanm	82:6473597d706e	2354
bogdanm	82:6473597d706e	2355	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2356	//! @brief Set the BUFLM field to a new value.
bogdanm	82:6473597d706e	2357	#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
bogdanm	82:6473597d706e	2358	#endif
bogdanm	82:6473597d706e	2359	//@}
bogdanm	82:6473597d706e	2360
bogdanm	82:6473597d706e	2361	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2362	// HW_CAN_IFLAG1 - Interrupt Flags 1 register
bogdanm	82:6473597d706e	2363	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2364
bogdanm	82:6473597d706e	2365	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2366	/*!
bogdanm	82:6473597d706e	2367	* @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
bogdanm	82:6473597d706e	2368	*
bogdanm	82:6473597d706e	2369	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2370	*
bogdanm	82:6473597d706e	2371	* This register defines the flags for the 32 Message Buffer interrupts for MB31
bogdanm	82:6473597d706e	2372	* to MB0. It contains one interrupt flag bit per buffer. Each successful
bogdanm	82:6473597d706e	2373	* transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
bogdanm	82:6473597d706e	2374	* IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
bogdanm	82:6473597d706e	2375	* cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
bogdanm	82:6473597d706e	2376	* are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
bogdanm	82:6473597d706e	2377	* bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
bogdanm	82:6473597d706e	2378	* BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
bogdanm	82:6473597d706e	2379	* the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
bogdanm	82:6473597d706e	2380	* must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
bogdanm	82:6473597d706e	2381	* FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
bogdanm	82:6473597d706e	2382	* belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
bogdanm	82:6473597d706e	2383	* the FIFO flags must be cleared. The same care must be taken when an RFFN
bogdanm	82:6473597d706e	2384	* value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
bogdanm	82:6473597d706e	2385	* 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
bogdanm	82:6473597d706e	2386	* must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
bogdanm	82:6473597d706e	2387	* bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
bogdanm	82:6473597d706e	2388	* they will remain set and be inconsistent with the number of MBs available.
bogdanm	82:6473597d706e	2389	*/
bogdanm	82:6473597d706e	2390	typedef union _hw_can_iflag1
bogdanm	82:6473597d706e	2391	{
bogdanm	82:6473597d706e	2392	uint32_t U;
bogdanm	82:6473597d706e	2393	struct _hw_can_iflag1_bitfields
bogdanm	82:6473597d706e	2394	{
bogdanm	82:6473597d706e	2395	uint32_t BUF0I : 1; //!< [0] Buffer MB0 Interrupt Or "reserved"
bogdanm	82:6473597d706e	2396	uint32_t BUF4TO1I : 4; //!< [4:1] Buffer MB i Interrupt Or "reserved"
bogdanm	82:6473597d706e	2397	uint32_t BUF5I : 1; //!< [5] Buffer MB5 Interrupt Or "Frames
bogdanm	82:6473597d706e	2398	//! available in Rx FIFO"
bogdanm	82:6473597d706e	2399	uint32_t BUF6I : 1; //!< [6] Buffer MB6 Interrupt Or "Rx FIFO Warning"
bogdanm	82:6473597d706e	2400	uint32_t BUF7I : 1; //!< [7] Buffer MB7 Interrupt Or "Rx FIFO
bogdanm	82:6473597d706e	2401	//! Overflow"
bogdanm	82:6473597d706e	2402	uint32_t BUF31TO8I : 24; //!< [31:8] Buffer MBi Interrupt
bogdanm	82:6473597d706e	2403	} B;
bogdanm	82:6473597d706e	2404	} hw_can_iflag1_t;
bogdanm	82:6473597d706e	2405	#endif
bogdanm	82:6473597d706e	2406
bogdanm	82:6473597d706e	2407	/*!
bogdanm	82:6473597d706e	2408	* @name Constants and macros for entire CAN_IFLAG1 register
bogdanm	82:6473597d706e	2409	*/
bogdanm	82:6473597d706e	2410	//@{
bogdanm	82:6473597d706e	2411	#define HW_CAN_IFLAG1_ADDR(x) (REGS_CAN_BASE(x) + 0x30U)
bogdanm	82:6473597d706e	2412
bogdanm	82:6473597d706e	2413	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2414	#define HW_CAN_IFLAG1(x) ((__IO hw_can_iflag1_t ) HW_CAN_IFLAG1_ADDR(x))
bogdanm	82:6473597d706e	2415	#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
bogdanm	82:6473597d706e	2416	#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
bogdanm	82:6473597d706e	2417	#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) \| (v)))
bogdanm	82:6473597d706e	2418	#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2419	#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2420	#endif
bogdanm	82:6473597d706e	2421	//@}
bogdanm	82:6473597d706e	2422
bogdanm	82:6473597d706e	2423	/*
bogdanm	82:6473597d706e	2424	* Constants & macros for individual CAN_IFLAG1 bitfields
bogdanm	82:6473597d706e	2425	*/
bogdanm	82:6473597d706e	2426
bogdanm	82:6473597d706e	2427	/*!
bogdanm	82:6473597d706e	2428	* @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
bogdanm	82:6473597d706e	2429	*
bogdanm	82:6473597d706e	2430	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
bogdanm	82:6473597d706e	2431	* the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
bogdanm	82:6473597d706e	2432	* MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
bogdanm	82:6473597d706e	2433	* set.
bogdanm	82:6473597d706e	2434	*
bogdanm	82:6473597d706e	2435	* Values:
bogdanm	82:6473597d706e	2436	* - 0 - The corresponding buffer has no occurrence of successfully completed
bogdanm	82:6473597d706e	2437	* transmission or reception when MCR[RFEN]=0.
bogdanm	82:6473597d706e	2438	* - 1 - The corresponding buffer has successfully completed transmission or
bogdanm	82:6473597d706e	2439	* reception when MCR[RFEN]=0.
bogdanm	82:6473597d706e	2440	*/
bogdanm	82:6473597d706e	2441	//@{
bogdanm	82:6473597d706e	2442	#define BP_CAN_IFLAG1_BUF0I (0U) //!< Bit position for CAN_IFLAG1_BUF0I.
bogdanm	82:6473597d706e	2443	#define BM_CAN_IFLAG1_BUF0I (0x00000001U) //!< Bit mask for CAN_IFLAG1_BUF0I.
bogdanm	82:6473597d706e	2444	#define BS_CAN_IFLAG1_BUF0I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF0I.
bogdanm	82:6473597d706e	2445
bogdanm	82:6473597d706e	2446	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2447	//! @brief Read current value of the CAN_IFLAG1_BUF0I field.
bogdanm	82:6473597d706e	2448	#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
bogdanm	82:6473597d706e	2449	#endif
bogdanm	82:6473597d706e	2450
bogdanm	82:6473597d706e	2451	//! @brief Format value for bitfield CAN_IFLAG1_BUF0I.
bogdanm	82:6473597d706e	2452	#define BF_CAN_IFLAG1_BUF0I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF0I), uint32_t) & BM_CAN_IFLAG1_BUF0I)
bogdanm	82:6473597d706e	2453
bogdanm	82:6473597d706e	2454	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2455	//! @brief Set the BUF0I field to a new value.
bogdanm	82:6473597d706e	2456	#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
bogdanm	82:6473597d706e	2457	#endif
bogdanm	82:6473597d706e	2458	//@}
bogdanm	82:6473597d706e	2459
bogdanm	82:6473597d706e	2460	/*!
bogdanm	82:6473597d706e	2461	* @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
bogdanm	82:6473597d706e	2462	*
bogdanm	82:6473597d706e	2463	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
bogdanm	82:6473597d706e	2464	* the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
bogdanm	82:6473597d706e	2465	* the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
bogdanm	82:6473597d706e	2466	* when MCR[RFEN] is set.
bogdanm	82:6473597d706e	2467	*
bogdanm	82:6473597d706e	2468	* Values:
bogdanm	82:6473597d706e	2469	* - 0 - The corresponding buffer has no occurrence of successfully completed
bogdanm	82:6473597d706e	2470	* transmission or reception when MCR[RFEN]=0.
bogdanm	82:6473597d706e	2471	* - 1 - The corresponding buffer has successfully completed transmission or
bogdanm	82:6473597d706e	2472	* reception when MCR[RFEN]=0.
bogdanm	82:6473597d706e	2473	*/
bogdanm	82:6473597d706e	2474	//@{
bogdanm	82:6473597d706e	2475	#define BP_CAN_IFLAG1_BUF4TO1I (1U) //!< Bit position for CAN_IFLAG1_BUF4TO1I.
bogdanm	82:6473597d706e	2476	#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) //!< Bit mask for CAN_IFLAG1_BUF4TO1I.
bogdanm	82:6473597d706e	2477	#define BS_CAN_IFLAG1_BUF4TO1I (4U) //!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I.
bogdanm	82:6473597d706e	2478
bogdanm	82:6473597d706e	2479	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2480	//! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field.
bogdanm	82:6473597d706e	2481	#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
bogdanm	82:6473597d706e	2482	#endif
bogdanm	82:6473597d706e	2483
bogdanm	82:6473597d706e	2484	//! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I.
bogdanm	82:6473597d706e	2485	#define BF_CAN_IFLAG1_BUF4TO1I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF4TO1I), uint32_t) & BM_CAN_IFLAG1_BUF4TO1I)
bogdanm	82:6473597d706e	2486
bogdanm	82:6473597d706e	2487	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2488	//! @brief Set the BUF4TO1I field to a new value.
bogdanm	82:6473597d706e	2489	#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) \| BF_CAN_IFLAG1_BUF4TO1I(v)))
bogdanm	82:6473597d706e	2490	#endif
bogdanm	82:6473597d706e	2491	//@}
bogdanm	82:6473597d706e	2492
bogdanm	82:6473597d706e	2493	/*!
bogdanm	82:6473597d706e	2494	* @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
bogdanm	82:6473597d706e	2495	*
bogdanm	82:6473597d706e	2496	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
bogdanm	82:6473597d706e	2497	* the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
bogdanm	82:6473597d706e	2498	* MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
bogdanm	82:6473597d706e	2499	* Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
bogdanm	82:6473597d706e	2500	* least one frame is available to be read from the Rx FIFO.
bogdanm	82:6473597d706e	2501	*
bogdanm	82:6473597d706e	2502	* Values:
bogdanm	82:6473597d706e	2503	* - 0 - No occurrence of MB5 completing transmission/reception when
bogdanm	82:6473597d706e	2504	* MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
bogdanm	82:6473597d706e	2505	* - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
bogdanm	82:6473597d706e	2506	* available in the Rx FIFO when MCR[RFEN]=1
bogdanm	82:6473597d706e	2507	*/
bogdanm	82:6473597d706e	2508	//@{
bogdanm	82:6473597d706e	2509	#define BP_CAN_IFLAG1_BUF5I (5U) //!< Bit position for CAN_IFLAG1_BUF5I.
bogdanm	82:6473597d706e	2510	#define BM_CAN_IFLAG1_BUF5I (0x00000020U) //!< Bit mask for CAN_IFLAG1_BUF5I.
bogdanm	82:6473597d706e	2511	#define BS_CAN_IFLAG1_BUF5I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF5I.
bogdanm	82:6473597d706e	2512
bogdanm	82:6473597d706e	2513	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2514	//! @brief Read current value of the CAN_IFLAG1_BUF5I field.
bogdanm	82:6473597d706e	2515	#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
bogdanm	82:6473597d706e	2516	#endif
bogdanm	82:6473597d706e	2517
bogdanm	82:6473597d706e	2518	//! @brief Format value for bitfield CAN_IFLAG1_BUF5I.
bogdanm	82:6473597d706e	2519	#define BF_CAN_IFLAG1_BUF5I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF5I), uint32_t) & BM_CAN_IFLAG1_BUF5I)
bogdanm	82:6473597d706e	2520
bogdanm	82:6473597d706e	2521	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2522	//! @brief Set the BUF5I field to a new value.
bogdanm	82:6473597d706e	2523	#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
bogdanm	82:6473597d706e	2524	#endif
bogdanm	82:6473597d706e	2525	//@}
bogdanm	82:6473597d706e	2526
bogdanm	82:6473597d706e	2527	/*!
bogdanm	82:6473597d706e	2528	* @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
bogdanm	82:6473597d706e	2529	*
bogdanm	82:6473597d706e	2530	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
bogdanm	82:6473597d706e	2531	* the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
bogdanm	82:6473597d706e	2532	* MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
bogdanm	82:6473597d706e	2533	* when MCR[RFEN] is set. In this case, the flag indicates when the number of
bogdanm	82:6473597d706e	2534	* unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
bogdanm	82:6473597d706e	2535	* a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
bogdanm	82:6473597d706e	2536	* cleared while the number of unread messages is greater than 4, it does not
bogdanm	82:6473597d706e	2537	* assert again until the number of unread messages within the Rx FIFO is decreased
bogdanm	82:6473597d706e	2538	* to be equal to or less than 4.
bogdanm	82:6473597d706e	2539	*
bogdanm	82:6473597d706e	2540	* Values:
bogdanm	82:6473597d706e	2541	* - 0 - No occurrence of MB6 completing transmission/reception when
bogdanm	82:6473597d706e	2542	* MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
bogdanm	82:6473597d706e	2543	* - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
bogdanm	82:6473597d706e	2544	* almost full when MCR[RFEN]=1
bogdanm	82:6473597d706e	2545	*/
bogdanm	82:6473597d706e	2546	//@{
bogdanm	82:6473597d706e	2547	#define BP_CAN_IFLAG1_BUF6I (6U) //!< Bit position for CAN_IFLAG1_BUF6I.
bogdanm	82:6473597d706e	2548	#define BM_CAN_IFLAG1_BUF6I (0x00000040U) //!< Bit mask for CAN_IFLAG1_BUF6I.
bogdanm	82:6473597d706e	2549	#define BS_CAN_IFLAG1_BUF6I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF6I.
bogdanm	82:6473597d706e	2550
bogdanm	82:6473597d706e	2551	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2552	//! @brief Read current value of the CAN_IFLAG1_BUF6I field.
bogdanm	82:6473597d706e	2553	#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
bogdanm	82:6473597d706e	2554	#endif
bogdanm	82:6473597d706e	2555
bogdanm	82:6473597d706e	2556	//! @brief Format value for bitfield CAN_IFLAG1_BUF6I.
bogdanm	82:6473597d706e	2557	#define BF_CAN_IFLAG1_BUF6I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF6I), uint32_t) & BM_CAN_IFLAG1_BUF6I)
bogdanm	82:6473597d706e	2558
bogdanm	82:6473597d706e	2559	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2560	//! @brief Set the BUF6I field to a new value.
bogdanm	82:6473597d706e	2561	#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
bogdanm	82:6473597d706e	2562	#endif
bogdanm	82:6473597d706e	2563	//@}
bogdanm	82:6473597d706e	2564
bogdanm	82:6473597d706e	2565	/*!
bogdanm	82:6473597d706e	2566	* @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
bogdanm	82:6473597d706e	2567	*
bogdanm	82:6473597d706e	2568	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
bogdanm	82:6473597d706e	2569	* the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
bogdanm	82:6473597d706e	2570	* MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
bogdanm	82:6473597d706e	2571	* when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
bogdanm	82:6473597d706e	2572	* because the Rx FIFO is full. Note that the flag will not be asserted when the
bogdanm	82:6473597d706e	2573	* Rx FIFO is full and the message was captured by a Mailbox.
bogdanm	82:6473597d706e	2574	*
bogdanm	82:6473597d706e	2575	* Values:
bogdanm	82:6473597d706e	2576	* - 0 - No occurrence of MB7 completing transmission/reception when
bogdanm	82:6473597d706e	2577	* MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
bogdanm	82:6473597d706e	2578	* - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
bogdanm	82:6473597d706e	2579	* overflow when MCR[RFEN]=1
bogdanm	82:6473597d706e	2580	*/
bogdanm	82:6473597d706e	2581	//@{
bogdanm	82:6473597d706e	2582	#define BP_CAN_IFLAG1_BUF7I (7U) //!< Bit position for CAN_IFLAG1_BUF7I.
bogdanm	82:6473597d706e	2583	#define BM_CAN_IFLAG1_BUF7I (0x00000080U) //!< Bit mask for CAN_IFLAG1_BUF7I.
bogdanm	82:6473597d706e	2584	#define BS_CAN_IFLAG1_BUF7I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF7I.
bogdanm	82:6473597d706e	2585
bogdanm	82:6473597d706e	2586	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2587	//! @brief Read current value of the CAN_IFLAG1_BUF7I field.
bogdanm	82:6473597d706e	2588	#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
bogdanm	82:6473597d706e	2589	#endif
bogdanm	82:6473597d706e	2590
bogdanm	82:6473597d706e	2591	//! @brief Format value for bitfield CAN_IFLAG1_BUF7I.
bogdanm	82:6473597d706e	2592	#define BF_CAN_IFLAG1_BUF7I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF7I), uint32_t) & BM_CAN_IFLAG1_BUF7I)
bogdanm	82:6473597d706e	2593
bogdanm	82:6473597d706e	2594	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2595	//! @brief Set the BUF7I field to a new value.
bogdanm	82:6473597d706e	2596	#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
bogdanm	82:6473597d706e	2597	#endif
bogdanm	82:6473597d706e	2598	//@}
bogdanm	82:6473597d706e	2599
bogdanm	82:6473597d706e	2600	/*!
bogdanm	82:6473597d706e	2601	* @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
bogdanm	82:6473597d706e	2602	*
bogdanm	82:6473597d706e	2603	* Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
bogdanm	82:6473597d706e	2604	* MB8.
bogdanm	82:6473597d706e	2605	*
bogdanm	82:6473597d706e	2606	* Values:
bogdanm	82:6473597d706e	2607	* - 0 - The corresponding buffer has no occurrence of successfully completed
bogdanm	82:6473597d706e	2608	* transmission or reception.
bogdanm	82:6473597d706e	2609	* - 1 - The corresponding buffer has successfully completed transmission or
bogdanm	82:6473597d706e	2610	* reception.
bogdanm	82:6473597d706e	2611	*/
bogdanm	82:6473597d706e	2612	//@{
bogdanm	82:6473597d706e	2613	#define BP_CAN_IFLAG1_BUF31TO8I (8U) //!< Bit position for CAN_IFLAG1_BUF31TO8I.
bogdanm	82:6473597d706e	2614	#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) //!< Bit mask for CAN_IFLAG1_BUF31TO8I.
bogdanm	82:6473597d706e	2615	#define BS_CAN_IFLAG1_BUF31TO8I (24U) //!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I.
bogdanm	82:6473597d706e	2616
bogdanm	82:6473597d706e	2617	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2618	//! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field.
bogdanm	82:6473597d706e	2619	#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
bogdanm	82:6473597d706e	2620	#endif
bogdanm	82:6473597d706e	2621
bogdanm	82:6473597d706e	2622	//! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I.
bogdanm	82:6473597d706e	2623	#define BF_CAN_IFLAG1_BUF31TO8I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF31TO8I), uint32_t) & BM_CAN_IFLAG1_BUF31TO8I)
bogdanm	82:6473597d706e	2624
bogdanm	82:6473597d706e	2625	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2626	//! @brief Set the BUF31TO8I field to a new value.
bogdanm	82:6473597d706e	2627	#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) \| BF_CAN_IFLAG1_BUF31TO8I(v)))
bogdanm	82:6473597d706e	2628	#endif
bogdanm	82:6473597d706e	2629	//@}
bogdanm	82:6473597d706e	2630
bogdanm	82:6473597d706e	2631	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2632	// HW_CAN_CTRL2 - Control 2 register
bogdanm	82:6473597d706e	2633	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2634
bogdanm	82:6473597d706e	2635	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2636	/*!
bogdanm	82:6473597d706e	2637	* @brief HW_CAN_CTRL2 - Control 2 register (RW)
bogdanm	82:6473597d706e	2638	*
bogdanm	82:6473597d706e	2639	* Reset value: 0x00B00000U
bogdanm	82:6473597d706e	2640	*
bogdanm	82:6473597d706e	2641	* This register contains control bits for CAN errors, FIFO features, and mode
bogdanm	82:6473597d706e	2642	* selection.
bogdanm	82:6473597d706e	2643	*/
bogdanm	82:6473597d706e	2644	typedef union _hw_can_ctrl2
bogdanm	82:6473597d706e	2645	{
bogdanm	82:6473597d706e	2646	uint32_t U;
bogdanm	82:6473597d706e	2647	struct _hw_can_ctrl2_bitfields
bogdanm	82:6473597d706e	2648	{
bogdanm	82:6473597d706e	2649	uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm	82:6473597d706e	2650	uint32_t EACEN : 1; //!< [16] Entire Frame Arbitration Field
bogdanm	82:6473597d706e	2651	//! Comparison Enable For Rx Mailboxes
bogdanm	82:6473597d706e	2652	uint32_t RRS : 1; //!< [17] Remote Request Storing
bogdanm	82:6473597d706e	2653	uint32_t MRP : 1; //!< [18] Mailboxes Reception Priority
bogdanm	82:6473597d706e	2654	uint32_t TASD : 5; //!< [23:19] Tx Arbitration Start Delay
bogdanm	82:6473597d706e	2655	uint32_t RFFN : 4; //!< [27:24] Number Of Rx FIFO Filters
bogdanm	82:6473597d706e	2656	uint32_t WRMFRZ : 1; //!< [28] Write-Access To Memory In Freeze Mode
bogdanm	82:6473597d706e	2657	uint32_t RESERVED1 : 3; //!< [31:29]
bogdanm	82:6473597d706e	2658	} B;
bogdanm	82:6473597d706e	2659	} hw_can_ctrl2_t;
bogdanm	82:6473597d706e	2660	#endif
bogdanm	82:6473597d706e	2661
bogdanm	82:6473597d706e	2662	/*!
bogdanm	82:6473597d706e	2663	* @name Constants and macros for entire CAN_CTRL2 register
bogdanm	82:6473597d706e	2664	*/
bogdanm	82:6473597d706e	2665	//@{
bogdanm	82:6473597d706e	2666	#define HW_CAN_CTRL2_ADDR(x) (REGS_CAN_BASE(x) + 0x34U)
bogdanm	82:6473597d706e	2667
bogdanm	82:6473597d706e	2668	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2669	#define HW_CAN_CTRL2(x) ((__IO hw_can_ctrl2_t ) HW_CAN_CTRL2_ADDR(x))
bogdanm	82:6473597d706e	2670	#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
bogdanm	82:6473597d706e	2671	#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
bogdanm	82:6473597d706e	2672	#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) \| (v)))
bogdanm	82:6473597d706e	2673	#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2674	#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2675	#endif
bogdanm	82:6473597d706e	2676	//@}
bogdanm	82:6473597d706e	2677
bogdanm	82:6473597d706e	2678	/*
bogdanm	82:6473597d706e	2679	* Constants & macros for individual CAN_CTRL2 bitfields
bogdanm	82:6473597d706e	2680	*/
bogdanm	82:6473597d706e	2681
bogdanm	82:6473597d706e	2682	/*!
bogdanm	82:6473597d706e	2683	* @name Register CAN_CTRL2, field EACEN[16] (RW)
bogdanm	82:6473597d706e	2684	*
bogdanm	82:6473597d706e	2685	* This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
bogdanm	82:6473597d706e	2686	* filters with their corresponding bits in the incoming frame by the matching
bogdanm	82:6473597d706e	2687	* process. This bit does not affect matching for Rx FIFO. This bit can be written
bogdanm	82:6473597d706e	2688	* only in Freeze mode because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	2689	*
bogdanm	82:6473597d706e	2690	* Values:
bogdanm	82:6473597d706e	2691	* - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
bogdanm	82:6473597d706e	2692	* compared despite mask bits.
bogdanm	82:6473597d706e	2693	* - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
bogdanm	82:6473597d706e	2694	* their corresponding bits within the incoming frame. Mask bits do apply.
bogdanm	82:6473597d706e	2695	*/
bogdanm	82:6473597d706e	2696	//@{
bogdanm	82:6473597d706e	2697	#define BP_CAN_CTRL2_EACEN (16U) //!< Bit position for CAN_CTRL2_EACEN.
bogdanm	82:6473597d706e	2698	#define BM_CAN_CTRL2_EACEN (0x00010000U) //!< Bit mask for CAN_CTRL2_EACEN.
bogdanm	82:6473597d706e	2699	#define BS_CAN_CTRL2_EACEN (1U) //!< Bit field size in bits for CAN_CTRL2_EACEN.
bogdanm	82:6473597d706e	2700
bogdanm	82:6473597d706e	2701	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2702	//! @brief Read current value of the CAN_CTRL2_EACEN field.
bogdanm	82:6473597d706e	2703	#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
bogdanm	82:6473597d706e	2704	#endif
bogdanm	82:6473597d706e	2705
bogdanm	82:6473597d706e	2706	//! @brief Format value for bitfield CAN_CTRL2_EACEN.
bogdanm	82:6473597d706e	2707	#define BF_CAN_CTRL2_EACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_EACEN), uint32_t) & BM_CAN_CTRL2_EACEN)
bogdanm	82:6473597d706e	2708
bogdanm	82:6473597d706e	2709	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2710	//! @brief Set the EACEN field to a new value.
bogdanm	82:6473597d706e	2711	#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
bogdanm	82:6473597d706e	2712	#endif
bogdanm	82:6473597d706e	2713	//@}
bogdanm	82:6473597d706e	2714
bogdanm	82:6473597d706e	2715	/*!
bogdanm	82:6473597d706e	2716	* @name Register CAN_CTRL2, field RRS[17] (RW)
bogdanm	82:6473597d706e	2717	*
bogdanm	82:6473597d706e	2718	* If this bit is asserted Remote Request Frame is submitted to a matching
bogdanm	82:6473597d706e	2719	* process and stored in the corresponding Message Buffer in the same fashion of a
bogdanm	82:6473597d706e	2720	* Data Frame. No automatic Remote Response Frame will be generated. If this bit is
bogdanm	82:6473597d706e	2721	* negated the Remote Request Frame is submitted to a matching process and an
bogdanm	82:6473597d706e	2722	* automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
bogdanm	82:6473597d706e	2723	* is found with the same ID. This bit can be written only in Freeze mode
bogdanm	82:6473597d706e	2724	* because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	2725	*
bogdanm	82:6473597d706e	2726	* Values:
bogdanm	82:6473597d706e	2727	* - 0 - Remote Response Frame is generated.
bogdanm	82:6473597d706e	2728	* - 1 - Remote Request Frame is stored.
bogdanm	82:6473597d706e	2729	*/
bogdanm	82:6473597d706e	2730	//@{
bogdanm	82:6473597d706e	2731	#define BP_CAN_CTRL2_RRS (17U) //!< Bit position for CAN_CTRL2_RRS.
bogdanm	82:6473597d706e	2732	#define BM_CAN_CTRL2_RRS (0x00020000U) //!< Bit mask for CAN_CTRL2_RRS.
bogdanm	82:6473597d706e	2733	#define BS_CAN_CTRL2_RRS (1U) //!< Bit field size in bits for CAN_CTRL2_RRS.
bogdanm	82:6473597d706e	2734
bogdanm	82:6473597d706e	2735	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2736	//! @brief Read current value of the CAN_CTRL2_RRS field.
bogdanm	82:6473597d706e	2737	#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
bogdanm	82:6473597d706e	2738	#endif
bogdanm	82:6473597d706e	2739
bogdanm	82:6473597d706e	2740	//! @brief Format value for bitfield CAN_CTRL2_RRS.
bogdanm	82:6473597d706e	2741	#define BF_CAN_CTRL2_RRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RRS), uint32_t) & BM_CAN_CTRL2_RRS)
bogdanm	82:6473597d706e	2742
bogdanm	82:6473597d706e	2743	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2744	//! @brief Set the RRS field to a new value.
bogdanm	82:6473597d706e	2745	#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
bogdanm	82:6473597d706e	2746	#endif
bogdanm	82:6473597d706e	2747	//@}
bogdanm	82:6473597d706e	2748
bogdanm	82:6473597d706e	2749	/*!
bogdanm	82:6473597d706e	2750	* @name Register CAN_CTRL2, field MRP[18] (RW)
bogdanm	82:6473597d706e	2751	*
bogdanm	82:6473597d706e	2752	* If this bit is set the matching process starts from the Mailboxes and if no
bogdanm	82:6473597d706e	2753	* match occurs the matching continues on the Rx FIFO. This bit can be written
bogdanm	82:6473597d706e	2754	* only in Freeze mode because it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	2755	*
bogdanm	82:6473597d706e	2756	* Values:
bogdanm	82:6473597d706e	2757	* - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
bogdanm	82:6473597d706e	2758	* - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
bogdanm	82:6473597d706e	2759	*/
bogdanm	82:6473597d706e	2760	//@{
bogdanm	82:6473597d706e	2761	#define BP_CAN_CTRL2_MRP (18U) //!< Bit position for CAN_CTRL2_MRP.
bogdanm	82:6473597d706e	2762	#define BM_CAN_CTRL2_MRP (0x00040000U) //!< Bit mask for CAN_CTRL2_MRP.
bogdanm	82:6473597d706e	2763	#define BS_CAN_CTRL2_MRP (1U) //!< Bit field size in bits for CAN_CTRL2_MRP.
bogdanm	82:6473597d706e	2764
bogdanm	82:6473597d706e	2765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2766	//! @brief Read current value of the CAN_CTRL2_MRP field.
bogdanm	82:6473597d706e	2767	#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
bogdanm	82:6473597d706e	2768	#endif
bogdanm	82:6473597d706e	2769
bogdanm	82:6473597d706e	2770	//! @brief Format value for bitfield CAN_CTRL2_MRP.
bogdanm	82:6473597d706e	2771	#define BF_CAN_CTRL2_MRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_MRP), uint32_t) & BM_CAN_CTRL2_MRP)
bogdanm	82:6473597d706e	2772
bogdanm	82:6473597d706e	2773	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2774	//! @brief Set the MRP field to a new value.
bogdanm	82:6473597d706e	2775	#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
bogdanm	82:6473597d706e	2776	#endif
bogdanm	82:6473597d706e	2777	//@}
bogdanm	82:6473597d706e	2778
bogdanm	82:6473597d706e	2779	/*!
bogdanm	82:6473597d706e	2780	* @name Register CAN_CTRL2, field TASD[23:19] (RW)
bogdanm	82:6473597d706e	2781	*
bogdanm	82:6473597d706e	2782	* This 5-bit field indicates how many CAN bits the Tx arbitration process start
bogdanm	82:6473597d706e	2783	* point can be delayed from the first bit of CRC field on CAN bus. This field
bogdanm	82:6473597d706e	2784	* can be written only in Freeze mode because it is blocked by hardware in other
bogdanm	82:6473597d706e	2785	* modes. This field is useful to optimize the transmit performance based on
bogdanm	82:6473597d706e	2786	* factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
bogdanm	82:6473597d706e	2787	* The duration of an arbitration process, in terms of CAN bits, is directly
bogdanm	82:6473597d706e	2788	* proportional to the number of available MBs and CAN baud rate and inversely
bogdanm	82:6473597d706e	2789	* proportional to the peripheral clock frequency. The optimal arbitration timing is
bogdanm	82:6473597d706e	2790	* that in which the last MB is scanned right before the first bit of the
bogdanm	82:6473597d706e	2791	* Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
bogdanm	82:6473597d706e	2792	* clock ratio is high and the CAN baud rate is low then the arbitration can be
bogdanm	82:6473597d706e	2793	* delayed and vice-versa. If TASD is 0 then the arbitration start is not
bogdanm	82:6473597d706e	2794	* delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
bogdanm	82:6473597d706e	2795	* but more time is reserved for arbitration. On the other hand, if TASD is 24 then
bogdanm	82:6473597d706e	2796	* the CPU can configure a Tx MB later and less time is reserved for
bogdanm	82:6473597d706e	2797	* arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
bogdanm	82:6473597d706e	2798	* to find winner MBs in time to compete with other nodes for the CAN bus. If the
bogdanm	82:6473597d706e	2799	* arbitration ends too much time before the first bit of Intermission field then
bogdanm	82:6473597d706e	2800	* there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
bogdanm	82:6473597d706e	2801	* not the best to be transmitted. The optimal configuration for TASD can be
bogdanm	82:6473597d706e	2802	* calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
bogdanm	82:6473597d706e	2803	* 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
bogdanm	82:6473597d706e	2804	* CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
bogdanm	82:6473597d706e	2805	* Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
bogdanm	82:6473597d706e	2806	* field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
bogdanm	82:6473597d706e	2807	* PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
bogdanm	82:6473597d706e	2808	* field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
bogdanm	82:6473597d706e	2809	* CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
bogdanm	82:6473597d706e	2810	* Timing" for more details.
bogdanm	82:6473597d706e	2811	*/
bogdanm	82:6473597d706e	2812	//@{
bogdanm	82:6473597d706e	2813	#define BP_CAN_CTRL2_TASD (19U) //!< Bit position for CAN_CTRL2_TASD.
bogdanm	82:6473597d706e	2814	#define BM_CAN_CTRL2_TASD (0x00F80000U) //!< Bit mask for CAN_CTRL2_TASD.
bogdanm	82:6473597d706e	2815	#define BS_CAN_CTRL2_TASD (5U) //!< Bit field size in bits for CAN_CTRL2_TASD.
bogdanm	82:6473597d706e	2816
bogdanm	82:6473597d706e	2817	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2818	//! @brief Read current value of the CAN_CTRL2_TASD field.
bogdanm	82:6473597d706e	2819	#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
bogdanm	82:6473597d706e	2820	#endif
bogdanm	82:6473597d706e	2821
bogdanm	82:6473597d706e	2822	//! @brief Format value for bitfield CAN_CTRL2_TASD.
bogdanm	82:6473597d706e	2823	#define BF_CAN_CTRL2_TASD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_TASD), uint32_t) & BM_CAN_CTRL2_TASD)
bogdanm	82:6473597d706e	2824
bogdanm	82:6473597d706e	2825	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2826	//! @brief Set the TASD field to a new value.
bogdanm	82:6473597d706e	2827	#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) \| BF_CAN_CTRL2_TASD(v)))
bogdanm	82:6473597d706e	2828	#endif
bogdanm	82:6473597d706e	2829	//@}
bogdanm	82:6473597d706e	2830
bogdanm	82:6473597d706e	2831	/*!
bogdanm	82:6473597d706e	2832	* @name Register CAN_CTRL2, field RFFN[27:24] (RW)
bogdanm	82:6473597d706e	2833	*
bogdanm	82:6473597d706e	2834	* This 4-bit field defines the number of Rx FIFO filters, as shown in the
bogdanm	82:6473597d706e	2835	* following table. The maximum selectable number of filters is determined by the MCU.
bogdanm	82:6473597d706e	2836	* This field can only be written in Freeze mode as it is blocked by hardware in
bogdanm	82:6473597d706e	2837	* other modes. This field must not be programmed with values that make the
bogdanm	82:6473597d706e	2838	* number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
bogdanm	82:6473597d706e	2839	* Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
bogdanm	82:6473597d706e	2840	* a memory space equivalent to two Message Buffers which means that the more
bogdanm	82:6473597d706e	2841	* filters are implemented the less Mailboxes will be available. Considering that
bogdanm	82:6473597d706e	2842	* the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
bogdanm	82:6473597d706e	2843	* be programmed with a value correponding to a number of filters not greater
bogdanm	82:6473597d706e	2844	* than the number of available memory words which can be calculated as follows:
bogdanm	82:6473597d706e	2845	* (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
bogdanm	82:6473597d706e	2846	* The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
bogdanm	82:6473597d706e	2847	* 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
bogdanm	82:6473597d706e	2848	* SETUP_MB value (memory space available) the exceeding ones will not be functional.
bogdanm	82:6473597d706e	2849	* RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
bogdanm	82:6473597d706e	2850	* Filter Table Remaining Available MailboxesThe number of the last remaining
bogdanm	82:6473597d706e	2851	* available mailboxes is defined by the least value between the parameter
bogdanm	82:6473597d706e	2852	* NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
bogdanm	82:6473597d706e	2853	* by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
bogdanm	82:6473597d706e	2854	* all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
bogdanm	82:6473597d706e	2855	* Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
bogdanm	82:6473597d706e	2856	* 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
bogdanm	82:6473597d706e	2857	* 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
bogdanm	82:6473597d706e	2858	* Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
bogdanm	82:6473597d706e	2859	* 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
bogdanm	82:6473597d706e	2860	* Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
bogdanm	82:6473597d706e	2861	* 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
bogdanm	82:6473597d706e	2862	* Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
bogdanm	82:6473597d706e	2863	* 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
bogdanm	82:6473597d706e	2864	* 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
bogdanm	82:6473597d706e	2865	* Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
bogdanm	82:6473597d706e	2866	* 0-37 MB 38-63 Elements 0-31 Elements 32-127
bogdanm	82:6473597d706e	2867	*/
bogdanm	82:6473597d706e	2868	//@{
bogdanm	82:6473597d706e	2869	#define BP_CAN_CTRL2_RFFN (24U) //!< Bit position for CAN_CTRL2_RFFN.
bogdanm	82:6473597d706e	2870	#define BM_CAN_CTRL2_RFFN (0x0F000000U) //!< Bit mask for CAN_CTRL2_RFFN.
bogdanm	82:6473597d706e	2871	#define BS_CAN_CTRL2_RFFN (4U) //!< Bit field size in bits for CAN_CTRL2_RFFN.
bogdanm	82:6473597d706e	2872
bogdanm	82:6473597d706e	2873	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2874	//! @brief Read current value of the CAN_CTRL2_RFFN field.
bogdanm	82:6473597d706e	2875	#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
bogdanm	82:6473597d706e	2876	#endif
bogdanm	82:6473597d706e	2877
bogdanm	82:6473597d706e	2878	//! @brief Format value for bitfield CAN_CTRL2_RFFN.
bogdanm	82:6473597d706e	2879	#define BF_CAN_CTRL2_RFFN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RFFN), uint32_t) & BM_CAN_CTRL2_RFFN)
bogdanm	82:6473597d706e	2880
bogdanm	82:6473597d706e	2881	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2882	//! @brief Set the RFFN field to a new value.
bogdanm	82:6473597d706e	2883	#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) \| BF_CAN_CTRL2_RFFN(v)))
bogdanm	82:6473597d706e	2884	#endif
bogdanm	82:6473597d706e	2885	//@}
bogdanm	82:6473597d706e	2886
bogdanm	82:6473597d706e	2887	/*!
bogdanm	82:6473597d706e	2888	* @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
bogdanm	82:6473597d706e	2889	*
bogdanm	82:6473597d706e	2890	* Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
bogdanm	82:6473597d706e	2891	* can only be written in Freeze mode and has no effect out of Freeze mode.
bogdanm	82:6473597d706e	2892	*
bogdanm	82:6473597d706e	2893	* Values:
bogdanm	82:6473597d706e	2894	* - 0 - Maintain the write access restrictions.
bogdanm	82:6473597d706e	2895	* - 1 - Enable unrestricted write access to FlexCAN memory.
bogdanm	82:6473597d706e	2896	*/
bogdanm	82:6473597d706e	2897	//@{
bogdanm	82:6473597d706e	2898	#define BP_CAN_CTRL2_WRMFRZ (28U) //!< Bit position for CAN_CTRL2_WRMFRZ.
bogdanm	82:6473597d706e	2899	#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) //!< Bit mask for CAN_CTRL2_WRMFRZ.
bogdanm	82:6473597d706e	2900	#define BS_CAN_CTRL2_WRMFRZ (1U) //!< Bit field size in bits for CAN_CTRL2_WRMFRZ.
bogdanm	82:6473597d706e	2901
bogdanm	82:6473597d706e	2902	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2903	//! @brief Read current value of the CAN_CTRL2_WRMFRZ field.
bogdanm	82:6473597d706e	2904	#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
bogdanm	82:6473597d706e	2905	#endif
bogdanm	82:6473597d706e	2906
bogdanm	82:6473597d706e	2907	//! @brief Format value for bitfield CAN_CTRL2_WRMFRZ.
bogdanm	82:6473597d706e	2908	#define BF_CAN_CTRL2_WRMFRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_WRMFRZ), uint32_t) & BM_CAN_CTRL2_WRMFRZ)
bogdanm	82:6473597d706e	2909
bogdanm	82:6473597d706e	2910	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2911	//! @brief Set the WRMFRZ field to a new value.
bogdanm	82:6473597d706e	2912	#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
bogdanm	82:6473597d706e	2913	#endif
bogdanm	82:6473597d706e	2914	//@}
bogdanm	82:6473597d706e	2915
bogdanm	82:6473597d706e	2916	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2917	// HW_CAN_ESR2 - Error and Status 2 register
bogdanm	82:6473597d706e	2918	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2919
bogdanm	82:6473597d706e	2920	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2921	/*!
bogdanm	82:6473597d706e	2922	* @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
bogdanm	82:6473597d706e	2923	*
bogdanm	82:6473597d706e	2924	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2925	*
bogdanm	82:6473597d706e	2926	* This register reflects various interrupt flags and some general status.
bogdanm	82:6473597d706e	2927	*/
bogdanm	82:6473597d706e	2928	typedef union _hw_can_esr2
bogdanm	82:6473597d706e	2929	{
bogdanm	82:6473597d706e	2930	uint32_t U;
bogdanm	82:6473597d706e	2931	struct _hw_can_esr2_bitfields
bogdanm	82:6473597d706e	2932	{
bogdanm	82:6473597d706e	2933	uint32_t RESERVED0 : 13; //!< [12:0]
bogdanm	82:6473597d706e	2934	uint32_t IMB : 1; //!< [13] Inactive Mailbox
bogdanm	82:6473597d706e	2935	uint32_t VPS : 1; //!< [14] Valid Priority Status
bogdanm	82:6473597d706e	2936	uint32_t RESERVED1 : 1; //!< [15]
bogdanm	82:6473597d706e	2937	uint32_t LPTM : 7; //!< [22:16] Lowest Priority Tx Mailbox
bogdanm	82:6473597d706e	2938	uint32_t RESERVED2 : 9; //!< [31:23]
bogdanm	82:6473597d706e	2939	} B;
bogdanm	82:6473597d706e	2940	} hw_can_esr2_t;
bogdanm	82:6473597d706e	2941	#endif
bogdanm	82:6473597d706e	2942
bogdanm	82:6473597d706e	2943	/*!
bogdanm	82:6473597d706e	2944	* @name Constants and macros for entire CAN_ESR2 register
bogdanm	82:6473597d706e	2945	*/
bogdanm	82:6473597d706e	2946	//@{
bogdanm	82:6473597d706e	2947	#define HW_CAN_ESR2_ADDR(x) (REGS_CAN_BASE(x) + 0x38U)
bogdanm	82:6473597d706e	2948
bogdanm	82:6473597d706e	2949	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2950	#define HW_CAN_ESR2(x) ((__I hw_can_esr2_t ) HW_CAN_ESR2_ADDR(x))
bogdanm	82:6473597d706e	2951	#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
bogdanm	82:6473597d706e	2952	#endif
bogdanm	82:6473597d706e	2953	//@}
bogdanm	82:6473597d706e	2954
bogdanm	82:6473597d706e	2955	/*
bogdanm	82:6473597d706e	2956	* Constants & macros for individual CAN_ESR2 bitfields
bogdanm	82:6473597d706e	2957	*/
bogdanm	82:6473597d706e	2958
bogdanm	82:6473597d706e	2959	/*!
bogdanm	82:6473597d706e	2960	* @name Register CAN_ESR2, field IMB[13] (RO)
bogdanm	82:6473597d706e	2961	*
bogdanm	82:6473597d706e	2962	* If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
bogdanm	82:6473597d706e	2963	* Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
bogdanm	82:6473597d706e	2964	* following cases: During arbitration, if an LPTM is found and it is inactive. If
bogdanm	82:6473597d706e	2965	* IMB is not asserted and a frame is transmitted successfully. This bit is
bogdanm	82:6473597d706e	2966	* cleared in all start of arbitration (see Section "Arbitration process"). LPTM
bogdanm	82:6473597d706e	2967	* mechanism have the following behavior: if an MB is successfully transmitted and
bogdanm	82:6473597d706e	2968	* ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
bogdanm	82:6473597d706e	2969	* the index related to the MB just transmitted is loaded into ESR2[LPTM].
bogdanm	82:6473597d706e	2970	*
bogdanm	82:6473597d706e	2971	* Values:
bogdanm	82:6473597d706e	2972	* - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
bogdanm	82:6473597d706e	2973	* - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
bogdanm	82:6473597d706e	2974	* content is the number of the first one.
bogdanm	82:6473597d706e	2975	*/
bogdanm	82:6473597d706e	2976	//@{
bogdanm	82:6473597d706e	2977	#define BP_CAN_ESR2_IMB (13U) //!< Bit position for CAN_ESR2_IMB.
bogdanm	82:6473597d706e	2978	#define BM_CAN_ESR2_IMB (0x00002000U) //!< Bit mask for CAN_ESR2_IMB.
bogdanm	82:6473597d706e	2979	#define BS_CAN_ESR2_IMB (1U) //!< Bit field size in bits for CAN_ESR2_IMB.
bogdanm	82:6473597d706e	2980
bogdanm	82:6473597d706e	2981	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2982	//! @brief Read current value of the CAN_ESR2_IMB field.
bogdanm	82:6473597d706e	2983	#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
bogdanm	82:6473597d706e	2984	#endif
bogdanm	82:6473597d706e	2985	//@}
bogdanm	82:6473597d706e	2986
bogdanm	82:6473597d706e	2987	/*!
bogdanm	82:6473597d706e	2988	* @name Register CAN_ESR2, field VPS[14] (RO)
bogdanm	82:6473597d706e	2989	*
bogdanm	82:6473597d706e	2990	* This bit indicates whether IMB and LPTM contents are currently valid or not.
bogdanm	82:6473597d706e	2991	* VPS is asserted upon every complete Tx arbitration process unless the CPU
bogdanm	82:6473597d706e	2992	* writes to Control and Status word of a Mailbox that has already been scanned, that
bogdanm	82:6473597d706e	2993	* is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
bogdanm	82:6473597d706e	2994	* If there is no inactive Mailbox and only one Tx Mailbox that is being
bogdanm	82:6473597d706e	2995	* transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
bogdanm	82:6473597d706e	2996	* arbitration process or upon a write to Control and Status word of any Mailbox.
bogdanm	82:6473597d706e	2997	* ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
bogdanm	82:6473597d706e	2998	* blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
bogdanm	82:6473597d706e	2999	* in C/S of a MB that is being transmitted (pending abort), or any write attempt
bogdanm	82:6473597d706e	3000	* into a Tx MB with IFLAG set is blocked.
bogdanm	82:6473597d706e	3001	*
bogdanm	82:6473597d706e	3002	* Values:
bogdanm	82:6473597d706e	3003	* - 0 - Contents of IMB and LPTM are invalid.
bogdanm	82:6473597d706e	3004	* - 1 - Contents of IMB and LPTM are valid.
bogdanm	82:6473597d706e	3005	*/
bogdanm	82:6473597d706e	3006	//@{
bogdanm	82:6473597d706e	3007	#define BP_CAN_ESR2_VPS (14U) //!< Bit position for CAN_ESR2_VPS.
bogdanm	82:6473597d706e	3008	#define BM_CAN_ESR2_VPS (0x00004000U) //!< Bit mask for CAN_ESR2_VPS.
bogdanm	82:6473597d706e	3009	#define BS_CAN_ESR2_VPS (1U) //!< Bit field size in bits for CAN_ESR2_VPS.
bogdanm	82:6473597d706e	3010
bogdanm	82:6473597d706e	3011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3012	//! @brief Read current value of the CAN_ESR2_VPS field.
bogdanm	82:6473597d706e	3013	#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
bogdanm	82:6473597d706e	3014	#endif
bogdanm	82:6473597d706e	3015	//@}
bogdanm	82:6473597d706e	3016
bogdanm	82:6473597d706e	3017	/*!
bogdanm	82:6473597d706e	3018	* @name Register CAN_ESR2, field LPTM[22:16] (RO)
bogdanm	82:6473597d706e	3019	*
bogdanm	82:6473597d706e	3020	* If ESR2[VPS] is asserted, this field indicates the lowest number inactive
bogdanm	82:6473597d706e	3021	* Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
bogdanm	82:6473597d706e	3022	* Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
bogdanm	82:6473597d706e	3023	* negated then the Mailbox indicated is the one that has the greatest arbitration
bogdanm	82:6473597d706e	3024	* value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
bogdanm	82:6473597d706e	3025	* asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
bogdanm	82:6473597d706e	3026	* a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
bogdanm	82:6473597d706e	3027	* If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
bogdanm	82:6473597d706e	3028	* updated with its Mailbox number.
bogdanm	82:6473597d706e	3029	*/
bogdanm	82:6473597d706e	3030	//@{
bogdanm	82:6473597d706e	3031	#define BP_CAN_ESR2_LPTM (16U) //!< Bit position for CAN_ESR2_LPTM.
bogdanm	82:6473597d706e	3032	#define BM_CAN_ESR2_LPTM (0x007F0000U) //!< Bit mask for CAN_ESR2_LPTM.
bogdanm	82:6473597d706e	3033	#define BS_CAN_ESR2_LPTM (7U) //!< Bit field size in bits for CAN_ESR2_LPTM.
bogdanm	82:6473597d706e	3034
bogdanm	82:6473597d706e	3035	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3036	//! @brief Read current value of the CAN_ESR2_LPTM field.
bogdanm	82:6473597d706e	3037	#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
bogdanm	82:6473597d706e	3038	#endif
bogdanm	82:6473597d706e	3039	//@}
bogdanm	82:6473597d706e	3040
bogdanm	82:6473597d706e	3041	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3042	// HW_CAN_CRCR - CRC Register
bogdanm	82:6473597d706e	3043	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3044
bogdanm	82:6473597d706e	3045	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3046	/*!
bogdanm	82:6473597d706e	3047	* @brief HW_CAN_CRCR - CRC Register (RO)
bogdanm	82:6473597d706e	3048	*
bogdanm	82:6473597d706e	3049	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3050	*
bogdanm	82:6473597d706e	3051	* This register provides information about the CRC of transmitted messages.
bogdanm	82:6473597d706e	3052	*/
bogdanm	82:6473597d706e	3053	typedef union _hw_can_crcr
bogdanm	82:6473597d706e	3054	{
bogdanm	82:6473597d706e	3055	uint32_t U;
bogdanm	82:6473597d706e	3056	struct _hw_can_crcr_bitfields
bogdanm	82:6473597d706e	3057	{
bogdanm	82:6473597d706e	3058	uint32_t TXCRC : 15; //!< [14:0] CRC Transmitted
bogdanm	82:6473597d706e	3059	uint32_t RESERVED0 : 1; //!< [15]
bogdanm	82:6473597d706e	3060	uint32_t MBCRC : 7; //!< [22:16] CRC Mailbox
bogdanm	82:6473597d706e	3061	uint32_t RESERVED1 : 9; //!< [31:23]
bogdanm	82:6473597d706e	3062	} B;
bogdanm	82:6473597d706e	3063	} hw_can_crcr_t;
bogdanm	82:6473597d706e	3064	#endif
bogdanm	82:6473597d706e	3065
bogdanm	82:6473597d706e	3066	/*!
bogdanm	82:6473597d706e	3067	* @name Constants and macros for entire CAN_CRCR register
bogdanm	82:6473597d706e	3068	*/
bogdanm	82:6473597d706e	3069	//@{
bogdanm	82:6473597d706e	3070	#define HW_CAN_CRCR_ADDR(x) (REGS_CAN_BASE(x) + 0x44U)
bogdanm	82:6473597d706e	3071
bogdanm	82:6473597d706e	3072	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3073	#define HW_CAN_CRCR(x) ((__I hw_can_crcr_t ) HW_CAN_CRCR_ADDR(x))
bogdanm	82:6473597d706e	3074	#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
bogdanm	82:6473597d706e	3075	#endif
bogdanm	82:6473597d706e	3076	//@}
bogdanm	82:6473597d706e	3077
bogdanm	82:6473597d706e	3078	/*
bogdanm	82:6473597d706e	3079	* Constants & macros for individual CAN_CRCR bitfields
bogdanm	82:6473597d706e	3080	*/
bogdanm	82:6473597d706e	3081
bogdanm	82:6473597d706e	3082	/*!
bogdanm	82:6473597d706e	3083	* @name Register CAN_CRCR, field TXCRC[14:0] (RO)
bogdanm	82:6473597d706e	3084	*
bogdanm	82:6473597d706e	3085	* This field indicates the CRC value of the last message transmitted. This
bogdanm	82:6473597d706e	3086	* field is updated at the same time the Tx Interrupt Flag is asserted.
bogdanm	82:6473597d706e	3087	*/
bogdanm	82:6473597d706e	3088	//@{
bogdanm	82:6473597d706e	3089	#define BP_CAN_CRCR_TXCRC (0U) //!< Bit position for CAN_CRCR_TXCRC.
bogdanm	82:6473597d706e	3090	#define BM_CAN_CRCR_TXCRC (0x00007FFFU) //!< Bit mask for CAN_CRCR_TXCRC.
bogdanm	82:6473597d706e	3091	#define BS_CAN_CRCR_TXCRC (15U) //!< Bit field size in bits for CAN_CRCR_TXCRC.
bogdanm	82:6473597d706e	3092
bogdanm	82:6473597d706e	3093	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3094	//! @brief Read current value of the CAN_CRCR_TXCRC field.
bogdanm	82:6473597d706e	3095	#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
bogdanm	82:6473597d706e	3096	#endif
bogdanm	82:6473597d706e	3097	//@}
bogdanm	82:6473597d706e	3098
bogdanm	82:6473597d706e	3099	/*!
bogdanm	82:6473597d706e	3100	* @name Register CAN_CRCR, field MBCRC[22:16] (RO)
bogdanm	82:6473597d706e	3101	*
bogdanm	82:6473597d706e	3102	* This field indicates the number of the Mailbox corresponding to the value in
bogdanm	82:6473597d706e	3103	* TXCRC field.
bogdanm	82:6473597d706e	3104	*/
bogdanm	82:6473597d706e	3105	//@{
bogdanm	82:6473597d706e	3106	#define BP_CAN_CRCR_MBCRC (16U) //!< Bit position for CAN_CRCR_MBCRC.
bogdanm	82:6473597d706e	3107	#define BM_CAN_CRCR_MBCRC (0x007F0000U) //!< Bit mask for CAN_CRCR_MBCRC.
bogdanm	82:6473597d706e	3108	#define BS_CAN_CRCR_MBCRC (7U) //!< Bit field size in bits for CAN_CRCR_MBCRC.
bogdanm	82:6473597d706e	3109
bogdanm	82:6473597d706e	3110	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3111	//! @brief Read current value of the CAN_CRCR_MBCRC field.
bogdanm	82:6473597d706e	3112	#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
bogdanm	82:6473597d706e	3113	#endif
bogdanm	82:6473597d706e	3114	//@}
bogdanm	82:6473597d706e	3115
bogdanm	82:6473597d706e	3116	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3117	// HW_CAN_RXFGMASK - Rx FIFO Global Mask register
bogdanm	82:6473597d706e	3118	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3119
bogdanm	82:6473597d706e	3120	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3121	/*!
bogdanm	82:6473597d706e	3122	* @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
bogdanm	82:6473597d706e	3123	*
bogdanm	82:6473597d706e	3124	* Reset value: 0xFFFFFFFFU
bogdanm	82:6473597d706e	3125	*
bogdanm	82:6473597d706e	3126	* This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
bogdanm	82:6473597d706e	3127	* mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
bogdanm	82:6473597d706e	3128	* according to CTRL2[RFFN] field setting. This register can only be written in
bogdanm	82:6473597d706e	3129	* Freeze mode as it is blocked by hardware in other modes.
bogdanm	82:6473597d706e	3130	*/
bogdanm	82:6473597d706e	3131	typedef union _hw_can_rxfgmask
bogdanm	82:6473597d706e	3132	{
bogdanm	82:6473597d706e	3133	uint32_t U;
bogdanm	82:6473597d706e	3134	struct _hw_can_rxfgmask_bitfields
bogdanm	82:6473597d706e	3135	{
bogdanm	82:6473597d706e	3136	uint32_t FGM : 32; //!< [31:0] Rx FIFO Global Mask Bits
bogdanm	82:6473597d706e	3137	} B;
bogdanm	82:6473597d706e	3138	} hw_can_rxfgmask_t;
bogdanm	82:6473597d706e	3139	#endif
bogdanm	82:6473597d706e	3140
bogdanm	82:6473597d706e	3141	/*!
bogdanm	82:6473597d706e	3142	* @name Constants and macros for entire CAN_RXFGMASK register
bogdanm	82:6473597d706e	3143	*/
bogdanm	82:6473597d706e	3144	//@{
bogdanm	82:6473597d706e	3145	#define HW_CAN_RXFGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x48U)
bogdanm	82:6473597d706e	3146
bogdanm	82:6473597d706e	3147	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3148	#define HW_CAN_RXFGMASK(x) ((__IO hw_can_rxfgmask_t ) HW_CAN_RXFGMASK_ADDR(x))
bogdanm	82:6473597d706e	3149	#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
bogdanm	82:6473597d706e	3150	#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
bogdanm	82:6473597d706e	3151	#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) \| (v)))
bogdanm	82:6473597d706e	3152	#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3153	#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3154	#endif
bogdanm	82:6473597d706e	3155	//@}
bogdanm	82:6473597d706e	3156
bogdanm	82:6473597d706e	3157	/*
bogdanm	82:6473597d706e	3158	* Constants & macros for individual CAN_RXFGMASK bitfields
bogdanm	82:6473597d706e	3159	*/
bogdanm	82:6473597d706e	3160
bogdanm	82:6473597d706e	3161	/*!
bogdanm	82:6473597d706e	3162	* @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
bogdanm	82:6473597d706e	3163	*
bogdanm	82:6473597d706e	3164	* These bits mask the ID Filter Table elements bits in a perfect alignment. The
bogdanm	82:6473597d706e	3165	* following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
bogdanm	82:6473597d706e	3166	* ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
bogdanm	82:6473597d706e	3167	* Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
bogdanm	82:6473597d706e	3168	* the fourteen most significant bits of the Identifier of the incoming frame are
bogdanm	82:6473597d706e	3169	* compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
bogdanm	82:6473597d706e	3170	* the format C only the eight most significant bits of the Identifier of the
bogdanm	82:6473597d706e	3171	* incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
bogdanm	82:6473597d706e	3172	* FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
bogdanm	82:6473597d706e	3173	* - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
bogdanm	82:6473597d706e	3174	*
bogdanm	82:6473597d706e	3175	* Values:
bogdanm	82:6473597d706e	3176	* - 0 - The corresponding bit in the filter is "don't care."
bogdanm	82:6473597d706e	3177	* - 1 - The corresponding bit in the filter is checked.
bogdanm	82:6473597d706e	3178	*/
bogdanm	82:6473597d706e	3179	//@{
bogdanm	82:6473597d706e	3180	#define BP_CAN_RXFGMASK_FGM (0U) //!< Bit position for CAN_RXFGMASK_FGM.
bogdanm	82:6473597d706e	3181	#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) //!< Bit mask for CAN_RXFGMASK_FGM.
bogdanm	82:6473597d706e	3182	#define BS_CAN_RXFGMASK_FGM (32U) //!< Bit field size in bits for CAN_RXFGMASK_FGM.
bogdanm	82:6473597d706e	3183
bogdanm	82:6473597d706e	3184	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3185	//! @brief Read current value of the CAN_RXFGMASK_FGM field.
bogdanm	82:6473597d706e	3186	#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
bogdanm	82:6473597d706e	3187	#endif
bogdanm	82:6473597d706e	3188
bogdanm	82:6473597d706e	3189	//! @brief Format value for bitfield CAN_RXFGMASK_FGM.
bogdanm	82:6473597d706e	3190	#define BF_CAN_RXFGMASK_FGM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXFGMASK_FGM), uint32_t) & BM_CAN_RXFGMASK_FGM)
bogdanm	82:6473597d706e	3191
bogdanm	82:6473597d706e	3192	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3193	//! @brief Set the FGM field to a new value.
bogdanm	82:6473597d706e	3194	#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
bogdanm	82:6473597d706e	3195	#endif
bogdanm	82:6473597d706e	3196	//@}
bogdanm	82:6473597d706e	3197
bogdanm	82:6473597d706e	3198	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3199	// HW_CAN_RXFIR - Rx FIFO Information Register
bogdanm	82:6473597d706e	3200	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3201
bogdanm	82:6473597d706e	3202	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3203	/*!
bogdanm	82:6473597d706e	3204	* @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
bogdanm	82:6473597d706e	3205	*
bogdanm	82:6473597d706e	3206	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3207	*
bogdanm	82:6473597d706e	3208	* RXFIR provides information on Rx FIFO. This register is the port through
bogdanm	82:6473597d706e	3209	* which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
bogdanm	82:6473597d706e	3210	* is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
bogdanm	82:6473597d706e	3211	* well as its output is updated whenever the output of the Rx FIFO is updated
bogdanm	82:6473597d706e	3212	* with the next message. See Section "Rx FIFO" for instructions on reading this
bogdanm	82:6473597d706e	3213	* register.
bogdanm	82:6473597d706e	3214	*/
bogdanm	82:6473597d706e	3215	typedef union _hw_can_rxfir
bogdanm	82:6473597d706e	3216	{
bogdanm	82:6473597d706e	3217	uint32_t U;
bogdanm	82:6473597d706e	3218	struct _hw_can_rxfir_bitfields
bogdanm	82:6473597d706e	3219	{
bogdanm	82:6473597d706e	3220	uint32_t IDHIT : 9; //!< [8:0] Identifier Acceptance Filter Hit
bogdanm	82:6473597d706e	3221	//! Indicator
bogdanm	82:6473597d706e	3222	uint32_t RESERVED0 : 23; //!< [31:9]
bogdanm	82:6473597d706e	3223	} B;
bogdanm	82:6473597d706e	3224	} hw_can_rxfir_t;
bogdanm	82:6473597d706e	3225	#endif
bogdanm	82:6473597d706e	3226
bogdanm	82:6473597d706e	3227	/*!
bogdanm	82:6473597d706e	3228	* @name Constants and macros for entire CAN_RXFIR register
bogdanm	82:6473597d706e	3229	*/
bogdanm	82:6473597d706e	3230	//@{
bogdanm	82:6473597d706e	3231	#define HW_CAN_RXFIR_ADDR(x) (REGS_CAN_BASE(x) + 0x4CU)
bogdanm	82:6473597d706e	3232
bogdanm	82:6473597d706e	3233	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3234	#define HW_CAN_RXFIR(x) ((__I hw_can_rxfir_t ) HW_CAN_RXFIR_ADDR(x))
bogdanm	82:6473597d706e	3235	#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
bogdanm	82:6473597d706e	3236	#endif
bogdanm	82:6473597d706e	3237	//@}
bogdanm	82:6473597d706e	3238
bogdanm	82:6473597d706e	3239	/*
bogdanm	82:6473597d706e	3240	* Constants & macros for individual CAN_RXFIR bitfields
bogdanm	82:6473597d706e	3241	*/
bogdanm	82:6473597d706e	3242
bogdanm	82:6473597d706e	3243	/*!
bogdanm	82:6473597d706e	3244	* @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
bogdanm	82:6473597d706e	3245	*
bogdanm	82:6473597d706e	3246	* This field indicates which Identifier Acceptance Filter was hit by the
bogdanm	82:6473597d706e	3247	* received message that is in the output of the Rx FIFO. If multiple filters match the
bogdanm	82:6473597d706e	3248	* incoming message ID then the first matching IDAF found (lowest number) by the
bogdanm	82:6473597d706e	3249	* matching process is indicated. This field is valid only while the
bogdanm	82:6473597d706e	3250	* IFLAG[BUF5I] is asserted.
bogdanm	82:6473597d706e	3251	*/
bogdanm	82:6473597d706e	3252	//@{
bogdanm	82:6473597d706e	3253	#define BP_CAN_RXFIR_IDHIT (0U) //!< Bit position for CAN_RXFIR_IDHIT.
bogdanm	82:6473597d706e	3254	#define BM_CAN_RXFIR_IDHIT (0x000001FFU) //!< Bit mask for CAN_RXFIR_IDHIT.
bogdanm	82:6473597d706e	3255	#define BS_CAN_RXFIR_IDHIT (9U) //!< Bit field size in bits for CAN_RXFIR_IDHIT.
bogdanm	82:6473597d706e	3256
bogdanm	82:6473597d706e	3257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3258	//! @brief Read current value of the CAN_RXFIR_IDHIT field.
bogdanm	82:6473597d706e	3259	#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
bogdanm	82:6473597d706e	3260	#endif
bogdanm	82:6473597d706e	3261	//@}
bogdanm	82:6473597d706e	3262
bogdanm	82:6473597d706e	3263	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3264	// HW_CAN_CS - Message Buffer 0 CS Register
bogdanm	82:6473597d706e	3265	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3266
bogdanm	82:6473597d706e	3267	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3268	/*!
bogdanm	82:6473597d706e	3269	* @brief HW_CAN_CS - Message Buffer 0 CS Register (RW)
bogdanm	82:6473597d706e	3270	*
bogdanm	82:6473597d706e	3271	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3272	*/
bogdanm	82:6473597d706e	3273	typedef union _hw_can_cs
bogdanm	82:6473597d706e	3274	{
bogdanm	82:6473597d706e	3275	uint32_t U;
bogdanm	82:6473597d706e	3276	struct _hw_can_cs_bitfields
bogdanm	82:6473597d706e	3277	{
bogdanm	82:6473597d706e	3278	uint32_t TIME_STAMP : 16; //!< [15:0] Free-Running Counter Time
bogdanm	82:6473597d706e	3279	//! stamp. This 16-bit field is a copy of the Free-Running Timer, captured for
bogdanm	82:6473597d706e	3280	//! Tx and Rx frames at the time when the beginning of the Identifier
bogdanm	82:6473597d706e	3281	//! field appears on the CAN bus.
bogdanm	82:6473597d706e	3282	uint32_t DLC : 4; //!< [19:16] Length of the data to be
bogdanm	82:6473597d706e	3283	//! stored/transmitted.
bogdanm	82:6473597d706e	3284	uint32_t RTR : 1; //!< [20] Remote Transmission Request. One/zero for
bogdanm	82:6473597d706e	3285	//! remote/data frame.
bogdanm	82:6473597d706e	3286	uint32_t IDE : 1; //!< [21] ID Extended. One/zero for
bogdanm	82:6473597d706e	3287	//! extended/standard format frame.
bogdanm	82:6473597d706e	3288	uint32_t SRR : 1; //!< [22] Substitute Remote Request. Contains a
bogdanm	82:6473597d706e	3289	//! fixed recessive bit.
bogdanm	82:6473597d706e	3290	uint32_t RESERVED0 : 1; //!< [23] Reserved
bogdanm	82:6473597d706e	3291	uint32_t CODE : 4; //!< [27:24] Reserved
bogdanm	82:6473597d706e	3292	uint32_t RESERVED1 : 4; //!< [31:28] Reserved
bogdanm	82:6473597d706e	3293	} B;
bogdanm	82:6473597d706e	3294	} hw_can_cs_t;
bogdanm	82:6473597d706e	3295	#endif
bogdanm	82:6473597d706e	3296
bogdanm	82:6473597d706e	3297	/*!
bogdanm	82:6473597d706e	3298	* @name Constants and macros for entire CAN_CS register
bogdanm	82:6473597d706e	3299	*/
bogdanm	82:6473597d706e	3300	//@{
bogdanm	82:6473597d706e	3301	#define HW_CAN_CS_COUNT (16U)
bogdanm	82:6473597d706e	3302
bogdanm	82:6473597d706e	3303	#define HW_CAN_CS_ADDR(x, n) (REGS_CAN_BASE(x) + 0x80U + (0x10U * n))
bogdanm	82:6473597d706e	3304
bogdanm	82:6473597d706e	3305	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3306	#define HW_CAN_CS(x, n) ((__IO hw_can_cs_t ) HW_CAN_CS_ADDR(x, n))
bogdanm	82:6473597d706e	3307	#define HW_CAN_CS_RD(x, n) (HW_CAN_CS(x, n).U)
bogdanm	82:6473597d706e	3308	#define HW_CAN_CS_WR(x, n, v) (HW_CAN_CS(x, n).U = (v))
bogdanm	82:6473597d706e	3309	#define HW_CAN_CS_SET(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3310	#define HW_CAN_CS_CLR(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3311	#define HW_CAN_CS_TOG(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3312	#endif
bogdanm	82:6473597d706e	3313	//@}
bogdanm	82:6473597d706e	3314
bogdanm	82:6473597d706e	3315	/*
bogdanm	82:6473597d706e	3316	* Constants & macros for individual CAN_CS bitfields
bogdanm	82:6473597d706e	3317	*/
bogdanm	82:6473597d706e	3318
bogdanm	82:6473597d706e	3319	/*!
bogdanm	82:6473597d706e	3320	* @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
bogdanm	82:6473597d706e	3321	*/
bogdanm	82:6473597d706e	3322	//@{
bogdanm	82:6473597d706e	3323	#define BP_CAN_CS_TIME_STAMP (0U) //!< Bit position for CAN_CS_TIME_STAMP.
bogdanm	82:6473597d706e	3324	#define BM_CAN_CS_TIME_STAMP (0x0000FFFFU) //!< Bit mask for CAN_CS_TIME_STAMP.
bogdanm	82:6473597d706e	3325	#define BS_CAN_CS_TIME_STAMP (16U) //!< Bit field size in bits for CAN_CS_TIME_STAMP.
bogdanm	82:6473597d706e	3326
bogdanm	82:6473597d706e	3327	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3328	//! @brief Read current value of the CAN_CS_TIME_STAMP field.
bogdanm	82:6473597d706e	3329	#define BR_CAN_CS_TIME_STAMP(x, n) (HW_CAN_CS(x, n).B.TIME_STAMP)
bogdanm	82:6473597d706e	3330	#endif
bogdanm	82:6473597d706e	3331
bogdanm	82:6473597d706e	3332	//! @brief Format value for bitfield CAN_CS_TIME_STAMP.
bogdanm	82:6473597d706e	3333	#define BF_CAN_CS_TIME_STAMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_TIME_STAMP), uint32_t) & BM_CAN_CS_TIME_STAMP)
bogdanm	82:6473597d706e	3334
bogdanm	82:6473597d706e	3335	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3336	//! @brief Set the TIME_STAMP field to a new value.
bogdanm	82:6473597d706e	3337	#define BW_CAN_CS_TIME_STAMP(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_TIME_STAMP) \| BF_CAN_CS_TIME_STAMP(v)))
bogdanm	82:6473597d706e	3338	#endif
bogdanm	82:6473597d706e	3339	//@}
bogdanm	82:6473597d706e	3340
bogdanm	82:6473597d706e	3341	/*!
bogdanm	82:6473597d706e	3342	* @name Register CAN_CS, field DLC[19:16] (RW)
bogdanm	82:6473597d706e	3343	*/
bogdanm	82:6473597d706e	3344	//@{
bogdanm	82:6473597d706e	3345	#define BP_CAN_CS_DLC (16U) //!< Bit position for CAN_CS_DLC.
bogdanm	82:6473597d706e	3346	#define BM_CAN_CS_DLC (0x000F0000U) //!< Bit mask for CAN_CS_DLC.
bogdanm	82:6473597d706e	3347	#define BS_CAN_CS_DLC (4U) //!< Bit field size in bits for CAN_CS_DLC.
bogdanm	82:6473597d706e	3348
bogdanm	82:6473597d706e	3349	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3350	//! @brief Read current value of the CAN_CS_DLC field.
bogdanm	82:6473597d706e	3351	#define BR_CAN_CS_DLC(x, n) (HW_CAN_CS(x, n).B.DLC)
bogdanm	82:6473597d706e	3352	#endif
bogdanm	82:6473597d706e	3353
bogdanm	82:6473597d706e	3354	//! @brief Format value for bitfield CAN_CS_DLC.
bogdanm	82:6473597d706e	3355	#define BF_CAN_CS_DLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_DLC), uint32_t) & BM_CAN_CS_DLC)
bogdanm	82:6473597d706e	3356
bogdanm	82:6473597d706e	3357	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3358	//! @brief Set the DLC field to a new value.
bogdanm	82:6473597d706e	3359	#define BW_CAN_CS_DLC(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_DLC) \| BF_CAN_CS_DLC(v)))
bogdanm	82:6473597d706e	3360	#endif
bogdanm	82:6473597d706e	3361	//@}
bogdanm	82:6473597d706e	3362
bogdanm	82:6473597d706e	3363	/*!
bogdanm	82:6473597d706e	3364	* @name Register CAN_CS, field RTR[20] (RW)
bogdanm	82:6473597d706e	3365	*/
bogdanm	82:6473597d706e	3366	//@{
bogdanm	82:6473597d706e	3367	#define BP_CAN_CS_RTR (20U) //!< Bit position for CAN_CS_RTR.
bogdanm	82:6473597d706e	3368	#define BM_CAN_CS_RTR (0x00100000U) //!< Bit mask for CAN_CS_RTR.
bogdanm	82:6473597d706e	3369	#define BS_CAN_CS_RTR (1U) //!< Bit field size in bits for CAN_CS_RTR.
bogdanm	82:6473597d706e	3370
bogdanm	82:6473597d706e	3371	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3372	//! @brief Read current value of the CAN_CS_RTR field.
bogdanm	82:6473597d706e	3373	#define BR_CAN_CS_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR))
bogdanm	82:6473597d706e	3374	#endif
bogdanm	82:6473597d706e	3375
bogdanm	82:6473597d706e	3376	//! @brief Format value for bitfield CAN_CS_RTR.
bogdanm	82:6473597d706e	3377	#define BF_CAN_CS_RTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_RTR), uint32_t) & BM_CAN_CS_RTR)
bogdanm	82:6473597d706e	3378
bogdanm	82:6473597d706e	3379	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3380	//! @brief Set the RTR field to a new value.
bogdanm	82:6473597d706e	3381	#define BW_CAN_CS_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR) = (v))
bogdanm	82:6473597d706e	3382	#endif
bogdanm	82:6473597d706e	3383	//@}
bogdanm	82:6473597d706e	3384
bogdanm	82:6473597d706e	3385	/*!
bogdanm	82:6473597d706e	3386	* @name Register CAN_CS, field IDE[21] (RW)
bogdanm	82:6473597d706e	3387	*/
bogdanm	82:6473597d706e	3388	//@{
bogdanm	82:6473597d706e	3389	#define BP_CAN_CS_IDE (21U) //!< Bit position for CAN_CS_IDE.
bogdanm	82:6473597d706e	3390	#define BM_CAN_CS_IDE (0x00200000U) //!< Bit mask for CAN_CS_IDE.
bogdanm	82:6473597d706e	3391	#define BS_CAN_CS_IDE (1U) //!< Bit field size in bits for CAN_CS_IDE.
bogdanm	82:6473597d706e	3392
bogdanm	82:6473597d706e	3393	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3394	//! @brief Read current value of the CAN_CS_IDE field.
bogdanm	82:6473597d706e	3395	#define BR_CAN_CS_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE))
bogdanm	82:6473597d706e	3396	#endif
bogdanm	82:6473597d706e	3397
bogdanm	82:6473597d706e	3398	//! @brief Format value for bitfield CAN_CS_IDE.
bogdanm	82:6473597d706e	3399	#define BF_CAN_CS_IDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_IDE), uint32_t) & BM_CAN_CS_IDE)
bogdanm	82:6473597d706e	3400
bogdanm	82:6473597d706e	3401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3402	//! @brief Set the IDE field to a new value.
bogdanm	82:6473597d706e	3403	#define BW_CAN_CS_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE) = (v))
bogdanm	82:6473597d706e	3404	#endif
bogdanm	82:6473597d706e	3405	//@}
bogdanm	82:6473597d706e	3406
bogdanm	82:6473597d706e	3407	/*!
bogdanm	82:6473597d706e	3408	* @name Register CAN_CS, field SRR[22] (RW)
bogdanm	82:6473597d706e	3409	*/
bogdanm	82:6473597d706e	3410	//@{
bogdanm	82:6473597d706e	3411	#define BP_CAN_CS_SRR (22U) //!< Bit position for CAN_CS_SRR.
bogdanm	82:6473597d706e	3412	#define BM_CAN_CS_SRR (0x00400000U) //!< Bit mask for CAN_CS_SRR.
bogdanm	82:6473597d706e	3413	#define BS_CAN_CS_SRR (1U) //!< Bit field size in bits for CAN_CS_SRR.
bogdanm	82:6473597d706e	3414
bogdanm	82:6473597d706e	3415	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3416	//! @brief Read current value of the CAN_CS_SRR field.
bogdanm	82:6473597d706e	3417	#define BR_CAN_CS_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR))
bogdanm	82:6473597d706e	3418	#endif
bogdanm	82:6473597d706e	3419
bogdanm	82:6473597d706e	3420	//! @brief Format value for bitfield CAN_CS_SRR.
bogdanm	82:6473597d706e	3421	#define BF_CAN_CS_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_SRR), uint32_t) & BM_CAN_CS_SRR)
bogdanm	82:6473597d706e	3422
bogdanm	82:6473597d706e	3423	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3424	//! @brief Set the SRR field to a new value.
bogdanm	82:6473597d706e	3425	#define BW_CAN_CS_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR) = (v))
bogdanm	82:6473597d706e	3426	#endif
bogdanm	82:6473597d706e	3427	//@}
bogdanm	82:6473597d706e	3428
bogdanm	82:6473597d706e	3429	/*!
bogdanm	82:6473597d706e	3430	* @name Register CAN_CS, field CODE[27:24] (RW)
bogdanm	82:6473597d706e	3431	*/
bogdanm	82:6473597d706e	3432	//@{
bogdanm	82:6473597d706e	3433	#define BP_CAN_CS_CODE (24U) //!< Bit position for CAN_CS_CODE.
bogdanm	82:6473597d706e	3434	#define BM_CAN_CS_CODE (0x0F000000U) //!< Bit mask for CAN_CS_CODE.
bogdanm	82:6473597d706e	3435	#define BS_CAN_CS_CODE (4U) //!< Bit field size in bits for CAN_CS_CODE.
bogdanm	82:6473597d706e	3436
bogdanm	82:6473597d706e	3437	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3438	//! @brief Read current value of the CAN_CS_CODE field.
bogdanm	82:6473597d706e	3439	#define BR_CAN_CS_CODE(x, n) (HW_CAN_CS(x, n).B.CODE)
bogdanm	82:6473597d706e	3440	#endif
bogdanm	82:6473597d706e	3441
bogdanm	82:6473597d706e	3442	//! @brief Format value for bitfield CAN_CS_CODE.
bogdanm	82:6473597d706e	3443	#define BF_CAN_CS_CODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_CODE), uint32_t) & BM_CAN_CS_CODE)
bogdanm	82:6473597d706e	3444
bogdanm	82:6473597d706e	3445	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3446	//! @brief Set the CODE field to a new value.
bogdanm	82:6473597d706e	3447	#define BW_CAN_CS_CODE(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_CODE) \| BF_CAN_CS_CODE(v)))
bogdanm	82:6473597d706e	3448	#endif
bogdanm	82:6473597d706e	3449	//@}
bogdanm	82:6473597d706e	3450	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3451	// HW_CAN_ID - Message Buffer 0 ID Register
bogdanm	82:6473597d706e	3452	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3453
bogdanm	82:6473597d706e	3454	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3455	/*!
bogdanm	82:6473597d706e	3456	* @brief HW_CAN_ID - Message Buffer 0 ID Register (RW)
bogdanm	82:6473597d706e	3457	*
bogdanm	82:6473597d706e	3458	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3459	*/
bogdanm	82:6473597d706e	3460	typedef union _hw_can_id
bogdanm	82:6473597d706e	3461	{
bogdanm	82:6473597d706e	3462	uint32_t U;
bogdanm	82:6473597d706e	3463	struct _hw_can_id_bitfields
bogdanm	82:6473597d706e	3464	{
bogdanm	82:6473597d706e	3465	uint32_t EXT : 18; //!< [17:0] Contains extended (LOW word)
bogdanm	82:6473597d706e	3466	//! identifier of message buffer.
bogdanm	82:6473597d706e	3467	uint32_t STD : 11; //!< [28:18] Contains standard/extended (HIGH
bogdanm	82:6473597d706e	3468	//! word) identifier of message buffer.
bogdanm	82:6473597d706e	3469	uint32_t PRIO : 3; //!< [31:29] Local priority. This 3-bit fieldis
bogdanm	82:6473597d706e	3470	//! only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
bogdanm	82:6473597d706e	3471	//! buffers. These bits are not transmitted. They are appended to the
bogdanm	82:6473597d706e	3472	//! regular ID to define the transmission priority.
bogdanm	82:6473597d706e	3473	} B;
bogdanm	82:6473597d706e	3474	} hw_can_id_t;
bogdanm	82:6473597d706e	3475	#endif
bogdanm	82:6473597d706e	3476
bogdanm	82:6473597d706e	3477	/*!
bogdanm	82:6473597d706e	3478	* @name Constants and macros for entire CAN_ID register
bogdanm	82:6473597d706e	3479	*/
bogdanm	82:6473597d706e	3480	//@{
bogdanm	82:6473597d706e	3481	#define HW_CAN_ID_COUNT (16U)
bogdanm	82:6473597d706e	3482
bogdanm	82:6473597d706e	3483	#define HW_CAN_ID_ADDR(x, n) (REGS_CAN_BASE(x) + 0x84U + (0x10U * n))
bogdanm	82:6473597d706e	3484
bogdanm	82:6473597d706e	3485	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3486	#define HW_CAN_ID(x, n) ((__IO hw_can_id_t ) HW_CAN_ID_ADDR(x, n))
bogdanm	82:6473597d706e	3487	#define HW_CAN_ID_RD(x, n) (HW_CAN_ID(x, n).U)
bogdanm	82:6473597d706e	3488	#define HW_CAN_ID_WR(x, n, v) (HW_CAN_ID(x, n).U = (v))
bogdanm	82:6473597d706e	3489	#define HW_CAN_ID_SET(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3490	#define HW_CAN_ID_CLR(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3491	#define HW_CAN_ID_TOG(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3492	#endif
bogdanm	82:6473597d706e	3493	//@}
bogdanm	82:6473597d706e	3494
bogdanm	82:6473597d706e	3495	/*
bogdanm	82:6473597d706e	3496	* Constants & macros for individual CAN_ID bitfields
bogdanm	82:6473597d706e	3497	*/
bogdanm	82:6473597d706e	3498
bogdanm	82:6473597d706e	3499	/*!
bogdanm	82:6473597d706e	3500	* @name Register CAN_ID, field EXT[17:0] (RW)
bogdanm	82:6473597d706e	3501	*/
bogdanm	82:6473597d706e	3502	//@{
bogdanm	82:6473597d706e	3503	#define BP_CAN_ID_EXT (0U) //!< Bit position for CAN_ID_EXT.
bogdanm	82:6473597d706e	3504	#define BM_CAN_ID_EXT (0x0003FFFFU) //!< Bit mask for CAN_ID_EXT.
bogdanm	82:6473597d706e	3505	#define BS_CAN_ID_EXT (18U) //!< Bit field size in bits for CAN_ID_EXT.
bogdanm	82:6473597d706e	3506
bogdanm	82:6473597d706e	3507	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3508	//! @brief Read current value of the CAN_ID_EXT field.
bogdanm	82:6473597d706e	3509	#define BR_CAN_ID_EXT(x, n) (HW_CAN_ID(x, n).B.EXT)
bogdanm	82:6473597d706e	3510	#endif
bogdanm	82:6473597d706e	3511
bogdanm	82:6473597d706e	3512	//! @brief Format value for bitfield CAN_ID_EXT.
bogdanm	82:6473597d706e	3513	#define BF_CAN_ID_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_EXT), uint32_t) & BM_CAN_ID_EXT)
bogdanm	82:6473597d706e	3514
bogdanm	82:6473597d706e	3515	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3516	//! @brief Set the EXT field to a new value.
bogdanm	82:6473597d706e	3517	#define BW_CAN_ID_EXT(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_EXT) \| BF_CAN_ID_EXT(v)))
bogdanm	82:6473597d706e	3518	#endif
bogdanm	82:6473597d706e	3519	//@}
bogdanm	82:6473597d706e	3520
bogdanm	82:6473597d706e	3521	/*!
bogdanm	82:6473597d706e	3522	* @name Register CAN_ID, field STD[28:18] (RW)
bogdanm	82:6473597d706e	3523	*/
bogdanm	82:6473597d706e	3524	//@{
bogdanm	82:6473597d706e	3525	#define BP_CAN_ID_STD (18U) //!< Bit position for CAN_ID_STD.
bogdanm	82:6473597d706e	3526	#define BM_CAN_ID_STD (0x1FFC0000U) //!< Bit mask for CAN_ID_STD.
bogdanm	82:6473597d706e	3527	#define BS_CAN_ID_STD (11U) //!< Bit field size in bits for CAN_ID_STD.
bogdanm	82:6473597d706e	3528
bogdanm	82:6473597d706e	3529	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3530	//! @brief Read current value of the CAN_ID_STD field.
bogdanm	82:6473597d706e	3531	#define BR_CAN_ID_STD(x, n) (HW_CAN_ID(x, n).B.STD)
bogdanm	82:6473597d706e	3532	#endif
bogdanm	82:6473597d706e	3533
bogdanm	82:6473597d706e	3534	//! @brief Format value for bitfield CAN_ID_STD.
bogdanm	82:6473597d706e	3535	#define BF_CAN_ID_STD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_STD), uint32_t) & BM_CAN_ID_STD)
bogdanm	82:6473597d706e	3536
bogdanm	82:6473597d706e	3537	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3538	//! @brief Set the STD field to a new value.
bogdanm	82:6473597d706e	3539	#define BW_CAN_ID_STD(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_STD) \| BF_CAN_ID_STD(v)))
bogdanm	82:6473597d706e	3540	#endif
bogdanm	82:6473597d706e	3541	//@}
bogdanm	82:6473597d706e	3542
bogdanm	82:6473597d706e	3543	/*!
bogdanm	82:6473597d706e	3544	* @name Register CAN_ID, field PRIO[31:29] (RW)
bogdanm	82:6473597d706e	3545	*/
bogdanm	82:6473597d706e	3546	//@{
bogdanm	82:6473597d706e	3547	#define BP_CAN_ID_PRIO (29U) //!< Bit position for CAN_ID_PRIO.
bogdanm	82:6473597d706e	3548	#define BM_CAN_ID_PRIO (0xE0000000U) //!< Bit mask for CAN_ID_PRIO.
bogdanm	82:6473597d706e	3549	#define BS_CAN_ID_PRIO (3U) //!< Bit field size in bits for CAN_ID_PRIO.
bogdanm	82:6473597d706e	3550
bogdanm	82:6473597d706e	3551	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3552	//! @brief Read current value of the CAN_ID_PRIO field.
bogdanm	82:6473597d706e	3553	#define BR_CAN_ID_PRIO(x, n) (HW_CAN_ID(x, n).B.PRIO)
bogdanm	82:6473597d706e	3554	#endif
bogdanm	82:6473597d706e	3555
bogdanm	82:6473597d706e	3556	//! @brief Format value for bitfield CAN_ID_PRIO.
bogdanm	82:6473597d706e	3557	#define BF_CAN_ID_PRIO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_PRIO), uint32_t) & BM_CAN_ID_PRIO)
bogdanm	82:6473597d706e	3558
bogdanm	82:6473597d706e	3559	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3560	//! @brief Set the PRIO field to a new value.
bogdanm	82:6473597d706e	3561	#define BW_CAN_ID_PRIO(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_PRIO) \| BF_CAN_ID_PRIO(v)))
bogdanm	82:6473597d706e	3562	#endif
bogdanm	82:6473597d706e	3563	//@}
bogdanm	82:6473597d706e	3564	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3565	// HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
bogdanm	82:6473597d706e	3566	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3567
bogdanm	82:6473597d706e	3568	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3569	/*!
bogdanm	82:6473597d706e	3570	* @brief HW_CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
bogdanm	82:6473597d706e	3571	*
bogdanm	82:6473597d706e	3572	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3573	*/
bogdanm	82:6473597d706e	3574	typedef union _hw_can_word0
bogdanm	82:6473597d706e	3575	{
bogdanm	82:6473597d706e	3576	uint32_t U;
bogdanm	82:6473597d706e	3577	struct _hw_can_word0_bitfields
bogdanm	82:6473597d706e	3578	{
bogdanm	82:6473597d706e	3579	uint32_t DATA_BYTE_3 : 8; //!< [7:0] Data byte 3 of Rx/Tx frame.
bogdanm	82:6473597d706e	3580	uint32_t DATA_BYTE_2 : 8; //!< [15:8] Data byte 2 of Rx/Tx frame.
bogdanm	82:6473597d706e	3581	uint32_t DATA_BYTE_1 : 8; //!< [23:16] Data byte 1 of Rx/Tx frame.
bogdanm	82:6473597d706e	3582	uint32_t DATA_BYTE_0 : 8; //!< [31:24] Data byte 0 of Rx/Tx frame.
bogdanm	82:6473597d706e	3583	} B;
bogdanm	82:6473597d706e	3584	} hw_can_word0_t;
bogdanm	82:6473597d706e	3585	#endif
bogdanm	82:6473597d706e	3586
bogdanm	82:6473597d706e	3587	/*!
bogdanm	82:6473597d706e	3588	* @name Constants and macros for entire CAN_WORD0 register
bogdanm	82:6473597d706e	3589	*/
bogdanm	82:6473597d706e	3590	//@{
bogdanm	82:6473597d706e	3591	#define HW_CAN_WORD0_COUNT (16U)
bogdanm	82:6473597d706e	3592
bogdanm	82:6473597d706e	3593	#define HW_CAN_WORD0_ADDR(x, n) (REGS_CAN_BASE(x) + 0x88U + (0x10U * n))
bogdanm	82:6473597d706e	3594
bogdanm	82:6473597d706e	3595	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3596	#define HW_CAN_WORD0(x, n) ((__IO hw_can_word0_t ) HW_CAN_WORD0_ADDR(x, n))
bogdanm	82:6473597d706e	3597	#define HW_CAN_WORD0_RD(x, n) (HW_CAN_WORD0(x, n).U)
bogdanm	82:6473597d706e	3598	#define HW_CAN_WORD0_WR(x, n, v) (HW_CAN_WORD0(x, n).U = (v))
bogdanm	82:6473597d706e	3599	#define HW_CAN_WORD0_SET(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3600	#define HW_CAN_WORD0_CLR(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3601	#define HW_CAN_WORD0_TOG(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3602	#endif
bogdanm	82:6473597d706e	3603	//@}
bogdanm	82:6473597d706e	3604
bogdanm	82:6473597d706e	3605	/*
bogdanm	82:6473597d706e	3606	* Constants & macros for individual CAN_WORD0 bitfields
bogdanm	82:6473597d706e	3607	*/
bogdanm	82:6473597d706e	3608
bogdanm	82:6473597d706e	3609	/*!
bogdanm	82:6473597d706e	3610	* @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
bogdanm	82:6473597d706e	3611	*/
bogdanm	82:6473597d706e	3612	//@{
bogdanm	82:6473597d706e	3613	#define BP_CAN_WORD0_DATA_BYTE_3 (0U) //!< Bit position for CAN_WORD0_DATA_BYTE_3.
bogdanm	82:6473597d706e	3614	#define BM_CAN_WORD0_DATA_BYTE_3 (0x000000FFU) //!< Bit mask for CAN_WORD0_DATA_BYTE_3.
bogdanm	82:6473597d706e	3615	#define BS_CAN_WORD0_DATA_BYTE_3 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_3.
bogdanm	82:6473597d706e	3616
bogdanm	82:6473597d706e	3617	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3618	//! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field.
bogdanm	82:6473597d706e	3619	#define BR_CAN_WORD0_DATA_BYTE_3(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_3)
bogdanm	82:6473597d706e	3620	#endif
bogdanm	82:6473597d706e	3621
bogdanm	82:6473597d706e	3622	//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_3.
bogdanm	82:6473597d706e	3623	#define BF_CAN_WORD0_DATA_BYTE_3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_3), uint32_t) & BM_CAN_WORD0_DATA_BYTE_3)
bogdanm	82:6473597d706e	3624
bogdanm	82:6473597d706e	3625	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3626	//! @brief Set the DATA_BYTE_3 field to a new value.
bogdanm	82:6473597d706e	3627	#define BW_CAN_WORD0_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_3) \| BF_CAN_WORD0_DATA_BYTE_3(v)))
bogdanm	82:6473597d706e	3628	#endif
bogdanm	82:6473597d706e	3629	//@}
bogdanm	82:6473597d706e	3630
bogdanm	82:6473597d706e	3631	/*!
bogdanm	82:6473597d706e	3632	* @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
bogdanm	82:6473597d706e	3633	*/
bogdanm	82:6473597d706e	3634	//@{
bogdanm	82:6473597d706e	3635	#define BP_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit position for CAN_WORD0_DATA_BYTE_2.
bogdanm	82:6473597d706e	3636	#define BM_CAN_WORD0_DATA_BYTE_2 (0x0000FF00U) //!< Bit mask for CAN_WORD0_DATA_BYTE_2.
bogdanm	82:6473597d706e	3637	#define BS_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_2.
bogdanm	82:6473597d706e	3638
bogdanm	82:6473597d706e	3639	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3640	//! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field.
bogdanm	82:6473597d706e	3641	#define BR_CAN_WORD0_DATA_BYTE_2(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_2)
bogdanm	82:6473597d706e	3642	#endif
bogdanm	82:6473597d706e	3643
bogdanm	82:6473597d706e	3644	//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_2.
bogdanm	82:6473597d706e	3645	#define BF_CAN_WORD0_DATA_BYTE_2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_2), uint32_t) & BM_CAN_WORD0_DATA_BYTE_2)
bogdanm	82:6473597d706e	3646
bogdanm	82:6473597d706e	3647	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3648	//! @brief Set the DATA_BYTE_2 field to a new value.
bogdanm	82:6473597d706e	3649	#define BW_CAN_WORD0_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_2) \| BF_CAN_WORD0_DATA_BYTE_2(v)))
bogdanm	82:6473597d706e	3650	#endif
bogdanm	82:6473597d706e	3651	//@}
bogdanm	82:6473597d706e	3652
bogdanm	82:6473597d706e	3653	/*!
bogdanm	82:6473597d706e	3654	* @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
bogdanm	82:6473597d706e	3655	*/
bogdanm	82:6473597d706e	3656	//@{
bogdanm	82:6473597d706e	3657	#define BP_CAN_WORD0_DATA_BYTE_1 (16U) //!< Bit position for CAN_WORD0_DATA_BYTE_1.
bogdanm	82:6473597d706e	3658	#define BM_CAN_WORD0_DATA_BYTE_1 (0x00FF0000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_1.
bogdanm	82:6473597d706e	3659	#define BS_CAN_WORD0_DATA_BYTE_1 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_1.
bogdanm	82:6473597d706e	3660
bogdanm	82:6473597d706e	3661	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3662	//! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field.
bogdanm	82:6473597d706e	3663	#define BR_CAN_WORD0_DATA_BYTE_1(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_1)
bogdanm	82:6473597d706e	3664	#endif
bogdanm	82:6473597d706e	3665
bogdanm	82:6473597d706e	3666	//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_1.
bogdanm	82:6473597d706e	3667	#define BF_CAN_WORD0_DATA_BYTE_1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_1), uint32_t) & BM_CAN_WORD0_DATA_BYTE_1)
bogdanm	82:6473597d706e	3668
bogdanm	82:6473597d706e	3669	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3670	//! @brief Set the DATA_BYTE_1 field to a new value.
bogdanm	82:6473597d706e	3671	#define BW_CAN_WORD0_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_1) \| BF_CAN_WORD0_DATA_BYTE_1(v)))
bogdanm	82:6473597d706e	3672	#endif
bogdanm	82:6473597d706e	3673	//@}
bogdanm	82:6473597d706e	3674
bogdanm	82:6473597d706e	3675	/*!
bogdanm	82:6473597d706e	3676	* @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
bogdanm	82:6473597d706e	3677	*/
bogdanm	82:6473597d706e	3678	//@{
bogdanm	82:6473597d706e	3679	#define BP_CAN_WORD0_DATA_BYTE_0 (24U) //!< Bit position for CAN_WORD0_DATA_BYTE_0.
bogdanm	82:6473597d706e	3680	#define BM_CAN_WORD0_DATA_BYTE_0 (0xFF000000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_0.
bogdanm	82:6473597d706e	3681	#define BS_CAN_WORD0_DATA_BYTE_0 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_0.
bogdanm	82:6473597d706e	3682
bogdanm	82:6473597d706e	3683	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3684	//! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field.
bogdanm	82:6473597d706e	3685	#define BR_CAN_WORD0_DATA_BYTE_0(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_0)
bogdanm	82:6473597d706e	3686	#endif
bogdanm	82:6473597d706e	3687
bogdanm	82:6473597d706e	3688	//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_0.
bogdanm	82:6473597d706e	3689	#define BF_CAN_WORD0_DATA_BYTE_0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_0), uint32_t) & BM_CAN_WORD0_DATA_BYTE_0)
bogdanm	82:6473597d706e	3690
bogdanm	82:6473597d706e	3691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3692	//! @brief Set the DATA_BYTE_0 field to a new value.
bogdanm	82:6473597d706e	3693	#define BW_CAN_WORD0_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_0) \| BF_CAN_WORD0_DATA_BYTE_0(v)))
bogdanm	82:6473597d706e	3694	#endif
bogdanm	82:6473597d706e	3695	//@}
bogdanm	82:6473597d706e	3696	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3697	// HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
bogdanm	82:6473597d706e	3698	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3699
bogdanm	82:6473597d706e	3700	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3701	/*!
bogdanm	82:6473597d706e	3702	* @brief HW_CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
bogdanm	82:6473597d706e	3703	*
bogdanm	82:6473597d706e	3704	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3705	*/
bogdanm	82:6473597d706e	3706	typedef union _hw_can_word1
bogdanm	82:6473597d706e	3707	{
bogdanm	82:6473597d706e	3708	uint32_t U;
bogdanm	82:6473597d706e	3709	struct _hw_can_word1_bitfields
bogdanm	82:6473597d706e	3710	{
bogdanm	82:6473597d706e	3711	uint32_t DATA_BYTE_7 : 8; //!< [7:0] Data byte 7 of Rx/Tx frame.
bogdanm	82:6473597d706e	3712	uint32_t DATA_BYTE_6 : 8; //!< [15:8] Data byte 6 of Rx/Tx frame.
bogdanm	82:6473597d706e	3713	uint32_t DATA_BYTE_5 : 8; //!< [23:16] Data byte 5 of Rx/Tx frame.
bogdanm	82:6473597d706e	3714	uint32_t DATA_BYTE_4 : 8; //!< [31:24] Data byte 4 of Rx/Tx frame.
bogdanm	82:6473597d706e	3715	} B;
bogdanm	82:6473597d706e	3716	} hw_can_word1_t;
bogdanm	82:6473597d706e	3717	#endif
bogdanm	82:6473597d706e	3718
bogdanm	82:6473597d706e	3719	/*!
bogdanm	82:6473597d706e	3720	* @name Constants and macros for entire CAN_WORD1 register
bogdanm	82:6473597d706e	3721	*/
bogdanm	82:6473597d706e	3722	//@{
bogdanm	82:6473597d706e	3723	#define HW_CAN_WORD1_COUNT (16U)
bogdanm	82:6473597d706e	3724
bogdanm	82:6473597d706e	3725	#define HW_CAN_WORD1_ADDR(x, n) (REGS_CAN_BASE(x) + 0x8CU + (0x10U * n))
bogdanm	82:6473597d706e	3726
bogdanm	82:6473597d706e	3727	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3728	#define HW_CAN_WORD1(x, n) ((__IO hw_can_word1_t ) HW_CAN_WORD1_ADDR(x, n))
bogdanm	82:6473597d706e	3729	#define HW_CAN_WORD1_RD(x, n) (HW_CAN_WORD1(x, n).U)
bogdanm	82:6473597d706e	3730	#define HW_CAN_WORD1_WR(x, n, v) (HW_CAN_WORD1(x, n).U = (v))
bogdanm	82:6473597d706e	3731	#define HW_CAN_WORD1_SET(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3732	#define HW_CAN_WORD1_CLR(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3733	#define HW_CAN_WORD1_TOG(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3734	#endif
bogdanm	82:6473597d706e	3735	//@}
bogdanm	82:6473597d706e	3736
bogdanm	82:6473597d706e	3737	/*
bogdanm	82:6473597d706e	3738	* Constants & macros for individual CAN_WORD1 bitfields
bogdanm	82:6473597d706e	3739	*/
bogdanm	82:6473597d706e	3740
bogdanm	82:6473597d706e	3741	/*!
bogdanm	82:6473597d706e	3742	* @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
bogdanm	82:6473597d706e	3743	*/
bogdanm	82:6473597d706e	3744	//@{
bogdanm	82:6473597d706e	3745	#define BP_CAN_WORD1_DATA_BYTE_7 (0U) //!< Bit position for CAN_WORD1_DATA_BYTE_7.
bogdanm	82:6473597d706e	3746	#define BM_CAN_WORD1_DATA_BYTE_7 (0x000000FFU) //!< Bit mask for CAN_WORD1_DATA_BYTE_7.
bogdanm	82:6473597d706e	3747	#define BS_CAN_WORD1_DATA_BYTE_7 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_7.
bogdanm	82:6473597d706e	3748
bogdanm	82:6473597d706e	3749	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3750	//! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field.
bogdanm	82:6473597d706e	3751	#define BR_CAN_WORD1_DATA_BYTE_7(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_7)
bogdanm	82:6473597d706e	3752	#endif
bogdanm	82:6473597d706e	3753
bogdanm	82:6473597d706e	3754	//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_7.
bogdanm	82:6473597d706e	3755	#define BF_CAN_WORD1_DATA_BYTE_7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_7), uint32_t) & BM_CAN_WORD1_DATA_BYTE_7)
bogdanm	82:6473597d706e	3756
bogdanm	82:6473597d706e	3757	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3758	//! @brief Set the DATA_BYTE_7 field to a new value.
bogdanm	82:6473597d706e	3759	#define BW_CAN_WORD1_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_7) \| BF_CAN_WORD1_DATA_BYTE_7(v)))
bogdanm	82:6473597d706e	3760	#endif
bogdanm	82:6473597d706e	3761	//@}
bogdanm	82:6473597d706e	3762
bogdanm	82:6473597d706e	3763	/*!
bogdanm	82:6473597d706e	3764	* @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
bogdanm	82:6473597d706e	3765	*/
bogdanm	82:6473597d706e	3766	//@{
bogdanm	82:6473597d706e	3767	#define BP_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit position for CAN_WORD1_DATA_BYTE_6.
bogdanm	82:6473597d706e	3768	#define BM_CAN_WORD1_DATA_BYTE_6 (0x0000FF00U) //!< Bit mask for CAN_WORD1_DATA_BYTE_6.
bogdanm	82:6473597d706e	3769	#define BS_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_6.
bogdanm	82:6473597d706e	3770
bogdanm	82:6473597d706e	3771	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3772	//! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field.
bogdanm	82:6473597d706e	3773	#define BR_CAN_WORD1_DATA_BYTE_6(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_6)
bogdanm	82:6473597d706e	3774	#endif
bogdanm	82:6473597d706e	3775
bogdanm	82:6473597d706e	3776	//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_6.
bogdanm	82:6473597d706e	3777	#define BF_CAN_WORD1_DATA_BYTE_6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_6), uint32_t) & BM_CAN_WORD1_DATA_BYTE_6)
bogdanm	82:6473597d706e	3778
bogdanm	82:6473597d706e	3779	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3780	//! @brief Set the DATA_BYTE_6 field to a new value.
bogdanm	82:6473597d706e	3781	#define BW_CAN_WORD1_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_6) \| BF_CAN_WORD1_DATA_BYTE_6(v)))
bogdanm	82:6473597d706e	3782	#endif
bogdanm	82:6473597d706e	3783	//@}
bogdanm	82:6473597d706e	3784
bogdanm	82:6473597d706e	3785	/*!
bogdanm	82:6473597d706e	3786	* @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
bogdanm	82:6473597d706e	3787	*/
bogdanm	82:6473597d706e	3788	//@{
bogdanm	82:6473597d706e	3789	#define BP_CAN_WORD1_DATA_BYTE_5 (16U) //!< Bit position for CAN_WORD1_DATA_BYTE_5.
bogdanm	82:6473597d706e	3790	#define BM_CAN_WORD1_DATA_BYTE_5 (0x00FF0000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_5.
bogdanm	82:6473597d706e	3791	#define BS_CAN_WORD1_DATA_BYTE_5 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_5.
bogdanm	82:6473597d706e	3792
bogdanm	82:6473597d706e	3793	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3794	//! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field.
bogdanm	82:6473597d706e	3795	#define BR_CAN_WORD1_DATA_BYTE_5(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_5)
bogdanm	82:6473597d706e	3796	#endif
bogdanm	82:6473597d706e	3797
bogdanm	82:6473597d706e	3798	//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_5.
bogdanm	82:6473597d706e	3799	#define BF_CAN_WORD1_DATA_BYTE_5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_5), uint32_t) & BM_CAN_WORD1_DATA_BYTE_5)
bogdanm	82:6473597d706e	3800
bogdanm	82:6473597d706e	3801	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3802	//! @brief Set the DATA_BYTE_5 field to a new value.
bogdanm	82:6473597d706e	3803	#define BW_CAN_WORD1_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_5) \| BF_CAN_WORD1_DATA_BYTE_5(v)))
bogdanm	82:6473597d706e	3804	#endif
bogdanm	82:6473597d706e	3805	//@}
bogdanm	82:6473597d706e	3806
bogdanm	82:6473597d706e	3807	/*!
bogdanm	82:6473597d706e	3808	* @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
bogdanm	82:6473597d706e	3809	*/
bogdanm	82:6473597d706e	3810	//@{
bogdanm	82:6473597d706e	3811	#define BP_CAN_WORD1_DATA_BYTE_4 (24U) //!< Bit position for CAN_WORD1_DATA_BYTE_4.
bogdanm	82:6473597d706e	3812	#define BM_CAN_WORD1_DATA_BYTE_4 (0xFF000000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_4.
bogdanm	82:6473597d706e	3813	#define BS_CAN_WORD1_DATA_BYTE_4 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_4.
bogdanm	82:6473597d706e	3814
bogdanm	82:6473597d706e	3815	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3816	//! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field.
bogdanm	82:6473597d706e	3817	#define BR_CAN_WORD1_DATA_BYTE_4(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_4)
bogdanm	82:6473597d706e	3818	#endif
bogdanm	82:6473597d706e	3819
bogdanm	82:6473597d706e	3820	//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_4.
bogdanm	82:6473597d706e	3821	#define BF_CAN_WORD1_DATA_BYTE_4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_4), uint32_t) & BM_CAN_WORD1_DATA_BYTE_4)
bogdanm	82:6473597d706e	3822
bogdanm	82:6473597d706e	3823	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3824	//! @brief Set the DATA_BYTE_4 field to a new value.
bogdanm	82:6473597d706e	3825	#define BW_CAN_WORD1_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_4) \| BF_CAN_WORD1_DATA_BYTE_4(v)))
bogdanm	82:6473597d706e	3826	#endif
bogdanm	82:6473597d706e	3827	//@}
bogdanm	82:6473597d706e	3828
bogdanm	82:6473597d706e	3829	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3830	// HW_CAN_RXIMRn - Rx Individual Mask Registers
bogdanm	82:6473597d706e	3831	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3832
bogdanm	82:6473597d706e	3833	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3834	/*!
bogdanm	82:6473597d706e	3835	* @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
bogdanm	82:6473597d706e	3836	*
bogdanm	82:6473597d706e	3837	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3838	*
bogdanm	82:6473597d706e	3839	* These registers are located in RAM. RXIMR are used as acceptance masks for ID
bogdanm	82:6473597d706e	3840	* filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
bogdanm	82:6473597d706e	3841	* register is provided for each available Mailbox, providing ID masking
bogdanm	82:6473597d706e	3842	* capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
bogdanm	82:6473597d706e	3843	* asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
bogdanm	82:6473597d706e	3844	* Table elements on a one-to-one correspondence depending on the setting of
bogdanm	82:6473597d706e	3845	* CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
bogdanm	82:6473597d706e	3846	* mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
bogdanm	82:6473597d706e	3847	* are not affected by reset and must be explicitly initialized prior to any
bogdanm	82:6473597d706e	3848	* reception.
bogdanm	82:6473597d706e	3849	*/
bogdanm	82:6473597d706e	3850	typedef union _hw_can_rximrn
bogdanm	82:6473597d706e	3851	{
bogdanm	82:6473597d706e	3852	uint32_t U;
bogdanm	82:6473597d706e	3853	struct _hw_can_rximrn_bitfields
bogdanm	82:6473597d706e	3854	{
bogdanm	82:6473597d706e	3855	uint32_t MI : 32; //!< [31:0] Individual Mask Bits
bogdanm	82:6473597d706e	3856	} B;
bogdanm	82:6473597d706e	3857	} hw_can_rximrn_t;
bogdanm	82:6473597d706e	3858	#endif
bogdanm	82:6473597d706e	3859
bogdanm	82:6473597d706e	3860	/*!
bogdanm	82:6473597d706e	3861	* @name Constants and macros for entire CAN_RXIMRn register
bogdanm	82:6473597d706e	3862	*/
bogdanm	82:6473597d706e	3863	//@{
bogdanm	82:6473597d706e	3864	#define HW_CAN_RXIMRn_COUNT (16U)
bogdanm	82:6473597d706e	3865
bogdanm	82:6473597d706e	3866	#define HW_CAN_RXIMRn_ADDR(x, n) (REGS_CAN_BASE(x) + 0x880U + (0x4U * n))
bogdanm	82:6473597d706e	3867
bogdanm	82:6473597d706e	3868	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3869	#define HW_CAN_RXIMRn(x, n) ((__IO hw_can_rximrn_t ) HW_CAN_RXIMRn_ADDR(x, n))
bogdanm	82:6473597d706e	3870	#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
bogdanm	82:6473597d706e	3871	#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
bogdanm	82:6473597d706e	3872	#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3873	#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3874	#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3875	#endif
bogdanm	82:6473597d706e	3876	//@}
bogdanm	82:6473597d706e	3877
bogdanm	82:6473597d706e	3878	/*
bogdanm	82:6473597d706e	3879	* Constants & macros for individual CAN_RXIMRn bitfields
bogdanm	82:6473597d706e	3880	*/
bogdanm	82:6473597d706e	3881
bogdanm	82:6473597d706e	3882	/*!
bogdanm	82:6473597d706e	3883	* @name Register CAN_RXIMRn, field MI[31:0] (RW)
bogdanm	82:6473597d706e	3884	*
bogdanm	82:6473597d706e	3885	* Each Individual Mask Bit masks the corresponding bit in both the Mailbox
bogdanm	82:6473597d706e	3886	* filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
bogdanm	82:6473597d706e	3887	* see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
bogdanm	82:6473597d706e	3888	* see the RXFGMASK register description.
bogdanm	82:6473597d706e	3889	*
bogdanm	82:6473597d706e	3890	* Values:
bogdanm	82:6473597d706e	3891	* - 0 - The corresponding bit in the filter is "don't care."
bogdanm	82:6473597d706e	3892	* - 1 - The corresponding bit in the filter is checked.
bogdanm	82:6473597d706e	3893	*/
bogdanm	82:6473597d706e	3894	//@{
bogdanm	82:6473597d706e	3895	#define BP_CAN_RXIMRn_MI (0U) //!< Bit position for CAN_RXIMRn_MI.
bogdanm	82:6473597d706e	3896	#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) //!< Bit mask for CAN_RXIMRn_MI.
bogdanm	82:6473597d706e	3897	#define BS_CAN_RXIMRn_MI (32U) //!< Bit field size in bits for CAN_RXIMRn_MI.
bogdanm	82:6473597d706e	3898
bogdanm	82:6473597d706e	3899	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3900	//! @brief Read current value of the CAN_RXIMRn_MI field.
bogdanm	82:6473597d706e	3901	#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
bogdanm	82:6473597d706e	3902	#endif
bogdanm	82:6473597d706e	3903
bogdanm	82:6473597d706e	3904	//! @brief Format value for bitfield CAN_RXIMRn_MI.
bogdanm	82:6473597d706e	3905	#define BF_CAN_RXIMRn_MI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXIMRn_MI), uint32_t) & BM_CAN_RXIMRn_MI)
bogdanm	82:6473597d706e	3906
bogdanm	82:6473597d706e	3907	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3908	//! @brief Set the MI field to a new value.
bogdanm	82:6473597d706e	3909	#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
bogdanm	82:6473597d706e	3910	#endif
bogdanm	82:6473597d706e	3911	//@}
bogdanm	82:6473597d706e	3912
bogdanm	82:6473597d706e	3913	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3914	// hw_can_t - module struct
bogdanm	82:6473597d706e	3915	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3916	/*!
bogdanm	82:6473597d706e	3917	* @brief All CAN module registers.
bogdanm	82:6473597d706e	3918	*/
bogdanm	82:6473597d706e	3919	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3920	#pragma pack(1)
bogdanm	82:6473597d706e	3921	typedef struct _hw_can
bogdanm	82:6473597d706e	3922	{
bogdanm	82:6473597d706e	3923	__IO hw_can_mcr_t MCR; //!< [0x0] Module Configuration Register
bogdanm	82:6473597d706e	3924	__IO hw_can_ctrl1_t CTRL1; //!< [0x4] Control 1 register
bogdanm	82:6473597d706e	3925	__IO hw_can_timer_t TIMER; //!< [0x8] Free Running Timer
bogdanm	82:6473597d706e	3926	uint8_t _reserved0[4];
bogdanm	82:6473597d706e	3927	__IO hw_can_rxmgmask_t RXMGMASK; //!< [0x10] Rx Mailboxes Global Mask Register
bogdanm	82:6473597d706e	3928	__IO hw_can_rx14mask_t RX14MASK; //!< [0x14] Rx 14 Mask register
bogdanm	82:6473597d706e	3929	__IO hw_can_rx15mask_t RX15MASK; //!< [0x18] Rx 15 Mask register
bogdanm	82:6473597d706e	3930	__IO hw_can_ecr_t ECR; //!< [0x1C] Error Counter
bogdanm	82:6473597d706e	3931	__IO hw_can_esr1_t ESR1; //!< [0x20] Error and Status 1 register
bogdanm	82:6473597d706e	3932	uint8_t _reserved1[4];
bogdanm	82:6473597d706e	3933	__IO hw_can_imask1_t IMASK1; //!< [0x28] Interrupt Masks 1 register
bogdanm	82:6473597d706e	3934	uint8_t _reserved2[4];
bogdanm	82:6473597d706e	3935	__IO hw_can_iflag1_t IFLAG1; //!< [0x30] Interrupt Flags 1 register
bogdanm	82:6473597d706e	3936	__IO hw_can_ctrl2_t CTRL2; //!< [0x34] Control 2 register
bogdanm	82:6473597d706e	3937	__I hw_can_esr2_t ESR2; //!< [0x38] Error and Status 2 register
bogdanm	82:6473597d706e	3938	uint8_t _reserved3[8];
bogdanm	82:6473597d706e	3939	__I hw_can_crcr_t CRCR; //!< [0x44] CRC Register
bogdanm	82:6473597d706e	3940	__IO hw_can_rxfgmask_t RXFGMASK; //!< [0x48] Rx FIFO Global Mask register
bogdanm	82:6473597d706e	3941	__I hw_can_rxfir_t RXFIR; //!< [0x4C] Rx FIFO Information Register
bogdanm	82:6473597d706e	3942	uint8_t _reserved4[48];
bogdanm	82:6473597d706e	3943	struct {
bogdanm	82:6473597d706e	3944	__IO hw_can_cs_t CS; //!< [0x80] Message Buffer 0 CS Register
bogdanm	82:6473597d706e	3945	__IO hw_can_id_t ID; //!< [0x84] Message Buffer 0 ID Register
bogdanm	82:6473597d706e	3946	__IO hw_can_word0_t WORD0; //!< [0x88] Message Buffer 0 WORD0 Register
bogdanm	82:6473597d706e	3947	__IO hw_can_word1_t WORD1; //!< [0x8C] Message Buffer 0 WORD1 Register
bogdanm	82:6473597d706e	3948	} MB[16];
bogdanm	82:6473597d706e	3949	uint8_t _reserved5[1792];
bogdanm	82:6473597d706e	3950	__IO hw_can_rximrn_t RXIMRn[16]; //!< [0x880] Rx Individual Mask Registers
bogdanm	82:6473597d706e	3951	} hw_can_t;
bogdanm	82:6473597d706e	3952	#pragma pack()
bogdanm	82:6473597d706e	3953
bogdanm	82:6473597d706e	3954	//! @brief Macro to access all CAN registers.
bogdanm	82:6473597d706e	3955	//! @param x CAN instance number.
bogdanm	82:6473597d706e	3956	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	3957	//! use the '&' operator, like <code>&HW_CAN(0)</code>.
bogdanm	82:6473597d706e	3958	#define HW_CAN(x) ((hw_can_t ) REGS_CAN_BASE(x))
bogdanm	82:6473597d706e	3959	#endif
bogdanm	82:6473597d706e	3960
bogdanm	82:6473597d706e	3961	#endif // __HW_CAN_REGISTERS_H__
bogdanm	82:6473597d706e	3962	// v22/130726/0.9
bogdanm	82:6473597d706e	3963	// EOF

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_can.h@82:6473597d706e, 2014-04-07 (annotated)

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