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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_adc.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_ADC_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_ADC_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 ADC
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Analog-to-Digital Converter
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_ADC_SC1n - ADC Status and Control Registers 1
bogdanm	82:6473597d706e	33	* - HW_ADC_CFG1 - ADC Configuration Register 1
bogdanm	82:6473597d706e	34	* - HW_ADC_CFG2 - ADC Configuration Register 2
bogdanm	82:6473597d706e	35	* - HW_ADC_Rn - ADC Data Result Register
bogdanm	82:6473597d706e	36	* - HW_ADC_CV1 - Compare Value Registers
bogdanm	82:6473597d706e	37	* - HW_ADC_CV2 - Compare Value Registers
bogdanm	82:6473597d706e	38	* - HW_ADC_SC2 - Status and Control Register 2
bogdanm	82:6473597d706e	39	* - HW_ADC_SC3 - Status and Control Register 3
bogdanm	82:6473597d706e	40	* - HW_ADC_OFS - ADC Offset Correction Register
bogdanm	82:6473597d706e	41	* - HW_ADC_PG - ADC Plus-Side Gain Register
bogdanm	82:6473597d706e	42	* - HW_ADC_MG - ADC Minus-Side Gain Register
bogdanm	82:6473597d706e	43	* - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	44	* - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	45	* - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	46	* - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	47	* - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	48	* - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	49	* - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	50	* - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	51	* - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	52	* - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	53	* - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	54	* - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	55	* - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	56	* - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	57	*
bogdanm	82:6473597d706e	58	* - hw_adc_t - Struct containing all module registers.
bogdanm	82:6473597d706e	59	*/
bogdanm	82:6473597d706e	60
bogdanm	82:6473597d706e	61	//! @name Module base addresses
bogdanm	82:6473597d706e	62	//@{
bogdanm	82:6473597d706e	63	#ifndef REGS_ADC_BASE
bogdanm	82:6473597d706e	64	#define HW_ADC_INSTANCE_COUNT (2U) //!< Number of instances of the ADC module.
bogdanm	82:6473597d706e	65	#define HW_ADC0 (0U) //!< Instance number for ADC0.
bogdanm	82:6473597d706e	66	#define HW_ADC1 (1U) //!< Instance number for ADC1.
bogdanm	82:6473597d706e	67	#define REGS_ADC0_BASE (0x4003B000U) //!< Base address for ADC0.
bogdanm	82:6473597d706e	68	#define REGS_ADC1_BASE (0x400BB000U) //!< Base address for ADC1.
bogdanm	82:6473597d706e	69
bogdanm	82:6473597d706e	70	//! @brief Table of base addresses for ADC instances.
bogdanm	82:6473597d706e	71	static const uint32_t __g_regs_ADC_base_addresses[] = {
bogdanm	82:6473597d706e	72	REGS_ADC0_BASE,
bogdanm	82:6473597d706e	73	REGS_ADC1_BASE,
bogdanm	82:6473597d706e	74	};
bogdanm	82:6473597d706e	75
bogdanm	82:6473597d706e	76	//! @brief Get the base address of ADC by instance number.
bogdanm	82:6473597d706e	77	//! @param x ADC instance number, from 0 through 1.
bogdanm	82:6473597d706e	78	#define REGS_ADC_BASE(x) (__g_regs_ADC_base_addresses[(x)])
bogdanm	82:6473597d706e	79
bogdanm	82:6473597d706e	80	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	81	//! @param b Base address for an instance of ADC.
bogdanm	82:6473597d706e	82	#define REGS_ADC_INSTANCE(b) ((b) == REGS_ADC0_BASE ? HW_ADC0 : (b) == REGS_ADC1_BASE ? HW_ADC1 : 0)
bogdanm	82:6473597d706e	83	#endif
bogdanm	82:6473597d706e	84	//@}
bogdanm	82:6473597d706e	85
bogdanm	82:6473597d706e	86	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	87	// HW_ADC_SC1n - ADC Status and Control Registers 1
bogdanm	82:6473597d706e	88	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	89
bogdanm	82:6473597d706e	90	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	91	/*!
bogdanm	82:6473597d706e	92	* @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
bogdanm	82:6473597d706e	93	*
bogdanm	82:6473597d706e	94	* Reset value: 0x0000001FU
bogdanm	82:6473597d706e	95	*
bogdanm	82:6473597d706e	96	* SC1A is used for both software and hardware trigger modes of operation. To
bogdanm	82:6473597d706e	97	* allow sequential conversions of the ADC to be triggered by internal peripherals,
bogdanm	82:6473597d706e	98	* the ADC can have more than one status and control register: one for each
bogdanm	82:6473597d706e	99	* conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
bogdanm	82:6473597d706e	100	* for use only in hardware trigger mode. See the chip configuration information
bogdanm	82:6473597d706e	101	* about the number of SC1n registers specific to this device. The SC1n registers
bogdanm	82:6473597d706e	102	* have identical fields, and are used in a "ping-pong" approach to control ADC
bogdanm	82:6473597d706e	103	* operation. At any one point in time, only one of the SC1n registers is actively
bogdanm	82:6473597d706e	104	* controlling ADC conversions. Updating SC1A while SC1n is actively controlling
bogdanm	82:6473597d706e	105	* a conversion is allowed, and vice-versa for any of the SC1n registers specific
bogdanm	82:6473597d706e	106	* to this MCU. Writing SC1A while SC1A is actively controlling a conversion
bogdanm	82:6473597d706e	107	* aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
bogdanm	82:6473597d706e	108	* writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
bogdanm	82:6473597d706e	109	* value other than all 1s. Writing any of the SC1n registers while that specific
bogdanm	82:6473597d706e	110	* SC1n register is actively controlling a conversion aborts the current conversion.
bogdanm	82:6473597d706e	111	* None of the SC1B-SC1n registers are used for software trigger operation and
bogdanm	82:6473597d706e	112	* therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
bogdanm	82:6473597d706e	113	*/
bogdanm	82:6473597d706e	114	typedef union _hw_adc_sc1n
bogdanm	82:6473597d706e	115	{
bogdanm	82:6473597d706e	116	uint32_t U;
bogdanm	82:6473597d706e	117	struct _hw_adc_sc1n_bitfields
bogdanm	82:6473597d706e	118	{
bogdanm	82:6473597d706e	119	uint32_t ADCH : 5; //!< [4:0] Input channel select
bogdanm	82:6473597d706e	120	uint32_t DIFF : 1; //!< [5] Differential Mode Enable
bogdanm	82:6473597d706e	121	uint32_t AIEN : 1; //!< [6] Interrupt Enable
bogdanm	82:6473597d706e	122	uint32_t COCO : 1; //!< [7] Conversion Complete Flag
bogdanm	82:6473597d706e	123	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	124	} B;
bogdanm	82:6473597d706e	125	} hw_adc_sc1n_t;
bogdanm	82:6473597d706e	126	#endif
bogdanm	82:6473597d706e	127
bogdanm	82:6473597d706e	128	/*!
bogdanm	82:6473597d706e	129	* @name Constants and macros for entire ADC_SC1n register
bogdanm	82:6473597d706e	130	*/
bogdanm	82:6473597d706e	131	//@{
bogdanm	82:6473597d706e	132	#define HW_ADC_SC1n_COUNT (2U)
bogdanm	82:6473597d706e	133
bogdanm	82:6473597d706e	134	#define HW_ADC_SC1n_ADDR(x, n) (REGS_ADC_BASE(x) + 0x0U + (0x4U * n))
bogdanm	82:6473597d706e	135
bogdanm	82:6473597d706e	136	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	137	#define HW_ADC_SC1n(x, n) ((__IO hw_adc_sc1n_t ) HW_ADC_SC1n_ADDR(x, n))
bogdanm	82:6473597d706e	138	#define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
bogdanm	82:6473597d706e	139	#define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
bogdanm	82:6473597d706e	140	#define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	141	#define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	142	#define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	143	#endif
bogdanm	82:6473597d706e	144	//@}
bogdanm	82:6473597d706e	145
bogdanm	82:6473597d706e	146	/*
bogdanm	82:6473597d706e	147	* Constants & macros for individual ADC_SC1n bitfields
bogdanm	82:6473597d706e	148	*/
bogdanm	82:6473597d706e	149
bogdanm	82:6473597d706e	150	/*!
bogdanm	82:6473597d706e	151	* @name Register ADC_SC1n, field ADCH[4:0] (RW)
bogdanm	82:6473597d706e	152	*
bogdanm	82:6473597d706e	153	* Selects one of the input channels. The input channel decode depends on the
bogdanm	82:6473597d706e	154	* value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
bogdanm	82:6473597d706e	155	* DADMx. Some of the input channel options in the bitfield-setting descriptions might
bogdanm	82:6473597d706e	156	* not be available for your device. For the actual ADC channel assignments for
bogdanm	82:6473597d706e	157	* your device, see the Chip Configuration details. The successive approximation
bogdanm	82:6473597d706e	158	* converter subsystem is turned off when the channel select bits are all set,
bogdanm	82:6473597d706e	159	* that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
bogdanm	82:6473597d706e	160	* isolation of the input channel from all sources. Terminating continuous
bogdanm	82:6473597d706e	161	* conversions this way prevents an additional single conversion from being performed. It
bogdanm	82:6473597d706e	162	* is not necessary to set ADCH to all 1s to place the ADC in a low-power state
bogdanm	82:6473597d706e	163	* when continuous conversions are not enabled because the module automatically
bogdanm	82:6473597d706e	164	* enters a low-power state when a conversion completes.
bogdanm	82:6473597d706e	165	*
bogdanm	82:6473597d706e	166	* Values:
bogdanm	82:6473597d706e	167	* - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
bogdanm	82:6473597d706e	168	* selected as input.
bogdanm	82:6473597d706e	169	* - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
bogdanm	82:6473597d706e	170	* selected as input.
bogdanm	82:6473597d706e	171	* - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
bogdanm	82:6473597d706e	172	* selected as input.
bogdanm	82:6473597d706e	173	* - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
bogdanm	82:6473597d706e	174	* selected as input.
bogdanm	82:6473597d706e	175	* - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	176	* - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	177	* - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	178	* - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	179	* - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	180	* - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	181	* - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	182	* - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	183	* - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	184	* - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	185	* - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	186	* - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	187	* - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	188	* - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	189	* - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	190	* - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	191	* - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	192	* - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	193	* - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	194	* - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
bogdanm	82:6473597d706e	195	* - 11000 - Reserved.
bogdanm	82:6473597d706e	196	* - 11001 - Reserved.
bogdanm	82:6473597d706e	197	* - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
bogdanm	82:6473597d706e	198	* DIFF=1, Temp Sensor (differential) is selected as input.
bogdanm	82:6473597d706e	199	* - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
bogdanm	82:6473597d706e	200	* DIFF=1, Bandgap (differential) is selected as input.
bogdanm	82:6473597d706e	201	* - 11100 - Reserved.
bogdanm	82:6473597d706e	202	* - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
bogdanm	82:6473597d706e	203	* (differential) is selected as input. Voltage reference selected is determined
bogdanm	82:6473597d706e	204	* by SC2[REFSEL].
bogdanm	82:6473597d706e	205	* - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
bogdanm	82:6473597d706e	206	* reserved. Voltage reference selected is determined by SC2[REFSEL].
bogdanm	82:6473597d706e	207	* - 11111 - Module is disabled.
bogdanm	82:6473597d706e	208	*/
bogdanm	82:6473597d706e	209	//@{
bogdanm	82:6473597d706e	210	#define BP_ADC_SC1n_ADCH (0U) //!< Bit position for ADC_SC1n_ADCH.
bogdanm	82:6473597d706e	211	#define BM_ADC_SC1n_ADCH (0x0000001FU) //!< Bit mask for ADC_SC1n_ADCH.
bogdanm	82:6473597d706e	212	#define BS_ADC_SC1n_ADCH (5U) //!< Bit field size in bits for ADC_SC1n_ADCH.
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	215	//! @brief Read current value of the ADC_SC1n_ADCH field.
bogdanm	82:6473597d706e	216	#define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
bogdanm	82:6473597d706e	217	#endif
bogdanm	82:6473597d706e	218
bogdanm	82:6473597d706e	219	//! @brief Format value for bitfield ADC_SC1n_ADCH.
bogdanm	82:6473597d706e	220	#define BF_ADC_SC1n_ADCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_ADCH), uint32_t) & BM_ADC_SC1n_ADCH)
bogdanm	82:6473597d706e	221
bogdanm	82:6473597d706e	222	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	223	//! @brief Set the ADCH field to a new value.
bogdanm	82:6473597d706e	224	#define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) \| BF_ADC_SC1n_ADCH(v)))
bogdanm	82:6473597d706e	225	#endif
bogdanm	82:6473597d706e	226	//@}
bogdanm	82:6473597d706e	227
bogdanm	82:6473597d706e	228	/*!
bogdanm	82:6473597d706e	229	* @name Register ADC_SC1n, field DIFF[5] (RW)
bogdanm	82:6473597d706e	230	*
bogdanm	82:6473597d706e	231	* Configures the ADC to operate in differential mode. When enabled, this mode
bogdanm	82:6473597d706e	232	* automatically selects from the differential channels, and changes the
bogdanm	82:6473597d706e	233	* conversion algorithm and the number of cycles to complete a conversion.
bogdanm	82:6473597d706e	234	*
bogdanm	82:6473597d706e	235	* Values:
bogdanm	82:6473597d706e	236	* - 0 - Single-ended conversions and input channels are selected.
bogdanm	82:6473597d706e	237	* - 1 - Differential conversions and input channels are selected.
bogdanm	82:6473597d706e	238	*/
bogdanm	82:6473597d706e	239	//@{
bogdanm	82:6473597d706e	240	#define BP_ADC_SC1n_DIFF (5U) //!< Bit position for ADC_SC1n_DIFF.
bogdanm	82:6473597d706e	241	#define BM_ADC_SC1n_DIFF (0x00000020U) //!< Bit mask for ADC_SC1n_DIFF.
bogdanm	82:6473597d706e	242	#define BS_ADC_SC1n_DIFF (1U) //!< Bit field size in bits for ADC_SC1n_DIFF.
bogdanm	82:6473597d706e	243
bogdanm	82:6473597d706e	244	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	245	//! @brief Read current value of the ADC_SC1n_DIFF field.
bogdanm	82:6473597d706e	246	#define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
bogdanm	82:6473597d706e	247	#endif
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	//! @brief Format value for bitfield ADC_SC1n_DIFF.
bogdanm	82:6473597d706e	250	#define BF_ADC_SC1n_DIFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_DIFF), uint32_t) & BM_ADC_SC1n_DIFF)
bogdanm	82:6473597d706e	251
bogdanm	82:6473597d706e	252	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	253	//! @brief Set the DIFF field to a new value.
bogdanm	82:6473597d706e	254	#define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
bogdanm	82:6473597d706e	255	#endif
bogdanm	82:6473597d706e	256	//@}
bogdanm	82:6473597d706e	257
bogdanm	82:6473597d706e	258	/*!
bogdanm	82:6473597d706e	259	* @name Register ADC_SC1n, field AIEN[6] (RW)
bogdanm	82:6473597d706e	260	*
bogdanm	82:6473597d706e	261	* Enables conversion complete interrupts. When COCO becomes set while the
bogdanm	82:6473597d706e	262	* respective AIEN is high, an interrupt is asserted.
bogdanm	82:6473597d706e	263	*
bogdanm	82:6473597d706e	264	* Values:
bogdanm	82:6473597d706e	265	* - 0 - Conversion complete interrupt is disabled.
bogdanm	82:6473597d706e	266	* - 1 - Conversion complete interrupt is enabled.
bogdanm	82:6473597d706e	267	*/
bogdanm	82:6473597d706e	268	//@{
bogdanm	82:6473597d706e	269	#define BP_ADC_SC1n_AIEN (6U) //!< Bit position for ADC_SC1n_AIEN.
bogdanm	82:6473597d706e	270	#define BM_ADC_SC1n_AIEN (0x00000040U) //!< Bit mask for ADC_SC1n_AIEN.
bogdanm	82:6473597d706e	271	#define BS_ADC_SC1n_AIEN (1U) //!< Bit field size in bits for ADC_SC1n_AIEN.
bogdanm	82:6473597d706e	272
bogdanm	82:6473597d706e	273	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	274	//! @brief Read current value of the ADC_SC1n_AIEN field.
bogdanm	82:6473597d706e	275	#define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
bogdanm	82:6473597d706e	276	#endif
bogdanm	82:6473597d706e	277
bogdanm	82:6473597d706e	278	//! @brief Format value for bitfield ADC_SC1n_AIEN.
bogdanm	82:6473597d706e	279	#define BF_ADC_SC1n_AIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_AIEN), uint32_t) & BM_ADC_SC1n_AIEN)
bogdanm	82:6473597d706e	280
bogdanm	82:6473597d706e	281	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	282	//! @brief Set the AIEN field to a new value.
bogdanm	82:6473597d706e	283	#define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
bogdanm	82:6473597d706e	284	#endif
bogdanm	82:6473597d706e	285	//@}
bogdanm	82:6473597d706e	286
bogdanm	82:6473597d706e	287	/*!
bogdanm	82:6473597d706e	288	* @name Register ADC_SC1n, field COCO[7] (RO)
bogdanm	82:6473597d706e	289	*
bogdanm	82:6473597d706e	290	* This is a read-only field that is set each time a conversion is completed
bogdanm	82:6473597d706e	291	* when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
bogdanm	82:6473597d706e	292	* function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
bogdanm	82:6473597d706e	293	* SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
bogdanm	82:6473597d706e	294	* result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
bogdanm	82:6473597d706e	295	* COCO is set upon completion of the selected number of conversions (determined
bogdanm	82:6473597d706e	296	* by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
bogdanm	82:6473597d706e	297	* COCO is cleared when the respective SC1n register is written or when the
bogdanm	82:6473597d706e	298	* respective Rn register is read.
bogdanm	82:6473597d706e	299	*
bogdanm	82:6473597d706e	300	* Values:
bogdanm	82:6473597d706e	301	* - 0 - Conversion is not completed.
bogdanm	82:6473597d706e	302	* - 1 - Conversion is completed.
bogdanm	82:6473597d706e	303	*/
bogdanm	82:6473597d706e	304	//@{
bogdanm	82:6473597d706e	305	#define BP_ADC_SC1n_COCO (7U) //!< Bit position for ADC_SC1n_COCO.
bogdanm	82:6473597d706e	306	#define BM_ADC_SC1n_COCO (0x00000080U) //!< Bit mask for ADC_SC1n_COCO.
bogdanm	82:6473597d706e	307	#define BS_ADC_SC1n_COCO (1U) //!< Bit field size in bits for ADC_SC1n_COCO.
bogdanm	82:6473597d706e	308
bogdanm	82:6473597d706e	309	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	310	//! @brief Read current value of the ADC_SC1n_COCO field.
bogdanm	82:6473597d706e	311	#define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
bogdanm	82:6473597d706e	312	#endif
bogdanm	82:6473597d706e	313	//@}
bogdanm	82:6473597d706e	314
bogdanm	82:6473597d706e	315	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	316	// HW_ADC_CFG1 - ADC Configuration Register 1
bogdanm	82:6473597d706e	317	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	318
bogdanm	82:6473597d706e	319	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	320	/*!
bogdanm	82:6473597d706e	321	* @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
bogdanm	82:6473597d706e	322	*
bogdanm	82:6473597d706e	323	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	324	*
bogdanm	82:6473597d706e	325	* The configuration Register 1 (CFG1) selects the mode of operation, clock
bogdanm	82:6473597d706e	326	* source, clock divide, and configuration for low power or long sample time.
bogdanm	82:6473597d706e	327	*/
bogdanm	82:6473597d706e	328	typedef union _hw_adc_cfg1
bogdanm	82:6473597d706e	329	{
bogdanm	82:6473597d706e	330	uint32_t U;
bogdanm	82:6473597d706e	331	struct _hw_adc_cfg1_bitfields
bogdanm	82:6473597d706e	332	{
bogdanm	82:6473597d706e	333	uint32_t ADICLK : 2; //!< [1:0] Input Clock Select
bogdanm	82:6473597d706e	334	uint32_t MODE : 2; //!< [3:2] Conversion mode selection
bogdanm	82:6473597d706e	335	uint32_t ADLSMP : 1; //!< [4] Sample Time Configuration
bogdanm	82:6473597d706e	336	uint32_t ADIV : 2; //!< [6:5] Clock Divide Select
bogdanm	82:6473597d706e	337	uint32_t ADLPC : 1; //!< [7] Low-Power Configuration
bogdanm	82:6473597d706e	338	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	339	} B;
bogdanm	82:6473597d706e	340	} hw_adc_cfg1_t;
bogdanm	82:6473597d706e	341	#endif
bogdanm	82:6473597d706e	342
bogdanm	82:6473597d706e	343	/*!
bogdanm	82:6473597d706e	344	* @name Constants and macros for entire ADC_CFG1 register
bogdanm	82:6473597d706e	345	*/
bogdanm	82:6473597d706e	346	//@{
bogdanm	82:6473597d706e	347	#define HW_ADC_CFG1_ADDR(x) (REGS_ADC_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	348
bogdanm	82:6473597d706e	349	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	350	#define HW_ADC_CFG1(x) ((__IO hw_adc_cfg1_t ) HW_ADC_CFG1_ADDR(x))
bogdanm	82:6473597d706e	351	#define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
bogdanm	82:6473597d706e	352	#define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
bogdanm	82:6473597d706e	353	#define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) \| (v)))
bogdanm	82:6473597d706e	354	#define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	355	#define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	356	#endif
bogdanm	82:6473597d706e	357	//@}
bogdanm	82:6473597d706e	358
bogdanm	82:6473597d706e	359	/*
bogdanm	82:6473597d706e	360	* Constants & macros for individual ADC_CFG1 bitfields
bogdanm	82:6473597d706e	361	*/
bogdanm	82:6473597d706e	362
bogdanm	82:6473597d706e	363	/*!
bogdanm	82:6473597d706e	364	* @name Register ADC_CFG1, field ADICLK[1:0] (RW)
bogdanm	82:6473597d706e	365	*
bogdanm	82:6473597d706e	366	* Selects the input clock source to generate the internal clock, ADCK. Note
bogdanm	82:6473597d706e	367	* that when the ADACK clock source is selected, it is not required to be active
bogdanm	82:6473597d706e	368	* prior to conversion start. When it is selected and it is not active prior to a
bogdanm	82:6473597d706e	369	* conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
bogdanm	82:6473597d706e	370	* the start of a conversion and deactivated when conversions are terminated. In
bogdanm	82:6473597d706e	371	* this case, there is an associated clock startup delay each time the clock
bogdanm	82:6473597d706e	372	* source is re-activated.
bogdanm	82:6473597d706e	373	*
bogdanm	82:6473597d706e	374	* Values:
bogdanm	82:6473597d706e	375	* - 00 - Bus clock
bogdanm	82:6473597d706e	376	* - 01 - Alternate clock 2 (ALTCLK2)
bogdanm	82:6473597d706e	377	* - 10 - Alternate clock (ALTCLK)
bogdanm	82:6473597d706e	378	* - 11 - Asynchronous clock (ADACK)
bogdanm	82:6473597d706e	379	*/
bogdanm	82:6473597d706e	380	//@{
bogdanm	82:6473597d706e	381	#define BP_ADC_CFG1_ADICLK (0U) //!< Bit position for ADC_CFG1_ADICLK.
bogdanm	82:6473597d706e	382	#define BM_ADC_CFG1_ADICLK (0x00000003U) //!< Bit mask for ADC_CFG1_ADICLK.
bogdanm	82:6473597d706e	383	#define BS_ADC_CFG1_ADICLK (2U) //!< Bit field size in bits for ADC_CFG1_ADICLK.
bogdanm	82:6473597d706e	384
bogdanm	82:6473597d706e	385	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	386	//! @brief Read current value of the ADC_CFG1_ADICLK field.
bogdanm	82:6473597d706e	387	#define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
bogdanm	82:6473597d706e	388	#endif
bogdanm	82:6473597d706e	389
bogdanm	82:6473597d706e	390	//! @brief Format value for bitfield ADC_CFG1_ADICLK.
bogdanm	82:6473597d706e	391	#define BF_ADC_CFG1_ADICLK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADICLK), uint32_t) & BM_ADC_CFG1_ADICLK)
bogdanm	82:6473597d706e	392
bogdanm	82:6473597d706e	393	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	394	//! @brief Set the ADICLK field to a new value.
bogdanm	82:6473597d706e	395	#define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) \| BF_ADC_CFG1_ADICLK(v)))
bogdanm	82:6473597d706e	396	#endif
bogdanm	82:6473597d706e	397	//@}
bogdanm	82:6473597d706e	398
bogdanm	82:6473597d706e	399	/*!
bogdanm	82:6473597d706e	400	* @name Register ADC_CFG1, field MODE[3:2] (RW)
bogdanm	82:6473597d706e	401	*
bogdanm	82:6473597d706e	402	* Selects the ADC resolution mode.
bogdanm	82:6473597d706e	403	*
bogdanm	82:6473597d706e	404	* Values:
bogdanm	82:6473597d706e	405	* - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
bogdanm	82:6473597d706e	406	* differential 9-bit conversion with 2's complement output.
bogdanm	82:6473597d706e	407	* - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
bogdanm	82:6473597d706e	408	* differential 13-bit conversion with 2's complement output.
bogdanm	82:6473597d706e	409	* - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
bogdanm	82:6473597d706e	410	* differential 11-bit conversion with 2's complement output
bogdanm	82:6473597d706e	411	* - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
bogdanm	82:6473597d706e	412	* differential 16-bit conversion with 2's complement output
bogdanm	82:6473597d706e	413	*/
bogdanm	82:6473597d706e	414	//@{
bogdanm	82:6473597d706e	415	#define BP_ADC_CFG1_MODE (2U) //!< Bit position for ADC_CFG1_MODE.
bogdanm	82:6473597d706e	416	#define BM_ADC_CFG1_MODE (0x0000000CU) //!< Bit mask for ADC_CFG1_MODE.
bogdanm	82:6473597d706e	417	#define BS_ADC_CFG1_MODE (2U) //!< Bit field size in bits for ADC_CFG1_MODE.
bogdanm	82:6473597d706e	418
bogdanm	82:6473597d706e	419	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	420	//! @brief Read current value of the ADC_CFG1_MODE field.
bogdanm	82:6473597d706e	421	#define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
bogdanm	82:6473597d706e	422	#endif
bogdanm	82:6473597d706e	423
bogdanm	82:6473597d706e	424	//! @brief Format value for bitfield ADC_CFG1_MODE.
bogdanm	82:6473597d706e	425	#define BF_ADC_CFG1_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_MODE), uint32_t) & BM_ADC_CFG1_MODE)
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	428	//! @brief Set the MODE field to a new value.
bogdanm	82:6473597d706e	429	#define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) \| BF_ADC_CFG1_MODE(v)))
bogdanm	82:6473597d706e	430	#endif
bogdanm	82:6473597d706e	431	//@}
bogdanm	82:6473597d706e	432
bogdanm	82:6473597d706e	433	/*!
bogdanm	82:6473597d706e	434	* @name Register ADC_CFG1, field ADLSMP[4] (RW)
bogdanm	82:6473597d706e	435	*
bogdanm	82:6473597d706e	436	* Selects between different sample times based on the conversion mode selected.
bogdanm	82:6473597d706e	437	* This field adjusts the sample period to allow higher impedance inputs to be
bogdanm	82:6473597d706e	438	* accurately sampled or to maximize conversion speed for lower impedance inputs.
bogdanm	82:6473597d706e	439	* Longer sample times can also be used to lower overall power consumption if
bogdanm	82:6473597d706e	440	* continuous conversions are enabled and high conversion rates are not required.
bogdanm	82:6473597d706e	441	* When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
bogdanm	82:6473597d706e	442	* extent of the long sample time.
bogdanm	82:6473597d706e	443	*
bogdanm	82:6473597d706e	444	* Values:
bogdanm	82:6473597d706e	445	* - 0 - Short sample time.
bogdanm	82:6473597d706e	446	* - 1 - Long sample time.
bogdanm	82:6473597d706e	447	*/
bogdanm	82:6473597d706e	448	//@{
bogdanm	82:6473597d706e	449	#define BP_ADC_CFG1_ADLSMP (4U) //!< Bit position for ADC_CFG1_ADLSMP.
bogdanm	82:6473597d706e	450	#define BM_ADC_CFG1_ADLSMP (0x00000010U) //!< Bit mask for ADC_CFG1_ADLSMP.
bogdanm	82:6473597d706e	451	#define BS_ADC_CFG1_ADLSMP (1U) //!< Bit field size in bits for ADC_CFG1_ADLSMP.
bogdanm	82:6473597d706e	452
bogdanm	82:6473597d706e	453	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	454	//! @brief Read current value of the ADC_CFG1_ADLSMP field.
bogdanm	82:6473597d706e	455	#define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
bogdanm	82:6473597d706e	456	#endif
bogdanm	82:6473597d706e	457
bogdanm	82:6473597d706e	458	//! @brief Format value for bitfield ADC_CFG1_ADLSMP.
bogdanm	82:6473597d706e	459	#define BF_ADC_CFG1_ADLSMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLSMP), uint32_t) & BM_ADC_CFG1_ADLSMP)
bogdanm	82:6473597d706e	460
bogdanm	82:6473597d706e	461	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	462	//! @brief Set the ADLSMP field to a new value.
bogdanm	82:6473597d706e	463	#define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
bogdanm	82:6473597d706e	464	#endif
bogdanm	82:6473597d706e	465	//@}
bogdanm	82:6473597d706e	466
bogdanm	82:6473597d706e	467	/*!
bogdanm	82:6473597d706e	468	* @name Register ADC_CFG1, field ADIV[6:5] (RW)
bogdanm	82:6473597d706e	469	*
bogdanm	82:6473597d706e	470	* Selects the divide ratio used by the ADC to generate the internal clock ADCK.
bogdanm	82:6473597d706e	471	*
bogdanm	82:6473597d706e	472	* Values:
bogdanm	82:6473597d706e	473	* - 00 - The divide ratio is 1 and the clock rate is input clock.
bogdanm	82:6473597d706e	474	* - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
bogdanm	82:6473597d706e	475	* - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
bogdanm	82:6473597d706e	476	* - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
bogdanm	82:6473597d706e	477	*/
bogdanm	82:6473597d706e	478	//@{
bogdanm	82:6473597d706e	479	#define BP_ADC_CFG1_ADIV (5U) //!< Bit position for ADC_CFG1_ADIV.
bogdanm	82:6473597d706e	480	#define BM_ADC_CFG1_ADIV (0x00000060U) //!< Bit mask for ADC_CFG1_ADIV.
bogdanm	82:6473597d706e	481	#define BS_ADC_CFG1_ADIV (2U) //!< Bit field size in bits for ADC_CFG1_ADIV.
bogdanm	82:6473597d706e	482
bogdanm	82:6473597d706e	483	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	484	//! @brief Read current value of the ADC_CFG1_ADIV field.
bogdanm	82:6473597d706e	485	#define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
bogdanm	82:6473597d706e	486	#endif
bogdanm	82:6473597d706e	487
bogdanm	82:6473597d706e	488	//! @brief Format value for bitfield ADC_CFG1_ADIV.
bogdanm	82:6473597d706e	489	#define BF_ADC_CFG1_ADIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADIV), uint32_t) & BM_ADC_CFG1_ADIV)
bogdanm	82:6473597d706e	490
bogdanm	82:6473597d706e	491	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	492	//! @brief Set the ADIV field to a new value.
bogdanm	82:6473597d706e	493	#define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) \| BF_ADC_CFG1_ADIV(v)))
bogdanm	82:6473597d706e	494	#endif
bogdanm	82:6473597d706e	495	//@}
bogdanm	82:6473597d706e	496
bogdanm	82:6473597d706e	497	/*!
bogdanm	82:6473597d706e	498	* @name Register ADC_CFG1, field ADLPC[7] (RW)
bogdanm	82:6473597d706e	499	*
bogdanm	82:6473597d706e	500	* Controls the power configuration of the successive approximation converter.
bogdanm	82:6473597d706e	501	* This optimizes power consumption when higher sample rates are not required.
bogdanm	82:6473597d706e	502	*
bogdanm	82:6473597d706e	503	* Values:
bogdanm	82:6473597d706e	504	* - 0 - Normal power configuration.
bogdanm	82:6473597d706e	505	* - 1 - Low-power configuration. The power is reduced at the expense of maximum
bogdanm	82:6473597d706e	506	* clock speed.
bogdanm	82:6473597d706e	507	*/
bogdanm	82:6473597d706e	508	//@{
bogdanm	82:6473597d706e	509	#define BP_ADC_CFG1_ADLPC (7U) //!< Bit position for ADC_CFG1_ADLPC.
bogdanm	82:6473597d706e	510	#define BM_ADC_CFG1_ADLPC (0x00000080U) //!< Bit mask for ADC_CFG1_ADLPC.
bogdanm	82:6473597d706e	511	#define BS_ADC_CFG1_ADLPC (1U) //!< Bit field size in bits for ADC_CFG1_ADLPC.
bogdanm	82:6473597d706e	512
bogdanm	82:6473597d706e	513	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	514	//! @brief Read current value of the ADC_CFG1_ADLPC field.
bogdanm	82:6473597d706e	515	#define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
bogdanm	82:6473597d706e	516	#endif
bogdanm	82:6473597d706e	517
bogdanm	82:6473597d706e	518	//! @brief Format value for bitfield ADC_CFG1_ADLPC.
bogdanm	82:6473597d706e	519	#define BF_ADC_CFG1_ADLPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLPC), uint32_t) & BM_ADC_CFG1_ADLPC)
bogdanm	82:6473597d706e	520
bogdanm	82:6473597d706e	521	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	522	//! @brief Set the ADLPC field to a new value.
bogdanm	82:6473597d706e	523	#define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
bogdanm	82:6473597d706e	524	#endif
bogdanm	82:6473597d706e	525	//@}
bogdanm	82:6473597d706e	526
bogdanm	82:6473597d706e	527	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	528	// HW_ADC_CFG2 - ADC Configuration Register 2
bogdanm	82:6473597d706e	529	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	530
bogdanm	82:6473597d706e	531	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	532	/*!
bogdanm	82:6473597d706e	533	* @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
bogdanm	82:6473597d706e	534	*
bogdanm	82:6473597d706e	535	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	536	*
bogdanm	82:6473597d706e	537	* Configuration Register 2 (CFG2) selects the special high-speed configuration
bogdanm	82:6473597d706e	538	* for very high speed conversions and selects the long sample time duration
bogdanm	82:6473597d706e	539	* during long sample mode.
bogdanm	82:6473597d706e	540	*/
bogdanm	82:6473597d706e	541	typedef union _hw_adc_cfg2
bogdanm	82:6473597d706e	542	{
bogdanm	82:6473597d706e	543	uint32_t U;
bogdanm	82:6473597d706e	544	struct _hw_adc_cfg2_bitfields
bogdanm	82:6473597d706e	545	{
bogdanm	82:6473597d706e	546	uint32_t ADLSTS : 2; //!< [1:0] Long Sample Time Select
bogdanm	82:6473597d706e	547	uint32_t ADHSC : 1; //!< [2] High-Speed Configuration
bogdanm	82:6473597d706e	548	uint32_t ADACKEN : 1; //!< [3] Asynchronous Clock Output Enable
bogdanm	82:6473597d706e	549	uint32_t MUXSEL : 1; //!< [4] ADC Mux Select
bogdanm	82:6473597d706e	550	uint32_t RESERVED0 : 27; //!< [31:5]
bogdanm	82:6473597d706e	551	} B;
bogdanm	82:6473597d706e	552	} hw_adc_cfg2_t;
bogdanm	82:6473597d706e	553	#endif
bogdanm	82:6473597d706e	554
bogdanm	82:6473597d706e	555	/*!
bogdanm	82:6473597d706e	556	* @name Constants and macros for entire ADC_CFG2 register
bogdanm	82:6473597d706e	557	*/
bogdanm	82:6473597d706e	558	//@{
bogdanm	82:6473597d706e	559	#define HW_ADC_CFG2_ADDR(x) (REGS_ADC_BASE(x) + 0xCU)
bogdanm	82:6473597d706e	560
bogdanm	82:6473597d706e	561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	562	#define HW_ADC_CFG2(x) ((__IO hw_adc_cfg2_t ) HW_ADC_CFG2_ADDR(x))
bogdanm	82:6473597d706e	563	#define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
bogdanm	82:6473597d706e	564	#define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
bogdanm	82:6473597d706e	565	#define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) \| (v)))
bogdanm	82:6473597d706e	566	#define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	567	#define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	568	#endif
bogdanm	82:6473597d706e	569	//@}
bogdanm	82:6473597d706e	570
bogdanm	82:6473597d706e	571	/*
bogdanm	82:6473597d706e	572	* Constants & macros for individual ADC_CFG2 bitfields
bogdanm	82:6473597d706e	573	*/
bogdanm	82:6473597d706e	574
bogdanm	82:6473597d706e	575	/*!
bogdanm	82:6473597d706e	576	* @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
bogdanm	82:6473597d706e	577	*
bogdanm	82:6473597d706e	578	* Selects between the extended sample times when long sample time is selected,
bogdanm	82:6473597d706e	579	* that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
bogdanm	82:6473597d706e	580	* accurately sampled or to maximize conversion speed for lower impedance inputs.
bogdanm	82:6473597d706e	581	* Longer sample times can also be used to lower overall power consumption when
bogdanm	82:6473597d706e	582	* continuous conversions are enabled if high conversion rates are not required.
bogdanm	82:6473597d706e	583	*
bogdanm	82:6473597d706e	584	* Values:
bogdanm	82:6473597d706e	585	* - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
bogdanm	82:6473597d706e	586	* total.
bogdanm	82:6473597d706e	587	* - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
bogdanm	82:6473597d706e	588	* - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
bogdanm	82:6473597d706e	589	* - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
bogdanm	82:6473597d706e	590	*/
bogdanm	82:6473597d706e	591	//@{
bogdanm	82:6473597d706e	592	#define BP_ADC_CFG2_ADLSTS (0U) //!< Bit position for ADC_CFG2_ADLSTS.
bogdanm	82:6473597d706e	593	#define BM_ADC_CFG2_ADLSTS (0x00000003U) //!< Bit mask for ADC_CFG2_ADLSTS.
bogdanm	82:6473597d706e	594	#define BS_ADC_CFG2_ADLSTS (2U) //!< Bit field size in bits for ADC_CFG2_ADLSTS.
bogdanm	82:6473597d706e	595
bogdanm	82:6473597d706e	596	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	597	//! @brief Read current value of the ADC_CFG2_ADLSTS field.
bogdanm	82:6473597d706e	598	#define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
bogdanm	82:6473597d706e	599	#endif
bogdanm	82:6473597d706e	600
bogdanm	82:6473597d706e	601	//! @brief Format value for bitfield ADC_CFG2_ADLSTS.
bogdanm	82:6473597d706e	602	#define BF_ADC_CFG2_ADLSTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADLSTS), uint32_t) & BM_ADC_CFG2_ADLSTS)
bogdanm	82:6473597d706e	603
bogdanm	82:6473597d706e	604	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	605	//! @brief Set the ADLSTS field to a new value.
bogdanm	82:6473597d706e	606	#define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) \| BF_ADC_CFG2_ADLSTS(v)))
bogdanm	82:6473597d706e	607	#endif
bogdanm	82:6473597d706e	608	//@}
bogdanm	82:6473597d706e	609
bogdanm	82:6473597d706e	610	/*!
bogdanm	82:6473597d706e	611	* @name Register ADC_CFG2, field ADHSC[2] (RW)
bogdanm	82:6473597d706e	612	*
bogdanm	82:6473597d706e	613	* Configures the ADC for very high-speed operation. The conversion sequence is
bogdanm	82:6473597d706e	614	* altered with 2 ADCK cycles added to the conversion time to allow higher speed
bogdanm	82:6473597d706e	615	* conversion clocks.
bogdanm	82:6473597d706e	616	*
bogdanm	82:6473597d706e	617	* Values:
bogdanm	82:6473597d706e	618	* - 0 - Normal conversion sequence selected.
bogdanm	82:6473597d706e	619	* - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
bogdanm	82:6473597d706e	620	* to total conversion time.
bogdanm	82:6473597d706e	621	*/
bogdanm	82:6473597d706e	622	//@{
bogdanm	82:6473597d706e	623	#define BP_ADC_CFG2_ADHSC (2U) //!< Bit position for ADC_CFG2_ADHSC.
bogdanm	82:6473597d706e	624	#define BM_ADC_CFG2_ADHSC (0x00000004U) //!< Bit mask for ADC_CFG2_ADHSC.
bogdanm	82:6473597d706e	625	#define BS_ADC_CFG2_ADHSC (1U) //!< Bit field size in bits for ADC_CFG2_ADHSC.
bogdanm	82:6473597d706e	626
bogdanm	82:6473597d706e	627	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	628	//! @brief Read current value of the ADC_CFG2_ADHSC field.
bogdanm	82:6473597d706e	629	#define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
bogdanm	82:6473597d706e	630	#endif
bogdanm	82:6473597d706e	631
bogdanm	82:6473597d706e	632	//! @brief Format value for bitfield ADC_CFG2_ADHSC.
bogdanm	82:6473597d706e	633	#define BF_ADC_CFG2_ADHSC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADHSC), uint32_t) & BM_ADC_CFG2_ADHSC)
bogdanm	82:6473597d706e	634
bogdanm	82:6473597d706e	635	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	636	//! @brief Set the ADHSC field to a new value.
bogdanm	82:6473597d706e	637	#define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
bogdanm	82:6473597d706e	638	#endif
bogdanm	82:6473597d706e	639	//@}
bogdanm	82:6473597d706e	640
bogdanm	82:6473597d706e	641	/*!
bogdanm	82:6473597d706e	642	* @name Register ADC_CFG2, field ADACKEN[3] (RW)
bogdanm	82:6473597d706e	643	*
bogdanm	82:6473597d706e	644	* Enables the asynchronous clock source and the clock source output regardless
bogdanm	82:6473597d706e	645	* of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
bogdanm	82:6473597d706e	646	* asynchronous clock may be used by other modules. See chip configuration
bogdanm	82:6473597d706e	647	* information. Setting this field allows the clock to be used even while the ADC is
bogdanm	82:6473597d706e	648	* idle or operating from a different clock source. Also, latency of initiating a
bogdanm	82:6473597d706e	649	* single or first-continuous conversion with the asynchronous clock selected is
bogdanm	82:6473597d706e	650	* reduced because the ADACK clock is already operational.
bogdanm	82:6473597d706e	651	*
bogdanm	82:6473597d706e	652	* Values:
bogdanm	82:6473597d706e	653	* - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
bogdanm	82:6473597d706e	654	* if selected by ADICLK and a conversion is active.
bogdanm	82:6473597d706e	655	* - 1 - Asynchronous clock and clock output is enabled regardless of the state
bogdanm	82:6473597d706e	656	* of the ADC.
bogdanm	82:6473597d706e	657	*/
bogdanm	82:6473597d706e	658	//@{
bogdanm	82:6473597d706e	659	#define BP_ADC_CFG2_ADACKEN (3U) //!< Bit position for ADC_CFG2_ADACKEN.
bogdanm	82:6473597d706e	660	#define BM_ADC_CFG2_ADACKEN (0x00000008U) //!< Bit mask for ADC_CFG2_ADACKEN.
bogdanm	82:6473597d706e	661	#define BS_ADC_CFG2_ADACKEN (1U) //!< Bit field size in bits for ADC_CFG2_ADACKEN.
bogdanm	82:6473597d706e	662
bogdanm	82:6473597d706e	663	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	664	//! @brief Read current value of the ADC_CFG2_ADACKEN field.
bogdanm	82:6473597d706e	665	#define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
bogdanm	82:6473597d706e	666	#endif
bogdanm	82:6473597d706e	667
bogdanm	82:6473597d706e	668	//! @brief Format value for bitfield ADC_CFG2_ADACKEN.
bogdanm	82:6473597d706e	669	#define BF_ADC_CFG2_ADACKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADACKEN), uint32_t) & BM_ADC_CFG2_ADACKEN)
bogdanm	82:6473597d706e	670
bogdanm	82:6473597d706e	671	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	672	//! @brief Set the ADACKEN field to a new value.
bogdanm	82:6473597d706e	673	#define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
bogdanm	82:6473597d706e	674	#endif
bogdanm	82:6473597d706e	675	//@}
bogdanm	82:6473597d706e	676
bogdanm	82:6473597d706e	677	/*!
bogdanm	82:6473597d706e	678	* @name Register ADC_CFG2, field MUXSEL[4] (RW)
bogdanm	82:6473597d706e	679	*
bogdanm	82:6473597d706e	680	* Changes the ADC mux setting to select between alternate sets of ADC channels.
bogdanm	82:6473597d706e	681	*
bogdanm	82:6473597d706e	682	* Values:
bogdanm	82:6473597d706e	683	* - 0 - ADxxa channels are selected.
bogdanm	82:6473597d706e	684	* - 1 - ADxxb channels are selected.
bogdanm	82:6473597d706e	685	*/
bogdanm	82:6473597d706e	686	//@{
bogdanm	82:6473597d706e	687	#define BP_ADC_CFG2_MUXSEL (4U) //!< Bit position for ADC_CFG2_MUXSEL.
bogdanm	82:6473597d706e	688	#define BM_ADC_CFG2_MUXSEL (0x00000010U) //!< Bit mask for ADC_CFG2_MUXSEL.
bogdanm	82:6473597d706e	689	#define BS_ADC_CFG2_MUXSEL (1U) //!< Bit field size in bits for ADC_CFG2_MUXSEL.
bogdanm	82:6473597d706e	690
bogdanm	82:6473597d706e	691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	692	//! @brief Read current value of the ADC_CFG2_MUXSEL field.
bogdanm	82:6473597d706e	693	#define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
bogdanm	82:6473597d706e	694	#endif
bogdanm	82:6473597d706e	695
bogdanm	82:6473597d706e	696	//! @brief Format value for bitfield ADC_CFG2_MUXSEL.
bogdanm	82:6473597d706e	697	#define BF_ADC_CFG2_MUXSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_MUXSEL), uint32_t) & BM_ADC_CFG2_MUXSEL)
bogdanm	82:6473597d706e	698
bogdanm	82:6473597d706e	699	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	700	//! @brief Set the MUXSEL field to a new value.
bogdanm	82:6473597d706e	701	#define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
bogdanm	82:6473597d706e	702	#endif
bogdanm	82:6473597d706e	703	//@}
bogdanm	82:6473597d706e	704
bogdanm	82:6473597d706e	705	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	706	// HW_ADC_Rn - ADC Data Result Register
bogdanm	82:6473597d706e	707	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	708
bogdanm	82:6473597d706e	709	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	710	/*!
bogdanm	82:6473597d706e	711	* @brief HW_ADC_Rn - ADC Data Result Register (RO)
bogdanm	82:6473597d706e	712	*
bogdanm	82:6473597d706e	713	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	714	*
bogdanm	82:6473597d706e	715	* The data result registers (Rn) contain the result of an ADC conversion of the
bogdanm	82:6473597d706e	716	* channel selected by the corresponding status and channel control register
bogdanm	82:6473597d706e	717	* (SC1A:SC1n). For every status and channel control register, there is a
bogdanm	82:6473597d706e	718	* corresponding data result register. Unused bits in R n are cleared in unsigned
bogdanm	82:6473597d706e	719	* right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
bogdanm	82:6473597d706e	720	* For example, when configured for 10-bit single-ended mode, D[15:10] are
bogdanm	82:6473597d706e	721	* cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
bogdanm	82:6473597d706e	722	* that is, bit 10 extended through bit 15. The following table describes the
bogdanm	82:6473597d706e	723	* behavior of the data result registers in the different modes of operation. Data
bogdanm	82:6473597d706e	724	* result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
bogdanm	82:6473597d706e	725	* D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
bogdanm	82:6473597d706e	726	* Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
bogdanm	82:6473597d706e	727	* Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
bogdanm	82:6473597d706e	728	* Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
bogdanm	82:6473597d706e	729	* Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
bogdanm	82:6473597d706e	730	* Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
bogdanm	82:6473597d706e	731	* Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
bogdanm	82:6473597d706e	732	* Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
bogdanm	82:6473597d706e	733	* Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
bogdanm	82:6473597d706e	734	* 2's complement data if indicated
bogdanm	82:6473597d706e	735	*/
bogdanm	82:6473597d706e	736	typedef union _hw_adc_rn
bogdanm	82:6473597d706e	737	{
bogdanm	82:6473597d706e	738	uint32_t U;
bogdanm	82:6473597d706e	739	struct _hw_adc_rn_bitfields
bogdanm	82:6473597d706e	740	{
bogdanm	82:6473597d706e	741	uint32_t D : 16; //!< [15:0] Data result
bogdanm	82:6473597d706e	742	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	743	} B;
bogdanm	82:6473597d706e	744	} hw_adc_rn_t;
bogdanm	82:6473597d706e	745	#endif
bogdanm	82:6473597d706e	746
bogdanm	82:6473597d706e	747	/*!
bogdanm	82:6473597d706e	748	* @name Constants and macros for entire ADC_Rn register
bogdanm	82:6473597d706e	749	*/
bogdanm	82:6473597d706e	750	//@{
bogdanm	82:6473597d706e	751	#define HW_ADC_Rn_COUNT (2U)
bogdanm	82:6473597d706e	752
bogdanm	82:6473597d706e	753	#define HW_ADC_Rn_ADDR(x, n) (REGS_ADC_BASE(x) + 0x10U + (0x4U * n))
bogdanm	82:6473597d706e	754
bogdanm	82:6473597d706e	755	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	756	#define HW_ADC_Rn(x, n) ((__I hw_adc_rn_t ) HW_ADC_Rn_ADDR(x, n))
bogdanm	82:6473597d706e	757	#define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
bogdanm	82:6473597d706e	758	#endif
bogdanm	82:6473597d706e	759	//@}
bogdanm	82:6473597d706e	760
bogdanm	82:6473597d706e	761	/*
bogdanm	82:6473597d706e	762	* Constants & macros for individual ADC_Rn bitfields
bogdanm	82:6473597d706e	763	*/
bogdanm	82:6473597d706e	764
bogdanm	82:6473597d706e	765	/*!
bogdanm	82:6473597d706e	766	* @name Register ADC_Rn, field D[15:0] (RO)
bogdanm	82:6473597d706e	767	*/
bogdanm	82:6473597d706e	768	//@{
bogdanm	82:6473597d706e	769	#define BP_ADC_Rn_D (0U) //!< Bit position for ADC_Rn_D.
bogdanm	82:6473597d706e	770	#define BM_ADC_Rn_D (0x0000FFFFU) //!< Bit mask for ADC_Rn_D.
bogdanm	82:6473597d706e	771	#define BS_ADC_Rn_D (16U) //!< Bit field size in bits for ADC_Rn_D.
bogdanm	82:6473597d706e	772
bogdanm	82:6473597d706e	773	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	774	//! @brief Read current value of the ADC_Rn_D field.
bogdanm	82:6473597d706e	775	#define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
bogdanm	82:6473597d706e	776	#endif
bogdanm	82:6473597d706e	777	//@}
bogdanm	82:6473597d706e	778
bogdanm	82:6473597d706e	779	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	780	// HW_ADC_CV1 - Compare Value Registers
bogdanm	82:6473597d706e	781	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	782
bogdanm	82:6473597d706e	783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	784	/*!
bogdanm	82:6473597d706e	785	* @brief HW_ADC_CV1 - Compare Value Registers (RW)
bogdanm	82:6473597d706e	786	*
bogdanm	82:6473597d706e	787	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	788	*
bogdanm	82:6473597d706e	789	* The Compare Value Registers (CV1 and CV2) contain a compare value used to
bogdanm	82:6473597d706e	790	* compare the conversion result when the compare function is enabled, that is,
bogdanm	82:6473597d706e	791	* SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
bogdanm	82:6473597d706e	792	* different modes of operation for both bit position definition and value format
bogdanm	82:6473597d706e	793	* using unsigned or sign-extended 2's complement. Therefore, the compare function
bogdanm	82:6473597d706e	794	* uses only the CVn fields that are related to the ADC mode of operation. The
bogdanm	82:6473597d706e	795	* compare value 2 register (CV2) is used only when the compare range function is
bogdanm	82:6473597d706e	796	* enabled, that is, SC2[ACREN]=1.
bogdanm	82:6473597d706e	797	*/
bogdanm	82:6473597d706e	798	typedef union _hw_adc_cv1
bogdanm	82:6473597d706e	799	{
bogdanm	82:6473597d706e	800	uint32_t U;
bogdanm	82:6473597d706e	801	struct _hw_adc_cv1_bitfields
bogdanm	82:6473597d706e	802	{
bogdanm	82:6473597d706e	803	uint32_t CV : 16; //!< [15:0] Compare Value.
bogdanm	82:6473597d706e	804	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	805	} B;
bogdanm	82:6473597d706e	806	} hw_adc_cv1_t;
bogdanm	82:6473597d706e	807	#endif
bogdanm	82:6473597d706e	808
bogdanm	82:6473597d706e	809	/*!
bogdanm	82:6473597d706e	810	* @name Constants and macros for entire ADC_CV1 register
bogdanm	82:6473597d706e	811	*/
bogdanm	82:6473597d706e	812	//@{
bogdanm	82:6473597d706e	813	#define HW_ADC_CV1_ADDR(x) (REGS_ADC_BASE(x) + 0x18U)
bogdanm	82:6473597d706e	814
bogdanm	82:6473597d706e	815	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	816	#define HW_ADC_CV1(x) ((__IO hw_adc_cv1_t ) HW_ADC_CV1_ADDR(x))
bogdanm	82:6473597d706e	817	#define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
bogdanm	82:6473597d706e	818	#define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
bogdanm	82:6473597d706e	819	#define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) \| (v)))
bogdanm	82:6473597d706e	820	#define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	821	#define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	822	#endif
bogdanm	82:6473597d706e	823	//@}
bogdanm	82:6473597d706e	824
bogdanm	82:6473597d706e	825	/*
bogdanm	82:6473597d706e	826	* Constants & macros for individual ADC_CV1 bitfields
bogdanm	82:6473597d706e	827	*/
bogdanm	82:6473597d706e	828
bogdanm	82:6473597d706e	829	/*!
bogdanm	82:6473597d706e	830	* @name Register ADC_CV1, field CV[15:0] (RW)
bogdanm	82:6473597d706e	831	*/
bogdanm	82:6473597d706e	832	//@{
bogdanm	82:6473597d706e	833	#define BP_ADC_CV1_CV (0U) //!< Bit position for ADC_CV1_CV.
bogdanm	82:6473597d706e	834	#define BM_ADC_CV1_CV (0x0000FFFFU) //!< Bit mask for ADC_CV1_CV.
bogdanm	82:6473597d706e	835	#define BS_ADC_CV1_CV (16U) //!< Bit field size in bits for ADC_CV1_CV.
bogdanm	82:6473597d706e	836
bogdanm	82:6473597d706e	837	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	838	//! @brief Read current value of the ADC_CV1_CV field.
bogdanm	82:6473597d706e	839	#define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
bogdanm	82:6473597d706e	840	#endif
bogdanm	82:6473597d706e	841
bogdanm	82:6473597d706e	842	//! @brief Format value for bitfield ADC_CV1_CV.
bogdanm	82:6473597d706e	843	#define BF_ADC_CV1_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV1_CV), uint32_t) & BM_ADC_CV1_CV)
bogdanm	82:6473597d706e	844
bogdanm	82:6473597d706e	845	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	846	//! @brief Set the CV field to a new value.
bogdanm	82:6473597d706e	847	#define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) \| BF_ADC_CV1_CV(v)))
bogdanm	82:6473597d706e	848	#endif
bogdanm	82:6473597d706e	849	//@}
bogdanm	82:6473597d706e	850
bogdanm	82:6473597d706e	851	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	852	// HW_ADC_CV2 - Compare Value Registers
bogdanm	82:6473597d706e	853	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	856	/*!
bogdanm	82:6473597d706e	857	* @brief HW_ADC_CV2 - Compare Value Registers (RW)
bogdanm	82:6473597d706e	858	*
bogdanm	82:6473597d706e	859	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	860	*
bogdanm	82:6473597d706e	861	* The Compare Value Registers (CV1 and CV2) contain a compare value used to
bogdanm	82:6473597d706e	862	* compare the conversion result when the compare function is enabled, that is,
bogdanm	82:6473597d706e	863	* SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
bogdanm	82:6473597d706e	864	* different modes of operation for both bit position definition and value format
bogdanm	82:6473597d706e	865	* using unsigned or sign-extended 2's complement. Therefore, the compare function
bogdanm	82:6473597d706e	866	* uses only the CVn fields that are related to the ADC mode of operation. The
bogdanm	82:6473597d706e	867	* compare value 2 register (CV2) is used only when the compare range function is
bogdanm	82:6473597d706e	868	* enabled, that is, SC2[ACREN]=1.
bogdanm	82:6473597d706e	869	*/
bogdanm	82:6473597d706e	870	typedef union _hw_adc_cv2
bogdanm	82:6473597d706e	871	{
bogdanm	82:6473597d706e	872	uint32_t U;
bogdanm	82:6473597d706e	873	struct _hw_adc_cv2_bitfields
bogdanm	82:6473597d706e	874	{
bogdanm	82:6473597d706e	875	uint32_t CV : 16; //!< [15:0] Compare Value.
bogdanm	82:6473597d706e	876	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	877	} B;
bogdanm	82:6473597d706e	878	} hw_adc_cv2_t;
bogdanm	82:6473597d706e	879	#endif
bogdanm	82:6473597d706e	880
bogdanm	82:6473597d706e	881	/*!
bogdanm	82:6473597d706e	882	* @name Constants and macros for entire ADC_CV2 register
bogdanm	82:6473597d706e	883	*/
bogdanm	82:6473597d706e	884	//@{
bogdanm	82:6473597d706e	885	#define HW_ADC_CV2_ADDR(x) (REGS_ADC_BASE(x) + 0x1CU)
bogdanm	82:6473597d706e	886
bogdanm	82:6473597d706e	887	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	888	#define HW_ADC_CV2(x) ((__IO hw_adc_cv2_t ) HW_ADC_CV2_ADDR(x))
bogdanm	82:6473597d706e	889	#define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
bogdanm	82:6473597d706e	890	#define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
bogdanm	82:6473597d706e	891	#define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) \| (v)))
bogdanm	82:6473597d706e	892	#define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	893	#define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	894	#endif
bogdanm	82:6473597d706e	895	//@}
bogdanm	82:6473597d706e	896
bogdanm	82:6473597d706e	897	/*
bogdanm	82:6473597d706e	898	* Constants & macros for individual ADC_CV2 bitfields
bogdanm	82:6473597d706e	899	*/
bogdanm	82:6473597d706e	900
bogdanm	82:6473597d706e	901	/*!
bogdanm	82:6473597d706e	902	* @name Register ADC_CV2, field CV[15:0] (RW)
bogdanm	82:6473597d706e	903	*/
bogdanm	82:6473597d706e	904	//@{
bogdanm	82:6473597d706e	905	#define BP_ADC_CV2_CV (0U) //!< Bit position for ADC_CV2_CV.
bogdanm	82:6473597d706e	906	#define BM_ADC_CV2_CV (0x0000FFFFU) //!< Bit mask for ADC_CV2_CV.
bogdanm	82:6473597d706e	907	#define BS_ADC_CV2_CV (16U) //!< Bit field size in bits for ADC_CV2_CV.
bogdanm	82:6473597d706e	908
bogdanm	82:6473597d706e	909	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	910	//! @brief Read current value of the ADC_CV2_CV field.
bogdanm	82:6473597d706e	911	#define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
bogdanm	82:6473597d706e	912	#endif
bogdanm	82:6473597d706e	913
bogdanm	82:6473597d706e	914	//! @brief Format value for bitfield ADC_CV2_CV.
bogdanm	82:6473597d706e	915	#define BF_ADC_CV2_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV2_CV), uint32_t) & BM_ADC_CV2_CV)
bogdanm	82:6473597d706e	916
bogdanm	82:6473597d706e	917	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	918	//! @brief Set the CV field to a new value.
bogdanm	82:6473597d706e	919	#define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) \| BF_ADC_CV2_CV(v)))
bogdanm	82:6473597d706e	920	#endif
bogdanm	82:6473597d706e	921	//@}
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	924	// HW_ADC_SC2 - Status and Control Register 2
bogdanm	82:6473597d706e	925	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	926
bogdanm	82:6473597d706e	927	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	928	/*!
bogdanm	82:6473597d706e	929	* @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
bogdanm	82:6473597d706e	930	*
bogdanm	82:6473597d706e	931	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	932	*
bogdanm	82:6473597d706e	933	* The status and control register 2 (SC2) contains the conversion active,
bogdanm	82:6473597d706e	934	* hardware/software trigger select, compare function, and voltage reference select of
bogdanm	82:6473597d706e	935	* the ADC module.
bogdanm	82:6473597d706e	936	*/
bogdanm	82:6473597d706e	937	typedef union _hw_adc_sc2
bogdanm	82:6473597d706e	938	{
bogdanm	82:6473597d706e	939	uint32_t U;
bogdanm	82:6473597d706e	940	struct _hw_adc_sc2_bitfields
bogdanm	82:6473597d706e	941	{
bogdanm	82:6473597d706e	942	uint32_t REFSEL : 2; //!< [1:0] Voltage Reference Selection
bogdanm	82:6473597d706e	943	uint32_t DMAEN : 1; //!< [2] DMA Enable
bogdanm	82:6473597d706e	944	uint32_t ACREN : 1; //!< [3] Compare Function Range Enable
bogdanm	82:6473597d706e	945	uint32_t ACFGT : 1; //!< [4] Compare Function Greater Than Enable
bogdanm	82:6473597d706e	946	uint32_t ACFE : 1; //!< [5] Compare Function Enable
bogdanm	82:6473597d706e	947	uint32_t ADTRG : 1; //!< [6] Conversion Trigger Select
bogdanm	82:6473597d706e	948	uint32_t ADACT : 1; //!< [7] Conversion Active
bogdanm	82:6473597d706e	949	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	950	} B;
bogdanm	82:6473597d706e	951	} hw_adc_sc2_t;
bogdanm	82:6473597d706e	952	#endif
bogdanm	82:6473597d706e	953
bogdanm	82:6473597d706e	954	/*!
bogdanm	82:6473597d706e	955	* @name Constants and macros for entire ADC_SC2 register
bogdanm	82:6473597d706e	956	*/
bogdanm	82:6473597d706e	957	//@{
bogdanm	82:6473597d706e	958	#define HW_ADC_SC2_ADDR(x) (REGS_ADC_BASE(x) + 0x20U)
bogdanm	82:6473597d706e	959
bogdanm	82:6473597d706e	960	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	961	#define HW_ADC_SC2(x) ((__IO hw_adc_sc2_t ) HW_ADC_SC2_ADDR(x))
bogdanm	82:6473597d706e	962	#define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
bogdanm	82:6473597d706e	963	#define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
bogdanm	82:6473597d706e	964	#define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) \| (v)))
bogdanm	82:6473597d706e	965	#define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	966	#define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	967	#endif
bogdanm	82:6473597d706e	968	//@}
bogdanm	82:6473597d706e	969
bogdanm	82:6473597d706e	970	/*
bogdanm	82:6473597d706e	971	* Constants & macros for individual ADC_SC2 bitfields
bogdanm	82:6473597d706e	972	*/
bogdanm	82:6473597d706e	973
bogdanm	82:6473597d706e	974	/*!
bogdanm	82:6473597d706e	975	* @name Register ADC_SC2, field REFSEL[1:0] (RW)
bogdanm	82:6473597d706e	976	*
bogdanm	82:6473597d706e	977	* Selects the voltage reference source used for conversions.
bogdanm	82:6473597d706e	978	*
bogdanm	82:6473597d706e	979	* Values:
bogdanm	82:6473597d706e	980	* - 00 - Default voltage reference pin pair, that is, external pins VREFH and
bogdanm	82:6473597d706e	981	* VREFL
bogdanm	82:6473597d706e	982	* - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
bogdanm	82:6473597d706e	983	* additional external pins or internal sources depending on the MCU
bogdanm	82:6473597d706e	984	* configuration. See the chip configuration information for details specific to this
bogdanm	82:6473597d706e	985	* MCU
bogdanm	82:6473597d706e	986	* - 10 - Reserved
bogdanm	82:6473597d706e	987	* - 11 - Reserved
bogdanm	82:6473597d706e	988	*/
bogdanm	82:6473597d706e	989	//@{
bogdanm	82:6473597d706e	990	#define BP_ADC_SC2_REFSEL (0U) //!< Bit position for ADC_SC2_REFSEL.
bogdanm	82:6473597d706e	991	#define BM_ADC_SC2_REFSEL (0x00000003U) //!< Bit mask for ADC_SC2_REFSEL.
bogdanm	82:6473597d706e	992	#define BS_ADC_SC2_REFSEL (2U) //!< Bit field size in bits for ADC_SC2_REFSEL.
bogdanm	82:6473597d706e	993
bogdanm	82:6473597d706e	994	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	995	//! @brief Read current value of the ADC_SC2_REFSEL field.
bogdanm	82:6473597d706e	996	#define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
bogdanm	82:6473597d706e	997	#endif
bogdanm	82:6473597d706e	998
bogdanm	82:6473597d706e	999	//! @brief Format value for bitfield ADC_SC2_REFSEL.
bogdanm	82:6473597d706e	1000	#define BF_ADC_SC2_REFSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_REFSEL), uint32_t) & BM_ADC_SC2_REFSEL)
bogdanm	82:6473597d706e	1001
bogdanm	82:6473597d706e	1002	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1003	//! @brief Set the REFSEL field to a new value.
bogdanm	82:6473597d706e	1004	#define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) \| BF_ADC_SC2_REFSEL(v)))
bogdanm	82:6473597d706e	1005	#endif
bogdanm	82:6473597d706e	1006	//@}
bogdanm	82:6473597d706e	1007
bogdanm	82:6473597d706e	1008	/*!
bogdanm	82:6473597d706e	1009	* @name Register ADC_SC2, field DMAEN[2] (RW)
bogdanm	82:6473597d706e	1010	*
bogdanm	82:6473597d706e	1011	* Values:
bogdanm	82:6473597d706e	1012	* - 0 - DMA is disabled.
bogdanm	82:6473597d706e	1013	* - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
bogdanm	82:6473597d706e	1014	* conversion complete event noted when any of the SC1n[COCO] flags is asserted.
bogdanm	82:6473597d706e	1015	*/
bogdanm	82:6473597d706e	1016	//@{
bogdanm	82:6473597d706e	1017	#define BP_ADC_SC2_DMAEN (2U) //!< Bit position for ADC_SC2_DMAEN.
bogdanm	82:6473597d706e	1018	#define BM_ADC_SC2_DMAEN (0x00000004U) //!< Bit mask for ADC_SC2_DMAEN.
bogdanm	82:6473597d706e	1019	#define BS_ADC_SC2_DMAEN (1U) //!< Bit field size in bits for ADC_SC2_DMAEN.
bogdanm	82:6473597d706e	1020
bogdanm	82:6473597d706e	1021	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1022	//! @brief Read current value of the ADC_SC2_DMAEN field.
bogdanm	82:6473597d706e	1023	#define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
bogdanm	82:6473597d706e	1024	#endif
bogdanm	82:6473597d706e	1025
bogdanm	82:6473597d706e	1026	//! @brief Format value for bitfield ADC_SC2_DMAEN.
bogdanm	82:6473597d706e	1027	#define BF_ADC_SC2_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_DMAEN), uint32_t) & BM_ADC_SC2_DMAEN)
bogdanm	82:6473597d706e	1028
bogdanm	82:6473597d706e	1029	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1030	//! @brief Set the DMAEN field to a new value.
bogdanm	82:6473597d706e	1031	#define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
bogdanm	82:6473597d706e	1032	#endif
bogdanm	82:6473597d706e	1033	//@}
bogdanm	82:6473597d706e	1034
bogdanm	82:6473597d706e	1035	/*!
bogdanm	82:6473597d706e	1036	* @name Register ADC_SC2, field ACREN[3] (RW)
bogdanm	82:6473597d706e	1037	*
bogdanm	82:6473597d706e	1038	* Configures the compare function to check if the conversion result of the
bogdanm	82:6473597d706e	1039	* input being monitored is either between or outside the range formed by CV1 and CV2
bogdanm	82:6473597d706e	1040	* determined by the value of ACFGT. ACFE must be set for ACFGT to have any
bogdanm	82:6473597d706e	1041	* effect.
bogdanm	82:6473597d706e	1042	*
bogdanm	82:6473597d706e	1043	* Values:
bogdanm	82:6473597d706e	1044	* - 0 - Range function disabled. Only CV1 is compared.
bogdanm	82:6473597d706e	1045	* - 1 - Range function enabled. Both CV1 and CV2 are compared.
bogdanm	82:6473597d706e	1046	*/
bogdanm	82:6473597d706e	1047	//@{
bogdanm	82:6473597d706e	1048	#define BP_ADC_SC2_ACREN (3U) //!< Bit position for ADC_SC2_ACREN.
bogdanm	82:6473597d706e	1049	#define BM_ADC_SC2_ACREN (0x00000008U) //!< Bit mask for ADC_SC2_ACREN.
bogdanm	82:6473597d706e	1050	#define BS_ADC_SC2_ACREN (1U) //!< Bit field size in bits for ADC_SC2_ACREN.
bogdanm	82:6473597d706e	1051
bogdanm	82:6473597d706e	1052	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1053	//! @brief Read current value of the ADC_SC2_ACREN field.
bogdanm	82:6473597d706e	1054	#define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
bogdanm	82:6473597d706e	1055	#endif
bogdanm	82:6473597d706e	1056
bogdanm	82:6473597d706e	1057	//! @brief Format value for bitfield ADC_SC2_ACREN.
bogdanm	82:6473597d706e	1058	#define BF_ADC_SC2_ACREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACREN), uint32_t) & BM_ADC_SC2_ACREN)
bogdanm	82:6473597d706e	1059
bogdanm	82:6473597d706e	1060	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1061	//! @brief Set the ACREN field to a new value.
bogdanm	82:6473597d706e	1062	#define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
bogdanm	82:6473597d706e	1063	#endif
bogdanm	82:6473597d706e	1064	//@}
bogdanm	82:6473597d706e	1065
bogdanm	82:6473597d706e	1066	/*!
bogdanm	82:6473597d706e	1067	* @name Register ADC_SC2, field ACFGT[4] (RW)
bogdanm	82:6473597d706e	1068	*
bogdanm	82:6473597d706e	1069	* Configures the compare function to check the conversion result relative to
bogdanm	82:6473597d706e	1070	* the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
bogdanm	82:6473597d706e	1071	* have any effect.
bogdanm	82:6473597d706e	1072	*
bogdanm	82:6473597d706e	1073	* Values:
bogdanm	82:6473597d706e	1074	* - 0 - Configures less than threshold, outside range not inclusive and inside
bogdanm	82:6473597d706e	1075	* range not inclusive; functionality based on the values placed in CV1 and
bogdanm	82:6473597d706e	1076	* CV2.
bogdanm	82:6473597d706e	1077	* - 1 - Configures greater than or equal to threshold, outside and inside
bogdanm	82:6473597d706e	1078	* ranges inclusive; functionality based on the values placed in CV1 and CV2.
bogdanm	82:6473597d706e	1079	*/
bogdanm	82:6473597d706e	1080	//@{
bogdanm	82:6473597d706e	1081	#define BP_ADC_SC2_ACFGT (4U) //!< Bit position for ADC_SC2_ACFGT.
bogdanm	82:6473597d706e	1082	#define BM_ADC_SC2_ACFGT (0x00000010U) //!< Bit mask for ADC_SC2_ACFGT.
bogdanm	82:6473597d706e	1083	#define BS_ADC_SC2_ACFGT (1U) //!< Bit field size in bits for ADC_SC2_ACFGT.
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1086	//! @brief Read current value of the ADC_SC2_ACFGT field.
bogdanm	82:6473597d706e	1087	#define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
bogdanm	82:6473597d706e	1088	#endif
bogdanm	82:6473597d706e	1089
bogdanm	82:6473597d706e	1090	//! @brief Format value for bitfield ADC_SC2_ACFGT.
bogdanm	82:6473597d706e	1091	#define BF_ADC_SC2_ACFGT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFGT), uint32_t) & BM_ADC_SC2_ACFGT)
bogdanm	82:6473597d706e	1092
bogdanm	82:6473597d706e	1093	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1094	//! @brief Set the ACFGT field to a new value.
bogdanm	82:6473597d706e	1095	#define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
bogdanm	82:6473597d706e	1096	#endif
bogdanm	82:6473597d706e	1097	//@}
bogdanm	82:6473597d706e	1098
bogdanm	82:6473597d706e	1099	/*!
bogdanm	82:6473597d706e	1100	* @name Register ADC_SC2, field ACFE[5] (RW)
bogdanm	82:6473597d706e	1101	*
bogdanm	82:6473597d706e	1102	* Enables the compare function.
bogdanm	82:6473597d706e	1103	*
bogdanm	82:6473597d706e	1104	* Values:
bogdanm	82:6473597d706e	1105	* - 0 - Compare function disabled.
bogdanm	82:6473597d706e	1106	* - 1 - Compare function enabled.
bogdanm	82:6473597d706e	1107	*/
bogdanm	82:6473597d706e	1108	//@{
bogdanm	82:6473597d706e	1109	#define BP_ADC_SC2_ACFE (5U) //!< Bit position for ADC_SC2_ACFE.
bogdanm	82:6473597d706e	1110	#define BM_ADC_SC2_ACFE (0x00000020U) //!< Bit mask for ADC_SC2_ACFE.
bogdanm	82:6473597d706e	1111	#define BS_ADC_SC2_ACFE (1U) //!< Bit field size in bits for ADC_SC2_ACFE.
bogdanm	82:6473597d706e	1112
bogdanm	82:6473597d706e	1113	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1114	//! @brief Read current value of the ADC_SC2_ACFE field.
bogdanm	82:6473597d706e	1115	#define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
bogdanm	82:6473597d706e	1116	#endif
bogdanm	82:6473597d706e	1117
bogdanm	82:6473597d706e	1118	//! @brief Format value for bitfield ADC_SC2_ACFE.
bogdanm	82:6473597d706e	1119	#define BF_ADC_SC2_ACFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFE), uint32_t) & BM_ADC_SC2_ACFE)
bogdanm	82:6473597d706e	1120
bogdanm	82:6473597d706e	1121	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1122	//! @brief Set the ACFE field to a new value.
bogdanm	82:6473597d706e	1123	#define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
bogdanm	82:6473597d706e	1124	#endif
bogdanm	82:6473597d706e	1125	//@}
bogdanm	82:6473597d706e	1126
bogdanm	82:6473597d706e	1127	/*!
bogdanm	82:6473597d706e	1128	* @name Register ADC_SC2, field ADTRG[6] (RW)
bogdanm	82:6473597d706e	1129	*
bogdanm	82:6473597d706e	1130	* Selects the type of trigger used for initiating a conversion. Two types of
bogdanm	82:6473597d706e	1131	* trigger are selectable: Software trigger: When software trigger is selected, a
bogdanm	82:6473597d706e	1132	* conversion is initiated following a write to SC1A. Hardware trigger: When
bogdanm	82:6473597d706e	1133	* hardware trigger is selected, a conversion is initiated following the assertion of
bogdanm	82:6473597d706e	1134	* the ADHWT input after a pulse of the ADHWTSn input.
bogdanm	82:6473597d706e	1135	*
bogdanm	82:6473597d706e	1136	* Values:
bogdanm	82:6473597d706e	1137	* - 0 - Software trigger selected.
bogdanm	82:6473597d706e	1138	* - 1 - Hardware trigger selected.
bogdanm	82:6473597d706e	1139	*/
bogdanm	82:6473597d706e	1140	//@{
bogdanm	82:6473597d706e	1141	#define BP_ADC_SC2_ADTRG (6U) //!< Bit position for ADC_SC2_ADTRG.
bogdanm	82:6473597d706e	1142	#define BM_ADC_SC2_ADTRG (0x00000040U) //!< Bit mask for ADC_SC2_ADTRG.
bogdanm	82:6473597d706e	1143	#define BS_ADC_SC2_ADTRG (1U) //!< Bit field size in bits for ADC_SC2_ADTRG.
bogdanm	82:6473597d706e	1144
bogdanm	82:6473597d706e	1145	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1146	//! @brief Read current value of the ADC_SC2_ADTRG field.
bogdanm	82:6473597d706e	1147	#define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
bogdanm	82:6473597d706e	1148	#endif
bogdanm	82:6473597d706e	1149
bogdanm	82:6473597d706e	1150	//! @brief Format value for bitfield ADC_SC2_ADTRG.
bogdanm	82:6473597d706e	1151	#define BF_ADC_SC2_ADTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ADTRG), uint32_t) & BM_ADC_SC2_ADTRG)
bogdanm	82:6473597d706e	1152
bogdanm	82:6473597d706e	1153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1154	//! @brief Set the ADTRG field to a new value.
bogdanm	82:6473597d706e	1155	#define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
bogdanm	82:6473597d706e	1156	#endif
bogdanm	82:6473597d706e	1157	//@}
bogdanm	82:6473597d706e	1158
bogdanm	82:6473597d706e	1159	/*!
bogdanm	82:6473597d706e	1160	* @name Register ADC_SC2, field ADACT[7] (RO)
bogdanm	82:6473597d706e	1161	*
bogdanm	82:6473597d706e	1162	* Indicates that a conversion or hardware averaging is in progress. ADACT is
bogdanm	82:6473597d706e	1163	* set when a conversion is initiated and cleared when a conversion is completed or
bogdanm	82:6473597d706e	1164	* aborted.
bogdanm	82:6473597d706e	1165	*
bogdanm	82:6473597d706e	1166	* Values:
bogdanm	82:6473597d706e	1167	* - 0 - Conversion not in progress.
bogdanm	82:6473597d706e	1168	* - 1 - Conversion in progress.
bogdanm	82:6473597d706e	1169	*/
bogdanm	82:6473597d706e	1170	//@{
bogdanm	82:6473597d706e	1171	#define BP_ADC_SC2_ADACT (7U) //!< Bit position for ADC_SC2_ADACT.
bogdanm	82:6473597d706e	1172	#define BM_ADC_SC2_ADACT (0x00000080U) //!< Bit mask for ADC_SC2_ADACT.
bogdanm	82:6473597d706e	1173	#define BS_ADC_SC2_ADACT (1U) //!< Bit field size in bits for ADC_SC2_ADACT.
bogdanm	82:6473597d706e	1174
bogdanm	82:6473597d706e	1175	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1176	//! @brief Read current value of the ADC_SC2_ADACT field.
bogdanm	82:6473597d706e	1177	#define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
bogdanm	82:6473597d706e	1178	#endif
bogdanm	82:6473597d706e	1179	//@}
bogdanm	82:6473597d706e	1180
bogdanm	82:6473597d706e	1181	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1182	// HW_ADC_SC3 - Status and Control Register 3
bogdanm	82:6473597d706e	1183	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1184
bogdanm	82:6473597d706e	1185	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1186	/*!
bogdanm	82:6473597d706e	1187	* @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
bogdanm	82:6473597d706e	1188	*
bogdanm	82:6473597d706e	1189	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1190	*
bogdanm	82:6473597d706e	1191	* The Status and Control Register 3 (SC3) controls the calibration, continuous
bogdanm	82:6473597d706e	1192	* convert, and hardware averaging functions of the ADC module.
bogdanm	82:6473597d706e	1193	*/
bogdanm	82:6473597d706e	1194	typedef union _hw_adc_sc3
bogdanm	82:6473597d706e	1195	{
bogdanm	82:6473597d706e	1196	uint32_t U;
bogdanm	82:6473597d706e	1197	struct _hw_adc_sc3_bitfields
bogdanm	82:6473597d706e	1198	{
bogdanm	82:6473597d706e	1199	uint32_t AVGS : 2; //!< [1:0] Hardware Average Select
bogdanm	82:6473597d706e	1200	uint32_t AVGE : 1; //!< [2] Hardware Average Enable
bogdanm	82:6473597d706e	1201	uint32_t ADCO : 1; //!< [3] Continuous Conversion Enable
bogdanm	82:6473597d706e	1202	uint32_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	1203	uint32_t CALF : 1; //!< [6] Calibration Failed Flag
bogdanm	82:6473597d706e	1204	uint32_t CAL : 1; //!< [7] Calibration
bogdanm	82:6473597d706e	1205	uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1206	} B;
bogdanm	82:6473597d706e	1207	} hw_adc_sc3_t;
bogdanm	82:6473597d706e	1208	#endif
bogdanm	82:6473597d706e	1209
bogdanm	82:6473597d706e	1210	/*!
bogdanm	82:6473597d706e	1211	* @name Constants and macros for entire ADC_SC3 register
bogdanm	82:6473597d706e	1212	*/
bogdanm	82:6473597d706e	1213	//@{
bogdanm	82:6473597d706e	1214	#define HW_ADC_SC3_ADDR(x) (REGS_ADC_BASE(x) + 0x24U)
bogdanm	82:6473597d706e	1215
bogdanm	82:6473597d706e	1216	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1217	#define HW_ADC_SC3(x) ((__IO hw_adc_sc3_t ) HW_ADC_SC3_ADDR(x))
bogdanm	82:6473597d706e	1218	#define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
bogdanm	82:6473597d706e	1219	#define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
bogdanm	82:6473597d706e	1220	#define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) \| (v)))
bogdanm	82:6473597d706e	1221	#define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1222	#define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1223	#endif
bogdanm	82:6473597d706e	1224	//@}
bogdanm	82:6473597d706e	1225
bogdanm	82:6473597d706e	1226	/*
bogdanm	82:6473597d706e	1227	* Constants & macros for individual ADC_SC3 bitfields
bogdanm	82:6473597d706e	1228	*/
bogdanm	82:6473597d706e	1229
bogdanm	82:6473597d706e	1230	/*!
bogdanm	82:6473597d706e	1231	* @name Register ADC_SC3, field AVGS[1:0] (RW)
bogdanm	82:6473597d706e	1232	*
bogdanm	82:6473597d706e	1233	* Determines how many ADC conversions will be averaged to create the ADC
bogdanm	82:6473597d706e	1234	* average result.
bogdanm	82:6473597d706e	1235	*
bogdanm	82:6473597d706e	1236	* Values:
bogdanm	82:6473597d706e	1237	* - 00 - 4 samples averaged.
bogdanm	82:6473597d706e	1238	* - 01 - 8 samples averaged.
bogdanm	82:6473597d706e	1239	* - 10 - 16 samples averaged.
bogdanm	82:6473597d706e	1240	* - 11 - 32 samples averaged.
bogdanm	82:6473597d706e	1241	*/
bogdanm	82:6473597d706e	1242	//@{
bogdanm	82:6473597d706e	1243	#define BP_ADC_SC3_AVGS (0U) //!< Bit position for ADC_SC3_AVGS.
bogdanm	82:6473597d706e	1244	#define BM_ADC_SC3_AVGS (0x00000003U) //!< Bit mask for ADC_SC3_AVGS.
bogdanm	82:6473597d706e	1245	#define BS_ADC_SC3_AVGS (2U) //!< Bit field size in bits for ADC_SC3_AVGS.
bogdanm	82:6473597d706e	1246
bogdanm	82:6473597d706e	1247	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1248	//! @brief Read current value of the ADC_SC3_AVGS field.
bogdanm	82:6473597d706e	1249	#define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
bogdanm	82:6473597d706e	1250	#endif
bogdanm	82:6473597d706e	1251
bogdanm	82:6473597d706e	1252	//! @brief Format value for bitfield ADC_SC3_AVGS.
bogdanm	82:6473597d706e	1253	#define BF_ADC_SC3_AVGS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGS), uint32_t) & BM_ADC_SC3_AVGS)
bogdanm	82:6473597d706e	1254
bogdanm	82:6473597d706e	1255	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1256	//! @brief Set the AVGS field to a new value.
bogdanm	82:6473597d706e	1257	#define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) \| BF_ADC_SC3_AVGS(v)))
bogdanm	82:6473597d706e	1258	#endif
bogdanm	82:6473597d706e	1259	//@}
bogdanm	82:6473597d706e	1260
bogdanm	82:6473597d706e	1261	/*!
bogdanm	82:6473597d706e	1262	* @name Register ADC_SC3, field AVGE[2] (RW)
bogdanm	82:6473597d706e	1263	*
bogdanm	82:6473597d706e	1264	* Enables the hardware average function of the ADC.
bogdanm	82:6473597d706e	1265	*
bogdanm	82:6473597d706e	1266	* Values:
bogdanm	82:6473597d706e	1267	* - 0 - Hardware average function disabled.
bogdanm	82:6473597d706e	1268	* - 1 - Hardware average function enabled.
bogdanm	82:6473597d706e	1269	*/
bogdanm	82:6473597d706e	1270	//@{
bogdanm	82:6473597d706e	1271	#define BP_ADC_SC3_AVGE (2U) //!< Bit position for ADC_SC3_AVGE.
bogdanm	82:6473597d706e	1272	#define BM_ADC_SC3_AVGE (0x00000004U) //!< Bit mask for ADC_SC3_AVGE.
bogdanm	82:6473597d706e	1273	#define BS_ADC_SC3_AVGE (1U) //!< Bit field size in bits for ADC_SC3_AVGE.
bogdanm	82:6473597d706e	1274
bogdanm	82:6473597d706e	1275	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1276	//! @brief Read current value of the ADC_SC3_AVGE field.
bogdanm	82:6473597d706e	1277	#define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
bogdanm	82:6473597d706e	1278	#endif
bogdanm	82:6473597d706e	1279
bogdanm	82:6473597d706e	1280	//! @brief Format value for bitfield ADC_SC3_AVGE.
bogdanm	82:6473597d706e	1281	#define BF_ADC_SC3_AVGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGE), uint32_t) & BM_ADC_SC3_AVGE)
bogdanm	82:6473597d706e	1282
bogdanm	82:6473597d706e	1283	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1284	//! @brief Set the AVGE field to a new value.
bogdanm	82:6473597d706e	1285	#define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
bogdanm	82:6473597d706e	1286	#endif
bogdanm	82:6473597d706e	1287	//@}
bogdanm	82:6473597d706e	1288
bogdanm	82:6473597d706e	1289	/*!
bogdanm	82:6473597d706e	1290	* @name Register ADC_SC3, field ADCO[3] (RW)
bogdanm	82:6473597d706e	1291	*
bogdanm	82:6473597d706e	1292	* Enables continuous conversions.
bogdanm	82:6473597d706e	1293	*
bogdanm	82:6473597d706e	1294	* Values:
bogdanm	82:6473597d706e	1295	* - 0 - One conversion or one set of conversions if the hardware average
bogdanm	82:6473597d706e	1296	* function is enabled, that is, AVGE=1, after initiating a conversion.
bogdanm	82:6473597d706e	1297	* - 1 - Continuous conversions or sets of conversions if the hardware average
bogdanm	82:6473597d706e	1298	* function is enabled, that is, AVGE=1, after initiating a conversion.
bogdanm	82:6473597d706e	1299	*/
bogdanm	82:6473597d706e	1300	//@{
bogdanm	82:6473597d706e	1301	#define BP_ADC_SC3_ADCO (3U) //!< Bit position for ADC_SC3_ADCO.
bogdanm	82:6473597d706e	1302	#define BM_ADC_SC3_ADCO (0x00000008U) //!< Bit mask for ADC_SC3_ADCO.
bogdanm	82:6473597d706e	1303	#define BS_ADC_SC3_ADCO (1U) //!< Bit field size in bits for ADC_SC3_ADCO.
bogdanm	82:6473597d706e	1304
bogdanm	82:6473597d706e	1305	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1306	//! @brief Read current value of the ADC_SC3_ADCO field.
bogdanm	82:6473597d706e	1307	#define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
bogdanm	82:6473597d706e	1308	#endif
bogdanm	82:6473597d706e	1309
bogdanm	82:6473597d706e	1310	//! @brief Format value for bitfield ADC_SC3_ADCO.
bogdanm	82:6473597d706e	1311	#define BF_ADC_SC3_ADCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_ADCO), uint32_t) & BM_ADC_SC3_ADCO)
bogdanm	82:6473597d706e	1312
bogdanm	82:6473597d706e	1313	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1314	//! @brief Set the ADCO field to a new value.
bogdanm	82:6473597d706e	1315	#define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
bogdanm	82:6473597d706e	1316	#endif
bogdanm	82:6473597d706e	1317	//@}
bogdanm	82:6473597d706e	1318
bogdanm	82:6473597d706e	1319	/*!
bogdanm	82:6473597d706e	1320	* @name Register ADC_SC3, field CALF[6] (RO)
bogdanm	82:6473597d706e	1321	*
bogdanm	82:6473597d706e	1322	* Displays the result of the calibration sequence. The calibration sequence
bogdanm	82:6473597d706e	1323	* will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
bogdanm	82:6473597d706e	1324	* entered before the calibration sequence completes. Writing 1 to CALF clears it.
bogdanm	82:6473597d706e	1325	*
bogdanm	82:6473597d706e	1326	* Values:
bogdanm	82:6473597d706e	1327	* - 0 - Calibration completed normally.
bogdanm	82:6473597d706e	1328	* - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
bogdanm	82:6473597d706e	1329	*/
bogdanm	82:6473597d706e	1330	//@{
bogdanm	82:6473597d706e	1331	#define BP_ADC_SC3_CALF (6U) //!< Bit position for ADC_SC3_CALF.
bogdanm	82:6473597d706e	1332	#define BM_ADC_SC3_CALF (0x00000040U) //!< Bit mask for ADC_SC3_CALF.
bogdanm	82:6473597d706e	1333	#define BS_ADC_SC3_CALF (1U) //!< Bit field size in bits for ADC_SC3_CALF.
bogdanm	82:6473597d706e	1334
bogdanm	82:6473597d706e	1335	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1336	//! @brief Read current value of the ADC_SC3_CALF field.
bogdanm	82:6473597d706e	1337	#define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
bogdanm	82:6473597d706e	1338	#endif
bogdanm	82:6473597d706e	1339	//@}
bogdanm	82:6473597d706e	1340
bogdanm	82:6473597d706e	1341	/*!
bogdanm	82:6473597d706e	1342	* @name Register ADC_SC3, field CAL[7] (RW)
bogdanm	82:6473597d706e	1343	*
bogdanm	82:6473597d706e	1344	* Begins the calibration sequence when set. This field stays set while the
bogdanm	82:6473597d706e	1345	* calibration is in progress and is cleared when the calibration sequence is
bogdanm	82:6473597d706e	1346	* completed. CALF must be checked to determine the result of the calibration sequence.
bogdanm	82:6473597d706e	1347	* Once started, the calibration routine cannot be interrupted by writes to the
bogdanm	82:6473597d706e	1348	* ADC registers or the results will be invalid and CALF will set. Setting CAL
bogdanm	82:6473597d706e	1349	* will abort any current conversion.
bogdanm	82:6473597d706e	1350	*/
bogdanm	82:6473597d706e	1351	//@{
bogdanm	82:6473597d706e	1352	#define BP_ADC_SC3_CAL (7U) //!< Bit position for ADC_SC3_CAL.
bogdanm	82:6473597d706e	1353	#define BM_ADC_SC3_CAL (0x00000080U) //!< Bit mask for ADC_SC3_CAL.
bogdanm	82:6473597d706e	1354	#define BS_ADC_SC3_CAL (1U) //!< Bit field size in bits for ADC_SC3_CAL.
bogdanm	82:6473597d706e	1355
bogdanm	82:6473597d706e	1356	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1357	//! @brief Read current value of the ADC_SC3_CAL field.
bogdanm	82:6473597d706e	1358	#define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
bogdanm	82:6473597d706e	1359	#endif
bogdanm	82:6473597d706e	1360
bogdanm	82:6473597d706e	1361	//! @brief Format value for bitfield ADC_SC3_CAL.
bogdanm	82:6473597d706e	1362	#define BF_ADC_SC3_CAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_CAL), uint32_t) & BM_ADC_SC3_CAL)
bogdanm	82:6473597d706e	1363
bogdanm	82:6473597d706e	1364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1365	//! @brief Set the CAL field to a new value.
bogdanm	82:6473597d706e	1366	#define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
bogdanm	82:6473597d706e	1367	#endif
bogdanm	82:6473597d706e	1368	//@}
bogdanm	82:6473597d706e	1369
bogdanm	82:6473597d706e	1370	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1371	// HW_ADC_OFS - ADC Offset Correction Register
bogdanm	82:6473597d706e	1372	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1373
bogdanm	82:6473597d706e	1374	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1375	/*!
bogdanm	82:6473597d706e	1376	* @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
bogdanm	82:6473597d706e	1377	*
bogdanm	82:6473597d706e	1378	* Reset value: 0x00000004U
bogdanm	82:6473597d706e	1379	*
bogdanm	82:6473597d706e	1380	* The ADC Offset Correction Register (OFS) contains the user-selected or
bogdanm	82:6473597d706e	1381	* calibration-generated offset error correction value. This register is a 2's
bogdanm	82:6473597d706e	1382	* complement, left-justified, 16-bit value . The value in OFS is subtracted from the
bogdanm	82:6473597d706e	1383	* conversion and the result is transferred into the result registers, Rn. If the
bogdanm	82:6473597d706e	1384	* result is greater than the maximum or less than the minimum result value, it is
bogdanm	82:6473597d706e	1385	* forced to the appropriate limit for the current mode of operation.
bogdanm	82:6473597d706e	1386	*/
bogdanm	82:6473597d706e	1387	typedef union _hw_adc_ofs
bogdanm	82:6473597d706e	1388	{
bogdanm	82:6473597d706e	1389	uint32_t U;
bogdanm	82:6473597d706e	1390	struct _hw_adc_ofs_bitfields
bogdanm	82:6473597d706e	1391	{
bogdanm	82:6473597d706e	1392	uint32_t OFS : 16; //!< [15:0] Offset Error Correction Value
bogdanm	82:6473597d706e	1393	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1394	} B;
bogdanm	82:6473597d706e	1395	} hw_adc_ofs_t;
bogdanm	82:6473597d706e	1396	#endif
bogdanm	82:6473597d706e	1397
bogdanm	82:6473597d706e	1398	/*!
bogdanm	82:6473597d706e	1399	* @name Constants and macros for entire ADC_OFS register
bogdanm	82:6473597d706e	1400	*/
bogdanm	82:6473597d706e	1401	//@{
bogdanm	82:6473597d706e	1402	#define HW_ADC_OFS_ADDR(x) (REGS_ADC_BASE(x) + 0x28U)
bogdanm	82:6473597d706e	1403
bogdanm	82:6473597d706e	1404	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1405	#define HW_ADC_OFS(x) ((__IO hw_adc_ofs_t ) HW_ADC_OFS_ADDR(x))
bogdanm	82:6473597d706e	1406	#define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
bogdanm	82:6473597d706e	1407	#define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
bogdanm	82:6473597d706e	1408	#define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) \| (v)))
bogdanm	82:6473597d706e	1409	#define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1410	#define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1411	#endif
bogdanm	82:6473597d706e	1412	//@}
bogdanm	82:6473597d706e	1413
bogdanm	82:6473597d706e	1414	/*
bogdanm	82:6473597d706e	1415	* Constants & macros for individual ADC_OFS bitfields
bogdanm	82:6473597d706e	1416	*/
bogdanm	82:6473597d706e	1417
bogdanm	82:6473597d706e	1418	/*!
bogdanm	82:6473597d706e	1419	* @name Register ADC_OFS, field OFS[15:0] (RW)
bogdanm	82:6473597d706e	1420	*/
bogdanm	82:6473597d706e	1421	//@{
bogdanm	82:6473597d706e	1422	#define BP_ADC_OFS_OFS (0U) //!< Bit position for ADC_OFS_OFS.
bogdanm	82:6473597d706e	1423	#define BM_ADC_OFS_OFS (0x0000FFFFU) //!< Bit mask for ADC_OFS_OFS.
bogdanm	82:6473597d706e	1424	#define BS_ADC_OFS_OFS (16U) //!< Bit field size in bits for ADC_OFS_OFS.
bogdanm	82:6473597d706e	1425
bogdanm	82:6473597d706e	1426	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1427	//! @brief Read current value of the ADC_OFS_OFS field.
bogdanm	82:6473597d706e	1428	#define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
bogdanm	82:6473597d706e	1429	#endif
bogdanm	82:6473597d706e	1430
bogdanm	82:6473597d706e	1431	//! @brief Format value for bitfield ADC_OFS_OFS.
bogdanm	82:6473597d706e	1432	#define BF_ADC_OFS_OFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_OFS_OFS), uint32_t) & BM_ADC_OFS_OFS)
bogdanm	82:6473597d706e	1433
bogdanm	82:6473597d706e	1434	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1435	//! @brief Set the OFS field to a new value.
bogdanm	82:6473597d706e	1436	#define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) \| BF_ADC_OFS_OFS(v)))
bogdanm	82:6473597d706e	1437	#endif
bogdanm	82:6473597d706e	1438	//@}
bogdanm	82:6473597d706e	1439
bogdanm	82:6473597d706e	1440	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1441	// HW_ADC_PG - ADC Plus-Side Gain Register
bogdanm	82:6473597d706e	1442	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1443
bogdanm	82:6473597d706e	1444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1445	/*!
bogdanm	82:6473597d706e	1446	* @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
bogdanm	82:6473597d706e	1447	*
bogdanm	82:6473597d706e	1448	* Reset value: 0x00008200U
bogdanm	82:6473597d706e	1449	*
bogdanm	82:6473597d706e	1450	* The Plus-Side Gain Register (PG) contains the gain error correction for the
bogdanm	82:6473597d706e	1451	* plus-side input in differential mode or the overall conversion in single-ended
bogdanm	82:6473597d706e	1452	* mode. PG, a 16-bit real number in binary format, is the gain adjustment
bogdanm	82:6473597d706e	1453	* factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
bogdanm	82:6473597d706e	1454	* written by the user with the value described in the calibration procedure.
bogdanm	82:6473597d706e	1455	* Otherwise, the gain error specifications may not be met.
bogdanm	82:6473597d706e	1456	*/
bogdanm	82:6473597d706e	1457	typedef union _hw_adc_pg
bogdanm	82:6473597d706e	1458	{
bogdanm	82:6473597d706e	1459	uint32_t U;
bogdanm	82:6473597d706e	1460	struct _hw_adc_pg_bitfields
bogdanm	82:6473597d706e	1461	{
bogdanm	82:6473597d706e	1462	uint32_t PG : 16; //!< [15:0] Plus-Side Gain
bogdanm	82:6473597d706e	1463	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1464	} B;
bogdanm	82:6473597d706e	1465	} hw_adc_pg_t;
bogdanm	82:6473597d706e	1466	#endif
bogdanm	82:6473597d706e	1467
bogdanm	82:6473597d706e	1468	/*!
bogdanm	82:6473597d706e	1469	* @name Constants and macros for entire ADC_PG register
bogdanm	82:6473597d706e	1470	*/
bogdanm	82:6473597d706e	1471	//@{
bogdanm	82:6473597d706e	1472	#define HW_ADC_PG_ADDR(x) (REGS_ADC_BASE(x) + 0x2CU)
bogdanm	82:6473597d706e	1473
bogdanm	82:6473597d706e	1474	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1475	#define HW_ADC_PG(x) ((__IO hw_adc_pg_t ) HW_ADC_PG_ADDR(x))
bogdanm	82:6473597d706e	1476	#define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
bogdanm	82:6473597d706e	1477	#define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
bogdanm	82:6473597d706e	1478	#define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) \| (v)))
bogdanm	82:6473597d706e	1479	#define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1480	#define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1481	#endif
bogdanm	82:6473597d706e	1482	//@}
bogdanm	82:6473597d706e	1483
bogdanm	82:6473597d706e	1484	/*
bogdanm	82:6473597d706e	1485	* Constants & macros for individual ADC_PG bitfields
bogdanm	82:6473597d706e	1486	*/
bogdanm	82:6473597d706e	1487
bogdanm	82:6473597d706e	1488	/*!
bogdanm	82:6473597d706e	1489	* @name Register ADC_PG, field PG[15:0] (RW)
bogdanm	82:6473597d706e	1490	*/
bogdanm	82:6473597d706e	1491	//@{
bogdanm	82:6473597d706e	1492	#define BP_ADC_PG_PG (0U) //!< Bit position for ADC_PG_PG.
bogdanm	82:6473597d706e	1493	#define BM_ADC_PG_PG (0x0000FFFFU) //!< Bit mask for ADC_PG_PG.
bogdanm	82:6473597d706e	1494	#define BS_ADC_PG_PG (16U) //!< Bit field size in bits for ADC_PG_PG.
bogdanm	82:6473597d706e	1495
bogdanm	82:6473597d706e	1496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1497	//! @brief Read current value of the ADC_PG_PG field.
bogdanm	82:6473597d706e	1498	#define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
bogdanm	82:6473597d706e	1499	#endif
bogdanm	82:6473597d706e	1500
bogdanm	82:6473597d706e	1501	//! @brief Format value for bitfield ADC_PG_PG.
bogdanm	82:6473597d706e	1502	#define BF_ADC_PG_PG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_PG_PG), uint32_t) & BM_ADC_PG_PG)
bogdanm	82:6473597d706e	1503
bogdanm	82:6473597d706e	1504	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1505	//! @brief Set the PG field to a new value.
bogdanm	82:6473597d706e	1506	#define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) \| BF_ADC_PG_PG(v)))
bogdanm	82:6473597d706e	1507	#endif
bogdanm	82:6473597d706e	1508	//@}
bogdanm	82:6473597d706e	1509
bogdanm	82:6473597d706e	1510	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1511	// HW_ADC_MG - ADC Minus-Side Gain Register
bogdanm	82:6473597d706e	1512	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1513
bogdanm	82:6473597d706e	1514	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1515	/*!
bogdanm	82:6473597d706e	1516	* @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
bogdanm	82:6473597d706e	1517	*
bogdanm	82:6473597d706e	1518	* Reset value: 0x00008200U
bogdanm	82:6473597d706e	1519	*
bogdanm	82:6473597d706e	1520	* The Minus-Side Gain Register (MG) contains the gain error correction for the
bogdanm	82:6473597d706e	1521	* minus-side input in differential mode. This register is ignored in
bogdanm	82:6473597d706e	1522	* single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
bogdanm	82:6473597d706e	1523	* factor, with the radix point fixed between ADMG15 and ADMG14. This register must
bogdanm	82:6473597d706e	1524	* be written by the user with the value described in the calibration procedure.
bogdanm	82:6473597d706e	1525	* Otherwise, the gain error specifications may not be met.
bogdanm	82:6473597d706e	1526	*/
bogdanm	82:6473597d706e	1527	typedef union _hw_adc_mg
bogdanm	82:6473597d706e	1528	{
bogdanm	82:6473597d706e	1529	uint32_t U;
bogdanm	82:6473597d706e	1530	struct _hw_adc_mg_bitfields
bogdanm	82:6473597d706e	1531	{
bogdanm	82:6473597d706e	1532	uint32_t MG : 16; //!< [15:0] Minus-Side Gain
bogdanm	82:6473597d706e	1533	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1534	} B;
bogdanm	82:6473597d706e	1535	} hw_adc_mg_t;
bogdanm	82:6473597d706e	1536	#endif
bogdanm	82:6473597d706e	1537
bogdanm	82:6473597d706e	1538	/*!
bogdanm	82:6473597d706e	1539	* @name Constants and macros for entire ADC_MG register
bogdanm	82:6473597d706e	1540	*/
bogdanm	82:6473597d706e	1541	//@{
bogdanm	82:6473597d706e	1542	#define HW_ADC_MG_ADDR(x) (REGS_ADC_BASE(x) + 0x30U)
bogdanm	82:6473597d706e	1543
bogdanm	82:6473597d706e	1544	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1545	#define HW_ADC_MG(x) ((__IO hw_adc_mg_t ) HW_ADC_MG_ADDR(x))
bogdanm	82:6473597d706e	1546	#define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
bogdanm	82:6473597d706e	1547	#define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
bogdanm	82:6473597d706e	1548	#define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) \| (v)))
bogdanm	82:6473597d706e	1549	#define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1550	#define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1551	#endif
bogdanm	82:6473597d706e	1552	//@}
bogdanm	82:6473597d706e	1553
bogdanm	82:6473597d706e	1554	/*
bogdanm	82:6473597d706e	1555	* Constants & macros for individual ADC_MG bitfields
bogdanm	82:6473597d706e	1556	*/
bogdanm	82:6473597d706e	1557
bogdanm	82:6473597d706e	1558	/*!
bogdanm	82:6473597d706e	1559	* @name Register ADC_MG, field MG[15:0] (RW)
bogdanm	82:6473597d706e	1560	*/
bogdanm	82:6473597d706e	1561	//@{
bogdanm	82:6473597d706e	1562	#define BP_ADC_MG_MG (0U) //!< Bit position for ADC_MG_MG.
bogdanm	82:6473597d706e	1563	#define BM_ADC_MG_MG (0x0000FFFFU) //!< Bit mask for ADC_MG_MG.
bogdanm	82:6473597d706e	1564	#define BS_ADC_MG_MG (16U) //!< Bit field size in bits for ADC_MG_MG.
bogdanm	82:6473597d706e	1565
bogdanm	82:6473597d706e	1566	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1567	//! @brief Read current value of the ADC_MG_MG field.
bogdanm	82:6473597d706e	1568	#define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
bogdanm	82:6473597d706e	1569	#endif
bogdanm	82:6473597d706e	1570
bogdanm	82:6473597d706e	1571	//! @brief Format value for bitfield ADC_MG_MG.
bogdanm	82:6473597d706e	1572	#define BF_ADC_MG_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_MG_MG), uint32_t) & BM_ADC_MG_MG)
bogdanm	82:6473597d706e	1573
bogdanm	82:6473597d706e	1574	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1575	//! @brief Set the MG field to a new value.
bogdanm	82:6473597d706e	1576	#define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) \| BF_ADC_MG_MG(v)))
bogdanm	82:6473597d706e	1577	#endif
bogdanm	82:6473597d706e	1578	//@}
bogdanm	82:6473597d706e	1579
bogdanm	82:6473597d706e	1580	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1581	// HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1582	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1583
bogdanm	82:6473597d706e	1584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1585	/*!
bogdanm	82:6473597d706e	1586	* @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1587	*
bogdanm	82:6473597d706e	1588	* Reset value: 0x0000000AU
bogdanm	82:6473597d706e	1589	*
bogdanm	82:6473597d706e	1590	* The Plus-Side General Calibration Value Registers (CLPx) contain calibration
bogdanm	82:6473597d706e	1591	* information that is generated by the calibration function. These registers
bogdanm	82:6473597d706e	1592	* contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
bogdanm	82:6473597d706e	1593	* CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
bogdanm	82:6473597d706e	1594	* when the self-calibration sequence is done, that is, CAL is cleared. If these
bogdanm	82:6473597d706e	1595	* registers are written by the user after calibration, the linearity error
bogdanm	82:6473597d706e	1596	* specifications may not be met.
bogdanm	82:6473597d706e	1597	*/
bogdanm	82:6473597d706e	1598	typedef union _hw_adc_clpd
bogdanm	82:6473597d706e	1599	{
bogdanm	82:6473597d706e	1600	uint32_t U;
bogdanm	82:6473597d706e	1601	struct _hw_adc_clpd_bitfields
bogdanm	82:6473597d706e	1602	{
bogdanm	82:6473597d706e	1603	uint32_t CLPD : 6; //!< [5:0]
bogdanm	82:6473597d706e	1604	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	1605	} B;
bogdanm	82:6473597d706e	1606	} hw_adc_clpd_t;
bogdanm	82:6473597d706e	1607	#endif
bogdanm	82:6473597d706e	1608
bogdanm	82:6473597d706e	1609	/*!
bogdanm	82:6473597d706e	1610	* @name Constants and macros for entire ADC_CLPD register
bogdanm	82:6473597d706e	1611	*/
bogdanm	82:6473597d706e	1612	//@{
bogdanm	82:6473597d706e	1613	#define HW_ADC_CLPD_ADDR(x) (REGS_ADC_BASE(x) + 0x34U)
bogdanm	82:6473597d706e	1614
bogdanm	82:6473597d706e	1615	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1616	#define HW_ADC_CLPD(x) ((__IO hw_adc_clpd_t ) HW_ADC_CLPD_ADDR(x))
bogdanm	82:6473597d706e	1617	#define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
bogdanm	82:6473597d706e	1618	#define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
bogdanm	82:6473597d706e	1619	#define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) \| (v)))
bogdanm	82:6473597d706e	1620	#define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1621	#define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1622	#endif
bogdanm	82:6473597d706e	1623	//@}
bogdanm	82:6473597d706e	1624
bogdanm	82:6473597d706e	1625	/*
bogdanm	82:6473597d706e	1626	* Constants & macros for individual ADC_CLPD bitfields
bogdanm	82:6473597d706e	1627	*/
bogdanm	82:6473597d706e	1628
bogdanm	82:6473597d706e	1629	/*!
bogdanm	82:6473597d706e	1630	* @name Register ADC_CLPD, field CLPD[5:0] (RW)
bogdanm	82:6473597d706e	1631	*
bogdanm	82:6473597d706e	1632	* Calibration Value
bogdanm	82:6473597d706e	1633	*/
bogdanm	82:6473597d706e	1634	//@{
bogdanm	82:6473597d706e	1635	#define BP_ADC_CLPD_CLPD (0U) //!< Bit position for ADC_CLPD_CLPD.
bogdanm	82:6473597d706e	1636	#define BM_ADC_CLPD_CLPD (0x0000003FU) //!< Bit mask for ADC_CLPD_CLPD.
bogdanm	82:6473597d706e	1637	#define BS_ADC_CLPD_CLPD (6U) //!< Bit field size in bits for ADC_CLPD_CLPD.
bogdanm	82:6473597d706e	1638
bogdanm	82:6473597d706e	1639	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1640	//! @brief Read current value of the ADC_CLPD_CLPD field.
bogdanm	82:6473597d706e	1641	#define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
bogdanm	82:6473597d706e	1642	#endif
bogdanm	82:6473597d706e	1643
bogdanm	82:6473597d706e	1644	//! @brief Format value for bitfield ADC_CLPD_CLPD.
bogdanm	82:6473597d706e	1645	#define BF_ADC_CLPD_CLPD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPD_CLPD), uint32_t) & BM_ADC_CLPD_CLPD)
bogdanm	82:6473597d706e	1646
bogdanm	82:6473597d706e	1647	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1648	//! @brief Set the CLPD field to a new value.
bogdanm	82:6473597d706e	1649	#define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) \| BF_ADC_CLPD_CLPD(v)))
bogdanm	82:6473597d706e	1650	#endif
bogdanm	82:6473597d706e	1651	//@}
bogdanm	82:6473597d706e	1652
bogdanm	82:6473597d706e	1653	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1654	// HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1655	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1656
bogdanm	82:6473597d706e	1657	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1658	/*!
bogdanm	82:6473597d706e	1659	* @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1660	*
bogdanm	82:6473597d706e	1661	* Reset value: 0x00000020U
bogdanm	82:6473597d706e	1662	*
bogdanm	82:6473597d706e	1663	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1664	*/
bogdanm	82:6473597d706e	1665	typedef union _hw_adc_clps
bogdanm	82:6473597d706e	1666	{
bogdanm	82:6473597d706e	1667	uint32_t U;
bogdanm	82:6473597d706e	1668	struct _hw_adc_clps_bitfields
bogdanm	82:6473597d706e	1669	{
bogdanm	82:6473597d706e	1670	uint32_t CLPS : 6; //!< [5:0]
bogdanm	82:6473597d706e	1671	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	1672	} B;
bogdanm	82:6473597d706e	1673	} hw_adc_clps_t;
bogdanm	82:6473597d706e	1674	#endif
bogdanm	82:6473597d706e	1675
bogdanm	82:6473597d706e	1676	/*!
bogdanm	82:6473597d706e	1677	* @name Constants and macros for entire ADC_CLPS register
bogdanm	82:6473597d706e	1678	*/
bogdanm	82:6473597d706e	1679	//@{
bogdanm	82:6473597d706e	1680	#define HW_ADC_CLPS_ADDR(x) (REGS_ADC_BASE(x) + 0x38U)
bogdanm	82:6473597d706e	1681
bogdanm	82:6473597d706e	1682	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1683	#define HW_ADC_CLPS(x) ((__IO hw_adc_clps_t ) HW_ADC_CLPS_ADDR(x))
bogdanm	82:6473597d706e	1684	#define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
bogdanm	82:6473597d706e	1685	#define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
bogdanm	82:6473597d706e	1686	#define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) \| (v)))
bogdanm	82:6473597d706e	1687	#define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1688	#define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1689	#endif
bogdanm	82:6473597d706e	1690	//@}
bogdanm	82:6473597d706e	1691
bogdanm	82:6473597d706e	1692	/*
bogdanm	82:6473597d706e	1693	* Constants & macros for individual ADC_CLPS bitfields
bogdanm	82:6473597d706e	1694	*/
bogdanm	82:6473597d706e	1695
bogdanm	82:6473597d706e	1696	/*!
bogdanm	82:6473597d706e	1697	* @name Register ADC_CLPS, field CLPS[5:0] (RW)
bogdanm	82:6473597d706e	1698	*
bogdanm	82:6473597d706e	1699	* Calibration Value
bogdanm	82:6473597d706e	1700	*/
bogdanm	82:6473597d706e	1701	//@{
bogdanm	82:6473597d706e	1702	#define BP_ADC_CLPS_CLPS (0U) //!< Bit position for ADC_CLPS_CLPS.
bogdanm	82:6473597d706e	1703	#define BM_ADC_CLPS_CLPS (0x0000003FU) //!< Bit mask for ADC_CLPS_CLPS.
bogdanm	82:6473597d706e	1704	#define BS_ADC_CLPS_CLPS (6U) //!< Bit field size in bits for ADC_CLPS_CLPS.
bogdanm	82:6473597d706e	1705
bogdanm	82:6473597d706e	1706	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1707	//! @brief Read current value of the ADC_CLPS_CLPS field.
bogdanm	82:6473597d706e	1708	#define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
bogdanm	82:6473597d706e	1709	#endif
bogdanm	82:6473597d706e	1710
bogdanm	82:6473597d706e	1711	//! @brief Format value for bitfield ADC_CLPS_CLPS.
bogdanm	82:6473597d706e	1712	#define BF_ADC_CLPS_CLPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPS_CLPS), uint32_t) & BM_ADC_CLPS_CLPS)
bogdanm	82:6473597d706e	1713
bogdanm	82:6473597d706e	1714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1715	//! @brief Set the CLPS field to a new value.
bogdanm	82:6473597d706e	1716	#define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) \| BF_ADC_CLPS_CLPS(v)))
bogdanm	82:6473597d706e	1717	#endif
bogdanm	82:6473597d706e	1718	//@}
bogdanm	82:6473597d706e	1719
bogdanm	82:6473597d706e	1720	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1721	// HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1722	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1723
bogdanm	82:6473597d706e	1724	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1725	/*!
bogdanm	82:6473597d706e	1726	* @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1727	*
bogdanm	82:6473597d706e	1728	* Reset value: 0x00000200U
bogdanm	82:6473597d706e	1729	*
bogdanm	82:6473597d706e	1730	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1731	*/
bogdanm	82:6473597d706e	1732	typedef union _hw_adc_clp4
bogdanm	82:6473597d706e	1733	{
bogdanm	82:6473597d706e	1734	uint32_t U;
bogdanm	82:6473597d706e	1735	struct _hw_adc_clp4_bitfields
bogdanm	82:6473597d706e	1736	{
bogdanm	82:6473597d706e	1737	uint32_t CLP4 : 10; //!< [9:0]
bogdanm	82:6473597d706e	1738	uint32_t RESERVED0 : 22; //!< [31:10]
bogdanm	82:6473597d706e	1739	} B;
bogdanm	82:6473597d706e	1740	} hw_adc_clp4_t;
bogdanm	82:6473597d706e	1741	#endif
bogdanm	82:6473597d706e	1742
bogdanm	82:6473597d706e	1743	/*!
bogdanm	82:6473597d706e	1744	* @name Constants and macros for entire ADC_CLP4 register
bogdanm	82:6473597d706e	1745	*/
bogdanm	82:6473597d706e	1746	//@{
bogdanm	82:6473597d706e	1747	#define HW_ADC_CLP4_ADDR(x) (REGS_ADC_BASE(x) + 0x3CU)
bogdanm	82:6473597d706e	1748
bogdanm	82:6473597d706e	1749	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1750	#define HW_ADC_CLP4(x) ((__IO hw_adc_clp4_t ) HW_ADC_CLP4_ADDR(x))
bogdanm	82:6473597d706e	1751	#define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
bogdanm	82:6473597d706e	1752	#define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
bogdanm	82:6473597d706e	1753	#define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) \| (v)))
bogdanm	82:6473597d706e	1754	#define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1755	#define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1756	#endif
bogdanm	82:6473597d706e	1757	//@}
bogdanm	82:6473597d706e	1758
bogdanm	82:6473597d706e	1759	/*
bogdanm	82:6473597d706e	1760	* Constants & macros for individual ADC_CLP4 bitfields
bogdanm	82:6473597d706e	1761	*/
bogdanm	82:6473597d706e	1762
bogdanm	82:6473597d706e	1763	/*!
bogdanm	82:6473597d706e	1764	* @name Register ADC_CLP4, field CLP4[9:0] (RW)
bogdanm	82:6473597d706e	1765	*
bogdanm	82:6473597d706e	1766	* Calibration Value
bogdanm	82:6473597d706e	1767	*/
bogdanm	82:6473597d706e	1768	//@{
bogdanm	82:6473597d706e	1769	#define BP_ADC_CLP4_CLP4 (0U) //!< Bit position for ADC_CLP4_CLP4.
bogdanm	82:6473597d706e	1770	#define BM_ADC_CLP4_CLP4 (0x000003FFU) //!< Bit mask for ADC_CLP4_CLP4.
bogdanm	82:6473597d706e	1771	#define BS_ADC_CLP4_CLP4 (10U) //!< Bit field size in bits for ADC_CLP4_CLP4.
bogdanm	82:6473597d706e	1772
bogdanm	82:6473597d706e	1773	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1774	//! @brief Read current value of the ADC_CLP4_CLP4 field.
bogdanm	82:6473597d706e	1775	#define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
bogdanm	82:6473597d706e	1776	#endif
bogdanm	82:6473597d706e	1777
bogdanm	82:6473597d706e	1778	//! @brief Format value for bitfield ADC_CLP4_CLP4.
bogdanm	82:6473597d706e	1779	#define BF_ADC_CLP4_CLP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP4_CLP4), uint32_t) & BM_ADC_CLP4_CLP4)
bogdanm	82:6473597d706e	1780
bogdanm	82:6473597d706e	1781	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1782	//! @brief Set the CLP4 field to a new value.
bogdanm	82:6473597d706e	1783	#define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) \| BF_ADC_CLP4_CLP4(v)))
bogdanm	82:6473597d706e	1784	#endif
bogdanm	82:6473597d706e	1785	//@}
bogdanm	82:6473597d706e	1786
bogdanm	82:6473597d706e	1787	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1788	// HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1789	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1790
bogdanm	82:6473597d706e	1791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1792	/*!
bogdanm	82:6473597d706e	1793	* @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1794	*
bogdanm	82:6473597d706e	1795	* Reset value: 0x00000100U
bogdanm	82:6473597d706e	1796	*
bogdanm	82:6473597d706e	1797	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1798	*/
bogdanm	82:6473597d706e	1799	typedef union _hw_adc_clp3
bogdanm	82:6473597d706e	1800	{
bogdanm	82:6473597d706e	1801	uint32_t U;
bogdanm	82:6473597d706e	1802	struct _hw_adc_clp3_bitfields
bogdanm	82:6473597d706e	1803	{
bogdanm	82:6473597d706e	1804	uint32_t CLP3 : 9; //!< [8:0]
bogdanm	82:6473597d706e	1805	uint32_t RESERVED0 : 23; //!< [31:9]
bogdanm	82:6473597d706e	1806	} B;
bogdanm	82:6473597d706e	1807	} hw_adc_clp3_t;
bogdanm	82:6473597d706e	1808	#endif
bogdanm	82:6473597d706e	1809
bogdanm	82:6473597d706e	1810	/*!
bogdanm	82:6473597d706e	1811	* @name Constants and macros for entire ADC_CLP3 register
bogdanm	82:6473597d706e	1812	*/
bogdanm	82:6473597d706e	1813	//@{
bogdanm	82:6473597d706e	1814	#define HW_ADC_CLP3_ADDR(x) (REGS_ADC_BASE(x) + 0x40U)
bogdanm	82:6473597d706e	1815
bogdanm	82:6473597d706e	1816	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1817	#define HW_ADC_CLP3(x) ((__IO hw_adc_clp3_t ) HW_ADC_CLP3_ADDR(x))
bogdanm	82:6473597d706e	1818	#define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
bogdanm	82:6473597d706e	1819	#define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
bogdanm	82:6473597d706e	1820	#define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) \| (v)))
bogdanm	82:6473597d706e	1821	#define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1822	#define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1823	#endif
bogdanm	82:6473597d706e	1824	//@}
bogdanm	82:6473597d706e	1825
bogdanm	82:6473597d706e	1826	/*
bogdanm	82:6473597d706e	1827	* Constants & macros for individual ADC_CLP3 bitfields
bogdanm	82:6473597d706e	1828	*/
bogdanm	82:6473597d706e	1829
bogdanm	82:6473597d706e	1830	/*!
bogdanm	82:6473597d706e	1831	* @name Register ADC_CLP3, field CLP3[8:0] (RW)
bogdanm	82:6473597d706e	1832	*
bogdanm	82:6473597d706e	1833	* Calibration Value
bogdanm	82:6473597d706e	1834	*/
bogdanm	82:6473597d706e	1835	//@{
bogdanm	82:6473597d706e	1836	#define BP_ADC_CLP3_CLP3 (0U) //!< Bit position for ADC_CLP3_CLP3.
bogdanm	82:6473597d706e	1837	#define BM_ADC_CLP3_CLP3 (0x000001FFU) //!< Bit mask for ADC_CLP3_CLP3.
bogdanm	82:6473597d706e	1838	#define BS_ADC_CLP3_CLP3 (9U) //!< Bit field size in bits for ADC_CLP3_CLP3.
bogdanm	82:6473597d706e	1839
bogdanm	82:6473597d706e	1840	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1841	//! @brief Read current value of the ADC_CLP3_CLP3 field.
bogdanm	82:6473597d706e	1842	#define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
bogdanm	82:6473597d706e	1843	#endif
bogdanm	82:6473597d706e	1844
bogdanm	82:6473597d706e	1845	//! @brief Format value for bitfield ADC_CLP3_CLP3.
bogdanm	82:6473597d706e	1846	#define BF_ADC_CLP3_CLP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP3_CLP3), uint32_t) & BM_ADC_CLP3_CLP3)
bogdanm	82:6473597d706e	1847
bogdanm	82:6473597d706e	1848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1849	//! @brief Set the CLP3 field to a new value.
bogdanm	82:6473597d706e	1850	#define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) \| BF_ADC_CLP3_CLP3(v)))
bogdanm	82:6473597d706e	1851	#endif
bogdanm	82:6473597d706e	1852	//@}
bogdanm	82:6473597d706e	1853
bogdanm	82:6473597d706e	1854	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1855	// HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1856	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1857
bogdanm	82:6473597d706e	1858	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1859	/*!
bogdanm	82:6473597d706e	1860	* @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1861	*
bogdanm	82:6473597d706e	1862	* Reset value: 0x00000080U
bogdanm	82:6473597d706e	1863	*
bogdanm	82:6473597d706e	1864	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1865	*/
bogdanm	82:6473597d706e	1866	typedef union _hw_adc_clp2
bogdanm	82:6473597d706e	1867	{
bogdanm	82:6473597d706e	1868	uint32_t U;
bogdanm	82:6473597d706e	1869	struct _hw_adc_clp2_bitfields
bogdanm	82:6473597d706e	1870	{
bogdanm	82:6473597d706e	1871	uint32_t CLP2 : 8; //!< [7:0]
bogdanm	82:6473597d706e	1872	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1873	} B;
bogdanm	82:6473597d706e	1874	} hw_adc_clp2_t;
bogdanm	82:6473597d706e	1875	#endif
bogdanm	82:6473597d706e	1876
bogdanm	82:6473597d706e	1877	/*!
bogdanm	82:6473597d706e	1878	* @name Constants and macros for entire ADC_CLP2 register
bogdanm	82:6473597d706e	1879	*/
bogdanm	82:6473597d706e	1880	//@{
bogdanm	82:6473597d706e	1881	#define HW_ADC_CLP2_ADDR(x) (REGS_ADC_BASE(x) + 0x44U)
bogdanm	82:6473597d706e	1882
bogdanm	82:6473597d706e	1883	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1884	#define HW_ADC_CLP2(x) ((__IO hw_adc_clp2_t ) HW_ADC_CLP2_ADDR(x))
bogdanm	82:6473597d706e	1885	#define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
bogdanm	82:6473597d706e	1886	#define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
bogdanm	82:6473597d706e	1887	#define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) \| (v)))
bogdanm	82:6473597d706e	1888	#define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1889	#define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1890	#endif
bogdanm	82:6473597d706e	1891	//@}
bogdanm	82:6473597d706e	1892
bogdanm	82:6473597d706e	1893	/*
bogdanm	82:6473597d706e	1894	* Constants & macros for individual ADC_CLP2 bitfields
bogdanm	82:6473597d706e	1895	*/
bogdanm	82:6473597d706e	1896
bogdanm	82:6473597d706e	1897	/*!
bogdanm	82:6473597d706e	1898	* @name Register ADC_CLP2, field CLP2[7:0] (RW)
bogdanm	82:6473597d706e	1899	*
bogdanm	82:6473597d706e	1900	* Calibration Value
bogdanm	82:6473597d706e	1901	*/
bogdanm	82:6473597d706e	1902	//@{
bogdanm	82:6473597d706e	1903	#define BP_ADC_CLP2_CLP2 (0U) //!< Bit position for ADC_CLP2_CLP2.
bogdanm	82:6473597d706e	1904	#define BM_ADC_CLP2_CLP2 (0x000000FFU) //!< Bit mask for ADC_CLP2_CLP2.
bogdanm	82:6473597d706e	1905	#define BS_ADC_CLP2_CLP2 (8U) //!< Bit field size in bits for ADC_CLP2_CLP2.
bogdanm	82:6473597d706e	1906
bogdanm	82:6473597d706e	1907	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1908	//! @brief Read current value of the ADC_CLP2_CLP2 field.
bogdanm	82:6473597d706e	1909	#define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
bogdanm	82:6473597d706e	1910	#endif
bogdanm	82:6473597d706e	1911
bogdanm	82:6473597d706e	1912	//! @brief Format value for bitfield ADC_CLP2_CLP2.
bogdanm	82:6473597d706e	1913	#define BF_ADC_CLP2_CLP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP2_CLP2), uint32_t) & BM_ADC_CLP2_CLP2)
bogdanm	82:6473597d706e	1914
bogdanm	82:6473597d706e	1915	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1916	//! @brief Set the CLP2 field to a new value.
bogdanm	82:6473597d706e	1917	#define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) \| BF_ADC_CLP2_CLP2(v)))
bogdanm	82:6473597d706e	1918	#endif
bogdanm	82:6473597d706e	1919	//@}
bogdanm	82:6473597d706e	1920
bogdanm	82:6473597d706e	1921	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1922	// HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1923	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1924
bogdanm	82:6473597d706e	1925	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1926	/*!
bogdanm	82:6473597d706e	1927	* @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1928	*
bogdanm	82:6473597d706e	1929	* Reset value: 0x00000040U
bogdanm	82:6473597d706e	1930	*
bogdanm	82:6473597d706e	1931	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1932	*/
bogdanm	82:6473597d706e	1933	typedef union _hw_adc_clp1
bogdanm	82:6473597d706e	1934	{
bogdanm	82:6473597d706e	1935	uint32_t U;
bogdanm	82:6473597d706e	1936	struct _hw_adc_clp1_bitfields
bogdanm	82:6473597d706e	1937	{
bogdanm	82:6473597d706e	1938	uint32_t CLP1 : 7; //!< [6:0]
bogdanm	82:6473597d706e	1939	uint32_t RESERVED0 : 25; //!< [31:7]
bogdanm	82:6473597d706e	1940	} B;
bogdanm	82:6473597d706e	1941	} hw_adc_clp1_t;
bogdanm	82:6473597d706e	1942	#endif
bogdanm	82:6473597d706e	1943
bogdanm	82:6473597d706e	1944	/*!
bogdanm	82:6473597d706e	1945	* @name Constants and macros for entire ADC_CLP1 register
bogdanm	82:6473597d706e	1946	*/
bogdanm	82:6473597d706e	1947	//@{
bogdanm	82:6473597d706e	1948	#define HW_ADC_CLP1_ADDR(x) (REGS_ADC_BASE(x) + 0x48U)
bogdanm	82:6473597d706e	1949
bogdanm	82:6473597d706e	1950	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1951	#define HW_ADC_CLP1(x) ((__IO hw_adc_clp1_t ) HW_ADC_CLP1_ADDR(x))
bogdanm	82:6473597d706e	1952	#define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
bogdanm	82:6473597d706e	1953	#define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
bogdanm	82:6473597d706e	1954	#define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) \| (v)))
bogdanm	82:6473597d706e	1955	#define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1956	#define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1957	#endif
bogdanm	82:6473597d706e	1958	//@}
bogdanm	82:6473597d706e	1959
bogdanm	82:6473597d706e	1960	/*
bogdanm	82:6473597d706e	1961	* Constants & macros for individual ADC_CLP1 bitfields
bogdanm	82:6473597d706e	1962	*/
bogdanm	82:6473597d706e	1963
bogdanm	82:6473597d706e	1964	/*!
bogdanm	82:6473597d706e	1965	* @name Register ADC_CLP1, field CLP1[6:0] (RW)
bogdanm	82:6473597d706e	1966	*
bogdanm	82:6473597d706e	1967	* Calibration Value
bogdanm	82:6473597d706e	1968	*/
bogdanm	82:6473597d706e	1969	//@{
bogdanm	82:6473597d706e	1970	#define BP_ADC_CLP1_CLP1 (0U) //!< Bit position for ADC_CLP1_CLP1.
bogdanm	82:6473597d706e	1971	#define BM_ADC_CLP1_CLP1 (0x0000007FU) //!< Bit mask for ADC_CLP1_CLP1.
bogdanm	82:6473597d706e	1972	#define BS_ADC_CLP1_CLP1 (7U) //!< Bit field size in bits for ADC_CLP1_CLP1.
bogdanm	82:6473597d706e	1973
bogdanm	82:6473597d706e	1974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1975	//! @brief Read current value of the ADC_CLP1_CLP1 field.
bogdanm	82:6473597d706e	1976	#define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
bogdanm	82:6473597d706e	1977	#endif
bogdanm	82:6473597d706e	1978
bogdanm	82:6473597d706e	1979	//! @brief Format value for bitfield ADC_CLP1_CLP1.
bogdanm	82:6473597d706e	1980	#define BF_ADC_CLP1_CLP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP1_CLP1), uint32_t) & BM_ADC_CLP1_CLP1)
bogdanm	82:6473597d706e	1981
bogdanm	82:6473597d706e	1982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1983	//! @brief Set the CLP1 field to a new value.
bogdanm	82:6473597d706e	1984	#define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) \| BF_ADC_CLP1_CLP1(v)))
bogdanm	82:6473597d706e	1985	#endif
bogdanm	82:6473597d706e	1986	//@}
bogdanm	82:6473597d706e	1987
bogdanm	82:6473597d706e	1988	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1989	// HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	1990	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1991
bogdanm	82:6473597d706e	1992	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1993	/*!
bogdanm	82:6473597d706e	1994	* @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	1995	*
bogdanm	82:6473597d706e	1996	* Reset value: 0x00000020U
bogdanm	82:6473597d706e	1997	*
bogdanm	82:6473597d706e	1998	* For more information, see CLPD register description.
bogdanm	82:6473597d706e	1999	*/
bogdanm	82:6473597d706e	2000	typedef union _hw_adc_clp0
bogdanm	82:6473597d706e	2001	{
bogdanm	82:6473597d706e	2002	uint32_t U;
bogdanm	82:6473597d706e	2003	struct _hw_adc_clp0_bitfields
bogdanm	82:6473597d706e	2004	{
bogdanm	82:6473597d706e	2005	uint32_t CLP0 : 6; //!< [5:0]
bogdanm	82:6473597d706e	2006	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	2007	} B;
bogdanm	82:6473597d706e	2008	} hw_adc_clp0_t;
bogdanm	82:6473597d706e	2009	#endif
bogdanm	82:6473597d706e	2010
bogdanm	82:6473597d706e	2011	/*!
bogdanm	82:6473597d706e	2012	* @name Constants and macros for entire ADC_CLP0 register
bogdanm	82:6473597d706e	2013	*/
bogdanm	82:6473597d706e	2014	//@{
bogdanm	82:6473597d706e	2015	#define HW_ADC_CLP0_ADDR(x) (REGS_ADC_BASE(x) + 0x4CU)
bogdanm	82:6473597d706e	2016
bogdanm	82:6473597d706e	2017	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2018	#define HW_ADC_CLP0(x) ((__IO hw_adc_clp0_t ) HW_ADC_CLP0_ADDR(x))
bogdanm	82:6473597d706e	2019	#define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
bogdanm	82:6473597d706e	2020	#define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
bogdanm	82:6473597d706e	2021	#define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) \| (v)))
bogdanm	82:6473597d706e	2022	#define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2023	#define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2024	#endif
bogdanm	82:6473597d706e	2025	//@}
bogdanm	82:6473597d706e	2026
bogdanm	82:6473597d706e	2027	/*
bogdanm	82:6473597d706e	2028	* Constants & macros for individual ADC_CLP0 bitfields
bogdanm	82:6473597d706e	2029	*/
bogdanm	82:6473597d706e	2030
bogdanm	82:6473597d706e	2031	/*!
bogdanm	82:6473597d706e	2032	* @name Register ADC_CLP0, field CLP0[5:0] (RW)
bogdanm	82:6473597d706e	2033	*
bogdanm	82:6473597d706e	2034	* Calibration Value
bogdanm	82:6473597d706e	2035	*/
bogdanm	82:6473597d706e	2036	//@{
bogdanm	82:6473597d706e	2037	#define BP_ADC_CLP0_CLP0 (0U) //!< Bit position for ADC_CLP0_CLP0.
bogdanm	82:6473597d706e	2038	#define BM_ADC_CLP0_CLP0 (0x0000003FU) //!< Bit mask for ADC_CLP0_CLP0.
bogdanm	82:6473597d706e	2039	#define BS_ADC_CLP0_CLP0 (6U) //!< Bit field size in bits for ADC_CLP0_CLP0.
bogdanm	82:6473597d706e	2040
bogdanm	82:6473597d706e	2041	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2042	//! @brief Read current value of the ADC_CLP0_CLP0 field.
bogdanm	82:6473597d706e	2043	#define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
bogdanm	82:6473597d706e	2044	#endif
bogdanm	82:6473597d706e	2045
bogdanm	82:6473597d706e	2046	//! @brief Format value for bitfield ADC_CLP0_CLP0.
bogdanm	82:6473597d706e	2047	#define BF_ADC_CLP0_CLP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP0_CLP0), uint32_t) & BM_ADC_CLP0_CLP0)
bogdanm	82:6473597d706e	2048
bogdanm	82:6473597d706e	2049	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2050	//! @brief Set the CLP0 field to a new value.
bogdanm	82:6473597d706e	2051	#define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) \| BF_ADC_CLP0_CLP0(v)))
bogdanm	82:6473597d706e	2052	#endif
bogdanm	82:6473597d706e	2053	//@}
bogdanm	82:6473597d706e	2054
bogdanm	82:6473597d706e	2055	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2056	// HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2057	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2058
bogdanm	82:6473597d706e	2059	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2060	/*!
bogdanm	82:6473597d706e	2061	* @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2062	*
bogdanm	82:6473597d706e	2063	* Reset value: 0x0000000AU
bogdanm	82:6473597d706e	2064	*
bogdanm	82:6473597d706e	2065	* The Minus-Side General Calibration Value (CLMx) registers contain calibration
bogdanm	82:6473597d706e	2066	* information that is generated by the calibration function. These registers
bogdanm	82:6473597d706e	2067	* contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
bogdanm	82:6473597d706e	2068	* CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
bogdanm	82:6473597d706e	2069	* set when the self-calibration sequence is done, that is, CAL is cleared. If
bogdanm	82:6473597d706e	2070	* these registers are written by the user after calibration, the linearity error
bogdanm	82:6473597d706e	2071	* specifications may not be met.
bogdanm	82:6473597d706e	2072	*/
bogdanm	82:6473597d706e	2073	typedef union _hw_adc_clmd
bogdanm	82:6473597d706e	2074	{
bogdanm	82:6473597d706e	2075	uint32_t U;
bogdanm	82:6473597d706e	2076	struct _hw_adc_clmd_bitfields
bogdanm	82:6473597d706e	2077	{
bogdanm	82:6473597d706e	2078	uint32_t CLMD : 6; //!< [5:0]
bogdanm	82:6473597d706e	2079	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	2080	} B;
bogdanm	82:6473597d706e	2081	} hw_adc_clmd_t;
bogdanm	82:6473597d706e	2082	#endif
bogdanm	82:6473597d706e	2083
bogdanm	82:6473597d706e	2084	/*!
bogdanm	82:6473597d706e	2085	* @name Constants and macros for entire ADC_CLMD register
bogdanm	82:6473597d706e	2086	*/
bogdanm	82:6473597d706e	2087	//@{
bogdanm	82:6473597d706e	2088	#define HW_ADC_CLMD_ADDR(x) (REGS_ADC_BASE(x) + 0x54U)
bogdanm	82:6473597d706e	2089
bogdanm	82:6473597d706e	2090	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2091	#define HW_ADC_CLMD(x) ((__IO hw_adc_clmd_t ) HW_ADC_CLMD_ADDR(x))
bogdanm	82:6473597d706e	2092	#define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
bogdanm	82:6473597d706e	2093	#define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
bogdanm	82:6473597d706e	2094	#define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) \| (v)))
bogdanm	82:6473597d706e	2095	#define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2096	#define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2097	#endif
bogdanm	82:6473597d706e	2098	//@}
bogdanm	82:6473597d706e	2099
bogdanm	82:6473597d706e	2100	/*
bogdanm	82:6473597d706e	2101	* Constants & macros for individual ADC_CLMD bitfields
bogdanm	82:6473597d706e	2102	*/
bogdanm	82:6473597d706e	2103
bogdanm	82:6473597d706e	2104	/*!
bogdanm	82:6473597d706e	2105	* @name Register ADC_CLMD, field CLMD[5:0] (RW)
bogdanm	82:6473597d706e	2106	*
bogdanm	82:6473597d706e	2107	* Calibration Value
bogdanm	82:6473597d706e	2108	*/
bogdanm	82:6473597d706e	2109	//@{
bogdanm	82:6473597d706e	2110	#define BP_ADC_CLMD_CLMD (0U) //!< Bit position for ADC_CLMD_CLMD.
bogdanm	82:6473597d706e	2111	#define BM_ADC_CLMD_CLMD (0x0000003FU) //!< Bit mask for ADC_CLMD_CLMD.
bogdanm	82:6473597d706e	2112	#define BS_ADC_CLMD_CLMD (6U) //!< Bit field size in bits for ADC_CLMD_CLMD.
bogdanm	82:6473597d706e	2113
bogdanm	82:6473597d706e	2114	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2115	//! @brief Read current value of the ADC_CLMD_CLMD field.
bogdanm	82:6473597d706e	2116	#define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
bogdanm	82:6473597d706e	2117	#endif
bogdanm	82:6473597d706e	2118
bogdanm	82:6473597d706e	2119	//! @brief Format value for bitfield ADC_CLMD_CLMD.
bogdanm	82:6473597d706e	2120	#define BF_ADC_CLMD_CLMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMD_CLMD), uint32_t) & BM_ADC_CLMD_CLMD)
bogdanm	82:6473597d706e	2121
bogdanm	82:6473597d706e	2122	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2123	//! @brief Set the CLMD field to a new value.
bogdanm	82:6473597d706e	2124	#define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) \| BF_ADC_CLMD_CLMD(v)))
bogdanm	82:6473597d706e	2125	#endif
bogdanm	82:6473597d706e	2126	//@}
bogdanm	82:6473597d706e	2127
bogdanm	82:6473597d706e	2128	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2129	// HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2130	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2131
bogdanm	82:6473597d706e	2132	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2133	/*!
bogdanm	82:6473597d706e	2134	* @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2135	*
bogdanm	82:6473597d706e	2136	* Reset value: 0x00000020U
bogdanm	82:6473597d706e	2137	*
bogdanm	82:6473597d706e	2138	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2139	*/
bogdanm	82:6473597d706e	2140	typedef union _hw_adc_clms
bogdanm	82:6473597d706e	2141	{
bogdanm	82:6473597d706e	2142	uint32_t U;
bogdanm	82:6473597d706e	2143	struct _hw_adc_clms_bitfields
bogdanm	82:6473597d706e	2144	{
bogdanm	82:6473597d706e	2145	uint32_t CLMS : 6; //!< [5:0]
bogdanm	82:6473597d706e	2146	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	2147	} B;
bogdanm	82:6473597d706e	2148	} hw_adc_clms_t;
bogdanm	82:6473597d706e	2149	#endif
bogdanm	82:6473597d706e	2150
bogdanm	82:6473597d706e	2151	/*!
bogdanm	82:6473597d706e	2152	* @name Constants and macros for entire ADC_CLMS register
bogdanm	82:6473597d706e	2153	*/
bogdanm	82:6473597d706e	2154	//@{
bogdanm	82:6473597d706e	2155	#define HW_ADC_CLMS_ADDR(x) (REGS_ADC_BASE(x) + 0x58U)
bogdanm	82:6473597d706e	2156
bogdanm	82:6473597d706e	2157	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2158	#define HW_ADC_CLMS(x) ((__IO hw_adc_clms_t ) HW_ADC_CLMS_ADDR(x))
bogdanm	82:6473597d706e	2159	#define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
bogdanm	82:6473597d706e	2160	#define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
bogdanm	82:6473597d706e	2161	#define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) \| (v)))
bogdanm	82:6473597d706e	2162	#define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2163	#define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2164	#endif
bogdanm	82:6473597d706e	2165	//@}
bogdanm	82:6473597d706e	2166
bogdanm	82:6473597d706e	2167	/*
bogdanm	82:6473597d706e	2168	* Constants & macros for individual ADC_CLMS bitfields
bogdanm	82:6473597d706e	2169	*/
bogdanm	82:6473597d706e	2170
bogdanm	82:6473597d706e	2171	/*!
bogdanm	82:6473597d706e	2172	* @name Register ADC_CLMS, field CLMS[5:0] (RW)
bogdanm	82:6473597d706e	2173	*
bogdanm	82:6473597d706e	2174	* Calibration Value
bogdanm	82:6473597d706e	2175	*/
bogdanm	82:6473597d706e	2176	//@{
bogdanm	82:6473597d706e	2177	#define BP_ADC_CLMS_CLMS (0U) //!< Bit position for ADC_CLMS_CLMS.
bogdanm	82:6473597d706e	2178	#define BM_ADC_CLMS_CLMS (0x0000003FU) //!< Bit mask for ADC_CLMS_CLMS.
bogdanm	82:6473597d706e	2179	#define BS_ADC_CLMS_CLMS (6U) //!< Bit field size in bits for ADC_CLMS_CLMS.
bogdanm	82:6473597d706e	2180
bogdanm	82:6473597d706e	2181	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2182	//! @brief Read current value of the ADC_CLMS_CLMS field.
bogdanm	82:6473597d706e	2183	#define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
bogdanm	82:6473597d706e	2184	#endif
bogdanm	82:6473597d706e	2185
bogdanm	82:6473597d706e	2186	//! @brief Format value for bitfield ADC_CLMS_CLMS.
bogdanm	82:6473597d706e	2187	#define BF_ADC_CLMS_CLMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMS_CLMS), uint32_t) & BM_ADC_CLMS_CLMS)
bogdanm	82:6473597d706e	2188
bogdanm	82:6473597d706e	2189	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2190	//! @brief Set the CLMS field to a new value.
bogdanm	82:6473597d706e	2191	#define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) \| BF_ADC_CLMS_CLMS(v)))
bogdanm	82:6473597d706e	2192	#endif
bogdanm	82:6473597d706e	2193	//@}
bogdanm	82:6473597d706e	2194
bogdanm	82:6473597d706e	2195	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2196	// HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2197	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2198
bogdanm	82:6473597d706e	2199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2200	/*!
bogdanm	82:6473597d706e	2201	* @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2202	*
bogdanm	82:6473597d706e	2203	* Reset value: 0x00000200U
bogdanm	82:6473597d706e	2204	*
bogdanm	82:6473597d706e	2205	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2206	*/
bogdanm	82:6473597d706e	2207	typedef union _hw_adc_clm4
bogdanm	82:6473597d706e	2208	{
bogdanm	82:6473597d706e	2209	uint32_t U;
bogdanm	82:6473597d706e	2210	struct _hw_adc_clm4_bitfields
bogdanm	82:6473597d706e	2211	{
bogdanm	82:6473597d706e	2212	uint32_t CLM4 : 10; //!< [9:0]
bogdanm	82:6473597d706e	2213	uint32_t RESERVED0 : 22; //!< [31:10]
bogdanm	82:6473597d706e	2214	} B;
bogdanm	82:6473597d706e	2215	} hw_adc_clm4_t;
bogdanm	82:6473597d706e	2216	#endif
bogdanm	82:6473597d706e	2217
bogdanm	82:6473597d706e	2218	/*!
bogdanm	82:6473597d706e	2219	* @name Constants and macros for entire ADC_CLM4 register
bogdanm	82:6473597d706e	2220	*/
bogdanm	82:6473597d706e	2221	//@{
bogdanm	82:6473597d706e	2222	#define HW_ADC_CLM4_ADDR(x) (REGS_ADC_BASE(x) + 0x5CU)
bogdanm	82:6473597d706e	2223
bogdanm	82:6473597d706e	2224	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2225	#define HW_ADC_CLM4(x) ((__IO hw_adc_clm4_t ) HW_ADC_CLM4_ADDR(x))
bogdanm	82:6473597d706e	2226	#define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
bogdanm	82:6473597d706e	2227	#define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
bogdanm	82:6473597d706e	2228	#define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) \| (v)))
bogdanm	82:6473597d706e	2229	#define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2230	#define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2231	#endif
bogdanm	82:6473597d706e	2232	//@}
bogdanm	82:6473597d706e	2233
bogdanm	82:6473597d706e	2234	/*
bogdanm	82:6473597d706e	2235	* Constants & macros for individual ADC_CLM4 bitfields
bogdanm	82:6473597d706e	2236	*/
bogdanm	82:6473597d706e	2237
bogdanm	82:6473597d706e	2238	/*!
bogdanm	82:6473597d706e	2239	* @name Register ADC_CLM4, field CLM4[9:0] (RW)
bogdanm	82:6473597d706e	2240	*
bogdanm	82:6473597d706e	2241	* Calibration Value
bogdanm	82:6473597d706e	2242	*/
bogdanm	82:6473597d706e	2243	//@{
bogdanm	82:6473597d706e	2244	#define BP_ADC_CLM4_CLM4 (0U) //!< Bit position for ADC_CLM4_CLM4.
bogdanm	82:6473597d706e	2245	#define BM_ADC_CLM4_CLM4 (0x000003FFU) //!< Bit mask for ADC_CLM4_CLM4.
bogdanm	82:6473597d706e	2246	#define BS_ADC_CLM4_CLM4 (10U) //!< Bit field size in bits for ADC_CLM4_CLM4.
bogdanm	82:6473597d706e	2247
bogdanm	82:6473597d706e	2248	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2249	//! @brief Read current value of the ADC_CLM4_CLM4 field.
bogdanm	82:6473597d706e	2250	#define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
bogdanm	82:6473597d706e	2251	#endif
bogdanm	82:6473597d706e	2252
bogdanm	82:6473597d706e	2253	//! @brief Format value for bitfield ADC_CLM4_CLM4.
bogdanm	82:6473597d706e	2254	#define BF_ADC_CLM4_CLM4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM4_CLM4), uint32_t) & BM_ADC_CLM4_CLM4)
bogdanm	82:6473597d706e	2255
bogdanm	82:6473597d706e	2256	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2257	//! @brief Set the CLM4 field to a new value.
bogdanm	82:6473597d706e	2258	#define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) \| BF_ADC_CLM4_CLM4(v)))
bogdanm	82:6473597d706e	2259	#endif
bogdanm	82:6473597d706e	2260	//@}
bogdanm	82:6473597d706e	2261
bogdanm	82:6473597d706e	2262	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2263	// HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2264	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2265
bogdanm	82:6473597d706e	2266	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2267	/*!
bogdanm	82:6473597d706e	2268	* @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2269	*
bogdanm	82:6473597d706e	2270	* Reset value: 0x00000100U
bogdanm	82:6473597d706e	2271	*
bogdanm	82:6473597d706e	2272	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2273	*/
bogdanm	82:6473597d706e	2274	typedef union _hw_adc_clm3
bogdanm	82:6473597d706e	2275	{
bogdanm	82:6473597d706e	2276	uint32_t U;
bogdanm	82:6473597d706e	2277	struct _hw_adc_clm3_bitfields
bogdanm	82:6473597d706e	2278	{
bogdanm	82:6473597d706e	2279	uint32_t CLM3 : 9; //!< [8:0]
bogdanm	82:6473597d706e	2280	uint32_t RESERVED0 : 23; //!< [31:9]
bogdanm	82:6473597d706e	2281	} B;
bogdanm	82:6473597d706e	2282	} hw_adc_clm3_t;
bogdanm	82:6473597d706e	2283	#endif
bogdanm	82:6473597d706e	2284
bogdanm	82:6473597d706e	2285	/*!
bogdanm	82:6473597d706e	2286	* @name Constants and macros for entire ADC_CLM3 register
bogdanm	82:6473597d706e	2287	*/
bogdanm	82:6473597d706e	2288	//@{
bogdanm	82:6473597d706e	2289	#define HW_ADC_CLM3_ADDR(x) (REGS_ADC_BASE(x) + 0x60U)
bogdanm	82:6473597d706e	2290
bogdanm	82:6473597d706e	2291	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2292	#define HW_ADC_CLM3(x) ((__IO hw_adc_clm3_t ) HW_ADC_CLM3_ADDR(x))
bogdanm	82:6473597d706e	2293	#define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
bogdanm	82:6473597d706e	2294	#define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
bogdanm	82:6473597d706e	2295	#define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) \| (v)))
bogdanm	82:6473597d706e	2296	#define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2297	#define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2298	#endif
bogdanm	82:6473597d706e	2299	//@}
bogdanm	82:6473597d706e	2300
bogdanm	82:6473597d706e	2301	/*
bogdanm	82:6473597d706e	2302	* Constants & macros for individual ADC_CLM3 bitfields
bogdanm	82:6473597d706e	2303	*/
bogdanm	82:6473597d706e	2304
bogdanm	82:6473597d706e	2305	/*!
bogdanm	82:6473597d706e	2306	* @name Register ADC_CLM3, field CLM3[8:0] (RW)
bogdanm	82:6473597d706e	2307	*
bogdanm	82:6473597d706e	2308	* Calibration Value
bogdanm	82:6473597d706e	2309	*/
bogdanm	82:6473597d706e	2310	//@{
bogdanm	82:6473597d706e	2311	#define BP_ADC_CLM3_CLM3 (0U) //!< Bit position for ADC_CLM3_CLM3.
bogdanm	82:6473597d706e	2312	#define BM_ADC_CLM3_CLM3 (0x000001FFU) //!< Bit mask for ADC_CLM3_CLM3.
bogdanm	82:6473597d706e	2313	#define BS_ADC_CLM3_CLM3 (9U) //!< Bit field size in bits for ADC_CLM3_CLM3.
bogdanm	82:6473597d706e	2314
bogdanm	82:6473597d706e	2315	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2316	//! @brief Read current value of the ADC_CLM3_CLM3 field.
bogdanm	82:6473597d706e	2317	#define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
bogdanm	82:6473597d706e	2318	#endif
bogdanm	82:6473597d706e	2319
bogdanm	82:6473597d706e	2320	//! @brief Format value for bitfield ADC_CLM3_CLM3.
bogdanm	82:6473597d706e	2321	#define BF_ADC_CLM3_CLM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM3_CLM3), uint32_t) & BM_ADC_CLM3_CLM3)
bogdanm	82:6473597d706e	2322
bogdanm	82:6473597d706e	2323	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2324	//! @brief Set the CLM3 field to a new value.
bogdanm	82:6473597d706e	2325	#define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) \| BF_ADC_CLM3_CLM3(v)))
bogdanm	82:6473597d706e	2326	#endif
bogdanm	82:6473597d706e	2327	//@}
bogdanm	82:6473597d706e	2328
bogdanm	82:6473597d706e	2329	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2330	// HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2331	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2332
bogdanm	82:6473597d706e	2333	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2334	/*!
bogdanm	82:6473597d706e	2335	* @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2336	*
bogdanm	82:6473597d706e	2337	* Reset value: 0x00000080U
bogdanm	82:6473597d706e	2338	*
bogdanm	82:6473597d706e	2339	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2340	*/
bogdanm	82:6473597d706e	2341	typedef union _hw_adc_clm2
bogdanm	82:6473597d706e	2342	{
bogdanm	82:6473597d706e	2343	uint32_t U;
bogdanm	82:6473597d706e	2344	struct _hw_adc_clm2_bitfields
bogdanm	82:6473597d706e	2345	{
bogdanm	82:6473597d706e	2346	uint32_t CLM2 : 8; //!< [7:0]
bogdanm	82:6473597d706e	2347	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	2348	} B;
bogdanm	82:6473597d706e	2349	} hw_adc_clm2_t;
bogdanm	82:6473597d706e	2350	#endif
bogdanm	82:6473597d706e	2351
bogdanm	82:6473597d706e	2352	/*!
bogdanm	82:6473597d706e	2353	* @name Constants and macros for entire ADC_CLM2 register
bogdanm	82:6473597d706e	2354	*/
bogdanm	82:6473597d706e	2355	//@{
bogdanm	82:6473597d706e	2356	#define HW_ADC_CLM2_ADDR(x) (REGS_ADC_BASE(x) + 0x64U)
bogdanm	82:6473597d706e	2357
bogdanm	82:6473597d706e	2358	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2359	#define HW_ADC_CLM2(x) ((__IO hw_adc_clm2_t ) HW_ADC_CLM2_ADDR(x))
bogdanm	82:6473597d706e	2360	#define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
bogdanm	82:6473597d706e	2361	#define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
bogdanm	82:6473597d706e	2362	#define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) \| (v)))
bogdanm	82:6473597d706e	2363	#define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2364	#define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2365	#endif
bogdanm	82:6473597d706e	2366	//@}
bogdanm	82:6473597d706e	2367
bogdanm	82:6473597d706e	2368	/*
bogdanm	82:6473597d706e	2369	* Constants & macros for individual ADC_CLM2 bitfields
bogdanm	82:6473597d706e	2370	*/
bogdanm	82:6473597d706e	2371
bogdanm	82:6473597d706e	2372	/*!
bogdanm	82:6473597d706e	2373	* @name Register ADC_CLM2, field CLM2[7:0] (RW)
bogdanm	82:6473597d706e	2374	*
bogdanm	82:6473597d706e	2375	* Calibration Value
bogdanm	82:6473597d706e	2376	*/
bogdanm	82:6473597d706e	2377	//@{
bogdanm	82:6473597d706e	2378	#define BP_ADC_CLM2_CLM2 (0U) //!< Bit position for ADC_CLM2_CLM2.
bogdanm	82:6473597d706e	2379	#define BM_ADC_CLM2_CLM2 (0x000000FFU) //!< Bit mask for ADC_CLM2_CLM2.
bogdanm	82:6473597d706e	2380	#define BS_ADC_CLM2_CLM2 (8U) //!< Bit field size in bits for ADC_CLM2_CLM2.
bogdanm	82:6473597d706e	2381
bogdanm	82:6473597d706e	2382	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2383	//! @brief Read current value of the ADC_CLM2_CLM2 field.
bogdanm	82:6473597d706e	2384	#define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
bogdanm	82:6473597d706e	2385	#endif
bogdanm	82:6473597d706e	2386
bogdanm	82:6473597d706e	2387	//! @brief Format value for bitfield ADC_CLM2_CLM2.
bogdanm	82:6473597d706e	2388	#define BF_ADC_CLM2_CLM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM2_CLM2), uint32_t) & BM_ADC_CLM2_CLM2)
bogdanm	82:6473597d706e	2389
bogdanm	82:6473597d706e	2390	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2391	//! @brief Set the CLM2 field to a new value.
bogdanm	82:6473597d706e	2392	#define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) \| BF_ADC_CLM2_CLM2(v)))
bogdanm	82:6473597d706e	2393	#endif
bogdanm	82:6473597d706e	2394	//@}
bogdanm	82:6473597d706e	2395
bogdanm	82:6473597d706e	2396	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2397	// HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2398	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2399
bogdanm	82:6473597d706e	2400	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2401	/*!
bogdanm	82:6473597d706e	2402	* @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2403	*
bogdanm	82:6473597d706e	2404	* Reset value: 0x00000040U
bogdanm	82:6473597d706e	2405	*
bogdanm	82:6473597d706e	2406	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2407	*/
bogdanm	82:6473597d706e	2408	typedef union _hw_adc_clm1
bogdanm	82:6473597d706e	2409	{
bogdanm	82:6473597d706e	2410	uint32_t U;
bogdanm	82:6473597d706e	2411	struct _hw_adc_clm1_bitfields
bogdanm	82:6473597d706e	2412	{
bogdanm	82:6473597d706e	2413	uint32_t CLM1 : 7; //!< [6:0]
bogdanm	82:6473597d706e	2414	uint32_t RESERVED0 : 25; //!< [31:7]
bogdanm	82:6473597d706e	2415	} B;
bogdanm	82:6473597d706e	2416	} hw_adc_clm1_t;
bogdanm	82:6473597d706e	2417	#endif
bogdanm	82:6473597d706e	2418
bogdanm	82:6473597d706e	2419	/*!
bogdanm	82:6473597d706e	2420	* @name Constants and macros for entire ADC_CLM1 register
bogdanm	82:6473597d706e	2421	*/
bogdanm	82:6473597d706e	2422	//@{
bogdanm	82:6473597d706e	2423	#define HW_ADC_CLM1_ADDR(x) (REGS_ADC_BASE(x) + 0x68U)
bogdanm	82:6473597d706e	2424
bogdanm	82:6473597d706e	2425	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2426	#define HW_ADC_CLM1(x) ((__IO hw_adc_clm1_t ) HW_ADC_CLM1_ADDR(x))
bogdanm	82:6473597d706e	2427	#define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
bogdanm	82:6473597d706e	2428	#define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
bogdanm	82:6473597d706e	2429	#define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) \| (v)))
bogdanm	82:6473597d706e	2430	#define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2431	#define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2432	#endif
bogdanm	82:6473597d706e	2433	//@}
bogdanm	82:6473597d706e	2434
bogdanm	82:6473597d706e	2435	/*
bogdanm	82:6473597d706e	2436	* Constants & macros for individual ADC_CLM1 bitfields
bogdanm	82:6473597d706e	2437	*/
bogdanm	82:6473597d706e	2438
bogdanm	82:6473597d706e	2439	/*!
bogdanm	82:6473597d706e	2440	* @name Register ADC_CLM1, field CLM1[6:0] (RW)
bogdanm	82:6473597d706e	2441	*
bogdanm	82:6473597d706e	2442	* Calibration Value
bogdanm	82:6473597d706e	2443	*/
bogdanm	82:6473597d706e	2444	//@{
bogdanm	82:6473597d706e	2445	#define BP_ADC_CLM1_CLM1 (0U) //!< Bit position for ADC_CLM1_CLM1.
bogdanm	82:6473597d706e	2446	#define BM_ADC_CLM1_CLM1 (0x0000007FU) //!< Bit mask for ADC_CLM1_CLM1.
bogdanm	82:6473597d706e	2447	#define BS_ADC_CLM1_CLM1 (7U) //!< Bit field size in bits for ADC_CLM1_CLM1.
bogdanm	82:6473597d706e	2448
bogdanm	82:6473597d706e	2449	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2450	//! @brief Read current value of the ADC_CLM1_CLM1 field.
bogdanm	82:6473597d706e	2451	#define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
bogdanm	82:6473597d706e	2452	#endif
bogdanm	82:6473597d706e	2453
bogdanm	82:6473597d706e	2454	//! @brief Format value for bitfield ADC_CLM1_CLM1.
bogdanm	82:6473597d706e	2455	#define BF_ADC_CLM1_CLM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM1_CLM1), uint32_t) & BM_ADC_CLM1_CLM1)
bogdanm	82:6473597d706e	2456
bogdanm	82:6473597d706e	2457	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2458	//! @brief Set the CLM1 field to a new value.
bogdanm	82:6473597d706e	2459	#define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) \| BF_ADC_CLM1_CLM1(v)))
bogdanm	82:6473597d706e	2460	#endif
bogdanm	82:6473597d706e	2461	//@}
bogdanm	82:6473597d706e	2462
bogdanm	82:6473597d706e	2463	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2464	// HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2465	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2466
bogdanm	82:6473597d706e	2467	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2468	/*!
bogdanm	82:6473597d706e	2469	* @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
bogdanm	82:6473597d706e	2470	*
bogdanm	82:6473597d706e	2471	* Reset value: 0x00000020U
bogdanm	82:6473597d706e	2472	*
bogdanm	82:6473597d706e	2473	* For more information, see CLMD register description.
bogdanm	82:6473597d706e	2474	*/
bogdanm	82:6473597d706e	2475	typedef union _hw_adc_clm0
bogdanm	82:6473597d706e	2476	{
bogdanm	82:6473597d706e	2477	uint32_t U;
bogdanm	82:6473597d706e	2478	struct _hw_adc_clm0_bitfields
bogdanm	82:6473597d706e	2479	{
bogdanm	82:6473597d706e	2480	uint32_t CLM0 : 6; //!< [5:0]
bogdanm	82:6473597d706e	2481	uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm	82:6473597d706e	2482	} B;
bogdanm	82:6473597d706e	2483	} hw_adc_clm0_t;
bogdanm	82:6473597d706e	2484	#endif
bogdanm	82:6473597d706e	2485
bogdanm	82:6473597d706e	2486	/*!
bogdanm	82:6473597d706e	2487	* @name Constants and macros for entire ADC_CLM0 register
bogdanm	82:6473597d706e	2488	*/
bogdanm	82:6473597d706e	2489	//@{
bogdanm	82:6473597d706e	2490	#define HW_ADC_CLM0_ADDR(x) (REGS_ADC_BASE(x) + 0x6CU)
bogdanm	82:6473597d706e	2491
bogdanm	82:6473597d706e	2492	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2493	#define HW_ADC_CLM0(x) ((__IO hw_adc_clm0_t ) HW_ADC_CLM0_ADDR(x))
bogdanm	82:6473597d706e	2494	#define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
bogdanm	82:6473597d706e	2495	#define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
bogdanm	82:6473597d706e	2496	#define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) \| (v)))
bogdanm	82:6473597d706e	2497	#define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2498	#define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2499	#endif
bogdanm	82:6473597d706e	2500	//@}
bogdanm	82:6473597d706e	2501
bogdanm	82:6473597d706e	2502	/*
bogdanm	82:6473597d706e	2503	* Constants & macros for individual ADC_CLM0 bitfields
bogdanm	82:6473597d706e	2504	*/
bogdanm	82:6473597d706e	2505
bogdanm	82:6473597d706e	2506	/*!
bogdanm	82:6473597d706e	2507	* @name Register ADC_CLM0, field CLM0[5:0] (RW)
bogdanm	82:6473597d706e	2508	*
bogdanm	82:6473597d706e	2509	* Calibration Value
bogdanm	82:6473597d706e	2510	*/
bogdanm	82:6473597d706e	2511	//@{
bogdanm	82:6473597d706e	2512	#define BP_ADC_CLM0_CLM0 (0U) //!< Bit position for ADC_CLM0_CLM0.
bogdanm	82:6473597d706e	2513	#define BM_ADC_CLM0_CLM0 (0x0000003FU) //!< Bit mask for ADC_CLM0_CLM0.
bogdanm	82:6473597d706e	2514	#define BS_ADC_CLM0_CLM0 (6U) //!< Bit field size in bits for ADC_CLM0_CLM0.
bogdanm	82:6473597d706e	2515
bogdanm	82:6473597d706e	2516	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2517	//! @brief Read current value of the ADC_CLM0_CLM0 field.
bogdanm	82:6473597d706e	2518	#define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
bogdanm	82:6473597d706e	2519	#endif
bogdanm	82:6473597d706e	2520
bogdanm	82:6473597d706e	2521	//! @brief Format value for bitfield ADC_CLM0_CLM0.
bogdanm	82:6473597d706e	2522	#define BF_ADC_CLM0_CLM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM0_CLM0), uint32_t) & BM_ADC_CLM0_CLM0)
bogdanm	82:6473597d706e	2523
bogdanm	82:6473597d706e	2524	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2525	//! @brief Set the CLM0 field to a new value.
bogdanm	82:6473597d706e	2526	#define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) \| BF_ADC_CLM0_CLM0(v)))
bogdanm	82:6473597d706e	2527	#endif
bogdanm	82:6473597d706e	2528	//@}
bogdanm	82:6473597d706e	2529
bogdanm	82:6473597d706e	2530	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2531	// hw_adc_t - module struct
bogdanm	82:6473597d706e	2532	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2533	/*!
bogdanm	82:6473597d706e	2534	* @brief All ADC module registers.
bogdanm	82:6473597d706e	2535	*/
bogdanm	82:6473597d706e	2536	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2537	#pragma pack(1)
bogdanm	82:6473597d706e	2538	typedef struct _hw_adc
bogdanm	82:6473597d706e	2539	{
bogdanm	82:6473597d706e	2540	__IO hw_adc_sc1n_t SC1n[2]; //!< [0x0] ADC Status and Control Registers 1
bogdanm	82:6473597d706e	2541	__IO hw_adc_cfg1_t CFG1; //!< [0x8] ADC Configuration Register 1
bogdanm	82:6473597d706e	2542	__IO hw_adc_cfg2_t CFG2; //!< [0xC] ADC Configuration Register 2
bogdanm	82:6473597d706e	2543	__I hw_adc_rn_t Rn[2]; //!< [0x10] ADC Data Result Register
bogdanm	82:6473597d706e	2544	__IO hw_adc_cv1_t CV1; //!< [0x18] Compare Value Registers
bogdanm	82:6473597d706e	2545	__IO hw_adc_cv2_t CV2; //!< [0x1C] Compare Value Registers
bogdanm	82:6473597d706e	2546	__IO hw_adc_sc2_t SC2; //!< [0x20] Status and Control Register 2
bogdanm	82:6473597d706e	2547	__IO hw_adc_sc3_t SC3; //!< [0x24] Status and Control Register 3
bogdanm	82:6473597d706e	2548	__IO hw_adc_ofs_t OFS; //!< [0x28] ADC Offset Correction Register
bogdanm	82:6473597d706e	2549	__IO hw_adc_pg_t PG; //!< [0x2C] ADC Plus-Side Gain Register
bogdanm	82:6473597d706e	2550	__IO hw_adc_mg_t MG; //!< [0x30] ADC Minus-Side Gain Register
bogdanm	82:6473597d706e	2551	__IO hw_adc_clpd_t CLPD; //!< [0x34] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2552	__IO hw_adc_clps_t CLPS; //!< [0x38] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2553	__IO hw_adc_clp4_t CLP4; //!< [0x3C] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2554	__IO hw_adc_clp3_t CLP3; //!< [0x40] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2555	__IO hw_adc_clp2_t CLP2; //!< [0x44] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2556	__IO hw_adc_clp1_t CLP1; //!< [0x48] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2557	__IO hw_adc_clp0_t CLP0; //!< [0x4C] ADC Plus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2558	uint8_t _reserved0[4];
bogdanm	82:6473597d706e	2559	__IO hw_adc_clmd_t CLMD; //!< [0x54] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2560	__IO hw_adc_clms_t CLMS; //!< [0x58] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2561	__IO hw_adc_clm4_t CLM4; //!< [0x5C] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2562	__IO hw_adc_clm3_t CLM3; //!< [0x60] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2563	__IO hw_adc_clm2_t CLM2; //!< [0x64] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2564	__IO hw_adc_clm1_t CLM1; //!< [0x68] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2565	__IO hw_adc_clm0_t CLM0; //!< [0x6C] ADC Minus-Side General Calibration Value Register
bogdanm	82:6473597d706e	2566	} hw_adc_t;
bogdanm	82:6473597d706e	2567	#pragma pack()
bogdanm	82:6473597d706e	2568
bogdanm	82:6473597d706e	2569	//! @brief Macro to access all ADC registers.
bogdanm	82:6473597d706e	2570	//! @param x ADC instance number.
bogdanm	82:6473597d706e	2571	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	2572	//! use the '&' operator, like <code>&HW_ADC(0)</code>.
bogdanm	82:6473597d706e	2573	#define HW_ADC(x) ((hw_adc_t ) REGS_ADC_BASE(x))
bogdanm	82:6473597d706e	2574	#endif
bogdanm	82:6473597d706e	2575
bogdanm	82:6473597d706e	2576	#endif // __HW_ADC_REGISTERS_H__
bogdanm	82:6473597d706e	2577	// v22/130726/0.9
bogdanm	82:6473597d706e	2578	// EOF

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Type:	Library
Created:	05 Dec 2014
Imports:	4
Forks:	0
Commits:	94
Dependents:	0
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_adc.h@82:6473597d706e, 2014-04-07 (annotated)

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