frederic blanc / ADC128D818

12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interface

Dependents:   ADC128D818_HelloWorld

ADC128D818.h@1:5f9dbbbc34c5, 2013-09-02 (annotated)

Committer:
fblanc
Date:
Mon Sep 02 11:39:46 2013 +0000
Revision:
1:5f9dbbbc34c5
Parent:
0:9cc68ef524da
Child:
2:f9a0518b352a
doc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fblanc 1:5f9dbbbc34c5 1 /**
fblanc 1:5f9dbbbc34c5 2 * @brief ADC128D818 12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interfac
fblanc 1:5f9dbbbc34c5 3 * http://www.ti.com/product/adc128d818/
fblanc 1:5f9dbbbc34c5 4 * @date 02/09/2013
fblanc 1:5f9dbbbc34c5 5 * @author F.BLANC LAAS-CNRS
fblanc 1:5f9dbbbc34c5 6 * http://homepages.laas.fr/fblanc/
fblanc 1:5f9dbbbc34c5 7 */
fblanc 0:9cc68ef524da 8
fblanc 0:9cc68ef524da 9 #ifndef ADC128D818_H
fblanc 0:9cc68ef524da 10
fblanc 0:9cc68ef524da 11 #define ADC128D818_H
fblanc 0:9cc68ef524da 12
fblanc 0:9cc68ef524da 13 #include "mbed.h"
fblanc 0:9cc68ef524da 14
fblanc 0:9cc68ef524da 15
fblanc 0:9cc68ef524da 16 //Library for the ADC128D818 12 BIT ADC.
fblanc 0:9cc68ef524da 17 enum ADC_MODE {
fblanc 0:9cc68ef524da 18 ADC_MODE_0 = 0x00,
fblanc 0:9cc68ef524da 19 ADC_MODE_1 = 0x01,
fblanc 0:9cc68ef524da 20 ADC_MODE_2 = 0x02,
fblanc 0:9cc68ef524da 21 ADC_MODE_3 = 0x03
fblanc 0:9cc68ef524da 22 };
fblanc 0:9cc68ef524da 23 enum ADC_ADDRESS {
fblanc 0:9cc68ef524da 24 ADC_ADDRESS_LOW_LOW = 0x1D,
fblanc 0:9cc68ef524da 25 ADC_ADDRESS_LOW_MID = 0x1E,
fblanc 0:9cc68ef524da 26 ADC_ADDRESS_LOW_HIGH = 0x1F,
fblanc 0:9cc68ef524da 27 ADC_ADDRESS_MID_LOW = 0x2D,
fblanc 0:9cc68ef524da 28 ADC_ADDRESS_MID_MID = 0x2E,
fblanc 0:9cc68ef524da 29 ADC_ADDRESS_MID_HIGH = 0x2F,
fblanc 0:9cc68ef524da 30 ADC_ADDRESS_HIGH_LOW = 0x35,
fblanc 0:9cc68ef524da 31 ADC_ADDRESS_HIGH_MID = 0x36,
fblanc 0:9cc68ef524da 32 ADC_ADDRESS_HIGH_HIGH = 0x37
fblanc 0:9cc68ef524da 33 };
fblanc 0:9cc68ef524da 34 enum ADC_VREF {
fblanc 0:9cc68ef524da 35 ADC_VREF_INT = 0x00,
fblanc 0:9cc68ef524da 36 ADC_VREF_EXT = 0x01
fblanc 0:9cc68ef524da 37 };
fblanc 0:9cc68ef524da 38 enum ADC_RATE {
fblanc 0:9cc68ef524da 39 ADC_RATE_LOW_POWER = 0x00,
fblanc 0:9cc68ef524da 40 ADC_RATE_CONTINUOUS = 0x01
fblanc 0:9cc68ef524da 41 };
fblanc 0:9cc68ef524da 42 enum ADC_LIMIT {
fblanc 0:9cc68ef524da 43 ADC_LIMIT_HIGH = 0x00,
fblanc 0:9cc68ef524da 44 ADC_LIMIT_LOW = 0x01
fblanc 0:9cc68ef524da 45 };
fblanc 0:9cc68ef524da 46 enum ADC_CHANNEL {
fblanc 0:9cc68ef524da 47 ADC_CHANNEL_IN0 = 0x00,
fblanc 0:9cc68ef524da 48 ADC_CHANNEL_IN1 = 0x01,
fblanc 0:9cc68ef524da 49 ADC_CHANNEL_IN2 = 0x02,
fblanc 0:9cc68ef524da 50 ADC_CHANNEL_IN3 = 0x03,
fblanc 0:9cc68ef524da 51 ADC_CHANNEL_IN4 = 0x04,
fblanc 0:9cc68ef524da 52 ADC_CHANNEL_IN5 = 0x05,
fblanc 0:9cc68ef524da 53 ADC_CHANNEL_IN6 = 0x06,
fblanc 0:9cc68ef524da 54 ADC_CHANNEL_IN7 = 0x07,
fblanc 0:9cc68ef524da 55 ADC_CHANNEL_TEMP = 0x07
fblanc 0:9cc68ef524da 56 };
fblanc 1:5f9dbbbc34c5 57 enum ADC_INT {
fblanc 1:5f9dbbbc34c5 58
fblanc 1:5f9dbbbc34c5 59 ADC_INT_IN0 = (char)~(0x01 <<0),
fblanc 1:5f9dbbbc34c5 60 ADC_INT_IN1 = (char)~(0x01 <<1),
fblanc 1:5f9dbbbc34c5 61 ADC_INT_IN2 = (char)~(0x01 <<2),
fblanc 1:5f9dbbbc34c5 62 ADC_INT_IN3 = (char)~(0x01 <<3),
fblanc 1:5f9dbbbc34c5 63 ADC_INT_IN4 = (char)~(0x01 <<4),
fblanc 1:5f9dbbbc34c5 64 ADC_INT_IN5 = (char)~(0x01 <<5),
fblanc 1:5f9dbbbc34c5 65 ADC_INT_IN6 = (char)~(0x01 <<6),
fblanc 1:5f9dbbbc34c5 66 ADC_INT_IN7 = (char)~(0x01 <<7),
fblanc 1:5f9dbbbc34c5 67 ADC_INT_TEMP = (char)~(0x01 <<7),
fblanc 1:5f9dbbbc34c5 68 ADC_INT_ALL = 0x00
fblanc 1:5f9dbbbc34c5 69 };
fblanc 1:5f9dbbbc34c5 70 enum ADC_ENABLE {
fblanc 1:5f9dbbbc34c5 71
fblanc 1:5f9dbbbc34c5 72 ADC_ENABLE_IN0 = (char)~(0x01 <<0),
fblanc 1:5f9dbbbc34c5 73 ADC_ENABLE_IN1 = (char)~(0x01 <<1),
fblanc 1:5f9dbbbc34c5 74 ADC_ENABLE_IN2 = (char)~(0x01 <<2),
fblanc 1:5f9dbbbc34c5 75 ADC_ENABLE_IN3 = (char)~(0x01 <<3),
fblanc 1:5f9dbbbc34c5 76 ADC_ENABLE_IN4 = (char)~(0x01 <<4),
fblanc 1:5f9dbbbc34c5 77 ADC_ENABLE_IN5 = (char)~(0x01 <<5),
fblanc 1:5f9dbbbc34c5 78 ADC_ENABLE_IN6 = (char)~(0x01 <<6),
fblanc 1:5f9dbbbc34c5 79 ADC_ENABLE_IN7 = (char)~(0x01 <<7),
fblanc 1:5f9dbbbc34c5 80 ADC_ENABLE_TEMP = ~(0x01 <<7),
fblanc 1:5f9dbbbc34c5 81 ADC_ENABLE_ALL = 0x00
fblanc 1:5f9dbbbc34c5 82 };
fblanc 0:9cc68ef524da 83 enum ADC_REG {
fblanc 0:9cc68ef524da 84 ADC_REG_Configuration_Register = 0x00,
fblanc 0:9cc68ef524da 85 ADC_REG_Interrupt_Status_Register = 0x01,
fblanc 0:9cc68ef524da 86 ADC_REG_Interrupt_Mask_Register = 0x03,
fblanc 0:9cc68ef524da 87 ADC_REG_Conversion_Rate_Register = 0x07,
fblanc 0:9cc68ef524da 88 ADC_REG_Channel_Disable_Register = 0x08,
fblanc 0:9cc68ef524da 89 ADC_REG_One_Shot_Register = 0x09,
fblanc 0:9cc68ef524da 90 ADC_REG_Deep_Shutdown_Register = 0x0A,
fblanc 0:9cc68ef524da 91 ADC_REG_Advanced_Configuration_Register = 0x0B,
fblanc 0:9cc68ef524da 92 ADC_REG_Busy_Status_Register = 0x0C,
fblanc 0:9cc68ef524da 93 ADC_REG_Channel_Readings_Registers = 0x20,
fblanc 0:9cc68ef524da 94 ADC_REG_Limit_Registers = 0x2A,
fblanc 0:9cc68ef524da 95 ADC_REG_Manufacturer_ID_Register = 0x3E,
fblanc 0:9cc68ef524da 96 ADC_REG_Revision_ID_Register = 0x3F
fblanc 0:9cc68ef524da 97 };
fblanc 0:9cc68ef524da 98 class ADC128D818
fblanc 0:9cc68ef524da 99 {
fblanc 0:9cc68ef524da 100 protected:
fblanc 0:9cc68ef524da 101
fblanc 0:9cc68ef524da 102
fblanc 0:9cc68ef524da 103 enum Configuration_Register {
fblanc 0:9cc68ef524da 104 Configuration_Register_Start = 1<<0,
fblanc 0:9cc68ef524da 105 Configuration_Register_INT_Enable = 1<<1,
fblanc 0:9cc68ef524da 106 Configuration_Register_INT_Clear = 1<<3,
fblanc 0:9cc68ef524da 107 Configuration_Register_Initialization = 1<<7
fblanc 0:9cc68ef524da 108 };
fblanc 0:9cc68ef524da 109
fblanc 0:9cc68ef524da 110 enum Busy_Status_Register {
fblanc 0:9cc68ef524da 111 Busy_Status_Register_Busy = 1<<0,
fblanc 0:9cc68ef524da 112 Busy_Status_Register_Not_Ready = 1<<1
fblanc 0:9cc68ef524da 113 };
fblanc 0:9cc68ef524da 114
fblanc 0:9cc68ef524da 115 enum Advanced_Configuration_Register {
fblanc 0:9cc68ef524da 116 Advanced_Configuration_Register_External_Reference_Enable = 1<<0,
fblanc 0:9cc68ef524da 117 Advanced_Configuration_Register_Mode_Select_0 = 1<<1,
fblanc 0:9cc68ef524da 118 Advanced_Configuration_Register_Mode_Select_1 = 1<<2
fblanc 0:9cc68ef524da 119 };
fblanc 0:9cc68ef524da 120
fblanc 0:9cc68ef524da 121 enum Conversion_Rate_Register {
fblanc 0:9cc68ef524da 122 Conversion_Rate_Register_Rate_Register = 1<<0
fblanc 0:9cc68ef524da 123 };
fblanc 0:9cc68ef524da 124
fblanc 0:9cc68ef524da 125
fblanc 0:9cc68ef524da 126 private:
fblanc 0:9cc68ef524da 127 I2C _i2c;
fblanc 0:9cc68ef524da 128 char _data[2];
fblanc 0:9cc68ef524da 129 char _address;
fblanc 0:9cc68ef524da 130 char _mode;
fblanc 0:9cc68ef524da 131
fblanc 0:9cc68ef524da 132 public:
fblanc 0:9cc68ef524da 133
fblanc 0:9cc68ef524da 134 ADC128D818(PinName sda, PinName scl, PinName adc_int );
fblanc 0:9cc68ef524da 135 ~ADC128D818();
fblanc 0:9cc68ef524da 136
fblanc 0:9cc68ef524da 137 InterruptIn _Adc_Int;
fblanc 0:9cc68ef524da 138 int read_channel(char channel);
fblanc 0:9cc68ef524da 139 char read_register(char Register);
fblanc 0:9cc68ef524da 140 int init(char address, char mode, char vref, char rate, char mask_channel, char mask_int);
fblanc 1:5f9dbbbc34c5 141 int init_limit(char channel, char limit, char high_low);
fblanc 0:9cc68ef524da 142 void start();
fblanc 0:9cc68ef524da 143 void stop();
fblanc 0:9cc68ef524da 144 };
fblanc 0:9cc68ef524da 145
fblanc 0:9cc68ef524da 146 #endif
fblanc 0:9cc68ef524da 147