COMPACT_FLASH - Compact Flash I/O test

Users » emh203 » Code » COMPACT_FLASH

Eli Hughes / Mbed 2 deprecated COMPACT_FLASH

Compact Flash I/O test

FAT_FS/diskio.c@1:dc171f34db9b, 2011-12-30 (annotated)

Committer:: emh203
Date:: Fri Dec 30 21:02:16 2011 +0000
Revision:: 1:dc171f34db9b
Parent:: 0:6b1e6c9e48ba

Who changed what in which revision?

User	Revision	Line number	New contents of line
emh203	0:6b1e6c9e48ba	1	#include "mbed.h"
emh203	0:6b1e6c9e48ba	2	#include "LPC17xx.h"
emh203	0:6b1e6c9e48ba	3	#include "integer.h"
emh203	0:6b1e6c9e48ba	4	#include "diskio.h"
emh203	0:6b1e6c9e48ba	5	#include "stdarg.h"
emh203	1:dc171f34db9b	6	#include "usbhost_inc.h"
emh203	0:6b1e6c9e48ba	7
emh203	1:dc171f34db9b	8
emh203	1:dc171f34db9b	9	/*--------------------------------------------------------------------------
emh203	1:dc171f34db9b	10
emh203	1:dc171f34db9b	11	Module Private Functions
emh203	1:dc171f34db9b	12
emh203	1:dc171f34db9b	13	---------------------------------------------------------------------------*/
emh203	1:dc171f34db9b	14
emh203	1:dc171f34db9b	15	static volatile DSTATUS Stat[3] = {STA_NOINIT \| STA_NODISK}; /* Disk status */
emh203	1:dc171f34db9b	16	static volatile BYTE DiskProcTimer[3]={0}; /* 100Hz decrement timer */
emh203	1:dc171f34db9b	17
emh203	1:dc171f34db9b	18
emh203	1:dc171f34db9b	19	BYTE RAM_DISK[512];
emh203	1:dc171f34db9b	20
emh203	1:dc171f34db9b	21
emh203	1:dc171f34db9b	22	//Usb Stuff
emh203	1:dc171f34db9b	23	uint32_t _numBlks;
emh203	1:dc171f34db9b	24	uint32_t _blkSize;
emh203	1:dc171f34db9b	25	USB_INT08U inquiryResult[INQUIRY_LENGTH];
emh203	1:dc171f34db9b	26
emh203	1:dc171f34db9b	27
emh203	1:dc171f34db9b	28	//#define _CF_DEBUG_MESSAGES
emh203	0:6b1e6c9e48ba	29	//#define _CF_DEBUG_READ_ATA
emh203	0:6b1e6c9e48ba	30
emh203	0:6b1e6c9e48ba	31	#ifdef _CF_DEBUG_MESSAGES
emh203	0:6b1e6c9e48ba	32	#define CF_DEBUG(...) printf(__VA_ARGS__)
emh203	0:6b1e6c9e48ba	33	#else
emh203	0:6b1e6c9e48ba	34	#define CF_DEBUG
emh203	0:6b1e6c9e48ba	35	#endif
emh203	0:6b1e6c9e48ba	36
emh203	0:6b1e6c9e48ba	37	void disk_timerproc (void);
emh203	0:6b1e6c9e48ba	38
emh203	0:6b1e6c9e48ba	39	#define LED1_MASK (uint32_t )(1<<18)
emh203	0:6b1e6c9e48ba	40	#define LED2_MASK (uint32_t )(1<<20)
emh203	0:6b1e6c9e48ba	41	#define LED3_MASK (uint32_t )(1<<21)
emh203	0:6b1e6c9e48ba	42	#define LED4_MASK (uint32_t )(1<<23)
emh203	0:6b1e6c9e48ba	43
emh203	0:6b1e6c9e48ba	44
emh203	0:6b1e6c9e48ba	45	#define LED1_ON LPC_GPIO1->FIOSET=LED1_MASK
emh203	0:6b1e6c9e48ba	46	#define LED1_OFF LPC_GPIO1->FIOCLR=LED1_MASK
emh203	0:6b1e6c9e48ba	47	#define LED1_TOGGLE LPC_GPIO1->FIOPIN^=LED1_MASK
emh203	0:6b1e6c9e48ba	48
emh203	0:6b1e6c9e48ba	49	#define LED2_ON LPC_GPIO1->FIOSET=LED2_MASK
emh203	0:6b1e6c9e48ba	50	#define LED2_OFF LPC_GPIO1->FIOCLR=LED2_MASK
emh203	0:6b1e6c9e48ba	51	#define LED2_TOGGLE LPC_GPIO1->FIOPIN^=LED2_MASK
emh203	0:6b1e6c9e48ba	52
emh203	0:6b1e6c9e48ba	53	#define LED3_ON LPC_GPIO1->FIOSET=LED3_MASK
emh203	0:6b1e6c9e48ba	54	#define LED3_OFF LPC_GPIO1->FIOCLR=LED3_MASK
emh203	0:6b1e6c9e48ba	55	#define LED3_TOGGLE LPC_GPIO1->FIOPIN^=LED3_MASK
emh203	0:6b1e6c9e48ba	56
emh203	0:6b1e6c9e48ba	57	#define LED4_ON LPC_GPIO1->FIOSET=LED4_MASK
emh203	0:6b1e6c9e48ba	58	#define LED4_OFF LPC_GPIO1->FIOCLR=LED4_MASK
emh203	0:6b1e6c9e48ba	59	#define LED4_TOGGLE LPC_GPIO1->FIOPIN^=LED4_MASK
emh203	0:6b1e6c9e48ba	60
emh203	0:6b1e6c9e48ba	61
emh203	0:6b1e6c9e48ba	62
emh203	0:6b1e6c9e48ba	63	//8-bit Data Bus is on Pins P0.4 - P0.11
emh203	0:6b1e6c9e48ba	64	#define DATA_BUS_MASK (uint32_t )((0xFF)<<4)
emh203	0:6b1e6c9e48ba	65
emh203	0:6b1e6c9e48ba	66	//3 bit address is on Port 2.0 - 2.2
emh203	0:6b1e6c9e48ba	67	#define ADDRESS_BUS_MASK (uint32_t )(0x7)
emh203	0:6b1e6c9e48ba	68
emh203	0:6b1e6c9e48ba	69	//ChipSelects are on port 2
emh203	0:6b1e6c9e48ba	70	#define CS0_MASK (uint32_t )(1<<3)
emh203	0:6b1e6c9e48ba	71	#define CS1_MASK (uint32_t )(1<<4)
emh203	0:6b1e6c9e48ba	72
emh203	0:6b1e6c9e48ba	73	//IORD and IOWR are on port 0
emh203	0:6b1e6c9e48ba	74	#define IORD_MASK (uint32_t )(1<<24)
emh203	0:6b1e6c9e48ba	75	#define IOWR_MASK (uint32_t )(1<<23)
emh203	0:6b1e6c9e48ba	76
emh203	0:6b1e6c9e48ba	77
emh203	0:6b1e6c9e48ba	78	//Reset and power enable are on port 1
emh203	0:6b1e6c9e48ba	79	#define COMPACT_FLASH_RESET_MASK (uint32_t )(1<<30)
emh203	0:6b1e6c9e48ba	80	#define COMPACT_FLASH_POWER_ENABLE_MASK (uint32_t )(0x80000000)
emh203	0:6b1e6c9e48ba	81	//Card Detect is on Port 2
emh203	0:6b1e6c9e48ba	82	#define COMPACT_FLASH_CARD_DETECT_MASK (uint32_t )(1<<5)
emh203	0:6b1e6c9e48ba	83
emh203	0:6b1e6c9e48ba	84	//Low Level Bus Operation Macros
emh203	0:6b1e6c9e48ba	85	//Note: LPC 176x have dedicate set and clear registers
emh203	0:6b1e6c9e48ba	86
emh203	0:6b1e6c9e48ba	87	#define SET_DATA_BUS_TO_INPUTS LPC_GPIO0->FIODIR &= ~(DATA_BUS_MASK);
emh203	0:6b1e6c9e48ba	88	#define SET_DATA_BUS_TO_OUTPUT LPC_GPIO0->FIODIR \|= (DATA_BUS_MASK);
emh203	0:6b1e6c9e48ba	89
emh203	0:6b1e6c9e48ba	90	#define CS0_ACTIVE LPC_GPIO2->FIOCLR = CS0_MASK
emh203	0:6b1e6c9e48ba	91	#define CS0_INACTIVE LPC_GPIO2->FIOSET = CS0_MASK
emh203	0:6b1e6c9e48ba	92	#define CS1_ACTIVE LPC_GPIO2->FIOCLR = CS1_MASK
emh203	0:6b1e6c9e48ba	93	#define CS1_INACTIVE LPC_GPIO2->FIOSET = CS1_MASK
emh203	0:6b1e6c9e48ba	94
emh203	0:6b1e6c9e48ba	95	#define IORD_ACTIVE LPC_GPIO0->FIOCLR = IORD_MASK
emh203	0:6b1e6c9e48ba	96	#define IORD_INACTIVE LPC_GPIO0->FIOSET = IORD_MASK
emh203	0:6b1e6c9e48ba	97
emh203	0:6b1e6c9e48ba	98	#define IOWR_ACTIVE LPC_GPIO0->FIOCLR = IOWR_MASK
emh203	0:6b1e6c9e48ba	99	#define IOWR_INACTIVE LPC_GPIO0->FIOSET = IOWR_MASK
emh203	0:6b1e6c9e48ba	100
emh203	0:6b1e6c9e48ba	101	#define COMPACT_FLASH_RESET_ACTIVE LPC_GPIO1->FIOCLR = COMPACT_FLASH_RESET_MASK
emh203	0:6b1e6c9e48ba	102	#define COMPACT_FLASH_RESET_INACTIVE LPC_GPIO1->FIOSET = COMPACT_FLASH_RESET_MASK
emh203	0:6b1e6c9e48ba	103
emh203	0:6b1e6c9e48ba	104	#define COMPACT_FLASH_POWER_ENABLE LPC_GPIO1->FIOCLR = COMPACT_FLASH_POWER_ENABLE_MASK
emh203	0:6b1e6c9e48ba	105	#define COMPACT_FLASH_POWER_DISABLE LPC_GPIO1->FIOSET = COMPACT_FLASH_POWER_ENABLE_MASK
emh203	0:6b1e6c9e48ba	106
emh203	0:6b1e6c9e48ba	107	#define COMPACT_FLASH_CARD_DETECTED (!((LPC_GPIO2->FIOPIN)&COMPACT_FLASH_CARD_DETECT_MASK))
emh203	0:6b1e6c9e48ba	108
emh203	0:6b1e6c9e48ba	109	//To set the Address and Data Bus Lines we will use the convient Mask register in the Port I/O modules
emh203	0:6b1e6c9e48ba	110	//The Hardware will mask out pins that are set to 1 in the MASK register
emh203	0:6b1e6c9e48ba	111
emh203	0:6b1e6c9e48ba	112	#define SET_CF_ADDRESS(ADDRESS) LPC_GPIO2->FIOMASK=~(ADDRESS_BUS_MASK); \
emh203	0:6b1e6c9e48ba	113	LPC_GPIO2->FIOPIN=ADDRESS; \
emh203	0:6b1e6c9e48ba	114	LPC_GPIO2->FIOMASK=0 //Always remember to reset the mask for other operations to complete correctly
emh203	0:6b1e6c9e48ba	115
emh203	0:6b1e6c9e48ba	116
emh203	0:6b1e6c9e48ba	117	#define SET_CF_DATA(DATA) LPC_GPIO0->FIOMASK=~(DATA_BUS_MASK); \
emh203	0:6b1e6c9e48ba	118	LPC_GPIO0->FIOPIN=(((uint32_t)DATA)<<4); \
emh203	0:6b1e6c9e48ba	119	LPC_GPIO0->FIOMASK=0 //Always remember to reset the mask for other operations to complete correctly
emh203	0:6b1e6c9e48ba	120
emh203	0:6b1e6c9e48ba	121	#define GET_CF_DATA(DATA) LPC_GPIO0->FIOMASK=~(DATA_BUS_MASK); \
emh203	0:6b1e6c9e48ba	122	(DATA) = (LPC_GPIO0->FIOPIN)>>4; \
emh203	0:6b1e6c9e48ba	123	LPC_GPIO0->FIOMASK=0 //Always remember to reset the mask for other operations to complete correctly
emh203	0:6b1e6c9e48ba	124
emh203	0:6b1e6c9e48ba	125	#define SET_DATA_BUS_AS_OUTPUTS LPC_GPIO0->FIODIR\|=DATA_BUS_MASK
emh203	0:6b1e6c9e48ba	126	#define SET_DATA_BUS_AS_INPUTS LPC_GPIO0->FIODIR&=~DATA_BUS_MASK
emh203	0:6b1e6c9e48ba	127
emh203	0:6b1e6c9e48ba	128	/* ATA command */
emh203	0:6b1e6c9e48ba	129	#define CMD_RESET 0x08 /* DEVICE RESET */
emh203	1:dc171f34db9b	130	#define CMD_READ 0x20 /* READ SECTOR(S) */
emh203	0:6b1e6c9e48ba	131	#define CMD_WRITE 0x30 /* WRITE SECTOR(S) */
emh203	1:dc171f34db9b	132	#define CMD_IDENTIFY 0xEC /* DEVICE IDENTIFY */
emh203	1:dc171f34db9b	133	#define CMD_SETFEATURES 0xEF /* SET FEATURES */
emh203	0:6b1e6c9e48ba	134
emh203	0:6b1e6c9e48ba	135	/* ATA register bit definitions */
emh203	0:6b1e6c9e48ba	136	#define LBA 0xE0
emh203	0:6b1e6c9e48ba	137	#define BUSY 0x80
emh203	0:6b1e6c9e48ba	138	#define DRDY 0x40
emh203	1:dc171f34db9b	139	#define DF 0x20
emh203	1:dc171f34db9b	140	#define DRQ 0x08
emh203	1:dc171f34db9b	141	#define ERR 0x01
emh203	0:6b1e6c9e48ba	142	#define SRST 0x40
emh203	0:6b1e6c9e48ba	143	#define nIEN 0x20
emh203	0:6b1e6c9e48ba	144
emh203	0:6b1e6c9e48ba	145	/* Bit definitions for Control Port */
emh203	0:6b1e6c9e48ba	146	#define CTL_READ 0x20
emh203	1:dc171f34db9b	147	#define CTL_WRITE 0x40
emh203	1:dc171f34db9b	148	#define CTL_RESET 0x80
emh203	0:6b1e6c9e48ba	149	#define REG_DATA 0x0
emh203	1:dc171f34db9b	150	#define REG_ERROR 0x1
emh203	0:6b1e6c9e48ba	151	#define REG_FEATURES 0x1
emh203	1:dc171f34db9b	152	#define REG_COUNT 0x2
emh203	1:dc171f34db9b	153	#define REG_SECTOR 0x3
emh203	0:6b1e6c9e48ba	154	#define REG_CYLL 0x4
emh203	0:6b1e6c9e48ba	155	#define REG_CYLH 0x5
emh203	1:dc171f34db9b	156	#define REG_DEV 0x6
emh203	1:dc171f34db9b	157	#define REG_COMMAND 0x7
emh203	1:dc171f34db9b	158	#define REG_STATUS 0x7
emh203	1:dc171f34db9b	159	#define REG_DEVCTRL 0xE
emh203	1:dc171f34db9b	160	#define REG_ALTSTAT 0xE
emh203	0:6b1e6c9e48ba	161
emh203	0:6b1e6c9e48ba	162	void InitCompactFlashInterface()
emh203	0:6b1e6c9e48ba	163	{
emh203	0:6b1e6c9e48ba	164	SET_DATA_BUS_AS_INPUTS;
emh203	0:6b1e6c9e48ba	165
emh203	0:6b1e6c9e48ba	166	LPC_GPIO2->FIODIR \|= ADDRESS_BUS_MASK \| CS0_MASK \| CS1_MASK;
emh203	0:6b1e6c9e48ba	167	LPC_GPIO2->FIODIR &=~(COMPACT_FLASH_CARD_DETECT_MASK);
emh203	0:6b1e6c9e48ba	168	LPC_GPIO1->FIODIR \|= COMPACT_FLASH_RESET_MASK \| COMPACT_FLASH_POWER_ENABLE_MASK \| LED1_MASK \| LED2_MASK \| LED3_MASK \| LED4_MASK;
emh203	0:6b1e6c9e48ba	169	LPC_GPIO0->FIODIR \|= IORD_MASK \| IOWR_MASK ;
emh203	0:6b1e6c9e48ba	170
emh203	0:6b1e6c9e48ba	171	COMPACT_FLASH_RESET_ACTIVE;
emh203	0:6b1e6c9e48ba	172	COMPACT_FLASH_POWER_DISABLE;
emh203	0:6b1e6c9e48ba	173	CS0_INACTIVE;
emh203	0:6b1e6c9e48ba	174	CS1_INACTIVE;
emh203	0:6b1e6c9e48ba	175
emh203	0:6b1e6c9e48ba	176	SysTick_Config(SystemCoreClock/100);
emh203	0:6b1e6c9e48ba	177	NVIC_SetVector(SysTick_IRQn, (uint32_t)(&disk_timerproc));
emh203	0:6b1e6c9e48ba	178	}
emh203	0:6b1e6c9e48ba	179
emh203	0:6b1e6c9e48ba	180	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	181	/* Read an ATA register */
emh203	0:6b1e6c9e48ba	182	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	183
emh203	0:6b1e6c9e48ba	184	static
emh203	0:6b1e6c9e48ba	185	BYTE read_ata (
emh203	0:6b1e6c9e48ba	186	BYTE reg /* Register to be read */
emh203	0:6b1e6c9e48ba	187	)
emh203	0:6b1e6c9e48ba	188	{
emh203	0:6b1e6c9e48ba	189	BYTE rd;
emh203	1:dc171f34db9b	190
emh203	0:6b1e6c9e48ba	191	CS0_ACTIVE;
emh203	0:6b1e6c9e48ba	192	SET_DATA_BUS_AS_INPUTS;
emh203	0:6b1e6c9e48ba	193	SET_CF_ADDRESS(reg);
emh203	0:6b1e6c9e48ba	194	IORD_ACTIVE;
emh203	0:6b1e6c9e48ba	195	__nop();
emh203	0:6b1e6c9e48ba	196	__nop();
emh203	0:6b1e6c9e48ba	197	__nop();
emh203	0:6b1e6c9e48ba	198	__nop();
emh203	0:6b1e6c9e48ba	199
emh203	0:6b1e6c9e48ba	200	GET_CF_DATA(rd);
emh203	0:6b1e6c9e48ba	201	__nop();
emh203	0:6b1e6c9e48ba	202	__nop();
emh203	0:6b1e6c9e48ba	203	__nop();
emh203	0:6b1e6c9e48ba	204	__nop();
emh203	0:6b1e6c9e48ba	205	IORD_INACTIVE;
emh203	0:6b1e6c9e48ba	206	CS0_INACTIVE;
emh203	0:6b1e6c9e48ba	207	#ifdef _CF_DEBUG_READ_ATA
emh203	0:6b1e6c9e48ba	208	CF_DEBUG("rd 0x%2x\r\n",rd);
emh203	0:6b1e6c9e48ba	209	#endif
emh203	0:6b1e6c9e48ba	210	return rd;
emh203	0:6b1e6c9e48ba	211	}
emh203	0:6b1e6c9e48ba	212
emh203	0:6b1e6c9e48ba	213
emh203	0:6b1e6c9e48ba	214
emh203	0:6b1e6c9e48ba	215	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	216	/* Write a byte to an ATA register */
emh203	0:6b1e6c9e48ba	217	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	218
emh203	0:6b1e6c9e48ba	219	static
emh203	0:6b1e6c9e48ba	220	void write_ata (
emh203	0:6b1e6c9e48ba	221	BYTE reg, /* Register to be written */
emh203	0:6b1e6c9e48ba	222	BYTE dat /* Data to be written */
emh203	0:6b1e6c9e48ba	223	)
emh203	0:6b1e6c9e48ba	224	{
emh203	1:dc171f34db9b	225
emh203	0:6b1e6c9e48ba	226	__nop();
emh203	0:6b1e6c9e48ba	227	CS0_ACTIVE;
emh203	0:6b1e6c9e48ba	228	SET_DATA_BUS_AS_OUTPUTS;
emh203	0:6b1e6c9e48ba	229	SET_CF_ADDRESS(reg);
emh203	0:6b1e6c9e48ba	230	SET_CF_DATA(dat);
emh203	0:6b1e6c9e48ba	231	IOWR_ACTIVE;
emh203	0:6b1e6c9e48ba	232	__nop();
emh203	0:6b1e6c9e48ba	233	__nop();
emh203	0:6b1e6c9e48ba	234	__nop();
emh203	0:6b1e6c9e48ba	235	__nop();
emh203	0:6b1e6c9e48ba	236	IOWR_INACTIVE;
emh203	0:6b1e6c9e48ba	237	__nop();
emh203	0:6b1e6c9e48ba	238	__nop();
emh203	0:6b1e6c9e48ba	239	__nop();
emh203	0:6b1e6c9e48ba	240	__nop();
emh203	0:6b1e6c9e48ba	241	CS0_INACTIVE;
emh203	0:6b1e6c9e48ba	242	SET_DATA_BUS_AS_INPUTS;
emh203	0:6b1e6c9e48ba	243	}
emh203	0:6b1e6c9e48ba	244
emh203	0:6b1e6c9e48ba	245
emh203	0:6b1e6c9e48ba	246
emh203	0:6b1e6c9e48ba	247	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	248	/* Read a part of data block */
emh203	0:6b1e6c9e48ba	249	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	250
emh203	0:6b1e6c9e48ba	251	static
emh203	0:6b1e6c9e48ba	252	void read_part (
emh203	0:6b1e6c9e48ba	253	BYTE buff, / Data buffer to store read data */
emh203	0:6b1e6c9e48ba	254	BYTE ofs, /* Offset of the part of data in unit of word */
emh203	0:6b1e6c9e48ba	255	BYTE count /* Number of word to pick up */
emh203	0:6b1e6c9e48ba	256	)
emh203	0:6b1e6c9e48ba	257	{
emh203	0:6b1e6c9e48ba	258	BYTE c = 0, dl, dh;
emh203	0:6b1e6c9e48ba	259
emh203	0:6b1e6c9e48ba	260	SET_CF_ADDRESS(REG_DATA); /* Select Data register */
emh203	0:6b1e6c9e48ba	261	__nop();
emh203	0:6b1e6c9e48ba	262	__nop();
emh203	0:6b1e6c9e48ba	263
emh203	0:6b1e6c9e48ba	264	SET_DATA_BUS_AS_INPUTS;
emh203	0:6b1e6c9e48ba	265	CS0_ACTIVE;
emh203	0:6b1e6c9e48ba	266	__nop();
emh203	0:6b1e6c9e48ba	267	__nop();
emh203	0:6b1e6c9e48ba	268	do {
emh203	0:6b1e6c9e48ba	269	IORD_ACTIVE; /* IORD = L */
emh203	0:6b1e6c9e48ba	270	__nop();
emh203	0:6b1e6c9e48ba	271	__nop();
emh203	0:6b1e6c9e48ba	272	__nop();
emh203	0:6b1e6c9e48ba	273	__nop();
emh203	0:6b1e6c9e48ba	274	GET_CF_DATA(dl); /* Read Even data */
emh203	0:6b1e6c9e48ba	275	IORD_INACTIVE; /* IORD = H */
emh203	0:6b1e6c9e48ba	276	__nop();
emh203	0:6b1e6c9e48ba	277	__nop();
emh203	0:6b1e6c9e48ba	278	__nop();
emh203	0:6b1e6c9e48ba	279	__nop();
emh203	0:6b1e6c9e48ba	280	IORD_ACTIVE; /* IORD = L */
emh203	0:6b1e6c9e48ba	281	__nop();
emh203	0:6b1e6c9e48ba	282	__nop();
emh203	0:6b1e6c9e48ba	283	__nop();
emh203	0:6b1e6c9e48ba	284	__nop();
emh203	0:6b1e6c9e48ba	285	GET_CF_DATA(dh); /* Read Odd data */
emh203	0:6b1e6c9e48ba	286	IORD_INACTIVE; /* IORD = H */
emh203	0:6b1e6c9e48ba	287	__nop();
emh203	0:6b1e6c9e48ba	288	__nop();
emh203	0:6b1e6c9e48ba	289	__nop();
emh203	0:6b1e6c9e48ba	290	__nop();
emh203	0:6b1e6c9e48ba	291	if (count && (c >= ofs)) { /* Pick up a part of block */
emh203	0:6b1e6c9e48ba	292	*buff++ = dl;
emh203	0:6b1e6c9e48ba	293	*buff++ = dh;
emh203	0:6b1e6c9e48ba	294	count--;
emh203	0:6b1e6c9e48ba	295	}
emh203	0:6b1e6c9e48ba	296	} while (++c);
emh203	0:6b1e6c9e48ba	297	CS0_INACTIVE;
emh203	0:6b1e6c9e48ba	298
emh203	0:6b1e6c9e48ba	299	read_ata(REG_ALTSTAT);
emh203	0:6b1e6c9e48ba	300	read_ata(REG_STATUS);
emh203	0:6b1e6c9e48ba	301	}
emh203	0:6b1e6c9e48ba	302
emh203	0:6b1e6c9e48ba	303
emh203	0:6b1e6c9e48ba	304	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	305	/* Wait for Data Ready */
emh203	0:6b1e6c9e48ba	306	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	307
emh203	0:6b1e6c9e48ba	308	static
emh203	0:6b1e6c9e48ba	309	int wait_data (void)
emh203	0:6b1e6c9e48ba	310	{
emh203	0:6b1e6c9e48ba	311	BYTE s;
emh203	0:6b1e6c9e48ba	312
emh203	1:dc171f34db9b	313	DiskProcTimer[CF] = 100; /* Time out = 1 sec */
emh203	0:6b1e6c9e48ba	314	do {
emh203	1:dc171f34db9b	315	if (!DiskProcTimer[CF]) return 0; /* Abort when timeout occured */
emh203	0:6b1e6c9e48ba	316	s = read_ata(REG_STATUS); /* Get status */
emh203	0:6b1e6c9e48ba	317	} while ((s & (BUSY\|DRQ)) != DRQ); /* Wait for BUSY goes low and DRQ goes high */
emh203	0:6b1e6c9e48ba	318
emh203	0:6b1e6c9e48ba	319	read_ata(REG_ALTSTAT);
emh203	0:6b1e6c9e48ba	320	return 1;
emh203	0:6b1e6c9e48ba	321	}
emh203	0:6b1e6c9e48ba	322
emh203	0:6b1e6c9e48ba	323
emh203	0:6b1e6c9e48ba	324
emh203	0:6b1e6c9e48ba	325
emh203	0:6b1e6c9e48ba	326	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	327	/* Initialize Disk Drive */
emh203	0:6b1e6c9e48ba	328	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	329
emh203	0:6b1e6c9e48ba	330	DSTATUS disk_initialize (
emh203	1:dc171f34db9b	331	BYTE drv /* Physical drive number (0) */
emh203	0:6b1e6c9e48ba	332	)
emh203	0:6b1e6c9e48ba	333	{
emh203	1:dc171f34db9b	334	DSTATUS RetVal;
emh203	1:dc171f34db9b	335	USB_INT32S rc;
emh203	1:dc171f34db9b	336
emh203	1:dc171f34db9b	337	switch(drv)
emh203	1:dc171f34db9b	338	{
emh203	1:dc171f34db9b	339	case COMPACT_FLASH:
emh203	1:dc171f34db9b	340
emh203	1:dc171f34db9b	341	Stat[CF] \|= STA_NOINIT;
emh203	1:dc171f34db9b	342	for (DiskProcTimer[CF] = 10; DiskProcTimer[CF]; ); /* 100ms */
emh203	1:dc171f34db9b	343	if (Stat[CF] & STA_NODISK) return Stat[CF]; /* Exit when socket is empty */
emh203	1:dc171f34db9b	344	COMPACT_FLASH_POWER_ENABLE; /* Initialize CFC control port */
emh203	1:dc171f34db9b	345	for (DiskProcTimer[CF] = 1;DiskProcTimer[CF]; ); /* 10ms */
emh203	1:dc171f34db9b	346
emh203	1:dc171f34db9b	347	SET_DATA_BUS_AS_INPUTS;
emh203	1:dc171f34db9b	348	for (DiskProcTimer[CF] = 5; DiskProcTimer[CF]; ); /* 50ms */
emh203	1:dc171f34db9b	349	COMPACT_FLASH_RESET_INACTIVE;
emh203	1:dc171f34db9b	350	for (DiskProcTimer[CF] = 5; DiskProcTimer[CF]; ); /* 50ms */
emh203	1:dc171f34db9b	351	write_ata(REG_DEV, LBA); /* Select Device 0 */
emh203	1:dc171f34db9b	352	DiskProcTimer[CF] = 200;
emh203	1:dc171f34db9b	353
emh203	1:dc171f34db9b	354	do { /* Wait for card goes ready */
emh203	1:dc171f34db9b	355	if (!DiskProcTimer[CF])
emh203	1:dc171f34db9b	356	{
emh203	1:dc171f34db9b	357	CF_DEBUG("Timeout waiting for card BUSY to go inactive\r\n");
emh203	1:dc171f34db9b	358	return Stat[CF];
emh203	1:dc171f34db9b	359	}
emh203	1:dc171f34db9b	360	} while (read_ata(REG_STATUS) & BUSY);
emh203	1:dc171f34db9b	361
emh203	1:dc171f34db9b	362
emh203	1:dc171f34db9b	363	write_ata(REG_DEVCTRL, SRST \| nIEN); /* Software reset */
emh203	1:dc171f34db9b	364	for (DiskProcTimer[CF] = 2; DiskProcTimer[CF]; ); /* 20ms */
emh203	1:dc171f34db9b	365
emh203	1:dc171f34db9b	366	write_ata(REG_DEVCTRL, nIEN); /* Release software reset */
emh203	1:dc171f34db9b	367
emh203	1:dc171f34db9b	368	for (DiskProcTimer[CF] = 2; DiskProcTimer[CF]; ); /* 20ms */
emh203	1:dc171f34db9b	369
emh203	1:dc171f34db9b	370	DiskProcTimer[CF] = 200;
emh203	1:dc171f34db9b	371	do { /* Wait for card goes ready */
emh203	1:dc171f34db9b	372	if (!DiskProcTimer[CF])
emh203	1:dc171f34db9b	373	{
emh203	1:dc171f34db9b	374	CF_DEBUG("Timeout waiting for card DRDY\r\n");
emh203	1:dc171f34db9b	375	return Stat[CF];
emh203	1:dc171f34db9b	376	}
emh203	1:dc171f34db9b	377	} while ((read_ata(REG_STATUS) & (DRDY\|BUSY)) != DRDY);
emh203	1:dc171f34db9b	378
emh203	1:dc171f34db9b	379	CF_DEBUG("Setting to 8-bit PIO MOD\r\n");
emh203	1:dc171f34db9b	380	write_ata(REG_FEATURES, 0x01); /* Select 8-bit PIO transfer mode */
emh203	1:dc171f34db9b	381	write_ata(REG_COMMAND, CMD_SETFEATURES);
emh203	1:dc171f34db9b	382	DiskProcTimer[CF] = 200;
emh203	1:dc171f34db9b	383	do {
emh203	1:dc171f34db9b	384	if (!DiskProcTimer[CF])
emh203	1:dc171f34db9b	385	{
emh203	1:dc171f34db9b	386	CF_DEBUG("Timeout waiting after trying to call the SETFEATURES command\r\n");
emh203	1:dc171f34db9b	387	return Stat[CF];
emh203	1:dc171f34db9b	388	}
emh203	1:dc171f34db9b	389
emh203	1:dc171f34db9b	390	} while (read_ata(REG_STATUS) & (BUSY \| ERR));
emh203	1:dc171f34db9b	391
emh203	1:dc171f34db9b	392	Stat[CF] &= ~STA_NOINIT; /* When device goes ready, clear STA_NOINIT */
emh203	1:dc171f34db9b	393
emh203	1:dc171f34db9b	394	RetVal = Stat[CF];
emh203	1:dc171f34db9b	395
emh203	1:dc171f34db9b	396	break;
emh203	1:dc171f34db9b	397
emh203	1:dc171f34db9b	398	case USB:
emh203	1:dc171f34db9b	399
emh203	1:dc171f34db9b	400	Host_Init();
emh203	1:dc171f34db9b	401	if(!Host_EnumDev())
emh203	1:dc171f34db9b	402	{
emh203	1:dc171f34db9b	403
emh203	1:dc171f34db9b	404	rc = MS_Init( &_blkSize, &_numBlks, inquiryResult );
emh203	1:dc171f34db9b	405	if (rc != OK)
emh203	1:dc171f34db9b	406	{
emh203	1:dc171f34db9b	407	TERMINAL_PRINTF("Could not initialize mass storage interface: %d\r\n", rc);
emh203	1:dc171f34db9b	408	Stat[USB] \|= STA_NOINIT;
emh203	1:dc171f34db9b	409	}
emh203	1:dc171f34db9b	410	else
emh203	1:dc171f34db9b	411	{
emh203	1:dc171f34db9b	412	Stat[USB] &= ~STA_NOINIT;
emh203	1:dc171f34db9b	413	}
emh203	1:dc171f34db9b	414	}
emh203	1:dc171f34db9b	415	else
emh203	1:dc171f34db9b	416	{
emh203	1:dc171f34db9b	417	Stat[USB] \|= STA_NOINIT;
emh203	1:dc171f34db9b	418	}
emh203	1:dc171f34db9b	419
emh203	1:dc171f34db9b	420	RetVal = Stat[USB];
emh203	1:dc171f34db9b	421	break;
emh203	1:dc171f34db9b	422
emh203	1:dc171f34db9b	423
emh203	1:dc171f34db9b	424	case RAM:
emh203	1:dc171f34db9b	425	Stat[RAM] &= ~STA_NOINIT;
emh203	1:dc171f34db9b	426	RetVal = Stat[RAM];
emh203	1:dc171f34db9b	427	break;
emh203	1:dc171f34db9b	428
emh203	1:dc171f34db9b	429	default:
emh203	1:dc171f34db9b	430	RetVal = STA_NOINIT;
emh203	1:dc171f34db9b	431	break;
emh203	1:dc171f34db9b	432	}
emh203	0:6b1e6c9e48ba	433
emh203	1:dc171f34db9b	434	return RetVal;
emh203	0:6b1e6c9e48ba	435	}
emh203	0:6b1e6c9e48ba	436
emh203	0:6b1e6c9e48ba	437
emh203	0:6b1e6c9e48ba	438
emh203	0:6b1e6c9e48ba	439	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	440	/* Return Disk Status */
emh203	0:6b1e6c9e48ba	441	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	442
emh203	0:6b1e6c9e48ba	443	DSTATUS disk_status (
emh203	1:dc171f34db9b	444	BYTE drv
emh203	0:6b1e6c9e48ba	445	)
emh203	0:6b1e6c9e48ba	446	{
emh203	1:dc171f34db9b	447	DSTATUS RetVal;
emh203	1:dc171f34db9b	448
emh203	1:dc171f34db9b	449	switch(drv)
emh203	1:dc171f34db9b	450	{
emh203	1:dc171f34db9b	451	case CF:
emh203	1:dc171f34db9b	452	RetVal = Stat[CF];
emh203	1:dc171f34db9b	453	break;
emh203	1:dc171f34db9b	454
emh203	1:dc171f34db9b	455
emh203	1:dc171f34db9b	456	case USB:
emh203	1:dc171f34db9b	457	RetVal = Stat[USB];
emh203	1:dc171f34db9b	458	break;
emh203	1:dc171f34db9b	459
emh203	1:dc171f34db9b	460	case RAM:
emh203	1:dc171f34db9b	461	RetVal = Stat[RAM];
emh203	1:dc171f34db9b	462	break;
emh203	1:dc171f34db9b	463
emh203	1:dc171f34db9b	464	default:
emh203	1:dc171f34db9b	465	RetVal = STA_NOINIT;
emh203	1:dc171f34db9b	466	break;
emh203	1:dc171f34db9b	467	}
emh203	1:dc171f34db9b	468
emh203	1:dc171f34db9b	469	return RetVal;
emh203	0:6b1e6c9e48ba	470	}
emh203	0:6b1e6c9e48ba	471
emh203	0:6b1e6c9e48ba	472
emh203	0:6b1e6c9e48ba	473
emh203	0:6b1e6c9e48ba	474	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	475	/* Read Sector(s) */
emh203	0:6b1e6c9e48ba	476	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	477
emh203	0:6b1e6c9e48ba	478	DRESULT disk_read (
emh203	0:6b1e6c9e48ba	479	BYTE drv, /* Physical drive nmuber (0) */
emh203	0:6b1e6c9e48ba	480	BYTE buff, / Data buffer to store read data */
emh203	0:6b1e6c9e48ba	481	DWORD sector, /* Sector number (LBA) */
emh203	0:6b1e6c9e48ba	482	BYTE count /* Sector count (1..255) */
emh203	0:6b1e6c9e48ba	483	)
emh203	0:6b1e6c9e48ba	484	{
emh203	0:6b1e6c9e48ba	485	BYTE c;
emh203	1:dc171f34db9b	486	DWORD i,j;
emh203	0:6b1e6c9e48ba	487
emh203	1:dc171f34db9b	488	switch(drv)
emh203	1:dc171f34db9b	489	{
emh203	1:dc171f34db9b	490	case CF:
emh203	1:dc171f34db9b	491	if (Stat[CF] & STA_NOINIT) return RES_NOTRDY;
emh203	0:6b1e6c9e48ba	492
emh203	1:dc171f34db9b	493	/* Issue Read Setor(s) command */
emh203	1:dc171f34db9b	494	write_ata(REG_COUNT, count);
emh203	1:dc171f34db9b	495	write_ata(REG_SECTOR, (BYTE)sector);
emh203	1:dc171f34db9b	496	write_ata(REG_CYLL, (BYTE)(sector >> 8));
emh203	1:dc171f34db9b	497	write_ata(REG_CYLH, (BYTE)(sector >> 16));
emh203	1:dc171f34db9b	498	write_ata(REG_DEV, ((BYTE)(sector >> 24) & 0x0F) \| LBA);
emh203	1:dc171f34db9b	499	write_ata(REG_COMMAND, CMD_READ);
emh203	1:dc171f34db9b	500
emh203	1:dc171f34db9b	501	do {
emh203	1:dc171f34db9b	502	if (!wait_data()) return RES_ERROR; /* Wait data ready */
emh203	1:dc171f34db9b	503
emh203	1:dc171f34db9b	504	SET_CF_ADDRESS(REG_DATA);
emh203	1:dc171f34db9b	505	__nop();
emh203	1:dc171f34db9b	506	__nop();
emh203	1:dc171f34db9b	507	__nop();
emh203	1:dc171f34db9b	508	__nop();
emh203	1:dc171f34db9b	509	CS0_ACTIVE;
emh203	1:dc171f34db9b	510	c = 0;
emh203	1:dc171f34db9b	511
emh203	1:dc171f34db9b	512	__nop();
emh203	1:dc171f34db9b	513	__nop();
emh203	1:dc171f34db9b	514	__nop();
emh203	1:dc171f34db9b	515
emh203	1:dc171f34db9b	516	SET_DATA_BUS_AS_INPUTS;
emh203	1:dc171f34db9b	517	do {
emh203	1:dc171f34db9b	518	IORD_ACTIVE; /* IORD = L */
emh203	1:dc171f34db9b	519	__nop();
emh203	1:dc171f34db9b	520	__nop();
emh203	1:dc171f34db9b	521	__nop();
emh203	1:dc171f34db9b	522	GET_CF_DATA(buff++); / Get even data */
emh203	1:dc171f34db9b	523	__nop();
emh203	1:dc171f34db9b	524	__nop();
emh203	1:dc171f34db9b	525	__nop();
emh203	1:dc171f34db9b	526
emh203	1:dc171f34db9b	527	__nop();
emh203	1:dc171f34db9b	528	__nop();
emh203	1:dc171f34db9b	529	__nop();
emh203	1:dc171f34db9b	530
emh203	1:dc171f34db9b	531	IORD_INACTIVE; /* IORD = H */
emh203	1:dc171f34db9b	532	__nop();
emh203	1:dc171f34db9b	533	__nop();
emh203	1:dc171f34db9b	534	__nop();
emh203	1:dc171f34db9b	535
emh203	1:dc171f34db9b	536	IORD_ACTIVE; /* IORD = L */
emh203	1:dc171f34db9b	537	__nop();
emh203	1:dc171f34db9b	538	__nop();
emh203	1:dc171f34db9b	539	__nop();
emh203	1:dc171f34db9b	540
emh203	1:dc171f34db9b	541	GET_CF_DATA(buff++); / Get Odd data */
emh203	1:dc171f34db9b	542	__nop();
emh203	1:dc171f34db9b	543	__nop();
emh203	1:dc171f34db9b	544	__nop();
emh203	1:dc171f34db9b	545
emh203	1:dc171f34db9b	546	__nop();
emh203	1:dc171f34db9b	547	IORD_INACTIVE; /* IORD = H */
emh203	1:dc171f34db9b	548	__nop();
emh203	1:dc171f34db9b	549	__nop();
emh203	1:dc171f34db9b	550	__nop();
emh203	1:dc171f34db9b	551
emh203	1:dc171f34db9b	552
emh203	1:dc171f34db9b	553	} while (--c);
emh203	1:dc171f34db9b	554	} while (--count);
emh203	1:dc171f34db9b	555
emh203	1:dc171f34db9b	556	CS0_INACTIVE;
emh203	1:dc171f34db9b	557	read_ata(REG_ALTSTAT);
emh203	1:dc171f34db9b	558	read_ata(REG_STATUS);
emh203	1:dc171f34db9b	559
emh203	1:dc171f34db9b	560	return RES_OK;
emh203	1:dc171f34db9b	561	break;
emh203	1:dc171f34db9b	562
emh203	1:dc171f34db9b	563
emh203	1:dc171f34db9b	564	case USB:
emh203	1:dc171f34db9b	565
emh203	1:dc171f34db9b	566	if ( OK == MS_BulkRecv(sector, 1, (USB_INT08U *)buff) )
emh203	1:dc171f34db9b	567	return RES_OK;
emh203	1:dc171f34db9b	568	else
emh203	1:dc171f34db9b	569	return RES_NOTRDY;
emh203	1:dc171f34db9b	570	break;
emh203	1:dc171f34db9b	571
emh203	1:dc171f34db9b	572	case RAM:
emh203	1:dc171f34db9b	573	for(i=0;i<512;i++)
emh203	1:dc171f34db9b	574	{
emh203	1:dc171f34db9b	575	buff[i] = RAM_DISK[i];
emh203	1:dc171f34db9b	576	}
emh203	1:dc171f34db9b	577	return RES_OK;
emh203	1:dc171f34db9b	578	break;
emh203	1:dc171f34db9b	579
emh203	1:dc171f34db9b	580	default:
emh203	1:dc171f34db9b	581	return RES_PARERR;
emh203	1:dc171f34db9b	582	break;
emh203	1:dc171f34db9b	583	}
emh203	0:6b1e6c9e48ba	584	}
emh203	0:6b1e6c9e48ba	585
emh203	0:6b1e6c9e48ba	586
emh203	0:6b1e6c9e48ba	587	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	588	/* Write Sector(s) */
emh203	0:6b1e6c9e48ba	589	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	590
emh203	0:6b1e6c9e48ba	591	DRESULT disk_write (
emh203	0:6b1e6c9e48ba	592	BYTE drv, /* Physical drive number (0) */
emh203	0:6b1e6c9e48ba	593	const BYTE buff, / Data to be written */
emh203	0:6b1e6c9e48ba	594	DWORD sector, /* Sector number (LBA) */
emh203	0:6b1e6c9e48ba	595	BYTE count /* Sector count (1..255) */
emh203	0:6b1e6c9e48ba	596	)
emh203	0:6b1e6c9e48ba	597	{
emh203	0:6b1e6c9e48ba	598	BYTE s, c;
emh203	0:6b1e6c9e48ba	599	DWORD i;
emh203	1:dc171f34db9b	600	DRESULT RetVal;
emh203	0:6b1e6c9e48ba	601
emh203	1:dc171f34db9b	602	switch(drv)
emh203	1:dc171f34db9b	603	{
emh203	1:dc171f34db9b	604	case CF:
emh203	1:dc171f34db9b	605	/* Issue Write Setor(s) command */
emh203	1:dc171f34db9b	606	write_ata(REG_COUNT, count);
emh203	1:dc171f34db9b	607	write_ata(REG_SECTOR, (BYTE)sector);
emh203	1:dc171f34db9b	608	write_ata(REG_CYLL, (BYTE)(sector >> 8));
emh203	1:dc171f34db9b	609	write_ata(REG_CYLH, (BYTE)(sector >> 16));
emh203	1:dc171f34db9b	610	write_ata(REG_DEV, ((BYTE)(sector >> 24) & 0x0F) \| LBA);
emh203	1:dc171f34db9b	611	write_ata(REG_COMMAND, CMD_WRITE);
emh203	1:dc171f34db9b	612
emh203	1:dc171f34db9b	613	do {
emh203	1:dc171f34db9b	614	if (!wait_data()) return RES_ERROR;
emh203	1:dc171f34db9b	615
emh203	1:dc171f34db9b	616	SET_CF_ADDRESS(REG_DATA);
emh203	1:dc171f34db9b	617	__nop();
emh203	1:dc171f34db9b	618	__nop();
emh203	1:dc171f34db9b	619	__nop();
emh203	1:dc171f34db9b	620	CS0_ACTIVE;
emh203	1:dc171f34db9b	621	__nop();
emh203	1:dc171f34db9b	622	__nop();
emh203	1:dc171f34db9b	623	__nop();
emh203	1:dc171f34db9b	624
emh203	1:dc171f34db9b	625	SET_DATA_BUS_AS_OUTPUTS;
emh203	1:dc171f34db9b	626	c = 0;
emh203	1:dc171f34db9b	627	do {
emh203	1:dc171f34db9b	628	SET_CF_DATA(buff++); / Set even data */
emh203	1:dc171f34db9b	629	__nop();
emh203	1:dc171f34db9b	630	__nop();
emh203	1:dc171f34db9b	631	__nop();
emh203	1:dc171f34db9b	632
emh203	1:dc171f34db9b	633	IOWR_ACTIVE; /* IOWR = L */
emh203	1:dc171f34db9b	634	__nop();
emh203	1:dc171f34db9b	635	__nop();
emh203	1:dc171f34db9b	636	__nop();
emh203	1:dc171f34db9b	637
emh203	1:dc171f34db9b	638	IOWR_INACTIVE; /* IOWR = H */
emh203	1:dc171f34db9b	639	__nop();
emh203	1:dc171f34db9b	640	__nop();
emh203	1:dc171f34db9b	641	__nop();
emh203	1:dc171f34db9b	642
emh203	1:dc171f34db9b	643	SET_CF_DATA(buff++); / Set odd data */
emh203	1:dc171f34db9b	644	__nop();
emh203	1:dc171f34db9b	645	__nop();
emh203	1:dc171f34db9b	646	__nop();
emh203	1:dc171f34db9b	647
emh203	1:dc171f34db9b	648	IOWR_ACTIVE; /* IOWR = L */
emh203	1:dc171f34db9b	649	__nop();
emh203	1:dc171f34db9b	650	__nop();
emh203	1:dc171f34db9b	651	__nop();
emh203	1:dc171f34db9b	652
emh203	1:dc171f34db9b	653	IOWR_INACTIVE; /* IOWR = H */
emh203	1:dc171f34db9b	654	__nop();
emh203	1:dc171f34db9b	655	__nop();
emh203	1:dc171f34db9b	656	__nop();
emh203	1:dc171f34db9b	657	} while (--c);
emh203	1:dc171f34db9b	658
emh203	1:dc171f34db9b	659	} while (--count);
emh203	1:dc171f34db9b	660
emh203	1:dc171f34db9b	661	SET_DATA_BUS_AS_INPUTS;
emh203	1:dc171f34db9b	662	CS0_INACTIVE;
emh203	1:dc171f34db9b	663
emh203	1:dc171f34db9b	664	DiskProcTimer[CF] = 100;
emh203	1:dc171f34db9b	665	do {
emh203	1:dc171f34db9b	666	if (!DiskProcTimer[CF]) return RES_ERROR;
emh203	1:dc171f34db9b	667	s = read_ata(REG_STATUS);
emh203	1:dc171f34db9b	668	} while (s & BUSY);
emh203	1:dc171f34db9b	669	if (s & ERR) return RES_ERROR;
emh203	1:dc171f34db9b	670
emh203	1:dc171f34db9b	671	read_ata(REG_ALTSTAT);
emh203	1:dc171f34db9b	672	read_ata(REG_STATUS);
emh203	0:6b1e6c9e48ba	673
emh203	1:dc171f34db9b	674	RetVal = RES_OK;
emh203	1:dc171f34db9b	675	break;
emh203	1:dc171f34db9b	676
emh203	1:dc171f34db9b	677
emh203	1:dc171f34db9b	678	case USB:
emh203	1:dc171f34db9b	679	if ( OK == MS_BulkSend(sector, 1, (USB_INT08U *)buff) )
emh203	1:dc171f34db9b	680	RetVal = RES_OK;
emh203	1:dc171f34db9b	681	else;
emh203	1:dc171f34db9b	682	RetVal = RES_NOTRDY;
emh203	1:dc171f34db9b	683	break;
emh203	1:dc171f34db9b	684
emh203	1:dc171f34db9b	685	case RAM:
emh203	1:dc171f34db9b	686
emh203	1:dc171f34db9b	687	for(i=0;i<512;i++)
emh203	1:dc171f34db9b	688	{
emh203	1:dc171f34db9b	689	RAM_DISK[i] = buff[i];
emh203	1:dc171f34db9b	690	}
emh203	1:dc171f34db9b	691	RetVal = RES_OK;
emh203	1:dc171f34db9b	692
emh203	1:dc171f34db9b	693	break;
emh203	1:dc171f34db9b	694
emh203	1:dc171f34db9b	695	default:
emh203	1:dc171f34db9b	696	RetVal = RES_PARERR;
emh203	1:dc171f34db9b	697	break;
emh203	1:dc171f34db9b	698
emh203	1:dc171f34db9b	699	return RetVal;
emh203	1:dc171f34db9b	700	}
emh203	0:6b1e6c9e48ba	701
emh203	1:dc171f34db9b	702	}
emh203	0:6b1e6c9e48ba	703
emh203	1:dc171f34db9b	704
emh203	1:dc171f34db9b	705
emh203	0:6b1e6c9e48ba	706
emh203	0:6b1e6c9e48ba	707	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	708	/* Miscellaneous Functions */
emh203	0:6b1e6c9e48ba	709	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	710
emh203	0:6b1e6c9e48ba	711	DRESULT disk_ioctl (
emh203	0:6b1e6c9e48ba	712	BYTE drv, /* Physical drive nmuber (0) */
emh203	0:6b1e6c9e48ba	713	BYTE ctrl, /* Control code */
emh203	0:6b1e6c9e48ba	714	void buff / Buffer to send/receive data block */
emh203	0:6b1e6c9e48ba	715	)
emh203	0:6b1e6c9e48ba	716	{
emh203	0:6b1e6c9e48ba	717	BYTE n, w, ofs, dl, dh, ptr = (BYTE )buff;
emh203	1:dc171f34db9b	718	USB_INT32S rc;
emh203	1:dc171f34db9b	719
emh203	1:dc171f34db9b	720	switch(drv)
emh203	1:dc171f34db9b	721	{
emh203	1:dc171f34db9b	722	case CF:
emh203	1:dc171f34db9b	723	switch (ctrl)
emh203	1:dc171f34db9b	724	{
emh203	1:dc171f34db9b	725	case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
emh203	1:dc171f34db9b	726	ofs = 60; w = 2; n = 0;
emh203	1:dc171f34db9b	727	break;
emh203	1:dc171f34db9b	728
emh203	1:dc171f34db9b	729	case GET_BLOCK_SIZE : /* Get erase block size in sectors (DWORD) */
emh203	1:dc171f34db9b	730	(DWORD)buff = 32;
emh203	1:dc171f34db9b	731	return RES_OK;
emh203	1:dc171f34db9b	732	break;
emh203	1:dc171f34db9b	733	case CTRL_SYNC : /* Nothing to do */
emh203	1:dc171f34db9b	734	return RES_OK;
emh203	1:dc171f34db9b	735	break;
emh203	1:dc171f34db9b	736	case ATA_GET_REV : /* Get firmware revision (8 chars) */
emh203	1:dc171f34db9b	737	ofs = 23; w = 4; n = 4;
emh203	1:dc171f34db9b	738	break;
emh203	1:dc171f34db9b	739
emh203	1:dc171f34db9b	740	case ATA_GET_MODEL : /* Get model name (40 chars) */
emh203	1:dc171f34db9b	741	ofs = 27; w = 20; n = 20;
emh203	1:dc171f34db9b	742	break;
emh203	1:dc171f34db9b	743
emh203	1:dc171f34db9b	744	case ATA_GET_SN : /* Get serial number (20 chars) */
emh203	1:dc171f34db9b	745	ofs = 10; w = 10; n = 10;
emh203	1:dc171f34db9b	746	break;
emh203	1:dc171f34db9b	747
emh203	1:dc171f34db9b	748	default:
emh203	1:dc171f34db9b	749	return RES_PARERR;
emh203	1:dc171f34db9b	750	}
emh203	1:dc171f34db9b	751
emh203	1:dc171f34db9b	752	write_ata(REG_COMMAND, CMD_IDENTIFY);
emh203	1:dc171f34db9b	753
emh203	1:dc171f34db9b	754	if (!wait_data()) return RES_ERROR;
emh203	1:dc171f34db9b	755
emh203	1:dc171f34db9b	756	read_part(ptr, ofs, w);
emh203	1:dc171f34db9b	757
emh203	1:dc171f34db9b	758	while (n--)
emh203	1:dc171f34db9b	759	{
emh203	1:dc171f34db9b	760	dl = ptr; dh = (ptr+1);
emh203	1:dc171f34db9b	761	ptr++ = dh; ptr++ = dl;
emh203	1:dc171f34db9b	762	}
emh203	1:dc171f34db9b	763
emh203	1:dc171f34db9b	764	return RES_OK;
emh203	1:dc171f34db9b	765	break;
emh203	1:dc171f34db9b	766
emh203	1:dc171f34db9b	767
emh203	1:dc171f34db9b	768	case USB:
emh203	1:dc171f34db9b	769	rc = MS_Init( &_blkSize, &_numBlks, inquiryResult );
emh203	1:dc171f34db9b	770
emh203	1:dc171f34db9b	771	if (rc != OK)
emh203	1:dc171f34db9b	772	{
emh203	1:dc171f34db9b	773	TERMINAL_PRINTF("Could not get data from USB Inquiry: %d\r\n", rc);
emh203	1:dc171f34db9b	774	return RES_ERROR;
emh203	1:dc171f34db9b	775	}
emh203	1:dc171f34db9b	776	else
emh203	1:dc171f34db9b	777	{
emh203	1:dc171f34db9b	778	Stat[USB] &= ~STA_NOINIT;
emh203	1:dc171f34db9b	779	switch (ctrl)
emh203	1:dc171f34db9b	780	{
emh203	1:dc171f34db9b	781	case GET_SECTOR_COUNT :
emh203	1:dc171f34db9b	782	(DWORD )(buff) =_numBlks;
emh203	1:dc171f34db9b	783	break;
emh203	1:dc171f34db9b	784
emh203	1:dc171f34db9b	785	case GET_BLOCK_SIZE :
emh203	1:dc171f34db9b	786	(DWORD )(buff) = _blkSize;
emh203	1:dc171f34db9b	787	return RES_OK;
emh203	1:dc171f34db9b	788	break;
emh203	1:dc171f34db9b	789	case CTRL_SYNC :
emh203	1:dc171f34db9b	790	return RES_OK;
emh203	1:dc171f34db9b	791	break;
emh203	1:dc171f34db9b	792	case ATA_GET_REV :
emh203	1:dc171f34db9b	793	memcpy ((CHAR )buff,(const char )&inquiryResult[32],8);
emh203	1:dc171f34db9b	794	return RES_OK;
emh203	1:dc171f34db9b	795	break;
emh203	1:dc171f34db9b	796
emh203	1:dc171f34db9b	797	case ATA_GET_MODEL :
emh203	1:dc171f34db9b	798	memcpy ((CHAR )buff, (const char )&inquiryResult[8],8);
emh203	1:dc171f34db9b	799	return RES_OK;
emh203	1:dc171f34db9b	800	break;
emh203	1:dc171f34db9b	801
emh203	1:dc171f34db9b	802	case ATA_GET_SN :
emh203	1:dc171f34db9b	803	memcpy ((CHAR )buff,(const char )&inquiryResult[16],8);
emh203	1:dc171f34db9b	804	return RES_OK;
emh203	1:dc171f34db9b	805	break;
emh203	1:dc171f34db9b	806
emh203	1:dc171f34db9b	807	default:
emh203	1:dc171f34db9b	808	return RES_PARERR;
emh203	1:dc171f34db9b	809	}
emh203	1:dc171f34db9b	810	}
emh203	1:dc171f34db9b	811
emh203	1:dc171f34db9b	812	break;
emh203	1:dc171f34db9b	813
emh203	1:dc171f34db9b	814	case RAM:
emh203	1:dc171f34db9b	815	switch (ctrl)
emh203	1:dc171f34db9b	816	{
emh203	1:dc171f34db9b	817	case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
emh203	1:dc171f34db9b	818	(DWORD )(buff) = 1;
emh203	1:dc171f34db9b	819	break;
emh203	1:dc171f34db9b	820
emh203	1:dc171f34db9b	821	case GET_BLOCK_SIZE : /* Get erase block size in sectors (DWORD) */
emh203	1:dc171f34db9b	822	(DWORD )(buff) = 1;
emh203	1:dc171f34db9b	823	return RES_OK;
emh203	1:dc171f34db9b	824	break;
emh203	1:dc171f34db9b	825	case CTRL_SYNC : /* Nothing to do */
emh203	1:dc171f34db9b	826	return RES_OK;
emh203	1:dc171f34db9b	827	break;
emh203	1:dc171f34db9b	828	case ATA_GET_REV : /* Get firmware revision (8 chars) */
emh203	1:dc171f34db9b	829	strcpy ((CHAR *)buff,"Rev 0.01");
emh203	1:dc171f34db9b	830	break;
emh203	1:dc171f34db9b	831
emh203	1:dc171f34db9b	832	case ATA_GET_MODEL : /* Get model name (40 chars) */
emh203	1:dc171f34db9b	833	strcpy ((CHAR *)buff,"Wavenumber RAM Drive");
emh203	1:dc171f34db9b	834	break;
emh203	1:dc171f34db9b	835
emh203	1:dc171f34db9b	836	case ATA_GET_SN : /* Get serial number (20 chars) */
emh203	1:dc171f34db9b	837	strcpy ((CHAR *)buff,"12345");
emh203	1:dc171f34db9b	838	break;
emh203	1:dc171f34db9b	839	default:
emh203	1:dc171f34db9b	840	return RES_PARERR;
emh203	1:dc171f34db9b	841	}
emh203	1:dc171f34db9b	842	return RES_OK;
emh203	1:dc171f34db9b	843	break;
emh203	1:dc171f34db9b	844
emh203	0:6b1e6c9e48ba	845	default:
emh203	1:dc171f34db9b	846	return RES_PARERR;
emh203	1:dc171f34db9b	847	break;
emh203	0:6b1e6c9e48ba	848	}
emh203	0:6b1e6c9e48ba	849
emh203	0:6b1e6c9e48ba	850	return RES_OK;
emh203	0:6b1e6c9e48ba	851	}
emh203	0:6b1e6c9e48ba	852
emh203	0:6b1e6c9e48ba	853
emh203	0:6b1e6c9e48ba	854	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	855	/* Device timer interrupt procedure */
emh203	0:6b1e6c9e48ba	856	/-----------------------------------------------------------------------/
emh203	0:6b1e6c9e48ba	857	/* This function must be called in period of 10ms */
emh203	0:6b1e6c9e48ba	858
emh203	0:6b1e6c9e48ba	859	void disk_timerproc (void)
emh203	0:6b1e6c9e48ba	860	{
emh203	0:6b1e6c9e48ba	861	static BYTE pv;
emh203	0:6b1e6c9e48ba	862	BYTE n;
emh203	1:dc171f34db9b	863
emh203	1:dc171f34db9b	864	n = DiskProcTimer[CF]; /* 100Hz decrement timer */
emh203	1:dc171f34db9b	865	if (n) DiskProcTimer[CF] = --n;
emh203	0:6b1e6c9e48ba	866
emh203	1:dc171f34db9b	867	n = DiskProcTimer[USB]; /* 100Hz decrement timer */
emh203	1:dc171f34db9b	868	if (n) DiskProcTimer[USB] = --n;
emh203	1:dc171f34db9b	869
emh203	1:dc171f34db9b	870	n = DiskProcTimer[RAM]; /* 100Hz decrement timer */
emh203	1:dc171f34db9b	871	if (n) DiskProcTimer[RAM] = --n;
emh203	0:6b1e6c9e48ba	872
emh203	0:6b1e6c9e48ba	873	n = pv;
emh203	0:6b1e6c9e48ba	874	pv = COMPACT_FLASH_CARD_DETECTED ; /* Sapmle socket switch */
emh203	0:6b1e6c9e48ba	875
emh203	1:dc171f34db9b	876
emh203	1:dc171f34db9b	877	//Check Compact Flash Card Detect
emh203	0:6b1e6c9e48ba	878	if (n == pv) { /* Have contacts stabled? */
emh203	0:6b1e6c9e48ba	879	if (!COMPACT_FLASH_CARD_DETECTED )
emh203	0:6b1e6c9e48ba	880	{ /* CD1 or CD2 is high (Socket empty) */
emh203	1:dc171f34db9b	881	Stat[CF] \|= (STA_NODISK \| STA_NOINIT);
emh203	0:6b1e6c9e48ba	882	SET_DATA_BUS_TO_INPUTS; /* Float D0-D7 */
emh203	0:6b1e6c9e48ba	883	COMPACT_FLASH_RESET_ACTIVE; /* Assert RESET# */
emh203	0:6b1e6c9e48ba	884	COMPACT_FLASH_POWER_DISABLE; /* Power OFF */
emh203	0:6b1e6c9e48ba	885	LED1_OFF;
emh203	1:dc171f34db9b	886	}
emh203	1:dc171f34db9b	887	else
emh203	1:dc171f34db9b	888	{ /* CD1 and CD2 are low (Card inserted) */
emh203	1:dc171f34db9b	889	Stat[CF] &= ~STA_NODISK;
emh203	0:6b1e6c9e48ba	890	LED1_ON;
emh203	0:6b1e6c9e48ba	891	}
emh203	0:6b1e6c9e48ba	892	}
emh203	1:dc171f34db9b	893
emh203	1:dc171f34db9b	894	//Check to see if a USB drive is connected
emh203	1:dc171f34db9b	895	if(HOST_RhscIntr>0)
emh203	1:dc171f34db9b	896	LED2_ON;
emh203	1:dc171f34db9b	897	else
emh203	1:dc171f34db9b	898	LED2_OFF;
emh203	1:dc171f34db9b	899
emh203	0:6b1e6c9e48ba	900	}
emh203	0:6b1e6c9e48ba	901
emh203	0:6b1e6c9e48ba	902
emh203	0:6b1e6c9e48ba	903	DWORD get_fattime(void)
emh203	0:6b1e6c9e48ba	904	{
emh203	0:6b1e6c9e48ba	905	time_t CurrentTimeStamp;
emh203	0:6b1e6c9e48ba	906	tm *CurrentLocalTime;
emh203	0:6b1e6c9e48ba	907	DWORD FATFSTimeCode;
emh203	0:6b1e6c9e48ba	908
emh203	0:6b1e6c9e48ba	909	CurrentTimeStamp = time(NULL);
emh203	0:6b1e6c9e48ba	910	CurrentLocalTime = localtime(&CurrentTimeStamp);
emh203	0:6b1e6c9e48ba	911
emh203	0:6b1e6c9e48ba	912	//Map the tm struct time into the FatFs time code
emh203	0:6b1e6c9e48ba	913	FATFSTimeCode = ((CurrentLocalTime->tm_year-80)<<25) \|
emh203	0:6b1e6c9e48ba	914	((CurrentLocalTime->tm_mon+1)<<21) \|
emh203	0:6b1e6c9e48ba	915	((CurrentLocalTime->tm_mday)<<16) \|
emh203	0:6b1e6c9e48ba	916	((CurrentLocalTime->tm_hour)<<11) \|
emh203	0:6b1e6c9e48ba	917	((CurrentLocalTime->tm_min)<<5) \|
emh203	0:6b1e6c9e48ba	918	((CurrentLocalTime->tm_sec));
emh203	0:6b1e6c9e48ba	919
emh203	0:6b1e6c9e48ba	920	return FATFSTimeCode;
emh203	0:6b1e6c9e48ba	921	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	27 Dec 2011
Imports:	3
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	2
Followers:	1

FAT_FS/diskio.c@1:dc171f34db9b, 2011-12-30 (annotated)

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